arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599 };
 600
 601 enum segment_cache_field {
 602         SEG_FIELD_SEL = 0,
 603         SEG_FIELD_BASE = 1,
 604         SEG_FIELD_LIMIT = 2,
 605         SEG_FIELD_AR = 3,
 606
 607         SEG_FIELD_NR = 4
 608 };
 609
 610 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 611 {
 612         return container_of(vcpu, struct vcpu_vmx, vcpu);
 613 }
 614
 615 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 616 {
 617         return &(to_vmx(vcpu)->pi_desc);
 618 }
 619
 620 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 621 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 622 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 623                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 624
 625
 626 static unsigned long shadow_read_only_fields[] = {
 627         /*
 628          * We do NOT shadow fields that are modified when L0
 629          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 630          * VMXON...) executed by L1.
 631          * For example, VM_INSTRUCTION_ERROR is read
 632          * by L1 if a vmx instruction fails (part of the error path).
 633          * Note the code assumes this logic. If for some reason
 634          * we start shadowing these fields then we need to
 635          * force a shadow sync when L0 emulates vmx instructions
 636          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 637          * by nested_vmx_failValid)
 638          */
 639         VM_EXIT_REASON,
 640         VM_EXIT_INTR_INFO,
 641         VM_EXIT_INSTRUCTION_LEN,
 642         IDT_VECTORING_INFO_FIELD,
 643         IDT_VECTORING_ERROR_CODE,
 644         VM_EXIT_INTR_ERROR_CODE,
 645         EXIT_QUALIFICATION,
 646         GUEST_LINEAR_ADDRESS,
 647         GUEST_PHYSICAL_ADDRESS
 648 };
 649 static int max_shadow_read_only_fields =
 650         ARRAY_SIZE(shadow_read_only_fields);
 651
 652 static unsigned long shadow_read_write_fields[] = {
 653         TPR_THRESHOLD,
 654         GUEST_RIP,
 655         GUEST_RSP,
 656         GUEST_CR0,
 657         GUEST_CR3,
 658         GUEST_CR4,
 659         GUEST_INTERRUPTIBILITY_INFO,
 660         GUEST_RFLAGS,
 661         GUEST_CS_SELECTOR,
 662         GUEST_CS_AR_BYTES,
 663         GUEST_CS_LIMIT,
 664         GUEST_CS_BASE,
 665         GUEST_ES_BASE,
 666         GUEST_BNDCFGS,
 667         CR0_GUEST_HOST_MASK,
 668         CR0_READ_SHADOW,
 669         CR4_READ_SHADOW,
 670         TSC_OFFSET,
 671         EXCEPTION_BITMAP,
 672         CPU_BASED_VM_EXEC_CONTROL,
 673         VM_ENTRY_EXCEPTION_ERROR_CODE,
 674         VM_ENTRY_INTR_INFO_FIELD,
 675         VM_ENTRY_INSTRUCTION_LEN,
 676         VM_ENTRY_EXCEPTION_ERROR_CODE,
 677         HOST_FS_BASE,
 678         HOST_GS_BASE,
 679         HOST_FS_SELECTOR,
 680         HOST_GS_SELECTOR
 681 };
 682 static int max_shadow_read_write_fields =
 683         ARRAY_SIZE(shadow_read_write_fields);
 684
 685 static const unsigned short vmcs_field_to_offset_table[] = {
 686         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 687         FIELD(POSTED_INTR_NV, posted_intr_nv),
 688         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 689         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 690         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 691         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 692         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 693         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 694         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 695         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 696         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 697         FIELD(HOST_ES_SELECTOR, host_es_selector),
 698         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 699         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 700         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 701         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 702         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 703         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 704         FIELD64(IO_BITMAP_A, io_bitmap_a),
 705         FIELD64(IO_BITMAP_B, io_bitmap_b),
 706         FIELD64(MSR_BITMAP, msr_bitmap),
 707         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 708         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 709         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 710         FIELD64(TSC_OFFSET, tsc_offset),
 711         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 712         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 713         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 714         FIELD64(EPT_POINTER, ept_pointer),
 715         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 716         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 717         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 718         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 719         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 720         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 721         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 722         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 723         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 724         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 725         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 726         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 727         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 728         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 729         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 730         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 731         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 732         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 733         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 734         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 735         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 736         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 737         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 738         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 739         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 740         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 741         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 742         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 743         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 744         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 745         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 746         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 747         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 748         FIELD(TPR_THRESHOLD, tpr_threshold),
 749         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 750         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 751         FIELD(VM_EXIT_REASON, vm_exit_reason),
 752         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 753         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 754         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 755         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 756         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 757         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 758         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 759         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 760         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 761         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 762         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 763         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 764         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 765         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 766         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 767         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 768         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 769         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 770         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 771         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 772         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 773         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 774         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 775         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 776         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 777         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 778         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 779         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 780         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 781         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 782         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 783         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 784         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 785         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 786         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 787         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 788         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 789         FIELD(EXIT_QUALIFICATION, exit_qualification),
 790         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 791         FIELD(GUEST_CR0, guest_cr0),
 792         FIELD(GUEST_CR3, guest_cr3),
 793         FIELD(GUEST_CR4, guest_cr4),
 794         FIELD(GUEST_ES_BASE, guest_es_base),
 795         FIELD(GUEST_CS_BASE, guest_cs_base),
 796         FIELD(GUEST_SS_BASE, guest_ss_base),
 797         FIELD(GUEST_DS_BASE, guest_ds_base),
 798         FIELD(GUEST_FS_BASE, guest_fs_base),
 799         FIELD(GUEST_GS_BASE, guest_gs_base),
 800         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 801         FIELD(GUEST_TR_BASE, guest_tr_base),
 802         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 803         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 804         FIELD(GUEST_DR7, guest_dr7),
 805         FIELD(GUEST_RSP, guest_rsp),
 806         FIELD(GUEST_RIP, guest_rip),
 807         FIELD(GUEST_RFLAGS, guest_rflags),
 808         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 809         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 810         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 811         FIELD(HOST_CR0, host_cr0),
 812         FIELD(HOST_CR3, host_cr3),
 813         FIELD(HOST_CR4, host_cr4),
 814         FIELD(HOST_FS_BASE, host_fs_base),
 815         FIELD(HOST_GS_BASE, host_gs_base),
 816         FIELD(HOST_TR_BASE, host_tr_base),
 817         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 818         FIELD(HOST_IDTR_BASE, host_idtr_base),
 819         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 820         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 821         FIELD(HOST_RSP, host_rsp),
 822         FIELD(HOST_RIP, host_rip),
 823 };
 824
 825 static inline short vmcs_field_to_offset(unsigned long field)
 826 {
 827         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 828
 829         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 830             vmcs_field_to_offset_table[field] == 0)
 831                 return -ENOENT;
 832
 833         return vmcs_field_to_offset_table[field];
 834 }
 835
 836 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 837 {
 838         return to_vmx(vcpu)->nested.current_vmcs12;
 839 }
 840
 841 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 842 {
 843         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 844         if (is_error_page(page))
 845                 return NULL;
 846
 847         return page;
 848 }
 849
 850 static void nested_release_page(struct page *page)
 851 {
 852         kvm_release_page_dirty(page);
 853 }
 854
 855 static void nested_release_page_clean(struct page *page)
 856 {
 857         kvm_release_page_clean(page);
 858 }
 859
 860 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 861 static u64 construct_eptp(unsigned long root_hpa);
 862 static void kvm_cpu_vmxon(u64 addr);
 863 static void kvm_cpu_vmxoff(void);
 864 static bool vmx_mpx_supported(void);
 865 static bool vmx_xsaves_supported(void);
 866 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 867 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 868                             struct kvm_segment *var, int seg);
 869 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 872 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 873 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 874 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 875 static int alloc_identity_pagetable(struct kvm *kvm);
 876
 877 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 878 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 879 /*
 880  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 881  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 882  */
 883 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 884 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 885
 886 /*
 887  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 888  * can find which vCPU should be waken up.
 889  */
 890 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 891 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 892
 893 static unsigned long *vmx_io_bitmap_a;
 894 static unsigned long *vmx_io_bitmap_b;
 895 static unsigned long *vmx_msr_bitmap_legacy;
 896 static unsigned long *vmx_msr_bitmap_longmode;
 897 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 898 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 899 static unsigned long *vmx_msr_bitmap_nested;
 900 static unsigned long *vmx_vmread_bitmap;
 901 static unsigned long *vmx_vmwrite_bitmap;
 902
 903 static bool cpu_has_load_ia32_efer;
 904 static bool cpu_has_load_perf_global_ctrl;
 905
 906 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 907 static DEFINE_SPINLOCK(vmx_vpid_lock);
 908
 909 static struct vmcs_config {
 910         int size;
 911         int order;
 912         u32 revision_id;
 913         u32 pin_based_exec_ctrl;
 914         u32 cpu_based_exec_ctrl;
 915         u32 cpu_based_2nd_exec_ctrl;
 916         u32 vmexit_ctrl;
 917         u32 vmentry_ctrl;
 918 } vmcs_config;
 919
 920 static struct vmx_capability {
 921         u32 ept;
 922         u32 vpid;
 923 } vmx_capability;
 924
 925 #define VMX_SEGMENT_FIELD(seg)                                  \
 926         [VCPU_SREG_##seg] = {                                   \
 927                 .selector = GUEST_##seg##_SELECTOR,             \
 928                 .base = GUEST_##seg##_BASE,                     \
 929                 .limit = GUEST_##seg##_LIMIT,                   \
 930                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 931         }
 932
 933 static const struct kvm_vmx_segment_field {
 934         unsigned selector;
 935         unsigned base;
 936         unsigned limit;
 937         unsigned ar_bytes;
 938 } kvm_vmx_segment_fields[] = {
 939         VMX_SEGMENT_FIELD(CS),
 940         VMX_SEGMENT_FIELD(DS),
 941         VMX_SEGMENT_FIELD(ES),
 942         VMX_SEGMENT_FIELD(FS),
 943         VMX_SEGMENT_FIELD(GS),
 944         VMX_SEGMENT_FIELD(SS),
 945         VMX_SEGMENT_FIELD(TR),
 946         VMX_SEGMENT_FIELD(LDTR),
 947 };
 948
 949 static u64 host_efer;
 950
 951 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 952
 953 /*
 954  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 955  * away by decrementing the array size.
 956  */
 957 static const u32 vmx_msr_index[] = {
 958 #ifdef CONFIG_X86_64
 959         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 960 #endif
 961         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 962 };
 963
 964 static inline bool is_exception_n(u32 intr_info, u8 vector)
 965 {
 966         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 967                              INTR_INFO_VALID_MASK)) ==
 968                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 969 }
 970
 971 static inline bool is_debug(u32 intr_info)
 972 {
 973         return is_exception_n(intr_info, DB_VECTOR);
 974 }
 975
 976 static inline bool is_breakpoint(u32 intr_info)
 977 {
 978         return is_exception_n(intr_info, BP_VECTOR);
 979 }
 980
 981 static inline bool is_page_fault(u32 intr_info)
 982 {
 983         return is_exception_n(intr_info, PF_VECTOR);
 984 }
 985
 986 static inline bool is_no_device(u32 intr_info)
 987 {
 988         return is_exception_n(intr_info, NM_VECTOR);
 989 }
 990
 991 static inline bool is_invalid_opcode(u32 intr_info)
 992 {
 993         return is_exception_n(intr_info, UD_VECTOR);
 994 }
 995
 996 static inline bool is_external_interrupt(u32 intr_info)
 997 {
 998         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 999                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1000 }
1001
1002 static inline bool is_machine_check(u32 intr_info)
1003 {
1004         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1005                              INTR_INFO_VALID_MASK)) ==
1006                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1007 }
1008
1009 static inline bool cpu_has_vmx_msr_bitmap(void)
1010 {
1011         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1012 }
1013
1014 static inline bool cpu_has_vmx_tpr_shadow(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1017 }
1018
1019 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1020 {
1021         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1022 }
1023
1024 static inline bool cpu_has_secondary_exec_ctrls(void)
1025 {
1026         return vmcs_config.cpu_based_exec_ctrl &
1027                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1028 }
1029
1030 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1031 {
1032         return vmcs_config.cpu_based_2nd_exec_ctrl &
1033                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1034 }
1035
1036 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1037 {
1038         return vmcs_config.cpu_based_2nd_exec_ctrl &
1039                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1040 }
1041
1042 static inline bool cpu_has_vmx_apic_register_virt(void)
1043 {
1044         return vmcs_config.cpu_based_2nd_exec_ctrl &
1045                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1046 }
1047
1048 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1049 {
1050         return vmcs_config.cpu_based_2nd_exec_ctrl &
1051                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1052 }
1053
1054 static inline bool cpu_has_vmx_posted_intr(void)
1055 {
1056         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1057                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1058 }
1059
1060 static inline bool cpu_has_vmx_apicv(void)
1061 {
1062         return cpu_has_vmx_apic_register_virt() &&
1063                 cpu_has_vmx_virtual_intr_delivery() &&
1064                 cpu_has_vmx_posted_intr();
1065 }
1066
1067 static inline bool cpu_has_vmx_flexpriority(void)
1068 {
1069         return cpu_has_vmx_tpr_shadow() &&
1070                 cpu_has_vmx_virtualize_apic_accesses();
1071 }
1072
1073 static inline bool cpu_has_vmx_ept_execute_only(void)
1074 {
1075         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_2m_page(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_1g_page(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_ept_4levels(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_ept_ad_bits(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_AD_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_invept_context(void)
1099 {
1100         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invept_global(void)
1104 {
1105         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_invvpid_single(void)
1109 {
1110         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1111 }
1112
1113 static inline bool cpu_has_vmx_invvpid_global(void)
1114 {
1115         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1116 }
1117
1118 static inline bool cpu_has_vmx_ept(void)
1119 {
1120         return vmcs_config.cpu_based_2nd_exec_ctrl &
1121                 SECONDARY_EXEC_ENABLE_EPT;
1122 }
1123
1124 static inline bool cpu_has_vmx_unrestricted_guest(void)
1125 {
1126         return vmcs_config.cpu_based_2nd_exec_ctrl &
1127                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1128 }
1129
1130 static inline bool cpu_has_vmx_ple(void)
1131 {
1132         return vmcs_config.cpu_based_2nd_exec_ctrl &
1133                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1134 }
1135
1136 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1137 {
1138         return flexpriority_enabled && lapic_in_kernel(vcpu);
1139 }
1140
1141 static inline bool cpu_has_vmx_vpid(void)
1142 {
1143         return vmcs_config.cpu_based_2nd_exec_ctrl &
1144                 SECONDARY_EXEC_ENABLE_VPID;
1145 }
1146
1147 static inline bool cpu_has_vmx_rdtscp(void)
1148 {
1149         return vmcs_config.cpu_based_2nd_exec_ctrl &
1150                 SECONDARY_EXEC_RDTSCP;
1151 }
1152
1153 static inline bool cpu_has_vmx_invpcid(void)
1154 {
1155         return vmcs_config.cpu_based_2nd_exec_ctrl &
1156                 SECONDARY_EXEC_ENABLE_INVPCID;
1157 }
1158
1159 static inline bool cpu_has_virtual_nmis(void)
1160 {
1161         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1162 }
1163
1164 static inline bool cpu_has_vmx_wbinvd_exit(void)
1165 {
1166         return vmcs_config.cpu_based_2nd_exec_ctrl &
1167                 SECONDARY_EXEC_WBINVD_EXITING;
1168 }
1169
1170 static inline bool cpu_has_vmx_shadow_vmcs(void)
1171 {
1172         u64 vmx_msr;
1173         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1174         /* check if the cpu supports writing r/o exit information fields */
1175         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1176                 return false;
1177
1178         return vmcs_config.cpu_based_2nd_exec_ctrl &
1179                 SECONDARY_EXEC_SHADOW_VMCS;
1180 }
1181
1182 static inline bool cpu_has_vmx_pml(void)
1183 {
1184         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1185 }
1186
1187 static inline bool cpu_has_vmx_tsc_scaling(void)
1188 {
1189         return vmcs_config.cpu_based_2nd_exec_ctrl &
1190                 SECONDARY_EXEC_TSC_SCALING;
1191 }
1192
1193 static inline bool report_flexpriority(void)
1194 {
1195         return flexpriority_enabled;
1196 }
1197
1198 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1199 {
1200         return vmcs12->cpu_based_vm_exec_control & bit;
1201 }
1202
1203 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205         return (vmcs12->cpu_based_vm_exec_control &
1206                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1207                 (vmcs12->secondary_vm_exec_control & bit);
1208 }
1209
1210 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1211 {
1212         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1213 }
1214
1215 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1216 {
1217         return vmcs12->pin_based_vm_exec_control &
1218                 PIN_BASED_VMX_PREEMPTION_TIMER;
1219 }
1220
1221 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1222 {
1223         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1224 }
1225
1226 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1229                 vmx_xsaves_supported();
1230 }
1231
1232 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1233 {
1234         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1235 }
1236
1237 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1240 }
1241
1242 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1243 {
1244         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1245 }
1246
1247 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1248 {
1249         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1250 }
1251
1252 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1253 {
1254         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1255 }
1256
1257 static inline bool is_exception(u32 intr_info)
1258 {
1259         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1260                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1261 }
1262
1263 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1264                               u32 exit_intr_info,
1265                               unsigned long exit_qualification);
1266 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1267                         struct vmcs12 *vmcs12,
1268                         u32 reason, unsigned long qualification);
1269
1270 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1271 {
1272         int i;
1273
1274         for (i = 0; i < vmx->nmsrs; ++i)
1275                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1276                         return i;
1277         return -1;
1278 }
1279
1280 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1281 {
1282     struct {
1283         u64 vpid : 16;
1284         u64 rsvd : 48;
1285         u64 gva;
1286     } operand = { vpid, 0, gva };
1287
1288     asm volatile (__ex(ASM_VMX_INVVPID)
1289                   /* CF==1 or ZF==1 --> rc = -1 */
1290                   "; ja 1f ; ud2 ; 1:"
1291                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1292 }
1293
1294 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1295 {
1296         struct {
1297                 u64 eptp, gpa;
1298         } operand = {eptp, gpa};
1299
1300         asm volatile (__ex(ASM_VMX_INVEPT)
1301                         /* CF==1 or ZF==1 --> rc = -1 */
1302                         "; ja 1f ; ud2 ; 1:\n"
1303                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1304 }
1305
1306 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1307 {
1308         int i;
1309
1310         i = __find_msr_index(vmx, msr);
1311         if (i >= 0)
1312                 return &vmx->guest_msrs[i];
1313         return NULL;
1314 }
1315
1316 static void vmcs_clear(struct vmcs *vmcs)
1317 {
1318         u64 phys_addr = __pa(vmcs);
1319         u8 error;
1320
1321         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1322                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1323                       : "cc", "memory");
1324         if (error)
1325                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1326                        vmcs, phys_addr);
1327 }
1328
1329 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1330 {
1331         vmcs_clear(loaded_vmcs->vmcs);
1332         loaded_vmcs->cpu = -1;
1333         loaded_vmcs->launched = 0;
1334 }
1335
1336 static void vmcs_load(struct vmcs *vmcs)
1337 {
1338         u64 phys_addr = __pa(vmcs);
1339         u8 error;
1340
1341         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1342                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1343                         : "cc", "memory");
1344         if (error)
1345                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1346                        vmcs, phys_addr);
1347 }
1348
1349 #ifdef CONFIG_KEXEC_CORE
1350 /*
1351  * This bitmap is used to indicate whether the vmclear
1352  * operation is enabled on all cpus. All disabled by
1353  * default.
1354  */
1355 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1356
1357 static inline void crash_enable_local_vmclear(int cpu)
1358 {
1359         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1360 }
1361
1362 static inline void crash_disable_local_vmclear(int cpu)
1363 {
1364         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366
1367 static inline int crash_local_vmclear_enabled(int cpu)
1368 {
1369         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371
1372 static void crash_vmclear_local_loaded_vmcss(void)
1373 {
1374         int cpu = raw_smp_processor_id();
1375         struct loaded_vmcs *v;
1376
1377         if (!crash_local_vmclear_enabled(cpu))
1378                 return;
1379
1380         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1381                             loaded_vmcss_on_cpu_link)
1382                 vmcs_clear(v->vmcs);
1383 }
1384 #else
1385 static inline void crash_enable_local_vmclear(int cpu) { }
1386 static inline void crash_disable_local_vmclear(int cpu) { }
1387 #endif /* CONFIG_KEXEC_CORE */
1388
1389 static void __loaded_vmcs_clear(void *arg)
1390 {
1391         struct loaded_vmcs *loaded_vmcs = arg;
1392         int cpu = raw_smp_processor_id();
1393
1394         if (loaded_vmcs->cpu != cpu)
1395                 return; /* vcpu migration can race with cpu offline */
1396         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1397                 per_cpu(current_vmcs, cpu) = NULL;
1398         crash_disable_local_vmclear(cpu);
1399         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1400
1401         /*
1402          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1403          * is before setting loaded_vmcs->vcpu to -1 which is done in
1404          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1405          * then adds the vmcs into percpu list before it is deleted.
1406          */
1407         smp_wmb();
1408
1409         loaded_vmcs_init(loaded_vmcs);
1410         crash_enable_local_vmclear(cpu);
1411 }
1412
1413 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1414 {
1415         int cpu = loaded_vmcs->cpu;
1416
1417         if (cpu != -1)
1418                 smp_call_function_single(cpu,
1419                          __loaded_vmcs_clear, loaded_vmcs, 1);
1420 }
1421
1422 static inline void vpid_sync_vcpu_single(int vpid)
1423 {
1424         if (vpid == 0)
1425                 return;
1426
1427         if (cpu_has_vmx_invvpid_single())
1428                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1429 }
1430
1431 static inline void vpid_sync_vcpu_global(void)
1432 {
1433         if (cpu_has_vmx_invvpid_global())
1434                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1435 }
1436
1437 static inline void vpid_sync_context(int vpid)
1438 {
1439         if (cpu_has_vmx_invvpid_single())
1440                 vpid_sync_vcpu_single(vpid);
1441         else
1442                 vpid_sync_vcpu_global();
1443 }
1444
1445 static inline void ept_sync_global(void)
1446 {
1447         if (cpu_has_vmx_invept_global())
1448                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1449 }
1450
1451 static inline void ept_sync_context(u64 eptp)
1452 {
1453         if (enable_ept) {
1454                 if (cpu_has_vmx_invept_context())
1455                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1456                 else
1457                         ept_sync_global();
1458         }
1459 }
1460
1461 static __always_inline void vmcs_check16(unsigned long field)
1462 {
1463         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1464                          "16-bit accessor invalid for 64-bit field");
1465         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1466                          "16-bit accessor invalid for 64-bit high field");
1467         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1468                          "16-bit accessor invalid for 32-bit high field");
1469         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1470                          "16-bit accessor invalid for natural width field");
1471 }
1472
1473 static __always_inline void vmcs_check32(unsigned long field)
1474 {
1475         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1476                          "32-bit accessor invalid for 16-bit field");
1477         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1478                          "32-bit accessor invalid for natural width field");
1479 }
1480
1481 static __always_inline void vmcs_check64(unsigned long field)
1482 {
1483         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1484                          "64-bit accessor invalid for 16-bit field");
1485         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1486                          "64-bit accessor invalid for 64-bit high field");
1487         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1488                          "64-bit accessor invalid for 32-bit field");
1489         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1490                          "64-bit accessor invalid for natural width field");
1491 }
1492
1493 static __always_inline void vmcs_checkl(unsigned long field)
1494 {
1495         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1496                          "Natural width accessor invalid for 16-bit field");
1497         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1498                          "Natural width accessor invalid for 64-bit field");
1499         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1500                          "Natural width accessor invalid for 64-bit high field");
1501         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1502                          "Natural width accessor invalid for 32-bit field");
1503 }
1504
1505 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1506 {
1507         unsigned long value;
1508
1509         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1510                       : "=a"(value) : "d"(field) : "cc");
1511         return value;
1512 }
1513
1514 static __always_inline u16 vmcs_read16(unsigned long field)
1515 {
1516         vmcs_check16(field);
1517         return __vmcs_readl(field);
1518 }
1519
1520 static __always_inline u32 vmcs_read32(unsigned long field)
1521 {
1522         vmcs_check32(field);
1523         return __vmcs_readl(field);
1524 }
1525
1526 static __always_inline u64 vmcs_read64(unsigned long field)
1527 {
1528         vmcs_check64(field);
1529 #ifdef CONFIG_X86_64
1530         return __vmcs_readl(field);
1531 #else
1532         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1533 #endif
1534 }
1535
1536 static __always_inline unsigned long vmcs_readl(unsigned long field)
1537 {
1538         vmcs_checkl(field);
1539         return __vmcs_readl(field);
1540 }
1541
1542 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1543 {
1544         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1545                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1546         dump_stack();
1547 }
1548
1549 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1550 {
1551         u8 error;
1552
1553         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1554                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1555         if (unlikely(error))
1556                 vmwrite_error(field, value);
1557 }
1558
1559 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1560 {
1561         vmcs_check16(field);
1562         __vmcs_writel(field, value);
1563 }
1564
1565 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1566 {
1567         vmcs_check32(field);
1568         __vmcs_writel(field, value);
1569 }
1570
1571 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1572 {
1573         vmcs_check64(field);
1574         __vmcs_writel(field, value);
1575 #ifndef CONFIG_X86_64
1576         asm volatile ("");
1577         __vmcs_writel(field+1, value >> 32);
1578 #endif
1579 }
1580
1581 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1582 {
1583         vmcs_checkl(field);
1584         __vmcs_writel(field, value);
1585 }
1586
1587 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1588 {
1589         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1590                          "vmcs_clear_bits does not support 64-bit fields");
1591         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1592 }
1593
1594 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1595 {
1596         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1597                          "vmcs_set_bits does not support 64-bit fields");
1598         __vmcs_writel(field, __vmcs_readl(field) | mask);
1599 }
1600
1601 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1602 {
1603         vmcs_write32(VM_ENTRY_CONTROLS, val);
1604         vmx->vm_entry_controls_shadow = val;
1605 }
1606
1607 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1608 {
1609         if (vmx->vm_entry_controls_shadow != val)
1610                 vm_entry_controls_init(vmx, val);
1611 }
1612
1613 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1614 {
1615         return vmx->vm_entry_controls_shadow;
1616 }
1617
1618
1619 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1620 {
1621         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1622 }
1623
1624 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1627 }
1628
1629 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1630 {
1631         vmcs_write32(VM_EXIT_CONTROLS, val);
1632         vmx->vm_exit_controls_shadow = val;
1633 }
1634
1635 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1636 {
1637         if (vmx->vm_exit_controls_shadow != val)
1638                 vm_exit_controls_init(vmx, val);
1639 }
1640
1641 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1642 {
1643         return vmx->vm_exit_controls_shadow;
1644 }
1645
1646
1647 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1648 {
1649         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1650 }
1651
1652 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1655 }
1656
1657 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1658 {
1659         vmx->segment_cache.bitmask = 0;
1660 }
1661
1662 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1663                                        unsigned field)
1664 {
1665         bool ret;
1666         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1667
1668         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1669                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1670                 vmx->segment_cache.bitmask = 0;
1671         }
1672         ret = vmx->segment_cache.bitmask & mask;
1673         vmx->segment_cache.bitmask |= mask;
1674         return ret;
1675 }
1676
1677 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1678 {
1679         u16 *p = &vmx->segment_cache.seg[seg].selector;
1680
1681         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1682                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1683         return *p;
1684 }
1685
1686 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1687 {
1688         ulong *p = &vmx->segment_cache.seg[seg].base;
1689
1690         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1691                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1692         return *p;
1693 }
1694
1695 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1696 {
1697         u32 *p = &vmx->segment_cache.seg[seg].limit;
1698
1699         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1700                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1701         return *p;
1702 }
1703
1704 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1705 {
1706         u32 *p = &vmx->segment_cache.seg[seg].ar;
1707
1708         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1709                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1710         return *p;
1711 }
1712
1713 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1714 {
1715         u32 eb;
1716
1717         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1718              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1719         if ((vcpu->guest_debug &
1720              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1721             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1722                 eb |= 1u << BP_VECTOR;
1723         if (to_vmx(vcpu)->rmode.vm86_active)
1724                 eb = ~0;
1725         if (enable_ept)
1726                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1727         if (vcpu->fpu_active)
1728                 eb &= ~(1u << NM_VECTOR);
1729
1730         /* When we are running a nested L2 guest and L1 specified for it a
1731          * certain exception bitmap, we must trap the same exceptions and pass
1732          * them to L1. When running L2, we will only handle the exceptions
1733          * specified above if L1 did not want them.
1734          */
1735         if (is_guest_mode(vcpu))
1736                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1737
1738         vmcs_write32(EXCEPTION_BITMAP, eb);
1739 }
1740
1741 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1742                 unsigned long entry, unsigned long exit)
1743 {
1744         vm_entry_controls_clearbit(vmx, entry);
1745         vm_exit_controls_clearbit(vmx, exit);
1746 }
1747
1748 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1749 {
1750         unsigned i;
1751         struct msr_autoload *m = &vmx->msr_autoload;
1752
1753         switch (msr) {
1754         case MSR_EFER:
1755                 if (cpu_has_load_ia32_efer) {
1756                         clear_atomic_switch_msr_special(vmx,
1757                                         VM_ENTRY_LOAD_IA32_EFER,
1758                                         VM_EXIT_LOAD_IA32_EFER);
1759                         return;
1760                 }
1761                 break;
1762         case MSR_CORE_PERF_GLOBAL_CTRL:
1763                 if (cpu_has_load_perf_global_ctrl) {
1764                         clear_atomic_switch_msr_special(vmx,
1765                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1766                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1767                         return;
1768                 }
1769                 break;
1770         }
1771
1772         for (i = 0; i < m->nr; ++i)
1773                 if (m->guest[i].index == msr)
1774                         break;
1775
1776         if (i == m->nr)
1777                 return;
1778         --m->nr;
1779         m->guest[i] = m->guest[m->nr];
1780         m->host[i] = m->host[m->nr];
1781         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1782         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1783 }
1784
1785 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1786                 unsigned long entry, unsigned long exit,
1787                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1788                 u64 guest_val, u64 host_val)
1789 {
1790         vmcs_write64(guest_val_vmcs, guest_val);
1791         vmcs_write64(host_val_vmcs, host_val);
1792         vm_entry_controls_setbit(vmx, entry);
1793         vm_exit_controls_setbit(vmx, exit);
1794 }
1795
1796 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1797                                   u64 guest_val, u64 host_val)
1798 {
1799         unsigned i;
1800         struct msr_autoload *m = &vmx->msr_autoload;
1801
1802         switch (msr) {
1803         case MSR_EFER:
1804                 if (cpu_has_load_ia32_efer) {
1805                         add_atomic_switch_msr_special(vmx,
1806                                         VM_ENTRY_LOAD_IA32_EFER,
1807                                         VM_EXIT_LOAD_IA32_EFER,
1808                                         GUEST_IA32_EFER,
1809                                         HOST_IA32_EFER,
1810                                         guest_val, host_val);
1811                         return;
1812                 }
1813                 break;
1814         case MSR_CORE_PERF_GLOBAL_CTRL:
1815                 if (cpu_has_load_perf_global_ctrl) {
1816                         add_atomic_switch_msr_special(vmx,
1817                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1818                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1819                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1820                                         HOST_IA32_PERF_GLOBAL_CTRL,
1821                                         guest_val, host_val);
1822                         return;
1823                 }
1824                 break;
1825         }
1826
1827         for (i = 0; i < m->nr; ++i)
1828                 if (m->guest[i].index == msr)
1829                         break;
1830
1831         if (i == NR_AUTOLOAD_MSRS) {
1832                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1833                                 "Can't add msr %x\n", msr);
1834                 return;
1835         } else if (i == m->nr) {
1836                 ++m->nr;
1837                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1838                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1839         }
1840
1841         m->guest[i].index = msr;
1842         m->guest[i].value = guest_val;
1843         m->host[i].index = msr;
1844         m->host[i].value = host_val;
1845 }
1846
1847 static void reload_tss(void)
1848 {
1849         /*
1850          * VT restores TR but not its size.  Useless.
1851          */
1852         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1853         struct desc_struct *descs;
1854
1855         descs = (void *)gdt->address;
1856         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1857         load_TR_desc();
1858 }
1859
1860 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1861 {
1862         u64 guest_efer;
1863         u64 ignore_bits;
1864
1865         guest_efer = vmx->vcpu.arch.efer;
1866
1867         /*
1868          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1869          * outside long mode
1870          */
1871         ignore_bits = EFER_NX | EFER_SCE;
1872 #ifdef CONFIG_X86_64
1873         ignore_bits |= EFER_LMA | EFER_LME;
1874         /* SCE is meaningful only in long mode on Intel */
1875         if (guest_efer & EFER_LMA)
1876                 ignore_bits &= ~(u64)EFER_SCE;
1877 #endif
1878         guest_efer &= ~ignore_bits;
1879         guest_efer |= host_efer & ignore_bits;
1880         vmx->guest_msrs[efer_offset].data = guest_efer;
1881         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1882
1883         clear_atomic_switch_msr(vmx, MSR_EFER);
1884
1885         /*
1886          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1887          * On CPUs that support "load IA32_EFER", always switch EFER
1888          * atomically, since it's faster than switching it manually.
1889          */
1890         if (cpu_has_load_ia32_efer ||
1891             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1892                 guest_efer = vmx->vcpu.arch.efer;
1893                 if (!(guest_efer & EFER_LMA))
1894                         guest_efer &= ~EFER_LME;
1895                 if (guest_efer != host_efer)
1896                         add_atomic_switch_msr(vmx, MSR_EFER,
1897                                               guest_efer, host_efer);
1898                 return false;
1899         }
1900
1901         return true;
1902 }
1903
1904 static unsigned long segment_base(u16 selector)
1905 {
1906         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1907         struct desc_struct *d;
1908         unsigned long table_base;
1909         unsigned long v;
1910
1911         if (!(selector & ~3))
1912                 return 0;
1913
1914         table_base = gdt->address;
1915
1916         if (selector & 4) {           /* from ldt */
1917                 u16 ldt_selector = kvm_read_ldt();
1918
1919                 if (!(ldt_selector & ~3))
1920                         return 0;
1921
1922                 table_base = segment_base(ldt_selector);
1923         }
1924         d = (struct desc_struct *)(table_base + (selector & ~7));
1925         v = get_desc_base(d);
1926 #ifdef CONFIG_X86_64
1927        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1928                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1929 #endif
1930         return v;
1931 }
1932
1933 static inline unsigned long kvm_read_tr_base(void)
1934 {
1935         u16 tr;
1936         asm("str %0" : "=g"(tr));
1937         return segment_base(tr);
1938 }
1939
1940 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1941 {
1942         struct vcpu_vmx *vmx = to_vmx(vcpu);
1943         int i;
1944
1945         if (vmx->host_state.loaded)
1946                 return;
1947
1948         vmx->host_state.loaded = 1;
1949         /*
1950          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1951          * allow segment selectors with cpl > 0 or ti == 1.
1952          */
1953         vmx->host_state.ldt_sel = kvm_read_ldt();
1954         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1955         savesegment(fs, vmx->host_state.fs_sel);
1956         if (!(vmx->host_state.fs_sel & 7)) {
1957                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1958                 vmx->host_state.fs_reload_needed = 0;
1959         } else {
1960                 vmcs_write16(HOST_FS_SELECTOR, 0);
1961                 vmx->host_state.fs_reload_needed = 1;
1962         }
1963         savesegment(gs, vmx->host_state.gs_sel);
1964         if (!(vmx->host_state.gs_sel & 7))
1965                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1966         else {
1967                 vmcs_write16(HOST_GS_SELECTOR, 0);
1968                 vmx->host_state.gs_ldt_reload_needed = 1;
1969         }
1970
1971 #ifdef CONFIG_X86_64
1972         savesegment(ds, vmx->host_state.ds_sel);
1973         savesegment(es, vmx->host_state.es_sel);
1974 #endif
1975
1976 #ifdef CONFIG_X86_64
1977         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1978         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1979 #else
1980         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1981         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1982 #endif
1983
1984 #ifdef CONFIG_X86_64
1985         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1986         if (is_long_mode(&vmx->vcpu))
1987                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1988 #endif
1989         if (boot_cpu_has(X86_FEATURE_MPX))
1990                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1991         for (i = 0; i < vmx->save_nmsrs; ++i)
1992                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1993                                    vmx->guest_msrs[i].data,
1994                                    vmx->guest_msrs[i].mask);
1995 }
1996
1997 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1998 {
1999         if (!vmx->host_state.loaded)
2000                 return;
2001
2002         ++vmx->vcpu.stat.host_state_reload;
2003         vmx->host_state.loaded = 0;
2004 #ifdef CONFIG_X86_64
2005         if (is_long_mode(&vmx->vcpu))
2006                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2007 #endif
2008         if (vmx->host_state.gs_ldt_reload_needed) {
2009                 kvm_load_ldt(vmx->host_state.ldt_sel);
2010 #ifdef CONFIG_X86_64
2011                 load_gs_index(vmx->host_state.gs_sel);
2012 #else
2013                 loadsegment(gs, vmx->host_state.gs_sel);
2014 #endif
2015         }
2016         if (vmx->host_state.fs_reload_needed)
2017                 loadsegment(fs, vmx->host_state.fs_sel);
2018 #ifdef CONFIG_X86_64
2019         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2020                 loadsegment(ds, vmx->host_state.ds_sel);
2021                 loadsegment(es, vmx->host_state.es_sel);
2022         }
2023 #endif
2024         reload_tss();
2025 #ifdef CONFIG_X86_64
2026         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2027 #endif
2028         if (vmx->host_state.msr_host_bndcfgs)
2029                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2030         /*
2031          * If the FPU is not active (through the host task or
2032          * the guest vcpu), then restore the cr0.TS bit.
2033          */
2034         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2035                 stts();
2036         load_gdt(this_cpu_ptr(&host_gdt));
2037 }
2038
2039 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2040 {
2041         preempt_disable();
2042         __vmx_load_host_state(vmx);
2043         preempt_enable();
2044 }
2045
2046 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2047 {
2048         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2049         struct pi_desc old, new;
2050         unsigned int dest;
2051
2052         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2053                 !irq_remapping_cap(IRQ_POSTING_CAP))
2054                 return;
2055
2056         do {
2057                 old.control = new.control = pi_desc->control;
2058
2059                 /*
2060                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2061                  * are two possible cases:
2062                  * 1. After running 'pre_block', context switch
2063                  *    happened. For this case, 'sn' was set in
2064                  *    vmx_vcpu_put(), so we need to clear it here.
2065                  * 2. After running 'pre_block', we were blocked,
2066                  *    and woken up by some other guy. For this case,
2067                  *    we don't need to do anything, 'pi_post_block'
2068                  *    will do everything for us. However, we cannot
2069                  *    check whether it is case #1 or case #2 here
2070                  *    (maybe, not needed), so we also clear sn here,
2071                  *    I think it is not a big deal.
2072                  */
2073                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2074                         if (vcpu->cpu != cpu) {
2075                                 dest = cpu_physical_id(cpu);
2076
2077                                 if (x2apic_enabled())
2078                                         new.ndst = dest;
2079                                 else
2080                                         new.ndst = (dest << 8) & 0xFF00;
2081                         }
2082
2083                         /* set 'NV' to 'notification vector' */
2084                         new.nv = POSTED_INTR_VECTOR;
2085                 }
2086
2087                 /* Allow posting non-urgent interrupts */
2088                 new.sn = 0;
2089         } while (cmpxchg(&pi_desc->control, old.control,
2090                         new.control) != old.control);
2091 }
2092 /*
2093  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2094  * vcpu mutex is already taken.
2095  */
2096 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2097 {
2098         struct vcpu_vmx *vmx = to_vmx(vcpu);
2099         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2100
2101         if (!vmm_exclusive)
2102                 kvm_cpu_vmxon(phys_addr);
2103         else if (vmx->loaded_vmcs->cpu != cpu)
2104                 loaded_vmcs_clear(vmx->loaded_vmcs);
2105
2106         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2107                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2108                 vmcs_load(vmx->loaded_vmcs->vmcs);
2109         }
2110
2111         if (vmx->loaded_vmcs->cpu != cpu) {
2112                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2113                 unsigned long sysenter_esp;
2114
2115                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2116                 local_irq_disable();
2117                 crash_disable_local_vmclear(cpu);
2118
2119                 /*
2120                  * Read loaded_vmcs->cpu should be before fetching
2121                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2122                  * See the comments in __loaded_vmcs_clear().
2123                  */
2124                 smp_rmb();
2125
2126                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2127                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2128                 crash_enable_local_vmclear(cpu);
2129                 local_irq_enable();
2130
2131                 /*
2132                  * Linux uses per-cpu TSS and GDT, so set these when switching
2133                  * processors.
2134                  */
2135                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2136                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2137
2138                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2139                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2140
2141                 /* Setup TSC multiplier */
2142                 if (cpu_has_vmx_tsc_scaling())
2143                         vmcs_write64(TSC_MULTIPLIER,
2144                                      vcpu->arch.tsc_scaling_ratio);
2145
2146                 vmx->loaded_vmcs->cpu = cpu;
2147         }
2148
2149         vmx_vcpu_pi_load(vcpu, cpu);
2150 }
2151
2152 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2153 {
2154         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2155
2156         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2157                 !irq_remapping_cap(IRQ_POSTING_CAP))
2158                 return;
2159
2160         /* Set SN when the vCPU is preempted */
2161         if (vcpu->preempted)
2162                 pi_set_sn(pi_desc);
2163 }
2164
2165 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2166 {
2167         vmx_vcpu_pi_put(vcpu);
2168
2169         __vmx_load_host_state(to_vmx(vcpu));
2170         if (!vmm_exclusive) {
2171                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2172                 vcpu->cpu = -1;
2173                 kvm_cpu_vmxoff();
2174         }
2175 }
2176
2177 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2178 {
2179         ulong cr0;
2180
2181         if (vcpu->fpu_active)
2182                 return;
2183         vcpu->fpu_active = 1;
2184         cr0 = vmcs_readl(GUEST_CR0);
2185         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2186         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2187         vmcs_writel(GUEST_CR0, cr0);
2188         update_exception_bitmap(vcpu);
2189         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2190         if (is_guest_mode(vcpu))
2191                 vcpu->arch.cr0_guest_owned_bits &=
2192                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2193         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2194 }
2195
2196 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2197
2198 /*
2199  * Return the cr0 value that a nested guest would read. This is a combination
2200  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2201  * its hypervisor (cr0_read_shadow).
2202  */
2203 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2204 {
2205         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2206                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2207 }
2208 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2209 {
2210         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2211                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2212 }
2213
2214 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2215 {
2216         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2217          * set this *before* calling this function.
2218          */
2219         vmx_decache_cr0_guest_bits(vcpu);
2220         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2221         update_exception_bitmap(vcpu);
2222         vcpu->arch.cr0_guest_owned_bits = 0;
2223         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2224         if (is_guest_mode(vcpu)) {
2225                 /*
2226                  * L1's specified read shadow might not contain the TS bit,
2227                  * so now that we turned on shadowing of this bit, we need to
2228                  * set this bit of the shadow. Like in nested_vmx_run we need
2229                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2230                  * up-to-date here because we just decached cr0.TS (and we'll
2231                  * only update vmcs12->guest_cr0 on nested exit).
2232                  */
2233                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2234                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2235                         (vcpu->arch.cr0 & X86_CR0_TS);
2236                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2237         } else
2238                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2239 }
2240
2241 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2242 {
2243         unsigned long rflags, save_rflags;
2244
2245         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2246                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2247                 rflags = vmcs_readl(GUEST_RFLAGS);
2248                 if (to_vmx(vcpu)->rmode.vm86_active) {
2249                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2250                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2251                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2252                 }
2253                 to_vmx(vcpu)->rflags = rflags;
2254         }
2255         return to_vmx(vcpu)->rflags;
2256 }
2257
2258 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2259 {
2260         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2261         to_vmx(vcpu)->rflags = rflags;
2262         if (to_vmx(vcpu)->rmode.vm86_active) {
2263                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2264                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2265         }
2266         vmcs_writel(GUEST_RFLAGS, rflags);
2267 }
2268
2269 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2270 {
2271         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2272         int ret = 0;
2273
2274         if (interruptibility & GUEST_INTR_STATE_STI)
2275                 ret |= KVM_X86_SHADOW_INT_STI;
2276         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2277                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2278
2279         return ret;
2280 }
2281
2282 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2283 {
2284         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2285         u32 interruptibility = interruptibility_old;
2286
2287         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2288
2289         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2290                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2291         else if (mask & KVM_X86_SHADOW_INT_STI)
2292                 interruptibility |= GUEST_INTR_STATE_STI;
2293
2294         if ((interruptibility != interruptibility_old))
2295                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2296 }
2297
2298 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2299 {
2300         unsigned long rip;
2301
2302         rip = kvm_rip_read(vcpu);
2303         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2304         kvm_rip_write(vcpu, rip);
2305
2306         /* skipping an emulated instruction also counts */
2307         vmx_set_interrupt_shadow(vcpu, 0);
2308 }
2309
2310 /*
2311  * KVM wants to inject page-faults which it got to the guest. This function
2312  * checks whether in a nested guest, we need to inject them to L1 or L2.
2313  */
2314 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2315 {
2316         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2317
2318         if (!(vmcs12->exception_bitmap & (1u << nr)))
2319                 return 0;
2320
2321         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2322                           vmcs_read32(VM_EXIT_INTR_INFO),
2323                           vmcs_readl(EXIT_QUALIFICATION));
2324         return 1;
2325 }
2326
2327 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2328                                 bool has_error_code, u32 error_code,
2329                                 bool reinject)
2330 {
2331         struct vcpu_vmx *vmx = to_vmx(vcpu);
2332         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2333
2334         if (!reinject && is_guest_mode(vcpu) &&
2335             nested_vmx_check_exception(vcpu, nr))
2336                 return;
2337
2338         if (has_error_code) {
2339                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2340                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2341         }
2342
2343         if (vmx->rmode.vm86_active) {
2344                 int inc_eip = 0;
2345                 if (kvm_exception_is_soft(nr))
2346                         inc_eip = vcpu->arch.event_exit_inst_len;
2347                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2348                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2349                 return;
2350         }
2351
2352         if (kvm_exception_is_soft(nr)) {
2353                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2354                              vmx->vcpu.arch.event_exit_inst_len);
2355                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2356         } else
2357                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2358
2359         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2360 }
2361
2362 static bool vmx_rdtscp_supported(void)
2363 {
2364         return cpu_has_vmx_rdtscp();
2365 }
2366
2367 static bool vmx_invpcid_supported(void)
2368 {
2369         return cpu_has_vmx_invpcid() && enable_ept;
2370 }
2371
2372 /*
2373  * Swap MSR entry in host/guest MSR entry array.
2374  */
2375 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2376 {
2377         struct shared_msr_entry tmp;
2378
2379         tmp = vmx->guest_msrs[to];
2380         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2381         vmx->guest_msrs[from] = tmp;
2382 }
2383
2384 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2385 {
2386         unsigned long *msr_bitmap;
2387
2388         if (is_guest_mode(vcpu))
2389                 msr_bitmap = vmx_msr_bitmap_nested;
2390         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2391                 if (is_long_mode(vcpu))
2392                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2393                 else
2394                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2395         } else {
2396                 if (is_long_mode(vcpu))
2397                         msr_bitmap = vmx_msr_bitmap_longmode;
2398                 else
2399                         msr_bitmap = vmx_msr_bitmap_legacy;
2400         }
2401
2402         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2403 }
2404
2405 /*
2406  * Set up the vmcs to automatically save and restore system
2407  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2408  * mode, as fiddling with msrs is very expensive.
2409  */
2410 static void setup_msrs(struct vcpu_vmx *vmx)
2411 {
2412         int save_nmsrs, index;
2413
2414         save_nmsrs = 0;
2415 #ifdef CONFIG_X86_64
2416         if (is_long_mode(&vmx->vcpu)) {
2417                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2418                 if (index >= 0)
2419                         move_msr_up(vmx, index, save_nmsrs++);
2420                 index = __find_msr_index(vmx, MSR_LSTAR);
2421                 if (index >= 0)
2422                         move_msr_up(vmx, index, save_nmsrs++);
2423                 index = __find_msr_index(vmx, MSR_CSTAR);
2424                 if (index >= 0)
2425                         move_msr_up(vmx, index, save_nmsrs++);
2426                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2427                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2428                         move_msr_up(vmx, index, save_nmsrs++);
2429                 /*
2430                  * MSR_STAR is only needed on long mode guests, and only
2431                  * if efer.sce is enabled.
2432                  */
2433                 index = __find_msr_index(vmx, MSR_STAR);
2434                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2435                         move_msr_up(vmx, index, save_nmsrs++);
2436         }
2437 #endif
2438         index = __find_msr_index(vmx, MSR_EFER);
2439         if (index >= 0 && update_transition_efer(vmx, index))
2440                 move_msr_up(vmx, index, save_nmsrs++);
2441
2442         vmx->save_nmsrs = save_nmsrs;
2443
2444         if (cpu_has_vmx_msr_bitmap())
2445                 vmx_set_msr_bitmap(&vmx->vcpu);
2446 }
2447
2448 /*
2449  * reads and returns guest's timestamp counter "register"
2450  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2451  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2452  */
2453 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2454 {
2455         u64 host_tsc, tsc_offset;
2456
2457         host_tsc = rdtsc();
2458         tsc_offset = vmcs_read64(TSC_OFFSET);
2459         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2460 }
2461
2462 /*
2463  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2464  * counter, even if a nested guest (L2) is currently running.
2465  */
2466 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2467 {
2468         u64 tsc_offset;
2469
2470         tsc_offset = is_guest_mode(vcpu) ?
2471                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2472                 vmcs_read64(TSC_OFFSET);
2473         return host_tsc + tsc_offset;
2474 }
2475
2476 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2477 {
2478         return vmcs_read64(TSC_OFFSET);
2479 }
2480
2481 /*
2482  * writes 'offset' into guest's timestamp counter offset register
2483  */
2484 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2485 {
2486         if (is_guest_mode(vcpu)) {
2487                 /*
2488                  * We're here if L1 chose not to trap WRMSR to TSC. According
2489                  * to the spec, this should set L1's TSC; The offset that L1
2490                  * set for L2 remains unchanged, and still needs to be added
2491                  * to the newly set TSC to get L2's TSC.
2492                  */
2493                 struct vmcs12 *vmcs12;
2494                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2495                 /* recalculate vmcs02.TSC_OFFSET: */
2496                 vmcs12 = get_vmcs12(vcpu);
2497                 vmcs_write64(TSC_OFFSET, offset +
2498                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2499                          vmcs12->tsc_offset : 0));
2500         } else {
2501                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2502                                            vmcs_read64(TSC_OFFSET), offset);
2503                 vmcs_write64(TSC_OFFSET, offset);
2504         }
2505 }
2506
2507 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2508 {
2509         u64 offset = vmcs_read64(TSC_OFFSET);
2510
2511         vmcs_write64(TSC_OFFSET, offset + adjustment);
2512         if (is_guest_mode(vcpu)) {
2513                 /* Even when running L2, the adjustment needs to apply to L1 */
2514                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2515         } else
2516                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2517                                            offset + adjustment);
2518 }
2519
2520 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2521 {
2522         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2523         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2524 }
2525
2526 /*
2527  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2528  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2529  * all guests if the "nested" module option is off, and can also be disabled
2530  * for a single guest by disabling its VMX cpuid bit.
2531  */
2532 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2533 {
2534         return nested && guest_cpuid_has_vmx(vcpu);
2535 }
2536
2537 /*
2538  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2539  * returned for the various VMX controls MSRs when nested VMX is enabled.
2540  * The same values should also be used to verify that vmcs12 control fields are
2541  * valid during nested entry from L1 to L2.
2542  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2543  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2544  * bit in the high half is on if the corresponding bit in the control field
2545  * may be on. See also vmx_control_verify().
2546  */
2547 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2548 {
2549         /*
2550          * Note that as a general rule, the high half of the MSRs (bits in
2551          * the control fields which may be 1) should be initialized by the
2552          * intersection of the underlying hardware's MSR (i.e., features which
2553          * can be supported) and the list of features we want to expose -
2554          * because they are known to be properly supported in our code.
2555          * Also, usually, the low half of the MSRs (bits which must be 1) can
2556          * be set to 0, meaning that L1 may turn off any of these bits. The
2557          * reason is that if one of these bits is necessary, it will appear
2558          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2559          * fields of vmcs01 and vmcs02, will turn these bits off - and
2560          * nested_vmx_exit_handled() will not pass related exits to L1.
2561          * These rules have exceptions below.
2562          */
2563
2564         /* pin-based controls */
2565         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2566                 vmx->nested.nested_vmx_pinbased_ctls_low,
2567                 vmx->nested.nested_vmx_pinbased_ctls_high);
2568         vmx->nested.nested_vmx_pinbased_ctls_low |=
2569                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2570         vmx->nested.nested_vmx_pinbased_ctls_high &=
2571                 PIN_BASED_EXT_INTR_MASK |
2572                 PIN_BASED_NMI_EXITING |
2573                 PIN_BASED_VIRTUAL_NMIS;
2574         vmx->nested.nested_vmx_pinbased_ctls_high |=
2575                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2576                 PIN_BASED_VMX_PREEMPTION_TIMER;
2577         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2578                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2579                         PIN_BASED_POSTED_INTR;
2580
2581         /* exit controls */
2582         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2583                 vmx->nested.nested_vmx_exit_ctls_low,
2584                 vmx->nested.nested_vmx_exit_ctls_high);
2585         vmx->nested.nested_vmx_exit_ctls_low =
2586                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2587
2588         vmx->nested.nested_vmx_exit_ctls_high &=
2589 #ifdef CONFIG_X86_64
2590                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2591 #endif
2592                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2593         vmx->nested.nested_vmx_exit_ctls_high |=
2594                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2595                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2596                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2597
2598         if (vmx_mpx_supported())
2599                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2600
2601         /* We support free control of debug control saving. */
2602         vmx->nested.nested_vmx_true_exit_ctls_low =
2603                 vmx->nested.nested_vmx_exit_ctls_low &
2604                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2605
2606         /* entry controls */
2607         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2608                 vmx->nested.nested_vmx_entry_ctls_low,
2609                 vmx->nested.nested_vmx_entry_ctls_high);
2610         vmx->nested.nested_vmx_entry_ctls_low =
2611                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2612         vmx->nested.nested_vmx_entry_ctls_high &=
2613 #ifdef CONFIG_X86_64
2614                 VM_ENTRY_IA32E_MODE |
2615 #endif
2616                 VM_ENTRY_LOAD_IA32_PAT;
2617         vmx->nested.nested_vmx_entry_ctls_high |=
2618                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2619         if (vmx_mpx_supported())
2620                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2621
2622         /* We support free control of debug control loading. */
2623         vmx->nested.nested_vmx_true_entry_ctls_low =
2624                 vmx->nested.nested_vmx_entry_ctls_low &
2625                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2626
2627         /* cpu-based controls */
2628         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2629                 vmx->nested.nested_vmx_procbased_ctls_low,
2630                 vmx->nested.nested_vmx_procbased_ctls_high);
2631         vmx->nested.nested_vmx_procbased_ctls_low =
2632                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2633         vmx->nested.nested_vmx_procbased_ctls_high &=
2634                 CPU_BASED_VIRTUAL_INTR_PENDING |
2635                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2636                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2637                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2638                 CPU_BASED_CR3_STORE_EXITING |
2639 #ifdef CONFIG_X86_64
2640                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2641 #endif
2642                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2643                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2644                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2645                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2646                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2647         /*
2648          * We can allow some features even when not supported by the
2649          * hardware. For example, L1 can specify an MSR bitmap - and we
2650          * can use it to avoid exits to L1 - even when L0 runs L2
2651          * without MSR bitmaps.
2652          */
2653         vmx->nested.nested_vmx_procbased_ctls_high |=
2654                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2655                 CPU_BASED_USE_MSR_BITMAPS;
2656
2657         /* We support free control of CR3 access interception. */
2658         vmx->nested.nested_vmx_true_procbased_ctls_low =
2659                 vmx->nested.nested_vmx_procbased_ctls_low &
2660                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2661
2662         /* secondary cpu-based controls */
2663         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2664                 vmx->nested.nested_vmx_secondary_ctls_low,
2665                 vmx->nested.nested_vmx_secondary_ctls_high);
2666         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2667         vmx->nested.nested_vmx_secondary_ctls_high &=
2668                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2669                 SECONDARY_EXEC_RDTSCP |
2670                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2671                 SECONDARY_EXEC_ENABLE_VPID |
2672                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2673                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2674                 SECONDARY_EXEC_WBINVD_EXITING |
2675                 SECONDARY_EXEC_XSAVES |
2676                 SECONDARY_EXEC_PCOMMIT;
2677
2678         if (enable_ept) {
2679                 /* nested EPT: emulate EPT also to L1 */
2680                 vmx->nested.nested_vmx_secondary_ctls_high |=
2681                         SECONDARY_EXEC_ENABLE_EPT;
2682                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2683                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2684                          VMX_EPT_INVEPT_BIT;
2685                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2686                 /*
2687                  * For nested guests, we don't do anything specific
2688                  * for single context invalidation. Hence, only advertise
2689                  * support for global context invalidation.
2690                  */
2691                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2692         } else
2693                 vmx->nested.nested_vmx_ept_caps = 0;
2694
2695         if (enable_vpid)
2696                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2697                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2698         else
2699                 vmx->nested.nested_vmx_vpid_caps = 0;
2700
2701         if (enable_unrestricted_guest)
2702                 vmx->nested.nested_vmx_secondary_ctls_high |=
2703                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2704
2705         /* miscellaneous data */
2706         rdmsr(MSR_IA32_VMX_MISC,
2707                 vmx->nested.nested_vmx_misc_low,
2708                 vmx->nested.nested_vmx_misc_high);
2709         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2710         vmx->nested.nested_vmx_misc_low |=
2711                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2712                 VMX_MISC_ACTIVITY_HLT;
2713         vmx->nested.nested_vmx_misc_high = 0;
2714 }
2715
2716 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2717 {
2718         /*
2719          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2720          */
2721         return ((control & high) | low) == control;
2722 }
2723
2724 static inline u64 vmx_control_msr(u32 low, u32 high)
2725 {
2726         return low | ((u64)high << 32);
2727 }
2728
2729 /* Returns 0 on success, non-0 otherwise. */
2730 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2731 {
2732         struct vcpu_vmx *vmx = to_vmx(vcpu);
2733
2734         switch (msr_index) {
2735         case MSR_IA32_VMX_BASIC:
2736                 /*
2737                  * This MSR reports some information about VMX support. We
2738                  * should return information about the VMX we emulate for the
2739                  * guest, and the VMCS structure we give it - not about the
2740                  * VMX support of the underlying hardware.
2741                  */
2742                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2743                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2744                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2745                 break;
2746         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2747         case MSR_IA32_VMX_PINBASED_CTLS:
2748                 *pdata = vmx_control_msr(
2749                         vmx->nested.nested_vmx_pinbased_ctls_low,
2750                         vmx->nested.nested_vmx_pinbased_ctls_high);
2751                 break;
2752         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2753                 *pdata = vmx_control_msr(
2754                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2755                         vmx->nested.nested_vmx_procbased_ctls_high);
2756                 break;
2757         case MSR_IA32_VMX_PROCBASED_CTLS:
2758                 *pdata = vmx_control_msr(
2759                         vmx->nested.nested_vmx_procbased_ctls_low,
2760                         vmx->nested.nested_vmx_procbased_ctls_high);
2761                 break;
2762         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2763                 *pdata = vmx_control_msr(
2764                         vmx->nested.nested_vmx_true_exit_ctls_low,
2765                         vmx->nested.nested_vmx_exit_ctls_high);
2766                 break;
2767         case MSR_IA32_VMX_EXIT_CTLS:
2768                 *pdata = vmx_control_msr(
2769                         vmx->nested.nested_vmx_exit_ctls_low,
2770                         vmx->nested.nested_vmx_exit_ctls_high);
2771                 break;
2772         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2773                 *pdata = vmx_control_msr(
2774                         vmx->nested.nested_vmx_true_entry_ctls_low,
2775                         vmx->nested.nested_vmx_entry_ctls_high);
2776                 break;
2777         case MSR_IA32_VMX_ENTRY_CTLS:
2778                 *pdata = vmx_control_msr(
2779                         vmx->nested.nested_vmx_entry_ctls_low,
2780                         vmx->nested.nested_vmx_entry_ctls_high);
2781                 break;
2782         case MSR_IA32_VMX_MISC:
2783                 *pdata = vmx_control_msr(
2784                         vmx->nested.nested_vmx_misc_low,
2785                         vmx->nested.nested_vmx_misc_high);
2786                 break;
2787         /*
2788          * These MSRs specify bits which the guest must keep fixed (on or off)
2789          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2790          * We picked the standard core2 setting.
2791          */
2792 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2793 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2794         case MSR_IA32_VMX_CR0_FIXED0:
2795                 *pdata = VMXON_CR0_ALWAYSON;
2796                 break;
2797         case MSR_IA32_VMX_CR0_FIXED1:
2798                 *pdata = -1ULL;
2799                 break;
2800         case MSR_IA32_VMX_CR4_FIXED0:
2801                 *pdata = VMXON_CR4_ALWAYSON;
2802                 break;
2803         case MSR_IA32_VMX_CR4_FIXED1:
2804                 *pdata = -1ULL;
2805                 break;
2806         case MSR_IA32_VMX_VMCS_ENUM:
2807                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2808                 break;
2809         case MSR_IA32_VMX_PROCBASED_CTLS2:
2810                 *pdata = vmx_control_msr(
2811                         vmx->nested.nested_vmx_secondary_ctls_low,
2812                         vmx->nested.nested_vmx_secondary_ctls_high);
2813                 break;
2814         case MSR_IA32_VMX_EPT_VPID_CAP:
2815                 /* Currently, no nested vpid support */
2816                 *pdata = vmx->nested.nested_vmx_ept_caps |
2817                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2818                 break;
2819         default:
2820                 return 1;
2821         }
2822
2823         return 0;
2824 }
2825
2826 /*
2827  * Reads an msr value (of 'msr_index') into 'pdata'.
2828  * Returns 0 on success, non-0 otherwise.
2829  * Assumes vcpu_load() was already called.
2830  */
2831 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2832 {
2833         struct shared_msr_entry *msr;
2834
2835         switch (msr_info->index) {
2836 #ifdef CONFIG_X86_64
2837         case MSR_FS_BASE:
2838                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2839                 break;
2840         case MSR_GS_BASE:
2841                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2842                 break;
2843         case MSR_KERNEL_GS_BASE:
2844                 vmx_load_host_state(to_vmx(vcpu));
2845                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2846                 break;
2847 #endif
2848         case MSR_EFER:
2849                 return kvm_get_msr_common(vcpu, msr_info);
2850         case MSR_IA32_TSC:
2851                 msr_info->data = guest_read_tsc(vcpu);
2852                 break;
2853         case MSR_IA32_SYSENTER_CS:
2854                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2855                 break;
2856         case MSR_IA32_SYSENTER_EIP:
2857                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2858                 break;
2859         case MSR_IA32_SYSENTER_ESP:
2860                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2861                 break;
2862         case MSR_IA32_BNDCFGS:
2863                 if (!vmx_mpx_supported())
2864                         return 1;
2865                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2866                 break;
2867         case MSR_IA32_FEATURE_CONTROL:
2868                 if (!nested_vmx_allowed(vcpu))
2869                         return 1;
2870                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2871                 break;
2872         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2873                 if (!nested_vmx_allowed(vcpu))
2874                         return 1;
2875                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2876         case MSR_IA32_XSS:
2877                 if (!vmx_xsaves_supported())
2878                         return 1;
2879                 msr_info->data = vcpu->arch.ia32_xss;
2880                 break;
2881         case MSR_TSC_AUX:
2882                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2883                         return 1;
2884                 /* Otherwise falls through */
2885         default:
2886                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2887                 if (msr) {
2888                         msr_info->data = msr->data;
2889                         break;
2890                 }
2891                 return kvm_get_msr_common(vcpu, msr_info);
2892         }
2893
2894         return 0;
2895 }
2896
2897 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2898
2899 /*
2900  * Writes msr value into into the appropriate "register".
2901  * Returns 0 on success, non-0 otherwise.
2902  * Assumes vcpu_load() was already called.
2903  */
2904 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2905 {
2906         struct vcpu_vmx *vmx = to_vmx(vcpu);
2907         struct shared_msr_entry *msr;
2908         int ret = 0;
2909         u32 msr_index = msr_info->index;
2910         u64 data = msr_info->data;
2911
2912         switch (msr_index) {
2913         case MSR_EFER:
2914                 ret = kvm_set_msr_common(vcpu, msr_info);
2915                 break;
2916 #ifdef CONFIG_X86_64
2917         case MSR_FS_BASE:
2918                 vmx_segment_cache_clear(vmx);
2919                 vmcs_writel(GUEST_FS_BASE, data);
2920                 break;
2921         case MSR_GS_BASE:
2922                 vmx_segment_cache_clear(vmx);
2923                 vmcs_writel(GUEST_GS_BASE, data);
2924                 break;
2925         case MSR_KERNEL_GS_BASE:
2926                 vmx_load_host_state(vmx);
2927                 vmx->msr_guest_kernel_gs_base = data;
2928                 break;
2929 #endif
2930         case MSR_IA32_SYSENTER_CS:
2931                 vmcs_write32(GUEST_SYSENTER_CS, data);
2932                 break;
2933         case MSR_IA32_SYSENTER_EIP:
2934                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2935                 break;
2936         case MSR_IA32_SYSENTER_ESP:
2937                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2938                 break;
2939         case MSR_IA32_BNDCFGS:
2940                 if (!vmx_mpx_supported())
2941                         return 1;
2942                 vmcs_write64(GUEST_BNDCFGS, data);
2943                 break;
2944         case MSR_IA32_TSC:
2945                 kvm_write_tsc(vcpu, msr_info);
2946                 break;
2947         case MSR_IA32_CR_PAT:
2948                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2949                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2950                                 return 1;
2951                         vmcs_write64(GUEST_IA32_PAT, data);
2952                         vcpu->arch.pat = data;
2953                         break;
2954                 }
2955                 ret = kvm_set_msr_common(vcpu, msr_info);
2956                 break;
2957         case MSR_IA32_TSC_ADJUST:
2958                 ret = kvm_set_msr_common(vcpu, msr_info);
2959                 break;
2960         case MSR_IA32_FEATURE_CONTROL:
2961                 if (!nested_vmx_allowed(vcpu) ||
2962                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2963                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2964                         return 1;
2965                 vmx->nested.msr_ia32_feature_control = data;
2966                 if (msr_info->host_initiated && data == 0)
2967                         vmx_leave_nested(vcpu);
2968                 break;
2969         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2970                 return 1; /* they are read-only */
2971         case MSR_IA32_XSS:
2972                 if (!vmx_xsaves_supported())
2973                         return 1;
2974                 /*
2975                  * The only supported bit as of Skylake is bit 8, but
2976                  * it is not supported on KVM.
2977                  */
2978                 if (data != 0)
2979                         return 1;
2980                 vcpu->arch.ia32_xss = data;
2981                 if (vcpu->arch.ia32_xss != host_xss)
2982                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2983                                 vcpu->arch.ia32_xss, host_xss);
2984                 else
2985                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2986                 break;
2987         case MSR_TSC_AUX:
2988                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2989                         return 1;
2990                 /* Check reserved bit, higher 32 bits should be zero */
2991                 if ((data >> 32) != 0)
2992                         return 1;
2993                 /* Otherwise falls through */
2994         default:
2995                 msr = find_msr_entry(vmx, msr_index);
2996                 if (msr) {
2997                         u64 old_msr_data = msr->data;
2998                         msr->data = data;
2999                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3000                                 preempt_disable();
3001                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3002                                                          msr->mask);
3003                                 preempt_enable();
3004                                 if (ret)
3005                                         msr->data = old_msr_data;
3006                         }
3007                         break;
3008                 }
3009                 ret = kvm_set_msr_common(vcpu, msr_info);
3010         }
3011
3012         return ret;
3013 }
3014
3015 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3016 {
3017         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3018         switch (reg) {
3019         case VCPU_REGS_RSP:
3020                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3021                 break;
3022         case VCPU_REGS_RIP:
3023                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3024                 break;
3025         case VCPU_EXREG_PDPTR:
3026                 if (enable_ept)
3027                         ept_save_pdptrs(vcpu);
3028                 break;
3029         default:
3030                 break;
3031         }
3032 }
3033
3034 static __init int cpu_has_kvm_support(void)
3035 {
3036         return cpu_has_vmx();
3037 }
3038
3039 static __init int vmx_disabled_by_bios(void)
3040 {
3041         u64 msr;
3042
3043         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3044         if (msr & FEATURE_CONTROL_LOCKED) {
3045                 /* launched w/ TXT and VMX disabled */
3046                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3047                         && tboot_enabled())
3048                         return 1;
3049                 /* launched w/o TXT and VMX only enabled w/ TXT */
3050                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3051                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3052                         && !tboot_enabled()) {
3053                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3054                                 "activate TXT before enabling KVM\n");
3055                         return 1;
3056                 }
3057                 /* launched w/o TXT and VMX disabled */
3058                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3059                         && !tboot_enabled())
3060                         return 1;
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void kvm_cpu_vmxon(u64 addr)
3067 {
3068         asm volatile (ASM_VMX_VMXON_RAX
3069                         : : "a"(&addr), "m"(addr)
3070                         : "memory", "cc");
3071 }
3072
3073 static int hardware_enable(void)
3074 {
3075         int cpu = raw_smp_processor_id();
3076         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3077         u64 old, test_bits;
3078
3079         if (cr4_read_shadow() & X86_CR4_VMXE)
3080                 return -EBUSY;
3081
3082         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3083         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3084         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3085
3086         /*
3087          * Now we can enable the vmclear operation in kdump
3088          * since the loaded_vmcss_on_cpu list on this cpu
3089          * has been initialized.
3090          *
3091          * Though the cpu is not in VMX operation now, there
3092          * is no problem to enable the vmclear operation
3093          * for the loaded_vmcss_on_cpu list is empty!
3094          */
3095         crash_enable_local_vmclear(cpu);
3096
3097         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3098
3099         test_bits = FEATURE_CONTROL_LOCKED;
3100         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3101         if (tboot_enabled())
3102                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3103
3104         if ((old & test_bits) != test_bits) {
3105                 /* enable and lock */
3106                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3107         }
3108         cr4_set_bits(X86_CR4_VMXE);
3109
3110         if (vmm_exclusive) {
3111                 kvm_cpu_vmxon(phys_addr);
3112                 ept_sync_global();
3113         }
3114
3115         native_store_gdt(this_cpu_ptr(&host_gdt));
3116
3117         return 0;
3118 }
3119
3120 static void vmclear_local_loaded_vmcss(void)
3121 {
3122         int cpu = raw_smp_processor_id();
3123         struct loaded_vmcs *v, *n;
3124
3125         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3126                                  loaded_vmcss_on_cpu_link)
3127                 __loaded_vmcs_clear(v);
3128 }
3129
3130
3131 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3132  * tricks.
3133  */
3134 static void kvm_cpu_vmxoff(void)
3135 {
3136         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3137 }
3138
3139 static void hardware_disable(void)
3140 {
3141         if (vmm_exclusive) {
3142                 vmclear_local_loaded_vmcss();
3143                 kvm_cpu_vmxoff();
3144         }
3145         cr4_clear_bits(X86_CR4_VMXE);
3146 }
3147
3148 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3149                                       u32 msr, u32 *result)
3150 {
3151         u32 vmx_msr_low, vmx_msr_high;
3152         u32 ctl = ctl_min | ctl_opt;
3153
3154         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3155
3156         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3157         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3158
3159         /* Ensure minimum (required) set of control bits are supported. */
3160         if (ctl_min & ~ctl)
3161                 return -EIO;
3162
3163         *result = ctl;
3164         return 0;
3165 }
3166
3167 static __init bool allow_1_setting(u32 msr, u32 ctl)
3168 {
3169         u32 vmx_msr_low, vmx_msr_high;
3170
3171         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3172         return vmx_msr_high & ctl;
3173 }
3174
3175 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3176 {
3177         u32 vmx_msr_low, vmx_msr_high;
3178         u32 min, opt, min2, opt2;
3179         u32 _pin_based_exec_control = 0;
3180         u32 _cpu_based_exec_control = 0;
3181         u32 _cpu_based_2nd_exec_control = 0;
3182         u32 _vmexit_control = 0;
3183         u32 _vmentry_control = 0;
3184
3185         min = CPU_BASED_HLT_EXITING |
3186 #ifdef CONFIG_X86_64
3187               CPU_BASED_CR8_LOAD_EXITING |
3188               CPU_BASED_CR8_STORE_EXITING |
3189 #endif
3190               CPU_BASED_CR3_LOAD_EXITING |
3191               CPU_BASED_CR3_STORE_EXITING |
3192               CPU_BASED_USE_IO_BITMAPS |
3193               CPU_BASED_MOV_DR_EXITING |
3194               CPU_BASED_USE_TSC_OFFSETING |
3195               CPU_BASED_MWAIT_EXITING |
3196               CPU_BASED_MONITOR_EXITING |
3197               CPU_BASED_INVLPG_EXITING |
3198               CPU_BASED_RDPMC_EXITING;
3199
3200         opt = CPU_BASED_TPR_SHADOW |
3201               CPU_BASED_USE_MSR_BITMAPS |
3202               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3203         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3204                                 &_cpu_based_exec_control) < 0)
3205                 return -EIO;
3206 #ifdef CONFIG_X86_64
3207         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3208                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3209                                            ~CPU_BASED_CR8_STORE_EXITING;
3210 #endif
3211         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3212                 min2 = 0;
3213                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3214                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3215                         SECONDARY_EXEC_WBINVD_EXITING |
3216                         SECONDARY_EXEC_ENABLE_VPID |
3217                         SECONDARY_EXEC_ENABLE_EPT |
3218                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3219                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3220                         SECONDARY_EXEC_RDTSCP |
3221                         SECONDARY_EXEC_ENABLE_INVPCID |
3222                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3223                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3224                         SECONDARY_EXEC_SHADOW_VMCS |
3225                         SECONDARY_EXEC_XSAVES |
3226                         SECONDARY_EXEC_ENABLE_PML |
3227                         SECONDARY_EXEC_PCOMMIT |
3228                         SECONDARY_EXEC_TSC_SCALING;
3229                 if (adjust_vmx_controls(min2, opt2,
3230                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3231                                         &_cpu_based_2nd_exec_control) < 0)
3232                         return -EIO;
3233         }
3234 #ifndef CONFIG_X86_64
3235         if (!(_cpu_based_2nd_exec_control &
3236                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3237                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3238 #endif
3239
3240         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3241                 _cpu_based_2nd_exec_control &= ~(
3242                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3243                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3244                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3245
3246         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3247                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3248                    enabled */
3249                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3250                                              CPU_BASED_CR3_STORE_EXITING |
3251                                              CPU_BASED_INVLPG_EXITING);
3252                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3253                       vmx_capability.ept, vmx_capability.vpid);
3254         }
3255
3256         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3257 #ifdef CONFIG_X86_64
3258         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3259 #endif
3260         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3261                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3262         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3263                                 &_vmexit_control) < 0)
3264                 return -EIO;
3265
3266         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3267         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3268         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3269                                 &_pin_based_exec_control) < 0)
3270                 return -EIO;
3271
3272         if (!(_cpu_based_2nd_exec_control &
3273                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3274                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3275                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3276
3277         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3278         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3279         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3280                                 &_vmentry_control) < 0)
3281                 return -EIO;
3282
3283         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3284
3285         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3286         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3287                 return -EIO;
3288
3289 #ifdef CONFIG_X86_64
3290         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3291         if (vmx_msr_high & (1u<<16))
3292                 return -EIO;
3293 #endif
3294
3295         /* Require Write-Back (WB) memory type for VMCS accesses. */
3296         if (((vmx_msr_high >> 18) & 15) != 6)
3297                 return -EIO;
3298
3299         vmcs_conf->size = vmx_msr_high & 0x1fff;
3300         vmcs_conf->order = get_order(vmcs_config.size);
3301         vmcs_conf->revision_id = vmx_msr_low;
3302
3303         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3304         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3305         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3306         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3307         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3308
3309         cpu_has_load_ia32_efer =
3310                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3311                                 VM_ENTRY_LOAD_IA32_EFER)
3312                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3313                                    VM_EXIT_LOAD_IA32_EFER);
3314
3315         cpu_has_load_perf_global_ctrl =
3316                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3317                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3318                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3319                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3320
3321         /*
3322          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3323          * but due to arrata below it can't be used. Workaround is to use
3324          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3325          *
3326          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3327          *
3328          * AAK155             (model 26)
3329          * AAP115             (model 30)
3330          * AAT100             (model 37)
3331          * BC86,AAY89,BD102   (model 44)
3332          * BA97               (model 46)
3333          *
3334          */
3335         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3336                 switch (boot_cpu_data.x86_model) {
3337                 case 26:
3338                 case 30:
3339                 case 37:
3340                 case 44:
3341                 case 46:
3342                         cpu_has_load_perf_global_ctrl = false;
3343                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3344                                         "does not work properly. Using workaround\n");
3345                         break;
3346                 default:
3347                         break;
3348                 }
3349         }
3350
3351         if (cpu_has_xsaves)
3352                 rdmsrl(MSR_IA32_XSS, host_xss);
3353
3354         return 0;
3355 }
3356
3357 static struct vmcs *alloc_vmcs_cpu(int cpu)
3358 {
3359         int node = cpu_to_node(cpu);
3360         struct page *pages;
3361         struct vmcs *vmcs;
3362
3363         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3364         if (!pages)
3365                 return NULL;
3366         vmcs = page_address(pages);
3367         memset(vmcs, 0, vmcs_config.size);
3368         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3369         return vmcs;
3370 }
3371
3372 static struct vmcs *alloc_vmcs(void)
3373 {
3374         return alloc_vmcs_cpu(raw_smp_processor_id());
3375 }
3376
3377 static void free_vmcs(struct vmcs *vmcs)
3378 {
3379         free_pages((unsigned long)vmcs, vmcs_config.order);
3380 }
3381
3382 /*
3383  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3384  */
3385 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3386 {
3387         if (!loaded_vmcs->vmcs)
3388                 return;
3389         loaded_vmcs_clear(loaded_vmcs);
3390         free_vmcs(loaded_vmcs->vmcs);
3391         loaded_vmcs->vmcs = NULL;
3392 }
3393
3394 static void free_kvm_area(void)
3395 {
3396         int cpu;
3397
3398         for_each_possible_cpu(cpu) {
3399                 free_vmcs(per_cpu(vmxarea, cpu));
3400                 per_cpu(vmxarea, cpu) = NULL;
3401         }
3402 }
3403
3404 static void init_vmcs_shadow_fields(void)
3405 {
3406         int i, j;
3407
3408         /* No checks for read only fields yet */
3409
3410         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3411                 switch (shadow_read_write_fields[i]) {
3412                 case GUEST_BNDCFGS:
3413                         if (!vmx_mpx_supported())
3414                                 continue;
3415                         break;
3416                 default:
3417                         break;
3418                 }
3419
3420                 if (j < i)
3421                         shadow_read_write_fields[j] =
3422                                 shadow_read_write_fields[i];
3423                 j++;
3424         }
3425         max_shadow_read_write_fields = j;
3426
3427         /* shadowed fields guest access without vmexit */
3428         for (i = 0; i < max_shadow_read_write_fields; i++) {
3429                 clear_bit(shadow_read_write_fields[i],
3430                           vmx_vmwrite_bitmap);
3431                 clear_bit(shadow_read_write_fields[i],
3432                           vmx_vmread_bitmap);
3433         }
3434         for (i = 0; i < max_shadow_read_only_fields; i++)
3435                 clear_bit(shadow_read_only_fields[i],
3436                           vmx_vmread_bitmap);
3437 }
3438
3439 static __init int alloc_kvm_area(void)
3440 {
3441         int cpu;
3442
3443         for_each_possible_cpu(cpu) {
3444                 struct vmcs *vmcs;
3445
3446                 vmcs = alloc_vmcs_cpu(cpu);
3447                 if (!vmcs) {
3448                         free_kvm_area();
3449                         return -ENOMEM;
3450                 }
3451
3452                 per_cpu(vmxarea, cpu) = vmcs;
3453         }
3454         return 0;
3455 }
3456
3457 static bool emulation_required(struct kvm_vcpu *vcpu)
3458 {
3459         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3460 }
3461
3462 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3463                 struct kvm_segment *save)
3464 {
3465         if (!emulate_invalid_guest_state) {
3466                 /*
3467                  * CS and SS RPL should be equal during guest entry according
3468                  * to VMX spec, but in reality it is not always so. Since vcpu
3469                  * is in the middle of the transition from real mode to
3470                  * protected mode it is safe to assume that RPL 0 is a good
3471                  * default value.
3472                  */
3473                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3474                         save->selector &= ~SEGMENT_RPL_MASK;
3475                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3476                 save->s = 1;
3477         }
3478         vmx_set_segment(vcpu, save, seg);
3479 }
3480
3481 static void enter_pmode(struct kvm_vcpu *vcpu)
3482 {
3483         unsigned long flags;
3484         struct vcpu_vmx *vmx = to_vmx(vcpu);
3485
3486         /*
3487          * Update real mode segment cache. It may be not up-to-date if sement
3488          * register was written while vcpu was in a guest mode.
3489          */
3490         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3491         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3492         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3493         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3494         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3495         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3496
3497         vmx->rmode.vm86_active = 0;
3498
3499         vmx_segment_cache_clear(vmx);
3500
3501         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3502
3503         flags = vmcs_readl(GUEST_RFLAGS);
3504         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3505         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3506         vmcs_writel(GUEST_RFLAGS, flags);
3507
3508         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3509                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3510
3511         update_exception_bitmap(vcpu);
3512
3513         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3514         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3515         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3516         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3517         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3518         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3519 }
3520
3521 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3522 {
3523         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3524         struct kvm_segment var = *save;
3525
3526         var.dpl = 0x3;
3527         if (seg == VCPU_SREG_CS)
3528                 var.type = 0x3;
3529
3530         if (!emulate_invalid_guest_state) {
3531                 var.selector = var.base >> 4;
3532                 var.base = var.base & 0xffff0;
3533                 var.limit = 0xffff;
3534                 var.g = 0;
3535                 var.db = 0;
3536                 var.present = 1;
3537                 var.s = 1;
3538                 var.l = 0;
3539                 var.unusable = 0;
3540                 var.type = 0x3;
3541                 var.avl = 0;
3542                 if (save->base & 0xf)
3543                         printk_once(KERN_WARNING "kvm: segment base is not "
3544                                         "paragraph aligned when entering "
3545                                         "protected mode (seg=%d)", seg);
3546         }
3547
3548         vmcs_write16(sf->selector, var.selector);
3549         vmcs_write32(sf->base, var.base);
3550         vmcs_write32(sf->limit, var.limit);
3551         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3552 }
3553
3554 static void enter_rmode(struct kvm_vcpu *vcpu)
3555 {
3556         unsigned long flags;
3557         struct vcpu_vmx *vmx = to_vmx(vcpu);
3558
3559         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3560         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3561         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3562         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3563         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3564         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3565         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3566
3567         vmx->rmode.vm86_active = 1;
3568
3569         /*
3570          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3571          * vcpu. Warn the user that an update is overdue.
3572          */
3573         if (!vcpu->kvm->arch.tss_addr)
3574                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3575                              "called before entering vcpu\n");
3576
3577         vmx_segment_cache_clear(vmx);
3578
3579         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3580         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3581         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3582
3583         flags = vmcs_readl(GUEST_RFLAGS);
3584         vmx->rmode.save_rflags = flags;
3585
3586         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3587
3588         vmcs_writel(GUEST_RFLAGS, flags);
3589         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3590         update_exception_bitmap(vcpu);
3591
3592         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3593         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3594         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3595         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3596         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3597         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3598
3599         kvm_mmu_reset_context(vcpu);
3600 }
3601
3602 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3603 {
3604         struct vcpu_vmx *vmx = to_vmx(vcpu);
3605         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3606
3607         if (!msr)
3608                 return;
3609
3610         /*
3611          * Force kernel_gs_base reloading before EFER changes, as control
3612          * of this msr depends on is_long_mode().
3613          */
3614         vmx_load_host_state(to_vmx(vcpu));
3615         vcpu->arch.efer = efer;
3616         if (efer & EFER_LMA) {
3617                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3618                 msr->data = efer;
3619         } else {
3620                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3621
3622                 msr->data = efer & ~EFER_LME;
3623         }
3624         setup_msrs(vmx);
3625 }
3626
3627 #ifdef CONFIG_X86_64
3628
3629 static void enter_lmode(struct kvm_vcpu *vcpu)
3630 {
3631         u32 guest_tr_ar;
3632
3633         vmx_segment_cache_clear(to_vmx(vcpu));
3634
3635         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3636         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3637                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3638                                      __func__);
3639                 vmcs_write32(GUEST_TR_AR_BYTES,
3640                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3641                              | VMX_AR_TYPE_BUSY_64_TSS);
3642         }
3643         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3644 }
3645
3646 static void exit_lmode(struct kvm_vcpu *vcpu)
3647 {
3648         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3649         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3650 }
3651
3652 #endif
3653
3654 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3655 {
3656         vpid_sync_context(vpid);
3657         if (enable_ept) {
3658                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3659                         return;
3660                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3661         }
3662 }
3663
3664 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3665 {
3666         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3667 }
3668
3669 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3670 {
3671         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3672
3673         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3674         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3675 }
3676
3677 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3678 {
3679         if (enable_ept && is_paging(vcpu))
3680                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3681         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3682 }
3683
3684 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3685 {
3686         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3687
3688         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3689         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3690 }
3691
3692 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3693 {
3694         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3695
3696         if (!test_bit(VCPU_EXREG_PDPTR,
3697                       (unsigned long *)&vcpu->arch.regs_dirty))
3698                 return;
3699
3700         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3701                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3702                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3703                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3704                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3705         }
3706 }
3707
3708 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3709 {
3710         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3711
3712         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3713                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3714                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3715                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3716                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3717         }
3718
3719         __set_bit(VCPU_EXREG_PDPTR,
3720                   (unsigned long *)&vcpu->arch.regs_avail);
3721         __set_bit(VCPU_EXREG_PDPTR,
3722                   (unsigned long *)&vcpu->arch.regs_dirty);
3723 }
3724
3725 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3726
3727 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3728                                         unsigned long cr0,
3729                                         struct kvm_vcpu *vcpu)
3730 {
3731         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3732                 vmx_decache_cr3(vcpu);
3733         if (!(cr0 & X86_CR0_PG)) {
3734                 /* From paging/starting to nonpaging */
3735                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3736                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3737                              (CPU_BASED_CR3_LOAD_EXITING |
3738                               CPU_BASED_CR3_STORE_EXITING));
3739                 vcpu->arch.cr0 = cr0;
3740                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3741         } else if (!is_paging(vcpu)) {
3742                 /* From nonpaging to paging */
3743                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3744                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3745                              ~(CPU_BASED_CR3_LOAD_EXITING |
3746                                CPU_BASED_CR3_STORE_EXITING));
3747                 vcpu->arch.cr0 = cr0;
3748                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3749         }
3750
3751         if (!(cr0 & X86_CR0_WP))
3752                 *hw_cr0 &= ~X86_CR0_WP;
3753 }
3754
3755 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3756 {
3757         struct vcpu_vmx *vmx = to_vmx(vcpu);
3758         unsigned long hw_cr0;
3759
3760         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3761         if (enable_unrestricted_guest)
3762                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3763         else {
3764                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3765
3766                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3767                         enter_pmode(vcpu);
3768
3769                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3770                         enter_rmode(vcpu);
3771         }
3772
3773 #ifdef CONFIG_X86_64
3774         if (vcpu->arch.efer & EFER_LME) {
3775                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3776                         enter_lmode(vcpu);
3777                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3778                         exit_lmode(vcpu);
3779         }
3780 #endif
3781
3782         if (enable_ept)
3783                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3784
3785         if (!vcpu->fpu_active)
3786                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3787
3788         vmcs_writel(CR0_READ_SHADOW, cr0);
3789         vmcs_writel(GUEST_CR0, hw_cr0);
3790         vcpu->arch.cr0 = cr0;
3791
3792         /* depends on vcpu->arch.cr0 to be set to a new value */
3793         vmx->emulation_required = emulation_required(vcpu);
3794 }
3795
3796 static u64 construct_eptp(unsigned long root_hpa)
3797 {
3798         u64 eptp;
3799
3800         /* TODO write the value reading from MSR */
3801         eptp = VMX_EPT_DEFAULT_MT |
3802                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3803         if (enable_ept_ad_bits)
3804                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3805         eptp |= (root_hpa & PAGE_MASK);
3806
3807         return eptp;
3808 }
3809
3810 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3811 {
3812         unsigned long guest_cr3;
3813         u64 eptp;
3814
3815         guest_cr3 = cr3;
3816         if (enable_ept) {
3817                 eptp = construct_eptp(cr3);
3818                 vmcs_write64(EPT_POINTER, eptp);
3819                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3820                         guest_cr3 = kvm_read_cr3(vcpu);
3821                 else
3822                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3823                 ept_load_pdptrs(vcpu);
3824         }
3825
3826         vmx_flush_tlb(vcpu);
3827         vmcs_writel(GUEST_CR3, guest_cr3);
3828 }
3829
3830 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3831 {
3832         /*
3833          * Pass through host's Machine Check Enable value to hw_cr4, which
3834          * is in force while we are in guest mode.  Do not let guests control
3835          * this bit, even if host CR4.MCE == 0.
3836          */
3837         unsigned long hw_cr4 =
3838                 (cr4_read_shadow() & X86_CR4_MCE) |
3839                 (cr4 & ~X86_CR4_MCE) |
3840                 (to_vmx(vcpu)->rmode.vm86_active ?
3841                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3842
3843         if (cr4 & X86_CR4_VMXE) {
3844                 /*
3845                  * To use VMXON (and later other VMX instructions), a guest
3846                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3847                  * So basically the check on whether to allow nested VMX
3848                  * is here.
3849                  */
3850                 if (!nested_vmx_allowed(vcpu))
3851                         return 1;
3852         }
3853         if (to_vmx(vcpu)->nested.vmxon &&
3854             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3855                 return 1;
3856
3857         vcpu->arch.cr4 = cr4;
3858         if (enable_ept) {
3859                 if (!is_paging(vcpu)) {
3860                         hw_cr4 &= ~X86_CR4_PAE;
3861                         hw_cr4 |= X86_CR4_PSE;
3862                 } else if (!(cr4 & X86_CR4_PAE)) {
3863                         hw_cr4 &= ~X86_CR4_PAE;
3864                 }
3865         }
3866
3867         if (!enable_unrestricted_guest && !is_paging(vcpu))
3868                 /*
3869                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3870                  * hardware.  However KVM always uses paging mode without
3871                  * unrestricted guest.
3872                  * To emulate this behavior, SMEP/SMAP needs to be manually
3873                  * disabled when guest switches to non-paging mode.
3874                  */
3875                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3876
3877         vmcs_writel(CR4_READ_SHADOW, cr4);
3878         vmcs_writel(GUEST_CR4, hw_cr4);
3879         return 0;
3880 }
3881
3882 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3883                             struct kvm_segment *var, int seg)
3884 {
3885         struct vcpu_vmx *vmx = to_vmx(vcpu);
3886         u32 ar;
3887
3888         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3889                 *var = vmx->rmode.segs[seg];
3890                 if (seg == VCPU_SREG_TR
3891                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3892                         return;
3893                 var->base = vmx_read_guest_seg_base(vmx, seg);
3894                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3895                 return;
3896         }
3897         var->base = vmx_read_guest_seg_base(vmx, seg);
3898         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3899         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3900         ar = vmx_read_guest_seg_ar(vmx, seg);
3901         var->unusable = (ar >> 16) & 1;
3902         var->type = ar & 15;
3903         var->s = (ar >> 4) & 1;
3904         var->dpl = (ar >> 5) & 3;
3905         /*
3906          * Some userspaces do not preserve unusable property. Since usable
3907          * segment has to be present according to VMX spec we can use present
3908          * property to amend userspace bug by making unusable segment always
3909          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3910          * segment as unusable.
3911          */
3912         var->present = !var->unusable;
3913         var->avl = (ar >> 12) & 1;
3914         var->l = (ar >> 13) & 1;
3915         var->db = (ar >> 14) & 1;
3916         var->g = (ar >> 15) & 1;
3917 }
3918
3919 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3920 {
3921         struct kvm_segment s;
3922
3923         if (to_vmx(vcpu)->rmode.vm86_active) {
3924                 vmx_get_segment(vcpu, &s, seg);
3925                 return s.base;
3926         }
3927         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3928 }
3929
3930 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3931 {
3932         struct vcpu_vmx *vmx = to_vmx(vcpu);
3933
3934         if (unlikely(vmx->rmode.vm86_active))
3935                 return 0;
3936         else {
3937                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3938                 return VMX_AR_DPL(ar);
3939         }
3940 }
3941
3942 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3943 {
3944         u32 ar;
3945
3946         if (var->unusable || !var->present)
3947                 ar = 1 << 16;
3948         else {
3949                 ar = var->type & 15;
3950                 ar |= (var->s & 1) << 4;
3951                 ar |= (var->dpl & 3) << 5;
3952                 ar |= (var->present & 1) << 7;
3953                 ar |= (var->avl & 1) << 12;
3954                 ar |= (var->l & 1) << 13;
3955                 ar |= (var->db & 1) << 14;
3956                 ar |= (var->g & 1) << 15;
3957         }
3958
3959         return ar;
3960 }
3961
3962 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3963                             struct kvm_segment *var, int seg)
3964 {
3965         struct vcpu_vmx *vmx = to_vmx(vcpu);
3966         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3967
3968         vmx_segment_cache_clear(vmx);
3969
3970         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3971                 vmx->rmode.segs[seg] = *var;
3972                 if (seg == VCPU_SREG_TR)
3973                         vmcs_write16(sf->selector, var->selector);
3974                 else if (var->s)
3975                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3976                 goto out;
3977         }
3978
3979         vmcs_writel(sf->base, var->base);
3980         vmcs_write32(sf->limit, var->limit);
3981         vmcs_write16(sf->selector, var->selector);
3982
3983         /*
3984          *   Fix the "Accessed" bit in AR field of segment registers for older
3985          * qemu binaries.
3986          *   IA32 arch specifies that at the time of processor reset the
3987          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3988          * is setting it to 0 in the userland code. This causes invalid guest
3989          * state vmexit when "unrestricted guest" mode is turned on.
3990          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3991          * tree. Newer qemu binaries with that qemu fix would not need this
3992          * kvm hack.
3993          */
3994         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3995                 var->type |= 0x1; /* Accessed */
3996
3997         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3998
3999 out:
4000         vmx->emulation_required = emulation_required(vcpu);
4001 }
4002
4003 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4004 {
4005         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4006
4007         *db = (ar >> 14) & 1;
4008         *l = (ar >> 13) & 1;
4009 }
4010
4011 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4012 {
4013         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4014         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4015 }
4016
4017 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4018 {
4019         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4020         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4021 }
4022
4023 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4024 {
4025         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4026         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4027 }
4028
4029 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4030 {
4031         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4032         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4033 }
4034
4035 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4036 {
4037         struct kvm_segment var;
4038         u32 ar;
4039
4040         vmx_get_segment(vcpu, &var, seg);
4041         var.dpl = 0x3;
4042         if (seg == VCPU_SREG_CS)
4043                 var.type = 0x3;
4044         ar = vmx_segment_access_rights(&var);
4045
4046         if (var.base != (var.selector << 4))
4047                 return false;
4048         if (var.limit != 0xffff)
4049                 return false;
4050         if (ar != 0xf3)
4051                 return false;
4052
4053         return true;
4054 }
4055
4056 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4057 {
4058         struct kvm_segment cs;
4059         unsigned int cs_rpl;
4060
4061         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4062         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4063
4064         if (cs.unusable)
4065                 return false;
4066         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4067                 return false;
4068         if (!cs.s)
4069                 return false;
4070         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4071                 if (cs.dpl > cs_rpl)
4072                         return false;
4073         } else {
4074                 if (cs.dpl != cs_rpl)
4075                         return false;
4076         }
4077         if (!cs.present)
4078                 return false;
4079
4080         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4081         return true;
4082 }
4083
4084 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4085 {
4086         struct kvm_segment ss;
4087         unsigned int ss_rpl;
4088
4089         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4090         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4091
4092         if (ss.unusable)
4093                 return true;
4094         if (ss.type != 3 && ss.type != 7)
4095                 return false;
4096         if (!ss.s)
4097                 return false;
4098         if (ss.dpl != ss_rpl) /* DPL != RPL */
4099                 return false;
4100         if (!ss.present)
4101                 return false;
4102
4103         return true;
4104 }
4105
4106 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4107 {
4108         struct kvm_segment var;
4109         unsigned int rpl;
4110
4111         vmx_get_segment(vcpu, &var, seg);
4112         rpl = var.selector & SEGMENT_RPL_MASK;
4113
4114         if (var.unusable)
4115                 return true;
4116         if (!var.s)
4117                 return false;
4118         if (!var.present)
4119                 return false;
4120         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4121                 if (var.dpl < rpl) /* DPL < RPL */
4122                         return false;
4123         }
4124
4125         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4126          * rights flags
4127          */
4128         return true;
4129 }
4130
4131 static bool tr_valid(struct kvm_vcpu *vcpu)
4132 {
4133         struct kvm_segment tr;
4134
4135         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4136
4137         if (tr.unusable)
4138                 return false;
4139         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4140                 return false;
4141         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4142                 return false;
4143         if (!tr.present)
4144                 return false;
4145
4146         return true;
4147 }
4148
4149 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4150 {
4151         struct kvm_segment ldtr;
4152
4153         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4154
4155         if (ldtr.unusable)
4156                 return true;
4157         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4158                 return false;
4159         if (ldtr.type != 2)
4160                 return false;
4161         if (!ldtr.present)
4162                 return false;
4163
4164         return true;
4165 }
4166
4167 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4168 {
4169         struct kvm_segment cs, ss;
4170
4171         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4172         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4173
4174         return ((cs.selector & SEGMENT_RPL_MASK) ==
4175                  (ss.selector & SEGMENT_RPL_MASK));
4176 }
4177
4178 /*
4179  * Check if guest state is valid. Returns true if valid, false if
4180  * not.
4181  * We assume that registers are always usable
4182  */
4183 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4184 {
4185         if (enable_unrestricted_guest)
4186                 return true;
4187
4188         /* real mode guest state checks */
4189         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4190                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4191                         return false;
4192                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4193                         return false;
4194                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4195                         return false;
4196                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4197                         return false;
4198                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4199                         return false;
4200                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4201                         return false;
4202         } else {
4203         /* protected mode guest state checks */
4204                 if (!cs_ss_rpl_check(vcpu))
4205                         return false;
4206                 if (!code_segment_valid(vcpu))
4207                         return false;
4208                 if (!stack_segment_valid(vcpu))
4209                         return false;
4210                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4211                         return false;
4212                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4213                         return false;
4214                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4215                         return false;
4216                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4217                         return false;
4218                 if (!tr_valid(vcpu))
4219                         return false;
4220                 if (!ldtr_valid(vcpu))
4221                         return false;
4222         }
4223         /* TODO:
4224          * - Add checks on RIP
4225          * - Add checks on RFLAGS
4226          */
4227
4228         return true;
4229 }
4230
4231 static int init_rmode_tss(struct kvm *kvm)
4232 {
4233         gfn_t fn;
4234         u16 data = 0;
4235         int idx, r;
4236
4237         idx = srcu_read_lock(&kvm->srcu);
4238         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4239         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4240         if (r < 0)
4241                 goto out;
4242         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4243         r = kvm_write_guest_page(kvm, fn++, &data,
4244                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4245         if (r < 0)
4246                 goto out;
4247         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4248         if (r < 0)
4249                 goto out;
4250         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4251         if (r < 0)
4252                 goto out;
4253         data = ~0;
4254         r = kvm_write_guest_page(kvm, fn, &data,
4255                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4256                                  sizeof(u8));
4257 out:
4258         srcu_read_unlock(&kvm->srcu, idx);
4259         return r;
4260 }
4261
4262 static int init_rmode_identity_map(struct kvm *kvm)
4263 {
4264         int i, idx, r = 0;
4265         kvm_pfn_t identity_map_pfn;
4266         u32 tmp;
4267
4268         if (!enable_ept)
4269                 return 0;
4270
4271         /* Protect kvm->arch.ept_identity_pagetable_done. */
4272         mutex_lock(&kvm->slots_lock);
4273
4274         if (likely(kvm->arch.ept_identity_pagetable_done))
4275                 goto out2;
4276
4277         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4278
4279         r = alloc_identity_pagetable(kvm);
4280         if (r < 0)
4281                 goto out2;
4282
4283         idx = srcu_read_lock(&kvm->srcu);
4284         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4285         if (r < 0)
4286                 goto out;
4287         /* Set up identity-mapping pagetable for EPT in real mode */
4288         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4289                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4290                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4291                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4292                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4293                 if (r < 0)
4294                         goto out;
4295         }
4296         kvm->arch.ept_identity_pagetable_done = true;
4297
4298 out:
4299         srcu_read_unlock(&kvm->srcu, idx);
4300
4301 out2:
4302         mutex_unlock(&kvm->slots_lock);
4303         return r;
4304 }
4305
4306 static void seg_setup(int seg)
4307 {
4308         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4309         unsigned int ar;
4310
4311         vmcs_write16(sf->selector, 0);
4312         vmcs_writel(sf->base, 0);
4313         vmcs_write32(sf->limit, 0xffff);
4314         ar = 0x93;
4315         if (seg == VCPU_SREG_CS)
4316                 ar |= 0x08; /* code segment */
4317
4318         vmcs_write32(sf->ar_bytes, ar);
4319 }
4320
4321 static int alloc_apic_access_page(struct kvm *kvm)
4322 {
4323         struct page *page;
4324         int r = 0;
4325
4326         mutex_lock(&kvm->slots_lock);
4327         if (kvm->arch.apic_access_page_done)
4328                 goto out;
4329         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4330                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4331         if (r)
4332                 goto out;
4333
4334         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4335         if (is_error_page(page)) {
4336                 r = -EFAULT;
4337                 goto out;
4338         }
4339
4340         /*
4341          * Do not pin the page in memory, so that memory hot-unplug
4342          * is able to migrate it.
4343          */
4344         put_page(page);
4345         kvm->arch.apic_access_page_done = true;
4346 out:
4347         mutex_unlock(&kvm->slots_lock);
4348         return r;
4349 }
4350
4351 static int alloc_identity_pagetable(struct kvm *kvm)
4352 {
4353         /* Called with kvm->slots_lock held. */
4354
4355         int r = 0;
4356
4357         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4358
4359         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4360                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4361
4362         return r;
4363 }
4364
4365 static int allocate_vpid(void)
4366 {
4367         int vpid;
4368
4369         if (!enable_vpid)
4370                 return 0;
4371         spin_lock(&vmx_vpid_lock);
4372         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4373         if (vpid < VMX_NR_VPIDS)
4374                 __set_bit(vpid, vmx_vpid_bitmap);
4375         else
4376                 vpid = 0;
4377         spin_unlock(&vmx_vpid_lock);
4378         return vpid;
4379 }
4380
4381 static void free_vpid(int vpid)
4382 {
4383         if (!enable_vpid || vpid == 0)
4384                 return;
4385         spin_lock(&vmx_vpid_lock);
4386         __clear_bit(vpid, vmx_vpid_bitmap);
4387         spin_unlock(&vmx_vpid_lock);
4388 }
4389
4390 #define MSR_TYPE_R      1
4391 #define MSR_TYPE_W      2
4392 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4393                                                 u32 msr, int type)
4394 {
4395         int f = sizeof(unsigned long);
4396
4397         if (!cpu_has_vmx_msr_bitmap())
4398                 return;
4399
4400         /*
4401          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4402          * have the write-low and read-high bitmap offsets the wrong way round.
4403          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4404          */
4405         if (msr <= 0x1fff) {
4406                 if (type & MSR_TYPE_R)
4407                         /* read-low */
4408                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4409
4410                 if (type & MSR_TYPE_W)
4411                         /* write-low */
4412                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4413
4414         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4415                 msr &= 0x1fff;
4416                 if (type & MSR_TYPE_R)
4417                         /* read-high */
4418                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4419
4420                 if (type & MSR_TYPE_W)
4421                         /* write-high */
4422                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4423
4424         }
4425 }
4426
4427 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4428                                                 u32 msr, int type)
4429 {
4430         int f = sizeof(unsigned long);
4431
4432         if (!cpu_has_vmx_msr_bitmap())
4433                 return;
4434
4435         /*
4436          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4437          * have the write-low and read-high bitmap offsets the wrong way round.
4438          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4439          */
4440         if (msr <= 0x1fff) {
4441                 if (type & MSR_TYPE_R)
4442                         /* read-low */
4443                         __set_bit(msr, msr_bitmap + 0x000 / f);
4444
4445                 if (type & MSR_TYPE_W)
4446                         /* write-low */
4447                         __set_bit(msr, msr_bitmap + 0x800 / f);
4448
4449         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4450                 msr &= 0x1fff;
4451                 if (type & MSR_TYPE_R)
4452                         /* read-high */
4453                         __set_bit(msr, msr_bitmap + 0x400 / f);
4454
4455                 if (type & MSR_TYPE_W)
4456                         /* write-high */
4457                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4458
4459         }
4460 }
4461
4462 /*
4463  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4464  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4465  */
4466 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4467                                                unsigned long *msr_bitmap_nested,
4468                                                u32 msr, int type)
4469 {
4470         int f = sizeof(unsigned long);
4471
4472         if (!cpu_has_vmx_msr_bitmap()) {
4473                 WARN_ON(1);
4474                 return;
4475         }
4476
4477         /*
4478          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4479          * have the write-low and read-high bitmap offsets the wrong way round.
4480          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4481          */
4482         if (msr <= 0x1fff) {
4483                 if (type & MSR_TYPE_R &&
4484                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4485                         /* read-low */
4486                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4487
4488                 if (type & MSR_TYPE_W &&
4489                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4490                         /* write-low */
4491                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4492
4493         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4494                 msr &= 0x1fff;
4495                 if (type & MSR_TYPE_R &&
4496                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4497                         /* read-high */
4498                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4499
4500                 if (type & MSR_TYPE_W &&
4501                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4502                         /* write-high */
4503                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4504
4505         }
4506 }
4507
4508 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4509 {
4510         if (!longmode_only)
4511                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4512                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4513         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4514                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4515 }
4516
4517 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4518 {
4519         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4520                         msr, MSR_TYPE_R);
4521         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4522                         msr, MSR_TYPE_R);
4523 }
4524
4525 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4526 {
4527         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4528                         msr, MSR_TYPE_R);
4529         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4530                         msr, MSR_TYPE_R);
4531 }
4532
4533 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4534 {
4535         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4536                         msr, MSR_TYPE_W);
4537         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4538                         msr, MSR_TYPE_W);
4539 }
4540
4541 static bool vmx_get_enable_apicv(void)
4542 {
4543         return enable_apicv;
4544 }
4545
4546 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4547 {
4548         struct vcpu_vmx *vmx = to_vmx(vcpu);
4549         int max_irr;
4550         void *vapic_page;
4551         u16 status;
4552
4553         if (vmx->nested.pi_desc &&
4554             vmx->nested.pi_pending) {
4555                 vmx->nested.pi_pending = false;
4556                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4557                         return 0;
4558
4559                 max_irr = find_last_bit(
4560                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4561
4562                 if (max_irr == 256)
4563                         return 0;
4564
4565                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4566                 if (!vapic_page) {
4567                         WARN_ON(1);
4568                         return -ENOMEM;
4569                 }
4570                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4571                 kunmap(vmx->nested.virtual_apic_page);
4572
4573                 status = vmcs_read16(GUEST_INTR_STATUS);
4574                 if ((u8)max_irr > ((u8)status & 0xff)) {
4575                         status &= ~0xff;
4576                         status |= (u8)max_irr;
4577                         vmcs_write16(GUEST_INTR_STATUS, status);
4578                 }
4579         }
4580         return 0;
4581 }
4582
4583 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4584 {
4585 #ifdef CONFIG_SMP
4586         if (vcpu->mode == IN_GUEST_MODE) {
4587                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4588
4589                 /*
4590                  * Currently, we don't support urgent interrupt,
4591                  * all interrupts are recognized as non-urgent
4592                  * interrupt, so we cannot post interrupts when
4593                  * 'SN' is set.
4594                  *
4595                  * If the vcpu is in guest mode, it means it is
4596                  * running instead of being scheduled out and
4597                  * waiting in the run queue, and that's the only
4598                  * case when 'SN' is set currently, warning if
4599                  * 'SN' is set.
4600                  */
4601                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4602
4603                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4604                                 POSTED_INTR_VECTOR);
4605                 return true;
4606         }
4607 #endif
4608         return false;
4609 }
4610
4611 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4612                                                 int vector)
4613 {
4614         struct vcpu_vmx *vmx = to_vmx(vcpu);
4615
4616         if (is_guest_mode(vcpu) &&
4617             vector == vmx->nested.posted_intr_nv) {
4618                 /* the PIR and ON have been set by L1. */
4619                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4620                 /*
4621                  * If a posted intr is not recognized by hardware,
4622                  * we will accomplish it in the next vmentry.
4623                  */
4624                 vmx->nested.pi_pending = true;
4625                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4626                 return 0;
4627         }
4628         return -1;
4629 }
4630 /*
4631  * Send interrupt to vcpu via posted interrupt way.
4632  * 1. If target vcpu is running(non-root mode), send posted interrupt
4633  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4634  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4635  * interrupt from PIR in next vmentry.
4636  */
4637 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4638 {
4639         struct vcpu_vmx *vmx = to_vmx(vcpu);
4640         int r;
4641
4642         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4643         if (!r)
4644                 return;
4645
4646         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4647                 return;
4648
4649         r = pi_test_and_set_on(&vmx->pi_desc);
4650         kvm_make_request(KVM_REQ_EVENT, vcpu);
4651         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4652                 kvm_vcpu_kick(vcpu);
4653 }
4654
4655 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4656 {
4657         struct vcpu_vmx *vmx = to_vmx(vcpu);
4658
4659         if (!pi_test_and_clear_on(&vmx->pi_desc))
4660                 return;
4661
4662         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4663 }
4664
4665 /*
4666  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4667  * will not change in the lifetime of the guest.
4668  * Note that host-state that does change is set elsewhere. E.g., host-state
4669  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4670  */
4671 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4672 {
4673         u32 low32, high32;
4674         unsigned long tmpl;
4675         struct desc_ptr dt;
4676         unsigned long cr4;
4677
4678         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4679         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4680
4681         /* Save the most likely value for this task's CR4 in the VMCS. */
4682         cr4 = cr4_read_shadow();
4683         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4684         vmx->host_state.vmcs_host_cr4 = cr4;
4685
4686         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4687 #ifdef CONFIG_X86_64
4688         /*
4689          * Load null selectors, so we can avoid reloading them in
4690          * __vmx_load_host_state(), in case userspace uses the null selectors
4691          * too (the expected case).
4692          */
4693         vmcs_write16(HOST_DS_SELECTOR, 0);
4694         vmcs_write16(HOST_ES_SELECTOR, 0);
4695 #else
4696         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4697         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4698 #endif
4699         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4700         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4701
4702         native_store_idt(&dt);
4703         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4704         vmx->host_idt_base = dt.address;
4705
4706         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4707
4708         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4709         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4710         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4711         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4712
4713         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4714                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4715                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4716         }
4717 }
4718
4719 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4720 {
4721         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4722         if (enable_ept)
4723                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4724         if (is_guest_mode(&vmx->vcpu))
4725                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4726                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4727         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4728 }
4729
4730 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4731 {
4732         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4733
4734         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4735                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4736         return pin_based_exec_ctrl;
4737 }
4738
4739 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4740 {
4741         struct vcpu_vmx *vmx = to_vmx(vcpu);
4742
4743         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4744 }
4745
4746 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4747 {
4748         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4749
4750         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4751                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4752
4753         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4754                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4755 #ifdef CONFIG_X86_64
4756                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4757                                 CPU_BASED_CR8_LOAD_EXITING;
4758 #endif
4759         }
4760         if (!enable_ept)
4761                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4762                                 CPU_BASED_CR3_LOAD_EXITING  |
4763                                 CPU_BASED_INVLPG_EXITING;
4764         return exec_control;
4765 }
4766
4767 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4768 {
4769         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4770         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4771                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4772         if (vmx->vpid == 0)
4773                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4774         if (!enable_ept) {
4775                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4776                 enable_unrestricted_guest = 0;
4777                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4778                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4779         }
4780         if (!enable_unrestricted_guest)
4781                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4782         if (!ple_gap)
4783                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4784         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4785                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4786                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4787         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4788         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4789            (handle_vmptrld).
4790            We can NOT enable shadow_vmcs here because we don't have yet
4791            a current VMCS12
4792         */
4793         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4794
4795         if (!enable_pml)
4796                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4797
4798         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4799         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4800
4801         return exec_control;
4802 }
4803
4804 static void ept_set_mmio_spte_mask(void)
4805 {
4806         /*
4807          * EPT Misconfigurations can be generated if the value of bits 2:0
4808          * of an EPT paging-structure entry is 110b (write/execute).
4809          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4810          * spte.
4811          */
4812         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4813 }
4814
4815 #define VMX_XSS_EXIT_BITMAP 0
4816 /*
4817  * Sets up the vmcs for emulated real mode.
4818  */
4819 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4820 {
4821 #ifdef CONFIG_X86_64
4822         unsigned long a;
4823 #endif
4824         int i;
4825
4826         /* I/O */
4827         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4828         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4829
4830         if (enable_shadow_vmcs) {
4831                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4832                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4833         }
4834         if (cpu_has_vmx_msr_bitmap())
4835                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4836
4837         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4838
4839         /* Control */
4840         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4841
4842         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4843
4844         if (cpu_has_secondary_exec_ctrls())
4845                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4846                                 vmx_secondary_exec_control(vmx));
4847
4848         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4849                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4850                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4851                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4852                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4853
4854                 vmcs_write16(GUEST_INTR_STATUS, 0);
4855
4856                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4857                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4858         }
4859
4860         if (ple_gap) {
4861                 vmcs_write32(PLE_GAP, ple_gap);
4862                 vmx->ple_window = ple_window;
4863                 vmx->ple_window_dirty = true;
4864         }
4865
4866         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4867         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4868         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4869
4870         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4871         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4872         vmx_set_constant_host_state(vmx);
4873 #ifdef CONFIG_X86_64
4874         rdmsrl(MSR_FS_BASE, a);
4875         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4876         rdmsrl(MSR_GS_BASE, a);
4877         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4878 #else
4879         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4880         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4881 #endif
4882
4883         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4884         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4885         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4886         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4887         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4888
4889         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4890                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4891
4892         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4893                 u32 index = vmx_msr_index[i];
4894                 u32 data_low, data_high;
4895                 int j = vmx->nmsrs;
4896
4897                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4898                         continue;
4899                 if (wrmsr_safe(index, data_low, data_high) < 0)
4900                         continue;
4901                 vmx->guest_msrs[j].index = i;
4902                 vmx->guest_msrs[j].data = 0;
4903                 vmx->guest_msrs[j].mask = -1ull;
4904                 ++vmx->nmsrs;
4905         }
4906
4907
4908         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4909
4910         /* 22.2.1, 20.8.1 */
4911         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4912
4913         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4914         set_cr4_guest_host_mask(vmx);
4915
4916         if (vmx_xsaves_supported())
4917                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4918
4919         return 0;
4920 }
4921
4922 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4923 {
4924         struct vcpu_vmx *vmx = to_vmx(vcpu);
4925         struct msr_data apic_base_msr;
4926         u64 cr0;
4927
4928         vmx->rmode.vm86_active = 0;
4929
4930         vmx->soft_vnmi_blocked = 0;
4931
4932         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4933         kvm_set_cr8(vcpu, 0);
4934
4935         if (!init_event) {
4936                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4937                                      MSR_IA32_APICBASE_ENABLE;
4938                 if (kvm_vcpu_is_reset_bsp(vcpu))
4939                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4940                 apic_base_msr.host_initiated = true;
4941                 kvm_set_apic_base(vcpu, &apic_base_msr);
4942         }
4943
4944         vmx_segment_cache_clear(vmx);
4945
4946         seg_setup(VCPU_SREG_CS);
4947         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4948         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4949
4950         seg_setup(VCPU_SREG_DS);
4951         seg_setup(VCPU_SREG_ES);
4952         seg_setup(VCPU_SREG_FS);
4953         seg_setup(VCPU_SREG_GS);
4954         seg_setup(VCPU_SREG_SS);
4955
4956         vmcs_write16(GUEST_TR_SELECTOR, 0);
4957         vmcs_writel(GUEST_TR_BASE, 0);
4958         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4959         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4960
4961         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4962         vmcs_writel(GUEST_LDTR_BASE, 0);
4963         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4964         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4965
4966         if (!init_event) {
4967                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4968                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4969                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4970                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4971         }
4972
4973         vmcs_writel(GUEST_RFLAGS, 0x02);
4974         kvm_rip_write(vcpu, 0xfff0);
4975
4976         vmcs_writel(GUEST_GDTR_BASE, 0);
4977         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4978
4979         vmcs_writel(GUEST_IDTR_BASE, 0);
4980         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4981
4982         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4983         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4984         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4985
4986         setup_msrs(vmx);
4987
4988         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4989
4990         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4991                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4992                 if (cpu_need_tpr_shadow(vcpu))
4993                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4994                                      __pa(vcpu->arch.apic->regs));
4995                 vmcs_write32(TPR_THRESHOLD, 0);
4996         }
4997
4998         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4999
5000         if (kvm_vcpu_apicv_active(vcpu))
5001                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5002
5003         if (vmx->vpid != 0)
5004                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5005
5006         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5007         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5008         vmx->vcpu.arch.cr0 = cr0;
5009         vmx_set_cr4(vcpu, 0);
5010         vmx_set_efer(vcpu, 0);
5011         vmx_fpu_activate(vcpu);
5012         update_exception_bitmap(vcpu);
5013
5014         vpid_sync_context(vmx->vpid);
5015 }
5016
5017 /*
5018  * In nested virtualization, check if L1 asked to exit on external interrupts.
5019  * For most existing hypervisors, this will always return true.
5020  */
5021 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5022 {
5023         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5024                 PIN_BASED_EXT_INTR_MASK;
5025 }
5026
5027 /*
5028  * In nested virtualization, check if L1 has set
5029  * VM_EXIT_ACK_INTR_ON_EXIT
5030  */
5031 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5032 {
5033         return get_vmcs12(vcpu)->vm_exit_controls &
5034                 VM_EXIT_ACK_INTR_ON_EXIT;
5035 }
5036
5037 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5038 {
5039         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5040                 PIN_BASED_NMI_EXITING;
5041 }
5042
5043 static void enable_irq_window(struct kvm_vcpu *vcpu)
5044 {
5045         u32 cpu_based_vm_exec_control;
5046
5047         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5048         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5049         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5050 }
5051
5052 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5053 {
5054         u32 cpu_based_vm_exec_control;
5055
5056         if (!cpu_has_virtual_nmis() ||
5057             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5058                 enable_irq_window(vcpu);
5059                 return;
5060         }
5061
5062         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5063         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5064         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5065 }
5066
5067 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5068 {
5069         struct vcpu_vmx *vmx = to_vmx(vcpu);
5070         uint32_t intr;
5071         int irq = vcpu->arch.interrupt.nr;
5072
5073         trace_kvm_inj_virq(irq);
5074
5075         ++vcpu->stat.irq_injections;
5076         if (vmx->rmode.vm86_active) {
5077                 int inc_eip = 0;
5078                 if (vcpu->arch.interrupt.soft)
5079                         inc_eip = vcpu->arch.event_exit_inst_len;
5080                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5081                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5082                 return;
5083         }
5084         intr = irq | INTR_INFO_VALID_MASK;
5085         if (vcpu->arch.interrupt.soft) {
5086                 intr |= INTR_TYPE_SOFT_INTR;
5087                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5088                              vmx->vcpu.arch.event_exit_inst_len);
5089         } else
5090                 intr |= INTR_TYPE_EXT_INTR;
5091         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5092 }
5093
5094 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5095 {
5096         struct vcpu_vmx *vmx = to_vmx(vcpu);
5097
5098         if (is_guest_mode(vcpu))
5099                 return;
5100
5101         if (!cpu_has_virtual_nmis()) {
5102                 /*
5103                  * Tracking the NMI-blocked state in software is built upon
5104                  * finding the next open IRQ window. This, in turn, depends on
5105                  * well-behaving guests: They have to keep IRQs disabled at
5106                  * least as long as the NMI handler runs. Otherwise we may
5107                  * cause NMI nesting, maybe breaking the guest. But as this is
5108                  * highly unlikely, we can live with the residual risk.
5109                  */
5110                 vmx->soft_vnmi_blocked = 1;
5111                 vmx->vnmi_blocked_time = 0;
5112         }
5113
5114         ++vcpu->stat.nmi_injections;
5115         vmx->nmi_known_unmasked = false;
5116         if (vmx->rmode.vm86_active) {
5117                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5118                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5119                 return;
5120         }
5121         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5122                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5123 }
5124
5125 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5126 {
5127         if (!cpu_has_virtual_nmis())
5128                 return to_vmx(vcpu)->soft_vnmi_blocked;
5129         if (to_vmx(vcpu)->nmi_known_unmasked)
5130                 return false;
5131         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5132 }
5133
5134 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5135 {
5136         struct vcpu_vmx *vmx = to_vmx(vcpu);
5137
5138         if (!cpu_has_virtual_nmis()) {
5139                 if (vmx->soft_vnmi_blocked != masked) {
5140                         vmx->soft_vnmi_blocked = masked;
5141                         vmx->vnmi_blocked_time = 0;
5142                 }
5143         } else {
5144                 vmx->nmi_known_unmasked = !masked;
5145                 if (masked)
5146                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5147                                       GUEST_INTR_STATE_NMI);
5148                 else
5149                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5150                                         GUEST_INTR_STATE_NMI);
5151         }
5152 }
5153
5154 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5155 {
5156         if (to_vmx(vcpu)->nested.nested_run_pending)
5157                 return 0;
5158
5159         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5160                 return 0;
5161
5162         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5163                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5164                    | GUEST_INTR_STATE_NMI));
5165 }
5166
5167 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5168 {
5169         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5170                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5171                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5172                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5173 }
5174
5175 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5176 {
5177         int ret;
5178
5179         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5180                                     PAGE_SIZE * 3);
5181         if (ret)
5182                 return ret;
5183         kvm->arch.tss_addr = addr;
5184         return init_rmode_tss(kvm);
5185 }
5186
5187 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5188 {
5189         switch (vec) {
5190         case BP_VECTOR:
5191                 /*
5192                  * Update instruction length as we may reinject the exception
5193                  * from user space while in guest debugging mode.
5194                  */
5195                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5196                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5197                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5198                         return false;
5199                 /* fall through */
5200         case DB_VECTOR:
5201                 if (vcpu->guest_debug &
5202                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5203                         return false;
5204                 /* fall through */
5205         case DE_VECTOR:
5206         case OF_VECTOR:
5207         case BR_VECTOR:
5208         case UD_VECTOR:
5209         case DF_VECTOR:
5210         case SS_VECTOR:
5211         case GP_VECTOR:
5212         case MF_VECTOR:
5213                 return true;
5214         break;
5215         }
5216         return false;
5217 }
5218
5219 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5220                                   int vec, u32 err_code)
5221 {
5222         /*
5223          * Instruction with address size override prefix opcode 0x67
5224          * Cause the #SS fault with 0 error code in VM86 mode.
5225          */
5226         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5227                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5228                         if (vcpu->arch.halt_request) {
5229                                 vcpu->arch.halt_request = 0;
5230                                 return kvm_vcpu_halt(vcpu);
5231                         }
5232                         return 1;
5233                 }
5234                 return 0;
5235         }
5236
5237         /*
5238          * Forward all other exceptions that are valid in real mode.
5239          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5240          *        the required debugging infrastructure rework.
5241          */
5242         kvm_queue_exception(vcpu, vec);
5243         return 1;
5244 }
5245
5246 /*
5247  * Trigger machine check on the host. We assume all the MSRs are already set up
5248  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5249  * We pass a fake environment to the machine check handler because we want
5250  * the guest to be always treated like user space, no matter what context
5251  * it used internally.
5252  */
5253 static void kvm_machine_check(void)
5254 {
5255 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5256         struct pt_regs regs = {
5257                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5258                 .flags = X86_EFLAGS_IF,
5259         };
5260
5261         do_machine_check(&regs, 0);
5262 #endif
5263 }
5264
5265 static int handle_machine_check(struct kvm_vcpu *vcpu)
5266 {
5267         /* already handled by vcpu_run */
5268         return 1;
5269 }
5270
5271 static int handle_exception(struct kvm_vcpu *vcpu)
5272 {
5273         struct vcpu_vmx *vmx = to_vmx(vcpu);
5274         struct kvm_run *kvm_run = vcpu->run;
5275         u32 intr_info, ex_no, error_code;
5276         unsigned long cr2, rip, dr6;
5277         u32 vect_info;
5278         enum emulation_result er;
5279
5280         vect_info = vmx->idt_vectoring_info;
5281         intr_info = vmx->exit_intr_info;
5282
5283         if (is_machine_check(intr_info))
5284                 return handle_machine_check(vcpu);
5285
5286         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5287                 return 1;  /* already handled by vmx_vcpu_run() */
5288
5289         if (is_no_device(intr_info)) {
5290                 vmx_fpu_activate(vcpu);
5291                 return 1;
5292         }
5293
5294         if (is_invalid_opcode(intr_info)) {
5295                 if (is_guest_mode(vcpu)) {
5296                         kvm_queue_exception(vcpu, UD_VECTOR);
5297                         return 1;
5298                 }
5299                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5300                 if (er != EMULATE_DONE)
5301                         kvm_queue_exception(vcpu, UD_VECTOR);
5302                 return 1;
5303         }
5304
5305         error_code = 0;
5306         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5307                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5308
5309         /*
5310          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5311          * MMIO, it is better to report an internal error.
5312          * See the comments in vmx_handle_exit.
5313          */
5314         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5315             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5316                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5317                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5318                 vcpu->run->internal.ndata = 3;
5319                 vcpu->run->internal.data[0] = vect_info;
5320                 vcpu->run->internal.data[1] = intr_info;
5321                 vcpu->run->internal.data[2] = error_code;
5322                 return 0;
5323         }
5324
5325         if (is_page_fault(intr_info)) {
5326                 /* EPT won't cause page fault directly */
5327                 BUG_ON(enable_ept);
5328                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5329                 trace_kvm_page_fault(cr2, error_code);
5330
5331                 if (kvm_event_needs_reinjection(vcpu))
5332                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5333                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5334         }
5335
5336         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5337
5338         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5339                 return handle_rmode_exception(vcpu, ex_no, error_code);
5340
5341         switch (ex_no) {
5342         case AC_VECTOR:
5343                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5344                 return 1;
5345         case DB_VECTOR:
5346                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5347                 if (!(vcpu->guest_debug &
5348                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5349                         vcpu->arch.dr6 &= ~15;
5350                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5351                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5352                                 skip_emulated_instruction(vcpu);
5353
5354                         kvm_queue_exception(vcpu, DB_VECTOR);
5355                         return 1;
5356                 }
5357                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5358                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5359                 /* fall through */
5360         case BP_VECTOR:
5361                 /*
5362                  * Update instruction length as we may reinject #BP from
5363                  * user space while in guest debugging mode. Reading it for
5364                  * #DB as well causes no harm, it is not used in that case.
5365                  */
5366                 vmx->vcpu.arch.event_exit_inst_len =
5367                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5368                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5369                 rip = kvm_rip_read(vcpu);
5370                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5371                 kvm_run->debug.arch.exception = ex_no;
5372                 break;
5373         default:
5374                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5375                 kvm_run->ex.exception = ex_no;
5376                 kvm_run->ex.error_code = error_code;
5377                 break;
5378         }
5379         return 0;
5380 }
5381
5382 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5383 {
5384         ++vcpu->stat.irq_exits;
5385         return 1;
5386 }
5387
5388 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5389 {
5390         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5391         return 0;
5392 }
5393
5394 static int handle_io(struct kvm_vcpu *vcpu)
5395 {
5396         unsigned long exit_qualification;
5397         int size, in, string;
5398         unsigned port;
5399
5400         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5401         string = (exit_qualification & 16) != 0;
5402         in = (exit_qualification & 8) != 0;
5403
5404         ++vcpu->stat.io_exits;
5405
5406         if (string || in)
5407                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5408
5409         port = exit_qualification >> 16;
5410         size = (exit_qualification & 7) + 1;
5411         skip_emulated_instruction(vcpu);
5412
5413         return kvm_fast_pio_out(vcpu, size, port);
5414 }
5415
5416 static void
5417 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5418 {
5419         /*
5420          * Patch in the VMCALL instruction:
5421          */
5422         hypercall[0] = 0x0f;
5423         hypercall[1] = 0x01;
5424         hypercall[2] = 0xc1;
5425 }
5426
5427 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5428 {
5429         unsigned long always_on = VMXON_CR0_ALWAYSON;
5430         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5431
5432         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5433                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5434             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5435                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5436         return (val & always_on) == always_on;
5437 }
5438
5439 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5440 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5441 {
5442         if (is_guest_mode(vcpu)) {
5443                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5444                 unsigned long orig_val = val;
5445
5446                 /*
5447                  * We get here when L2 changed cr0 in a way that did not change
5448                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5449                  * but did change L0 shadowed bits. So we first calculate the
5450                  * effective cr0 value that L1 would like to write into the
5451                  * hardware. It consists of the L2-owned bits from the new
5452                  * value combined with the L1-owned bits from L1's guest_cr0.
5453                  */
5454                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5455                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5456
5457                 if (!nested_cr0_valid(vcpu, val))
5458                         return 1;
5459
5460                 if (kvm_set_cr0(vcpu, val))
5461                         return 1;
5462                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5463                 return 0;
5464         } else {
5465                 if (to_vmx(vcpu)->nested.vmxon &&
5466                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5467                         return 1;
5468                 return kvm_set_cr0(vcpu, val);
5469         }
5470 }
5471
5472 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5473 {
5474         if (is_guest_mode(vcpu)) {
5475                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5476                 unsigned long orig_val = val;
5477
5478                 /* analogously to handle_set_cr0 */
5479                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5480                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5481                 if (kvm_set_cr4(vcpu, val))
5482                         return 1;
5483                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5484                 return 0;
5485         } else
5486                 return kvm_set_cr4(vcpu, val);
5487 }
5488
5489 /* called to set cr0 as approriate for clts instruction exit. */
5490 static void handle_clts(struct kvm_vcpu *vcpu)
5491 {
5492         if (is_guest_mode(vcpu)) {
5493                 /*
5494                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5495                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5496                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5497                  */
5498                 vmcs_writel(CR0_READ_SHADOW,
5499                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5500                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5501         } else
5502                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5503 }
5504
5505 static int handle_cr(struct kvm_vcpu *vcpu)
5506 {
5507         unsigned long exit_qualification, val;
5508         int cr;
5509         int reg;
5510         int err;
5511
5512         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5513         cr = exit_qualification & 15;
5514         reg = (exit_qualification >> 8) & 15;
5515         switch ((exit_qualification >> 4) & 3) {
5516         case 0: /* mov to cr */
5517                 val = kvm_register_readl(vcpu, reg);
5518                 trace_kvm_cr_write(cr, val);
5519                 switch (cr) {
5520                 case 0:
5521                         err = handle_set_cr0(vcpu, val);
5522                         kvm_complete_insn_gp(vcpu, err);
5523                         return 1;
5524                 case 3:
5525                         err = kvm_set_cr3(vcpu, val);
5526                         kvm_complete_insn_gp(vcpu, err);
5527                         return 1;
5528                 case 4:
5529                         err = handle_set_cr4(vcpu, val);
5530                         kvm_complete_insn_gp(vcpu, err);
5531                         return 1;
5532                 case 8: {
5533                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5534                                 u8 cr8 = (u8)val;
5535                                 err = kvm_set_cr8(vcpu, cr8);
5536                                 kvm_complete_insn_gp(vcpu, err);
5537                                 if (lapic_in_kernel(vcpu))
5538                                         return 1;
5539                                 if (cr8_prev <= cr8)
5540                                         return 1;
5541                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5542                                 return 0;
5543                         }
5544                 }
5545                 break;
5546         case 2: /* clts */
5547                 handle_clts(vcpu);
5548                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5549                 skip_emulated_instruction(vcpu);
5550                 vmx_fpu_activate(vcpu);
5551                 return 1;
5552         case 1: /*mov from cr*/
5553                 switch (cr) {
5554                 case 3:
5555                         val = kvm_read_cr3(vcpu);
5556                         kvm_register_write(vcpu, reg, val);
5557                         trace_kvm_cr_read(cr, val);
5558                         skip_emulated_instruction(vcpu);
5559                         return 1;
5560                 case 8:
5561                         val = kvm_get_cr8(vcpu);
5562                         kvm_register_write(vcpu, reg, val);
5563                         trace_kvm_cr_read(cr, val);
5564                         skip_emulated_instruction(vcpu);
5565                         return 1;
5566                 }
5567                 break;
5568         case 3: /* lmsw */
5569                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5570                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5571                 kvm_lmsw(vcpu, val);
5572
5573                 skip_emulated_instruction(vcpu);
5574                 return 1;
5575         default:
5576                 break;
5577         }
5578         vcpu->run->exit_reason = 0;
5579         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5580                (int)(exit_qualification >> 4) & 3, cr);
5581         return 0;
5582 }
5583
5584 static int handle_dr(struct kvm_vcpu *vcpu)
5585 {
5586         unsigned long exit_qualification;
5587         int dr, dr7, reg;
5588
5589         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5590         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5591
5592         /* First, if DR does not exist, trigger UD */
5593         if (!kvm_require_dr(vcpu, dr))
5594                 return 1;
5595
5596         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5597         if (!kvm_require_cpl(vcpu, 0))
5598                 return 1;
5599         dr7 = vmcs_readl(GUEST_DR7);
5600         if (dr7 & DR7_GD) {
5601                 /*
5602                  * As the vm-exit takes precedence over the debug trap, we
5603                  * need to emulate the latter, either for the host or the
5604                  * guest debugging itself.
5605                  */
5606                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5607                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5608                         vcpu->run->debug.arch.dr7 = dr7;
5609                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5610                         vcpu->run->debug.arch.exception = DB_VECTOR;
5611                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5612                         return 0;
5613                 } else {
5614                         vcpu->arch.dr6 &= ~15;
5615                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5616                         kvm_queue_exception(vcpu, DB_VECTOR);
5617                         return 1;
5618                 }
5619         }
5620
5621         if (vcpu->guest_debug == 0) {
5622                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5623                                 CPU_BASED_MOV_DR_EXITING);
5624
5625                 /*
5626                  * No more DR vmexits; force a reload of the debug registers
5627                  * and reenter on this instruction.  The next vmexit will
5628                  * retrieve the full state of the debug registers.
5629                  */
5630                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5631                 return 1;
5632         }
5633
5634         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5635         if (exit_qualification & TYPE_MOV_FROM_DR) {
5636                 unsigned long val;
5637
5638                 if (kvm_get_dr(vcpu, dr, &val))
5639                         return 1;
5640                 kvm_register_write(vcpu, reg, val);
5641         } else
5642                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5643                         return 1;
5644
5645         skip_emulated_instruction(vcpu);
5646         return 1;
5647 }
5648
5649 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5650 {
5651         return vcpu->arch.dr6;
5652 }
5653
5654 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5655 {
5656 }
5657
5658 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5659 {
5660         get_debugreg(vcpu->arch.db[0], 0);
5661         get_debugreg(vcpu->arch.db[1], 1);
5662         get_debugreg(vcpu->arch.db[2], 2);
5663         get_debugreg(vcpu->arch.db[3], 3);
5664         get_debugreg(vcpu->arch.dr6, 6);
5665         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5666
5667         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5668         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5669 }
5670
5671 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5672 {
5673         vmcs_writel(GUEST_DR7, val);
5674 }
5675
5676 static int handle_cpuid(struct kvm_vcpu *vcpu)
5677 {
5678         kvm_emulate_cpuid(vcpu);
5679         return 1;
5680 }
5681
5682 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5683 {
5684         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5685         struct msr_data msr_info;
5686
5687         msr_info.index = ecx;
5688         msr_info.host_initiated = false;
5689         if (vmx_get_msr(vcpu, &msr_info)) {
5690                 trace_kvm_msr_read_ex(ecx);
5691                 kvm_inject_gp(vcpu, 0);
5692                 return 1;
5693         }
5694
5695         trace_kvm_msr_read(ecx, msr_info.data);
5696
5697         /* FIXME: handling of bits 32:63 of rax, rdx */
5698         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5699         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5700         skip_emulated_instruction(vcpu);
5701         return 1;
5702 }
5703
5704 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5705 {
5706         struct msr_data msr;
5707         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5708         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5709                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5710
5711         msr.data = data;
5712         msr.index = ecx;
5713         msr.host_initiated = false;
5714         if (kvm_set_msr(vcpu, &msr) != 0) {
5715                 trace_kvm_msr_write_ex(ecx, data);
5716                 kvm_inject_gp(vcpu, 0);
5717                 return 1;
5718         }
5719
5720         trace_kvm_msr_write(ecx, data);
5721         skip_emulated_instruction(vcpu);
5722         return 1;
5723 }
5724
5725 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5726 {
5727         kvm_make_request(KVM_REQ_EVENT, vcpu);
5728         return 1;
5729 }
5730
5731 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5732 {
5733         u32 cpu_based_vm_exec_control;
5734
5735         /* clear pending irq */
5736         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5737         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5738         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5739
5740         kvm_make_request(KVM_REQ_EVENT, vcpu);
5741
5742         ++vcpu->stat.irq_window_exits;
5743         return 1;
5744 }
5745
5746 static int handle_halt(struct kvm_vcpu *vcpu)
5747 {
5748         return kvm_emulate_halt(vcpu);
5749 }
5750
5751 static int handle_vmcall(struct kvm_vcpu *vcpu)
5752 {
5753         return kvm_emulate_hypercall(vcpu);
5754 }
5755
5756 static int handle_invd(struct kvm_vcpu *vcpu)
5757 {
5758         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5759 }
5760
5761 static int handle_invlpg(struct kvm_vcpu *vcpu)
5762 {
5763         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5764
5765         kvm_mmu_invlpg(vcpu, exit_qualification);
5766         skip_emulated_instruction(vcpu);
5767         return 1;
5768 }
5769
5770 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5771 {
5772         int err;
5773
5774         err = kvm_rdpmc(vcpu);
5775         kvm_complete_insn_gp(vcpu, err);
5776
5777         return 1;
5778 }
5779
5780 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5781 {
5782         kvm_emulate_wbinvd(vcpu);
5783         return 1;
5784 }
5785
5786 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5787 {
5788         u64 new_bv = kvm_read_edx_eax(vcpu);
5789         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5790
5791         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5792                 skip_emulated_instruction(vcpu);
5793         return 1;
5794 }
5795
5796 static int handle_xsaves(struct kvm_vcpu *vcpu)
5797 {
5798         skip_emulated_instruction(vcpu);
5799         WARN(1, "this should never happen\n");
5800         return 1;
5801 }
5802
5803 static int handle_xrstors(struct kvm_vcpu *vcpu)
5804 {
5805         skip_emulated_instruction(vcpu);
5806         WARN(1, "this should never happen\n");
5807         return 1;
5808 }
5809
5810 static int handle_apic_access(struct kvm_vcpu *vcpu)
5811 {
5812         if (likely(fasteoi)) {
5813                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5814                 int access_type, offset;
5815
5816                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5817                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5818                 /*
5819                  * Sane guest uses MOV to write EOI, with written value
5820                  * not cared. So make a short-circuit here by avoiding
5821                  * heavy instruction emulation.
5822                  */
5823                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5824                     (offset == APIC_EOI)) {
5825                         kvm_lapic_set_eoi(vcpu);
5826                         skip_emulated_instruction(vcpu);
5827                         return 1;
5828                 }
5829         }
5830         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5831 }
5832
5833 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5834 {
5835         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5836         int vector = exit_qualification & 0xff;
5837
5838         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5839         kvm_apic_set_eoi_accelerated(vcpu, vector);
5840         return 1;
5841 }
5842
5843 static int handle_apic_write(struct kvm_vcpu *vcpu)
5844 {
5845         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5846         u32 offset = exit_qualification & 0xfff;
5847
5848         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5849         kvm_apic_write_nodecode(vcpu, offset);
5850         return 1;
5851 }
5852
5853 static int handle_task_switch(struct kvm_vcpu *vcpu)
5854 {
5855         struct vcpu_vmx *vmx = to_vmx(vcpu);
5856         unsigned long exit_qualification;
5857         bool has_error_code = false;
5858         u32 error_code = 0;
5859         u16 tss_selector;
5860         int reason, type, idt_v, idt_index;
5861
5862         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5863         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5864         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5865
5866         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5867
5868         reason = (u32)exit_qualification >> 30;
5869         if (reason == TASK_SWITCH_GATE && idt_v) {
5870                 switch (type) {
5871                 case INTR_TYPE_NMI_INTR:
5872                         vcpu->arch.nmi_injected = false;
5873                         vmx_set_nmi_mask(vcpu, true);
5874                         break;
5875                 case INTR_TYPE_EXT_INTR:
5876                 case INTR_TYPE_SOFT_INTR:
5877                         kvm_clear_interrupt_queue(vcpu);
5878                         break;
5879                 case INTR_TYPE_HARD_EXCEPTION:
5880                         if (vmx->idt_vectoring_info &
5881                             VECTORING_INFO_DELIVER_CODE_MASK) {
5882                                 has_error_code = true;
5883                                 error_code =
5884                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5885                         }
5886                         /* fall through */
5887                 case INTR_TYPE_SOFT_EXCEPTION:
5888                         kvm_clear_exception_queue(vcpu);
5889                         break;
5890                 default:
5891                         break;
5892                 }
5893         }
5894         tss_selector = exit_qualification;
5895
5896         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5897                        type != INTR_TYPE_EXT_INTR &&
5898                        type != INTR_TYPE_NMI_INTR))
5899                 skip_emulated_instruction(vcpu);
5900
5901         if (kvm_task_switch(vcpu, tss_selector,
5902                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5903                             has_error_code, error_code) == EMULATE_FAIL) {
5904                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5905                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5906                 vcpu->run->internal.ndata = 0;
5907                 return 0;
5908         }
5909
5910         /*
5911          * TODO: What about debug traps on tss switch?
5912          *       Are we supposed to inject them and update dr6?
5913          */
5914
5915         return 1;
5916 }
5917
5918 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5919 {
5920         unsigned long exit_qualification;
5921         gpa_t gpa;
5922         u32 error_code;
5923         int gla_validity;
5924
5925         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5926
5927         gla_validity = (exit_qualification >> 7) & 0x3;
5928         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5929                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5930                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5931                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5932                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5933                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5934                         (long unsigned int)exit_qualification);
5935                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5936                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5937                 return 0;
5938         }
5939
5940         /*
5941          * EPT violation happened while executing iret from NMI,
5942          * "blocked by NMI" bit has to be set before next VM entry.
5943          * There are errata that may cause this bit to not be set:
5944          * AAK134, BY25.
5945          */
5946         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5947                         cpu_has_virtual_nmis() &&
5948                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5949                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5950
5951         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5952         trace_kvm_page_fault(gpa, exit_qualification);
5953
5954         /* It is a write fault? */
5955         error_code = exit_qualification & PFERR_WRITE_MASK;
5956         /* It is a fetch fault? */
5957         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5958         /* ept page table is present? */
5959         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5960
5961         vcpu->arch.exit_qualification = exit_qualification;
5962
5963         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5964 }
5965
5966 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5967 {
5968         int ret;
5969         gpa_t gpa;
5970
5971         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5972         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5973                 skip_emulated_instruction(vcpu);
5974                 trace_kvm_fast_mmio(gpa);
5975                 return 1;
5976         }
5977
5978         ret = handle_mmio_page_fault(vcpu, gpa, true);
5979         if (likely(ret == RET_MMIO_PF_EMULATE))
5980                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5981                                               EMULATE_DONE;
5982
5983         if (unlikely(ret == RET_MMIO_PF_INVALID))
5984                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5985
5986         if (unlikely(ret == RET_MMIO_PF_RETRY))
5987                 return 1;
5988
5989         /* It is the real ept misconfig */
5990         WARN_ON(1);
5991
5992         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5993         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5994
5995         return 0;
5996 }
5997
5998 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5999 {
6000         u32 cpu_based_vm_exec_control;
6001
6002         /* clear pending NMI */
6003         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6004         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6005         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6006         ++vcpu->stat.nmi_window_exits;
6007         kvm_make_request(KVM_REQ_EVENT, vcpu);
6008
6009         return 1;
6010 }
6011
6012 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6013 {
6014         struct vcpu_vmx *vmx = to_vmx(vcpu);
6015         enum emulation_result err = EMULATE_DONE;
6016         int ret = 1;
6017         u32 cpu_exec_ctrl;
6018         bool intr_window_requested;
6019         unsigned count = 130;
6020
6021         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6022         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6023
6024         while (vmx->emulation_required && count-- != 0) {
6025                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6026                         return handle_interrupt_window(&vmx->vcpu);
6027
6028                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6029                         return 1;
6030
6031                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6032
6033                 if (err == EMULATE_USER_EXIT) {
6034                         ++vcpu->stat.mmio_exits;
6035                         ret = 0;
6036                         goto out;
6037                 }
6038
6039                 if (err != EMULATE_DONE) {
6040                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6041                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6042                         vcpu->run->internal.ndata = 0;
6043                         return 0;
6044                 }
6045
6046                 if (vcpu->arch.halt_request) {
6047                         vcpu->arch.halt_request = 0;
6048                         ret = kvm_vcpu_halt(vcpu);
6049                         goto out;
6050                 }
6051
6052                 if (signal_pending(current))
6053                         goto out;
6054                 if (need_resched())
6055                         schedule();
6056         }
6057
6058 out:
6059         return ret;
6060 }
6061
6062 static int __grow_ple_window(int val)
6063 {
6064         if (ple_window_grow < 1)
6065                 return ple_window;
6066
6067         val = min(val, ple_window_actual_max);
6068
6069         if (ple_window_grow < ple_window)
6070                 val *= ple_window_grow;
6071         else
6072                 val += ple_window_grow;
6073
6074         return val;
6075 }
6076
6077 static int __shrink_ple_window(int val, int modifier, int minimum)
6078 {
6079         if (modifier < 1)
6080                 return ple_window;
6081
6082         if (modifier < ple_window)
6083                 val /= modifier;
6084         else
6085                 val -= modifier;
6086
6087         return max(val, minimum);
6088 }
6089
6090 static void grow_ple_window(struct kvm_vcpu *vcpu)
6091 {
6092         struct vcpu_vmx *vmx = to_vmx(vcpu);
6093         int old = vmx->ple_window;
6094
6095         vmx->ple_window = __grow_ple_window(old);
6096
6097         if (vmx->ple_window != old)
6098                 vmx->ple_window_dirty = true;
6099
6100         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6101 }
6102
6103 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6104 {
6105         struct vcpu_vmx *vmx = to_vmx(vcpu);
6106         int old = vmx->ple_window;
6107
6108         vmx->ple_window = __shrink_ple_window(old,
6109                                               ple_window_shrink, ple_window);
6110
6111         if (vmx->ple_window != old)
6112                 vmx->ple_window_dirty = true;
6113
6114         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6115 }
6116
6117 /*
6118  * ple_window_actual_max is computed to be one grow_ple_window() below
6119  * ple_window_max. (See __grow_ple_window for the reason.)
6120  * This prevents overflows, because ple_window_max is int.
6121  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6122  * this process.
6123  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6124  */
6125 static void update_ple_window_actual_max(void)
6126 {
6127         ple_window_actual_max =
6128                         __shrink_ple_window(max(ple_window_max, ple_window),
6129                                             ple_window_grow, INT_MIN);
6130 }
6131
6132 /*
6133  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6134  */
6135 static void wakeup_handler(void)
6136 {
6137         struct kvm_vcpu *vcpu;
6138         int cpu = smp_processor_id();
6139
6140         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6141         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6142                         blocked_vcpu_list) {
6143                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6144
6145                 if (pi_test_on(pi_desc) == 1)
6146                         kvm_vcpu_kick(vcpu);
6147         }
6148         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6149 }
6150
6151 static __init int hardware_setup(void)
6152 {
6153         int r = -ENOMEM, i, msr;
6154
6155         rdmsrl_safe(MSR_EFER, &host_efer);
6156
6157         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6158                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6159
6160         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6161         if (!vmx_io_bitmap_a)
6162                 return r;
6163
6164         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6165         if (!vmx_io_bitmap_b)
6166                 goto out;
6167
6168         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6169         if (!vmx_msr_bitmap_legacy)
6170                 goto out1;
6171
6172         vmx_msr_bitmap_legacy_x2apic =
6173                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6174         if (!vmx_msr_bitmap_legacy_x2apic)
6175                 goto out2;
6176
6177         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6178         if (!vmx_msr_bitmap_longmode)
6179                 goto out3;
6180
6181         vmx_msr_bitmap_longmode_x2apic =
6182                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6183         if (!vmx_msr_bitmap_longmode_x2apic)
6184                 goto out4;
6185
6186         if (nested) {
6187                 vmx_msr_bitmap_nested =
6188                         (unsigned long *)__get_free_page(GFP_KERNEL);
6189                 if (!vmx_msr_bitmap_nested)
6190                         goto out5;
6191         }
6192
6193         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6194         if (!vmx_vmread_bitmap)
6195                 goto out6;
6196
6197         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6198         if (!vmx_vmwrite_bitmap)
6199                 goto out7;
6200
6201         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6202         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6203
6204         /*
6205          * Allow direct access to the PC debug port (it is often used for I/O
6206          * delays, but the vmexits simply slow things down).
6207          */
6208         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6209         clear_bit(0x80, vmx_io_bitmap_a);
6210
6211         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6212
6213         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6214         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6215         if (nested)
6216                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6217
6218         if (setup_vmcs_config(&vmcs_config) < 0) {
6219                 r = -EIO;
6220                 goto out8;
6221         }
6222
6223         if (boot_cpu_has(X86_FEATURE_NX))
6224                 kvm_enable_efer_bits(EFER_NX);
6225
6226         if (!cpu_has_vmx_vpid())
6227                 enable_vpid = 0;
6228         if (!cpu_has_vmx_shadow_vmcs())
6229                 enable_shadow_vmcs = 0;
6230         if (enable_shadow_vmcs)
6231                 init_vmcs_shadow_fields();
6232
6233         if (!cpu_has_vmx_ept() ||
6234             !cpu_has_vmx_ept_4levels()) {
6235                 enable_ept = 0;
6236                 enable_unrestricted_guest = 0;
6237                 enable_ept_ad_bits = 0;
6238         }
6239
6240         if (!cpu_has_vmx_ept_ad_bits())
6241                 enable_ept_ad_bits = 0;
6242
6243         if (!cpu_has_vmx_unrestricted_guest())
6244                 enable_unrestricted_guest = 0;
6245
6246         if (!cpu_has_vmx_flexpriority())
6247                 flexpriority_enabled = 0;
6248
6249         /*
6250          * set_apic_access_page_addr() is used to reload apic access
6251          * page upon invalidation.  No need to do anything if not
6252          * using the APIC_ACCESS_ADDR VMCS field.
6253          */
6254         if (!flexpriority_enabled)
6255                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6256
6257         if (!cpu_has_vmx_tpr_shadow())
6258                 kvm_x86_ops->update_cr8_intercept = NULL;
6259
6260         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6261                 kvm_disable_largepages();
6262
6263         if (!cpu_has_vmx_ple())
6264                 ple_gap = 0;
6265
6266         if (!cpu_has_vmx_apicv())
6267                 enable_apicv = 0;
6268
6269         if (cpu_has_vmx_tsc_scaling()) {
6270                 kvm_has_tsc_control = true;
6271                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6272                 kvm_tsc_scaling_ratio_frac_bits = 48;
6273         }
6274
6275         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6276         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6277         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6278         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6279         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6280         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6281         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6282
6283         memcpy(vmx_msr_bitmap_legacy_x2apic,
6284                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6285         memcpy(vmx_msr_bitmap_longmode_x2apic,
6286                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6287
6288         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6289
6290         if (enable_apicv) {
6291                 for (msr = 0x800; msr <= 0x8ff; msr++)
6292                         vmx_disable_intercept_msr_read_x2apic(msr);
6293
6294                 /* According SDM, in x2apic mode, the whole id reg is used.
6295                  * But in KVM, it only use the highest eight bits. Need to
6296                  * intercept it */
6297                 vmx_enable_intercept_msr_read_x2apic(0x802);
6298                 /* TMCCT */
6299                 vmx_enable_intercept_msr_read_x2apic(0x839);
6300                 /* TPR */
6301                 vmx_disable_intercept_msr_write_x2apic(0x808);
6302                 /* EOI */
6303                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6304                 /* SELF-IPI */
6305                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6306         }
6307
6308         if (enable_ept) {
6309                 kvm_mmu_set_mask_ptes(0ull,
6310                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6311                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6312                         0ull, VMX_EPT_EXECUTABLE_MASK);
6313                 ept_set_mmio_spte_mask();
6314                 kvm_enable_tdp();
6315         } else
6316                 kvm_disable_tdp();
6317
6318         update_ple_window_actual_max();
6319
6320         /*
6321          * Only enable PML when hardware supports PML feature, and both EPT
6322          * and EPT A/D bit features are enabled -- PML depends on them to work.
6323          */
6324         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6325                 enable_pml = 0;
6326
6327         if (!enable_pml) {
6328                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6329                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6330                 kvm_x86_ops->flush_log_dirty = NULL;
6331                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6332         }
6333
6334         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6335
6336         return alloc_kvm_area();
6337
6338 out8:
6339         free_page((unsigned long)vmx_vmwrite_bitmap);
6340 out7:
6341         free_page((unsigned long)vmx_vmread_bitmap);
6342 out6:
6343         if (nested)
6344                 free_page((unsigned long)vmx_msr_bitmap_nested);
6345 out5:
6346         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6347 out4:
6348         free_page((unsigned long)vmx_msr_bitmap_longmode);
6349 out3:
6350         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6351 out2:
6352         free_page((unsigned long)vmx_msr_bitmap_legacy);
6353 out1:
6354         free_page((unsigned long)vmx_io_bitmap_b);
6355 out:
6356         free_page((unsigned long)vmx_io_bitmap_a);
6357
6358     return r;
6359 }
6360
6361 static __exit void hardware_unsetup(void)
6362 {
6363         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6364         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6365         free_page((unsigned long)vmx_msr_bitmap_legacy);
6366         free_page((unsigned long)vmx_msr_bitmap_longmode);
6367         free_page((unsigned long)vmx_io_bitmap_b);
6368         free_page((unsigned long)vmx_io_bitmap_a);
6369         free_page((unsigned long)vmx_vmwrite_bitmap);
6370         free_page((unsigned long)vmx_vmread_bitmap);
6371         if (nested)
6372                 free_page((unsigned long)vmx_msr_bitmap_nested);
6373
6374         free_kvm_area();
6375 }
6376
6377 /*
6378  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6379  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6380  */
6381 static int handle_pause(struct kvm_vcpu *vcpu)
6382 {
6383         if (ple_gap)
6384                 grow_ple_window(vcpu);
6385
6386         skip_emulated_instruction(vcpu);
6387         kvm_vcpu_on_spin(vcpu);
6388
6389         return 1;
6390 }
6391
6392 static int handle_nop(struct kvm_vcpu *vcpu)
6393 {
6394         skip_emulated_instruction(vcpu);
6395         return 1;
6396 }
6397
6398 static int handle_mwait(struct kvm_vcpu *vcpu)
6399 {
6400         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6401         return handle_nop(vcpu);
6402 }
6403
6404 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6405 {
6406         return 1;
6407 }
6408
6409 static int handle_monitor(struct kvm_vcpu *vcpu)
6410 {
6411         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6412         return handle_nop(vcpu);
6413 }
6414
6415 /*
6416  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6417  * We could reuse a single VMCS for all the L2 guests, but we also want the
6418  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6419  * allows keeping them loaded on the processor, and in the future will allow
6420  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6421  * every entry if they never change.
6422  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6423  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6424  *
6425  * The following functions allocate and free a vmcs02 in this pool.
6426  */
6427
6428 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6429 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6430 {
6431         struct vmcs02_list *item;
6432         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6433                 if (item->vmptr == vmx->nested.current_vmptr) {
6434                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6435                         return &item->vmcs02;
6436                 }
6437
6438         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6439                 /* Recycle the least recently used VMCS. */
6440                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6441                                        struct vmcs02_list, list);
6442                 item->vmptr = vmx->nested.current_vmptr;
6443                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6444                 return &item->vmcs02;
6445         }
6446
6447         /* Create a new VMCS */
6448         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6449         if (!item)
6450                 return NULL;
6451         item->vmcs02.vmcs = alloc_vmcs();
6452         if (!item->vmcs02.vmcs) {
6453                 kfree(item);
6454                 return NULL;
6455         }
6456         loaded_vmcs_init(&item->vmcs02);
6457         item->vmptr = vmx->nested.current_vmptr;
6458         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6459         vmx->nested.vmcs02_num++;
6460         return &item->vmcs02;
6461 }
6462
6463 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6464 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6465 {
6466         struct vmcs02_list *item;
6467         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6468                 if (item->vmptr == vmptr) {
6469                         free_loaded_vmcs(&item->vmcs02);
6470                         list_del(&item->list);
6471                         kfree(item);
6472                         vmx->nested.vmcs02_num--;
6473                         return;
6474                 }
6475 }
6476
6477 /*
6478  * Free all VMCSs saved for this vcpu, except the one pointed by
6479  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6480  * must be &vmx->vmcs01.
6481  */
6482 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6483 {
6484         struct vmcs02_list *item, *n;
6485
6486         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6487         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6488                 /*
6489                  * Something will leak if the above WARN triggers.  Better than
6490                  * a use-after-free.
6491                  */
6492                 if (vmx->loaded_vmcs == &item->vmcs02)
6493                         continue;
6494
6495                 free_loaded_vmcs(&item->vmcs02);
6496                 list_del(&item->list);
6497                 kfree(item);
6498                 vmx->nested.vmcs02_num--;
6499         }
6500 }
6501
6502 /*
6503  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6504  * set the success or error code of an emulated VMX instruction, as specified
6505  * by Vol 2B, VMX Instruction Reference, "Conventions".
6506  */
6507 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6508 {
6509         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6510                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6511                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6512 }
6513
6514 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6515 {
6516         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6517                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6518                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6519                         | X86_EFLAGS_CF);
6520 }
6521
6522 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6523                                         u32 vm_instruction_error)
6524 {
6525         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6526                 /*
6527                  * failValid writes the error number to the current VMCS, which
6528                  * can't be done there isn't a current VMCS.
6529                  */
6530                 nested_vmx_failInvalid(vcpu);
6531                 return;
6532         }
6533         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6534                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6535                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6536                         | X86_EFLAGS_ZF);
6537         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6538         /*
6539          * We don't need to force a shadow sync because
6540          * VM_INSTRUCTION_ERROR is not shadowed
6541          */
6542 }
6543
6544 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6545 {
6546         /* TODO: not to reset guest simply here. */
6547         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6548         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6549 }
6550
6551 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6552 {
6553         struct vcpu_vmx *vmx =
6554                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6555
6556         vmx->nested.preemption_timer_expired = true;
6557         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6558         kvm_vcpu_kick(&vmx->vcpu);
6559
6560         return HRTIMER_NORESTART;
6561 }
6562
6563 /*
6564  * Decode the memory-address operand of a vmx instruction, as recorded on an
6565  * exit caused by such an instruction (run by a guest hypervisor).
6566  * On success, returns 0. When the operand is invalid, returns 1 and throws
6567  * #UD or #GP.
6568  */
6569 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6570                                  unsigned long exit_qualification,
6571                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6572 {
6573         gva_t off;
6574         bool exn;
6575         struct kvm_segment s;
6576
6577         /*
6578          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6579          * Execution", on an exit, vmx_instruction_info holds most of the
6580          * addressing components of the operand. Only the displacement part
6581          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6582          * For how an actual address is calculated from all these components,
6583          * refer to Vol. 1, "Operand Addressing".
6584          */
6585         int  scaling = vmx_instruction_info & 3;
6586         int  addr_size = (vmx_instruction_info >> 7) & 7;
6587         bool is_reg = vmx_instruction_info & (1u << 10);
6588         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6589         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6590         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6591         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6592         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6593
6594         if (is_reg) {
6595                 kvm_queue_exception(vcpu, UD_VECTOR);
6596                 return 1;
6597         }
6598
6599         /* Addr = segment_base + offset */
6600         /* offset = base + [index * scale] + displacement */
6601         off = exit_qualification; /* holds the displacement */
6602         if (base_is_valid)
6603                 off += kvm_register_read(vcpu, base_reg);
6604         if (index_is_valid)
6605                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6606         vmx_get_segment(vcpu, &s, seg_reg);
6607         *ret = s.base + off;
6608
6609         if (addr_size == 1) /* 32 bit */
6610                 *ret &= 0xffffffff;
6611
6612         /* Checks for #GP/#SS exceptions. */
6613         exn = false;
6614         if (is_protmode(vcpu)) {
6615                 /* Protected mode: apply checks for segment validity in the
6616                  * following order:
6617                  * - segment type check (#GP(0) may be thrown)
6618                  * - usability check (#GP(0)/#SS(0))
6619                  * - limit check (#GP(0)/#SS(0))
6620                  */
6621                 if (wr)
6622                         /* #GP(0) if the destination operand is located in a
6623                          * read-only data segment or any code segment.
6624                          */
6625                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6626                 else
6627                         /* #GP(0) if the source operand is located in an
6628                          * execute-only code segment
6629                          */
6630                         exn = ((s.type & 0xa) == 8);
6631         }
6632         if (exn) {
6633                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6634                 return 1;
6635         }
6636         if (is_long_mode(vcpu)) {
6637                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6638                  * non-canonical form. This is an only check for long mode.
6639                  */
6640                 exn = is_noncanonical_address(*ret);
6641         } else if (is_protmode(vcpu)) {
6642                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6643                  */
6644                 exn = (s.unusable != 0);
6645                 /* Protected mode: #GP(0)/#SS(0) if the memory
6646                  * operand is outside the segment limit.
6647                  */
6648                 exn = exn || (off + sizeof(u64) > s.limit);
6649         }
6650         if (exn) {
6651                 kvm_queue_exception_e(vcpu,
6652                                       seg_reg == VCPU_SREG_SS ?
6653                                                 SS_VECTOR : GP_VECTOR,
6654                                       0);
6655                 return 1;
6656         }
6657
6658         return 0;
6659 }
6660
6661 /*
6662  * This function performs the various checks including
6663  * - if it's 4KB aligned
6664  * - No bits beyond the physical address width are set
6665  * - Returns 0 on success or else 1
6666  * (Intel SDM Section 30.3)
6667  */
6668 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6669                                   gpa_t *vmpointer)
6670 {
6671         gva_t gva;
6672         gpa_t vmptr;
6673         struct x86_exception e;
6674         struct page *page;
6675         struct vcpu_vmx *vmx = to_vmx(vcpu);
6676         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6677
6678         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6679                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6680                 return 1;
6681
6682         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6683                                 sizeof(vmptr), &e)) {
6684                 kvm_inject_page_fault(vcpu, &e);
6685                 return 1;
6686         }
6687
6688         switch (exit_reason) {
6689         case EXIT_REASON_VMON:
6690                 /*
6691                  * SDM 3: 24.11.5
6692                  * The first 4 bytes of VMXON region contain the supported
6693                  * VMCS revision identifier
6694                  *
6695                  * Note - IA32_VMX_BASIC[48] will never be 1
6696                  * for the nested case;
6697                  * which replaces physical address width with 32
6698                  *
6699                  */
6700                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6701                         nested_vmx_failInvalid(vcpu);
6702                         skip_emulated_instruction(vcpu);
6703                         return 1;
6704                 }
6705
6706                 page = nested_get_page(vcpu, vmptr);
6707                 if (page == NULL ||
6708                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6709                         nested_vmx_failInvalid(vcpu);
6710                         kunmap(page);
6711                         skip_emulated_instruction(vcpu);
6712                         return 1;
6713                 }
6714                 kunmap(page);
6715                 vmx->nested.vmxon_ptr = vmptr;
6716                 break;
6717         case EXIT_REASON_VMCLEAR:
6718                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6719                         nested_vmx_failValid(vcpu,
6720                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6721                         skip_emulated_instruction(vcpu);
6722                         return 1;
6723                 }
6724
6725                 if (vmptr == vmx->nested.vmxon_ptr) {
6726                         nested_vmx_failValid(vcpu,
6727                                              VMXERR_VMCLEAR_VMXON_POINTER);
6728                         skip_emulated_instruction(vcpu);
6729                         return 1;
6730                 }
6731                 break;
6732         case EXIT_REASON_VMPTRLD:
6733                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6734                         nested_vmx_failValid(vcpu,
6735                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6736                         skip_emulated_instruction(vcpu);
6737                         return 1;
6738                 }
6739
6740                 if (vmptr == vmx->nested.vmxon_ptr) {
6741                         nested_vmx_failValid(vcpu,
6742                                              VMXERR_VMCLEAR_VMXON_POINTER);
6743                         skip_emulated_instruction(vcpu);
6744                         return 1;
6745                 }
6746                 break;
6747         default:
6748                 return 1; /* shouldn't happen */
6749         }
6750
6751         if (vmpointer)
6752                 *vmpointer = vmptr;
6753         return 0;
6754 }
6755
6756 /*
6757  * Emulate the VMXON instruction.
6758  * Currently, we just remember that VMX is active, and do not save or even
6759  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6760  * do not currently need to store anything in that guest-allocated memory
6761  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6762  * argument is different from the VMXON pointer (which the spec says they do).
6763  */
6764 static int handle_vmon(struct kvm_vcpu *vcpu)
6765 {
6766         struct kvm_segment cs;
6767         struct vcpu_vmx *vmx = to_vmx(vcpu);
6768         struct vmcs *shadow_vmcs;
6769         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6770                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6771
6772         /* The Intel VMX Instruction Reference lists a bunch of bits that
6773          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6774          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6775          * Otherwise, we should fail with #UD. We test these now:
6776          */
6777         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6778             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6779             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6780                 kvm_queue_exception(vcpu, UD_VECTOR);
6781                 return 1;
6782         }
6783
6784         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6785         if (is_long_mode(vcpu) && !cs.l) {
6786                 kvm_queue_exception(vcpu, UD_VECTOR);
6787                 return 1;
6788         }
6789
6790         if (vmx_get_cpl(vcpu)) {
6791                 kvm_inject_gp(vcpu, 0);
6792                 return 1;
6793         }
6794
6795         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6796                 return 1;
6797
6798         if (vmx->nested.vmxon) {
6799                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6800                 skip_emulated_instruction(vcpu);
6801                 return 1;
6802         }
6803
6804         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6805                         != VMXON_NEEDED_FEATURES) {
6806                 kvm_inject_gp(vcpu, 0);
6807                 return 1;
6808         }
6809
6810         if (enable_shadow_vmcs) {
6811                 shadow_vmcs = alloc_vmcs();
6812                 if (!shadow_vmcs)
6813                         return -ENOMEM;
6814                 /* mark vmcs as shadow */
6815                 shadow_vmcs->revision_id |= (1u << 31);
6816                 /* init shadow vmcs */
6817                 vmcs_clear(shadow_vmcs);
6818                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6819         }
6820
6821         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6822         vmx->nested.vmcs02_num = 0;
6823
6824         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6825                      HRTIMER_MODE_REL);
6826         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6827
6828         vmx->nested.vmxon = true;
6829
6830         skip_emulated_instruction(vcpu);
6831         nested_vmx_succeed(vcpu);
6832         return 1;
6833 }
6834
6835 /*
6836  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6837  * for running VMX instructions (except VMXON, whose prerequisites are
6838  * slightly different). It also specifies what exception to inject otherwise.
6839  */
6840 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6841 {
6842         struct kvm_segment cs;
6843         struct vcpu_vmx *vmx = to_vmx(vcpu);
6844
6845         if (!vmx->nested.vmxon) {
6846                 kvm_queue_exception(vcpu, UD_VECTOR);
6847                 return 0;
6848         }
6849
6850         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6851         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6852             (is_long_mode(vcpu) && !cs.l)) {
6853                 kvm_queue_exception(vcpu, UD_VECTOR);
6854                 return 0;
6855         }
6856
6857         if (vmx_get_cpl(vcpu)) {
6858                 kvm_inject_gp(vcpu, 0);
6859                 return 0;
6860         }
6861
6862         return 1;
6863 }
6864
6865 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6866 {
6867         if (vmx->nested.current_vmptr == -1ull)
6868                 return;
6869
6870         /* current_vmptr and current_vmcs12 are always set/reset together */
6871         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6872                 return;
6873
6874         if (enable_shadow_vmcs) {
6875                 /* copy to memory all shadowed fields in case
6876                    they were modified */
6877                 copy_shadow_to_vmcs12(vmx);
6878                 vmx->nested.sync_shadow_vmcs = false;
6879                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6880                                 SECONDARY_EXEC_SHADOW_VMCS);
6881                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6882         }
6883         vmx->nested.posted_intr_nv = -1;
6884         kunmap(vmx->nested.current_vmcs12_page);
6885         nested_release_page(vmx->nested.current_vmcs12_page);
6886         vmx->nested.current_vmptr = -1ull;
6887         vmx->nested.current_vmcs12 = NULL;
6888 }
6889
6890 /*
6891  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6892  * just stops using VMX.
6893  */
6894 static void free_nested(struct vcpu_vmx *vmx)
6895 {
6896         if (!vmx->nested.vmxon)
6897                 return;
6898
6899         vmx->nested.vmxon = false;
6900         free_vpid(vmx->nested.vpid02);
6901         nested_release_vmcs12(vmx);
6902         if (enable_shadow_vmcs)
6903                 free_vmcs(vmx->nested.current_shadow_vmcs);
6904         /* Unpin physical memory we referred to in current vmcs02 */
6905         if (vmx->nested.apic_access_page) {
6906                 nested_release_page(vmx->nested.apic_access_page);
6907                 vmx->nested.apic_access_page = NULL;
6908         }
6909         if (vmx->nested.virtual_apic_page) {
6910                 nested_release_page(vmx->nested.virtual_apic_page);
6911                 vmx->nested.virtual_apic_page = NULL;
6912         }
6913         if (vmx->nested.pi_desc_page) {
6914                 kunmap(vmx->nested.pi_desc_page);
6915                 nested_release_page(vmx->nested.pi_desc_page);
6916                 vmx->nested.pi_desc_page = NULL;
6917                 vmx->nested.pi_desc = NULL;
6918         }
6919
6920         nested_free_all_saved_vmcss(vmx);
6921 }
6922
6923 /* Emulate the VMXOFF instruction */
6924 static int handle_vmoff(struct kvm_vcpu *vcpu)
6925 {
6926         if (!nested_vmx_check_permission(vcpu))
6927                 return 1;
6928         free_nested(to_vmx(vcpu));
6929         skip_emulated_instruction(vcpu);
6930         nested_vmx_succeed(vcpu);
6931         return 1;
6932 }
6933
6934 /* Emulate the VMCLEAR instruction */
6935 static int handle_vmclear(struct kvm_vcpu *vcpu)
6936 {
6937         struct vcpu_vmx *vmx = to_vmx(vcpu);
6938         gpa_t vmptr;
6939         struct vmcs12 *vmcs12;
6940         struct page *page;
6941
6942         if (!nested_vmx_check_permission(vcpu))
6943                 return 1;
6944
6945         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6946                 return 1;
6947
6948         if (vmptr == vmx->nested.current_vmptr)
6949                 nested_release_vmcs12(vmx);
6950
6951         page = nested_get_page(vcpu, vmptr);
6952         if (page == NULL) {
6953                 /*
6954                  * For accurate processor emulation, VMCLEAR beyond available
6955                  * physical memory should do nothing at all. However, it is
6956                  * possible that a nested vmx bug, not a guest hypervisor bug,
6957                  * resulted in this case, so let's shut down before doing any
6958                  * more damage:
6959                  */
6960                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6961                 return 1;
6962         }
6963         vmcs12 = kmap(page);
6964         vmcs12->launch_state = 0;
6965         kunmap(page);
6966         nested_release_page(page);
6967
6968         nested_free_vmcs02(vmx, vmptr);
6969
6970         skip_emulated_instruction(vcpu);
6971         nested_vmx_succeed(vcpu);
6972         return 1;
6973 }
6974
6975 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6976
6977 /* Emulate the VMLAUNCH instruction */
6978 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6979 {
6980         return nested_vmx_run(vcpu, true);
6981 }
6982
6983 /* Emulate the VMRESUME instruction */
6984 static int handle_vmresume(struct kvm_vcpu *vcpu)
6985 {
6986
6987         return nested_vmx_run(vcpu, false);
6988 }
6989
6990 enum vmcs_field_type {
6991         VMCS_FIELD_TYPE_U16 = 0,
6992         VMCS_FIELD_TYPE_U64 = 1,
6993         VMCS_FIELD_TYPE_U32 = 2,
6994         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6995 };
6996
6997 static inline int vmcs_field_type(unsigned long field)
6998 {
6999         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7000                 return VMCS_FIELD_TYPE_U32;
7001         return (field >> 13) & 0x3 ;
7002 }
7003
7004 static inline int vmcs_field_readonly(unsigned long field)
7005 {
7006         return (((field >> 10) & 0x3) == 1);
7007 }
7008
7009 /*
7010  * Read a vmcs12 field. Since these can have varying lengths and we return
7011  * one type, we chose the biggest type (u64) and zero-extend the return value
7012  * to that size. Note that the caller, handle_vmread, might need to use only
7013  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7014  * 64-bit fields are to be returned).
7015  */
7016 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7017                                   unsigned long field, u64 *ret)
7018 {
7019         short offset = vmcs_field_to_offset(field);
7020         char *p;
7021
7022         if (offset < 0)
7023                 return offset;
7024
7025         p = ((char *)(get_vmcs12(vcpu))) + offset;
7026
7027         switch (vmcs_field_type(field)) {
7028         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7029                 *ret = *((natural_width *)p);
7030                 return 0;
7031         case VMCS_FIELD_TYPE_U16:
7032                 *ret = *((u16 *)p);
7033                 return 0;
7034         case VMCS_FIELD_TYPE_U32:
7035                 *ret = *((u32 *)p);
7036                 return 0;
7037         case VMCS_FIELD_TYPE_U64:
7038                 *ret = *((u64 *)p);
7039                 return 0;
7040         default:
7041                 WARN_ON(1);
7042                 return -ENOENT;
7043         }
7044 }
7045
7046
7047 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7048                                    unsigned long field, u64 field_value){
7049         short offset = vmcs_field_to_offset(field);
7050         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7051         if (offset < 0)
7052                 return offset;
7053
7054         switch (vmcs_field_type(field)) {
7055         case VMCS_FIELD_TYPE_U16:
7056                 *(u16 *)p = field_value;
7057                 return 0;
7058         case VMCS_FIELD_TYPE_U32:
7059                 *(u32 *)p = field_value;
7060                 return 0;
7061         case VMCS_FIELD_TYPE_U64:
7062                 *(u64 *)p = field_value;
7063                 return 0;
7064         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7065                 *(natural_width *)p = field_value;
7066                 return 0;
7067         default:
7068                 WARN_ON(1);
7069                 return -ENOENT;
7070         }
7071
7072 }
7073
7074 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7075 {
7076         int i;
7077         unsigned long field;
7078         u64 field_value;
7079         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7080         const unsigned long *fields = shadow_read_write_fields;
7081         const int num_fields = max_shadow_read_write_fields;
7082
7083         preempt_disable();
7084
7085         vmcs_load(shadow_vmcs);
7086
7087         for (i = 0; i < num_fields; i++) {
7088                 field = fields[i];
7089                 switch (vmcs_field_type(field)) {
7090                 case VMCS_FIELD_TYPE_U16:
7091                         field_value = vmcs_read16(field);
7092                         break;
7093                 case VMCS_FIELD_TYPE_U32:
7094                         field_value = vmcs_read32(field);
7095                         break;
7096                 case VMCS_FIELD_TYPE_U64:
7097                         field_value = vmcs_read64(field);
7098                         break;
7099                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7100                         field_value = vmcs_readl(field);
7101                         break;
7102                 default:
7103                         WARN_ON(1);
7104                         continue;
7105                 }
7106                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7107         }
7108
7109         vmcs_clear(shadow_vmcs);
7110         vmcs_load(vmx->loaded_vmcs->vmcs);
7111
7112         preempt_enable();
7113 }
7114
7115 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7116 {
7117         const unsigned long *fields[] = {
7118                 shadow_read_write_fields,
7119                 shadow_read_only_fields
7120         };
7121         const int max_fields[] = {
7122                 max_shadow_read_write_fields,
7123                 max_shadow_read_only_fields
7124         };
7125         int i, q;
7126         unsigned long field;
7127         u64 field_value = 0;
7128         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7129
7130         vmcs_load(shadow_vmcs);
7131
7132         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7133                 for (i = 0; i < max_fields[q]; i++) {
7134                         field = fields[q][i];
7135                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7136
7137                         switch (vmcs_field_type(field)) {
7138                         case VMCS_FIELD_TYPE_U16:
7139                                 vmcs_write16(field, (u16)field_value);
7140                                 break;
7141                         case VMCS_FIELD_TYPE_U32:
7142                                 vmcs_write32(field, (u32)field_value);
7143                                 break;
7144                         case VMCS_FIELD_TYPE_U64:
7145                                 vmcs_write64(field, (u64)field_value);
7146                                 break;
7147                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7148                                 vmcs_writel(field, (long)field_value);
7149                                 break;
7150                         default:
7151                                 WARN_ON(1);
7152                                 break;
7153                         }
7154                 }
7155         }
7156
7157         vmcs_clear(shadow_vmcs);
7158         vmcs_load(vmx->loaded_vmcs->vmcs);
7159 }
7160
7161 /*
7162  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7163  * used before) all generate the same failure when it is missing.
7164  */
7165 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7166 {
7167         struct vcpu_vmx *vmx = to_vmx(vcpu);
7168         if (vmx->nested.current_vmptr == -1ull) {
7169                 nested_vmx_failInvalid(vcpu);
7170                 skip_emulated_instruction(vcpu);
7171                 return 0;
7172         }
7173         return 1;
7174 }
7175
7176 static int handle_vmread(struct kvm_vcpu *vcpu)
7177 {
7178         unsigned long field;
7179         u64 field_value;
7180         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7181         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7182         gva_t gva = 0;
7183
7184         if (!nested_vmx_check_permission(vcpu) ||
7185             !nested_vmx_check_vmcs12(vcpu))
7186                 return 1;
7187
7188         /* Decode instruction info and find the field to read */
7189         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7190         /* Read the field, zero-extended to a u64 field_value */
7191         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7192                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7193                 skip_emulated_instruction(vcpu);
7194                 return 1;
7195         }
7196         /*
7197          * Now copy part of this value to register or memory, as requested.
7198          * Note that the number of bits actually copied is 32 or 64 depending
7199          * on the guest's mode (32 or 64 bit), not on the given field's length.
7200          */
7201         if (vmx_instruction_info & (1u << 10)) {
7202                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7203                         field_value);
7204         } else {
7205                 if (get_vmx_mem_address(vcpu, exit_qualification,
7206                                 vmx_instruction_info, true, &gva))
7207                         return 1;
7208                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7209                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7210                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7211         }
7212
7213         nested_vmx_succeed(vcpu);
7214         skip_emulated_instruction(vcpu);
7215         return 1;
7216 }
7217
7218
7219 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7220 {
7221         unsigned long field;
7222         gva_t gva;
7223         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7224         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7225         /* The value to write might be 32 or 64 bits, depending on L1's long
7226          * mode, and eventually we need to write that into a field of several
7227          * possible lengths. The code below first zero-extends the value to 64
7228          * bit (field_value), and then copies only the approriate number of
7229          * bits into the vmcs12 field.
7230          */
7231         u64 field_value = 0;
7232         struct x86_exception e;
7233
7234         if (!nested_vmx_check_permission(vcpu) ||
7235             !nested_vmx_check_vmcs12(vcpu))
7236                 return 1;
7237
7238         if (vmx_instruction_info & (1u << 10))
7239                 field_value = kvm_register_readl(vcpu,
7240                         (((vmx_instruction_info) >> 3) & 0xf));
7241         else {
7242                 if (get_vmx_mem_address(vcpu, exit_qualification,
7243                                 vmx_instruction_info, false, &gva))
7244                         return 1;
7245                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7246                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7247                         kvm_inject_page_fault(vcpu, &e);
7248                         return 1;
7249                 }
7250         }
7251
7252
7253         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7254         if (vmcs_field_readonly(field)) {
7255                 nested_vmx_failValid(vcpu,
7256                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7257                 skip_emulated_instruction(vcpu);
7258                 return 1;
7259         }
7260
7261         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7262                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7263                 skip_emulated_instruction(vcpu);
7264                 return 1;
7265         }
7266
7267         nested_vmx_succeed(vcpu);
7268         skip_emulated_instruction(vcpu);
7269         return 1;
7270 }
7271
7272 /* Emulate the VMPTRLD instruction */
7273 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7274 {
7275         struct vcpu_vmx *vmx = to_vmx(vcpu);
7276         gpa_t vmptr;
7277
7278         if (!nested_vmx_check_permission(vcpu))
7279                 return 1;
7280
7281         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7282                 return 1;
7283
7284         if (vmx->nested.current_vmptr != vmptr) {
7285                 struct vmcs12 *new_vmcs12;
7286                 struct page *page;
7287                 page = nested_get_page(vcpu, vmptr);
7288                 if (page == NULL) {
7289                         nested_vmx_failInvalid(vcpu);
7290                         skip_emulated_instruction(vcpu);
7291                         return 1;
7292                 }
7293                 new_vmcs12 = kmap(page);
7294                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7295                         kunmap(page);
7296                         nested_release_page_clean(page);
7297                         nested_vmx_failValid(vcpu,
7298                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7299                         skip_emulated_instruction(vcpu);
7300                         return 1;
7301                 }
7302
7303                 nested_release_vmcs12(vmx);
7304                 vmx->nested.current_vmptr = vmptr;
7305                 vmx->nested.current_vmcs12 = new_vmcs12;
7306                 vmx->nested.current_vmcs12_page = page;
7307                 if (enable_shadow_vmcs) {
7308                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7309                                       SECONDARY_EXEC_SHADOW_VMCS);
7310                         vmcs_write64(VMCS_LINK_POINTER,
7311                                      __pa(vmx->nested.current_shadow_vmcs));
7312                         vmx->nested.sync_shadow_vmcs = true;
7313                 }
7314         }
7315
7316         nested_vmx_succeed(vcpu);
7317         skip_emulated_instruction(vcpu);
7318         return 1;
7319 }
7320
7321 /* Emulate the VMPTRST instruction */
7322 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7323 {
7324         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7325         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7326         gva_t vmcs_gva;
7327         struct x86_exception e;
7328
7329         if (!nested_vmx_check_permission(vcpu))
7330                 return 1;
7331
7332         if (get_vmx_mem_address(vcpu, exit_qualification,
7333                         vmx_instruction_info, true, &vmcs_gva))
7334                 return 1;
7335         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7336         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7337                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7338                                  sizeof(u64), &e)) {
7339                 kvm_inject_page_fault(vcpu, &e);
7340                 return 1;
7341         }
7342         nested_vmx_succeed(vcpu);
7343         skip_emulated_instruction(vcpu);
7344         return 1;
7345 }
7346
7347 /* Emulate the INVEPT instruction */
7348 static int handle_invept(struct kvm_vcpu *vcpu)
7349 {
7350         struct vcpu_vmx *vmx = to_vmx(vcpu);
7351         u32 vmx_instruction_info, types;
7352         unsigned long type;
7353         gva_t gva;
7354         struct x86_exception e;
7355         struct {
7356                 u64 eptp, gpa;
7357         } operand;
7358
7359         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7360               SECONDARY_EXEC_ENABLE_EPT) ||
7361             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7362                 kvm_queue_exception(vcpu, UD_VECTOR);
7363                 return 1;
7364         }
7365
7366         if (!nested_vmx_check_permission(vcpu))
7367                 return 1;
7368
7369         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7370                 kvm_queue_exception(vcpu, UD_VECTOR);
7371                 return 1;
7372         }
7373
7374         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7375         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7376
7377         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7378
7379         if (!(types & (1UL << type))) {
7380                 nested_vmx_failValid(vcpu,
7381                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7382                 return 1;
7383         }
7384
7385         /* According to the Intel VMX instruction reference, the memory
7386          * operand is read even if it isn't needed (e.g., for type==global)
7387          */
7388         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7389                         vmx_instruction_info, false, &gva))
7390                 return 1;
7391         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7392                                 sizeof(operand), &e)) {
7393                 kvm_inject_page_fault(vcpu, &e);
7394                 return 1;
7395         }
7396
7397         switch (type) {
7398         case VMX_EPT_EXTENT_GLOBAL:
7399                 kvm_mmu_sync_roots(vcpu);
7400                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7401                 nested_vmx_succeed(vcpu);
7402                 break;
7403         default:
7404                 /* Trap single context invalidation invept calls */
7405                 BUG_ON(1);
7406                 break;
7407         }
7408
7409         skip_emulated_instruction(vcpu);
7410         return 1;
7411 }
7412
7413 static int handle_invvpid(struct kvm_vcpu *vcpu)
7414 {
7415         struct vcpu_vmx *vmx = to_vmx(vcpu);
7416         u32 vmx_instruction_info;
7417         unsigned long type, types;
7418         gva_t gva;
7419         struct x86_exception e;
7420         int vpid;
7421
7422         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7423               SECONDARY_EXEC_ENABLE_VPID) ||
7424                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7425                 kvm_queue_exception(vcpu, UD_VECTOR);
7426                 return 1;
7427         }
7428
7429         if (!nested_vmx_check_permission(vcpu))
7430                 return 1;
7431
7432         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7433         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7434
7435         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7436
7437         if (!(types & (1UL << type))) {
7438                 nested_vmx_failValid(vcpu,
7439                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7440                 return 1;
7441         }
7442
7443         /* according to the intel vmx instruction reference, the memory
7444          * operand is read even if it isn't needed (e.g., for type==global)
7445          */
7446         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7447                         vmx_instruction_info, false, &gva))
7448                 return 1;
7449         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7450                                 sizeof(u32), &e)) {
7451                 kvm_inject_page_fault(vcpu, &e);
7452                 return 1;
7453         }
7454
7455         switch (type) {
7456         case VMX_VPID_EXTENT_ALL_CONTEXT:
7457                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7458                 nested_vmx_succeed(vcpu);
7459                 break;
7460         default:
7461                 /* Trap single context invalidation invvpid calls */
7462                 BUG_ON(1);
7463                 break;
7464         }
7465
7466         skip_emulated_instruction(vcpu);
7467         return 1;
7468 }
7469
7470 static int handle_pml_full(struct kvm_vcpu *vcpu)
7471 {
7472         unsigned long exit_qualification;
7473
7474         trace_kvm_pml_full(vcpu->vcpu_id);
7475
7476         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7477
7478         /*
7479          * PML buffer FULL happened while executing iret from NMI,
7480          * "blocked by NMI" bit has to be set before next VM entry.
7481          */
7482         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7483                         cpu_has_virtual_nmis() &&
7484                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7485                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7486                                 GUEST_INTR_STATE_NMI);
7487
7488         /*
7489          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7490          * here.., and there's no userspace involvement needed for PML.
7491          */
7492         return 1;
7493 }
7494
7495 static int handle_pcommit(struct kvm_vcpu *vcpu)
7496 {
7497         /* we never catch pcommit instruct for L1 guest. */
7498         WARN_ON(1);
7499         return 1;
7500 }
7501
7502 /*
7503  * The exit handlers return 1 if the exit was handled fully and guest execution
7504  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7505  * to be done to userspace and return 0.
7506  */
7507 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7508         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7509         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7510         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7511         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7512         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7513         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7514         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7515         [EXIT_REASON_CPUID]                   = handle_cpuid,
7516         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7517         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7518         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7519         [EXIT_REASON_HLT]                     = handle_halt,
7520         [EXIT_REASON_INVD]                    = handle_invd,
7521         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7522         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7523         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7524         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7525         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7526         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7527         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7528         [EXIT_REASON_VMREAD]                  = handle_vmread,
7529         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7530         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7531         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7532         [EXIT_REASON_VMON]                    = handle_vmon,
7533         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7534         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7535         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7536         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7537         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7538         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7539         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7540         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7541         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7542         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7543         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7544         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7545         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7546         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7547         [EXIT_REASON_INVEPT]                  = handle_invept,
7548         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7549         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7550         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7551         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7552         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7553 };
7554
7555 static const int kvm_vmx_max_exit_handlers =
7556         ARRAY_SIZE(kvm_vmx_exit_handlers);
7557
7558 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7559                                        struct vmcs12 *vmcs12)
7560 {
7561         unsigned long exit_qualification;
7562         gpa_t bitmap, last_bitmap;
7563         unsigned int port;
7564         int size;
7565         u8 b;
7566
7567         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7568                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7569
7570         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7571
7572         port = exit_qualification >> 16;
7573         size = (exit_qualification & 7) + 1;
7574
7575         last_bitmap = (gpa_t)-1;
7576         b = -1;
7577
7578         while (size > 0) {
7579                 if (port < 0x8000)
7580                         bitmap = vmcs12->io_bitmap_a;
7581                 else if (port < 0x10000)
7582                         bitmap = vmcs12->io_bitmap_b;
7583                 else
7584                         return true;
7585                 bitmap += (port & 0x7fff) / 8;
7586
7587                 if (last_bitmap != bitmap)
7588                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7589                                 return true;
7590                 if (b & (1 << (port & 7)))
7591                         return true;
7592
7593                 port++;
7594                 size--;
7595                 last_bitmap = bitmap;
7596         }
7597
7598         return false;
7599 }
7600
7601 /*
7602  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7603  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7604  * disinterest in the current event (read or write a specific MSR) by using an
7605  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7606  */
7607 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7608         struct vmcs12 *vmcs12, u32 exit_reason)
7609 {
7610         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7611         gpa_t bitmap;
7612
7613         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7614                 return true;
7615
7616         /*
7617          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7618          * for the four combinations of read/write and low/high MSR numbers.
7619          * First we need to figure out which of the four to use:
7620          */
7621         bitmap = vmcs12->msr_bitmap;
7622         if (exit_reason == EXIT_REASON_MSR_WRITE)
7623                 bitmap += 2048;
7624         if (msr_index >= 0xc0000000) {
7625                 msr_index -= 0xc0000000;
7626                 bitmap += 1024;
7627         }
7628
7629         /* Then read the msr_index'th bit from this bitmap: */
7630         if (msr_index < 1024*8) {
7631                 unsigned char b;
7632                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7633                         return true;
7634                 return 1 & (b >> (msr_index & 7));
7635         } else
7636                 return true; /* let L1 handle the wrong parameter */
7637 }
7638
7639 /*
7640  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7641  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7642  * intercept (via guest_host_mask etc.) the current event.
7643  */
7644 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7645         struct vmcs12 *vmcs12)
7646 {
7647         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7648         int cr = exit_qualification & 15;
7649         int reg = (exit_qualification >> 8) & 15;
7650         unsigned long val = kvm_register_readl(vcpu, reg);
7651
7652         switch ((exit_qualification >> 4) & 3) {
7653         case 0: /* mov to cr */
7654                 switch (cr) {
7655                 case 0:
7656                         if (vmcs12->cr0_guest_host_mask &
7657                             (val ^ vmcs12->cr0_read_shadow))
7658                                 return true;
7659                         break;
7660                 case 3:
7661                         if ((vmcs12->cr3_target_count >= 1 &&
7662                                         vmcs12->cr3_target_value0 == val) ||
7663                                 (vmcs12->cr3_target_count >= 2 &&
7664                                         vmcs12->cr3_target_value1 == val) ||
7665                                 (vmcs12->cr3_target_count >= 3 &&
7666                                         vmcs12->cr3_target_value2 == val) ||
7667                                 (vmcs12->cr3_target_count >= 4 &&
7668                                         vmcs12->cr3_target_value3 == val))
7669                                 return false;
7670                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7671                                 return true;
7672                         break;
7673                 case 4:
7674                         if (vmcs12->cr4_guest_host_mask &
7675                             (vmcs12->cr4_read_shadow ^ val))
7676                                 return true;
7677                         break;
7678                 case 8:
7679                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7680                                 return true;
7681                         break;
7682                 }
7683                 break;
7684         case 2: /* clts */
7685                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7686                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7687                         return true;
7688                 break;
7689         case 1: /* mov from cr */
7690                 switch (cr) {
7691                 case 3:
7692                         if (vmcs12->cpu_based_vm_exec_control &
7693                             CPU_BASED_CR3_STORE_EXITING)
7694                                 return true;
7695                         break;
7696                 case 8:
7697                         if (vmcs12->cpu_based_vm_exec_control &
7698                             CPU_BASED_CR8_STORE_EXITING)
7699                                 return true;
7700                         break;
7701                 }
7702                 break;
7703         case 3: /* lmsw */
7704                 /*
7705                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7706                  * cr0. Other attempted changes are ignored, with no exit.
7707                  */
7708                 if (vmcs12->cr0_guest_host_mask & 0xe &
7709                     (val ^ vmcs12->cr0_read_shadow))
7710                         return true;
7711                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7712                     !(vmcs12->cr0_read_shadow & 0x1) &&
7713                     (val & 0x1))
7714                         return true;
7715                 break;
7716         }
7717         return false;
7718 }
7719
7720 /*
7721  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7722  * should handle it ourselves in L0 (and then continue L2). Only call this
7723  * when in is_guest_mode (L2).
7724  */
7725 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7726 {
7727         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7728         struct vcpu_vmx *vmx = to_vmx(vcpu);
7729         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7730         u32 exit_reason = vmx->exit_reason;
7731
7732         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7733                                 vmcs_readl(EXIT_QUALIFICATION),
7734                                 vmx->idt_vectoring_info,
7735                                 intr_info,
7736                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7737                                 KVM_ISA_VMX);
7738
7739         if (vmx->nested.nested_run_pending)
7740                 return false;
7741
7742         if (unlikely(vmx->fail)) {
7743                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7744                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7745                 return true;
7746         }
7747
7748         switch (exit_reason) {
7749         case EXIT_REASON_EXCEPTION_NMI:
7750                 if (!is_exception(intr_info))
7751                         return false;
7752                 else if (is_page_fault(intr_info))
7753                         return enable_ept;
7754                 else if (is_no_device(intr_info) &&
7755                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7756                         return false;
7757                 else if (is_debug(intr_info) &&
7758                          vcpu->guest_debug &
7759                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7760                         return false;
7761                 else if (is_breakpoint(intr_info) &&
7762                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7763                         return false;
7764                 return vmcs12->exception_bitmap &
7765                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7766         case EXIT_REASON_EXTERNAL_INTERRUPT:
7767                 return false;
7768         case EXIT_REASON_TRIPLE_FAULT:
7769                 return true;
7770         case EXIT_REASON_PENDING_INTERRUPT:
7771                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7772         case EXIT_REASON_NMI_WINDOW:
7773                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7774         case EXIT_REASON_TASK_SWITCH:
7775                 return true;
7776         case EXIT_REASON_CPUID:
7777                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7778                         return false;
7779                 return true;
7780         case EXIT_REASON_HLT:
7781                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7782         case EXIT_REASON_INVD:
7783                 return true;
7784         case EXIT_REASON_INVLPG:
7785                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7786         case EXIT_REASON_RDPMC:
7787                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7788         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7789                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7790         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7791         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7792         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7793         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7794         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7795         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7796                 /*
7797                  * VMX instructions trap unconditionally. This allows L1 to
7798                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7799                  */
7800                 return true;
7801         case EXIT_REASON_CR_ACCESS:
7802                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7803         case EXIT_REASON_DR_ACCESS:
7804                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7805         case EXIT_REASON_IO_INSTRUCTION:
7806                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7807         case EXIT_REASON_MSR_READ:
7808         case EXIT_REASON_MSR_WRITE:
7809                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7810         case EXIT_REASON_INVALID_STATE:
7811                 return true;
7812         case EXIT_REASON_MWAIT_INSTRUCTION:
7813                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7814         case EXIT_REASON_MONITOR_TRAP_FLAG:
7815                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7816         case EXIT_REASON_MONITOR_INSTRUCTION:
7817                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7818         case EXIT_REASON_PAUSE_INSTRUCTION:
7819                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7820                         nested_cpu_has2(vmcs12,
7821                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7822         case EXIT_REASON_MCE_DURING_VMENTRY:
7823                 return false;
7824         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7825                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7826         case EXIT_REASON_APIC_ACCESS:
7827                 return nested_cpu_has2(vmcs12,
7828                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7829         case EXIT_REASON_APIC_WRITE:
7830         case EXIT_REASON_EOI_INDUCED:
7831                 /* apic_write and eoi_induced should exit unconditionally. */
7832                 return true;
7833         case EXIT_REASON_EPT_VIOLATION:
7834                 /*
7835                  * L0 always deals with the EPT violation. If nested EPT is
7836                  * used, and the nested mmu code discovers that the address is
7837                  * missing in the guest EPT table (EPT12), the EPT violation
7838                  * will be injected with nested_ept_inject_page_fault()
7839                  */
7840                 return false;
7841         case EXIT_REASON_EPT_MISCONFIG:
7842                 /*
7843                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7844                  * table (shadow on EPT) or a merged EPT table that L0 built
7845                  * (EPT on EPT). So any problems with the structure of the
7846                  * table is L0's fault.
7847                  */
7848                 return false;
7849         case EXIT_REASON_WBINVD:
7850                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7851         case EXIT_REASON_XSETBV:
7852                 return true;
7853         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7854                 /*
7855                  * This should never happen, since it is not possible to
7856                  * set XSS to a non-zero value---neither in L1 nor in L2.
7857                  * If if it were, XSS would have to be checked against
7858                  * the XSS exit bitmap in vmcs12.
7859                  */
7860                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7861         case EXIT_REASON_PCOMMIT:
7862                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7863         default:
7864                 return true;
7865         }
7866 }
7867
7868 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7869 {
7870         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7871         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7872 }
7873
7874 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7875 {
7876         struct page *pml_pg;
7877
7878         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7879         if (!pml_pg)
7880                 return -ENOMEM;
7881
7882         vmx->pml_pg = pml_pg;
7883
7884         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7885         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7886
7887         return 0;
7888 }
7889
7890 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7891 {
7892         if (vmx->pml_pg) {
7893                 __free_page(vmx->pml_pg);
7894                 vmx->pml_pg = NULL;
7895         }
7896 }
7897
7898 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7899 {
7900         struct vcpu_vmx *vmx = to_vmx(vcpu);
7901         u64 *pml_buf;
7902         u16 pml_idx;
7903
7904         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7905
7906         /* Do nothing if PML buffer is empty */
7907         if (pml_idx == (PML_ENTITY_NUM - 1))
7908                 return;
7909
7910         /* PML index always points to next available PML buffer entity */
7911         if (pml_idx >= PML_ENTITY_NUM)
7912                 pml_idx = 0;
7913         else
7914                 pml_idx++;
7915
7916         pml_buf = page_address(vmx->pml_pg);
7917         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7918                 u64 gpa;
7919
7920                 gpa = pml_buf[pml_idx];
7921                 WARN_ON(gpa & (PAGE_SIZE - 1));
7922                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7923         }
7924
7925         /* reset PML index */
7926         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7927 }
7928
7929 /*
7930  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7931  * Called before reporting dirty_bitmap to userspace.
7932  */
7933 static void kvm_flush_pml_buffers(struct kvm *kvm)
7934 {
7935         int i;
7936         struct kvm_vcpu *vcpu;
7937         /*
7938          * We only need to kick vcpu out of guest mode here, as PML buffer
7939          * is flushed at beginning of all VMEXITs, and it's obvious that only
7940          * vcpus running in guest are possible to have unflushed GPAs in PML
7941          * buffer.
7942          */
7943         kvm_for_each_vcpu(i, vcpu, kvm)
7944                 kvm_vcpu_kick(vcpu);
7945 }
7946
7947 static void vmx_dump_sel(char *name, uint32_t sel)
7948 {
7949         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7950                name, vmcs_read32(sel),
7951                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7952                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7953                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7954 }
7955
7956 static void vmx_dump_dtsel(char *name, uint32_t limit)
7957 {
7958         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7959                name, vmcs_read32(limit),
7960                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7961 }
7962
7963 static void dump_vmcs(void)
7964 {
7965         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7966         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7967         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7968         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7969         u32 secondary_exec_control = 0;
7970         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7971         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7972         int i, n;
7973
7974         if (cpu_has_secondary_exec_ctrls())
7975                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7976
7977         pr_err("*** Guest State ***\n");
7978         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7979                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7980                vmcs_readl(CR0_GUEST_HOST_MASK));
7981         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7982                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7983         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7984         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7985             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7986         {
7987                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
7988                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
7989                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
7990                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
7991         }
7992         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7993                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7994         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7995                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7996         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7997                vmcs_readl(GUEST_SYSENTER_ESP),
7998                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7999         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8000         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8001         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8002         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8003         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8004         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8005         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8006         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8007         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8008         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8009         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8010             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8011                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8012                        efer, vmcs_read64(GUEST_IA32_PAT));
8013         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8014                vmcs_read64(GUEST_IA32_DEBUGCTL),
8015                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8016         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8017                 pr_err("PerfGlobCtl = 0x%016llx\n",
8018                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8019         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8020                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8021         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8022                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8023                vmcs_read32(GUEST_ACTIVITY_STATE));
8024         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8025                 pr_err("InterruptStatus = %04x\n",
8026                        vmcs_read16(GUEST_INTR_STATUS));
8027
8028         pr_err("*** Host State ***\n");
8029         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8030                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8031         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8032                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8033                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8034                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8035                vmcs_read16(HOST_TR_SELECTOR));
8036         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8037                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8038                vmcs_readl(HOST_TR_BASE));
8039         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8040                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8041         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8042                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8043                vmcs_readl(HOST_CR4));
8044         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8045                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8046                vmcs_read32(HOST_IA32_SYSENTER_CS),
8047                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8048         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8049                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8050                        vmcs_read64(HOST_IA32_EFER),
8051                        vmcs_read64(HOST_IA32_PAT));
8052         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8053                 pr_err("PerfGlobCtl = 0x%016llx\n",
8054                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8055
8056         pr_err("*** Control State ***\n");
8057         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8058                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8059         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8060         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8061                vmcs_read32(EXCEPTION_BITMAP),
8062                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8063                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8064         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8065                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8066                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8067                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8068         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8069                vmcs_read32(VM_EXIT_INTR_INFO),
8070                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8071                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8072         pr_err("        reason=%08x qualification=%016lx\n",
8073                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8074         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8075                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8076                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8077         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8078         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8079                 pr_err("TSC Multiplier = 0x%016llx\n",
8080                        vmcs_read64(TSC_MULTIPLIER));
8081         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8082                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8083         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8084                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8085         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8086                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8087         n = vmcs_read32(CR3_TARGET_COUNT);
8088         for (i = 0; i + 1 < n; i += 4)
8089                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8090                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8091                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8092         if (i < n)
8093                 pr_err("CR3 target%u=%016lx\n",
8094                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8095         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8096                 pr_err("PLE Gap=%08x Window=%08x\n",
8097                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8098         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8099                 pr_err("Virtual processor ID = 0x%04x\n",
8100                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8101 }
8102
8103 /*
8104  * The guest has exited.  See if we can fix it or if we need userspace
8105  * assistance.
8106  */
8107 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8108 {
8109         struct vcpu_vmx *vmx = to_vmx(vcpu);
8110         u32 exit_reason = vmx->exit_reason;
8111         u32 vectoring_info = vmx->idt_vectoring_info;
8112
8113         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8114
8115         /*
8116          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8117          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8118          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8119          * mode as if vcpus is in root mode, the PML buffer must has been
8120          * flushed already.
8121          */
8122         if (enable_pml)
8123                 vmx_flush_pml_buffer(vcpu);
8124
8125         /* If guest state is invalid, start emulating */
8126         if (vmx->emulation_required)
8127                 return handle_invalid_guest_state(vcpu);
8128
8129         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8130                 nested_vmx_vmexit(vcpu, exit_reason,
8131                                   vmcs_read32(VM_EXIT_INTR_INFO),
8132                                   vmcs_readl(EXIT_QUALIFICATION));
8133                 return 1;
8134         }
8135
8136         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8137                 dump_vmcs();
8138                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8139                 vcpu->run->fail_entry.hardware_entry_failure_reason
8140                         = exit_reason;
8141                 return 0;
8142         }
8143
8144         if (unlikely(vmx->fail)) {
8145                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8146                 vcpu->run->fail_entry.hardware_entry_failure_reason
8147                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8148                 return 0;
8149         }
8150
8151         /*
8152          * Note:
8153          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8154          * delivery event since it indicates guest is accessing MMIO.
8155          * The vm-exit can be triggered again after return to guest that
8156          * will cause infinite loop.
8157          */
8158         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8159                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8160                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8161                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8162                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8163                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8164                 vcpu->run->internal.ndata = 2;
8165                 vcpu->run->internal.data[0] = vectoring_info;
8166                 vcpu->run->internal.data[1] = exit_reason;
8167                 return 0;
8168         }
8169
8170         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8171             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8172                                         get_vmcs12(vcpu))))) {
8173                 if (vmx_interrupt_allowed(vcpu)) {
8174                         vmx->soft_vnmi_blocked = 0;
8175                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8176                            vcpu->arch.nmi_pending) {
8177                         /*
8178                          * This CPU don't support us in finding the end of an
8179                          * NMI-blocked window if the guest runs with IRQs
8180                          * disabled. So we pull the trigger after 1 s of
8181                          * futile waiting, but inform the user about this.
8182                          */
8183                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8184                                "state on VCPU %d after 1 s timeout\n",
8185                                __func__, vcpu->vcpu_id);
8186                         vmx->soft_vnmi_blocked = 0;
8187                 }
8188         }
8189
8190         if (exit_reason < kvm_vmx_max_exit_handlers
8191             && kvm_vmx_exit_handlers[exit_reason])
8192                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8193         else {
8194                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8195                 kvm_queue_exception(vcpu, UD_VECTOR);
8196                 return 1;
8197         }
8198 }
8199
8200 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8201 {
8202         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8203
8204         if (is_guest_mode(vcpu) &&
8205                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8206                 return;
8207
8208         if (irr == -1 || tpr < irr) {
8209                 vmcs_write32(TPR_THRESHOLD, 0);
8210                 return;
8211         }
8212
8213         vmcs_write32(TPR_THRESHOLD, irr);
8214 }
8215
8216 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8217 {
8218         u32 sec_exec_control;
8219
8220         /*
8221          * There is not point to enable virtualize x2apic without enable
8222          * apicv
8223          */
8224         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8225                                 !kvm_vcpu_apicv_active(vcpu))
8226                 return;
8227
8228         if (!cpu_need_tpr_shadow(vcpu))
8229                 return;
8230
8231         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8232
8233         if (set) {
8234                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8235                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8236         } else {
8237                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8238                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8239         }
8240         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8241
8242         vmx_set_msr_bitmap(vcpu);
8243 }
8244
8245 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8246 {
8247         struct vcpu_vmx *vmx = to_vmx(vcpu);
8248
8249         /*
8250          * Currently we do not handle the nested case where L2 has an
8251          * APIC access page of its own; that page is still pinned.
8252          * Hence, we skip the case where the VCPU is in guest mode _and_
8253          * L1 prepared an APIC access page for L2.
8254          *
8255          * For the case where L1 and L2 share the same APIC access page
8256          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8257          * in the vmcs12), this function will only update either the vmcs01
8258          * or the vmcs02.  If the former, the vmcs02 will be updated by
8259          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8260          * the next L2->L1 exit.
8261          */
8262         if (!is_guest_mode(vcpu) ||
8263             !nested_cpu_has2(vmx->nested.current_vmcs12,
8264                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8265                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8266 }
8267
8268 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8269 {
8270         u16 status;
8271         u8 old;
8272
8273         if (isr == -1)
8274                 isr = 0;
8275
8276         status = vmcs_read16(GUEST_INTR_STATUS);
8277         old = status >> 8;
8278         if (isr != old) {
8279                 status &= 0xff;
8280                 status |= isr << 8;
8281                 vmcs_write16(GUEST_INTR_STATUS, status);
8282         }
8283 }
8284
8285 static void vmx_set_rvi(int vector)
8286 {
8287         u16 status;
8288         u8 old;
8289
8290         if (vector == -1)
8291                 vector = 0;
8292
8293         status = vmcs_read16(GUEST_INTR_STATUS);
8294         old = (u8)status & 0xff;
8295         if ((u8)vector != old) {
8296                 status &= ~0xff;
8297                 status |= (u8)vector;
8298                 vmcs_write16(GUEST_INTR_STATUS, status);
8299         }
8300 }
8301
8302 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8303 {
8304         if (!is_guest_mode(vcpu)) {
8305                 vmx_set_rvi(max_irr);
8306                 return;
8307         }
8308
8309         if (max_irr == -1)
8310                 return;
8311
8312         /*
8313          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8314          * handles it.
8315          */
8316         if (nested_exit_on_intr(vcpu))
8317                 return;
8318
8319         /*
8320          * Else, fall back to pre-APICv interrupt injection since L2
8321          * is run without virtual interrupt delivery.
8322          */
8323         if (!kvm_event_needs_reinjection(vcpu) &&
8324             vmx_interrupt_allowed(vcpu)) {
8325                 kvm_queue_interrupt(vcpu, max_irr, false);
8326                 vmx_inject_irq(vcpu);
8327         }
8328 }
8329
8330 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8331 {
8332         if (!kvm_vcpu_apicv_active(vcpu))
8333                 return;
8334
8335         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8336         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8337         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8338         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8339 }
8340
8341 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8342 {
8343         u32 exit_intr_info;
8344
8345         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8346               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8347                 return;
8348
8349         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8350         exit_intr_info = vmx->exit_intr_info;
8351
8352         /* Handle machine checks before interrupts are enabled */
8353         if (is_machine_check(exit_intr_info))
8354                 kvm_machine_check();
8355
8356         /* We need to handle NMIs before interrupts are enabled */
8357         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8358             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8359                 kvm_before_handle_nmi(&vmx->vcpu);
8360                 asm("int $2");
8361                 kvm_after_handle_nmi(&vmx->vcpu);
8362         }
8363 }
8364
8365 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8366 {
8367         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8368
8369         /*
8370          * If external interrupt exists, IF bit is set in rflags/eflags on the
8371          * interrupt stack frame, and interrupt will be enabled on a return
8372          * from interrupt handler.
8373          */
8374         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8375                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8376                 unsigned int vector;
8377                 unsigned long entry;
8378                 gate_desc *desc;
8379                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8380 #ifdef CONFIG_X86_64
8381                 unsigned long tmp;
8382 #endif
8383
8384                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8385                 desc = (gate_desc *)vmx->host_idt_base + vector;
8386                 entry = gate_offset(*desc);
8387                 asm volatile(
8388 #ifdef CONFIG_X86_64
8389                         "mov %%" _ASM_SP ", %[sp]\n\t"
8390                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8391                         "push $%c[ss]\n\t"
8392                         "push %[sp]\n\t"
8393 #endif
8394                         "pushf\n\t"
8395                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8396                         __ASM_SIZE(push) " $%c[cs]\n\t"
8397                         "call *%[entry]\n\t"
8398                         :
8399 #ifdef CONFIG_X86_64
8400                         [sp]"=&r"(tmp)
8401 #endif
8402                         :
8403                         [entry]"r"(entry),
8404                         [ss]"i"(__KERNEL_DS),
8405                         [cs]"i"(__KERNEL_CS)
8406                         );
8407         } else
8408                 local_irq_enable();
8409 }
8410
8411 static bool vmx_has_high_real_mode_segbase(void)
8412 {
8413         return enable_unrestricted_guest || emulate_invalid_guest_state;
8414 }
8415
8416 static bool vmx_mpx_supported(void)
8417 {
8418         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8419                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8420 }
8421
8422 static bool vmx_xsaves_supported(void)
8423 {
8424         return vmcs_config.cpu_based_2nd_exec_ctrl &
8425                 SECONDARY_EXEC_XSAVES;
8426 }
8427
8428 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8429 {
8430         u32 exit_intr_info;
8431         bool unblock_nmi;
8432         u8 vector;
8433         bool idtv_info_valid;
8434
8435         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8436
8437         if (cpu_has_virtual_nmis()) {
8438                 if (vmx->nmi_known_unmasked)
8439                         return;
8440                 /*
8441                  * Can't use vmx->exit_intr_info since we're not sure what
8442                  * the exit reason is.
8443                  */
8444                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8445                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8446                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8447                 /*
8448                  * SDM 3: 27.7.1.2 (September 2008)
8449                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8450                  * a guest IRET fault.
8451                  * SDM 3: 23.2.2 (September 2008)
8452                  * Bit 12 is undefined in any of the following cases:
8453                  *  If the VM exit sets the valid bit in the IDT-vectoring
8454                  *   information field.
8455                  *  If the VM exit is due to a double fault.
8456                  */
8457                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8458                     vector != DF_VECTOR && !idtv_info_valid)
8459                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8460                                       GUEST_INTR_STATE_NMI);
8461                 else
8462                         vmx->nmi_known_unmasked =
8463                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8464                                   & GUEST_INTR_STATE_NMI);
8465         } else if (unlikely(vmx->soft_vnmi_blocked))
8466                 vmx->vnmi_blocked_time +=
8467                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8468 }
8469
8470 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8471                                       u32 idt_vectoring_info,
8472                                       int instr_len_field,
8473                                       int error_code_field)
8474 {
8475         u8 vector;
8476         int type;
8477         bool idtv_info_valid;
8478
8479         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8480
8481         vcpu->arch.nmi_injected = false;
8482         kvm_clear_exception_queue(vcpu);
8483         kvm_clear_interrupt_queue(vcpu);
8484
8485         if (!idtv_info_valid)
8486                 return;
8487
8488         kvm_make_request(KVM_REQ_EVENT, vcpu);
8489
8490         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8491         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8492
8493         switch (type) {
8494         case INTR_TYPE_NMI_INTR:
8495                 vcpu->arch.nmi_injected = true;
8496                 /*
8497                  * SDM 3: 27.7.1.2 (September 2008)
8498                  * Clear bit "block by NMI" before VM entry if a NMI
8499                  * delivery faulted.
8500                  */
8501                 vmx_set_nmi_mask(vcpu, false);
8502                 break;
8503         case INTR_TYPE_SOFT_EXCEPTION:
8504                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8505                 /* fall through */
8506         case INTR_TYPE_HARD_EXCEPTION:
8507                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8508                         u32 err = vmcs_read32(error_code_field);
8509                         kvm_requeue_exception_e(vcpu, vector, err);
8510                 } else
8511                         kvm_requeue_exception(vcpu, vector);
8512                 break;
8513         case INTR_TYPE_SOFT_INTR:
8514                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8515                 /* fall through */
8516         case INTR_TYPE_EXT_INTR:
8517                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8518                 break;
8519         default:
8520                 break;
8521         }
8522 }
8523
8524 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8525 {
8526         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8527                                   VM_EXIT_INSTRUCTION_LEN,
8528                                   IDT_VECTORING_ERROR_CODE);
8529 }
8530
8531 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8532 {
8533         __vmx_complete_interrupts(vcpu,
8534                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8535                                   VM_ENTRY_INSTRUCTION_LEN,
8536                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8537
8538         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8539 }
8540
8541 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8542 {
8543         int i, nr_msrs;
8544         struct perf_guest_switch_msr *msrs;
8545
8546         msrs = perf_guest_get_msrs(&nr_msrs);
8547
8548         if (!msrs)
8549                 return;
8550
8551         for (i = 0; i < nr_msrs; i++)
8552                 if (msrs[i].host == msrs[i].guest)
8553                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8554                 else
8555                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8556                                         msrs[i].host);
8557 }
8558
8559 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8560 {
8561         struct vcpu_vmx *vmx = to_vmx(vcpu);
8562         unsigned long debugctlmsr, cr4;
8563
8564         /* Record the guest's net vcpu time for enforced NMI injections. */
8565         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8566                 vmx->entry_time = ktime_get();
8567
8568         /* Don't enter VMX if guest state is invalid, let the exit handler
8569            start emulation until we arrive back to a valid state */
8570         if (vmx->emulation_required)
8571                 return;
8572
8573         if (vmx->ple_window_dirty) {
8574                 vmx->ple_window_dirty = false;
8575                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8576         }
8577
8578         if (vmx->nested.sync_shadow_vmcs) {
8579                 copy_vmcs12_to_shadow(vmx);
8580                 vmx->nested.sync_shadow_vmcs = false;
8581         }
8582
8583         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8584                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8585         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8586                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8587
8588         cr4 = cr4_read_shadow();
8589         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8590                 vmcs_writel(HOST_CR4, cr4);
8591                 vmx->host_state.vmcs_host_cr4 = cr4;
8592         }
8593
8594         /* When single-stepping over STI and MOV SS, we must clear the
8595          * corresponding interruptibility bits in the guest state. Otherwise
8596          * vmentry fails as it then expects bit 14 (BS) in pending debug
8597          * exceptions being set, but that's not correct for the guest debugging
8598          * case. */
8599         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8600                 vmx_set_interrupt_shadow(vcpu, 0);
8601
8602         atomic_switch_perf_msrs(vmx);
8603         debugctlmsr = get_debugctlmsr();
8604
8605         vmx->__launched = vmx->loaded_vmcs->launched;
8606         asm(
8607                 /* Store host registers */
8608                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8609                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8610                 "push %%" _ASM_CX " \n\t"
8611                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8612                 "je 1f \n\t"
8613                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8614                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8615                 "1: \n\t"
8616                 /* Reload cr2 if changed */
8617                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8618                 "mov %%cr2, %%" _ASM_DX " \n\t"
8619                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8620                 "je 2f \n\t"
8621                 "mov %%" _ASM_AX", %%cr2 \n\t"
8622                 "2: \n\t"
8623                 /* Check if vmlaunch of vmresume is needed */
8624                 "cmpl $0, %c[launched](%0) \n\t"
8625                 /* Load guest registers.  Don't clobber flags. */
8626                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8627                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8628                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8629                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8630                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8631                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8632 #ifdef CONFIG_X86_64
8633                 "mov %c[r8](%0),  %%r8  \n\t"
8634                 "mov %c[r9](%0),  %%r9  \n\t"
8635                 "mov %c[r10](%0), %%r10 \n\t"
8636                 "mov %c[r11](%0), %%r11 \n\t"
8637                 "mov %c[r12](%0), %%r12 \n\t"
8638                 "mov %c[r13](%0), %%r13 \n\t"
8639                 "mov %c[r14](%0), %%r14 \n\t"
8640                 "mov %c[r15](%0), %%r15 \n\t"
8641 #endif
8642                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8643
8644                 /* Enter guest mode */
8645                 "jne 1f \n\t"
8646                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8647                 "jmp 2f \n\t"
8648                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8649                 "2: "
8650                 /* Save guest registers, load host registers, keep flags */
8651                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8652                 "pop %0 \n\t"
8653                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8654                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8655                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8656                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8657                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8658                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8659                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8660 #ifdef CONFIG_X86_64
8661                 "mov %%r8,  %c[r8](%0) \n\t"
8662                 "mov %%r9,  %c[r9](%0) \n\t"
8663                 "mov %%r10, %c[r10](%0) \n\t"
8664                 "mov %%r11, %c[r11](%0) \n\t"
8665                 "mov %%r12, %c[r12](%0) \n\t"
8666                 "mov %%r13, %c[r13](%0) \n\t"
8667                 "mov %%r14, %c[r14](%0) \n\t"
8668                 "mov %%r15, %c[r15](%0) \n\t"
8669 #endif
8670                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8671                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8672
8673                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8674                 "setbe %c[fail](%0) \n\t"
8675                 ".pushsection .rodata \n\t"
8676                 ".global vmx_return \n\t"
8677                 "vmx_return: " _ASM_PTR " 2b \n\t"
8678                 ".popsection"
8679               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8680                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8681                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8682                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8683                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8684                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8685                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8686                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8687                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8688                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8689                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8690 #ifdef CONFIG_X86_64
8691                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8692                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8693                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8694                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8695                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8696                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8697                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8698                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8699 #endif
8700                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8701                 [wordsize]"i"(sizeof(ulong))
8702               : "cc", "memory"
8703 #ifdef CONFIG_X86_64
8704                 , "rax", "rbx", "rdi", "rsi"
8705                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8706 #else
8707                 , "eax", "ebx", "edi", "esi"
8708 #endif
8709               );
8710
8711         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8712         if (debugctlmsr)
8713                 update_debugctlmsr(debugctlmsr);
8714
8715 #ifndef CONFIG_X86_64
8716         /*
8717          * The sysexit path does not restore ds/es, so we must set them to
8718          * a reasonable value ourselves.
8719          *
8720          * We can't defer this to vmx_load_host_state() since that function
8721          * may be executed in interrupt context, which saves and restore segments
8722          * around it, nullifying its effect.
8723          */
8724         loadsegment(ds, __USER_DS);
8725         loadsegment(es, __USER_DS);
8726 #endif
8727
8728         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8729                                   | (1 << VCPU_EXREG_RFLAGS)
8730                                   | (1 << VCPU_EXREG_PDPTR)
8731                                   | (1 << VCPU_EXREG_SEGMENTS)
8732                                   | (1 << VCPU_EXREG_CR3));
8733         vcpu->arch.regs_dirty = 0;
8734
8735         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8736
8737         vmx->loaded_vmcs->launched = 1;
8738
8739         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8740
8741         /*
8742          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8743          * we did not inject a still-pending event to L1 now because of
8744          * nested_run_pending, we need to re-enable this bit.
8745          */
8746         if (vmx->nested.nested_run_pending)
8747                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8748
8749         vmx->nested.nested_run_pending = 0;
8750
8751         vmx_complete_atomic_exit(vmx);
8752         vmx_recover_nmi_blocking(vmx);
8753         vmx_complete_interrupts(vmx);
8754 }
8755
8756 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8757 {
8758         struct vcpu_vmx *vmx = to_vmx(vcpu);
8759         int cpu;
8760
8761         if (vmx->loaded_vmcs == &vmx->vmcs01)
8762                 return;
8763
8764         cpu = get_cpu();
8765         vmx->loaded_vmcs = &vmx->vmcs01;
8766         vmx_vcpu_put(vcpu);
8767         vmx_vcpu_load(vcpu, cpu);
8768         vcpu->cpu = cpu;
8769         put_cpu();
8770 }
8771
8772 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8773 {
8774         struct vcpu_vmx *vmx = to_vmx(vcpu);
8775
8776         if (enable_pml)
8777                 vmx_destroy_pml_buffer(vmx);
8778         free_vpid(vmx->vpid);
8779         leave_guest_mode(vcpu);
8780         vmx_load_vmcs01(vcpu);
8781         free_nested(vmx);
8782         free_loaded_vmcs(vmx->loaded_vmcs);
8783         kfree(vmx->guest_msrs);
8784         kvm_vcpu_uninit(vcpu);
8785         kmem_cache_free(kvm_vcpu_cache, vmx);
8786 }
8787
8788 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8789 {
8790         int err;
8791         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8792         int cpu;
8793
8794         if (!vmx)
8795                 return ERR_PTR(-ENOMEM);
8796
8797         vmx->vpid = allocate_vpid();
8798
8799         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8800         if (err)
8801                 goto free_vcpu;
8802
8803         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8804         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8805                      > PAGE_SIZE);
8806
8807         err = -ENOMEM;
8808         if (!vmx->guest_msrs) {
8809                 goto uninit_vcpu;
8810         }
8811
8812         vmx->loaded_vmcs = &vmx->vmcs01;
8813         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8814         if (!vmx->loaded_vmcs->vmcs)
8815                 goto free_msrs;
8816         if (!vmm_exclusive)
8817                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8818         loaded_vmcs_init(vmx->loaded_vmcs);
8819         if (!vmm_exclusive)
8820                 kvm_cpu_vmxoff();
8821
8822         cpu = get_cpu();
8823         vmx_vcpu_load(&vmx->vcpu, cpu);
8824         vmx->vcpu.cpu = cpu;
8825         err = vmx_vcpu_setup(vmx);
8826         vmx_vcpu_put(&vmx->vcpu);
8827         put_cpu();
8828         if (err)
8829                 goto free_vmcs;
8830         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8831                 err = alloc_apic_access_page(kvm);
8832                 if (err)
8833                         goto free_vmcs;
8834         }
8835
8836         if (enable_ept) {
8837                 if (!kvm->arch.ept_identity_map_addr)
8838                         kvm->arch.ept_identity_map_addr =
8839                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8840                 err = init_rmode_identity_map(kvm);
8841                 if (err)
8842                         goto free_vmcs;
8843         }
8844
8845         if (nested) {
8846                 nested_vmx_setup_ctls_msrs(vmx);
8847                 vmx->nested.vpid02 = allocate_vpid();
8848         }
8849
8850         vmx->nested.posted_intr_nv = -1;
8851         vmx->nested.current_vmptr = -1ull;
8852         vmx->nested.current_vmcs12 = NULL;
8853
8854         /*
8855          * If PML is turned on, failure on enabling PML just results in failure
8856          * of creating the vcpu, therefore we can simplify PML logic (by
8857          * avoiding dealing with cases, such as enabling PML partially on vcpus
8858          * for the guest, etc.
8859          */
8860         if (enable_pml) {
8861                 err = vmx_create_pml_buffer(vmx);
8862                 if (err)
8863                         goto free_vmcs;
8864         }
8865
8866         return &vmx->vcpu;
8867
8868 free_vmcs:
8869         free_vpid(vmx->nested.vpid02);
8870         free_loaded_vmcs(vmx->loaded_vmcs);
8871 free_msrs:
8872         kfree(vmx->guest_msrs);
8873 uninit_vcpu:
8874         kvm_vcpu_uninit(&vmx->vcpu);
8875 free_vcpu:
8876         free_vpid(vmx->vpid);
8877         kmem_cache_free(kvm_vcpu_cache, vmx);
8878         return ERR_PTR(err);
8879 }
8880
8881 static void __init vmx_check_processor_compat(void *rtn)
8882 {
8883         struct vmcs_config vmcs_conf;
8884
8885         *(int *)rtn = 0;
8886         if (setup_vmcs_config(&vmcs_conf) < 0)
8887                 *(int *)rtn = -EIO;
8888         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8889                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8890                                 smp_processor_id());
8891                 *(int *)rtn = -EIO;
8892         }
8893 }
8894
8895 static int get_ept_level(void)
8896 {
8897         return VMX_EPT_DEFAULT_GAW + 1;
8898 }
8899
8900 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8901 {
8902         u8 cache;
8903         u64 ipat = 0;
8904
8905         /* For VT-d and EPT combination
8906          * 1. MMIO: always map as UC
8907          * 2. EPT with VT-d:
8908          *   a. VT-d without snooping control feature: can't guarantee the
8909          *      result, try to trust guest.
8910          *   b. VT-d with snooping control feature: snooping control feature of
8911          *      VT-d engine can guarantee the cache correctness. Just set it
8912          *      to WB to keep consistent with host. So the same as item 3.
8913          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8914          *    consistent with host MTRR
8915          */
8916         if (is_mmio) {
8917                 cache = MTRR_TYPE_UNCACHABLE;
8918                 goto exit;
8919         }
8920
8921         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8922                 ipat = VMX_EPT_IPAT_BIT;
8923                 cache = MTRR_TYPE_WRBACK;
8924                 goto exit;
8925         }
8926
8927         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8928                 ipat = VMX_EPT_IPAT_BIT;
8929                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8930                         cache = MTRR_TYPE_WRBACK;
8931                 else
8932                         cache = MTRR_TYPE_UNCACHABLE;
8933                 goto exit;
8934         }
8935
8936         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8937
8938 exit:
8939         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8940 }
8941
8942 static int vmx_get_lpage_level(void)
8943 {
8944         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8945                 return PT_DIRECTORY_LEVEL;
8946         else
8947                 /* For shadow and EPT supported 1GB page */
8948                 return PT_PDPE_LEVEL;
8949 }
8950
8951 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8952 {
8953         /*
8954          * These bits in the secondary execution controls field
8955          * are dynamic, the others are mostly based on the hypervisor
8956          * architecture and the guest's CPUID.  Do not touch the
8957          * dynamic bits.
8958          */
8959         u32 mask =
8960                 SECONDARY_EXEC_SHADOW_VMCS |
8961                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8962                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8963
8964         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8965
8966         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8967                      (new_ctl & ~mask) | (cur_ctl & mask));
8968 }
8969
8970 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8971 {
8972         struct kvm_cpuid_entry2 *best;
8973         struct vcpu_vmx *vmx = to_vmx(vcpu);
8974         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8975
8976         if (vmx_rdtscp_supported()) {
8977                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8978                 if (!rdtscp_enabled)
8979                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8980
8981                 if (nested) {
8982                         if (rdtscp_enabled)
8983                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8984                                         SECONDARY_EXEC_RDTSCP;
8985                         else
8986                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8987                                         ~SECONDARY_EXEC_RDTSCP;
8988                 }
8989         }
8990
8991         /* Exposing INVPCID only when PCID is exposed */
8992         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8993         if (vmx_invpcid_supported() &&
8994             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8995             !guest_cpuid_has_pcid(vcpu))) {
8996                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8997
8998                 if (best)
8999                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9000         }
9001
9002         if (cpu_has_secondary_exec_ctrls())
9003                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9004
9005         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9006                 if (guest_cpuid_has_pcommit(vcpu))
9007                         vmx->nested.nested_vmx_secondary_ctls_high |=
9008                                 SECONDARY_EXEC_PCOMMIT;
9009                 else
9010                         vmx->nested.nested_vmx_secondary_ctls_high &=
9011                                 ~SECONDARY_EXEC_PCOMMIT;
9012         }
9013 }
9014
9015 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9016 {
9017         if (func == 1 && nested)
9018                 entry->ecx |= bit(X86_FEATURE_VMX);
9019 }
9020
9021 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9022                 struct x86_exception *fault)
9023 {
9024         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9025         u32 exit_reason;
9026
9027         if (fault->error_code & PFERR_RSVD_MASK)
9028                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9029         else
9030                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9031         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9032         vmcs12->guest_physical_address = fault->address;
9033 }
9034
9035 /* Callbacks for nested_ept_init_mmu_context: */
9036
9037 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9038 {
9039         /* return the page table to be shadowed - in our case, EPT12 */
9040         return get_vmcs12(vcpu)->ept_pointer;
9041 }
9042
9043 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9044 {
9045         WARN_ON(mmu_is_nested(vcpu));
9046         kvm_init_shadow_ept_mmu(vcpu,
9047                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9048                         VMX_EPT_EXECUTE_ONLY_BIT);
9049         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9050         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9051         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9052
9053         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9054 }
9055
9056 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9057 {
9058         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9059 }
9060
9061 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9062                                             u16 error_code)
9063 {
9064         bool inequality, bit;
9065
9066         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9067         inequality =
9068                 (error_code & vmcs12->page_fault_error_code_mask) !=
9069                  vmcs12->page_fault_error_code_match;
9070         return inequality ^ bit;
9071 }
9072
9073 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9074                 struct x86_exception *fault)
9075 {
9076         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9077
9078         WARN_ON(!is_guest_mode(vcpu));
9079
9080         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9081                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9082                                   vmcs_read32(VM_EXIT_INTR_INFO),
9083                                   vmcs_readl(EXIT_QUALIFICATION));
9084         else
9085                 kvm_inject_page_fault(vcpu, fault);
9086 }
9087
9088 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9089                                         struct vmcs12 *vmcs12)
9090 {
9091         struct vcpu_vmx *vmx = to_vmx(vcpu);
9092         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9093
9094         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9095                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9096                     vmcs12->apic_access_addr >> maxphyaddr)
9097                         return false;
9098
9099                 /*
9100                  * Translate L1 physical address to host physical
9101                  * address for vmcs02. Keep the page pinned, so this
9102                  * physical address remains valid. We keep a reference
9103                  * to it so we can release it later.
9104                  */
9105                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9106                         nested_release_page(vmx->nested.apic_access_page);
9107                 vmx->nested.apic_access_page =
9108                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9109         }
9110
9111         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9112                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9113                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9114                         return false;
9115
9116                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9117                         nested_release_page(vmx->nested.virtual_apic_page);
9118                 vmx->nested.virtual_apic_page =
9119                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9120
9121                 /*
9122                  * Failing the vm entry is _not_ what the processor does
9123                  * but it's basically the only possibility we have.
9124                  * We could still enter the guest if CR8 load exits are
9125                  * enabled, CR8 store exits are enabled, and virtualize APIC
9126                  * access is disabled; in this case the processor would never
9127                  * use the TPR shadow and we could simply clear the bit from
9128                  * the execution control.  But such a configuration is useless,
9129                  * so let's keep the code simple.
9130                  */
9131                 if (!vmx->nested.virtual_apic_page)
9132                         return false;
9133         }
9134
9135         if (nested_cpu_has_posted_intr(vmcs12)) {
9136                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9137                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9138                         return false;
9139
9140                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9141                         kunmap(vmx->nested.pi_desc_page);
9142                         nested_release_page(vmx->nested.pi_desc_page);
9143                 }
9144                 vmx->nested.pi_desc_page =
9145                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9146                 if (!vmx->nested.pi_desc_page)
9147                         return false;
9148
9149                 vmx->nested.pi_desc =
9150                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9151                 if (!vmx->nested.pi_desc) {
9152                         nested_release_page_clean(vmx->nested.pi_desc_page);
9153                         return false;
9154                 }
9155                 vmx->nested.pi_desc =
9156                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9157                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9158                         (PAGE_SIZE - 1)));
9159         }
9160
9161         return true;
9162 }
9163
9164 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9165 {
9166         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9167         struct vcpu_vmx *vmx = to_vmx(vcpu);
9168
9169         if (vcpu->arch.virtual_tsc_khz == 0)
9170                 return;
9171
9172         /* Make sure short timeouts reliably trigger an immediate vmexit.
9173          * hrtimer_start does not guarantee this. */
9174         if (preemption_timeout <= 1) {
9175                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9176                 return;
9177         }
9178
9179         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9180         preemption_timeout *= 1000000;
9181         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9182         hrtimer_start(&vmx->nested.preemption_timer,
9183                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9184 }
9185
9186 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9187                                                 struct vmcs12 *vmcs12)
9188 {
9189         int maxphyaddr;
9190         u64 addr;
9191
9192         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9193                 return 0;
9194
9195         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9196                 WARN_ON(1);
9197                 return -EINVAL;
9198         }
9199         maxphyaddr = cpuid_maxphyaddr(vcpu);
9200
9201         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9202            ((addr + PAGE_SIZE) >> maxphyaddr))
9203                 return -EINVAL;
9204
9205         return 0;
9206 }
9207
9208 /*
9209  * Merge L0's and L1's MSR bitmap, return false to indicate that
9210  * we do not use the hardware.
9211  */
9212 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9213                                                struct vmcs12 *vmcs12)
9214 {
9215         int msr;
9216         struct page *page;
9217         unsigned long *msr_bitmap;
9218
9219         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9220                 return false;
9221
9222         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9223         if (!page) {
9224                 WARN_ON(1);
9225                 return false;
9226         }
9227         msr_bitmap = (unsigned long *)kmap(page);
9228         if (!msr_bitmap) {
9229                 nested_release_page_clean(page);
9230                 WARN_ON(1);
9231                 return false;
9232         }
9233
9234         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9235                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9236                         for (msr = 0x800; msr <= 0x8ff; msr++)
9237                                 nested_vmx_disable_intercept_for_msr(
9238                                         msr_bitmap,
9239                                         vmx_msr_bitmap_nested,
9240                                         msr, MSR_TYPE_R);
9241                 /* TPR is allowed */
9242                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9243                                 vmx_msr_bitmap_nested,
9244                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9245                                 MSR_TYPE_R | MSR_TYPE_W);
9246                 if (nested_cpu_has_vid(vmcs12)) {
9247                         /* EOI and self-IPI are allowed */
9248                         nested_vmx_disable_intercept_for_msr(
9249                                 msr_bitmap,
9250                                 vmx_msr_bitmap_nested,
9251                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9252                                 MSR_TYPE_W);
9253                         nested_vmx_disable_intercept_for_msr(
9254                                 msr_bitmap,
9255                                 vmx_msr_bitmap_nested,
9256                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9257                                 MSR_TYPE_W);
9258                 }
9259         } else {
9260                 /*
9261                  * Enable reading intercept of all the x2apic
9262                  * MSRs. We should not rely on vmcs12 to do any
9263                  * optimizations here, it may have been modified
9264                  * by L1.
9265                  */
9266                 for (msr = 0x800; msr <= 0x8ff; msr++)
9267                         __vmx_enable_intercept_for_msr(
9268                                 vmx_msr_bitmap_nested,
9269                                 msr,
9270                                 MSR_TYPE_R);
9271
9272                 __vmx_enable_intercept_for_msr(
9273                                 vmx_msr_bitmap_nested,
9274                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9275                                 MSR_TYPE_W);
9276                 __vmx_enable_intercept_for_msr(
9277                                 vmx_msr_bitmap_nested,
9278                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9279                                 MSR_TYPE_W);
9280                 __vmx_enable_intercept_for_msr(
9281                                 vmx_msr_bitmap_nested,
9282                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9283                                 MSR_TYPE_W);
9284         }
9285         kunmap(page);
9286         nested_release_page_clean(page);
9287
9288         return true;
9289 }
9290
9291 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9292                                            struct vmcs12 *vmcs12)
9293 {
9294         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9295             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9296             !nested_cpu_has_vid(vmcs12) &&
9297             !nested_cpu_has_posted_intr(vmcs12))
9298                 return 0;
9299
9300         /*
9301          * If virtualize x2apic mode is enabled,
9302          * virtualize apic access must be disabled.
9303          */
9304         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9305             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9306                 return -EINVAL;
9307
9308         /*
9309          * If virtual interrupt delivery is enabled,
9310          * we must exit on external interrupts.
9311          */
9312         if (nested_cpu_has_vid(vmcs12) &&
9313            !nested_exit_on_intr(vcpu))
9314                 return -EINVAL;
9315
9316         /*
9317          * bits 15:8 should be zero in posted_intr_nv,
9318          * the descriptor address has been already checked
9319          * in nested_get_vmcs12_pages.
9320          */
9321         if (nested_cpu_has_posted_intr(vmcs12) &&
9322            (!nested_cpu_has_vid(vmcs12) ||
9323             !nested_exit_intr_ack_set(vcpu) ||
9324             vmcs12->posted_intr_nv & 0xff00))
9325                 return -EINVAL;
9326
9327         /* tpr shadow is needed by all apicv features. */
9328         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9329                 return -EINVAL;
9330
9331         return 0;
9332 }
9333
9334 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9335                                        unsigned long count_field,
9336                                        unsigned long addr_field)
9337 {
9338         int maxphyaddr;
9339         u64 count, addr;
9340
9341         if (vmcs12_read_any(vcpu, count_field, &count) ||
9342             vmcs12_read_any(vcpu, addr_field, &addr)) {
9343                 WARN_ON(1);
9344                 return -EINVAL;
9345         }
9346         if (count == 0)
9347                 return 0;
9348         maxphyaddr = cpuid_maxphyaddr(vcpu);
9349         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9350             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9351                 pr_warn_ratelimited(
9352                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9353                         addr_field, maxphyaddr, count, addr);
9354                 return -EINVAL;
9355         }
9356         return 0;
9357 }
9358
9359 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9360                                                 struct vmcs12 *vmcs12)
9361 {
9362         if (vmcs12->vm_exit_msr_load_count == 0 &&
9363             vmcs12->vm_exit_msr_store_count == 0 &&
9364             vmcs12->vm_entry_msr_load_count == 0)
9365                 return 0; /* Fast path */
9366         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9367                                         VM_EXIT_MSR_LOAD_ADDR) ||
9368             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9369                                         VM_EXIT_MSR_STORE_ADDR) ||
9370             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9371                                         VM_ENTRY_MSR_LOAD_ADDR))
9372                 return -EINVAL;
9373         return 0;
9374 }
9375
9376 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9377                                        struct vmx_msr_entry *e)
9378 {
9379         /* x2APIC MSR accesses are not allowed */
9380         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9381                 return -EINVAL;
9382         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9383             e->index == MSR_IA32_UCODE_REV)
9384                 return -EINVAL;
9385         if (e->reserved != 0)
9386                 return -EINVAL;
9387         return 0;
9388 }
9389
9390 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9391                                      struct vmx_msr_entry *e)
9392 {
9393         if (e->index == MSR_FS_BASE ||
9394             e->index == MSR_GS_BASE ||
9395             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9396             nested_vmx_msr_check_common(vcpu, e))
9397                 return -EINVAL;
9398         return 0;
9399 }
9400
9401 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9402                                       struct vmx_msr_entry *e)
9403 {
9404         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9405             nested_vmx_msr_check_common(vcpu, e))
9406                 return -EINVAL;
9407         return 0;
9408 }
9409
9410 /*
9411  * Load guest's/host's msr at nested entry/exit.
9412  * return 0 for success, entry index for failure.
9413  */
9414 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9415 {
9416         u32 i;
9417         struct vmx_msr_entry e;
9418         struct msr_data msr;
9419
9420         msr.host_initiated = false;
9421         for (i = 0; i < count; i++) {
9422                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9423                                         &e, sizeof(e))) {
9424                         pr_warn_ratelimited(
9425                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9426                                 __func__, i, gpa + i * sizeof(e));
9427                         goto fail;
9428                 }
9429                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9430                         pr_warn_ratelimited(
9431                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9432                                 __func__, i, e.index, e.reserved);
9433                         goto fail;
9434                 }
9435                 msr.index = e.index;
9436                 msr.data = e.value;
9437                 if (kvm_set_msr(vcpu, &msr)) {
9438                         pr_warn_ratelimited(
9439                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9440                                 __func__, i, e.index, e.value);
9441                         goto fail;
9442                 }
9443         }
9444         return 0;
9445 fail:
9446         return i + 1;
9447 }
9448
9449 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9450 {
9451         u32 i;
9452         struct vmx_msr_entry e;
9453
9454         for (i = 0; i < count; i++) {
9455                 struct msr_data msr_info;
9456                 if (kvm_vcpu_read_guest(vcpu,
9457                                         gpa + i * sizeof(e),
9458                                         &e, 2 * sizeof(u32))) {
9459                         pr_warn_ratelimited(
9460                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9461                                 __func__, i, gpa + i * sizeof(e));
9462                         return -EINVAL;
9463                 }
9464                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9465                         pr_warn_ratelimited(
9466                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9467                                 __func__, i, e.index, e.reserved);
9468                         return -EINVAL;
9469                 }
9470                 msr_info.host_initiated = false;
9471                 msr_info.index = e.index;
9472                 if (kvm_get_msr(vcpu, &msr_info)) {
9473                         pr_warn_ratelimited(
9474                                 "%s cannot read MSR (%u, 0x%x)\n",
9475                                 __func__, i, e.index);
9476                         return -EINVAL;
9477                 }
9478                 if (kvm_vcpu_write_guest(vcpu,
9479                                          gpa + i * sizeof(e) +
9480                                              offsetof(struct vmx_msr_entry, value),
9481                                          &msr_info.data, sizeof(msr_info.data))) {
9482                         pr_warn_ratelimited(
9483                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9484                                 __func__, i, e.index, msr_info.data);
9485                         return -EINVAL;
9486                 }
9487         }
9488         return 0;
9489 }
9490
9491 /*
9492  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9493  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9494  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9495  * guest in a way that will both be appropriate to L1's requests, and our
9496  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9497  * function also has additional necessary side-effects, like setting various
9498  * vcpu->arch fields.
9499  */
9500 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9501 {
9502         struct vcpu_vmx *vmx = to_vmx(vcpu);
9503         u32 exec_control;
9504
9505         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9506         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9507         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9508         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9509         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9510         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9511         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9512         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9513         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9514         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9515         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9516         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9517         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9518         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9519         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9520         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9521         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9522         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9523         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9524         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9525         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9526         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9527         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9528         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9529         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9530         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9531         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9532         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9533         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9534         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9535         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9536         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9537         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9538         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9539         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9540         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9541
9542         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9543                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9544                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9545         } else {
9546                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9547                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9548         }
9549         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9550                 vmcs12->vm_entry_intr_info_field);
9551         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9552                 vmcs12->vm_entry_exception_error_code);
9553         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9554                 vmcs12->vm_entry_instruction_len);
9555         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9556                 vmcs12->guest_interruptibility_info);
9557         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9558         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9559         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9560                 vmcs12->guest_pending_dbg_exceptions);
9561         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9562         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9563
9564         if (nested_cpu_has_xsaves(vmcs12))
9565                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9566         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9567
9568         exec_control = vmcs12->pin_based_vm_exec_control;
9569         exec_control |= vmcs_config.pin_based_exec_ctrl;
9570         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9571
9572         if (nested_cpu_has_posted_intr(vmcs12)) {
9573                 /*
9574                  * Note that we use L0's vector here and in
9575                  * vmx_deliver_nested_posted_interrupt.
9576                  */
9577                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9578                 vmx->nested.pi_pending = false;
9579                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9580                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9581                         page_to_phys(vmx->nested.pi_desc_page) +
9582                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9583                         (PAGE_SIZE - 1)));
9584         } else
9585                 exec_control &= ~PIN_BASED_POSTED_INTR;
9586
9587         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9588
9589         vmx->nested.preemption_timer_expired = false;
9590         if (nested_cpu_has_preemption_timer(vmcs12))
9591                 vmx_start_preemption_timer(vcpu);
9592
9593         /*
9594          * Whether page-faults are trapped is determined by a combination of
9595          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9596          * If enable_ept, L0 doesn't care about page faults and we should
9597          * set all of these to L1's desires. However, if !enable_ept, L0 does
9598          * care about (at least some) page faults, and because it is not easy
9599          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9600          * to exit on each and every L2 page fault. This is done by setting
9601          * MASK=MATCH=0 and (see below) EB.PF=1.
9602          * Note that below we don't need special code to set EB.PF beyond the
9603          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9604          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9605          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9606          *
9607          * A problem with this approach (when !enable_ept) is that L1 may be
9608          * injected with more page faults than it asked for. This could have
9609          * caused problems, but in practice existing hypervisors don't care.
9610          * To fix this, we will need to emulate the PFEC checking (on the L1
9611          * page tables), using walk_addr(), when injecting PFs to L1.
9612          */
9613         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9614                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9615         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9616                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9617
9618         if (cpu_has_secondary_exec_ctrls()) {
9619                 exec_control = vmx_secondary_exec_control(vmx);
9620
9621                 /* Take the following fields only from vmcs12 */
9622                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9623                                   SECONDARY_EXEC_RDTSCP |
9624                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9625                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9626                                   SECONDARY_EXEC_PCOMMIT);
9627                 if (nested_cpu_has(vmcs12,
9628                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9629                         exec_control |= vmcs12->secondary_vm_exec_control;
9630
9631                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9632                         /*
9633                          * If translation failed, no matter: This feature asks
9634                          * to exit when accessing the given address, and if it
9635                          * can never be accessed, this feature won't do
9636                          * anything anyway.
9637                          */
9638                         if (!vmx->nested.apic_access_page)
9639                                 exec_control &=
9640                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9641                         else
9642                                 vmcs_write64(APIC_ACCESS_ADDR,
9643                                   page_to_phys(vmx->nested.apic_access_page));
9644                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9645                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9646                         exec_control |=
9647                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9648                         kvm_vcpu_reload_apic_access_page(vcpu);
9649                 }
9650
9651                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9652                         vmcs_write64(EOI_EXIT_BITMAP0,
9653                                 vmcs12->eoi_exit_bitmap0);
9654                         vmcs_write64(EOI_EXIT_BITMAP1,
9655                                 vmcs12->eoi_exit_bitmap1);
9656                         vmcs_write64(EOI_EXIT_BITMAP2,
9657                                 vmcs12->eoi_exit_bitmap2);
9658                         vmcs_write64(EOI_EXIT_BITMAP3,
9659                                 vmcs12->eoi_exit_bitmap3);
9660                         vmcs_write16(GUEST_INTR_STATUS,
9661                                 vmcs12->guest_intr_status);
9662                 }
9663
9664                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9665         }
9666
9667
9668         /*
9669          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9670          * Some constant fields are set here by vmx_set_constant_host_state().
9671          * Other fields are different per CPU, and will be set later when
9672          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9673          */
9674         vmx_set_constant_host_state(vmx);
9675
9676         /*
9677          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9678          * entry, but only if the current (host) sp changed from the value
9679          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9680          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9681          * here we just force the write to happen on entry.
9682          */
9683         vmx->host_rsp = 0;
9684
9685         exec_control = vmx_exec_control(vmx); /* L0's desires */
9686         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9687         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9688         exec_control &= ~CPU_BASED_TPR_SHADOW;
9689         exec_control |= vmcs12->cpu_based_vm_exec_control;
9690
9691         if (exec_control & CPU_BASED_TPR_SHADOW) {
9692                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9693                                 page_to_phys(vmx->nested.virtual_apic_page));
9694                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9695         }
9696
9697         if (cpu_has_vmx_msr_bitmap() &&
9698             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9699                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9700                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9701         } else
9702                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9703
9704         /*
9705          * Merging of IO bitmap not currently supported.
9706          * Rather, exit every time.
9707          */
9708         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9709         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9710
9711         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9712
9713         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9714          * bitwise-or of what L1 wants to trap for L2, and what we want to
9715          * trap. Note that CR0.TS also needs updating - we do this later.
9716          */
9717         update_exception_bitmap(vcpu);
9718         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9719         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9720
9721         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9722          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9723          * bits are further modified by vmx_set_efer() below.
9724          */
9725         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9726
9727         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9728          * emulated by vmx_set_efer(), below.
9729          */
9730         vm_entry_controls_init(vmx,
9731                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9732                         ~VM_ENTRY_IA32E_MODE) |
9733                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9734
9735         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9736                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9737                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9738         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9739                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9740
9741
9742         set_cr4_guest_host_mask(vmx);
9743
9744         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9745                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9746
9747         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9748                 vmcs_write64(TSC_OFFSET,
9749                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9750         else
9751                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9752
9753         if (enable_vpid) {
9754                 /*
9755                  * There is no direct mapping between vpid02 and vpid12, the
9756                  * vpid02 is per-vCPU for L0 and reused while the value of
9757                  * vpid12 is changed w/ one invvpid during nested vmentry.
9758                  * The vpid12 is allocated by L1 for L2, so it will not
9759                  * influence global bitmap(for vpid01 and vpid02 allocation)
9760                  * even if spawn a lot of nested vCPUs.
9761                  */
9762                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9763                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9764                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9765                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9766                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9767                         }
9768                 } else {
9769                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9770                         vmx_flush_tlb(vcpu);
9771                 }
9772
9773         }
9774
9775         if (nested_cpu_has_ept(vmcs12)) {
9776                 kvm_mmu_unload(vcpu);
9777                 nested_ept_init_mmu_context(vcpu);
9778         }
9779
9780         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9781                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9782         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9783                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9784         else
9785                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9786         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9787         vmx_set_efer(vcpu, vcpu->arch.efer);
9788
9789         /*
9790          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9791          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9792          * The CR0_READ_SHADOW is what L2 should have expected to read given
9793          * the specifications by L1; It's not enough to take
9794          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9795          * have more bits than L1 expected.
9796          */
9797         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9798         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9799
9800         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9801         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9802
9803         /* shadow page tables on either EPT or shadow page tables */
9804         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9805         kvm_mmu_reset_context(vcpu);
9806
9807         if (!enable_ept)
9808                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9809
9810         /*
9811          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9812          */
9813         if (enable_ept) {
9814                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9815                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9816                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9817                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9818         }
9819
9820         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9821         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9822 }
9823
9824 /*
9825  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9826  * for running an L2 nested guest.
9827  */
9828 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9829 {
9830         struct vmcs12 *vmcs12;
9831         struct vcpu_vmx *vmx = to_vmx(vcpu);
9832         int cpu;
9833         struct loaded_vmcs *vmcs02;
9834         bool ia32e;
9835         u32 msr_entry_idx;
9836
9837         if (!nested_vmx_check_permission(vcpu) ||
9838             !nested_vmx_check_vmcs12(vcpu))
9839                 return 1;
9840
9841         skip_emulated_instruction(vcpu);
9842         vmcs12 = get_vmcs12(vcpu);
9843
9844         if (enable_shadow_vmcs)
9845                 copy_shadow_to_vmcs12(vmx);
9846
9847         /*
9848          * The nested entry process starts with enforcing various prerequisites
9849          * on vmcs12 as required by the Intel SDM, and act appropriately when
9850          * they fail: As the SDM explains, some conditions should cause the
9851          * instruction to fail, while others will cause the instruction to seem
9852          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9853          * To speed up the normal (success) code path, we should avoid checking
9854          * for misconfigurations which will anyway be caught by the processor
9855          * when using the merged vmcs02.
9856          */
9857         if (vmcs12->launch_state == launch) {
9858                 nested_vmx_failValid(vcpu,
9859                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9860                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9861                 return 1;
9862         }
9863
9864         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9865             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9866                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9867                 return 1;
9868         }
9869
9870         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9871                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9872                 return 1;
9873         }
9874
9875         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9876                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9877                 return 1;
9878         }
9879
9880         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9881                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9882                 return 1;
9883         }
9884
9885         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9886                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9887                 return 1;
9888         }
9889
9890         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9891                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9892                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9893             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9894                                 vmx->nested.nested_vmx_secondary_ctls_low,
9895                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9896             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9897                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9898                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9899             !vmx_control_verify(vmcs12->vm_exit_controls,
9900                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9901                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9902             !vmx_control_verify(vmcs12->vm_entry_controls,
9903                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9904                                 vmx->nested.nested_vmx_entry_ctls_high))
9905         {
9906                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9907                 return 1;
9908         }
9909
9910         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9911             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9912                 nested_vmx_failValid(vcpu,
9913                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9914                 return 1;
9915         }
9916
9917         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9918             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9919                 nested_vmx_entry_failure(vcpu, vmcs12,
9920                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9921                 return 1;
9922         }
9923         if (vmcs12->vmcs_link_pointer != -1ull) {
9924                 nested_vmx_entry_failure(vcpu, vmcs12,
9925                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9926                 return 1;
9927         }
9928
9929         /*
9930          * If the load IA32_EFER VM-entry control is 1, the following checks
9931          * are performed on the field for the IA32_EFER MSR:
9932          * - Bits reserved in the IA32_EFER MSR must be 0.
9933          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9934          *   the IA-32e mode guest VM-exit control. It must also be identical
9935          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9936          *   CR0.PG) is 1.
9937          */
9938         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9939                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9940                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9941                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9942                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9943                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9944                         nested_vmx_entry_failure(vcpu, vmcs12,
9945                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9946                         return 1;
9947                 }
9948         }
9949
9950         /*
9951          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9952          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9953          * the values of the LMA and LME bits in the field must each be that of
9954          * the host address-space size VM-exit control.
9955          */
9956         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9957                 ia32e = (vmcs12->vm_exit_controls &
9958                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9959                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9960                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9961                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9962                         nested_vmx_entry_failure(vcpu, vmcs12,
9963                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9964                         return 1;
9965                 }
9966         }
9967
9968         /*
9969          * We're finally done with prerequisite checking, and can start with
9970          * the nested entry.
9971          */
9972
9973         vmcs02 = nested_get_current_vmcs02(vmx);
9974         if (!vmcs02)
9975                 return -ENOMEM;
9976
9977         enter_guest_mode(vcpu);
9978
9979         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9980
9981         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9982                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9983
9984         cpu = get_cpu();
9985         vmx->loaded_vmcs = vmcs02;
9986         vmx_vcpu_put(vcpu);
9987         vmx_vcpu_load(vcpu, cpu);
9988         vcpu->cpu = cpu;
9989         put_cpu();
9990
9991         vmx_segment_cache_clear(vmx);
9992
9993         prepare_vmcs02(vcpu, vmcs12);
9994
9995         msr_entry_idx = nested_vmx_load_msr(vcpu,
9996                                             vmcs12->vm_entry_msr_load_addr,
9997                                             vmcs12->vm_entry_msr_load_count);
9998         if (msr_entry_idx) {
9999                 leave_guest_mode(vcpu);
10000                 vmx_load_vmcs01(vcpu);
10001                 nested_vmx_entry_failure(vcpu, vmcs12,
10002                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10003                 return 1;
10004         }
10005
10006         vmcs12->launch_state = 1;
10007
10008         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10009                 return kvm_vcpu_halt(vcpu);
10010
10011         vmx->nested.nested_run_pending = 1;
10012
10013         /*
10014          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10015          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10016          * returned as far as L1 is concerned. It will only return (and set
10017          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10018          */
10019         return 1;
10020 }
10021
10022 /*
10023  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10024  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10025  * This function returns the new value we should put in vmcs12.guest_cr0.
10026  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10027  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10028  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10029  *     didn't trap the bit, because if L1 did, so would L0).
10030  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10031  *     been modified by L2, and L1 knows it. So just leave the old value of
10032  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10033  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10034  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10035  *     changed these bits, and therefore they need to be updated, but L0
10036  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10037  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10038  */
10039 static inline unsigned long
10040 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10041 {
10042         return
10043         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10044         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10045         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10046                         vcpu->arch.cr0_guest_owned_bits));
10047 }
10048
10049 static inline unsigned long
10050 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10051 {
10052         return
10053         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10054         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10055         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10056                         vcpu->arch.cr4_guest_owned_bits));
10057 }
10058
10059 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10060                                        struct vmcs12 *vmcs12)
10061 {
10062         u32 idt_vectoring;
10063         unsigned int nr;
10064
10065         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10066                 nr = vcpu->arch.exception.nr;
10067                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10068
10069                 if (kvm_exception_is_soft(nr)) {
10070                         vmcs12->vm_exit_instruction_len =
10071                                 vcpu->arch.event_exit_inst_len;
10072                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10073                 } else
10074                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10075
10076                 if (vcpu->arch.exception.has_error_code) {
10077                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10078                         vmcs12->idt_vectoring_error_code =
10079                                 vcpu->arch.exception.error_code;
10080                 }
10081
10082                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10083         } else if (vcpu->arch.nmi_injected) {
10084                 vmcs12->idt_vectoring_info_field =
10085                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10086         } else if (vcpu->arch.interrupt.pending) {
10087                 nr = vcpu->arch.interrupt.nr;
10088                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10089
10090                 if (vcpu->arch.interrupt.soft) {
10091                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10092                         vmcs12->vm_entry_instruction_len =
10093                                 vcpu->arch.event_exit_inst_len;
10094                 } else
10095                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10096
10097                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10098         }
10099 }
10100
10101 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10102 {
10103         struct vcpu_vmx *vmx = to_vmx(vcpu);
10104
10105         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10106             vmx->nested.preemption_timer_expired) {
10107                 if (vmx->nested.nested_run_pending)
10108                         return -EBUSY;
10109                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10110                 return 0;
10111         }
10112
10113         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10114                 if (vmx->nested.nested_run_pending ||
10115                     vcpu->arch.interrupt.pending)
10116                         return -EBUSY;
10117                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10118                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10119                                   INTR_INFO_VALID_MASK, 0);
10120                 /*
10121                  * The NMI-triggered VM exit counts as injection:
10122                  * clear this one and block further NMIs.
10123                  */
10124                 vcpu->arch.nmi_pending = 0;
10125                 vmx_set_nmi_mask(vcpu, true);
10126                 return 0;
10127         }
10128
10129         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10130             nested_exit_on_intr(vcpu)) {
10131                 if (vmx->nested.nested_run_pending)
10132                         return -EBUSY;
10133                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10134                 return 0;
10135         }
10136
10137         return vmx_complete_nested_posted_interrupt(vcpu);
10138 }
10139
10140 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10141 {
10142         ktime_t remaining =
10143                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10144         u64 value;
10145
10146         if (ktime_to_ns(remaining) <= 0)
10147                 return 0;
10148
10149         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10150         do_div(value, 1000000);
10151         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10152 }
10153
10154 /*
10155  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10156  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10157  * and this function updates it to reflect the changes to the guest state while
10158  * L2 was running (and perhaps made some exits which were handled directly by L0
10159  * without going back to L1), and to reflect the exit reason.
10160  * Note that we do not have to copy here all VMCS fields, just those that
10161  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10162  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10163  * which already writes to vmcs12 directly.
10164  */
10165 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10166                            u32 exit_reason, u32 exit_intr_info,
10167                            unsigned long exit_qualification)
10168 {
10169         /* update guest state fields: */
10170         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10171         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10172
10173         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10174         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10175         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10176
10177         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10178         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10179         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10180         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10181         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10182         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10183         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10184         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10185         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10186         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10187         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10188         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10189         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10190         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10191         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10192         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10193         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10194         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10195         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10196         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10197         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10198         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10199         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10200         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10201         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10202         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10203         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10204         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10205         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10206         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10207         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10208         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10209         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10210         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10211         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10212         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10213
10214         vmcs12->guest_interruptibility_info =
10215                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10216         vmcs12->guest_pending_dbg_exceptions =
10217                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10218         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10219                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10220         else
10221                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10222
10223         if (nested_cpu_has_preemption_timer(vmcs12)) {
10224                 if (vmcs12->vm_exit_controls &
10225                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10226                         vmcs12->vmx_preemption_timer_value =
10227                                 vmx_get_preemption_timer_value(vcpu);
10228                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10229         }
10230
10231         /*
10232          * In some cases (usually, nested EPT), L2 is allowed to change its
10233          * own CR3 without exiting. If it has changed it, we must keep it.
10234          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10235          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10236          *
10237          * Additionally, restore L2's PDPTR to vmcs12.
10238          */
10239         if (enable_ept) {
10240                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10241                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10242                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10243                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10244                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10245         }
10246
10247         if (nested_cpu_has_vid(vmcs12))
10248                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10249
10250         vmcs12->vm_entry_controls =
10251                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10252                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10253
10254         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10255                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10256                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10257         }
10258
10259         /* TODO: These cannot have changed unless we have MSR bitmaps and
10260          * the relevant bit asks not to trap the change */
10261         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10262                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10263         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10264                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10265         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10266         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10267         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10268         if (vmx_mpx_supported())
10269                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10270         if (nested_cpu_has_xsaves(vmcs12))
10271                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10272
10273         /* update exit information fields: */
10274
10275         vmcs12->vm_exit_reason = exit_reason;
10276         vmcs12->exit_qualification = exit_qualification;
10277
10278         vmcs12->vm_exit_intr_info = exit_intr_info;
10279         if ((vmcs12->vm_exit_intr_info &
10280              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10281             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10282                 vmcs12->vm_exit_intr_error_code =
10283                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10284         vmcs12->idt_vectoring_info_field = 0;
10285         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10286         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10287
10288         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10289                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10290                  * instead of reading the real value. */
10291                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10292
10293                 /*
10294                  * Transfer the event that L0 or L1 may wanted to inject into
10295                  * L2 to IDT_VECTORING_INFO_FIELD.
10296                  */
10297                 vmcs12_save_pending_event(vcpu, vmcs12);
10298         }
10299
10300         /*
10301          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10302          * preserved above and would only end up incorrectly in L1.
10303          */
10304         vcpu->arch.nmi_injected = false;
10305         kvm_clear_exception_queue(vcpu);
10306         kvm_clear_interrupt_queue(vcpu);
10307 }
10308
10309 /*
10310  * A part of what we need to when the nested L2 guest exits and we want to
10311  * run its L1 parent, is to reset L1's guest state to the host state specified
10312  * in vmcs12.
10313  * This function is to be called not only on normal nested exit, but also on
10314  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10315  * Failures During or After Loading Guest State").
10316  * This function should be called when the active VMCS is L1's (vmcs01).
10317  */
10318 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10319                                    struct vmcs12 *vmcs12)
10320 {
10321         struct kvm_segment seg;
10322
10323         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10324                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10325         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10326                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10327         else
10328                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10329         vmx_set_efer(vcpu, vcpu->arch.efer);
10330
10331         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10332         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10333         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10334         /*
10335          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10336          * actually changed, because it depends on the current state of
10337          * fpu_active (which may have changed).
10338          * Note that vmx_set_cr0 refers to efer set above.
10339          */
10340         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10341         /*
10342          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10343          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10344          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10345          */
10346         update_exception_bitmap(vcpu);
10347         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10348         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10349
10350         /*
10351          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10352          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10353          */
10354         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10355         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10356
10357         nested_ept_uninit_mmu_context(vcpu);
10358
10359         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10360         kvm_mmu_reset_context(vcpu);
10361
10362         if (!enable_ept)
10363                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10364
10365         if (enable_vpid) {
10366                 /*
10367                  * Trivially support vpid by letting L2s share their parent
10368                  * L1's vpid. TODO: move to a more elaborate solution, giving
10369                  * each L2 its own vpid and exposing the vpid feature to L1.
10370                  */
10371                 vmx_flush_tlb(vcpu);
10372         }
10373
10374
10375         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10376         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10377         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10378         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10379         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10380
10381         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10382         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10383                 vmcs_write64(GUEST_BNDCFGS, 0);
10384
10385         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10386                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10387                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10388         }
10389         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10390                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10391                         vmcs12->host_ia32_perf_global_ctrl);
10392
10393         /* Set L1 segment info according to Intel SDM
10394             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10395         seg = (struct kvm_segment) {
10396                 .base = 0,
10397                 .limit = 0xFFFFFFFF,
10398                 .selector = vmcs12->host_cs_selector,
10399                 .type = 11,
10400                 .present = 1,
10401                 .s = 1,
10402                 .g = 1
10403         };
10404         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10405                 seg.l = 1;
10406         else
10407                 seg.db = 1;
10408         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10409         seg = (struct kvm_segment) {
10410                 .base = 0,
10411                 .limit = 0xFFFFFFFF,
10412                 .type = 3,
10413                 .present = 1,
10414                 .s = 1,
10415                 .db = 1,
10416                 .g = 1
10417         };
10418         seg.selector = vmcs12->host_ds_selector;
10419         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10420         seg.selector = vmcs12->host_es_selector;
10421         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10422         seg.selector = vmcs12->host_ss_selector;
10423         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10424         seg.selector = vmcs12->host_fs_selector;
10425         seg.base = vmcs12->host_fs_base;
10426         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10427         seg.selector = vmcs12->host_gs_selector;
10428         seg.base = vmcs12->host_gs_base;
10429         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10430         seg = (struct kvm_segment) {
10431                 .base = vmcs12->host_tr_base,
10432                 .limit = 0x67,
10433                 .selector = vmcs12->host_tr_selector,
10434                 .type = 11,
10435                 .present = 1
10436         };
10437         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10438
10439         kvm_set_dr(vcpu, 7, 0x400);
10440         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10441
10442         if (cpu_has_vmx_msr_bitmap())
10443                 vmx_set_msr_bitmap(vcpu);
10444
10445         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10446                                 vmcs12->vm_exit_msr_load_count))
10447                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10448 }
10449
10450 /*
10451  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10452  * and modify vmcs12 to make it see what it would expect to see there if
10453  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10454  */
10455 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10456                               u32 exit_intr_info,
10457                               unsigned long exit_qualification)
10458 {
10459         struct vcpu_vmx *vmx = to_vmx(vcpu);
10460         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10461
10462         /* trying to cancel vmlaunch/vmresume is a bug */
10463         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10464
10465         leave_guest_mode(vcpu);
10466         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10467                        exit_qualification);
10468
10469         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10470                                  vmcs12->vm_exit_msr_store_count))
10471                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10472
10473         vmx_load_vmcs01(vcpu);
10474
10475         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10476             && nested_exit_intr_ack_set(vcpu)) {
10477                 int irq = kvm_cpu_get_interrupt(vcpu);
10478                 WARN_ON(irq < 0);
10479                 vmcs12->vm_exit_intr_info = irq |
10480                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10481         }
10482
10483         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10484                                        vmcs12->exit_qualification,
10485                                        vmcs12->idt_vectoring_info_field,
10486                                        vmcs12->vm_exit_intr_info,
10487                                        vmcs12->vm_exit_intr_error_code,
10488                                        KVM_ISA_VMX);
10489
10490         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10491         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10492         vmx_segment_cache_clear(vmx);
10493
10494         /* if no vmcs02 cache requested, remove the one we used */
10495         if (VMCS02_POOL_SIZE == 0)
10496                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10497
10498         load_vmcs12_host_state(vcpu, vmcs12);
10499
10500         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10501         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10502
10503         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10504         vmx->host_rsp = 0;
10505
10506         /* Unpin physical memory we referred to in vmcs02 */
10507         if (vmx->nested.apic_access_page) {
10508                 nested_release_page(vmx->nested.apic_access_page);
10509                 vmx->nested.apic_access_page = NULL;
10510         }
10511         if (vmx->nested.virtual_apic_page) {
10512                 nested_release_page(vmx->nested.virtual_apic_page);
10513                 vmx->nested.virtual_apic_page = NULL;
10514         }
10515         if (vmx->nested.pi_desc_page) {
10516                 kunmap(vmx->nested.pi_desc_page);
10517                 nested_release_page(vmx->nested.pi_desc_page);
10518                 vmx->nested.pi_desc_page = NULL;
10519                 vmx->nested.pi_desc = NULL;
10520         }
10521
10522         /*
10523          * We are now running in L2, mmu_notifier will force to reload the
10524          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10525          */
10526         kvm_vcpu_reload_apic_access_page(vcpu);
10527
10528         /*
10529          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10530          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10531          * success or failure flag accordingly.
10532          */
10533         if (unlikely(vmx->fail)) {
10534                 vmx->fail = 0;
10535                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10536         } else
10537                 nested_vmx_succeed(vcpu);
10538         if (enable_shadow_vmcs)
10539                 vmx->nested.sync_shadow_vmcs = true;
10540
10541         /* in case we halted in L2 */
10542         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10543 }
10544
10545 /*
10546  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10547  */
10548 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10549 {
10550         if (is_guest_mode(vcpu))
10551                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10552         free_nested(to_vmx(vcpu));
10553 }
10554
10555 /*
10556  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10557  * 23.7 "VM-entry failures during or after loading guest state" (this also
10558  * lists the acceptable exit-reason and exit-qualification parameters).
10559  * It should only be called before L2 actually succeeded to run, and when
10560  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10561  */
10562 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10563                         struct vmcs12 *vmcs12,
10564                         u32 reason, unsigned long qualification)
10565 {
10566         load_vmcs12_host_state(vcpu, vmcs12);
10567         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10568         vmcs12->exit_qualification = qualification;
10569         nested_vmx_succeed(vcpu);
10570         if (enable_shadow_vmcs)
10571                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10572 }
10573
10574 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10575                                struct x86_instruction_info *info,
10576                                enum x86_intercept_stage stage)
10577 {
10578         return X86EMUL_CONTINUE;
10579 }
10580
10581 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10582 {
10583         if (ple_gap)
10584                 shrink_ple_window(vcpu);
10585 }
10586
10587 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10588                                      struct kvm_memory_slot *slot)
10589 {
10590         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10591         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10592 }
10593
10594 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10595                                        struct kvm_memory_slot *slot)
10596 {
10597         kvm_mmu_slot_set_dirty(kvm, slot);
10598 }
10599
10600 static void vmx_flush_log_dirty(struct kvm *kvm)
10601 {
10602         kvm_flush_pml_buffers(kvm);
10603 }
10604
10605 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10606                                            struct kvm_memory_slot *memslot,
10607                                            gfn_t offset, unsigned long mask)
10608 {
10609         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10610 }
10611
10612 /*
10613  * This routine does the following things for vCPU which is going
10614  * to be blocked if VT-d PI is enabled.
10615  * - Store the vCPU to the wakeup list, so when interrupts happen
10616  *   we can find the right vCPU to wake up.
10617  * - Change the Posted-interrupt descriptor as below:
10618  *      'NDST' <-- vcpu->pre_pcpu
10619  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10620  * - If 'ON' is set during this process, which means at least one
10621  *   interrupt is posted for this vCPU, we cannot block it, in
10622  *   this case, return 1, otherwise, return 0.
10623  *
10624  */
10625 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10626 {
10627         unsigned long flags;
10628         unsigned int dest;
10629         struct pi_desc old, new;
10630         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10631
10632         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10633                 !irq_remapping_cap(IRQ_POSTING_CAP))
10634                 return 0;
10635
10636         vcpu->pre_pcpu = vcpu->cpu;
10637         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10638                           vcpu->pre_pcpu), flags);
10639         list_add_tail(&vcpu->blocked_vcpu_list,
10640                       &per_cpu(blocked_vcpu_on_cpu,
10641                       vcpu->pre_pcpu));
10642         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10643                                vcpu->pre_pcpu), flags);
10644
10645         do {
10646                 old.control = new.control = pi_desc->control;
10647
10648                 /*
10649                  * We should not block the vCPU if
10650                  * an interrupt is posted for it.
10651                  */
10652                 if (pi_test_on(pi_desc) == 1) {
10653                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10654                                           vcpu->pre_pcpu), flags);
10655                         list_del(&vcpu->blocked_vcpu_list);
10656                         spin_unlock_irqrestore(
10657                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10658                                         vcpu->pre_pcpu), flags);
10659                         vcpu->pre_pcpu = -1;
10660
10661                         return 1;
10662                 }
10663
10664                 WARN((pi_desc->sn == 1),
10665                      "Warning: SN field of posted-interrupts "
10666                      "is set before blocking\n");
10667
10668                 /*
10669                  * Since vCPU can be preempted during this process,
10670                  * vcpu->cpu could be different with pre_pcpu, we
10671                  * need to set pre_pcpu as the destination of wakeup
10672                  * notification event, then we can find the right vCPU
10673                  * to wakeup in wakeup handler if interrupts happen
10674                  * when the vCPU is in blocked state.
10675                  */
10676                 dest = cpu_physical_id(vcpu->pre_pcpu);
10677
10678                 if (x2apic_enabled())
10679                         new.ndst = dest;
10680                 else
10681                         new.ndst = (dest << 8) & 0xFF00;
10682
10683                 /* set 'NV' to 'wakeup vector' */
10684                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10685         } while (cmpxchg(&pi_desc->control, old.control,
10686                         new.control) != old.control);
10687
10688         return 0;
10689 }
10690
10691 static void vmx_post_block(struct kvm_vcpu *vcpu)
10692 {
10693         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10694         struct pi_desc old, new;
10695         unsigned int dest;
10696         unsigned long flags;
10697
10698         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10699                 !irq_remapping_cap(IRQ_POSTING_CAP))
10700                 return;
10701
10702         do {
10703                 old.control = new.control = pi_desc->control;
10704
10705                 dest = cpu_physical_id(vcpu->cpu);
10706
10707                 if (x2apic_enabled())
10708                         new.ndst = dest;
10709                 else
10710                         new.ndst = (dest << 8) & 0xFF00;
10711
10712                 /* Allow posting non-urgent interrupts */
10713                 new.sn = 0;
10714
10715                 /* set 'NV' to 'notification vector' */
10716                 new.nv = POSTED_INTR_VECTOR;
10717         } while (cmpxchg(&pi_desc->control, old.control,
10718                         new.control) != old.control);
10719
10720         if(vcpu->pre_pcpu != -1) {
10721                 spin_lock_irqsave(
10722                         &per_cpu(blocked_vcpu_on_cpu_lock,
10723                         vcpu->pre_pcpu), flags);
10724                 list_del(&vcpu->blocked_vcpu_list);
10725                 spin_unlock_irqrestore(
10726                         &per_cpu(blocked_vcpu_on_cpu_lock,
10727                         vcpu->pre_pcpu), flags);
10728                 vcpu->pre_pcpu = -1;
10729         }
10730 }
10731
10732 /*
10733  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10734  *
10735  * @kvm: kvm
10736  * @host_irq: host irq of the interrupt
10737  * @guest_irq: gsi of the interrupt
10738  * @set: set or unset PI
10739  * returns 0 on success, < 0 on failure
10740  */
10741 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10742                               uint32_t guest_irq, bool set)
10743 {
10744         struct kvm_kernel_irq_routing_entry *e;
10745         struct kvm_irq_routing_table *irq_rt;
10746         struct kvm_lapic_irq irq;
10747         struct kvm_vcpu *vcpu;
10748         struct vcpu_data vcpu_info;
10749         int idx, ret = -EINVAL;
10750
10751         if (!kvm_arch_has_assigned_device(kvm) ||
10752                 !irq_remapping_cap(IRQ_POSTING_CAP))
10753                 return 0;
10754
10755         idx = srcu_read_lock(&kvm->irq_srcu);
10756         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10757         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10758
10759         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10760                 if (e->type != KVM_IRQ_ROUTING_MSI)
10761                         continue;
10762                 /*
10763                  * VT-d PI cannot support posting multicast/broadcast
10764                  * interrupts to a vCPU, we still use interrupt remapping
10765                  * for these kind of interrupts.
10766                  *
10767                  * For lowest-priority interrupts, we only support
10768                  * those with single CPU as the destination, e.g. user
10769                  * configures the interrupts via /proc/irq or uses
10770                  * irqbalance to make the interrupts single-CPU.
10771                  *
10772                  * We will support full lowest-priority interrupt later.
10773                  */
10774
10775                 kvm_set_msi_irq(e, &irq);
10776                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10777                         /*
10778                          * Make sure the IRTE is in remapped mode if
10779                          * we don't handle it in posted mode.
10780                          */
10781                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10782                         if (ret < 0) {
10783                                 printk(KERN_INFO
10784                                    "failed to back to remapped mode, irq: %u\n",
10785                                    host_irq);
10786                                 goto out;
10787                         }
10788
10789                         continue;
10790                 }
10791
10792                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10793                 vcpu_info.vector = irq.vector;
10794
10795                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10796                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10797
10798                 if (set)
10799                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10800                 else {
10801                         /* suppress notification event before unposting */
10802                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10803                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10804                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10805                 }
10806
10807                 if (ret < 0) {
10808                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10809                                         __func__);
10810                         goto out;
10811                 }
10812         }
10813
10814         ret = 0;
10815 out:
10816         srcu_read_unlock(&kvm->irq_srcu, idx);
10817         return ret;
10818 }
10819
10820 static struct kvm_x86_ops vmx_x86_ops = {
10821         .cpu_has_kvm_support = cpu_has_kvm_support,
10822         .disabled_by_bios = vmx_disabled_by_bios,
10823         .hardware_setup = hardware_setup,
10824         .hardware_unsetup = hardware_unsetup,
10825         .check_processor_compatibility = vmx_check_processor_compat,
10826         .hardware_enable = hardware_enable,
10827         .hardware_disable = hardware_disable,
10828         .cpu_has_accelerated_tpr = report_flexpriority,
10829         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10830
10831         .vcpu_create = vmx_create_vcpu,
10832         .vcpu_free = vmx_free_vcpu,
10833         .vcpu_reset = vmx_vcpu_reset,
10834
10835         .prepare_guest_switch = vmx_save_host_state,
10836         .vcpu_load = vmx_vcpu_load,
10837         .vcpu_put = vmx_vcpu_put,
10838
10839         .update_bp_intercept = update_exception_bitmap,
10840         .get_msr = vmx_get_msr,
10841         .set_msr = vmx_set_msr,
10842         .get_segment_base = vmx_get_segment_base,
10843         .get_segment = vmx_get_segment,
10844         .set_segment = vmx_set_segment,
10845         .get_cpl = vmx_get_cpl,
10846         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10847         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10848         .decache_cr3 = vmx_decache_cr3,
10849         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10850         .set_cr0 = vmx_set_cr0,
10851         .set_cr3 = vmx_set_cr3,
10852         .set_cr4 = vmx_set_cr4,
10853         .set_efer = vmx_set_efer,
10854         .get_idt = vmx_get_idt,
10855         .set_idt = vmx_set_idt,
10856         .get_gdt = vmx_get_gdt,
10857         .set_gdt = vmx_set_gdt,
10858         .get_dr6 = vmx_get_dr6,
10859         .set_dr6 = vmx_set_dr6,
10860         .set_dr7 = vmx_set_dr7,
10861         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10862         .cache_reg = vmx_cache_reg,
10863         .get_rflags = vmx_get_rflags,
10864         .set_rflags = vmx_set_rflags,
10865         .fpu_activate = vmx_fpu_activate,
10866         .fpu_deactivate = vmx_fpu_deactivate,
10867
10868         .tlb_flush = vmx_flush_tlb,
10869
10870         .run = vmx_vcpu_run,
10871         .handle_exit = vmx_handle_exit,
10872         .skip_emulated_instruction = skip_emulated_instruction,
10873         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10874         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10875         .patch_hypercall = vmx_patch_hypercall,
10876         .set_irq = vmx_inject_irq,
10877         .set_nmi = vmx_inject_nmi,
10878         .queue_exception = vmx_queue_exception,
10879         .cancel_injection = vmx_cancel_injection,
10880         .interrupt_allowed = vmx_interrupt_allowed,
10881         .nmi_allowed = vmx_nmi_allowed,
10882         .get_nmi_mask = vmx_get_nmi_mask,
10883         .set_nmi_mask = vmx_set_nmi_mask,
10884         .enable_nmi_window = enable_nmi_window,
10885         .enable_irq_window = enable_irq_window,
10886         .update_cr8_intercept = update_cr8_intercept,
10887         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10888         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10889         .get_enable_apicv = vmx_get_enable_apicv,
10890         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10891         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10892         .hwapic_irr_update = vmx_hwapic_irr_update,
10893         .hwapic_isr_update = vmx_hwapic_isr_update,
10894         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10895         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10896
10897         .set_tss_addr = vmx_set_tss_addr,
10898         .get_tdp_level = get_ept_level,
10899         .get_mt_mask = vmx_get_mt_mask,
10900
10901         .get_exit_info = vmx_get_exit_info,
10902
10903         .get_lpage_level = vmx_get_lpage_level,
10904
10905         .cpuid_update = vmx_cpuid_update,
10906
10907         .rdtscp_supported = vmx_rdtscp_supported,
10908         .invpcid_supported = vmx_invpcid_supported,
10909
10910         .set_supported_cpuid = vmx_set_supported_cpuid,
10911
10912         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10913
10914         .read_tsc_offset = vmx_read_tsc_offset,
10915         .write_tsc_offset = vmx_write_tsc_offset,
10916         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10917         .read_l1_tsc = vmx_read_l1_tsc,
10918
10919         .set_tdp_cr3 = vmx_set_cr3,
10920
10921         .check_intercept = vmx_check_intercept,
10922         .handle_external_intr = vmx_handle_external_intr,
10923         .mpx_supported = vmx_mpx_supported,
10924         .xsaves_supported = vmx_xsaves_supported,
10925
10926         .check_nested_events = vmx_check_nested_events,
10927
10928         .sched_in = vmx_sched_in,
10929
10930         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10931         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10932         .flush_log_dirty = vmx_flush_log_dirty,
10933         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10934
10935         .pre_block = vmx_pre_block,
10936         .post_block = vmx_post_block,
10937
10938         .pmu_ops = &intel_pmu_ops,
10939
10940         .update_pi_irte = vmx_update_pi_irte,
10941 };
10942
10943 static int __init vmx_init(void)
10944 {
10945         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10946                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10947         if (r)
10948                 return r;
10949
10950 #ifdef CONFIG_KEXEC_CORE
10951         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10952                            crash_vmclear_local_loaded_vmcss);
10953 #endif
10954
10955         return 0;
10956 }
10957
10958 static void __exit vmx_exit(void)
10959 {
10960 #ifdef CONFIG_KEXEC_CORE
10961         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10962         synchronize_rcu();
10963 #endif
10964
10965         kvm_exit();
10966 }
10967
10968 module_init(vmx_init)
10969 module_exit(vmx_exit)