arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599 };
 600
 601 enum segment_cache_field {
 602         SEG_FIELD_SEL = 0,
 603         SEG_FIELD_BASE = 1,
 604         SEG_FIELD_LIMIT = 2,
 605         SEG_FIELD_AR = 3,
 606
 607         SEG_FIELD_NR = 4
 608 };
 609
 610 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 611 {
 612         return container_of(vcpu, struct vcpu_vmx, vcpu);
 613 }
 614
 615 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 616 {
 617         return &(to_vmx(vcpu)->pi_desc);
 618 }
 619
 620 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 621 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 622 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 623                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 624
 625
 626 static unsigned long shadow_read_only_fields[] = {
 627         /*
 628          * We do NOT shadow fields that are modified when L0
 629          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 630          * VMXON...) executed by L1.
 631          * For example, VM_INSTRUCTION_ERROR is read
 632          * by L1 if a vmx instruction fails (part of the error path).
 633          * Note the code assumes this logic. If for some reason
 634          * we start shadowing these fields then we need to
 635          * force a shadow sync when L0 emulates vmx instructions
 636          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 637          * by nested_vmx_failValid)
 638          */
 639         VM_EXIT_REASON,
 640         VM_EXIT_INTR_INFO,
 641         VM_EXIT_INSTRUCTION_LEN,
 642         IDT_VECTORING_INFO_FIELD,
 643         IDT_VECTORING_ERROR_CODE,
 644         VM_EXIT_INTR_ERROR_CODE,
 645         EXIT_QUALIFICATION,
 646         GUEST_LINEAR_ADDRESS,
 647         GUEST_PHYSICAL_ADDRESS
 648 };
 649 static int max_shadow_read_only_fields =
 650         ARRAY_SIZE(shadow_read_only_fields);
 651
 652 static unsigned long shadow_read_write_fields[] = {
 653         TPR_THRESHOLD,
 654         GUEST_RIP,
 655         GUEST_RSP,
 656         GUEST_CR0,
 657         GUEST_CR3,
 658         GUEST_CR4,
 659         GUEST_INTERRUPTIBILITY_INFO,
 660         GUEST_RFLAGS,
 661         GUEST_CS_SELECTOR,
 662         GUEST_CS_AR_BYTES,
 663         GUEST_CS_LIMIT,
 664         GUEST_CS_BASE,
 665         GUEST_ES_BASE,
 666         GUEST_BNDCFGS,
 667         CR0_GUEST_HOST_MASK,
 668         CR0_READ_SHADOW,
 669         CR4_READ_SHADOW,
 670         TSC_OFFSET,
 671         EXCEPTION_BITMAP,
 672         CPU_BASED_VM_EXEC_CONTROL,
 673         VM_ENTRY_EXCEPTION_ERROR_CODE,
 674         VM_ENTRY_INTR_INFO_FIELD,
 675         VM_ENTRY_INSTRUCTION_LEN,
 676         VM_ENTRY_EXCEPTION_ERROR_CODE,
 677         HOST_FS_BASE,
 678         HOST_GS_BASE,
 679         HOST_FS_SELECTOR,
 680         HOST_GS_SELECTOR
 681 };
 682 static int max_shadow_read_write_fields =
 683         ARRAY_SIZE(shadow_read_write_fields);
 684
 685 static const unsigned short vmcs_field_to_offset_table[] = {
 686         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 687         FIELD(POSTED_INTR_NV, posted_intr_nv),
 688         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 689         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 690         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 691         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 692         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 693         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 694         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 695         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 696         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 697         FIELD(HOST_ES_SELECTOR, host_es_selector),
 698         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 699         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 700         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 701         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 702         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 703         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 704         FIELD64(IO_BITMAP_A, io_bitmap_a),
 705         FIELD64(IO_BITMAP_B, io_bitmap_b),
 706         FIELD64(MSR_BITMAP, msr_bitmap),
 707         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 708         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 709         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 710         FIELD64(TSC_OFFSET, tsc_offset),
 711         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 712         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 713         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 714         FIELD64(EPT_POINTER, ept_pointer),
 715         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 716         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 717         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 718         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 719         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 720         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 721         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 722         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 723         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 724         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 725         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 726         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 727         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 728         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 729         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 730         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 731         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 732         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 733         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 734         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 735         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 736         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 737         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 738         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 739         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 740         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 741         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 742         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 743         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 744         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 745         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 746         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 747         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 748         FIELD(TPR_THRESHOLD, tpr_threshold),
 749         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 750         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 751         FIELD(VM_EXIT_REASON, vm_exit_reason),
 752         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 753         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 754         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 755         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 756         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 757         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 758         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 759         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 760         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 761         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 762         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 763         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 764         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 765         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 766         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 767         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 768         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 769         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 770         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 771         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 772         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 773         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 774         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 775         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 776         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 777         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 778         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 779         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 780         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 781         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 782         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 783         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 784         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 785         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 786         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 787         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 788         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 789         FIELD(EXIT_QUALIFICATION, exit_qualification),
 790         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 791         FIELD(GUEST_CR0, guest_cr0),
 792         FIELD(GUEST_CR3, guest_cr3),
 793         FIELD(GUEST_CR4, guest_cr4),
 794         FIELD(GUEST_ES_BASE, guest_es_base),
 795         FIELD(GUEST_CS_BASE, guest_cs_base),
 796         FIELD(GUEST_SS_BASE, guest_ss_base),
 797         FIELD(GUEST_DS_BASE, guest_ds_base),
 798         FIELD(GUEST_FS_BASE, guest_fs_base),
 799         FIELD(GUEST_GS_BASE, guest_gs_base),
 800         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 801         FIELD(GUEST_TR_BASE, guest_tr_base),
 802         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 803         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 804         FIELD(GUEST_DR7, guest_dr7),
 805         FIELD(GUEST_RSP, guest_rsp),
 806         FIELD(GUEST_RIP, guest_rip),
 807         FIELD(GUEST_RFLAGS, guest_rflags),
 808         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 809         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 810         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 811         FIELD(HOST_CR0, host_cr0),
 812         FIELD(HOST_CR3, host_cr3),
 813         FIELD(HOST_CR4, host_cr4),
 814         FIELD(HOST_FS_BASE, host_fs_base),
 815         FIELD(HOST_GS_BASE, host_gs_base),
 816         FIELD(HOST_TR_BASE, host_tr_base),
 817         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 818         FIELD(HOST_IDTR_BASE, host_idtr_base),
 819         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 820         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 821         FIELD(HOST_RSP, host_rsp),
 822         FIELD(HOST_RIP, host_rip),
 823 };
 824
 825 static inline short vmcs_field_to_offset(unsigned long field)
 826 {
 827         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 828
 829         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 830             vmcs_field_to_offset_table[field] == 0)
 831                 return -ENOENT;
 832
 833         return vmcs_field_to_offset_table[field];
 834 }
 835
 836 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 837 {
 838         return to_vmx(vcpu)->nested.current_vmcs12;
 839 }
 840
 841 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 842 {
 843         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 844         if (is_error_page(page))
 845                 return NULL;
 846
 847         return page;
 848 }
 849
 850 static void nested_release_page(struct page *page)
 851 {
 852         kvm_release_page_dirty(page);
 853 }
 854
 855 static void nested_release_page_clean(struct page *page)
 856 {
 857         kvm_release_page_clean(page);
 858 }
 859
 860 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 861 static u64 construct_eptp(unsigned long root_hpa);
 862 static void kvm_cpu_vmxon(u64 addr);
 863 static void kvm_cpu_vmxoff(void);
 864 static bool vmx_xsaves_supported(void);
 865 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 866 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 867                             struct kvm_segment *var, int seg);
 868 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 869                             struct kvm_segment *var, int seg);
 870 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 871 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 872 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 873 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 874 static int alloc_identity_pagetable(struct kvm *kvm);
 875
 876 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 877 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 878 /*
 879  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 880  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 881  */
 882 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 883 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 884
 885 /*
 886  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 887  * can find which vCPU should be waken up.
 888  */
 889 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 890 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 891
 892 static unsigned long *vmx_io_bitmap_a;
 893 static unsigned long *vmx_io_bitmap_b;
 894 static unsigned long *vmx_msr_bitmap_legacy;
 895 static unsigned long *vmx_msr_bitmap_longmode;
 896 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 897 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 898 static unsigned long *vmx_msr_bitmap_nested;
 899 static unsigned long *vmx_vmread_bitmap;
 900 static unsigned long *vmx_vmwrite_bitmap;
 901
 902 static bool cpu_has_load_ia32_efer;
 903 static bool cpu_has_load_perf_global_ctrl;
 904
 905 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 906 static DEFINE_SPINLOCK(vmx_vpid_lock);
 907
 908 static struct vmcs_config {
 909         int size;
 910         int order;
 911         u32 revision_id;
 912         u32 pin_based_exec_ctrl;
 913         u32 cpu_based_exec_ctrl;
 914         u32 cpu_based_2nd_exec_ctrl;
 915         u32 vmexit_ctrl;
 916         u32 vmentry_ctrl;
 917 } vmcs_config;
 918
 919 static struct vmx_capability {
 920         u32 ept;
 921         u32 vpid;
 922 } vmx_capability;
 923
 924 #define VMX_SEGMENT_FIELD(seg)                                  \
 925         [VCPU_SREG_##seg] = {                                   \
 926                 .selector = GUEST_##seg##_SELECTOR,             \
 927                 .base = GUEST_##seg##_BASE,                     \
 928                 .limit = GUEST_##seg##_LIMIT,                   \
 929                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 930         }
 931
 932 static const struct kvm_vmx_segment_field {
 933         unsigned selector;
 934         unsigned base;
 935         unsigned limit;
 936         unsigned ar_bytes;
 937 } kvm_vmx_segment_fields[] = {
 938         VMX_SEGMENT_FIELD(CS),
 939         VMX_SEGMENT_FIELD(DS),
 940         VMX_SEGMENT_FIELD(ES),
 941         VMX_SEGMENT_FIELD(FS),
 942         VMX_SEGMENT_FIELD(GS),
 943         VMX_SEGMENT_FIELD(SS),
 944         VMX_SEGMENT_FIELD(TR),
 945         VMX_SEGMENT_FIELD(LDTR),
 946 };
 947
 948 static u64 host_efer;
 949
 950 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 951
 952 /*
 953  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 954  * away by decrementing the array size.
 955  */
 956 static const u32 vmx_msr_index[] = {
 957 #ifdef CONFIG_X86_64
 958         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 959 #endif
 960         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 961 };
 962
 963 static inline bool is_exception_n(u32 intr_info, u8 vector)
 964 {
 965         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 966                              INTR_INFO_VALID_MASK)) ==
 967                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 968 }
 969
 970 static inline bool is_debug(u32 intr_info)
 971 {
 972         return is_exception_n(intr_info, DB_VECTOR);
 973 }
 974
 975 static inline bool is_breakpoint(u32 intr_info)
 976 {
 977         return is_exception_n(intr_info, BP_VECTOR);
 978 }
 979
 980 static inline bool is_page_fault(u32 intr_info)
 981 {
 982         return is_exception_n(intr_info, PF_VECTOR);
 983 }
 984
 985 static inline bool is_no_device(u32 intr_info)
 986 {
 987         return is_exception_n(intr_info, NM_VECTOR);
 988 }
 989
 990 static inline bool is_invalid_opcode(u32 intr_info)
 991 {
 992         return is_exception_n(intr_info, UD_VECTOR);
 993 }
 994
 995 static inline bool is_external_interrupt(u32 intr_info)
 996 {
 997         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 998                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 999 }
1000
1001 static inline bool is_machine_check(u32 intr_info)
1002 {
1003         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1004                              INTR_INFO_VALID_MASK)) ==
1005                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1006 }
1007
1008 static inline bool cpu_has_vmx_msr_bitmap(void)
1009 {
1010         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1011 }
1012
1013 static inline bool cpu_has_vmx_tpr_shadow(void)
1014 {
1015         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1016 }
1017
1018 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1019 {
1020         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1021 }
1022
1023 static inline bool cpu_has_secondary_exec_ctrls(void)
1024 {
1025         return vmcs_config.cpu_based_exec_ctrl &
1026                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1027 }
1028
1029 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1030 {
1031         return vmcs_config.cpu_based_2nd_exec_ctrl &
1032                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1033 }
1034
1035 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1039 }
1040
1041 static inline bool cpu_has_vmx_apic_register_virt(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1045 }
1046
1047 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1051 }
1052
1053 static inline bool cpu_has_vmx_posted_intr(void)
1054 {
1055         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1056                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1057 }
1058
1059 static inline bool cpu_has_vmx_apicv(void)
1060 {
1061         return cpu_has_vmx_apic_register_virt() &&
1062                 cpu_has_vmx_virtual_intr_delivery() &&
1063                 cpu_has_vmx_posted_intr();
1064 }
1065
1066 static inline bool cpu_has_vmx_flexpriority(void)
1067 {
1068         return cpu_has_vmx_tpr_shadow() &&
1069                 cpu_has_vmx_virtualize_apic_accesses();
1070 }
1071
1072 static inline bool cpu_has_vmx_ept_execute_only(void)
1073 {
1074         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1075 }
1076
1077 static inline bool cpu_has_vmx_ept_2m_page(void)
1078 {
1079         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1080 }
1081
1082 static inline bool cpu_has_vmx_ept_1g_page(void)
1083 {
1084         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1085 }
1086
1087 static inline bool cpu_has_vmx_ept_4levels(void)
1088 {
1089         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1090 }
1091
1092 static inline bool cpu_has_vmx_ept_ad_bits(void)
1093 {
1094         return vmx_capability.ept & VMX_EPT_AD_BIT;
1095 }
1096
1097 static inline bool cpu_has_vmx_invept_context(void)
1098 {
1099         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1100 }
1101
1102 static inline bool cpu_has_vmx_invept_global(void)
1103 {
1104         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1105 }
1106
1107 static inline bool cpu_has_vmx_invvpid_single(void)
1108 {
1109         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1110 }
1111
1112 static inline bool cpu_has_vmx_invvpid_global(void)
1113 {
1114         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1115 }
1116
1117 static inline bool cpu_has_vmx_ept(void)
1118 {
1119         return vmcs_config.cpu_based_2nd_exec_ctrl &
1120                 SECONDARY_EXEC_ENABLE_EPT;
1121 }
1122
1123 static inline bool cpu_has_vmx_unrestricted_guest(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1127 }
1128
1129 static inline bool cpu_has_vmx_ple(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1133 }
1134
1135 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1136 {
1137         return flexpriority_enabled && lapic_in_kernel(vcpu);
1138 }
1139
1140 static inline bool cpu_has_vmx_vpid(void)
1141 {
1142         return vmcs_config.cpu_based_2nd_exec_ctrl &
1143                 SECONDARY_EXEC_ENABLE_VPID;
1144 }
1145
1146 static inline bool cpu_has_vmx_rdtscp(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_RDTSCP;
1150 }
1151
1152 static inline bool cpu_has_vmx_invpcid(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_ENABLE_INVPCID;
1156 }
1157
1158 static inline bool cpu_has_virtual_nmis(void)
1159 {
1160         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1161 }
1162
1163 static inline bool cpu_has_vmx_wbinvd_exit(void)
1164 {
1165         return vmcs_config.cpu_based_2nd_exec_ctrl &
1166                 SECONDARY_EXEC_WBINVD_EXITING;
1167 }
1168
1169 static inline bool cpu_has_vmx_shadow_vmcs(void)
1170 {
1171         u64 vmx_msr;
1172         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1173         /* check if the cpu supports writing r/o exit information fields */
1174         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1175                 return false;
1176
1177         return vmcs_config.cpu_based_2nd_exec_ctrl &
1178                 SECONDARY_EXEC_SHADOW_VMCS;
1179 }
1180
1181 static inline bool cpu_has_vmx_pml(void)
1182 {
1183         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1184 }
1185
1186 static inline bool cpu_has_vmx_tsc_scaling(void)
1187 {
1188         return vmcs_config.cpu_based_2nd_exec_ctrl &
1189                 SECONDARY_EXEC_TSC_SCALING;
1190 }
1191
1192 static inline bool report_flexpriority(void)
1193 {
1194         return flexpriority_enabled;
1195 }
1196
1197 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1198 {
1199         return vmcs12->cpu_based_vm_exec_control & bit;
1200 }
1201
1202 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1203 {
1204         return (vmcs12->cpu_based_vm_exec_control &
1205                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1206                 (vmcs12->secondary_vm_exec_control & bit);
1207 }
1208
1209 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1210 {
1211         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1212 }
1213
1214 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1215 {
1216         return vmcs12->pin_based_vm_exec_control &
1217                 PIN_BASED_VMX_PREEMPTION_TIMER;
1218 }
1219
1220 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1221 {
1222         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1223 }
1224
1225 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1226 {
1227         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1228                 vmx_xsaves_supported();
1229 }
1230
1231 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1234 }
1235
1236 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1237 {
1238         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1239 }
1240
1241 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1242 {
1243         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1244 }
1245
1246 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1247 {
1248         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1249 }
1250
1251 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1252 {
1253         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1254 }
1255
1256 static inline bool is_exception(u32 intr_info)
1257 {
1258         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1259                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1260 }
1261
1262 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1263                               u32 exit_intr_info,
1264                               unsigned long exit_qualification);
1265 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1266                         struct vmcs12 *vmcs12,
1267                         u32 reason, unsigned long qualification);
1268
1269 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1270 {
1271         int i;
1272
1273         for (i = 0; i < vmx->nmsrs; ++i)
1274                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1275                         return i;
1276         return -1;
1277 }
1278
1279 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1280 {
1281     struct {
1282         u64 vpid : 16;
1283         u64 rsvd : 48;
1284         u64 gva;
1285     } operand = { vpid, 0, gva };
1286
1287     asm volatile (__ex(ASM_VMX_INVVPID)
1288                   /* CF==1 or ZF==1 --> rc = -1 */
1289                   "; ja 1f ; ud2 ; 1:"
1290                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1291 }
1292
1293 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1294 {
1295         struct {
1296                 u64 eptp, gpa;
1297         } operand = {eptp, gpa};
1298
1299         asm volatile (__ex(ASM_VMX_INVEPT)
1300                         /* CF==1 or ZF==1 --> rc = -1 */
1301                         "; ja 1f ; ud2 ; 1:\n"
1302                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1303 }
1304
1305 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1306 {
1307         int i;
1308
1309         i = __find_msr_index(vmx, msr);
1310         if (i >= 0)
1311                 return &vmx->guest_msrs[i];
1312         return NULL;
1313 }
1314
1315 static void vmcs_clear(struct vmcs *vmcs)
1316 {
1317         u64 phys_addr = __pa(vmcs);
1318         u8 error;
1319
1320         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1321                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1322                       : "cc", "memory");
1323         if (error)
1324                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1325                        vmcs, phys_addr);
1326 }
1327
1328 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1329 {
1330         vmcs_clear(loaded_vmcs->vmcs);
1331         loaded_vmcs->cpu = -1;
1332         loaded_vmcs->launched = 0;
1333 }
1334
1335 static void vmcs_load(struct vmcs *vmcs)
1336 {
1337         u64 phys_addr = __pa(vmcs);
1338         u8 error;
1339
1340         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1341                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1342                         : "cc", "memory");
1343         if (error)
1344                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1345                        vmcs, phys_addr);
1346 }
1347
1348 #ifdef CONFIG_KEXEC_CORE
1349 /*
1350  * This bitmap is used to indicate whether the vmclear
1351  * operation is enabled on all cpus. All disabled by
1352  * default.
1353  */
1354 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1355
1356 static inline void crash_enable_local_vmclear(int cpu)
1357 {
1358         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1359 }
1360
1361 static inline void crash_disable_local_vmclear(int cpu)
1362 {
1363         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1364 }
1365
1366 static inline int crash_local_vmclear_enabled(int cpu)
1367 {
1368         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1369 }
1370
1371 static void crash_vmclear_local_loaded_vmcss(void)
1372 {
1373         int cpu = raw_smp_processor_id();
1374         struct loaded_vmcs *v;
1375
1376         if (!crash_local_vmclear_enabled(cpu))
1377                 return;
1378
1379         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1380                             loaded_vmcss_on_cpu_link)
1381                 vmcs_clear(v->vmcs);
1382 }
1383 #else
1384 static inline void crash_enable_local_vmclear(int cpu) { }
1385 static inline void crash_disable_local_vmclear(int cpu) { }
1386 #endif /* CONFIG_KEXEC_CORE */
1387
1388 static void __loaded_vmcs_clear(void *arg)
1389 {
1390         struct loaded_vmcs *loaded_vmcs = arg;
1391         int cpu = raw_smp_processor_id();
1392
1393         if (loaded_vmcs->cpu != cpu)
1394                 return; /* vcpu migration can race with cpu offline */
1395         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1396                 per_cpu(current_vmcs, cpu) = NULL;
1397         crash_disable_local_vmclear(cpu);
1398         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1399
1400         /*
1401          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1402          * is before setting loaded_vmcs->vcpu to -1 which is done in
1403          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1404          * then adds the vmcs into percpu list before it is deleted.
1405          */
1406         smp_wmb();
1407
1408         loaded_vmcs_init(loaded_vmcs);
1409         crash_enable_local_vmclear(cpu);
1410 }
1411
1412 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1413 {
1414         int cpu = loaded_vmcs->cpu;
1415
1416         if (cpu != -1)
1417                 smp_call_function_single(cpu,
1418                          __loaded_vmcs_clear, loaded_vmcs, 1);
1419 }
1420
1421 static inline void vpid_sync_vcpu_single(int vpid)
1422 {
1423         if (vpid == 0)
1424                 return;
1425
1426         if (cpu_has_vmx_invvpid_single())
1427                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1428 }
1429
1430 static inline void vpid_sync_vcpu_global(void)
1431 {
1432         if (cpu_has_vmx_invvpid_global())
1433                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1434 }
1435
1436 static inline void vpid_sync_context(int vpid)
1437 {
1438         if (cpu_has_vmx_invvpid_single())
1439                 vpid_sync_vcpu_single(vpid);
1440         else
1441                 vpid_sync_vcpu_global();
1442 }
1443
1444 static inline void ept_sync_global(void)
1445 {
1446         if (cpu_has_vmx_invept_global())
1447                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1448 }
1449
1450 static inline void ept_sync_context(u64 eptp)
1451 {
1452         if (enable_ept) {
1453                 if (cpu_has_vmx_invept_context())
1454                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1455                 else
1456                         ept_sync_global();
1457         }
1458 }
1459
1460 static __always_inline void vmcs_check16(unsigned long field)
1461 {
1462         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1463                          "16-bit accessor invalid for 64-bit field");
1464         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1465                          "16-bit accessor invalid for 64-bit high field");
1466         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1467                          "16-bit accessor invalid for 32-bit high field");
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1469                          "16-bit accessor invalid for natural width field");
1470 }
1471
1472 static __always_inline void vmcs_check32(unsigned long field)
1473 {
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1475                          "32-bit accessor invalid for 16-bit field");
1476         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1477                          "32-bit accessor invalid for natural width field");
1478 }
1479
1480 static __always_inline void vmcs_check64(unsigned long field)
1481 {
1482         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1483                          "64-bit accessor invalid for 16-bit field");
1484         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1485                          "64-bit accessor invalid for 64-bit high field");
1486         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1487                          "64-bit accessor invalid for 32-bit field");
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1489                          "64-bit accessor invalid for natural width field");
1490 }
1491
1492 static __always_inline void vmcs_checkl(unsigned long field)
1493 {
1494         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1495                          "Natural width accessor invalid for 16-bit field");
1496         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1497                          "Natural width accessor invalid for 64-bit field");
1498         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1499                          "Natural width accessor invalid for 64-bit high field");
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1501                          "Natural width accessor invalid for 32-bit field");
1502 }
1503
1504 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1505 {
1506         unsigned long value;
1507
1508         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1509                       : "=a"(value) : "d"(field) : "cc");
1510         return value;
1511 }
1512
1513 static __always_inline u16 vmcs_read16(unsigned long field)
1514 {
1515         vmcs_check16(field);
1516         return __vmcs_readl(field);
1517 }
1518
1519 static __always_inline u32 vmcs_read32(unsigned long field)
1520 {
1521         vmcs_check32(field);
1522         return __vmcs_readl(field);
1523 }
1524
1525 static __always_inline u64 vmcs_read64(unsigned long field)
1526 {
1527         vmcs_check64(field);
1528 #ifdef CONFIG_X86_64
1529         return __vmcs_readl(field);
1530 #else
1531         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1532 #endif
1533 }
1534
1535 static __always_inline unsigned long vmcs_readl(unsigned long field)
1536 {
1537         vmcs_checkl(field);
1538         return __vmcs_readl(field);
1539 }
1540
1541 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1542 {
1543         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1544                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1545         dump_stack();
1546 }
1547
1548 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1549 {
1550         u8 error;
1551
1552         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1553                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1554         if (unlikely(error))
1555                 vmwrite_error(field, value);
1556 }
1557
1558 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1559 {
1560         vmcs_check16(field);
1561         __vmcs_writel(field, value);
1562 }
1563
1564 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1565 {
1566         vmcs_check32(field);
1567         __vmcs_writel(field, value);
1568 }
1569
1570 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1571 {
1572         vmcs_check64(field);
1573         __vmcs_writel(field, value);
1574 #ifndef CONFIG_X86_64
1575         asm volatile ("");
1576         __vmcs_writel(field+1, value >> 32);
1577 #endif
1578 }
1579
1580 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1581 {
1582         vmcs_checkl(field);
1583         __vmcs_writel(field, value);
1584 }
1585
1586 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1587 {
1588         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1589                          "vmcs_clear_bits does not support 64-bit fields");
1590         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1591 }
1592
1593 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1594 {
1595         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1596                          "vmcs_set_bits does not support 64-bit fields");
1597         __vmcs_writel(field, __vmcs_readl(field) | mask);
1598 }
1599
1600 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1601 {
1602         vmcs_write32(VM_ENTRY_CONTROLS, val);
1603         vmx->vm_entry_controls_shadow = val;
1604 }
1605
1606 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1607 {
1608         if (vmx->vm_entry_controls_shadow != val)
1609                 vm_entry_controls_init(vmx, val);
1610 }
1611
1612 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1613 {
1614         return vmx->vm_entry_controls_shadow;
1615 }
1616
1617
1618 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1619 {
1620         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1621 }
1622
1623 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1624 {
1625         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1626 }
1627
1628 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1629 {
1630         vmcs_write32(VM_EXIT_CONTROLS, val);
1631         vmx->vm_exit_controls_shadow = val;
1632 }
1633
1634 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1635 {
1636         if (vmx->vm_exit_controls_shadow != val)
1637                 vm_exit_controls_init(vmx, val);
1638 }
1639
1640 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1641 {
1642         return vmx->vm_exit_controls_shadow;
1643 }
1644
1645
1646 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1647 {
1648         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1649 }
1650
1651 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1652 {
1653         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1654 }
1655
1656 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1657 {
1658         vmx->segment_cache.bitmask = 0;
1659 }
1660
1661 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1662                                        unsigned field)
1663 {
1664         bool ret;
1665         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1666
1667         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1668                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1669                 vmx->segment_cache.bitmask = 0;
1670         }
1671         ret = vmx->segment_cache.bitmask & mask;
1672         vmx->segment_cache.bitmask |= mask;
1673         return ret;
1674 }
1675
1676 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1677 {
1678         u16 *p = &vmx->segment_cache.seg[seg].selector;
1679
1680         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1681                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1682         return *p;
1683 }
1684
1685 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1686 {
1687         ulong *p = &vmx->segment_cache.seg[seg].base;
1688
1689         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1690                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1691         return *p;
1692 }
1693
1694 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1695 {
1696         u32 *p = &vmx->segment_cache.seg[seg].limit;
1697
1698         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1699                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1700         return *p;
1701 }
1702
1703 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1704 {
1705         u32 *p = &vmx->segment_cache.seg[seg].ar;
1706
1707         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1708                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1709         return *p;
1710 }
1711
1712 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1713 {
1714         u32 eb;
1715
1716         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1717              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1718         if ((vcpu->guest_debug &
1719              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1720             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1721                 eb |= 1u << BP_VECTOR;
1722         if (to_vmx(vcpu)->rmode.vm86_active)
1723                 eb = ~0;
1724         if (enable_ept)
1725                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1726         if (vcpu->fpu_active)
1727                 eb &= ~(1u << NM_VECTOR);
1728
1729         /* When we are running a nested L2 guest and L1 specified for it a
1730          * certain exception bitmap, we must trap the same exceptions and pass
1731          * them to L1. When running L2, we will only handle the exceptions
1732          * specified above if L1 did not want them.
1733          */
1734         if (is_guest_mode(vcpu))
1735                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1736
1737         vmcs_write32(EXCEPTION_BITMAP, eb);
1738 }
1739
1740 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1741                 unsigned long entry, unsigned long exit)
1742 {
1743         vm_entry_controls_clearbit(vmx, entry);
1744         vm_exit_controls_clearbit(vmx, exit);
1745 }
1746
1747 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1748 {
1749         unsigned i;
1750         struct msr_autoload *m = &vmx->msr_autoload;
1751
1752         switch (msr) {
1753         case MSR_EFER:
1754                 if (cpu_has_load_ia32_efer) {
1755                         clear_atomic_switch_msr_special(vmx,
1756                                         VM_ENTRY_LOAD_IA32_EFER,
1757                                         VM_EXIT_LOAD_IA32_EFER);
1758                         return;
1759                 }
1760                 break;
1761         case MSR_CORE_PERF_GLOBAL_CTRL:
1762                 if (cpu_has_load_perf_global_ctrl) {
1763                         clear_atomic_switch_msr_special(vmx,
1764                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1765                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1766                         return;
1767                 }
1768                 break;
1769         }
1770
1771         for (i = 0; i < m->nr; ++i)
1772                 if (m->guest[i].index == msr)
1773                         break;
1774
1775         if (i == m->nr)
1776                 return;
1777         --m->nr;
1778         m->guest[i] = m->guest[m->nr];
1779         m->host[i] = m->host[m->nr];
1780         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1781         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1782 }
1783
1784 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1785                 unsigned long entry, unsigned long exit,
1786                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1787                 u64 guest_val, u64 host_val)
1788 {
1789         vmcs_write64(guest_val_vmcs, guest_val);
1790         vmcs_write64(host_val_vmcs, host_val);
1791         vm_entry_controls_setbit(vmx, entry);
1792         vm_exit_controls_setbit(vmx, exit);
1793 }
1794
1795 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1796                                   u64 guest_val, u64 host_val)
1797 {
1798         unsigned i;
1799         struct msr_autoload *m = &vmx->msr_autoload;
1800
1801         switch (msr) {
1802         case MSR_EFER:
1803                 if (cpu_has_load_ia32_efer) {
1804                         add_atomic_switch_msr_special(vmx,
1805                                         VM_ENTRY_LOAD_IA32_EFER,
1806                                         VM_EXIT_LOAD_IA32_EFER,
1807                                         GUEST_IA32_EFER,
1808                                         HOST_IA32_EFER,
1809                                         guest_val, host_val);
1810                         return;
1811                 }
1812                 break;
1813         case MSR_CORE_PERF_GLOBAL_CTRL:
1814                 if (cpu_has_load_perf_global_ctrl) {
1815                         add_atomic_switch_msr_special(vmx,
1816                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1817                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1818                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1819                                         HOST_IA32_PERF_GLOBAL_CTRL,
1820                                         guest_val, host_val);
1821                         return;
1822                 }
1823                 break;
1824         }
1825
1826         for (i = 0; i < m->nr; ++i)
1827                 if (m->guest[i].index == msr)
1828                         break;
1829
1830         if (i == NR_AUTOLOAD_MSRS) {
1831                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1832                                 "Can't add msr %x\n", msr);
1833                 return;
1834         } else if (i == m->nr) {
1835                 ++m->nr;
1836                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1837                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1838         }
1839
1840         m->guest[i].index = msr;
1841         m->guest[i].value = guest_val;
1842         m->host[i].index = msr;
1843         m->host[i].value = host_val;
1844 }
1845
1846 static void reload_tss(void)
1847 {
1848         /*
1849          * VT restores TR but not its size.  Useless.
1850          */
1851         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1852         struct desc_struct *descs;
1853
1854         descs = (void *)gdt->address;
1855         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1856         load_TR_desc();
1857 }
1858
1859 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1860 {
1861         u64 guest_efer;
1862         u64 ignore_bits;
1863
1864         guest_efer = vmx->vcpu.arch.efer;
1865
1866         /*
1867          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1868          * outside long mode
1869          */
1870         ignore_bits = EFER_NX | EFER_SCE;
1871 #ifdef CONFIG_X86_64
1872         ignore_bits |= EFER_LMA | EFER_LME;
1873         /* SCE is meaningful only in long mode on Intel */
1874         if (guest_efer & EFER_LMA)
1875                 ignore_bits &= ~(u64)EFER_SCE;
1876 #endif
1877         guest_efer &= ~ignore_bits;
1878         guest_efer |= host_efer & ignore_bits;
1879         vmx->guest_msrs[efer_offset].data = guest_efer;
1880         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1881
1882         clear_atomic_switch_msr(vmx, MSR_EFER);
1883
1884         /*
1885          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1886          * On CPUs that support "load IA32_EFER", always switch EFER
1887          * atomically, since it's faster than switching it manually.
1888          */
1889         if (cpu_has_load_ia32_efer ||
1890             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1891                 guest_efer = vmx->vcpu.arch.efer;
1892                 if (!(guest_efer & EFER_LMA))
1893                         guest_efer &= ~EFER_LME;
1894                 if (guest_efer != host_efer)
1895                         add_atomic_switch_msr(vmx, MSR_EFER,
1896                                               guest_efer, host_efer);
1897                 return false;
1898         }
1899
1900         return true;
1901 }
1902
1903 static unsigned long segment_base(u16 selector)
1904 {
1905         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1906         struct desc_struct *d;
1907         unsigned long table_base;
1908         unsigned long v;
1909
1910         if (!(selector & ~3))
1911                 return 0;
1912
1913         table_base = gdt->address;
1914
1915         if (selector & 4) {           /* from ldt */
1916                 u16 ldt_selector = kvm_read_ldt();
1917
1918                 if (!(ldt_selector & ~3))
1919                         return 0;
1920
1921                 table_base = segment_base(ldt_selector);
1922         }
1923         d = (struct desc_struct *)(table_base + (selector & ~7));
1924         v = get_desc_base(d);
1925 #ifdef CONFIG_X86_64
1926        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1927                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1928 #endif
1929         return v;
1930 }
1931
1932 static inline unsigned long kvm_read_tr_base(void)
1933 {
1934         u16 tr;
1935         asm("str %0" : "=g"(tr));
1936         return segment_base(tr);
1937 }
1938
1939 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1940 {
1941         struct vcpu_vmx *vmx = to_vmx(vcpu);
1942         int i;
1943
1944         if (vmx->host_state.loaded)
1945                 return;
1946
1947         vmx->host_state.loaded = 1;
1948         /*
1949          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1950          * allow segment selectors with cpl > 0 or ti == 1.
1951          */
1952         vmx->host_state.ldt_sel = kvm_read_ldt();
1953         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1954         savesegment(fs, vmx->host_state.fs_sel);
1955         if (!(vmx->host_state.fs_sel & 7)) {
1956                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1957                 vmx->host_state.fs_reload_needed = 0;
1958         } else {
1959                 vmcs_write16(HOST_FS_SELECTOR, 0);
1960                 vmx->host_state.fs_reload_needed = 1;
1961         }
1962         savesegment(gs, vmx->host_state.gs_sel);
1963         if (!(vmx->host_state.gs_sel & 7))
1964                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1965         else {
1966                 vmcs_write16(HOST_GS_SELECTOR, 0);
1967                 vmx->host_state.gs_ldt_reload_needed = 1;
1968         }
1969
1970 #ifdef CONFIG_X86_64
1971         savesegment(ds, vmx->host_state.ds_sel);
1972         savesegment(es, vmx->host_state.es_sel);
1973 #endif
1974
1975 #ifdef CONFIG_X86_64
1976         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1977         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1978 #else
1979         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1980         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1981 #endif
1982
1983 #ifdef CONFIG_X86_64
1984         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1985         if (is_long_mode(&vmx->vcpu))
1986                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1987 #endif
1988         if (boot_cpu_has(X86_FEATURE_MPX))
1989                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1990         for (i = 0; i < vmx->save_nmsrs; ++i)
1991                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1992                                    vmx->guest_msrs[i].data,
1993                                    vmx->guest_msrs[i].mask);
1994 }
1995
1996 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1997 {
1998         if (!vmx->host_state.loaded)
1999                 return;
2000
2001         ++vmx->vcpu.stat.host_state_reload;
2002         vmx->host_state.loaded = 0;
2003 #ifdef CONFIG_X86_64
2004         if (is_long_mode(&vmx->vcpu))
2005                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2006 #endif
2007         if (vmx->host_state.gs_ldt_reload_needed) {
2008                 kvm_load_ldt(vmx->host_state.ldt_sel);
2009 #ifdef CONFIG_X86_64
2010                 load_gs_index(vmx->host_state.gs_sel);
2011 #else
2012                 loadsegment(gs, vmx->host_state.gs_sel);
2013 #endif
2014         }
2015         if (vmx->host_state.fs_reload_needed)
2016                 loadsegment(fs, vmx->host_state.fs_sel);
2017 #ifdef CONFIG_X86_64
2018         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2019                 loadsegment(ds, vmx->host_state.ds_sel);
2020                 loadsegment(es, vmx->host_state.es_sel);
2021         }
2022 #endif
2023         reload_tss();
2024 #ifdef CONFIG_X86_64
2025         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2026 #endif
2027         if (vmx->host_state.msr_host_bndcfgs)
2028                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2029         /*
2030          * If the FPU is not active (through the host task or
2031          * the guest vcpu), then restore the cr0.TS bit.
2032          */
2033         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2034                 stts();
2035         load_gdt(this_cpu_ptr(&host_gdt));
2036 }
2037
2038 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2039 {
2040         preempt_disable();
2041         __vmx_load_host_state(vmx);
2042         preempt_enable();
2043 }
2044
2045 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2046 {
2047         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2048         struct pi_desc old, new;
2049         unsigned int dest;
2050
2051         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2052                 !irq_remapping_cap(IRQ_POSTING_CAP))
2053                 return;
2054
2055         do {
2056                 old.control = new.control = pi_desc->control;
2057
2058                 /*
2059                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2060                  * are two possible cases:
2061                  * 1. After running 'pre_block', context switch
2062                  *    happened. For this case, 'sn' was set in
2063                  *    vmx_vcpu_put(), so we need to clear it here.
2064                  * 2. After running 'pre_block', we were blocked,
2065                  *    and woken up by some other guy. For this case,
2066                  *    we don't need to do anything, 'pi_post_block'
2067                  *    will do everything for us. However, we cannot
2068                  *    check whether it is case #1 or case #2 here
2069                  *    (maybe, not needed), so we also clear sn here,
2070                  *    I think it is not a big deal.
2071                  */
2072                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2073                         if (vcpu->cpu != cpu) {
2074                                 dest = cpu_physical_id(cpu);
2075
2076                                 if (x2apic_enabled())
2077                                         new.ndst = dest;
2078                                 else
2079                                         new.ndst = (dest << 8) & 0xFF00;
2080                         }
2081
2082                         /* set 'NV' to 'notification vector' */
2083                         new.nv = POSTED_INTR_VECTOR;
2084                 }
2085
2086                 /* Allow posting non-urgent interrupts */
2087                 new.sn = 0;
2088         } while (cmpxchg(&pi_desc->control, old.control,
2089                         new.control) != old.control);
2090 }
2091 /*
2092  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2093  * vcpu mutex is already taken.
2094  */
2095 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2096 {
2097         struct vcpu_vmx *vmx = to_vmx(vcpu);
2098         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2099
2100         if (!vmm_exclusive)
2101                 kvm_cpu_vmxon(phys_addr);
2102         else if (vmx->loaded_vmcs->cpu != cpu)
2103                 loaded_vmcs_clear(vmx->loaded_vmcs);
2104
2105         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2106                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2107                 vmcs_load(vmx->loaded_vmcs->vmcs);
2108         }
2109
2110         if (vmx->loaded_vmcs->cpu != cpu) {
2111                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2112                 unsigned long sysenter_esp;
2113
2114                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2115                 local_irq_disable();
2116                 crash_disable_local_vmclear(cpu);
2117
2118                 /*
2119                  * Read loaded_vmcs->cpu should be before fetching
2120                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2121                  * See the comments in __loaded_vmcs_clear().
2122                  */
2123                 smp_rmb();
2124
2125                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2126                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2127                 crash_enable_local_vmclear(cpu);
2128                 local_irq_enable();
2129
2130                 /*
2131                  * Linux uses per-cpu TSS and GDT, so set these when switching
2132                  * processors.
2133                  */
2134                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2135                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2136
2137                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2138                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2139
2140                 /* Setup TSC multiplier */
2141                 if (cpu_has_vmx_tsc_scaling())
2142                         vmcs_write64(TSC_MULTIPLIER,
2143                                      vcpu->arch.tsc_scaling_ratio);
2144
2145                 vmx->loaded_vmcs->cpu = cpu;
2146         }
2147
2148         vmx_vcpu_pi_load(vcpu, cpu);
2149 }
2150
2151 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2152 {
2153         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2154
2155         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2156                 !irq_remapping_cap(IRQ_POSTING_CAP))
2157                 return;
2158
2159         /* Set SN when the vCPU is preempted */
2160         if (vcpu->preempted)
2161                 pi_set_sn(pi_desc);
2162 }
2163
2164 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2165 {
2166         vmx_vcpu_pi_put(vcpu);
2167
2168         __vmx_load_host_state(to_vmx(vcpu));
2169         if (!vmm_exclusive) {
2170                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2171                 vcpu->cpu = -1;
2172                 kvm_cpu_vmxoff();
2173         }
2174 }
2175
2176 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2177 {
2178         ulong cr0;
2179
2180         if (vcpu->fpu_active)
2181                 return;
2182         vcpu->fpu_active = 1;
2183         cr0 = vmcs_readl(GUEST_CR0);
2184         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2185         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2186         vmcs_writel(GUEST_CR0, cr0);
2187         update_exception_bitmap(vcpu);
2188         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2189         if (is_guest_mode(vcpu))
2190                 vcpu->arch.cr0_guest_owned_bits &=
2191                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2192         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2193 }
2194
2195 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2196
2197 /*
2198  * Return the cr0 value that a nested guest would read. This is a combination
2199  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2200  * its hypervisor (cr0_read_shadow).
2201  */
2202 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2203 {
2204         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2205                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2206 }
2207 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2208 {
2209         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2210                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2211 }
2212
2213 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2214 {
2215         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2216          * set this *before* calling this function.
2217          */
2218         vmx_decache_cr0_guest_bits(vcpu);
2219         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2220         update_exception_bitmap(vcpu);
2221         vcpu->arch.cr0_guest_owned_bits = 0;
2222         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2223         if (is_guest_mode(vcpu)) {
2224                 /*
2225                  * L1's specified read shadow might not contain the TS bit,
2226                  * so now that we turned on shadowing of this bit, we need to
2227                  * set this bit of the shadow. Like in nested_vmx_run we need
2228                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2229                  * up-to-date here because we just decached cr0.TS (and we'll
2230                  * only update vmcs12->guest_cr0 on nested exit).
2231                  */
2232                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2233                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2234                         (vcpu->arch.cr0 & X86_CR0_TS);
2235                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2236         } else
2237                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2238 }
2239
2240 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2241 {
2242         unsigned long rflags, save_rflags;
2243
2244         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2245                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2246                 rflags = vmcs_readl(GUEST_RFLAGS);
2247                 if (to_vmx(vcpu)->rmode.vm86_active) {
2248                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2249                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2250                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2251                 }
2252                 to_vmx(vcpu)->rflags = rflags;
2253         }
2254         return to_vmx(vcpu)->rflags;
2255 }
2256
2257 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2258 {
2259         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2260         to_vmx(vcpu)->rflags = rflags;
2261         if (to_vmx(vcpu)->rmode.vm86_active) {
2262                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2263                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2264         }
2265         vmcs_writel(GUEST_RFLAGS, rflags);
2266 }
2267
2268 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2269 {
2270         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2271         int ret = 0;
2272
2273         if (interruptibility & GUEST_INTR_STATE_STI)
2274                 ret |= KVM_X86_SHADOW_INT_STI;
2275         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2276                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2277
2278         return ret;
2279 }
2280
2281 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2282 {
2283         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2284         u32 interruptibility = interruptibility_old;
2285
2286         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2287
2288         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2289                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2290         else if (mask & KVM_X86_SHADOW_INT_STI)
2291                 interruptibility |= GUEST_INTR_STATE_STI;
2292
2293         if ((interruptibility != interruptibility_old))
2294                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2295 }
2296
2297 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2298 {
2299         unsigned long rip;
2300
2301         rip = kvm_rip_read(vcpu);
2302         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2303         kvm_rip_write(vcpu, rip);
2304
2305         /* skipping an emulated instruction also counts */
2306         vmx_set_interrupt_shadow(vcpu, 0);
2307 }
2308
2309 /*
2310  * KVM wants to inject page-faults which it got to the guest. This function
2311  * checks whether in a nested guest, we need to inject them to L1 or L2.
2312  */
2313 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2314 {
2315         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2316
2317         if (!(vmcs12->exception_bitmap & (1u << nr)))
2318                 return 0;
2319
2320         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2321                           vmcs_read32(VM_EXIT_INTR_INFO),
2322                           vmcs_readl(EXIT_QUALIFICATION));
2323         return 1;
2324 }
2325
2326 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2327                                 bool has_error_code, u32 error_code,
2328                                 bool reinject)
2329 {
2330         struct vcpu_vmx *vmx = to_vmx(vcpu);
2331         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2332
2333         if (!reinject && is_guest_mode(vcpu) &&
2334             nested_vmx_check_exception(vcpu, nr))
2335                 return;
2336
2337         if (has_error_code) {
2338                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2339                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2340         }
2341
2342         if (vmx->rmode.vm86_active) {
2343                 int inc_eip = 0;
2344                 if (kvm_exception_is_soft(nr))
2345                         inc_eip = vcpu->arch.event_exit_inst_len;
2346                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2347                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2348                 return;
2349         }
2350
2351         if (kvm_exception_is_soft(nr)) {
2352                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2353                              vmx->vcpu.arch.event_exit_inst_len);
2354                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2355         } else
2356                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2357
2358         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2359 }
2360
2361 static bool vmx_rdtscp_supported(void)
2362 {
2363         return cpu_has_vmx_rdtscp();
2364 }
2365
2366 static bool vmx_invpcid_supported(void)
2367 {
2368         return cpu_has_vmx_invpcid() && enable_ept;
2369 }
2370
2371 /*
2372  * Swap MSR entry in host/guest MSR entry array.
2373  */
2374 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2375 {
2376         struct shared_msr_entry tmp;
2377
2378         tmp = vmx->guest_msrs[to];
2379         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2380         vmx->guest_msrs[from] = tmp;
2381 }
2382
2383 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2384 {
2385         unsigned long *msr_bitmap;
2386
2387         if (is_guest_mode(vcpu))
2388                 msr_bitmap = vmx_msr_bitmap_nested;
2389         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2390                 if (is_long_mode(vcpu))
2391                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2392                 else
2393                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2394         } else {
2395                 if (is_long_mode(vcpu))
2396                         msr_bitmap = vmx_msr_bitmap_longmode;
2397                 else
2398                         msr_bitmap = vmx_msr_bitmap_legacy;
2399         }
2400
2401         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2402 }
2403
2404 /*
2405  * Set up the vmcs to automatically save and restore system
2406  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2407  * mode, as fiddling with msrs is very expensive.
2408  */
2409 static void setup_msrs(struct vcpu_vmx *vmx)
2410 {
2411         int save_nmsrs, index;
2412
2413         save_nmsrs = 0;
2414 #ifdef CONFIG_X86_64
2415         if (is_long_mode(&vmx->vcpu)) {
2416                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2417                 if (index >= 0)
2418                         move_msr_up(vmx, index, save_nmsrs++);
2419                 index = __find_msr_index(vmx, MSR_LSTAR);
2420                 if (index >= 0)
2421                         move_msr_up(vmx, index, save_nmsrs++);
2422                 index = __find_msr_index(vmx, MSR_CSTAR);
2423                 if (index >= 0)
2424                         move_msr_up(vmx, index, save_nmsrs++);
2425                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2426                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2427                         move_msr_up(vmx, index, save_nmsrs++);
2428                 /*
2429                  * MSR_STAR is only needed on long mode guests, and only
2430                  * if efer.sce is enabled.
2431                  */
2432                 index = __find_msr_index(vmx, MSR_STAR);
2433                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2434                         move_msr_up(vmx, index, save_nmsrs++);
2435         }
2436 #endif
2437         index = __find_msr_index(vmx, MSR_EFER);
2438         if (index >= 0 && update_transition_efer(vmx, index))
2439                 move_msr_up(vmx, index, save_nmsrs++);
2440
2441         vmx->save_nmsrs = save_nmsrs;
2442
2443         if (cpu_has_vmx_msr_bitmap())
2444                 vmx_set_msr_bitmap(&vmx->vcpu);
2445 }
2446
2447 /*
2448  * reads and returns guest's timestamp counter "register"
2449  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2450  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2451  */
2452 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2453 {
2454         u64 host_tsc, tsc_offset;
2455
2456         host_tsc = rdtsc();
2457         tsc_offset = vmcs_read64(TSC_OFFSET);
2458         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2459 }
2460
2461 /*
2462  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2463  * counter, even if a nested guest (L2) is currently running.
2464  */
2465 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2466 {
2467         u64 tsc_offset;
2468
2469         tsc_offset = is_guest_mode(vcpu) ?
2470                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2471                 vmcs_read64(TSC_OFFSET);
2472         return host_tsc + tsc_offset;
2473 }
2474
2475 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2476 {
2477         return vmcs_read64(TSC_OFFSET);
2478 }
2479
2480 /*
2481  * writes 'offset' into guest's timestamp counter offset register
2482  */
2483 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2484 {
2485         if (is_guest_mode(vcpu)) {
2486                 /*
2487                  * We're here if L1 chose not to trap WRMSR to TSC. According
2488                  * to the spec, this should set L1's TSC; The offset that L1
2489                  * set for L2 remains unchanged, and still needs to be added
2490                  * to the newly set TSC to get L2's TSC.
2491                  */
2492                 struct vmcs12 *vmcs12;
2493                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2494                 /* recalculate vmcs02.TSC_OFFSET: */
2495                 vmcs12 = get_vmcs12(vcpu);
2496                 vmcs_write64(TSC_OFFSET, offset +
2497                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2498                          vmcs12->tsc_offset : 0));
2499         } else {
2500                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2501                                            vmcs_read64(TSC_OFFSET), offset);
2502                 vmcs_write64(TSC_OFFSET, offset);
2503         }
2504 }
2505
2506 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2507 {
2508         u64 offset = vmcs_read64(TSC_OFFSET);
2509
2510         vmcs_write64(TSC_OFFSET, offset + adjustment);
2511         if (is_guest_mode(vcpu)) {
2512                 /* Even when running L2, the adjustment needs to apply to L1 */
2513                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2514         } else
2515                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2516                                            offset + adjustment);
2517 }
2518
2519 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2520 {
2521         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2522         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2523 }
2524
2525 /*
2526  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2527  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2528  * all guests if the "nested" module option is off, and can also be disabled
2529  * for a single guest by disabling its VMX cpuid bit.
2530  */
2531 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2532 {
2533         return nested && guest_cpuid_has_vmx(vcpu);
2534 }
2535
2536 /*
2537  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2538  * returned for the various VMX controls MSRs when nested VMX is enabled.
2539  * The same values should also be used to verify that vmcs12 control fields are
2540  * valid during nested entry from L1 to L2.
2541  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2542  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2543  * bit in the high half is on if the corresponding bit in the control field
2544  * may be on. See also vmx_control_verify().
2545  */
2546 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2547 {
2548         /*
2549          * Note that as a general rule, the high half of the MSRs (bits in
2550          * the control fields which may be 1) should be initialized by the
2551          * intersection of the underlying hardware's MSR (i.e., features which
2552          * can be supported) and the list of features we want to expose -
2553          * because they are known to be properly supported in our code.
2554          * Also, usually, the low half of the MSRs (bits which must be 1) can
2555          * be set to 0, meaning that L1 may turn off any of these bits. The
2556          * reason is that if one of these bits is necessary, it will appear
2557          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2558          * fields of vmcs01 and vmcs02, will turn these bits off - and
2559          * nested_vmx_exit_handled() will not pass related exits to L1.
2560          * These rules have exceptions below.
2561          */
2562
2563         /* pin-based controls */
2564         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2565                 vmx->nested.nested_vmx_pinbased_ctls_low,
2566                 vmx->nested.nested_vmx_pinbased_ctls_high);
2567         vmx->nested.nested_vmx_pinbased_ctls_low |=
2568                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2569         vmx->nested.nested_vmx_pinbased_ctls_high &=
2570                 PIN_BASED_EXT_INTR_MASK |
2571                 PIN_BASED_NMI_EXITING |
2572                 PIN_BASED_VIRTUAL_NMIS;
2573         vmx->nested.nested_vmx_pinbased_ctls_high |=
2574                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2575                 PIN_BASED_VMX_PREEMPTION_TIMER;
2576         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2577                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2578                         PIN_BASED_POSTED_INTR;
2579
2580         /* exit controls */
2581         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2582                 vmx->nested.nested_vmx_exit_ctls_low,
2583                 vmx->nested.nested_vmx_exit_ctls_high);
2584         vmx->nested.nested_vmx_exit_ctls_low =
2585                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2586
2587         vmx->nested.nested_vmx_exit_ctls_high &=
2588 #ifdef CONFIG_X86_64
2589                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2590 #endif
2591                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2592         vmx->nested.nested_vmx_exit_ctls_high |=
2593                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2594                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2595                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2596
2597         if (kvm_mpx_supported())
2598                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2599
2600         /* We support free control of debug control saving. */
2601         vmx->nested.nested_vmx_true_exit_ctls_low =
2602                 vmx->nested.nested_vmx_exit_ctls_low &
2603                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2604
2605         /* entry controls */
2606         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2607                 vmx->nested.nested_vmx_entry_ctls_low,
2608                 vmx->nested.nested_vmx_entry_ctls_high);
2609         vmx->nested.nested_vmx_entry_ctls_low =
2610                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2611         vmx->nested.nested_vmx_entry_ctls_high &=
2612 #ifdef CONFIG_X86_64
2613                 VM_ENTRY_IA32E_MODE |
2614 #endif
2615                 VM_ENTRY_LOAD_IA32_PAT;
2616         vmx->nested.nested_vmx_entry_ctls_high |=
2617                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2618         if (kvm_mpx_supported())
2619                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2620
2621         /* We support free control of debug control loading. */
2622         vmx->nested.nested_vmx_true_entry_ctls_low =
2623                 vmx->nested.nested_vmx_entry_ctls_low &
2624                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2625
2626         /* cpu-based controls */
2627         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2628                 vmx->nested.nested_vmx_procbased_ctls_low,
2629                 vmx->nested.nested_vmx_procbased_ctls_high);
2630         vmx->nested.nested_vmx_procbased_ctls_low =
2631                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2632         vmx->nested.nested_vmx_procbased_ctls_high &=
2633                 CPU_BASED_VIRTUAL_INTR_PENDING |
2634                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2635                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2636                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2637                 CPU_BASED_CR3_STORE_EXITING |
2638 #ifdef CONFIG_X86_64
2639                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2640 #endif
2641                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2642                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2643                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2644                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2645                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2646         /*
2647          * We can allow some features even when not supported by the
2648          * hardware. For example, L1 can specify an MSR bitmap - and we
2649          * can use it to avoid exits to L1 - even when L0 runs L2
2650          * without MSR bitmaps.
2651          */
2652         vmx->nested.nested_vmx_procbased_ctls_high |=
2653                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2654                 CPU_BASED_USE_MSR_BITMAPS;
2655
2656         /* We support free control of CR3 access interception. */
2657         vmx->nested.nested_vmx_true_procbased_ctls_low =
2658                 vmx->nested.nested_vmx_procbased_ctls_low &
2659                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2660
2661         /* secondary cpu-based controls */
2662         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2663                 vmx->nested.nested_vmx_secondary_ctls_low,
2664                 vmx->nested.nested_vmx_secondary_ctls_high);
2665         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2666         vmx->nested.nested_vmx_secondary_ctls_high &=
2667                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2668                 SECONDARY_EXEC_RDTSCP |
2669                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2670                 SECONDARY_EXEC_ENABLE_VPID |
2671                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2672                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2673                 SECONDARY_EXEC_WBINVD_EXITING |
2674                 SECONDARY_EXEC_XSAVES |
2675                 SECONDARY_EXEC_PCOMMIT;
2676
2677         if (enable_ept) {
2678                 /* nested EPT: emulate EPT also to L1 */
2679                 vmx->nested.nested_vmx_secondary_ctls_high |=
2680                         SECONDARY_EXEC_ENABLE_EPT;
2681                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2682                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2683                          VMX_EPT_INVEPT_BIT;
2684                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2685                 /*
2686                  * For nested guests, we don't do anything specific
2687                  * for single context invalidation. Hence, only advertise
2688                  * support for global context invalidation.
2689                  */
2690                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2691         } else
2692                 vmx->nested.nested_vmx_ept_caps = 0;
2693
2694         if (enable_vpid)
2695                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2696                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2697         else
2698                 vmx->nested.nested_vmx_vpid_caps = 0;
2699
2700         if (enable_unrestricted_guest)
2701                 vmx->nested.nested_vmx_secondary_ctls_high |=
2702                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2703
2704         /* miscellaneous data */
2705         rdmsr(MSR_IA32_VMX_MISC,
2706                 vmx->nested.nested_vmx_misc_low,
2707                 vmx->nested.nested_vmx_misc_high);
2708         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2709         vmx->nested.nested_vmx_misc_low |=
2710                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2711                 VMX_MISC_ACTIVITY_HLT;
2712         vmx->nested.nested_vmx_misc_high = 0;
2713 }
2714
2715 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2716 {
2717         /*
2718          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2719          */
2720         return ((control & high) | low) == control;
2721 }
2722
2723 static inline u64 vmx_control_msr(u32 low, u32 high)
2724 {
2725         return low | ((u64)high << 32);
2726 }
2727
2728 /* Returns 0 on success, non-0 otherwise. */
2729 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2730 {
2731         struct vcpu_vmx *vmx = to_vmx(vcpu);
2732
2733         switch (msr_index) {
2734         case MSR_IA32_VMX_BASIC:
2735                 /*
2736                  * This MSR reports some information about VMX support. We
2737                  * should return information about the VMX we emulate for the
2738                  * guest, and the VMCS structure we give it - not about the
2739                  * VMX support of the underlying hardware.
2740                  */
2741                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2742                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2743                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2744                 break;
2745         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2746         case MSR_IA32_VMX_PINBASED_CTLS:
2747                 *pdata = vmx_control_msr(
2748                         vmx->nested.nested_vmx_pinbased_ctls_low,
2749                         vmx->nested.nested_vmx_pinbased_ctls_high);
2750                 break;
2751         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2752                 *pdata = vmx_control_msr(
2753                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2754                         vmx->nested.nested_vmx_procbased_ctls_high);
2755                 break;
2756         case MSR_IA32_VMX_PROCBASED_CTLS:
2757                 *pdata = vmx_control_msr(
2758                         vmx->nested.nested_vmx_procbased_ctls_low,
2759                         vmx->nested.nested_vmx_procbased_ctls_high);
2760                 break;
2761         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2762                 *pdata = vmx_control_msr(
2763                         vmx->nested.nested_vmx_true_exit_ctls_low,
2764                         vmx->nested.nested_vmx_exit_ctls_high);
2765                 break;
2766         case MSR_IA32_VMX_EXIT_CTLS:
2767                 *pdata = vmx_control_msr(
2768                         vmx->nested.nested_vmx_exit_ctls_low,
2769                         vmx->nested.nested_vmx_exit_ctls_high);
2770                 break;
2771         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2772                 *pdata = vmx_control_msr(
2773                         vmx->nested.nested_vmx_true_entry_ctls_low,
2774                         vmx->nested.nested_vmx_entry_ctls_high);
2775                 break;
2776         case MSR_IA32_VMX_ENTRY_CTLS:
2777                 *pdata = vmx_control_msr(
2778                         vmx->nested.nested_vmx_entry_ctls_low,
2779                         vmx->nested.nested_vmx_entry_ctls_high);
2780                 break;
2781         case MSR_IA32_VMX_MISC:
2782                 *pdata = vmx_control_msr(
2783                         vmx->nested.nested_vmx_misc_low,
2784                         vmx->nested.nested_vmx_misc_high);
2785                 break;
2786         /*
2787          * These MSRs specify bits which the guest must keep fixed (on or off)
2788          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2789          * We picked the standard core2 setting.
2790          */
2791 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2792 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2793         case MSR_IA32_VMX_CR0_FIXED0:
2794                 *pdata = VMXON_CR0_ALWAYSON;
2795                 break;
2796         case MSR_IA32_VMX_CR0_FIXED1:
2797                 *pdata = -1ULL;
2798                 break;
2799         case MSR_IA32_VMX_CR4_FIXED0:
2800                 *pdata = VMXON_CR4_ALWAYSON;
2801                 break;
2802         case MSR_IA32_VMX_CR4_FIXED1:
2803                 *pdata = -1ULL;
2804                 break;
2805         case MSR_IA32_VMX_VMCS_ENUM:
2806                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2807                 break;
2808         case MSR_IA32_VMX_PROCBASED_CTLS2:
2809                 *pdata = vmx_control_msr(
2810                         vmx->nested.nested_vmx_secondary_ctls_low,
2811                         vmx->nested.nested_vmx_secondary_ctls_high);
2812                 break;
2813         case MSR_IA32_VMX_EPT_VPID_CAP:
2814                 /* Currently, no nested vpid support */
2815                 *pdata = vmx->nested.nested_vmx_ept_caps |
2816                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2817                 break;
2818         default:
2819                 return 1;
2820         }
2821
2822         return 0;
2823 }
2824
2825 /*
2826  * Reads an msr value (of 'msr_index') into 'pdata'.
2827  * Returns 0 on success, non-0 otherwise.
2828  * Assumes vcpu_load() was already called.
2829  */
2830 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2831 {
2832         struct shared_msr_entry *msr;
2833
2834         switch (msr_info->index) {
2835 #ifdef CONFIG_X86_64
2836         case MSR_FS_BASE:
2837                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2838                 break;
2839         case MSR_GS_BASE:
2840                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2841                 break;
2842         case MSR_KERNEL_GS_BASE:
2843                 vmx_load_host_state(to_vmx(vcpu));
2844                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2845                 break;
2846 #endif
2847         case MSR_EFER:
2848                 return kvm_get_msr_common(vcpu, msr_info);
2849         case MSR_IA32_TSC:
2850                 msr_info->data = guest_read_tsc(vcpu);
2851                 break;
2852         case MSR_IA32_SYSENTER_CS:
2853                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2854                 break;
2855         case MSR_IA32_SYSENTER_EIP:
2856                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2857                 break;
2858         case MSR_IA32_SYSENTER_ESP:
2859                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2860                 break;
2861         case MSR_IA32_BNDCFGS:
2862                 if (!kvm_mpx_supported())
2863                         return 1;
2864                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2865                 break;
2866         case MSR_IA32_FEATURE_CONTROL:
2867                 if (!nested_vmx_allowed(vcpu))
2868                         return 1;
2869                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2870                 break;
2871         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2872                 if (!nested_vmx_allowed(vcpu))
2873                         return 1;
2874                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2875         case MSR_IA32_XSS:
2876                 if (!vmx_xsaves_supported())
2877                         return 1;
2878                 msr_info->data = vcpu->arch.ia32_xss;
2879                 break;
2880         case MSR_TSC_AUX:
2881                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2882                         return 1;
2883                 /* Otherwise falls through */
2884         default:
2885                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2886                 if (msr) {
2887                         msr_info->data = msr->data;
2888                         break;
2889                 }
2890                 return kvm_get_msr_common(vcpu, msr_info);
2891         }
2892
2893         return 0;
2894 }
2895
2896 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2897
2898 /*
2899  * Writes msr value into into the appropriate "register".
2900  * Returns 0 on success, non-0 otherwise.
2901  * Assumes vcpu_load() was already called.
2902  */
2903 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2904 {
2905         struct vcpu_vmx *vmx = to_vmx(vcpu);
2906         struct shared_msr_entry *msr;
2907         int ret = 0;
2908         u32 msr_index = msr_info->index;
2909         u64 data = msr_info->data;
2910
2911         switch (msr_index) {
2912         case MSR_EFER:
2913                 ret = kvm_set_msr_common(vcpu, msr_info);
2914                 break;
2915 #ifdef CONFIG_X86_64
2916         case MSR_FS_BASE:
2917                 vmx_segment_cache_clear(vmx);
2918                 vmcs_writel(GUEST_FS_BASE, data);
2919                 break;
2920         case MSR_GS_BASE:
2921                 vmx_segment_cache_clear(vmx);
2922                 vmcs_writel(GUEST_GS_BASE, data);
2923                 break;
2924         case MSR_KERNEL_GS_BASE:
2925                 vmx_load_host_state(vmx);
2926                 vmx->msr_guest_kernel_gs_base = data;
2927                 break;
2928 #endif
2929         case MSR_IA32_SYSENTER_CS:
2930                 vmcs_write32(GUEST_SYSENTER_CS, data);
2931                 break;
2932         case MSR_IA32_SYSENTER_EIP:
2933                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2934                 break;
2935         case MSR_IA32_SYSENTER_ESP:
2936                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2937                 break;
2938         case MSR_IA32_BNDCFGS:
2939                 if (!kvm_mpx_supported())
2940                         return 1;
2941                 vmcs_write64(GUEST_BNDCFGS, data);
2942                 break;
2943         case MSR_IA32_TSC:
2944                 kvm_write_tsc(vcpu, msr_info);
2945                 break;
2946         case MSR_IA32_CR_PAT:
2947                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2948                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2949                                 return 1;
2950                         vmcs_write64(GUEST_IA32_PAT, data);
2951                         vcpu->arch.pat = data;
2952                         break;
2953                 }
2954                 ret = kvm_set_msr_common(vcpu, msr_info);
2955                 break;
2956         case MSR_IA32_TSC_ADJUST:
2957                 ret = kvm_set_msr_common(vcpu, msr_info);
2958                 break;
2959         case MSR_IA32_FEATURE_CONTROL:
2960                 if (!nested_vmx_allowed(vcpu) ||
2961                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2962                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2963                         return 1;
2964                 vmx->nested.msr_ia32_feature_control = data;
2965                 if (msr_info->host_initiated && data == 0)
2966                         vmx_leave_nested(vcpu);
2967                 break;
2968         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2969                 return 1; /* they are read-only */
2970         case MSR_IA32_XSS:
2971                 if (!vmx_xsaves_supported())
2972                         return 1;
2973                 /*
2974                  * The only supported bit as of Skylake is bit 8, but
2975                  * it is not supported on KVM.
2976                  */
2977                 if (data != 0)
2978                         return 1;
2979                 vcpu->arch.ia32_xss = data;
2980                 if (vcpu->arch.ia32_xss != host_xss)
2981                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2982                                 vcpu->arch.ia32_xss, host_xss);
2983                 else
2984                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2985                 break;
2986         case MSR_TSC_AUX:
2987                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2988                         return 1;
2989                 /* Check reserved bit, higher 32 bits should be zero */
2990                 if ((data >> 32) != 0)
2991                         return 1;
2992                 /* Otherwise falls through */
2993         default:
2994                 msr = find_msr_entry(vmx, msr_index);
2995                 if (msr) {
2996                         u64 old_msr_data = msr->data;
2997                         msr->data = data;
2998                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2999                                 preempt_disable();
3000                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3001                                                          msr->mask);
3002                                 preempt_enable();
3003                                 if (ret)
3004                                         msr->data = old_msr_data;
3005                         }
3006                         break;
3007                 }
3008                 ret = kvm_set_msr_common(vcpu, msr_info);
3009         }
3010
3011         return ret;
3012 }
3013
3014 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3015 {
3016         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3017         switch (reg) {
3018         case VCPU_REGS_RSP:
3019                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3020                 break;
3021         case VCPU_REGS_RIP:
3022                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3023                 break;
3024         case VCPU_EXREG_PDPTR:
3025                 if (enable_ept)
3026                         ept_save_pdptrs(vcpu);
3027                 break;
3028         default:
3029                 break;
3030         }
3031 }
3032
3033 static __init int cpu_has_kvm_support(void)
3034 {
3035         return cpu_has_vmx();
3036 }
3037
3038 static __init int vmx_disabled_by_bios(void)
3039 {
3040         u64 msr;
3041
3042         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3043         if (msr & FEATURE_CONTROL_LOCKED) {
3044                 /* launched w/ TXT and VMX disabled */
3045                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3046                         && tboot_enabled())
3047                         return 1;
3048                 /* launched w/o TXT and VMX only enabled w/ TXT */
3049                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3050                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3051                         && !tboot_enabled()) {
3052                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3053                                 "activate TXT before enabling KVM\n");
3054                         return 1;
3055                 }
3056                 /* launched w/o TXT and VMX disabled */
3057                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3058                         && !tboot_enabled())
3059                         return 1;
3060         }
3061
3062         return 0;
3063 }
3064
3065 static void kvm_cpu_vmxon(u64 addr)
3066 {
3067         asm volatile (ASM_VMX_VMXON_RAX
3068                         : : "a"(&addr), "m"(addr)
3069                         : "memory", "cc");
3070 }
3071
3072 static int hardware_enable(void)
3073 {
3074         int cpu = raw_smp_processor_id();
3075         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3076         u64 old, test_bits;
3077
3078         if (cr4_read_shadow() & X86_CR4_VMXE)
3079                 return -EBUSY;
3080
3081         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3082         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3083         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3084
3085         /*
3086          * Now we can enable the vmclear operation in kdump
3087          * since the loaded_vmcss_on_cpu list on this cpu
3088          * has been initialized.
3089          *
3090          * Though the cpu is not in VMX operation now, there
3091          * is no problem to enable the vmclear operation
3092          * for the loaded_vmcss_on_cpu list is empty!
3093          */
3094         crash_enable_local_vmclear(cpu);
3095
3096         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3097
3098         test_bits = FEATURE_CONTROL_LOCKED;
3099         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3100         if (tboot_enabled())
3101                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3102
3103         if ((old & test_bits) != test_bits) {
3104                 /* enable and lock */
3105                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3106         }
3107         cr4_set_bits(X86_CR4_VMXE);
3108
3109         if (vmm_exclusive) {
3110                 kvm_cpu_vmxon(phys_addr);
3111                 ept_sync_global();
3112         }
3113
3114         native_store_gdt(this_cpu_ptr(&host_gdt));
3115
3116         return 0;
3117 }
3118
3119 static void vmclear_local_loaded_vmcss(void)
3120 {
3121         int cpu = raw_smp_processor_id();
3122         struct loaded_vmcs *v, *n;
3123
3124         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3125                                  loaded_vmcss_on_cpu_link)
3126                 __loaded_vmcs_clear(v);
3127 }
3128
3129
3130 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3131  * tricks.
3132  */
3133 static void kvm_cpu_vmxoff(void)
3134 {
3135         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3136 }
3137
3138 static void hardware_disable(void)
3139 {
3140         if (vmm_exclusive) {
3141                 vmclear_local_loaded_vmcss();
3142                 kvm_cpu_vmxoff();
3143         }
3144         cr4_clear_bits(X86_CR4_VMXE);
3145 }
3146
3147 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3148                                       u32 msr, u32 *result)
3149 {
3150         u32 vmx_msr_low, vmx_msr_high;
3151         u32 ctl = ctl_min | ctl_opt;
3152
3153         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3154
3155         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3156         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3157
3158         /* Ensure minimum (required) set of control bits are supported. */
3159         if (ctl_min & ~ctl)
3160                 return -EIO;
3161
3162         *result = ctl;
3163         return 0;
3164 }
3165
3166 static __init bool allow_1_setting(u32 msr, u32 ctl)
3167 {
3168         u32 vmx_msr_low, vmx_msr_high;
3169
3170         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3171         return vmx_msr_high & ctl;
3172 }
3173
3174 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3175 {
3176         u32 vmx_msr_low, vmx_msr_high;
3177         u32 min, opt, min2, opt2;
3178         u32 _pin_based_exec_control = 0;
3179         u32 _cpu_based_exec_control = 0;
3180         u32 _cpu_based_2nd_exec_control = 0;
3181         u32 _vmexit_control = 0;
3182         u32 _vmentry_control = 0;
3183
3184         min = CPU_BASED_HLT_EXITING |
3185 #ifdef CONFIG_X86_64
3186               CPU_BASED_CR8_LOAD_EXITING |
3187               CPU_BASED_CR8_STORE_EXITING |
3188 #endif
3189               CPU_BASED_CR3_LOAD_EXITING |
3190               CPU_BASED_CR3_STORE_EXITING |
3191               CPU_BASED_USE_IO_BITMAPS |
3192               CPU_BASED_MOV_DR_EXITING |
3193               CPU_BASED_USE_TSC_OFFSETING |
3194               CPU_BASED_MWAIT_EXITING |
3195               CPU_BASED_MONITOR_EXITING |
3196               CPU_BASED_INVLPG_EXITING |
3197               CPU_BASED_RDPMC_EXITING;
3198
3199         opt = CPU_BASED_TPR_SHADOW |
3200               CPU_BASED_USE_MSR_BITMAPS |
3201               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3202         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3203                                 &_cpu_based_exec_control) < 0)
3204                 return -EIO;
3205 #ifdef CONFIG_X86_64
3206         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3207                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3208                                            ~CPU_BASED_CR8_STORE_EXITING;
3209 #endif
3210         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3211                 min2 = 0;
3212                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3213                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3214                         SECONDARY_EXEC_WBINVD_EXITING |
3215                         SECONDARY_EXEC_ENABLE_VPID |
3216                         SECONDARY_EXEC_ENABLE_EPT |
3217                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3218                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3219                         SECONDARY_EXEC_RDTSCP |
3220                         SECONDARY_EXEC_ENABLE_INVPCID |
3221                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3222                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3223                         SECONDARY_EXEC_SHADOW_VMCS |
3224                         SECONDARY_EXEC_XSAVES |
3225                         SECONDARY_EXEC_ENABLE_PML |
3226                         SECONDARY_EXEC_PCOMMIT |
3227                         SECONDARY_EXEC_TSC_SCALING;
3228                 if (adjust_vmx_controls(min2, opt2,
3229                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3230                                         &_cpu_based_2nd_exec_control) < 0)
3231                         return -EIO;
3232         }
3233 #ifndef CONFIG_X86_64
3234         if (!(_cpu_based_2nd_exec_control &
3235                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3236                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3237 #endif
3238
3239         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3240                 _cpu_based_2nd_exec_control &= ~(
3241                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3242                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3243                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3244
3245         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3246                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3247                    enabled */
3248                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3249                                              CPU_BASED_CR3_STORE_EXITING |
3250                                              CPU_BASED_INVLPG_EXITING);
3251                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3252                       vmx_capability.ept, vmx_capability.vpid);
3253         }
3254
3255         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3256 #ifdef CONFIG_X86_64
3257         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3258 #endif
3259         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3260                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3261         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3262                                 &_vmexit_control) < 0)
3263                 return -EIO;
3264
3265         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3266         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3267         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3268                                 &_pin_based_exec_control) < 0)
3269                 return -EIO;
3270
3271         if (!(_cpu_based_2nd_exec_control &
3272                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3273                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3274                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3275
3276         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3277         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3278         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3279                                 &_vmentry_control) < 0)
3280                 return -EIO;
3281
3282         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3283
3284         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3285         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3286                 return -EIO;
3287
3288 #ifdef CONFIG_X86_64
3289         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3290         if (vmx_msr_high & (1u<<16))
3291                 return -EIO;
3292 #endif
3293
3294         /* Require Write-Back (WB) memory type for VMCS accesses. */
3295         if (((vmx_msr_high >> 18) & 15) != 6)
3296                 return -EIO;
3297
3298         vmcs_conf->size = vmx_msr_high & 0x1fff;
3299         vmcs_conf->order = get_order(vmcs_config.size);
3300         vmcs_conf->revision_id = vmx_msr_low;
3301
3302         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3303         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3304         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3305         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3306         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3307
3308         cpu_has_load_ia32_efer =
3309                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3310                                 VM_ENTRY_LOAD_IA32_EFER)
3311                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3312                                    VM_EXIT_LOAD_IA32_EFER);
3313
3314         cpu_has_load_perf_global_ctrl =
3315                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3316                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3317                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3318                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3319
3320         /*
3321          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3322          * but due to arrata below it can't be used. Workaround is to use
3323          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3324          *
3325          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3326          *
3327          * AAK155             (model 26)
3328          * AAP115             (model 30)
3329          * AAT100             (model 37)
3330          * BC86,AAY89,BD102   (model 44)
3331          * BA97               (model 46)
3332          *
3333          */
3334         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3335                 switch (boot_cpu_data.x86_model) {
3336                 case 26:
3337                 case 30:
3338                 case 37:
3339                 case 44:
3340                 case 46:
3341                         cpu_has_load_perf_global_ctrl = false;
3342                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3343                                         "does not work properly. Using workaround\n");
3344                         break;
3345                 default:
3346                         break;
3347                 }
3348         }
3349
3350         if (cpu_has_xsaves)
3351                 rdmsrl(MSR_IA32_XSS, host_xss);
3352
3353         return 0;
3354 }
3355
3356 static struct vmcs *alloc_vmcs_cpu(int cpu)
3357 {
3358         int node = cpu_to_node(cpu);
3359         struct page *pages;
3360         struct vmcs *vmcs;
3361
3362         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3363         if (!pages)
3364                 return NULL;
3365         vmcs = page_address(pages);
3366         memset(vmcs, 0, vmcs_config.size);
3367         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3368         return vmcs;
3369 }
3370
3371 static struct vmcs *alloc_vmcs(void)
3372 {
3373         return alloc_vmcs_cpu(raw_smp_processor_id());
3374 }
3375
3376 static void free_vmcs(struct vmcs *vmcs)
3377 {
3378         free_pages((unsigned long)vmcs, vmcs_config.order);
3379 }
3380
3381 /*
3382  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3383  */
3384 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3385 {
3386         if (!loaded_vmcs->vmcs)
3387                 return;
3388         loaded_vmcs_clear(loaded_vmcs);
3389         free_vmcs(loaded_vmcs->vmcs);
3390         loaded_vmcs->vmcs = NULL;
3391 }
3392
3393 static void free_kvm_area(void)
3394 {
3395         int cpu;
3396
3397         for_each_possible_cpu(cpu) {
3398                 free_vmcs(per_cpu(vmxarea, cpu));
3399                 per_cpu(vmxarea, cpu) = NULL;
3400         }
3401 }
3402
3403 static void init_vmcs_shadow_fields(void)
3404 {
3405         int i, j;
3406
3407         /* No checks for read only fields yet */
3408
3409         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3410                 switch (shadow_read_write_fields[i]) {
3411                 case GUEST_BNDCFGS:
3412                         if (!kvm_mpx_supported())
3413                                 continue;
3414                         break;
3415                 default:
3416                         break;
3417                 }
3418
3419                 if (j < i)
3420                         shadow_read_write_fields[j] =
3421                                 shadow_read_write_fields[i];
3422                 j++;
3423         }
3424         max_shadow_read_write_fields = j;
3425
3426         /* shadowed fields guest access without vmexit */
3427         for (i = 0; i < max_shadow_read_write_fields; i++) {
3428                 clear_bit(shadow_read_write_fields[i],
3429                           vmx_vmwrite_bitmap);
3430                 clear_bit(shadow_read_write_fields[i],
3431                           vmx_vmread_bitmap);
3432         }
3433         for (i = 0; i < max_shadow_read_only_fields; i++)
3434                 clear_bit(shadow_read_only_fields[i],
3435                           vmx_vmread_bitmap);
3436 }
3437
3438 static __init int alloc_kvm_area(void)
3439 {
3440         int cpu;
3441
3442         for_each_possible_cpu(cpu) {
3443                 struct vmcs *vmcs;
3444
3445                 vmcs = alloc_vmcs_cpu(cpu);
3446                 if (!vmcs) {
3447                         free_kvm_area();
3448                         return -ENOMEM;
3449                 }
3450
3451                 per_cpu(vmxarea, cpu) = vmcs;
3452         }
3453         return 0;
3454 }
3455
3456 static bool emulation_required(struct kvm_vcpu *vcpu)
3457 {
3458         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3459 }
3460
3461 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3462                 struct kvm_segment *save)
3463 {
3464         if (!emulate_invalid_guest_state) {
3465                 /*
3466                  * CS and SS RPL should be equal during guest entry according
3467                  * to VMX spec, but in reality it is not always so. Since vcpu
3468                  * is in the middle of the transition from real mode to
3469                  * protected mode it is safe to assume that RPL 0 is a good
3470                  * default value.
3471                  */
3472                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3473                         save->selector &= ~SEGMENT_RPL_MASK;
3474                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3475                 save->s = 1;
3476         }
3477         vmx_set_segment(vcpu, save, seg);
3478 }
3479
3480 static void enter_pmode(struct kvm_vcpu *vcpu)
3481 {
3482         unsigned long flags;
3483         struct vcpu_vmx *vmx = to_vmx(vcpu);
3484
3485         /*
3486          * Update real mode segment cache. It may be not up-to-date if sement
3487          * register was written while vcpu was in a guest mode.
3488          */
3489         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3490         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3491         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3492         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3493         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3494         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3495
3496         vmx->rmode.vm86_active = 0;
3497
3498         vmx_segment_cache_clear(vmx);
3499
3500         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3501
3502         flags = vmcs_readl(GUEST_RFLAGS);
3503         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3504         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3505         vmcs_writel(GUEST_RFLAGS, flags);
3506
3507         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3508                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3509
3510         update_exception_bitmap(vcpu);
3511
3512         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3513         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3514         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3515         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3516         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3517         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3518 }
3519
3520 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3521 {
3522         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3523         struct kvm_segment var = *save;
3524
3525         var.dpl = 0x3;
3526         if (seg == VCPU_SREG_CS)
3527                 var.type = 0x3;
3528
3529         if (!emulate_invalid_guest_state) {
3530                 var.selector = var.base >> 4;
3531                 var.base = var.base & 0xffff0;
3532                 var.limit = 0xffff;
3533                 var.g = 0;
3534                 var.db = 0;
3535                 var.present = 1;
3536                 var.s = 1;
3537                 var.l = 0;
3538                 var.unusable = 0;
3539                 var.type = 0x3;
3540                 var.avl = 0;
3541                 if (save->base & 0xf)
3542                         printk_once(KERN_WARNING "kvm: segment base is not "
3543                                         "paragraph aligned when entering "
3544                                         "protected mode (seg=%d)", seg);
3545         }
3546
3547         vmcs_write16(sf->selector, var.selector);
3548         vmcs_write32(sf->base, var.base);
3549         vmcs_write32(sf->limit, var.limit);
3550         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3551 }
3552
3553 static void enter_rmode(struct kvm_vcpu *vcpu)
3554 {
3555         unsigned long flags;
3556         struct vcpu_vmx *vmx = to_vmx(vcpu);
3557
3558         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3559         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3560         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3561         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3562         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3563         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3564         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3565
3566         vmx->rmode.vm86_active = 1;
3567
3568         /*
3569          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3570          * vcpu. Warn the user that an update is overdue.
3571          */
3572         if (!vcpu->kvm->arch.tss_addr)
3573                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3574                              "called before entering vcpu\n");
3575
3576         vmx_segment_cache_clear(vmx);
3577
3578         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3579         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3580         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3581
3582         flags = vmcs_readl(GUEST_RFLAGS);
3583         vmx->rmode.save_rflags = flags;
3584
3585         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3586
3587         vmcs_writel(GUEST_RFLAGS, flags);
3588         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3589         update_exception_bitmap(vcpu);
3590
3591         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3592         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3593         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3594         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3595         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3596         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3597
3598         kvm_mmu_reset_context(vcpu);
3599 }
3600
3601 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3602 {
3603         struct vcpu_vmx *vmx = to_vmx(vcpu);
3604         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3605
3606         if (!msr)
3607                 return;
3608
3609         /*
3610          * Force kernel_gs_base reloading before EFER changes, as control
3611          * of this msr depends on is_long_mode().
3612          */
3613         vmx_load_host_state(to_vmx(vcpu));
3614         vcpu->arch.efer = efer;
3615         if (efer & EFER_LMA) {
3616                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3617                 msr->data = efer;
3618         } else {
3619                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3620
3621                 msr->data = efer & ~EFER_LME;
3622         }
3623         setup_msrs(vmx);
3624 }
3625
3626 #ifdef CONFIG_X86_64
3627
3628 static void enter_lmode(struct kvm_vcpu *vcpu)
3629 {
3630         u32 guest_tr_ar;
3631
3632         vmx_segment_cache_clear(to_vmx(vcpu));
3633
3634         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3635         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3636                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3637                                      __func__);
3638                 vmcs_write32(GUEST_TR_AR_BYTES,
3639                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3640                              | VMX_AR_TYPE_BUSY_64_TSS);
3641         }
3642         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3643 }
3644
3645 static void exit_lmode(struct kvm_vcpu *vcpu)
3646 {
3647         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3648         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3649 }
3650
3651 #endif
3652
3653 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3654 {
3655         vpid_sync_context(vpid);
3656         if (enable_ept) {
3657                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3658                         return;
3659                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3660         }
3661 }
3662
3663 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3664 {
3665         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3666 }
3667
3668 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3669 {
3670         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3671
3672         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3673         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3674 }
3675
3676 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3677 {
3678         if (enable_ept && is_paging(vcpu))
3679                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3680         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3681 }
3682
3683 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3684 {
3685         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3686
3687         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3688         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3689 }
3690
3691 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3692 {
3693         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3694
3695         if (!test_bit(VCPU_EXREG_PDPTR,
3696                       (unsigned long *)&vcpu->arch.regs_dirty))
3697                 return;
3698
3699         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3700                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3701                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3702                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3703                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3704         }
3705 }
3706
3707 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3708 {
3709         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3710
3711         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3712                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3713                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3714                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3715                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3716         }
3717
3718         __set_bit(VCPU_EXREG_PDPTR,
3719                   (unsigned long *)&vcpu->arch.regs_avail);
3720         __set_bit(VCPU_EXREG_PDPTR,
3721                   (unsigned long *)&vcpu->arch.regs_dirty);
3722 }
3723
3724 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3725
3726 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3727                                         unsigned long cr0,
3728                                         struct kvm_vcpu *vcpu)
3729 {
3730         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3731                 vmx_decache_cr3(vcpu);
3732         if (!(cr0 & X86_CR0_PG)) {
3733                 /* From paging/starting to nonpaging */
3734                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3735                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3736                              (CPU_BASED_CR3_LOAD_EXITING |
3737                               CPU_BASED_CR3_STORE_EXITING));
3738                 vcpu->arch.cr0 = cr0;
3739                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3740         } else if (!is_paging(vcpu)) {
3741                 /* From nonpaging to paging */
3742                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3743                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3744                              ~(CPU_BASED_CR3_LOAD_EXITING |
3745                                CPU_BASED_CR3_STORE_EXITING));
3746                 vcpu->arch.cr0 = cr0;
3747                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3748         }
3749
3750         if (!(cr0 & X86_CR0_WP))
3751                 *hw_cr0 &= ~X86_CR0_WP;
3752 }
3753
3754 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3755 {
3756         struct vcpu_vmx *vmx = to_vmx(vcpu);
3757         unsigned long hw_cr0;
3758
3759         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3760         if (enable_unrestricted_guest)
3761                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3762         else {
3763                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3764
3765                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3766                         enter_pmode(vcpu);
3767
3768                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3769                         enter_rmode(vcpu);
3770         }
3771
3772 #ifdef CONFIG_X86_64
3773         if (vcpu->arch.efer & EFER_LME) {
3774                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3775                         enter_lmode(vcpu);
3776                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3777                         exit_lmode(vcpu);
3778         }
3779 #endif
3780
3781         if (enable_ept)
3782                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3783
3784         if (!vcpu->fpu_active)
3785                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3786
3787         vmcs_writel(CR0_READ_SHADOW, cr0);
3788         vmcs_writel(GUEST_CR0, hw_cr0);
3789         vcpu->arch.cr0 = cr0;
3790
3791         /* depends on vcpu->arch.cr0 to be set to a new value */
3792         vmx->emulation_required = emulation_required(vcpu);
3793 }
3794
3795 static u64 construct_eptp(unsigned long root_hpa)
3796 {
3797         u64 eptp;
3798
3799         /* TODO write the value reading from MSR */
3800         eptp = VMX_EPT_DEFAULT_MT |
3801                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3802         if (enable_ept_ad_bits)
3803                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3804         eptp |= (root_hpa & PAGE_MASK);
3805
3806         return eptp;
3807 }
3808
3809 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3810 {
3811         unsigned long guest_cr3;
3812         u64 eptp;
3813
3814         guest_cr3 = cr3;
3815         if (enable_ept) {
3816                 eptp = construct_eptp(cr3);
3817                 vmcs_write64(EPT_POINTER, eptp);
3818                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3819                         guest_cr3 = kvm_read_cr3(vcpu);
3820                 else
3821                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3822                 ept_load_pdptrs(vcpu);
3823         }
3824
3825         vmx_flush_tlb(vcpu);
3826         vmcs_writel(GUEST_CR3, guest_cr3);
3827 }
3828
3829 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3830 {
3831         /*
3832          * Pass through host's Machine Check Enable value to hw_cr4, which
3833          * is in force while we are in guest mode.  Do not let guests control
3834          * this bit, even if host CR4.MCE == 0.
3835          */
3836         unsigned long hw_cr4 =
3837                 (cr4_read_shadow() & X86_CR4_MCE) |
3838                 (cr4 & ~X86_CR4_MCE) |
3839                 (to_vmx(vcpu)->rmode.vm86_active ?
3840                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3841
3842         if (cr4 & X86_CR4_VMXE) {
3843                 /*
3844                  * To use VMXON (and later other VMX instructions), a guest
3845                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3846                  * So basically the check on whether to allow nested VMX
3847                  * is here.
3848                  */
3849                 if (!nested_vmx_allowed(vcpu))
3850                         return 1;
3851         }
3852         if (to_vmx(vcpu)->nested.vmxon &&
3853             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3854                 return 1;
3855
3856         vcpu->arch.cr4 = cr4;
3857         if (enable_ept) {
3858                 if (!is_paging(vcpu)) {
3859                         hw_cr4 &= ~X86_CR4_PAE;
3860                         hw_cr4 |= X86_CR4_PSE;
3861                 } else if (!(cr4 & X86_CR4_PAE)) {
3862                         hw_cr4 &= ~X86_CR4_PAE;
3863                 }
3864         }
3865
3866         if (!enable_unrestricted_guest && !is_paging(vcpu))
3867                 /*
3868                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3869                  * hardware.  However KVM always uses paging mode without
3870                  * unrestricted guest.
3871                  * To emulate this behavior, SMEP/SMAP needs to be manually
3872                  * disabled when guest switches to non-paging mode.
3873                  */
3874                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3875
3876         vmcs_writel(CR4_READ_SHADOW, cr4);
3877         vmcs_writel(GUEST_CR4, hw_cr4);
3878         return 0;
3879 }
3880
3881 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3882                             struct kvm_segment *var, int seg)
3883 {
3884         struct vcpu_vmx *vmx = to_vmx(vcpu);
3885         u32 ar;
3886
3887         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3888                 *var = vmx->rmode.segs[seg];
3889                 if (seg == VCPU_SREG_TR
3890                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3891                         return;
3892                 var->base = vmx_read_guest_seg_base(vmx, seg);
3893                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3894                 return;
3895         }
3896         var->base = vmx_read_guest_seg_base(vmx, seg);
3897         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3898         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3899         ar = vmx_read_guest_seg_ar(vmx, seg);
3900         var->unusable = (ar >> 16) & 1;
3901         var->type = ar & 15;
3902         var->s = (ar >> 4) & 1;
3903         var->dpl = (ar >> 5) & 3;
3904         /*
3905          * Some userspaces do not preserve unusable property. Since usable
3906          * segment has to be present according to VMX spec we can use present
3907          * property to amend userspace bug by making unusable segment always
3908          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3909          * segment as unusable.
3910          */
3911         var->present = !var->unusable;
3912         var->avl = (ar >> 12) & 1;
3913         var->l = (ar >> 13) & 1;
3914         var->db = (ar >> 14) & 1;
3915         var->g = (ar >> 15) & 1;
3916 }
3917
3918 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3919 {
3920         struct kvm_segment s;
3921
3922         if (to_vmx(vcpu)->rmode.vm86_active) {
3923                 vmx_get_segment(vcpu, &s, seg);
3924                 return s.base;
3925         }
3926         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3927 }
3928
3929 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3930 {
3931         struct vcpu_vmx *vmx = to_vmx(vcpu);
3932
3933         if (unlikely(vmx->rmode.vm86_active))
3934                 return 0;
3935         else {
3936                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3937                 return VMX_AR_DPL(ar);
3938         }
3939 }
3940
3941 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3942 {
3943         u32 ar;
3944
3945         if (var->unusable || !var->present)
3946                 ar = 1 << 16;
3947         else {
3948                 ar = var->type & 15;
3949                 ar |= (var->s & 1) << 4;
3950                 ar |= (var->dpl & 3) << 5;
3951                 ar |= (var->present & 1) << 7;
3952                 ar |= (var->avl & 1) << 12;
3953                 ar |= (var->l & 1) << 13;
3954                 ar |= (var->db & 1) << 14;
3955                 ar |= (var->g & 1) << 15;
3956         }
3957
3958         return ar;
3959 }
3960
3961 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3962                             struct kvm_segment *var, int seg)
3963 {
3964         struct vcpu_vmx *vmx = to_vmx(vcpu);
3965         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3966
3967         vmx_segment_cache_clear(vmx);
3968
3969         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3970                 vmx->rmode.segs[seg] = *var;
3971                 if (seg == VCPU_SREG_TR)
3972                         vmcs_write16(sf->selector, var->selector);
3973                 else if (var->s)
3974                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3975                 goto out;
3976         }
3977
3978         vmcs_writel(sf->base, var->base);
3979         vmcs_write32(sf->limit, var->limit);
3980         vmcs_write16(sf->selector, var->selector);
3981
3982         /*
3983          *   Fix the "Accessed" bit in AR field of segment registers for older
3984          * qemu binaries.
3985          *   IA32 arch specifies that at the time of processor reset the
3986          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3987          * is setting it to 0 in the userland code. This causes invalid guest
3988          * state vmexit when "unrestricted guest" mode is turned on.
3989          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3990          * tree. Newer qemu binaries with that qemu fix would not need this
3991          * kvm hack.
3992          */
3993         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3994                 var->type |= 0x1; /* Accessed */
3995
3996         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3997
3998 out:
3999         vmx->emulation_required = emulation_required(vcpu);
4000 }
4001
4002 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4003 {
4004         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4005
4006         *db = (ar >> 14) & 1;
4007         *l = (ar >> 13) & 1;
4008 }
4009
4010 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4011 {
4012         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4013         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4014 }
4015
4016 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4017 {
4018         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4019         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4020 }
4021
4022 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4023 {
4024         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4025         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4026 }
4027
4028 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4029 {
4030         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4031         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4032 }
4033
4034 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4035 {
4036         struct kvm_segment var;
4037         u32 ar;
4038
4039         vmx_get_segment(vcpu, &var, seg);
4040         var.dpl = 0x3;
4041         if (seg == VCPU_SREG_CS)
4042                 var.type = 0x3;
4043         ar = vmx_segment_access_rights(&var);
4044
4045         if (var.base != (var.selector << 4))
4046                 return false;
4047         if (var.limit != 0xffff)
4048                 return false;
4049         if (ar != 0xf3)
4050                 return false;
4051
4052         return true;
4053 }
4054
4055 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4056 {
4057         struct kvm_segment cs;
4058         unsigned int cs_rpl;
4059
4060         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4061         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4062
4063         if (cs.unusable)
4064                 return false;
4065         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4066                 return false;
4067         if (!cs.s)
4068                 return false;
4069         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4070                 if (cs.dpl > cs_rpl)
4071                         return false;
4072         } else {
4073                 if (cs.dpl != cs_rpl)
4074                         return false;
4075         }
4076         if (!cs.present)
4077                 return false;
4078
4079         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4080         return true;
4081 }
4082
4083 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4084 {
4085         struct kvm_segment ss;
4086         unsigned int ss_rpl;
4087
4088         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4089         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4090
4091         if (ss.unusable)
4092                 return true;
4093         if (ss.type != 3 && ss.type != 7)
4094                 return false;
4095         if (!ss.s)
4096                 return false;
4097         if (ss.dpl != ss_rpl) /* DPL != RPL */
4098                 return false;
4099         if (!ss.present)
4100                 return false;
4101
4102         return true;
4103 }
4104
4105 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4106 {
4107         struct kvm_segment var;
4108         unsigned int rpl;
4109
4110         vmx_get_segment(vcpu, &var, seg);
4111         rpl = var.selector & SEGMENT_RPL_MASK;
4112
4113         if (var.unusable)
4114                 return true;
4115         if (!var.s)
4116                 return false;
4117         if (!var.present)
4118                 return false;
4119         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4120                 if (var.dpl < rpl) /* DPL < RPL */
4121                         return false;
4122         }
4123
4124         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4125          * rights flags
4126          */
4127         return true;
4128 }
4129
4130 static bool tr_valid(struct kvm_vcpu *vcpu)
4131 {
4132         struct kvm_segment tr;
4133
4134         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4135
4136         if (tr.unusable)
4137                 return false;
4138         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4139                 return false;
4140         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4141                 return false;
4142         if (!tr.present)
4143                 return false;
4144
4145         return true;
4146 }
4147
4148 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4149 {
4150         struct kvm_segment ldtr;
4151
4152         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4153
4154         if (ldtr.unusable)
4155                 return true;
4156         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4157                 return false;
4158         if (ldtr.type != 2)
4159                 return false;
4160         if (!ldtr.present)
4161                 return false;
4162
4163         return true;
4164 }
4165
4166 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4167 {
4168         struct kvm_segment cs, ss;
4169
4170         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4171         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4172
4173         return ((cs.selector & SEGMENT_RPL_MASK) ==
4174                  (ss.selector & SEGMENT_RPL_MASK));
4175 }
4176
4177 /*
4178  * Check if guest state is valid. Returns true if valid, false if
4179  * not.
4180  * We assume that registers are always usable
4181  */
4182 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4183 {
4184         if (enable_unrestricted_guest)
4185                 return true;
4186
4187         /* real mode guest state checks */
4188         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4189                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4190                         return false;
4191                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4192                         return false;
4193                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4194                         return false;
4195                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4196                         return false;
4197                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4198                         return false;
4199                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4200                         return false;
4201         } else {
4202         /* protected mode guest state checks */
4203                 if (!cs_ss_rpl_check(vcpu))
4204                         return false;
4205                 if (!code_segment_valid(vcpu))
4206                         return false;
4207                 if (!stack_segment_valid(vcpu))
4208                         return false;
4209                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4210                         return false;
4211                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4212                         return false;
4213                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4214                         return false;
4215                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4216                         return false;
4217                 if (!tr_valid(vcpu))
4218                         return false;
4219                 if (!ldtr_valid(vcpu))
4220                         return false;
4221         }
4222         /* TODO:
4223          * - Add checks on RIP
4224          * - Add checks on RFLAGS
4225          */
4226
4227         return true;
4228 }
4229
4230 static int init_rmode_tss(struct kvm *kvm)
4231 {
4232         gfn_t fn;
4233         u16 data = 0;
4234         int idx, r;
4235
4236         idx = srcu_read_lock(&kvm->srcu);
4237         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4238         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4239         if (r < 0)
4240                 goto out;
4241         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4242         r = kvm_write_guest_page(kvm, fn++, &data,
4243                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4244         if (r < 0)
4245                 goto out;
4246         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4247         if (r < 0)
4248                 goto out;
4249         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4250         if (r < 0)
4251                 goto out;
4252         data = ~0;
4253         r = kvm_write_guest_page(kvm, fn, &data,
4254                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4255                                  sizeof(u8));
4256 out:
4257         srcu_read_unlock(&kvm->srcu, idx);
4258         return r;
4259 }
4260
4261 static int init_rmode_identity_map(struct kvm *kvm)
4262 {
4263         int i, idx, r = 0;
4264         kvm_pfn_t identity_map_pfn;
4265         u32 tmp;
4266
4267         if (!enable_ept)
4268                 return 0;
4269
4270         /* Protect kvm->arch.ept_identity_pagetable_done. */
4271         mutex_lock(&kvm->slots_lock);
4272
4273         if (likely(kvm->arch.ept_identity_pagetable_done))
4274                 goto out2;
4275
4276         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4277
4278         r = alloc_identity_pagetable(kvm);
4279         if (r < 0)
4280                 goto out2;
4281
4282         idx = srcu_read_lock(&kvm->srcu);
4283         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4284         if (r < 0)
4285                 goto out;
4286         /* Set up identity-mapping pagetable for EPT in real mode */
4287         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4288                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4289                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4290                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4291                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4292                 if (r < 0)
4293                         goto out;
4294         }
4295         kvm->arch.ept_identity_pagetable_done = true;
4296
4297 out:
4298         srcu_read_unlock(&kvm->srcu, idx);
4299
4300 out2:
4301         mutex_unlock(&kvm->slots_lock);
4302         return r;
4303 }
4304
4305 static void seg_setup(int seg)
4306 {
4307         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4308         unsigned int ar;
4309
4310         vmcs_write16(sf->selector, 0);
4311         vmcs_writel(sf->base, 0);
4312         vmcs_write32(sf->limit, 0xffff);
4313         ar = 0x93;
4314         if (seg == VCPU_SREG_CS)
4315                 ar |= 0x08; /* code segment */
4316
4317         vmcs_write32(sf->ar_bytes, ar);
4318 }
4319
4320 static int alloc_apic_access_page(struct kvm *kvm)
4321 {
4322         struct page *page;
4323         int r = 0;
4324
4325         mutex_lock(&kvm->slots_lock);
4326         if (kvm->arch.apic_access_page_done)
4327                 goto out;
4328         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4329                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4330         if (r)
4331                 goto out;
4332
4333         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4334         if (is_error_page(page)) {
4335                 r = -EFAULT;
4336                 goto out;
4337         }
4338
4339         /*
4340          * Do not pin the page in memory, so that memory hot-unplug
4341          * is able to migrate it.
4342          */
4343         put_page(page);
4344         kvm->arch.apic_access_page_done = true;
4345 out:
4346         mutex_unlock(&kvm->slots_lock);
4347         return r;
4348 }
4349
4350 static int alloc_identity_pagetable(struct kvm *kvm)
4351 {
4352         /* Called with kvm->slots_lock held. */
4353
4354         int r = 0;
4355
4356         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4357
4358         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4359                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4360
4361         return r;
4362 }
4363
4364 static int allocate_vpid(void)
4365 {
4366         int vpid;
4367
4368         if (!enable_vpid)
4369                 return 0;
4370         spin_lock(&vmx_vpid_lock);
4371         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4372         if (vpid < VMX_NR_VPIDS)
4373                 __set_bit(vpid, vmx_vpid_bitmap);
4374         else
4375                 vpid = 0;
4376         spin_unlock(&vmx_vpid_lock);
4377         return vpid;
4378 }
4379
4380 static void free_vpid(int vpid)
4381 {
4382         if (!enable_vpid || vpid == 0)
4383                 return;
4384         spin_lock(&vmx_vpid_lock);
4385         __clear_bit(vpid, vmx_vpid_bitmap);
4386         spin_unlock(&vmx_vpid_lock);
4387 }
4388
4389 #define MSR_TYPE_R      1
4390 #define MSR_TYPE_W      2
4391 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4392                                                 u32 msr, int type)
4393 {
4394         int f = sizeof(unsigned long);
4395
4396         if (!cpu_has_vmx_msr_bitmap())
4397                 return;
4398
4399         /*
4400          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4401          * have the write-low and read-high bitmap offsets the wrong way round.
4402          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4403          */
4404         if (msr <= 0x1fff) {
4405                 if (type & MSR_TYPE_R)
4406                         /* read-low */
4407                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4408
4409                 if (type & MSR_TYPE_W)
4410                         /* write-low */
4411                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4412
4413         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4414                 msr &= 0x1fff;
4415                 if (type & MSR_TYPE_R)
4416                         /* read-high */
4417                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4418
4419                 if (type & MSR_TYPE_W)
4420                         /* write-high */
4421                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4422
4423         }
4424 }
4425
4426 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4427                                                 u32 msr, int type)
4428 {
4429         int f = sizeof(unsigned long);
4430
4431         if (!cpu_has_vmx_msr_bitmap())
4432                 return;
4433
4434         /*
4435          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4436          * have the write-low and read-high bitmap offsets the wrong way round.
4437          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4438          */
4439         if (msr <= 0x1fff) {
4440                 if (type & MSR_TYPE_R)
4441                         /* read-low */
4442                         __set_bit(msr, msr_bitmap + 0x000 / f);
4443
4444                 if (type & MSR_TYPE_W)
4445                         /* write-low */
4446                         __set_bit(msr, msr_bitmap + 0x800 / f);
4447
4448         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4449                 msr &= 0x1fff;
4450                 if (type & MSR_TYPE_R)
4451                         /* read-high */
4452                         __set_bit(msr, msr_bitmap + 0x400 / f);
4453
4454                 if (type & MSR_TYPE_W)
4455                         /* write-high */
4456                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4457
4458         }
4459 }
4460
4461 /*
4462  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4463  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4464  */
4465 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4466                                                unsigned long *msr_bitmap_nested,
4467                                                u32 msr, int type)
4468 {
4469         int f = sizeof(unsigned long);
4470
4471         if (!cpu_has_vmx_msr_bitmap()) {
4472                 WARN_ON(1);
4473                 return;
4474         }
4475
4476         /*
4477          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4478          * have the write-low and read-high bitmap offsets the wrong way round.
4479          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4480          */
4481         if (msr <= 0x1fff) {
4482                 if (type & MSR_TYPE_R &&
4483                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4484                         /* read-low */
4485                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4486
4487                 if (type & MSR_TYPE_W &&
4488                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4489                         /* write-low */
4490                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4491
4492         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4493                 msr &= 0x1fff;
4494                 if (type & MSR_TYPE_R &&
4495                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4496                         /* read-high */
4497                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4498
4499                 if (type & MSR_TYPE_W &&
4500                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4501                         /* write-high */
4502                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4503
4504         }
4505 }
4506
4507 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4508 {
4509         if (!longmode_only)
4510                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4511                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4512         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4513                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4514 }
4515
4516 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4517 {
4518         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4519                         msr, MSR_TYPE_R);
4520         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4521                         msr, MSR_TYPE_R);
4522 }
4523
4524 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4525 {
4526         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4527                         msr, MSR_TYPE_R);
4528         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4529                         msr, MSR_TYPE_R);
4530 }
4531
4532 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4533 {
4534         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4535                         msr, MSR_TYPE_W);
4536         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4537                         msr, MSR_TYPE_W);
4538 }
4539
4540 static bool vmx_get_enable_apicv(void)
4541 {
4542         return enable_apicv;
4543 }
4544
4545 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4546 {
4547         struct vcpu_vmx *vmx = to_vmx(vcpu);
4548         int max_irr;
4549         void *vapic_page;
4550         u16 status;
4551
4552         if (vmx->nested.pi_desc &&
4553             vmx->nested.pi_pending) {
4554                 vmx->nested.pi_pending = false;
4555                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4556                         return 0;
4557
4558                 max_irr = find_last_bit(
4559                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4560
4561                 if (max_irr == 256)
4562                         return 0;
4563
4564                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4565                 if (!vapic_page) {
4566                         WARN_ON(1);
4567                         return -ENOMEM;
4568                 }
4569                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4570                 kunmap(vmx->nested.virtual_apic_page);
4571
4572                 status = vmcs_read16(GUEST_INTR_STATUS);
4573                 if ((u8)max_irr > ((u8)status & 0xff)) {
4574                         status &= ~0xff;
4575                         status |= (u8)max_irr;
4576                         vmcs_write16(GUEST_INTR_STATUS, status);
4577                 }
4578         }
4579         return 0;
4580 }
4581
4582 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4583 {
4584 #ifdef CONFIG_SMP
4585         if (vcpu->mode == IN_GUEST_MODE) {
4586                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4587
4588                 /*
4589                  * Currently, we don't support urgent interrupt,
4590                  * all interrupts are recognized as non-urgent
4591                  * interrupt, so we cannot post interrupts when
4592                  * 'SN' is set.
4593                  *
4594                  * If the vcpu is in guest mode, it means it is
4595                  * running instead of being scheduled out and
4596                  * waiting in the run queue, and that's the only
4597                  * case when 'SN' is set currently, warning if
4598                  * 'SN' is set.
4599                  */
4600                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4601
4602                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4603                                 POSTED_INTR_VECTOR);
4604                 return true;
4605         }
4606 #endif
4607         return false;
4608 }
4609
4610 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4611                                                 int vector)
4612 {
4613         struct vcpu_vmx *vmx = to_vmx(vcpu);
4614
4615         if (is_guest_mode(vcpu) &&
4616             vector == vmx->nested.posted_intr_nv) {
4617                 /* the PIR and ON have been set by L1. */
4618                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4619                 /*
4620                  * If a posted intr is not recognized by hardware,
4621                  * we will accomplish it in the next vmentry.
4622                  */
4623                 vmx->nested.pi_pending = true;
4624                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4625                 return 0;
4626         }
4627         return -1;
4628 }
4629 /*
4630  * Send interrupt to vcpu via posted interrupt way.
4631  * 1. If target vcpu is running(non-root mode), send posted interrupt
4632  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4633  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4634  * interrupt from PIR in next vmentry.
4635  */
4636 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4637 {
4638         struct vcpu_vmx *vmx = to_vmx(vcpu);
4639         int r;
4640
4641         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4642         if (!r)
4643                 return;
4644
4645         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4646                 return;
4647
4648         r = pi_test_and_set_on(&vmx->pi_desc);
4649         kvm_make_request(KVM_REQ_EVENT, vcpu);
4650         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4651                 kvm_vcpu_kick(vcpu);
4652 }
4653
4654 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4655 {
4656         struct vcpu_vmx *vmx = to_vmx(vcpu);
4657
4658         if (!pi_test_and_clear_on(&vmx->pi_desc))
4659                 return;
4660
4661         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4662 }
4663
4664 /*
4665  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4666  * will not change in the lifetime of the guest.
4667  * Note that host-state that does change is set elsewhere. E.g., host-state
4668  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4669  */
4670 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4671 {
4672         u32 low32, high32;
4673         unsigned long tmpl;
4674         struct desc_ptr dt;
4675         unsigned long cr4;
4676
4677         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4678         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4679
4680         /* Save the most likely value for this task's CR4 in the VMCS. */
4681         cr4 = cr4_read_shadow();
4682         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4683         vmx->host_state.vmcs_host_cr4 = cr4;
4684
4685         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4686 #ifdef CONFIG_X86_64
4687         /*
4688          * Load null selectors, so we can avoid reloading them in
4689          * __vmx_load_host_state(), in case userspace uses the null selectors
4690          * too (the expected case).
4691          */
4692         vmcs_write16(HOST_DS_SELECTOR, 0);
4693         vmcs_write16(HOST_ES_SELECTOR, 0);
4694 #else
4695         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4696         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4697 #endif
4698         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4699         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4700
4701         native_store_idt(&dt);
4702         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4703         vmx->host_idt_base = dt.address;
4704
4705         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4706
4707         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4708         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4709         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4710         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4711
4712         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4713                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4714                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4715         }
4716 }
4717
4718 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4719 {
4720         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4721         if (enable_ept)
4722                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4723         if (is_guest_mode(&vmx->vcpu))
4724                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4725                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4726         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4727 }
4728
4729 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4730 {
4731         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4732
4733         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4734                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4735         return pin_based_exec_ctrl;
4736 }
4737
4738 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4739 {
4740         struct vcpu_vmx *vmx = to_vmx(vcpu);
4741
4742         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4743 }
4744
4745 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4746 {
4747         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4748
4749         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4750                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4751
4752         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4753                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4754 #ifdef CONFIG_X86_64
4755                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4756                                 CPU_BASED_CR8_LOAD_EXITING;
4757 #endif
4758         }
4759         if (!enable_ept)
4760                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4761                                 CPU_BASED_CR3_LOAD_EXITING  |
4762                                 CPU_BASED_INVLPG_EXITING;
4763         return exec_control;
4764 }
4765
4766 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4767 {
4768         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4769         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4770                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4771         if (vmx->vpid == 0)
4772                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4773         if (!enable_ept) {
4774                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4775                 enable_unrestricted_guest = 0;
4776                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4777                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4778         }
4779         if (!enable_unrestricted_guest)
4780                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4781         if (!ple_gap)
4782                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4783         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4784                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4785                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4786         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4787         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4788            (handle_vmptrld).
4789            We can NOT enable shadow_vmcs here because we don't have yet
4790            a current VMCS12
4791         */
4792         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4793
4794         if (!enable_pml)
4795                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4796
4797         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4798         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4799
4800         return exec_control;
4801 }
4802
4803 static void ept_set_mmio_spte_mask(void)
4804 {
4805         /*
4806          * EPT Misconfigurations can be generated if the value of bits 2:0
4807          * of an EPT paging-structure entry is 110b (write/execute).
4808          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4809          * spte.
4810          */
4811         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4812 }
4813
4814 #define VMX_XSS_EXIT_BITMAP 0
4815 /*
4816  * Sets up the vmcs for emulated real mode.
4817  */
4818 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4819 {
4820 #ifdef CONFIG_X86_64
4821         unsigned long a;
4822 #endif
4823         int i;
4824
4825         /* I/O */
4826         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4827         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4828
4829         if (enable_shadow_vmcs) {
4830                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4831                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4832         }
4833         if (cpu_has_vmx_msr_bitmap())
4834                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4835
4836         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4837
4838         /* Control */
4839         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4840
4841         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4842
4843         if (cpu_has_secondary_exec_ctrls())
4844                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4845                                 vmx_secondary_exec_control(vmx));
4846
4847         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4848                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4849                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4850                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4851                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4852
4853                 vmcs_write16(GUEST_INTR_STATUS, 0);
4854
4855                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4856                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4857         }
4858
4859         if (ple_gap) {
4860                 vmcs_write32(PLE_GAP, ple_gap);
4861                 vmx->ple_window = ple_window;
4862                 vmx->ple_window_dirty = true;
4863         }
4864
4865         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4866         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4867         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4868
4869         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4870         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4871         vmx_set_constant_host_state(vmx);
4872 #ifdef CONFIG_X86_64
4873         rdmsrl(MSR_FS_BASE, a);
4874         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4875         rdmsrl(MSR_GS_BASE, a);
4876         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4877 #else
4878         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4879         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4880 #endif
4881
4882         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4883         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4884         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4885         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4886         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4887
4888         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4889                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4890
4891         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4892                 u32 index = vmx_msr_index[i];
4893                 u32 data_low, data_high;
4894                 int j = vmx->nmsrs;
4895
4896                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4897                         continue;
4898                 if (wrmsr_safe(index, data_low, data_high) < 0)
4899                         continue;
4900                 vmx->guest_msrs[j].index = i;
4901                 vmx->guest_msrs[j].data = 0;
4902                 vmx->guest_msrs[j].mask = -1ull;
4903                 ++vmx->nmsrs;
4904         }
4905
4906
4907         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4908
4909         /* 22.2.1, 20.8.1 */
4910         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4911
4912         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4913         set_cr4_guest_host_mask(vmx);
4914
4915         if (vmx_xsaves_supported())
4916                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4917
4918         return 0;
4919 }
4920
4921 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4922 {
4923         struct vcpu_vmx *vmx = to_vmx(vcpu);
4924         struct msr_data apic_base_msr;
4925         u64 cr0;
4926
4927         vmx->rmode.vm86_active = 0;
4928
4929         vmx->soft_vnmi_blocked = 0;
4930
4931         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4932         kvm_set_cr8(vcpu, 0);
4933
4934         if (!init_event) {
4935                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4936                                      MSR_IA32_APICBASE_ENABLE;
4937                 if (kvm_vcpu_is_reset_bsp(vcpu))
4938                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4939                 apic_base_msr.host_initiated = true;
4940                 kvm_set_apic_base(vcpu, &apic_base_msr);
4941         }
4942
4943         vmx_segment_cache_clear(vmx);
4944
4945         seg_setup(VCPU_SREG_CS);
4946         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4947         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4948
4949         seg_setup(VCPU_SREG_DS);
4950         seg_setup(VCPU_SREG_ES);
4951         seg_setup(VCPU_SREG_FS);
4952         seg_setup(VCPU_SREG_GS);
4953         seg_setup(VCPU_SREG_SS);
4954
4955         vmcs_write16(GUEST_TR_SELECTOR, 0);
4956         vmcs_writel(GUEST_TR_BASE, 0);
4957         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4958         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4959
4960         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4961         vmcs_writel(GUEST_LDTR_BASE, 0);
4962         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4963         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4964
4965         if (!init_event) {
4966                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4967                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4968                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4969                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4970         }
4971
4972         vmcs_writel(GUEST_RFLAGS, 0x02);
4973         kvm_rip_write(vcpu, 0xfff0);
4974
4975         vmcs_writel(GUEST_GDTR_BASE, 0);
4976         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4977
4978         vmcs_writel(GUEST_IDTR_BASE, 0);
4979         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4980
4981         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4982         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4983         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4984
4985         setup_msrs(vmx);
4986
4987         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4988
4989         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4990                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4991                 if (cpu_need_tpr_shadow(vcpu))
4992                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4993                                      __pa(vcpu->arch.apic->regs));
4994                 vmcs_write32(TPR_THRESHOLD, 0);
4995         }
4996
4997         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4998
4999         if (kvm_vcpu_apicv_active(vcpu))
5000                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5001
5002         if (vmx->vpid != 0)
5003                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5004
5005         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5006         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5007         vmx->vcpu.arch.cr0 = cr0;
5008         vmx_set_cr4(vcpu, 0);
5009         vmx_set_efer(vcpu, 0);
5010         vmx_fpu_activate(vcpu);
5011         update_exception_bitmap(vcpu);
5012
5013         vpid_sync_context(vmx->vpid);
5014 }
5015
5016 /*
5017  * In nested virtualization, check if L1 asked to exit on external interrupts.
5018  * For most existing hypervisors, this will always return true.
5019  */
5020 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5021 {
5022         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5023                 PIN_BASED_EXT_INTR_MASK;
5024 }
5025
5026 /*
5027  * In nested virtualization, check if L1 has set
5028  * VM_EXIT_ACK_INTR_ON_EXIT
5029  */
5030 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5031 {
5032         return get_vmcs12(vcpu)->vm_exit_controls &
5033                 VM_EXIT_ACK_INTR_ON_EXIT;
5034 }
5035
5036 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5037 {
5038         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5039                 PIN_BASED_NMI_EXITING;
5040 }
5041
5042 static void enable_irq_window(struct kvm_vcpu *vcpu)
5043 {
5044         u32 cpu_based_vm_exec_control;
5045
5046         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5047         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5048         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5049 }
5050
5051 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5052 {
5053         u32 cpu_based_vm_exec_control;
5054
5055         if (!cpu_has_virtual_nmis() ||
5056             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5057                 enable_irq_window(vcpu);
5058                 return;
5059         }
5060
5061         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5062         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5063         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5064 }
5065
5066 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5067 {
5068         struct vcpu_vmx *vmx = to_vmx(vcpu);
5069         uint32_t intr;
5070         int irq = vcpu->arch.interrupt.nr;
5071
5072         trace_kvm_inj_virq(irq);
5073
5074         ++vcpu->stat.irq_injections;
5075         if (vmx->rmode.vm86_active) {
5076                 int inc_eip = 0;
5077                 if (vcpu->arch.interrupt.soft)
5078                         inc_eip = vcpu->arch.event_exit_inst_len;
5079                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5080                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5081                 return;
5082         }
5083         intr = irq | INTR_INFO_VALID_MASK;
5084         if (vcpu->arch.interrupt.soft) {
5085                 intr |= INTR_TYPE_SOFT_INTR;
5086                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5087                              vmx->vcpu.arch.event_exit_inst_len);
5088         } else
5089                 intr |= INTR_TYPE_EXT_INTR;
5090         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5091 }
5092
5093 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5094 {
5095         struct vcpu_vmx *vmx = to_vmx(vcpu);
5096
5097         if (is_guest_mode(vcpu))
5098                 return;
5099
5100         if (!cpu_has_virtual_nmis()) {
5101                 /*
5102                  * Tracking the NMI-blocked state in software is built upon
5103                  * finding the next open IRQ window. This, in turn, depends on
5104                  * well-behaving guests: They have to keep IRQs disabled at
5105                  * least as long as the NMI handler runs. Otherwise we may
5106                  * cause NMI nesting, maybe breaking the guest. But as this is
5107                  * highly unlikely, we can live with the residual risk.
5108                  */
5109                 vmx->soft_vnmi_blocked = 1;
5110                 vmx->vnmi_blocked_time = 0;
5111         }
5112
5113         ++vcpu->stat.nmi_injections;
5114         vmx->nmi_known_unmasked = false;
5115         if (vmx->rmode.vm86_active) {
5116                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5117                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5118                 return;
5119         }
5120         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5121                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5122 }
5123
5124 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5125 {
5126         if (!cpu_has_virtual_nmis())
5127                 return to_vmx(vcpu)->soft_vnmi_blocked;
5128         if (to_vmx(vcpu)->nmi_known_unmasked)
5129                 return false;
5130         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5131 }
5132
5133 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5134 {
5135         struct vcpu_vmx *vmx = to_vmx(vcpu);
5136
5137         if (!cpu_has_virtual_nmis()) {
5138                 if (vmx->soft_vnmi_blocked != masked) {
5139                         vmx->soft_vnmi_blocked = masked;
5140                         vmx->vnmi_blocked_time = 0;
5141                 }
5142         } else {
5143                 vmx->nmi_known_unmasked = !masked;
5144                 if (masked)
5145                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5146                                       GUEST_INTR_STATE_NMI);
5147                 else
5148                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5149                                         GUEST_INTR_STATE_NMI);
5150         }
5151 }
5152
5153 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5154 {
5155         if (to_vmx(vcpu)->nested.nested_run_pending)
5156                 return 0;
5157
5158         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5159                 return 0;
5160
5161         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5162                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5163                    | GUEST_INTR_STATE_NMI));
5164 }
5165
5166 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5167 {
5168         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5169                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5170                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5171                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5172 }
5173
5174 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5175 {
5176         int ret;
5177
5178         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5179                                     PAGE_SIZE * 3);
5180         if (ret)
5181                 return ret;
5182         kvm->arch.tss_addr = addr;
5183         return init_rmode_tss(kvm);
5184 }
5185
5186 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5187 {
5188         switch (vec) {
5189         case BP_VECTOR:
5190                 /*
5191                  * Update instruction length as we may reinject the exception
5192                  * from user space while in guest debugging mode.
5193                  */
5194                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5195                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5196                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5197                         return false;
5198                 /* fall through */
5199         case DB_VECTOR:
5200                 if (vcpu->guest_debug &
5201                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5202                         return false;
5203                 /* fall through */
5204         case DE_VECTOR:
5205         case OF_VECTOR:
5206         case BR_VECTOR:
5207         case UD_VECTOR:
5208         case DF_VECTOR:
5209         case SS_VECTOR:
5210         case GP_VECTOR:
5211         case MF_VECTOR:
5212                 return true;
5213         break;
5214         }
5215         return false;
5216 }
5217
5218 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5219                                   int vec, u32 err_code)
5220 {
5221         /*
5222          * Instruction with address size override prefix opcode 0x67
5223          * Cause the #SS fault with 0 error code in VM86 mode.
5224          */
5225         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5226                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5227                         if (vcpu->arch.halt_request) {
5228                                 vcpu->arch.halt_request = 0;
5229                                 return kvm_vcpu_halt(vcpu);
5230                         }
5231                         return 1;
5232                 }
5233                 return 0;
5234         }
5235
5236         /*
5237          * Forward all other exceptions that are valid in real mode.
5238          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5239          *        the required debugging infrastructure rework.
5240          */
5241         kvm_queue_exception(vcpu, vec);
5242         return 1;
5243 }
5244
5245 /*
5246  * Trigger machine check on the host. We assume all the MSRs are already set up
5247  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5248  * We pass a fake environment to the machine check handler because we want
5249  * the guest to be always treated like user space, no matter what context
5250  * it used internally.
5251  */
5252 static void kvm_machine_check(void)
5253 {
5254 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5255         struct pt_regs regs = {
5256                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5257                 .flags = X86_EFLAGS_IF,
5258         };
5259
5260         do_machine_check(&regs, 0);
5261 #endif
5262 }
5263
5264 static int handle_machine_check(struct kvm_vcpu *vcpu)
5265 {
5266         /* already handled by vcpu_run */
5267         return 1;
5268 }
5269
5270 static int handle_exception(struct kvm_vcpu *vcpu)
5271 {
5272         struct vcpu_vmx *vmx = to_vmx(vcpu);
5273         struct kvm_run *kvm_run = vcpu->run;
5274         u32 intr_info, ex_no, error_code;
5275         unsigned long cr2, rip, dr6;
5276         u32 vect_info;
5277         enum emulation_result er;
5278
5279         vect_info = vmx->idt_vectoring_info;
5280         intr_info = vmx->exit_intr_info;
5281
5282         if (is_machine_check(intr_info))
5283                 return handle_machine_check(vcpu);
5284
5285         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5286                 return 1;  /* already handled by vmx_vcpu_run() */
5287
5288         if (is_no_device(intr_info)) {
5289                 vmx_fpu_activate(vcpu);
5290                 return 1;
5291         }
5292
5293         if (is_invalid_opcode(intr_info)) {
5294                 if (is_guest_mode(vcpu)) {
5295                         kvm_queue_exception(vcpu, UD_VECTOR);
5296                         return 1;
5297                 }
5298                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5299                 if (er != EMULATE_DONE)
5300                         kvm_queue_exception(vcpu, UD_VECTOR);
5301                 return 1;
5302         }
5303
5304         error_code = 0;
5305         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5306                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5307
5308         /*
5309          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5310          * MMIO, it is better to report an internal error.
5311          * See the comments in vmx_handle_exit.
5312          */
5313         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5314             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5315                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5316                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5317                 vcpu->run->internal.ndata = 3;
5318                 vcpu->run->internal.data[0] = vect_info;
5319                 vcpu->run->internal.data[1] = intr_info;
5320                 vcpu->run->internal.data[2] = error_code;
5321                 return 0;
5322         }
5323
5324         if (is_page_fault(intr_info)) {
5325                 /* EPT won't cause page fault directly */
5326                 BUG_ON(enable_ept);
5327                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5328                 trace_kvm_page_fault(cr2, error_code);
5329
5330                 if (kvm_event_needs_reinjection(vcpu))
5331                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5332                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5333         }
5334
5335         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5336
5337         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5338                 return handle_rmode_exception(vcpu, ex_no, error_code);
5339
5340         switch (ex_no) {
5341         case AC_VECTOR:
5342                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5343                 return 1;
5344         case DB_VECTOR:
5345                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5346                 if (!(vcpu->guest_debug &
5347                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5348                         vcpu->arch.dr6 &= ~15;
5349                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5350                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5351                                 skip_emulated_instruction(vcpu);
5352
5353                         kvm_queue_exception(vcpu, DB_VECTOR);
5354                         return 1;
5355                 }
5356                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5357                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5358                 /* fall through */
5359         case BP_VECTOR:
5360                 /*
5361                  * Update instruction length as we may reinject #BP from
5362                  * user space while in guest debugging mode. Reading it for
5363                  * #DB as well causes no harm, it is not used in that case.
5364                  */
5365                 vmx->vcpu.arch.event_exit_inst_len =
5366                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5367                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5368                 rip = kvm_rip_read(vcpu);
5369                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5370                 kvm_run->debug.arch.exception = ex_no;
5371                 break;
5372         default:
5373                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5374                 kvm_run->ex.exception = ex_no;
5375                 kvm_run->ex.error_code = error_code;
5376                 break;
5377         }
5378         return 0;
5379 }
5380
5381 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5382 {
5383         ++vcpu->stat.irq_exits;
5384         return 1;
5385 }
5386
5387 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5388 {
5389         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5390         return 0;
5391 }
5392
5393 static int handle_io(struct kvm_vcpu *vcpu)
5394 {
5395         unsigned long exit_qualification;
5396         int size, in, string;
5397         unsigned port;
5398
5399         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5400         string = (exit_qualification & 16) != 0;
5401         in = (exit_qualification & 8) != 0;
5402
5403         ++vcpu->stat.io_exits;
5404
5405         if (string || in)
5406                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5407
5408         port = exit_qualification >> 16;
5409         size = (exit_qualification & 7) + 1;
5410         skip_emulated_instruction(vcpu);
5411
5412         return kvm_fast_pio_out(vcpu, size, port);
5413 }
5414
5415 static void
5416 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5417 {
5418         /*
5419          * Patch in the VMCALL instruction:
5420          */
5421         hypercall[0] = 0x0f;
5422         hypercall[1] = 0x01;
5423         hypercall[2] = 0xc1;
5424 }
5425
5426 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5427 {
5428         unsigned long always_on = VMXON_CR0_ALWAYSON;
5429         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5430
5431         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5432                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5433             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5434                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5435         return (val & always_on) == always_on;
5436 }
5437
5438 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5439 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5440 {
5441         if (is_guest_mode(vcpu)) {
5442                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5443                 unsigned long orig_val = val;
5444
5445                 /*
5446                  * We get here when L2 changed cr0 in a way that did not change
5447                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5448                  * but did change L0 shadowed bits. So we first calculate the
5449                  * effective cr0 value that L1 would like to write into the
5450                  * hardware. It consists of the L2-owned bits from the new
5451                  * value combined with the L1-owned bits from L1's guest_cr0.
5452                  */
5453                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5454                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5455
5456                 if (!nested_cr0_valid(vcpu, val))
5457                         return 1;
5458
5459                 if (kvm_set_cr0(vcpu, val))
5460                         return 1;
5461                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5462                 return 0;
5463         } else {
5464                 if (to_vmx(vcpu)->nested.vmxon &&
5465                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5466                         return 1;
5467                 return kvm_set_cr0(vcpu, val);
5468         }
5469 }
5470
5471 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5472 {
5473         if (is_guest_mode(vcpu)) {
5474                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5475                 unsigned long orig_val = val;
5476
5477                 /* analogously to handle_set_cr0 */
5478                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5479                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5480                 if (kvm_set_cr4(vcpu, val))
5481                         return 1;
5482                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5483                 return 0;
5484         } else
5485                 return kvm_set_cr4(vcpu, val);
5486 }
5487
5488 /* called to set cr0 as approriate for clts instruction exit. */
5489 static void handle_clts(struct kvm_vcpu *vcpu)
5490 {
5491         if (is_guest_mode(vcpu)) {
5492                 /*
5493                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5494                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5495                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5496                  */
5497                 vmcs_writel(CR0_READ_SHADOW,
5498                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5499                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5500         } else
5501                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5502 }
5503
5504 static int handle_cr(struct kvm_vcpu *vcpu)
5505 {
5506         unsigned long exit_qualification, val;
5507         int cr;
5508         int reg;
5509         int err;
5510
5511         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5512         cr = exit_qualification & 15;
5513         reg = (exit_qualification >> 8) & 15;
5514         switch ((exit_qualification >> 4) & 3) {
5515         case 0: /* mov to cr */
5516                 val = kvm_register_readl(vcpu, reg);
5517                 trace_kvm_cr_write(cr, val);
5518                 switch (cr) {
5519                 case 0:
5520                         err = handle_set_cr0(vcpu, val);
5521                         kvm_complete_insn_gp(vcpu, err);
5522                         return 1;
5523                 case 3:
5524                         err = kvm_set_cr3(vcpu, val);
5525                         kvm_complete_insn_gp(vcpu, err);
5526                         return 1;
5527                 case 4:
5528                         err = handle_set_cr4(vcpu, val);
5529                         kvm_complete_insn_gp(vcpu, err);
5530                         return 1;
5531                 case 8: {
5532                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5533                                 u8 cr8 = (u8)val;
5534                                 err = kvm_set_cr8(vcpu, cr8);
5535                                 kvm_complete_insn_gp(vcpu, err);
5536                                 if (lapic_in_kernel(vcpu))
5537                                         return 1;
5538                                 if (cr8_prev <= cr8)
5539                                         return 1;
5540                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5541                                 return 0;
5542                         }
5543                 }
5544                 break;
5545         case 2: /* clts */
5546                 handle_clts(vcpu);
5547                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5548                 skip_emulated_instruction(vcpu);
5549                 vmx_fpu_activate(vcpu);
5550                 return 1;
5551         case 1: /*mov from cr*/
5552                 switch (cr) {
5553                 case 3:
5554                         val = kvm_read_cr3(vcpu);
5555                         kvm_register_write(vcpu, reg, val);
5556                         trace_kvm_cr_read(cr, val);
5557                         skip_emulated_instruction(vcpu);
5558                         return 1;
5559                 case 8:
5560                         val = kvm_get_cr8(vcpu);
5561                         kvm_register_write(vcpu, reg, val);
5562                         trace_kvm_cr_read(cr, val);
5563                         skip_emulated_instruction(vcpu);
5564                         return 1;
5565                 }
5566                 break;
5567         case 3: /* lmsw */
5568                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5569                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5570                 kvm_lmsw(vcpu, val);
5571
5572                 skip_emulated_instruction(vcpu);
5573                 return 1;
5574         default:
5575                 break;
5576         }
5577         vcpu->run->exit_reason = 0;
5578         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5579                (int)(exit_qualification >> 4) & 3, cr);
5580         return 0;
5581 }
5582
5583 static int handle_dr(struct kvm_vcpu *vcpu)
5584 {
5585         unsigned long exit_qualification;
5586         int dr, dr7, reg;
5587
5588         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5589         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5590
5591         /* First, if DR does not exist, trigger UD */
5592         if (!kvm_require_dr(vcpu, dr))
5593                 return 1;
5594
5595         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5596         if (!kvm_require_cpl(vcpu, 0))
5597                 return 1;
5598         dr7 = vmcs_readl(GUEST_DR7);
5599         if (dr7 & DR7_GD) {
5600                 /*
5601                  * As the vm-exit takes precedence over the debug trap, we
5602                  * need to emulate the latter, either for the host or the
5603                  * guest debugging itself.
5604                  */
5605                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5606                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5607                         vcpu->run->debug.arch.dr7 = dr7;
5608                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5609                         vcpu->run->debug.arch.exception = DB_VECTOR;
5610                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5611                         return 0;
5612                 } else {
5613                         vcpu->arch.dr6 &= ~15;
5614                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5615                         kvm_queue_exception(vcpu, DB_VECTOR);
5616                         return 1;
5617                 }
5618         }
5619
5620         if (vcpu->guest_debug == 0) {
5621                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5622                                 CPU_BASED_MOV_DR_EXITING);
5623
5624                 /*
5625                  * No more DR vmexits; force a reload of the debug registers
5626                  * and reenter on this instruction.  The next vmexit will
5627                  * retrieve the full state of the debug registers.
5628                  */
5629                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5630                 return 1;
5631         }
5632
5633         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5634         if (exit_qualification & TYPE_MOV_FROM_DR) {
5635                 unsigned long val;
5636
5637                 if (kvm_get_dr(vcpu, dr, &val))
5638                         return 1;
5639                 kvm_register_write(vcpu, reg, val);
5640         } else
5641                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5642                         return 1;
5643
5644         skip_emulated_instruction(vcpu);
5645         return 1;
5646 }
5647
5648 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5649 {
5650         return vcpu->arch.dr6;
5651 }
5652
5653 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5654 {
5655 }
5656
5657 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5658 {
5659         get_debugreg(vcpu->arch.db[0], 0);
5660         get_debugreg(vcpu->arch.db[1], 1);
5661         get_debugreg(vcpu->arch.db[2], 2);
5662         get_debugreg(vcpu->arch.db[3], 3);
5663         get_debugreg(vcpu->arch.dr6, 6);
5664         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5665
5666         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5667         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5668 }
5669
5670 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5671 {
5672         vmcs_writel(GUEST_DR7, val);
5673 }
5674
5675 static int handle_cpuid(struct kvm_vcpu *vcpu)
5676 {
5677         kvm_emulate_cpuid(vcpu);
5678         return 1;
5679 }
5680
5681 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5682 {
5683         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5684         struct msr_data msr_info;
5685
5686         msr_info.index = ecx;
5687         msr_info.host_initiated = false;
5688         if (vmx_get_msr(vcpu, &msr_info)) {
5689                 trace_kvm_msr_read_ex(ecx);
5690                 kvm_inject_gp(vcpu, 0);
5691                 return 1;
5692         }
5693
5694         trace_kvm_msr_read(ecx, msr_info.data);
5695
5696         /* FIXME: handling of bits 32:63 of rax, rdx */
5697         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5698         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5699         skip_emulated_instruction(vcpu);
5700         return 1;
5701 }
5702
5703 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5704 {
5705         struct msr_data msr;
5706         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5707         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5708                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5709
5710         msr.data = data;
5711         msr.index = ecx;
5712         msr.host_initiated = false;
5713         if (kvm_set_msr(vcpu, &msr) != 0) {
5714                 trace_kvm_msr_write_ex(ecx, data);
5715                 kvm_inject_gp(vcpu, 0);
5716                 return 1;
5717         }
5718
5719         trace_kvm_msr_write(ecx, data);
5720         skip_emulated_instruction(vcpu);
5721         return 1;
5722 }
5723
5724 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5725 {
5726         kvm_make_request(KVM_REQ_EVENT, vcpu);
5727         return 1;
5728 }
5729
5730 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5731 {
5732         u32 cpu_based_vm_exec_control;
5733
5734         /* clear pending irq */
5735         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5736         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5737         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5738
5739         kvm_make_request(KVM_REQ_EVENT, vcpu);
5740
5741         ++vcpu->stat.irq_window_exits;
5742         return 1;
5743 }
5744
5745 static int handle_halt(struct kvm_vcpu *vcpu)
5746 {
5747         return kvm_emulate_halt(vcpu);
5748 }
5749
5750 static int handle_vmcall(struct kvm_vcpu *vcpu)
5751 {
5752         return kvm_emulate_hypercall(vcpu);
5753 }
5754
5755 static int handle_invd(struct kvm_vcpu *vcpu)
5756 {
5757         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5758 }
5759
5760 static int handle_invlpg(struct kvm_vcpu *vcpu)
5761 {
5762         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5763
5764         kvm_mmu_invlpg(vcpu, exit_qualification);
5765         skip_emulated_instruction(vcpu);
5766         return 1;
5767 }
5768
5769 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5770 {
5771         int err;
5772
5773         err = kvm_rdpmc(vcpu);
5774         kvm_complete_insn_gp(vcpu, err);
5775
5776         return 1;
5777 }
5778
5779 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5780 {
5781         kvm_emulate_wbinvd(vcpu);
5782         return 1;
5783 }
5784
5785 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5786 {
5787         u64 new_bv = kvm_read_edx_eax(vcpu);
5788         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5789
5790         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5791                 skip_emulated_instruction(vcpu);
5792         return 1;
5793 }
5794
5795 static int handle_xsaves(struct kvm_vcpu *vcpu)
5796 {
5797         skip_emulated_instruction(vcpu);
5798         WARN(1, "this should never happen\n");
5799         return 1;
5800 }
5801
5802 static int handle_xrstors(struct kvm_vcpu *vcpu)
5803 {
5804         skip_emulated_instruction(vcpu);
5805         WARN(1, "this should never happen\n");
5806         return 1;
5807 }
5808
5809 static int handle_apic_access(struct kvm_vcpu *vcpu)
5810 {
5811         if (likely(fasteoi)) {
5812                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5813                 int access_type, offset;
5814
5815                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5816                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5817                 /*
5818                  * Sane guest uses MOV to write EOI, with written value
5819                  * not cared. So make a short-circuit here by avoiding
5820                  * heavy instruction emulation.
5821                  */
5822                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5823                     (offset == APIC_EOI)) {
5824                         kvm_lapic_set_eoi(vcpu);
5825                         skip_emulated_instruction(vcpu);
5826                         return 1;
5827                 }
5828         }
5829         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5830 }
5831
5832 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5833 {
5834         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5835         int vector = exit_qualification & 0xff;
5836
5837         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5838         kvm_apic_set_eoi_accelerated(vcpu, vector);
5839         return 1;
5840 }
5841
5842 static int handle_apic_write(struct kvm_vcpu *vcpu)
5843 {
5844         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5845         u32 offset = exit_qualification & 0xfff;
5846
5847         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5848         kvm_apic_write_nodecode(vcpu, offset);
5849         return 1;
5850 }
5851
5852 static int handle_task_switch(struct kvm_vcpu *vcpu)
5853 {
5854         struct vcpu_vmx *vmx = to_vmx(vcpu);
5855         unsigned long exit_qualification;
5856         bool has_error_code = false;
5857         u32 error_code = 0;
5858         u16 tss_selector;
5859         int reason, type, idt_v, idt_index;
5860
5861         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5862         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5863         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5864
5865         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5866
5867         reason = (u32)exit_qualification >> 30;
5868         if (reason == TASK_SWITCH_GATE && idt_v) {
5869                 switch (type) {
5870                 case INTR_TYPE_NMI_INTR:
5871                         vcpu->arch.nmi_injected = false;
5872                         vmx_set_nmi_mask(vcpu, true);
5873                         break;
5874                 case INTR_TYPE_EXT_INTR:
5875                 case INTR_TYPE_SOFT_INTR:
5876                         kvm_clear_interrupt_queue(vcpu);
5877                         break;
5878                 case INTR_TYPE_HARD_EXCEPTION:
5879                         if (vmx->idt_vectoring_info &
5880                             VECTORING_INFO_DELIVER_CODE_MASK) {
5881                                 has_error_code = true;
5882                                 error_code =
5883                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5884                         }
5885                         /* fall through */
5886                 case INTR_TYPE_SOFT_EXCEPTION:
5887                         kvm_clear_exception_queue(vcpu);
5888                         break;
5889                 default:
5890                         break;
5891                 }
5892         }
5893         tss_selector = exit_qualification;
5894
5895         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5896                        type != INTR_TYPE_EXT_INTR &&
5897                        type != INTR_TYPE_NMI_INTR))
5898                 skip_emulated_instruction(vcpu);
5899
5900         if (kvm_task_switch(vcpu, tss_selector,
5901                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5902                             has_error_code, error_code) == EMULATE_FAIL) {
5903                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5904                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5905                 vcpu->run->internal.ndata = 0;
5906                 return 0;
5907         }
5908
5909         /*
5910          * TODO: What about debug traps on tss switch?
5911          *       Are we supposed to inject them and update dr6?
5912          */
5913
5914         return 1;
5915 }
5916
5917 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5918 {
5919         unsigned long exit_qualification;
5920         gpa_t gpa;
5921         u32 error_code;
5922         int gla_validity;
5923
5924         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5925
5926         gla_validity = (exit_qualification >> 7) & 0x3;
5927         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5928                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5929                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5930                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5931                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5932                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5933                         (long unsigned int)exit_qualification);
5934                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5935                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5936                 return 0;
5937         }
5938
5939         /*
5940          * EPT violation happened while executing iret from NMI,
5941          * "blocked by NMI" bit has to be set before next VM entry.
5942          * There are errata that may cause this bit to not be set:
5943          * AAK134, BY25.
5944          */
5945         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5946                         cpu_has_virtual_nmis() &&
5947                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5948                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5949
5950         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5951         trace_kvm_page_fault(gpa, exit_qualification);
5952
5953         /* It is a write fault? */
5954         error_code = exit_qualification & PFERR_WRITE_MASK;
5955         /* It is a fetch fault? */
5956         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5957         /* ept page table is present? */
5958         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5959
5960         vcpu->arch.exit_qualification = exit_qualification;
5961
5962         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5963 }
5964
5965 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5966 {
5967         int ret;
5968         gpa_t gpa;
5969
5970         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5971         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5972                 skip_emulated_instruction(vcpu);
5973                 trace_kvm_fast_mmio(gpa);
5974                 return 1;
5975         }
5976
5977         ret = handle_mmio_page_fault(vcpu, gpa, true);
5978         if (likely(ret == RET_MMIO_PF_EMULATE))
5979                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5980                                               EMULATE_DONE;
5981
5982         if (unlikely(ret == RET_MMIO_PF_INVALID))
5983                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5984
5985         if (unlikely(ret == RET_MMIO_PF_RETRY))
5986                 return 1;
5987
5988         /* It is the real ept misconfig */
5989         WARN_ON(1);
5990
5991         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5992         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5993
5994         return 0;
5995 }
5996
5997 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5998 {
5999         u32 cpu_based_vm_exec_control;
6000
6001         /* clear pending NMI */
6002         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6003         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6004         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6005         ++vcpu->stat.nmi_window_exits;
6006         kvm_make_request(KVM_REQ_EVENT, vcpu);
6007
6008         return 1;
6009 }
6010
6011 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6012 {
6013         struct vcpu_vmx *vmx = to_vmx(vcpu);
6014         enum emulation_result err = EMULATE_DONE;
6015         int ret = 1;
6016         u32 cpu_exec_ctrl;
6017         bool intr_window_requested;
6018         unsigned count = 130;
6019
6020         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6021         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6022
6023         while (vmx->emulation_required && count-- != 0) {
6024                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6025                         return handle_interrupt_window(&vmx->vcpu);
6026
6027                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6028                         return 1;
6029
6030                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6031
6032                 if (err == EMULATE_USER_EXIT) {
6033                         ++vcpu->stat.mmio_exits;
6034                         ret = 0;
6035                         goto out;
6036                 }
6037
6038                 if (err != EMULATE_DONE) {
6039                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6040                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6041                         vcpu->run->internal.ndata = 0;
6042                         return 0;
6043                 }
6044
6045                 if (vcpu->arch.halt_request) {
6046                         vcpu->arch.halt_request = 0;
6047                         ret = kvm_vcpu_halt(vcpu);
6048                         goto out;
6049                 }
6050
6051                 if (signal_pending(current))
6052                         goto out;
6053                 if (need_resched())
6054                         schedule();
6055         }
6056
6057 out:
6058         return ret;
6059 }
6060
6061 static int __grow_ple_window(int val)
6062 {
6063         if (ple_window_grow < 1)
6064                 return ple_window;
6065
6066         val = min(val, ple_window_actual_max);
6067
6068         if (ple_window_grow < ple_window)
6069                 val *= ple_window_grow;
6070         else
6071                 val += ple_window_grow;
6072
6073         return val;
6074 }
6075
6076 static int __shrink_ple_window(int val, int modifier, int minimum)
6077 {
6078         if (modifier < 1)
6079                 return ple_window;
6080
6081         if (modifier < ple_window)
6082                 val /= modifier;
6083         else
6084                 val -= modifier;
6085
6086         return max(val, minimum);
6087 }
6088
6089 static void grow_ple_window(struct kvm_vcpu *vcpu)
6090 {
6091         struct vcpu_vmx *vmx = to_vmx(vcpu);
6092         int old = vmx->ple_window;
6093
6094         vmx->ple_window = __grow_ple_window(old);
6095
6096         if (vmx->ple_window != old)
6097                 vmx->ple_window_dirty = true;
6098
6099         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6100 }
6101
6102 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6103 {
6104         struct vcpu_vmx *vmx = to_vmx(vcpu);
6105         int old = vmx->ple_window;
6106
6107         vmx->ple_window = __shrink_ple_window(old,
6108                                               ple_window_shrink, ple_window);
6109
6110         if (vmx->ple_window != old)
6111                 vmx->ple_window_dirty = true;
6112
6113         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6114 }
6115
6116 /*
6117  * ple_window_actual_max is computed to be one grow_ple_window() below
6118  * ple_window_max. (See __grow_ple_window for the reason.)
6119  * This prevents overflows, because ple_window_max is int.
6120  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6121  * this process.
6122  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6123  */
6124 static void update_ple_window_actual_max(void)
6125 {
6126         ple_window_actual_max =
6127                         __shrink_ple_window(max(ple_window_max, ple_window),
6128                                             ple_window_grow, INT_MIN);
6129 }
6130
6131 /*
6132  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6133  */
6134 static void wakeup_handler(void)
6135 {
6136         struct kvm_vcpu *vcpu;
6137         int cpu = smp_processor_id();
6138
6139         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6140         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6141                         blocked_vcpu_list) {
6142                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6143
6144                 if (pi_test_on(pi_desc) == 1)
6145                         kvm_vcpu_kick(vcpu);
6146         }
6147         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6148 }
6149
6150 static __init int hardware_setup(void)
6151 {
6152         int r = -ENOMEM, i, msr;
6153
6154         rdmsrl_safe(MSR_EFER, &host_efer);
6155
6156         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6157                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6158
6159         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6160         if (!vmx_io_bitmap_a)
6161                 return r;
6162
6163         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6164         if (!vmx_io_bitmap_b)
6165                 goto out;
6166
6167         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6168         if (!vmx_msr_bitmap_legacy)
6169                 goto out1;
6170
6171         vmx_msr_bitmap_legacy_x2apic =
6172                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6173         if (!vmx_msr_bitmap_legacy_x2apic)
6174                 goto out2;
6175
6176         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6177         if (!vmx_msr_bitmap_longmode)
6178                 goto out3;
6179
6180         vmx_msr_bitmap_longmode_x2apic =
6181                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6182         if (!vmx_msr_bitmap_longmode_x2apic)
6183                 goto out4;
6184
6185         if (nested) {
6186                 vmx_msr_bitmap_nested =
6187                         (unsigned long *)__get_free_page(GFP_KERNEL);
6188                 if (!vmx_msr_bitmap_nested)
6189                         goto out5;
6190         }
6191
6192         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6193         if (!vmx_vmread_bitmap)
6194                 goto out6;
6195
6196         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6197         if (!vmx_vmwrite_bitmap)
6198                 goto out7;
6199
6200         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6201         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6202
6203         /*
6204          * Allow direct access to the PC debug port (it is often used for I/O
6205          * delays, but the vmexits simply slow things down).
6206          */
6207         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6208         clear_bit(0x80, vmx_io_bitmap_a);
6209
6210         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6211
6212         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6213         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6214         if (nested)
6215                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6216
6217         if (setup_vmcs_config(&vmcs_config) < 0) {
6218                 r = -EIO;
6219                 goto out8;
6220         }
6221
6222         if (boot_cpu_has(X86_FEATURE_NX))
6223                 kvm_enable_efer_bits(EFER_NX);
6224
6225         if (!cpu_has_vmx_vpid())
6226                 enable_vpid = 0;
6227         if (!cpu_has_vmx_shadow_vmcs())
6228                 enable_shadow_vmcs = 0;
6229         if (enable_shadow_vmcs)
6230                 init_vmcs_shadow_fields();
6231
6232         if (!cpu_has_vmx_ept() ||
6233             !cpu_has_vmx_ept_4levels()) {
6234                 enable_ept = 0;
6235                 enable_unrestricted_guest = 0;
6236                 enable_ept_ad_bits = 0;
6237         }
6238
6239         if (!cpu_has_vmx_ept_ad_bits())
6240                 enable_ept_ad_bits = 0;
6241
6242         if (!cpu_has_vmx_unrestricted_guest())
6243                 enable_unrestricted_guest = 0;
6244
6245         if (!cpu_has_vmx_flexpriority())
6246                 flexpriority_enabled = 0;
6247
6248         /*
6249          * set_apic_access_page_addr() is used to reload apic access
6250          * page upon invalidation.  No need to do anything if not
6251          * using the APIC_ACCESS_ADDR VMCS field.
6252          */
6253         if (!flexpriority_enabled)
6254                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6255
6256         if (!cpu_has_vmx_tpr_shadow())
6257                 kvm_x86_ops->update_cr8_intercept = NULL;
6258
6259         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6260                 kvm_disable_largepages();
6261
6262         if (!cpu_has_vmx_ple())
6263                 ple_gap = 0;
6264
6265         if (!cpu_has_vmx_apicv())
6266                 enable_apicv = 0;
6267
6268         if (cpu_has_vmx_tsc_scaling()) {
6269                 kvm_has_tsc_control = true;
6270                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6271                 kvm_tsc_scaling_ratio_frac_bits = 48;
6272         }
6273
6274         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6275         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6276         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6277         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6278         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6279         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6280         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6281
6282         memcpy(vmx_msr_bitmap_legacy_x2apic,
6283                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6284         memcpy(vmx_msr_bitmap_longmode_x2apic,
6285                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6286
6287         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6288
6289         if (enable_apicv) {
6290                 for (msr = 0x800; msr <= 0x8ff; msr++)
6291                         vmx_disable_intercept_msr_read_x2apic(msr);
6292
6293                 /* According SDM, in x2apic mode, the whole id reg is used.
6294                  * But in KVM, it only use the highest eight bits. Need to
6295                  * intercept it */
6296                 vmx_enable_intercept_msr_read_x2apic(0x802);
6297                 /* TMCCT */
6298                 vmx_enable_intercept_msr_read_x2apic(0x839);
6299                 /* TPR */
6300                 vmx_disable_intercept_msr_write_x2apic(0x808);
6301                 /* EOI */
6302                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6303                 /* SELF-IPI */
6304                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6305         }
6306
6307         if (enable_ept) {
6308                 kvm_mmu_set_mask_ptes(0ull,
6309                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6310                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6311                         0ull, VMX_EPT_EXECUTABLE_MASK);
6312                 ept_set_mmio_spte_mask();
6313                 kvm_enable_tdp();
6314         } else
6315                 kvm_disable_tdp();
6316
6317         update_ple_window_actual_max();
6318
6319         /*
6320          * Only enable PML when hardware supports PML feature, and both EPT
6321          * and EPT A/D bit features are enabled -- PML depends on them to work.
6322          */
6323         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6324                 enable_pml = 0;
6325
6326         if (!enable_pml) {
6327                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6328                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6329                 kvm_x86_ops->flush_log_dirty = NULL;
6330                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6331         }
6332
6333         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6334
6335         return alloc_kvm_area();
6336
6337 out8:
6338         free_page((unsigned long)vmx_vmwrite_bitmap);
6339 out7:
6340         free_page((unsigned long)vmx_vmread_bitmap);
6341 out6:
6342         if (nested)
6343                 free_page((unsigned long)vmx_msr_bitmap_nested);
6344 out5:
6345         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6346 out4:
6347         free_page((unsigned long)vmx_msr_bitmap_longmode);
6348 out3:
6349         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6350 out2:
6351         free_page((unsigned long)vmx_msr_bitmap_legacy);
6352 out1:
6353         free_page((unsigned long)vmx_io_bitmap_b);
6354 out:
6355         free_page((unsigned long)vmx_io_bitmap_a);
6356
6357     return r;
6358 }
6359
6360 static __exit void hardware_unsetup(void)
6361 {
6362         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6363         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6364         free_page((unsigned long)vmx_msr_bitmap_legacy);
6365         free_page((unsigned long)vmx_msr_bitmap_longmode);
6366         free_page((unsigned long)vmx_io_bitmap_b);
6367         free_page((unsigned long)vmx_io_bitmap_a);
6368         free_page((unsigned long)vmx_vmwrite_bitmap);
6369         free_page((unsigned long)vmx_vmread_bitmap);
6370         if (nested)
6371                 free_page((unsigned long)vmx_msr_bitmap_nested);
6372
6373         free_kvm_area();
6374 }
6375
6376 /*
6377  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6378  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6379  */
6380 static int handle_pause(struct kvm_vcpu *vcpu)
6381 {
6382         if (ple_gap)
6383                 grow_ple_window(vcpu);
6384
6385         skip_emulated_instruction(vcpu);
6386         kvm_vcpu_on_spin(vcpu);
6387
6388         return 1;
6389 }
6390
6391 static int handle_nop(struct kvm_vcpu *vcpu)
6392 {
6393         skip_emulated_instruction(vcpu);
6394         return 1;
6395 }
6396
6397 static int handle_mwait(struct kvm_vcpu *vcpu)
6398 {
6399         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6400         return handle_nop(vcpu);
6401 }
6402
6403 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6404 {
6405         return 1;
6406 }
6407
6408 static int handle_monitor(struct kvm_vcpu *vcpu)
6409 {
6410         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6411         return handle_nop(vcpu);
6412 }
6413
6414 /*
6415  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6416  * We could reuse a single VMCS for all the L2 guests, but we also want the
6417  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6418  * allows keeping them loaded on the processor, and in the future will allow
6419  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6420  * every entry if they never change.
6421  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6422  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6423  *
6424  * The following functions allocate and free a vmcs02 in this pool.
6425  */
6426
6427 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6428 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6429 {
6430         struct vmcs02_list *item;
6431         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6432                 if (item->vmptr == vmx->nested.current_vmptr) {
6433                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6434                         return &item->vmcs02;
6435                 }
6436
6437         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6438                 /* Recycle the least recently used VMCS. */
6439                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6440                                        struct vmcs02_list, list);
6441                 item->vmptr = vmx->nested.current_vmptr;
6442                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6443                 return &item->vmcs02;
6444         }
6445
6446         /* Create a new VMCS */
6447         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6448         if (!item)
6449                 return NULL;
6450         item->vmcs02.vmcs = alloc_vmcs();
6451         if (!item->vmcs02.vmcs) {
6452                 kfree(item);
6453                 return NULL;
6454         }
6455         loaded_vmcs_init(&item->vmcs02);
6456         item->vmptr = vmx->nested.current_vmptr;
6457         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6458         vmx->nested.vmcs02_num++;
6459         return &item->vmcs02;
6460 }
6461
6462 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6463 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6464 {
6465         struct vmcs02_list *item;
6466         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6467                 if (item->vmptr == vmptr) {
6468                         free_loaded_vmcs(&item->vmcs02);
6469                         list_del(&item->list);
6470                         kfree(item);
6471                         vmx->nested.vmcs02_num--;
6472                         return;
6473                 }
6474 }
6475
6476 /*
6477  * Free all VMCSs saved for this vcpu, except the one pointed by
6478  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6479  * must be &vmx->vmcs01.
6480  */
6481 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6482 {
6483         struct vmcs02_list *item, *n;
6484
6485         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6486         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6487                 /*
6488                  * Something will leak if the above WARN triggers.  Better than
6489                  * a use-after-free.
6490                  */
6491                 if (vmx->loaded_vmcs == &item->vmcs02)
6492                         continue;
6493
6494                 free_loaded_vmcs(&item->vmcs02);
6495                 list_del(&item->list);
6496                 kfree(item);
6497                 vmx->nested.vmcs02_num--;
6498         }
6499 }
6500
6501 /*
6502  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6503  * set the success or error code of an emulated VMX instruction, as specified
6504  * by Vol 2B, VMX Instruction Reference, "Conventions".
6505  */
6506 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6507 {
6508         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6509                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6510                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6511 }
6512
6513 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6514 {
6515         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6516                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6517                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6518                         | X86_EFLAGS_CF);
6519 }
6520
6521 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6522                                         u32 vm_instruction_error)
6523 {
6524         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6525                 /*
6526                  * failValid writes the error number to the current VMCS, which
6527                  * can't be done there isn't a current VMCS.
6528                  */
6529                 nested_vmx_failInvalid(vcpu);
6530                 return;
6531         }
6532         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6533                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6534                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6535                         | X86_EFLAGS_ZF);
6536         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6537         /*
6538          * We don't need to force a shadow sync because
6539          * VM_INSTRUCTION_ERROR is not shadowed
6540          */
6541 }
6542
6543 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6544 {
6545         /* TODO: not to reset guest simply here. */
6546         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6547         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6548 }
6549
6550 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6551 {
6552         struct vcpu_vmx *vmx =
6553                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6554
6555         vmx->nested.preemption_timer_expired = true;
6556         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6557         kvm_vcpu_kick(&vmx->vcpu);
6558
6559         return HRTIMER_NORESTART;
6560 }
6561
6562 /*
6563  * Decode the memory-address operand of a vmx instruction, as recorded on an
6564  * exit caused by such an instruction (run by a guest hypervisor).
6565  * On success, returns 0. When the operand is invalid, returns 1 and throws
6566  * #UD or #GP.
6567  */
6568 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6569                                  unsigned long exit_qualification,
6570                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6571 {
6572         gva_t off;
6573         bool exn;
6574         struct kvm_segment s;
6575
6576         /*
6577          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6578          * Execution", on an exit, vmx_instruction_info holds most of the
6579          * addressing components of the operand. Only the displacement part
6580          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6581          * For how an actual address is calculated from all these components,
6582          * refer to Vol. 1, "Operand Addressing".
6583          */
6584         int  scaling = vmx_instruction_info & 3;
6585         int  addr_size = (vmx_instruction_info >> 7) & 7;
6586         bool is_reg = vmx_instruction_info & (1u << 10);
6587         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6588         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6589         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6590         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6591         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6592
6593         if (is_reg) {
6594                 kvm_queue_exception(vcpu, UD_VECTOR);
6595                 return 1;
6596         }
6597
6598         /* Addr = segment_base + offset */
6599         /* offset = base + [index * scale] + displacement */
6600         off = exit_qualification; /* holds the displacement */
6601         if (base_is_valid)
6602                 off += kvm_register_read(vcpu, base_reg);
6603         if (index_is_valid)
6604                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6605         vmx_get_segment(vcpu, &s, seg_reg);
6606         *ret = s.base + off;
6607
6608         if (addr_size == 1) /* 32 bit */
6609                 *ret &= 0xffffffff;
6610
6611         /* Checks for #GP/#SS exceptions. */
6612         exn = false;
6613         if (is_protmode(vcpu)) {
6614                 /* Protected mode: apply checks for segment validity in the
6615                  * following order:
6616                  * - segment type check (#GP(0) may be thrown)
6617                  * - usability check (#GP(0)/#SS(0))
6618                  * - limit check (#GP(0)/#SS(0))
6619                  */
6620                 if (wr)
6621                         /* #GP(0) if the destination operand is located in a
6622                          * read-only data segment or any code segment.
6623                          */
6624                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6625                 else
6626                         /* #GP(0) if the source operand is located in an
6627                          * execute-only code segment
6628                          */
6629                         exn = ((s.type & 0xa) == 8);
6630         }
6631         if (exn) {
6632                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6633                 return 1;
6634         }
6635         if (is_long_mode(vcpu)) {
6636                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6637                  * non-canonical form. This is an only check for long mode.
6638                  */
6639                 exn = is_noncanonical_address(*ret);
6640         } else if (is_protmode(vcpu)) {
6641                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6642                  */
6643                 exn = (s.unusable != 0);
6644                 /* Protected mode: #GP(0)/#SS(0) if the memory
6645                  * operand is outside the segment limit.
6646                  */
6647                 exn = exn || (off + sizeof(u64) > s.limit);
6648         }
6649         if (exn) {
6650                 kvm_queue_exception_e(vcpu,
6651                                       seg_reg == VCPU_SREG_SS ?
6652                                                 SS_VECTOR : GP_VECTOR,
6653                                       0);
6654                 return 1;
6655         }
6656
6657         return 0;
6658 }
6659
6660 /*
6661  * This function performs the various checks including
6662  * - if it's 4KB aligned
6663  * - No bits beyond the physical address width are set
6664  * - Returns 0 on success or else 1
6665  * (Intel SDM Section 30.3)
6666  */
6667 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6668                                   gpa_t *vmpointer)
6669 {
6670         gva_t gva;
6671         gpa_t vmptr;
6672         struct x86_exception e;
6673         struct page *page;
6674         struct vcpu_vmx *vmx = to_vmx(vcpu);
6675         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6676
6677         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6678                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6679                 return 1;
6680
6681         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6682                                 sizeof(vmptr), &e)) {
6683                 kvm_inject_page_fault(vcpu, &e);
6684                 return 1;
6685         }
6686
6687         switch (exit_reason) {
6688         case EXIT_REASON_VMON:
6689                 /*
6690                  * SDM 3: 24.11.5
6691                  * The first 4 bytes of VMXON region contain the supported
6692                  * VMCS revision identifier
6693                  *
6694                  * Note - IA32_VMX_BASIC[48] will never be 1
6695                  * for the nested case;
6696                  * which replaces physical address width with 32
6697                  *
6698                  */
6699                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6700                         nested_vmx_failInvalid(vcpu);
6701                         skip_emulated_instruction(vcpu);
6702                         return 1;
6703                 }
6704
6705                 page = nested_get_page(vcpu, vmptr);
6706                 if (page == NULL ||
6707                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6708                         nested_vmx_failInvalid(vcpu);
6709                         kunmap(page);
6710                         skip_emulated_instruction(vcpu);
6711                         return 1;
6712                 }
6713                 kunmap(page);
6714                 vmx->nested.vmxon_ptr = vmptr;
6715                 break;
6716         case EXIT_REASON_VMCLEAR:
6717                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6718                         nested_vmx_failValid(vcpu,
6719                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6720                         skip_emulated_instruction(vcpu);
6721                         return 1;
6722                 }
6723
6724                 if (vmptr == vmx->nested.vmxon_ptr) {
6725                         nested_vmx_failValid(vcpu,
6726                                              VMXERR_VMCLEAR_VMXON_POINTER);
6727                         skip_emulated_instruction(vcpu);
6728                         return 1;
6729                 }
6730                 break;
6731         case EXIT_REASON_VMPTRLD:
6732                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6733                         nested_vmx_failValid(vcpu,
6734                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6735                         skip_emulated_instruction(vcpu);
6736                         return 1;
6737                 }
6738
6739                 if (vmptr == vmx->nested.vmxon_ptr) {
6740                         nested_vmx_failValid(vcpu,
6741                                              VMXERR_VMCLEAR_VMXON_POINTER);
6742                         skip_emulated_instruction(vcpu);
6743                         return 1;
6744                 }
6745                 break;
6746         default:
6747                 return 1; /* shouldn't happen */
6748         }
6749
6750         if (vmpointer)
6751                 *vmpointer = vmptr;
6752         return 0;
6753 }
6754
6755 /*
6756  * Emulate the VMXON instruction.
6757  * Currently, we just remember that VMX is active, and do not save or even
6758  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6759  * do not currently need to store anything in that guest-allocated memory
6760  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6761  * argument is different from the VMXON pointer (which the spec says they do).
6762  */
6763 static int handle_vmon(struct kvm_vcpu *vcpu)
6764 {
6765         struct kvm_segment cs;
6766         struct vcpu_vmx *vmx = to_vmx(vcpu);
6767         struct vmcs *shadow_vmcs;
6768         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6769                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6770
6771         /* The Intel VMX Instruction Reference lists a bunch of bits that
6772          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6773          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6774          * Otherwise, we should fail with #UD. We test these now:
6775          */
6776         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6777             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6778             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6779                 kvm_queue_exception(vcpu, UD_VECTOR);
6780                 return 1;
6781         }
6782
6783         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6784         if (is_long_mode(vcpu) && !cs.l) {
6785                 kvm_queue_exception(vcpu, UD_VECTOR);
6786                 return 1;
6787         }
6788
6789         if (vmx_get_cpl(vcpu)) {
6790                 kvm_inject_gp(vcpu, 0);
6791                 return 1;
6792         }
6793
6794         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6795                 return 1;
6796
6797         if (vmx->nested.vmxon) {
6798                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6799                 skip_emulated_instruction(vcpu);
6800                 return 1;
6801         }
6802
6803         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6804                         != VMXON_NEEDED_FEATURES) {
6805                 kvm_inject_gp(vcpu, 0);
6806                 return 1;
6807         }
6808
6809         if (enable_shadow_vmcs) {
6810                 shadow_vmcs = alloc_vmcs();
6811                 if (!shadow_vmcs)
6812                         return -ENOMEM;
6813                 /* mark vmcs as shadow */
6814                 shadow_vmcs->revision_id |= (1u << 31);
6815                 /* init shadow vmcs */
6816                 vmcs_clear(shadow_vmcs);
6817                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6818         }
6819
6820         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6821         vmx->nested.vmcs02_num = 0;
6822
6823         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6824                      HRTIMER_MODE_REL);
6825         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6826
6827         vmx->nested.vmxon = true;
6828
6829         skip_emulated_instruction(vcpu);
6830         nested_vmx_succeed(vcpu);
6831         return 1;
6832 }
6833
6834 /*
6835  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6836  * for running VMX instructions (except VMXON, whose prerequisites are
6837  * slightly different). It also specifies what exception to inject otherwise.
6838  */
6839 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6840 {
6841         struct kvm_segment cs;
6842         struct vcpu_vmx *vmx = to_vmx(vcpu);
6843
6844         if (!vmx->nested.vmxon) {
6845                 kvm_queue_exception(vcpu, UD_VECTOR);
6846                 return 0;
6847         }
6848
6849         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6850         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6851             (is_long_mode(vcpu) && !cs.l)) {
6852                 kvm_queue_exception(vcpu, UD_VECTOR);
6853                 return 0;
6854         }
6855
6856         if (vmx_get_cpl(vcpu)) {
6857                 kvm_inject_gp(vcpu, 0);
6858                 return 0;
6859         }
6860
6861         return 1;
6862 }
6863
6864 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6865 {
6866         if (vmx->nested.current_vmptr == -1ull)
6867                 return;
6868
6869         /* current_vmptr and current_vmcs12 are always set/reset together */
6870         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6871                 return;
6872
6873         if (enable_shadow_vmcs) {
6874                 /* copy to memory all shadowed fields in case
6875                    they were modified */
6876                 copy_shadow_to_vmcs12(vmx);
6877                 vmx->nested.sync_shadow_vmcs = false;
6878                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6879                                 SECONDARY_EXEC_SHADOW_VMCS);
6880                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6881         }
6882         vmx->nested.posted_intr_nv = -1;
6883         kunmap(vmx->nested.current_vmcs12_page);
6884         nested_release_page(vmx->nested.current_vmcs12_page);
6885         vmx->nested.current_vmptr = -1ull;
6886         vmx->nested.current_vmcs12 = NULL;
6887 }
6888
6889 /*
6890  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6891  * just stops using VMX.
6892  */
6893 static void free_nested(struct vcpu_vmx *vmx)
6894 {
6895         if (!vmx->nested.vmxon)
6896                 return;
6897
6898         vmx->nested.vmxon = false;
6899         free_vpid(vmx->nested.vpid02);
6900         nested_release_vmcs12(vmx);
6901         if (enable_shadow_vmcs)
6902                 free_vmcs(vmx->nested.current_shadow_vmcs);
6903         /* Unpin physical memory we referred to in current vmcs02 */
6904         if (vmx->nested.apic_access_page) {
6905                 nested_release_page(vmx->nested.apic_access_page);
6906                 vmx->nested.apic_access_page = NULL;
6907         }
6908         if (vmx->nested.virtual_apic_page) {
6909                 nested_release_page(vmx->nested.virtual_apic_page);
6910                 vmx->nested.virtual_apic_page = NULL;
6911         }
6912         if (vmx->nested.pi_desc_page) {
6913                 kunmap(vmx->nested.pi_desc_page);
6914                 nested_release_page(vmx->nested.pi_desc_page);
6915                 vmx->nested.pi_desc_page = NULL;
6916                 vmx->nested.pi_desc = NULL;
6917         }
6918
6919         nested_free_all_saved_vmcss(vmx);
6920 }
6921
6922 /* Emulate the VMXOFF instruction */
6923 static int handle_vmoff(struct kvm_vcpu *vcpu)
6924 {
6925         if (!nested_vmx_check_permission(vcpu))
6926                 return 1;
6927         free_nested(to_vmx(vcpu));
6928         skip_emulated_instruction(vcpu);
6929         nested_vmx_succeed(vcpu);
6930         return 1;
6931 }
6932
6933 /* Emulate the VMCLEAR instruction */
6934 static int handle_vmclear(struct kvm_vcpu *vcpu)
6935 {
6936         struct vcpu_vmx *vmx = to_vmx(vcpu);
6937         gpa_t vmptr;
6938         struct vmcs12 *vmcs12;
6939         struct page *page;
6940
6941         if (!nested_vmx_check_permission(vcpu))
6942                 return 1;
6943
6944         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6945                 return 1;
6946
6947         if (vmptr == vmx->nested.current_vmptr)
6948                 nested_release_vmcs12(vmx);
6949
6950         page = nested_get_page(vcpu, vmptr);
6951         if (page == NULL) {
6952                 /*
6953                  * For accurate processor emulation, VMCLEAR beyond available
6954                  * physical memory should do nothing at all. However, it is
6955                  * possible that a nested vmx bug, not a guest hypervisor bug,
6956                  * resulted in this case, so let's shut down before doing any
6957                  * more damage:
6958                  */
6959                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6960                 return 1;
6961         }
6962         vmcs12 = kmap(page);
6963         vmcs12->launch_state = 0;
6964         kunmap(page);
6965         nested_release_page(page);
6966
6967         nested_free_vmcs02(vmx, vmptr);
6968
6969         skip_emulated_instruction(vcpu);
6970         nested_vmx_succeed(vcpu);
6971         return 1;
6972 }
6973
6974 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6975
6976 /* Emulate the VMLAUNCH instruction */
6977 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6978 {
6979         return nested_vmx_run(vcpu, true);
6980 }
6981
6982 /* Emulate the VMRESUME instruction */
6983 static int handle_vmresume(struct kvm_vcpu *vcpu)
6984 {
6985
6986         return nested_vmx_run(vcpu, false);
6987 }
6988
6989 enum vmcs_field_type {
6990         VMCS_FIELD_TYPE_U16 = 0,
6991         VMCS_FIELD_TYPE_U64 = 1,
6992         VMCS_FIELD_TYPE_U32 = 2,
6993         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6994 };
6995
6996 static inline int vmcs_field_type(unsigned long field)
6997 {
6998         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6999                 return VMCS_FIELD_TYPE_U32;
7000         return (field >> 13) & 0x3 ;
7001 }
7002
7003 static inline int vmcs_field_readonly(unsigned long field)
7004 {
7005         return (((field >> 10) & 0x3) == 1);
7006 }
7007
7008 /*
7009  * Read a vmcs12 field. Since these can have varying lengths and we return
7010  * one type, we chose the biggest type (u64) and zero-extend the return value
7011  * to that size. Note that the caller, handle_vmread, might need to use only
7012  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7013  * 64-bit fields are to be returned).
7014  */
7015 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7016                                   unsigned long field, u64 *ret)
7017 {
7018         short offset = vmcs_field_to_offset(field);
7019         char *p;
7020
7021         if (offset < 0)
7022                 return offset;
7023
7024         p = ((char *)(get_vmcs12(vcpu))) + offset;
7025
7026         switch (vmcs_field_type(field)) {
7027         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7028                 *ret = *((natural_width *)p);
7029                 return 0;
7030         case VMCS_FIELD_TYPE_U16:
7031                 *ret = *((u16 *)p);
7032                 return 0;
7033         case VMCS_FIELD_TYPE_U32:
7034                 *ret = *((u32 *)p);
7035                 return 0;
7036         case VMCS_FIELD_TYPE_U64:
7037                 *ret = *((u64 *)p);
7038                 return 0;
7039         default:
7040                 WARN_ON(1);
7041                 return -ENOENT;
7042         }
7043 }
7044
7045
7046 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7047                                    unsigned long field, u64 field_value){
7048         short offset = vmcs_field_to_offset(field);
7049         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7050         if (offset < 0)
7051                 return offset;
7052
7053         switch (vmcs_field_type(field)) {
7054         case VMCS_FIELD_TYPE_U16:
7055                 *(u16 *)p = field_value;
7056                 return 0;
7057         case VMCS_FIELD_TYPE_U32:
7058                 *(u32 *)p = field_value;
7059                 return 0;
7060         case VMCS_FIELD_TYPE_U64:
7061                 *(u64 *)p = field_value;
7062                 return 0;
7063         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7064                 *(natural_width *)p = field_value;
7065                 return 0;
7066         default:
7067                 WARN_ON(1);
7068                 return -ENOENT;
7069         }
7070
7071 }
7072
7073 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7074 {
7075         int i;
7076         unsigned long field;
7077         u64 field_value;
7078         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7079         const unsigned long *fields = shadow_read_write_fields;
7080         const int num_fields = max_shadow_read_write_fields;
7081
7082         preempt_disable();
7083
7084         vmcs_load(shadow_vmcs);
7085
7086         for (i = 0; i < num_fields; i++) {
7087                 field = fields[i];
7088                 switch (vmcs_field_type(field)) {
7089                 case VMCS_FIELD_TYPE_U16:
7090                         field_value = vmcs_read16(field);
7091                         break;
7092                 case VMCS_FIELD_TYPE_U32:
7093                         field_value = vmcs_read32(field);
7094                         break;
7095                 case VMCS_FIELD_TYPE_U64:
7096                         field_value = vmcs_read64(field);
7097                         break;
7098                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7099                         field_value = vmcs_readl(field);
7100                         break;
7101                 default:
7102                         WARN_ON(1);
7103                         continue;
7104                 }
7105                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7106         }
7107
7108         vmcs_clear(shadow_vmcs);
7109         vmcs_load(vmx->loaded_vmcs->vmcs);
7110
7111         preempt_enable();
7112 }
7113
7114 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7115 {
7116         const unsigned long *fields[] = {
7117                 shadow_read_write_fields,
7118                 shadow_read_only_fields
7119         };
7120         const int max_fields[] = {
7121                 max_shadow_read_write_fields,
7122                 max_shadow_read_only_fields
7123         };
7124         int i, q;
7125         unsigned long field;
7126         u64 field_value = 0;
7127         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7128
7129         vmcs_load(shadow_vmcs);
7130
7131         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7132                 for (i = 0; i < max_fields[q]; i++) {
7133                         field = fields[q][i];
7134                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7135
7136                         switch (vmcs_field_type(field)) {
7137                         case VMCS_FIELD_TYPE_U16:
7138                                 vmcs_write16(field, (u16)field_value);
7139                                 break;
7140                         case VMCS_FIELD_TYPE_U32:
7141                                 vmcs_write32(field, (u32)field_value);
7142                                 break;
7143                         case VMCS_FIELD_TYPE_U64:
7144                                 vmcs_write64(field, (u64)field_value);
7145                                 break;
7146                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7147                                 vmcs_writel(field, (long)field_value);
7148                                 break;
7149                         default:
7150                                 WARN_ON(1);
7151                                 break;
7152                         }
7153                 }
7154         }
7155
7156         vmcs_clear(shadow_vmcs);
7157         vmcs_load(vmx->loaded_vmcs->vmcs);
7158 }
7159
7160 /*
7161  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7162  * used before) all generate the same failure when it is missing.
7163  */
7164 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7165 {
7166         struct vcpu_vmx *vmx = to_vmx(vcpu);
7167         if (vmx->nested.current_vmptr == -1ull) {
7168                 nested_vmx_failInvalid(vcpu);
7169                 skip_emulated_instruction(vcpu);
7170                 return 0;
7171         }
7172         return 1;
7173 }
7174
7175 static int handle_vmread(struct kvm_vcpu *vcpu)
7176 {
7177         unsigned long field;
7178         u64 field_value;
7179         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7180         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7181         gva_t gva = 0;
7182
7183         if (!nested_vmx_check_permission(vcpu) ||
7184             !nested_vmx_check_vmcs12(vcpu))
7185                 return 1;
7186
7187         /* Decode instruction info and find the field to read */
7188         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7189         /* Read the field, zero-extended to a u64 field_value */
7190         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7191                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7192                 skip_emulated_instruction(vcpu);
7193                 return 1;
7194         }
7195         /*
7196          * Now copy part of this value to register or memory, as requested.
7197          * Note that the number of bits actually copied is 32 or 64 depending
7198          * on the guest's mode (32 or 64 bit), not on the given field's length.
7199          */
7200         if (vmx_instruction_info & (1u << 10)) {
7201                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7202                         field_value);
7203         } else {
7204                 if (get_vmx_mem_address(vcpu, exit_qualification,
7205                                 vmx_instruction_info, true, &gva))
7206                         return 1;
7207                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7208                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7209                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7210         }
7211
7212         nested_vmx_succeed(vcpu);
7213         skip_emulated_instruction(vcpu);
7214         return 1;
7215 }
7216
7217
7218 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7219 {
7220         unsigned long field;
7221         gva_t gva;
7222         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7223         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7224         /* The value to write might be 32 or 64 bits, depending on L1's long
7225          * mode, and eventually we need to write that into a field of several
7226          * possible lengths. The code below first zero-extends the value to 64
7227          * bit (field_value), and then copies only the approriate number of
7228          * bits into the vmcs12 field.
7229          */
7230         u64 field_value = 0;
7231         struct x86_exception e;
7232
7233         if (!nested_vmx_check_permission(vcpu) ||
7234             !nested_vmx_check_vmcs12(vcpu))
7235                 return 1;
7236
7237         if (vmx_instruction_info & (1u << 10))
7238                 field_value = kvm_register_readl(vcpu,
7239                         (((vmx_instruction_info) >> 3) & 0xf));
7240         else {
7241                 if (get_vmx_mem_address(vcpu, exit_qualification,
7242                                 vmx_instruction_info, false, &gva))
7243                         return 1;
7244                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7245                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7246                         kvm_inject_page_fault(vcpu, &e);
7247                         return 1;
7248                 }
7249         }
7250
7251
7252         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7253         if (vmcs_field_readonly(field)) {
7254                 nested_vmx_failValid(vcpu,
7255                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7256                 skip_emulated_instruction(vcpu);
7257                 return 1;
7258         }
7259
7260         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7261                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7262                 skip_emulated_instruction(vcpu);
7263                 return 1;
7264         }
7265
7266         nested_vmx_succeed(vcpu);
7267         skip_emulated_instruction(vcpu);
7268         return 1;
7269 }
7270
7271 /* Emulate the VMPTRLD instruction */
7272 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7273 {
7274         struct vcpu_vmx *vmx = to_vmx(vcpu);
7275         gpa_t vmptr;
7276
7277         if (!nested_vmx_check_permission(vcpu))
7278                 return 1;
7279
7280         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7281                 return 1;
7282
7283         if (vmx->nested.current_vmptr != vmptr) {
7284                 struct vmcs12 *new_vmcs12;
7285                 struct page *page;
7286                 page = nested_get_page(vcpu, vmptr);
7287                 if (page == NULL) {
7288                         nested_vmx_failInvalid(vcpu);
7289                         skip_emulated_instruction(vcpu);
7290                         return 1;
7291                 }
7292                 new_vmcs12 = kmap(page);
7293                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7294                         kunmap(page);
7295                         nested_release_page_clean(page);
7296                         nested_vmx_failValid(vcpu,
7297                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7298                         skip_emulated_instruction(vcpu);
7299                         return 1;
7300                 }
7301
7302                 nested_release_vmcs12(vmx);
7303                 vmx->nested.current_vmptr = vmptr;
7304                 vmx->nested.current_vmcs12 = new_vmcs12;
7305                 vmx->nested.current_vmcs12_page = page;
7306                 if (enable_shadow_vmcs) {
7307                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7308                                       SECONDARY_EXEC_SHADOW_VMCS);
7309                         vmcs_write64(VMCS_LINK_POINTER,
7310                                      __pa(vmx->nested.current_shadow_vmcs));
7311                         vmx->nested.sync_shadow_vmcs = true;
7312                 }
7313         }
7314
7315         nested_vmx_succeed(vcpu);
7316         skip_emulated_instruction(vcpu);
7317         return 1;
7318 }
7319
7320 /* Emulate the VMPTRST instruction */
7321 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7322 {
7323         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7324         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7325         gva_t vmcs_gva;
7326         struct x86_exception e;
7327
7328         if (!nested_vmx_check_permission(vcpu))
7329                 return 1;
7330
7331         if (get_vmx_mem_address(vcpu, exit_qualification,
7332                         vmx_instruction_info, true, &vmcs_gva))
7333                 return 1;
7334         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7335         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7336                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7337                                  sizeof(u64), &e)) {
7338                 kvm_inject_page_fault(vcpu, &e);
7339                 return 1;
7340         }
7341         nested_vmx_succeed(vcpu);
7342         skip_emulated_instruction(vcpu);
7343         return 1;
7344 }
7345
7346 /* Emulate the INVEPT instruction */
7347 static int handle_invept(struct kvm_vcpu *vcpu)
7348 {
7349         struct vcpu_vmx *vmx = to_vmx(vcpu);
7350         u32 vmx_instruction_info, types;
7351         unsigned long type;
7352         gva_t gva;
7353         struct x86_exception e;
7354         struct {
7355                 u64 eptp, gpa;
7356         } operand;
7357
7358         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7359               SECONDARY_EXEC_ENABLE_EPT) ||
7360             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7361                 kvm_queue_exception(vcpu, UD_VECTOR);
7362                 return 1;
7363         }
7364
7365         if (!nested_vmx_check_permission(vcpu))
7366                 return 1;
7367
7368         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7369                 kvm_queue_exception(vcpu, UD_VECTOR);
7370                 return 1;
7371         }
7372
7373         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7374         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7375
7376         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7377
7378         if (!(types & (1UL << type))) {
7379                 nested_vmx_failValid(vcpu,
7380                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7381                 return 1;
7382         }
7383
7384         /* According to the Intel VMX instruction reference, the memory
7385          * operand is read even if it isn't needed (e.g., for type==global)
7386          */
7387         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7388                         vmx_instruction_info, false, &gva))
7389                 return 1;
7390         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7391                                 sizeof(operand), &e)) {
7392                 kvm_inject_page_fault(vcpu, &e);
7393                 return 1;
7394         }
7395
7396         switch (type) {
7397         case VMX_EPT_EXTENT_GLOBAL:
7398                 kvm_mmu_sync_roots(vcpu);
7399                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7400                 nested_vmx_succeed(vcpu);
7401                 break;
7402         default:
7403                 /* Trap single context invalidation invept calls */
7404                 BUG_ON(1);
7405                 break;
7406         }
7407
7408         skip_emulated_instruction(vcpu);
7409         return 1;
7410 }
7411
7412 static int handle_invvpid(struct kvm_vcpu *vcpu)
7413 {
7414         struct vcpu_vmx *vmx = to_vmx(vcpu);
7415         u32 vmx_instruction_info;
7416         unsigned long type, types;
7417         gva_t gva;
7418         struct x86_exception e;
7419         int vpid;
7420
7421         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7422               SECONDARY_EXEC_ENABLE_VPID) ||
7423                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7424                 kvm_queue_exception(vcpu, UD_VECTOR);
7425                 return 1;
7426         }
7427
7428         if (!nested_vmx_check_permission(vcpu))
7429                 return 1;
7430
7431         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7432         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7433
7434         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7435
7436         if (!(types & (1UL << type))) {
7437                 nested_vmx_failValid(vcpu,
7438                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7439                 return 1;
7440         }
7441
7442         /* according to the intel vmx instruction reference, the memory
7443          * operand is read even if it isn't needed (e.g., for type==global)
7444          */
7445         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7446                         vmx_instruction_info, false, &gva))
7447                 return 1;
7448         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7449                                 sizeof(u32), &e)) {
7450                 kvm_inject_page_fault(vcpu, &e);
7451                 return 1;
7452         }
7453
7454         switch (type) {
7455         case VMX_VPID_EXTENT_ALL_CONTEXT:
7456                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7457                 nested_vmx_succeed(vcpu);
7458                 break;
7459         default:
7460                 /* Trap single context invalidation invvpid calls */
7461                 BUG_ON(1);
7462                 break;
7463         }
7464
7465         skip_emulated_instruction(vcpu);
7466         return 1;
7467 }
7468
7469 static int handle_pml_full(struct kvm_vcpu *vcpu)
7470 {
7471         unsigned long exit_qualification;
7472
7473         trace_kvm_pml_full(vcpu->vcpu_id);
7474
7475         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7476
7477         /*
7478          * PML buffer FULL happened while executing iret from NMI,
7479          * "blocked by NMI" bit has to be set before next VM entry.
7480          */
7481         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7482                         cpu_has_virtual_nmis() &&
7483                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7484                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7485                                 GUEST_INTR_STATE_NMI);
7486
7487         /*
7488          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7489          * here.., and there's no userspace involvement needed for PML.
7490          */
7491         return 1;
7492 }
7493
7494 static int handle_pcommit(struct kvm_vcpu *vcpu)
7495 {
7496         /* we never catch pcommit instruct for L1 guest. */
7497         WARN_ON(1);
7498         return 1;
7499 }
7500
7501 /*
7502  * The exit handlers return 1 if the exit was handled fully and guest execution
7503  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7504  * to be done to userspace and return 0.
7505  */
7506 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7507         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7508         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7509         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7510         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7511         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7512         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7513         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7514         [EXIT_REASON_CPUID]                   = handle_cpuid,
7515         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7516         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7517         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7518         [EXIT_REASON_HLT]                     = handle_halt,
7519         [EXIT_REASON_INVD]                    = handle_invd,
7520         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7521         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7522         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7523         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7524         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7525         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7526         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7527         [EXIT_REASON_VMREAD]                  = handle_vmread,
7528         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7529         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7530         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7531         [EXIT_REASON_VMON]                    = handle_vmon,
7532         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7533         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7534         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7535         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7536         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7537         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7538         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7539         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7540         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7541         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7542         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7543         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7544         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7545         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7546         [EXIT_REASON_INVEPT]                  = handle_invept,
7547         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7548         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7549         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7550         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7551         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7552 };
7553
7554 static const int kvm_vmx_max_exit_handlers =
7555         ARRAY_SIZE(kvm_vmx_exit_handlers);
7556
7557 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7558                                        struct vmcs12 *vmcs12)
7559 {
7560         unsigned long exit_qualification;
7561         gpa_t bitmap, last_bitmap;
7562         unsigned int port;
7563         int size;
7564         u8 b;
7565
7566         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7567                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7568
7569         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7570
7571         port = exit_qualification >> 16;
7572         size = (exit_qualification & 7) + 1;
7573
7574         last_bitmap = (gpa_t)-1;
7575         b = -1;
7576
7577         while (size > 0) {
7578                 if (port < 0x8000)
7579                         bitmap = vmcs12->io_bitmap_a;
7580                 else if (port < 0x10000)
7581                         bitmap = vmcs12->io_bitmap_b;
7582                 else
7583                         return true;
7584                 bitmap += (port & 0x7fff) / 8;
7585
7586                 if (last_bitmap != bitmap)
7587                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7588                                 return true;
7589                 if (b & (1 << (port & 7)))
7590                         return true;
7591
7592                 port++;
7593                 size--;
7594                 last_bitmap = bitmap;
7595         }
7596
7597         return false;
7598 }
7599
7600 /*
7601  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7602  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7603  * disinterest in the current event (read or write a specific MSR) by using an
7604  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7605  */
7606 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7607         struct vmcs12 *vmcs12, u32 exit_reason)
7608 {
7609         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7610         gpa_t bitmap;
7611
7612         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7613                 return true;
7614
7615         /*
7616          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7617          * for the four combinations of read/write and low/high MSR numbers.
7618          * First we need to figure out which of the four to use:
7619          */
7620         bitmap = vmcs12->msr_bitmap;
7621         if (exit_reason == EXIT_REASON_MSR_WRITE)
7622                 bitmap += 2048;
7623         if (msr_index >= 0xc0000000) {
7624                 msr_index -= 0xc0000000;
7625                 bitmap += 1024;
7626         }
7627
7628         /* Then read the msr_index'th bit from this bitmap: */
7629         if (msr_index < 1024*8) {
7630                 unsigned char b;
7631                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7632                         return true;
7633                 return 1 & (b >> (msr_index & 7));
7634         } else
7635                 return true; /* let L1 handle the wrong parameter */
7636 }
7637
7638 /*
7639  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7640  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7641  * intercept (via guest_host_mask etc.) the current event.
7642  */
7643 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7644         struct vmcs12 *vmcs12)
7645 {
7646         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7647         int cr = exit_qualification & 15;
7648         int reg = (exit_qualification >> 8) & 15;
7649         unsigned long val = kvm_register_readl(vcpu, reg);
7650
7651         switch ((exit_qualification >> 4) & 3) {
7652         case 0: /* mov to cr */
7653                 switch (cr) {
7654                 case 0:
7655                         if (vmcs12->cr0_guest_host_mask &
7656                             (val ^ vmcs12->cr0_read_shadow))
7657                                 return true;
7658                         break;
7659                 case 3:
7660                         if ((vmcs12->cr3_target_count >= 1 &&
7661                                         vmcs12->cr3_target_value0 == val) ||
7662                                 (vmcs12->cr3_target_count >= 2 &&
7663                                         vmcs12->cr3_target_value1 == val) ||
7664                                 (vmcs12->cr3_target_count >= 3 &&
7665                                         vmcs12->cr3_target_value2 == val) ||
7666                                 (vmcs12->cr3_target_count >= 4 &&
7667                                         vmcs12->cr3_target_value3 == val))
7668                                 return false;
7669                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7670                                 return true;
7671                         break;
7672                 case 4:
7673                         if (vmcs12->cr4_guest_host_mask &
7674                             (vmcs12->cr4_read_shadow ^ val))
7675                                 return true;
7676                         break;
7677                 case 8:
7678                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7679                                 return true;
7680                         break;
7681                 }
7682                 break;
7683         case 2: /* clts */
7684                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7685                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7686                         return true;
7687                 break;
7688         case 1: /* mov from cr */
7689                 switch (cr) {
7690                 case 3:
7691                         if (vmcs12->cpu_based_vm_exec_control &
7692                             CPU_BASED_CR3_STORE_EXITING)
7693                                 return true;
7694                         break;
7695                 case 8:
7696                         if (vmcs12->cpu_based_vm_exec_control &
7697                             CPU_BASED_CR8_STORE_EXITING)
7698                                 return true;
7699                         break;
7700                 }
7701                 break;
7702         case 3: /* lmsw */
7703                 /*
7704                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7705                  * cr0. Other attempted changes are ignored, with no exit.
7706                  */
7707                 if (vmcs12->cr0_guest_host_mask & 0xe &
7708                     (val ^ vmcs12->cr0_read_shadow))
7709                         return true;
7710                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7711                     !(vmcs12->cr0_read_shadow & 0x1) &&
7712                     (val & 0x1))
7713                         return true;
7714                 break;
7715         }
7716         return false;
7717 }
7718
7719 /*
7720  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7721  * should handle it ourselves in L0 (and then continue L2). Only call this
7722  * when in is_guest_mode (L2).
7723  */
7724 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7725 {
7726         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7727         struct vcpu_vmx *vmx = to_vmx(vcpu);
7728         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7729         u32 exit_reason = vmx->exit_reason;
7730
7731         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7732                                 vmcs_readl(EXIT_QUALIFICATION),
7733                                 vmx->idt_vectoring_info,
7734                                 intr_info,
7735                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7736                                 KVM_ISA_VMX);
7737
7738         if (vmx->nested.nested_run_pending)
7739                 return false;
7740
7741         if (unlikely(vmx->fail)) {
7742                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7743                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7744                 return true;
7745         }
7746
7747         switch (exit_reason) {
7748         case EXIT_REASON_EXCEPTION_NMI:
7749                 if (!is_exception(intr_info))
7750                         return false;
7751                 else if (is_page_fault(intr_info))
7752                         return enable_ept;
7753                 else if (is_no_device(intr_info) &&
7754                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7755                         return false;
7756                 else if (is_debug(intr_info) &&
7757                          vcpu->guest_debug &
7758                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7759                         return false;
7760                 else if (is_breakpoint(intr_info) &&
7761                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7762                         return false;
7763                 return vmcs12->exception_bitmap &
7764                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7765         case EXIT_REASON_EXTERNAL_INTERRUPT:
7766                 return false;
7767         case EXIT_REASON_TRIPLE_FAULT:
7768                 return true;
7769         case EXIT_REASON_PENDING_INTERRUPT:
7770                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7771         case EXIT_REASON_NMI_WINDOW:
7772                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7773         case EXIT_REASON_TASK_SWITCH:
7774                 return true;
7775         case EXIT_REASON_CPUID:
7776                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7777                         return false;
7778                 return true;
7779         case EXIT_REASON_HLT:
7780                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7781         case EXIT_REASON_INVD:
7782                 return true;
7783         case EXIT_REASON_INVLPG:
7784                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7785         case EXIT_REASON_RDPMC:
7786                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7787         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7788                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7789         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7790         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7791         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7792         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7793         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7794         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7795                 /*
7796                  * VMX instructions trap unconditionally. This allows L1 to
7797                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7798                  */
7799                 return true;
7800         case EXIT_REASON_CR_ACCESS:
7801                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7802         case EXIT_REASON_DR_ACCESS:
7803                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7804         case EXIT_REASON_IO_INSTRUCTION:
7805                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7806         case EXIT_REASON_MSR_READ:
7807         case EXIT_REASON_MSR_WRITE:
7808                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7809         case EXIT_REASON_INVALID_STATE:
7810                 return true;
7811         case EXIT_REASON_MWAIT_INSTRUCTION:
7812                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7813         case EXIT_REASON_MONITOR_TRAP_FLAG:
7814                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7815         case EXIT_REASON_MONITOR_INSTRUCTION:
7816                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7817         case EXIT_REASON_PAUSE_INSTRUCTION:
7818                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7819                         nested_cpu_has2(vmcs12,
7820                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7821         case EXIT_REASON_MCE_DURING_VMENTRY:
7822                 return false;
7823         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7824                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7825         case EXIT_REASON_APIC_ACCESS:
7826                 return nested_cpu_has2(vmcs12,
7827                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7828         case EXIT_REASON_APIC_WRITE:
7829         case EXIT_REASON_EOI_INDUCED:
7830                 /* apic_write and eoi_induced should exit unconditionally. */
7831                 return true;
7832         case EXIT_REASON_EPT_VIOLATION:
7833                 /*
7834                  * L0 always deals with the EPT violation. If nested EPT is
7835                  * used, and the nested mmu code discovers that the address is
7836                  * missing in the guest EPT table (EPT12), the EPT violation
7837                  * will be injected with nested_ept_inject_page_fault()
7838                  */
7839                 return false;
7840         case EXIT_REASON_EPT_MISCONFIG:
7841                 /*
7842                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7843                  * table (shadow on EPT) or a merged EPT table that L0 built
7844                  * (EPT on EPT). So any problems with the structure of the
7845                  * table is L0's fault.
7846                  */
7847                 return false;
7848         case EXIT_REASON_WBINVD:
7849                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7850         case EXIT_REASON_XSETBV:
7851                 return true;
7852         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7853                 /*
7854                  * This should never happen, since it is not possible to
7855                  * set XSS to a non-zero value---neither in L1 nor in L2.
7856                  * If if it were, XSS would have to be checked against
7857                  * the XSS exit bitmap in vmcs12.
7858                  */
7859                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7860         case EXIT_REASON_PCOMMIT:
7861                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7862         default:
7863                 return true;
7864         }
7865 }
7866
7867 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7868 {
7869         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7870         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7871 }
7872
7873 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7874 {
7875         struct page *pml_pg;
7876
7877         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7878         if (!pml_pg)
7879                 return -ENOMEM;
7880
7881         vmx->pml_pg = pml_pg;
7882
7883         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7884         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7885
7886         return 0;
7887 }
7888
7889 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7890 {
7891         if (vmx->pml_pg) {
7892                 __free_page(vmx->pml_pg);
7893                 vmx->pml_pg = NULL;
7894         }
7895 }
7896
7897 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7898 {
7899         struct vcpu_vmx *vmx = to_vmx(vcpu);
7900         u64 *pml_buf;
7901         u16 pml_idx;
7902
7903         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7904
7905         /* Do nothing if PML buffer is empty */
7906         if (pml_idx == (PML_ENTITY_NUM - 1))
7907                 return;
7908
7909         /* PML index always points to next available PML buffer entity */
7910         if (pml_idx >= PML_ENTITY_NUM)
7911                 pml_idx = 0;
7912         else
7913                 pml_idx++;
7914
7915         pml_buf = page_address(vmx->pml_pg);
7916         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7917                 u64 gpa;
7918
7919                 gpa = pml_buf[pml_idx];
7920                 WARN_ON(gpa & (PAGE_SIZE - 1));
7921                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7922         }
7923
7924         /* reset PML index */
7925         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7926 }
7927
7928 /*
7929  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7930  * Called before reporting dirty_bitmap to userspace.
7931  */
7932 static void kvm_flush_pml_buffers(struct kvm *kvm)
7933 {
7934         int i;
7935         struct kvm_vcpu *vcpu;
7936         /*
7937          * We only need to kick vcpu out of guest mode here, as PML buffer
7938          * is flushed at beginning of all VMEXITs, and it's obvious that only
7939          * vcpus running in guest are possible to have unflushed GPAs in PML
7940          * buffer.
7941          */
7942         kvm_for_each_vcpu(i, vcpu, kvm)
7943                 kvm_vcpu_kick(vcpu);
7944 }
7945
7946 static void vmx_dump_sel(char *name, uint32_t sel)
7947 {
7948         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7949                name, vmcs_read32(sel),
7950                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7951                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7952                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7953 }
7954
7955 static void vmx_dump_dtsel(char *name, uint32_t limit)
7956 {
7957         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7958                name, vmcs_read32(limit),
7959                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7960 }
7961
7962 static void dump_vmcs(void)
7963 {
7964         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7965         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7966         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7967         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7968         u32 secondary_exec_control = 0;
7969         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7970         u64 efer = vmcs_read64(GUEST_IA32_EFER);
7971         int i, n;
7972
7973         if (cpu_has_secondary_exec_ctrls())
7974                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7975
7976         pr_err("*** Guest State ***\n");
7977         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7978                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7979                vmcs_readl(CR0_GUEST_HOST_MASK));
7980         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7981                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7982         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7983         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7984             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7985         {
7986                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
7987                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
7988                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
7989                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
7990         }
7991         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7992                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7993         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7994                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7995         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7996                vmcs_readl(GUEST_SYSENTER_ESP),
7997                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7998         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7999         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8000         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8001         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8002         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8003         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8004         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8005         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8006         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8007         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8008         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8009             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8010                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8011                        efer, vmcs_read64(GUEST_IA32_PAT));
8012         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8013                vmcs_read64(GUEST_IA32_DEBUGCTL),
8014                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8015         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8016                 pr_err("PerfGlobCtl = 0x%016llx\n",
8017                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8018         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8019                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8020         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8021                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8022                vmcs_read32(GUEST_ACTIVITY_STATE));
8023         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8024                 pr_err("InterruptStatus = %04x\n",
8025                        vmcs_read16(GUEST_INTR_STATUS));
8026
8027         pr_err("*** Host State ***\n");
8028         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8029                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8030         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8031                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8032                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8033                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8034                vmcs_read16(HOST_TR_SELECTOR));
8035         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8036                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8037                vmcs_readl(HOST_TR_BASE));
8038         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8039                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8040         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8041                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8042                vmcs_readl(HOST_CR4));
8043         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8044                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8045                vmcs_read32(HOST_IA32_SYSENTER_CS),
8046                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8047         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8048                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8049                        vmcs_read64(HOST_IA32_EFER),
8050                        vmcs_read64(HOST_IA32_PAT));
8051         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8052                 pr_err("PerfGlobCtl = 0x%016llx\n",
8053                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8054
8055         pr_err("*** Control State ***\n");
8056         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8057                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8058         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8059         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8060                vmcs_read32(EXCEPTION_BITMAP),
8061                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8062                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8063         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8064                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8065                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8066                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8067         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8068                vmcs_read32(VM_EXIT_INTR_INFO),
8069                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8070                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8071         pr_err("        reason=%08x qualification=%016lx\n",
8072                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8073         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8074                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8075                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8076         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8077         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8078                 pr_err("TSC Multiplier = 0x%016llx\n",
8079                        vmcs_read64(TSC_MULTIPLIER));
8080         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8081                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8082         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8083                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8084         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8085                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8086         n = vmcs_read32(CR3_TARGET_COUNT);
8087         for (i = 0; i + 1 < n; i += 4)
8088                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8089                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8090                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8091         if (i < n)
8092                 pr_err("CR3 target%u=%016lx\n",
8093                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8094         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8095                 pr_err("PLE Gap=%08x Window=%08x\n",
8096                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8097         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8098                 pr_err("Virtual processor ID = 0x%04x\n",
8099                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8100 }
8101
8102 /*
8103  * The guest has exited.  See if we can fix it or if we need userspace
8104  * assistance.
8105  */
8106 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8107 {
8108         struct vcpu_vmx *vmx = to_vmx(vcpu);
8109         u32 exit_reason = vmx->exit_reason;
8110         u32 vectoring_info = vmx->idt_vectoring_info;
8111
8112         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8113
8114         /*
8115          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8116          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8117          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8118          * mode as if vcpus is in root mode, the PML buffer must has been
8119          * flushed already.
8120          */
8121         if (enable_pml)
8122                 vmx_flush_pml_buffer(vcpu);
8123
8124         /* If guest state is invalid, start emulating */
8125         if (vmx->emulation_required)
8126                 return handle_invalid_guest_state(vcpu);
8127
8128         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8129                 nested_vmx_vmexit(vcpu, exit_reason,
8130                                   vmcs_read32(VM_EXIT_INTR_INFO),
8131                                   vmcs_readl(EXIT_QUALIFICATION));
8132                 return 1;
8133         }
8134
8135         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8136                 dump_vmcs();
8137                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8138                 vcpu->run->fail_entry.hardware_entry_failure_reason
8139                         = exit_reason;
8140                 return 0;
8141         }
8142
8143         if (unlikely(vmx->fail)) {
8144                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8145                 vcpu->run->fail_entry.hardware_entry_failure_reason
8146                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8147                 return 0;
8148         }
8149
8150         /*
8151          * Note:
8152          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8153          * delivery event since it indicates guest is accessing MMIO.
8154          * The vm-exit can be triggered again after return to guest that
8155          * will cause infinite loop.
8156          */
8157         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8158                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8159                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8160                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8161                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8162                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8163                 vcpu->run->internal.ndata = 2;
8164                 vcpu->run->internal.data[0] = vectoring_info;
8165                 vcpu->run->internal.data[1] = exit_reason;
8166                 return 0;
8167         }
8168
8169         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8170             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8171                                         get_vmcs12(vcpu))))) {
8172                 if (vmx_interrupt_allowed(vcpu)) {
8173                         vmx->soft_vnmi_blocked = 0;
8174                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8175                            vcpu->arch.nmi_pending) {
8176                         /*
8177                          * This CPU don't support us in finding the end of an
8178                          * NMI-blocked window if the guest runs with IRQs
8179                          * disabled. So we pull the trigger after 1 s of
8180                          * futile waiting, but inform the user about this.
8181                          */
8182                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8183                                "state on VCPU %d after 1 s timeout\n",
8184                                __func__, vcpu->vcpu_id);
8185                         vmx->soft_vnmi_blocked = 0;
8186                 }
8187         }
8188
8189         if (exit_reason < kvm_vmx_max_exit_handlers
8190             && kvm_vmx_exit_handlers[exit_reason])
8191                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8192         else {
8193                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8194                 kvm_queue_exception(vcpu, UD_VECTOR);
8195                 return 1;
8196         }
8197 }
8198
8199 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8200 {
8201         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8202
8203         if (is_guest_mode(vcpu) &&
8204                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8205                 return;
8206
8207         if (irr == -1 || tpr < irr) {
8208                 vmcs_write32(TPR_THRESHOLD, 0);
8209                 return;
8210         }
8211
8212         vmcs_write32(TPR_THRESHOLD, irr);
8213 }
8214
8215 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8216 {
8217         u32 sec_exec_control;
8218
8219         /*
8220          * There is not point to enable virtualize x2apic without enable
8221          * apicv
8222          */
8223         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8224                                 !kvm_vcpu_apicv_active(vcpu))
8225                 return;
8226
8227         if (!cpu_need_tpr_shadow(vcpu))
8228                 return;
8229
8230         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8231
8232         if (set) {
8233                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8234                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8235         } else {
8236                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8237                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8238         }
8239         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8240
8241         vmx_set_msr_bitmap(vcpu);
8242 }
8243
8244 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8245 {
8246         struct vcpu_vmx *vmx = to_vmx(vcpu);
8247
8248         /*
8249          * Currently we do not handle the nested case where L2 has an
8250          * APIC access page of its own; that page is still pinned.
8251          * Hence, we skip the case where the VCPU is in guest mode _and_
8252          * L1 prepared an APIC access page for L2.
8253          *
8254          * For the case where L1 and L2 share the same APIC access page
8255          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8256          * in the vmcs12), this function will only update either the vmcs01
8257          * or the vmcs02.  If the former, the vmcs02 will be updated by
8258          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8259          * the next L2->L1 exit.
8260          */
8261         if (!is_guest_mode(vcpu) ||
8262             !nested_cpu_has2(vmx->nested.current_vmcs12,
8263                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8264                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8265 }
8266
8267 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8268 {
8269         u16 status;
8270         u8 old;
8271
8272         if (isr == -1)
8273                 isr = 0;
8274
8275         status = vmcs_read16(GUEST_INTR_STATUS);
8276         old = status >> 8;
8277         if (isr != old) {
8278                 status &= 0xff;
8279                 status |= isr << 8;
8280                 vmcs_write16(GUEST_INTR_STATUS, status);
8281         }
8282 }
8283
8284 static void vmx_set_rvi(int vector)
8285 {
8286         u16 status;
8287         u8 old;
8288
8289         if (vector == -1)
8290                 vector = 0;
8291
8292         status = vmcs_read16(GUEST_INTR_STATUS);
8293         old = (u8)status & 0xff;
8294         if ((u8)vector != old) {
8295                 status &= ~0xff;
8296                 status |= (u8)vector;
8297                 vmcs_write16(GUEST_INTR_STATUS, status);
8298         }
8299 }
8300
8301 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8302 {
8303         if (!is_guest_mode(vcpu)) {
8304                 vmx_set_rvi(max_irr);
8305                 return;
8306         }
8307
8308         if (max_irr == -1)
8309                 return;
8310
8311         /*
8312          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8313          * handles it.
8314          */
8315         if (nested_exit_on_intr(vcpu))
8316                 return;
8317
8318         /*
8319          * Else, fall back to pre-APICv interrupt injection since L2
8320          * is run without virtual interrupt delivery.
8321          */
8322         if (!kvm_event_needs_reinjection(vcpu) &&
8323             vmx_interrupt_allowed(vcpu)) {
8324                 kvm_queue_interrupt(vcpu, max_irr, false);
8325                 vmx_inject_irq(vcpu);
8326         }
8327 }
8328
8329 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8330 {
8331         if (!kvm_vcpu_apicv_active(vcpu))
8332                 return;
8333
8334         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8335         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8336         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8337         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8338 }
8339
8340 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8341 {
8342         u32 exit_intr_info;
8343
8344         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8345               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8346                 return;
8347
8348         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8349         exit_intr_info = vmx->exit_intr_info;
8350
8351         /* Handle machine checks before interrupts are enabled */
8352         if (is_machine_check(exit_intr_info))
8353                 kvm_machine_check();
8354
8355         /* We need to handle NMIs before interrupts are enabled */
8356         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8357             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8358                 kvm_before_handle_nmi(&vmx->vcpu);
8359                 asm("int $2");
8360                 kvm_after_handle_nmi(&vmx->vcpu);
8361         }
8362 }
8363
8364 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8365 {
8366         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8367
8368         /*
8369          * If external interrupt exists, IF bit is set in rflags/eflags on the
8370          * interrupt stack frame, and interrupt will be enabled on a return
8371          * from interrupt handler.
8372          */
8373         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8374                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8375                 unsigned int vector;
8376                 unsigned long entry;
8377                 gate_desc *desc;
8378                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8379 #ifdef CONFIG_X86_64
8380                 unsigned long tmp;
8381 #endif
8382
8383                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8384                 desc = (gate_desc *)vmx->host_idt_base + vector;
8385                 entry = gate_offset(*desc);
8386                 asm volatile(
8387 #ifdef CONFIG_X86_64
8388                         "mov %%" _ASM_SP ", %[sp]\n\t"
8389                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8390                         "push $%c[ss]\n\t"
8391                         "push %[sp]\n\t"
8392 #endif
8393                         "pushf\n\t"
8394                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8395                         __ASM_SIZE(push) " $%c[cs]\n\t"
8396                         "call *%[entry]\n\t"
8397                         :
8398 #ifdef CONFIG_X86_64
8399                         [sp]"=&r"(tmp)
8400 #endif
8401                         :
8402                         [entry]"r"(entry),
8403                         [ss]"i"(__KERNEL_DS),
8404                         [cs]"i"(__KERNEL_CS)
8405                         );
8406         } else
8407                 local_irq_enable();
8408 }
8409
8410 static bool vmx_has_high_real_mode_segbase(void)
8411 {
8412         return enable_unrestricted_guest || emulate_invalid_guest_state;
8413 }
8414
8415 static bool vmx_mpx_supported(void)
8416 {
8417         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8418                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8419 }
8420
8421 static bool vmx_xsaves_supported(void)
8422 {
8423         return vmcs_config.cpu_based_2nd_exec_ctrl &
8424                 SECONDARY_EXEC_XSAVES;
8425 }
8426
8427 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8428 {
8429         u32 exit_intr_info;
8430         bool unblock_nmi;
8431         u8 vector;
8432         bool idtv_info_valid;
8433
8434         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8435
8436         if (cpu_has_virtual_nmis()) {
8437                 if (vmx->nmi_known_unmasked)
8438                         return;
8439                 /*
8440                  * Can't use vmx->exit_intr_info since we're not sure what
8441                  * the exit reason is.
8442                  */
8443                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8444                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8445                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8446                 /*
8447                  * SDM 3: 27.7.1.2 (September 2008)
8448                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8449                  * a guest IRET fault.
8450                  * SDM 3: 23.2.2 (September 2008)
8451                  * Bit 12 is undefined in any of the following cases:
8452                  *  If the VM exit sets the valid bit in the IDT-vectoring
8453                  *   information field.
8454                  *  If the VM exit is due to a double fault.
8455                  */
8456                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8457                     vector != DF_VECTOR && !idtv_info_valid)
8458                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8459                                       GUEST_INTR_STATE_NMI);
8460                 else
8461                         vmx->nmi_known_unmasked =
8462                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8463                                   & GUEST_INTR_STATE_NMI);
8464         } else if (unlikely(vmx->soft_vnmi_blocked))
8465                 vmx->vnmi_blocked_time +=
8466                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8467 }
8468
8469 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8470                                       u32 idt_vectoring_info,
8471                                       int instr_len_field,
8472                                       int error_code_field)
8473 {
8474         u8 vector;
8475         int type;
8476         bool idtv_info_valid;
8477
8478         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8479
8480         vcpu->arch.nmi_injected = false;
8481         kvm_clear_exception_queue(vcpu);
8482         kvm_clear_interrupt_queue(vcpu);
8483
8484         if (!idtv_info_valid)
8485                 return;
8486
8487         kvm_make_request(KVM_REQ_EVENT, vcpu);
8488
8489         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8490         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8491
8492         switch (type) {
8493         case INTR_TYPE_NMI_INTR:
8494                 vcpu->arch.nmi_injected = true;
8495                 /*
8496                  * SDM 3: 27.7.1.2 (September 2008)
8497                  * Clear bit "block by NMI" before VM entry if a NMI
8498                  * delivery faulted.
8499                  */
8500                 vmx_set_nmi_mask(vcpu, false);
8501                 break;
8502         case INTR_TYPE_SOFT_EXCEPTION:
8503                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8504                 /* fall through */
8505         case INTR_TYPE_HARD_EXCEPTION:
8506                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8507                         u32 err = vmcs_read32(error_code_field);
8508                         kvm_requeue_exception_e(vcpu, vector, err);
8509                 } else
8510                         kvm_requeue_exception(vcpu, vector);
8511                 break;
8512         case INTR_TYPE_SOFT_INTR:
8513                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8514                 /* fall through */
8515         case INTR_TYPE_EXT_INTR:
8516                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8517                 break;
8518         default:
8519                 break;
8520         }
8521 }
8522
8523 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8524 {
8525         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8526                                   VM_EXIT_INSTRUCTION_LEN,
8527                                   IDT_VECTORING_ERROR_CODE);
8528 }
8529
8530 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8531 {
8532         __vmx_complete_interrupts(vcpu,
8533                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8534                                   VM_ENTRY_INSTRUCTION_LEN,
8535                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8536
8537         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8538 }
8539
8540 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8541 {
8542         int i, nr_msrs;
8543         struct perf_guest_switch_msr *msrs;
8544
8545         msrs = perf_guest_get_msrs(&nr_msrs);
8546
8547         if (!msrs)
8548                 return;
8549
8550         for (i = 0; i < nr_msrs; i++)
8551                 if (msrs[i].host == msrs[i].guest)
8552                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8553                 else
8554                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8555                                         msrs[i].host);
8556 }
8557
8558 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8559 {
8560         struct vcpu_vmx *vmx = to_vmx(vcpu);
8561         unsigned long debugctlmsr, cr4;
8562
8563         /* Record the guest's net vcpu time for enforced NMI injections. */
8564         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8565                 vmx->entry_time = ktime_get();
8566
8567         /* Don't enter VMX if guest state is invalid, let the exit handler
8568            start emulation until we arrive back to a valid state */
8569         if (vmx->emulation_required)
8570                 return;
8571
8572         if (vmx->ple_window_dirty) {
8573                 vmx->ple_window_dirty = false;
8574                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8575         }
8576
8577         if (vmx->nested.sync_shadow_vmcs) {
8578                 copy_vmcs12_to_shadow(vmx);
8579                 vmx->nested.sync_shadow_vmcs = false;
8580         }
8581
8582         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8583                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8584         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8585                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8586
8587         cr4 = cr4_read_shadow();
8588         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8589                 vmcs_writel(HOST_CR4, cr4);
8590                 vmx->host_state.vmcs_host_cr4 = cr4;
8591         }
8592
8593         /* When single-stepping over STI and MOV SS, we must clear the
8594          * corresponding interruptibility bits in the guest state. Otherwise
8595          * vmentry fails as it then expects bit 14 (BS) in pending debug
8596          * exceptions being set, but that's not correct for the guest debugging
8597          * case. */
8598         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8599                 vmx_set_interrupt_shadow(vcpu, 0);
8600
8601         atomic_switch_perf_msrs(vmx);
8602         debugctlmsr = get_debugctlmsr();
8603
8604         vmx->__launched = vmx->loaded_vmcs->launched;
8605         asm(
8606                 /* Store host registers */
8607                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8608                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8609                 "push %%" _ASM_CX " \n\t"
8610                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8611                 "je 1f \n\t"
8612                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8613                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8614                 "1: \n\t"
8615                 /* Reload cr2 if changed */
8616                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8617                 "mov %%cr2, %%" _ASM_DX " \n\t"
8618                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8619                 "je 2f \n\t"
8620                 "mov %%" _ASM_AX", %%cr2 \n\t"
8621                 "2: \n\t"
8622                 /* Check if vmlaunch of vmresume is needed */
8623                 "cmpl $0, %c[launched](%0) \n\t"
8624                 /* Load guest registers.  Don't clobber flags. */
8625                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8626                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8627                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8628                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8629                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8630                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8631 #ifdef CONFIG_X86_64
8632                 "mov %c[r8](%0),  %%r8  \n\t"
8633                 "mov %c[r9](%0),  %%r9  \n\t"
8634                 "mov %c[r10](%0), %%r10 \n\t"
8635                 "mov %c[r11](%0), %%r11 \n\t"
8636                 "mov %c[r12](%0), %%r12 \n\t"
8637                 "mov %c[r13](%0), %%r13 \n\t"
8638                 "mov %c[r14](%0), %%r14 \n\t"
8639                 "mov %c[r15](%0), %%r15 \n\t"
8640 #endif
8641                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8642
8643                 /* Enter guest mode */
8644                 "jne 1f \n\t"
8645                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8646                 "jmp 2f \n\t"
8647                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8648                 "2: "
8649                 /* Save guest registers, load host registers, keep flags */
8650                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8651                 "pop %0 \n\t"
8652                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8653                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8654                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8655                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8656                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8657                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8658                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8659 #ifdef CONFIG_X86_64
8660                 "mov %%r8,  %c[r8](%0) \n\t"
8661                 "mov %%r9,  %c[r9](%0) \n\t"
8662                 "mov %%r10, %c[r10](%0) \n\t"
8663                 "mov %%r11, %c[r11](%0) \n\t"
8664                 "mov %%r12, %c[r12](%0) \n\t"
8665                 "mov %%r13, %c[r13](%0) \n\t"
8666                 "mov %%r14, %c[r14](%0) \n\t"
8667                 "mov %%r15, %c[r15](%0) \n\t"
8668 #endif
8669                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8670                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8671
8672                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8673                 "setbe %c[fail](%0) \n\t"
8674                 ".pushsection .rodata \n\t"
8675                 ".global vmx_return \n\t"
8676                 "vmx_return: " _ASM_PTR " 2b \n\t"
8677                 ".popsection"
8678               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8679                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8680                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8681                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8682                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8683                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8684                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8685                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8686                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8687                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8688                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8689 #ifdef CONFIG_X86_64
8690                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8691                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8692                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8693                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8694                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8695                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8696                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8697                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8698 #endif
8699                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8700                 [wordsize]"i"(sizeof(ulong))
8701               : "cc", "memory"
8702 #ifdef CONFIG_X86_64
8703                 , "rax", "rbx", "rdi", "rsi"
8704                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8705 #else
8706                 , "eax", "ebx", "edi", "esi"
8707 #endif
8708               );
8709
8710         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8711         if (debugctlmsr)
8712                 update_debugctlmsr(debugctlmsr);
8713
8714 #ifndef CONFIG_X86_64
8715         /*
8716          * The sysexit path does not restore ds/es, so we must set them to
8717          * a reasonable value ourselves.
8718          *
8719          * We can't defer this to vmx_load_host_state() since that function
8720          * may be executed in interrupt context, which saves and restore segments
8721          * around it, nullifying its effect.
8722          */
8723         loadsegment(ds, __USER_DS);
8724         loadsegment(es, __USER_DS);
8725 #endif
8726
8727         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8728                                   | (1 << VCPU_EXREG_RFLAGS)
8729                                   | (1 << VCPU_EXREG_PDPTR)
8730                                   | (1 << VCPU_EXREG_SEGMENTS)
8731                                   | (1 << VCPU_EXREG_CR3));
8732         vcpu->arch.regs_dirty = 0;
8733
8734         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8735
8736         vmx->loaded_vmcs->launched = 1;
8737
8738         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8739
8740         /*
8741          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8742          * we did not inject a still-pending event to L1 now because of
8743          * nested_run_pending, we need to re-enable this bit.
8744          */
8745         if (vmx->nested.nested_run_pending)
8746                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8747
8748         vmx->nested.nested_run_pending = 0;
8749
8750         vmx_complete_atomic_exit(vmx);
8751         vmx_recover_nmi_blocking(vmx);
8752         vmx_complete_interrupts(vmx);
8753 }
8754
8755 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8756 {
8757         struct vcpu_vmx *vmx = to_vmx(vcpu);
8758         int cpu;
8759
8760         if (vmx->loaded_vmcs == &vmx->vmcs01)
8761                 return;
8762
8763         cpu = get_cpu();
8764         vmx->loaded_vmcs = &vmx->vmcs01;
8765         vmx_vcpu_put(vcpu);
8766         vmx_vcpu_load(vcpu, cpu);
8767         vcpu->cpu = cpu;
8768         put_cpu();
8769 }
8770
8771 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8772 {
8773         struct vcpu_vmx *vmx = to_vmx(vcpu);
8774
8775         if (enable_pml)
8776                 vmx_destroy_pml_buffer(vmx);
8777         free_vpid(vmx->vpid);
8778         leave_guest_mode(vcpu);
8779         vmx_load_vmcs01(vcpu);
8780         free_nested(vmx);
8781         free_loaded_vmcs(vmx->loaded_vmcs);
8782         kfree(vmx->guest_msrs);
8783         kvm_vcpu_uninit(vcpu);
8784         kmem_cache_free(kvm_vcpu_cache, vmx);
8785 }
8786
8787 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8788 {
8789         int err;
8790         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8791         int cpu;
8792
8793         if (!vmx)
8794                 return ERR_PTR(-ENOMEM);
8795
8796         vmx->vpid = allocate_vpid();
8797
8798         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8799         if (err)
8800                 goto free_vcpu;
8801
8802         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8803         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8804                      > PAGE_SIZE);
8805
8806         err = -ENOMEM;
8807         if (!vmx->guest_msrs) {
8808                 goto uninit_vcpu;
8809         }
8810
8811         vmx->loaded_vmcs = &vmx->vmcs01;
8812         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8813         if (!vmx->loaded_vmcs->vmcs)
8814                 goto free_msrs;
8815         if (!vmm_exclusive)
8816                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8817         loaded_vmcs_init(vmx->loaded_vmcs);
8818         if (!vmm_exclusive)
8819                 kvm_cpu_vmxoff();
8820
8821         cpu = get_cpu();
8822         vmx_vcpu_load(&vmx->vcpu, cpu);
8823         vmx->vcpu.cpu = cpu;
8824         err = vmx_vcpu_setup(vmx);
8825         vmx_vcpu_put(&vmx->vcpu);
8826         put_cpu();
8827         if (err)
8828                 goto free_vmcs;
8829         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8830                 err = alloc_apic_access_page(kvm);
8831                 if (err)
8832                         goto free_vmcs;
8833         }
8834
8835         if (enable_ept) {
8836                 if (!kvm->arch.ept_identity_map_addr)
8837                         kvm->arch.ept_identity_map_addr =
8838                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8839                 err = init_rmode_identity_map(kvm);
8840                 if (err)
8841                         goto free_vmcs;
8842         }
8843
8844         if (nested) {
8845                 nested_vmx_setup_ctls_msrs(vmx);
8846                 vmx->nested.vpid02 = allocate_vpid();
8847         }
8848
8849         vmx->nested.posted_intr_nv = -1;
8850         vmx->nested.current_vmptr = -1ull;
8851         vmx->nested.current_vmcs12 = NULL;
8852
8853         /*
8854          * If PML is turned on, failure on enabling PML just results in failure
8855          * of creating the vcpu, therefore we can simplify PML logic (by
8856          * avoiding dealing with cases, such as enabling PML partially on vcpus
8857          * for the guest, etc.
8858          */
8859         if (enable_pml) {
8860                 err = vmx_create_pml_buffer(vmx);
8861                 if (err)
8862                         goto free_vmcs;
8863         }
8864
8865         return &vmx->vcpu;
8866
8867 free_vmcs:
8868         free_vpid(vmx->nested.vpid02);
8869         free_loaded_vmcs(vmx->loaded_vmcs);
8870 free_msrs:
8871         kfree(vmx->guest_msrs);
8872 uninit_vcpu:
8873         kvm_vcpu_uninit(&vmx->vcpu);
8874 free_vcpu:
8875         free_vpid(vmx->vpid);
8876         kmem_cache_free(kvm_vcpu_cache, vmx);
8877         return ERR_PTR(err);
8878 }
8879
8880 static void __init vmx_check_processor_compat(void *rtn)
8881 {
8882         struct vmcs_config vmcs_conf;
8883
8884         *(int *)rtn = 0;
8885         if (setup_vmcs_config(&vmcs_conf) < 0)
8886                 *(int *)rtn = -EIO;
8887         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8888                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8889                                 smp_processor_id());
8890                 *(int *)rtn = -EIO;
8891         }
8892 }
8893
8894 static int get_ept_level(void)
8895 {
8896         return VMX_EPT_DEFAULT_GAW + 1;
8897 }
8898
8899 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8900 {
8901         u8 cache;
8902         u64 ipat = 0;
8903
8904         /* For VT-d and EPT combination
8905          * 1. MMIO: always map as UC
8906          * 2. EPT with VT-d:
8907          *   a. VT-d without snooping control feature: can't guarantee the
8908          *      result, try to trust guest.
8909          *   b. VT-d with snooping control feature: snooping control feature of
8910          *      VT-d engine can guarantee the cache correctness. Just set it
8911          *      to WB to keep consistent with host. So the same as item 3.
8912          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8913          *    consistent with host MTRR
8914          */
8915         if (is_mmio) {
8916                 cache = MTRR_TYPE_UNCACHABLE;
8917                 goto exit;
8918         }
8919
8920         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8921                 ipat = VMX_EPT_IPAT_BIT;
8922                 cache = MTRR_TYPE_WRBACK;
8923                 goto exit;
8924         }
8925
8926         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8927                 ipat = VMX_EPT_IPAT_BIT;
8928                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8929                         cache = MTRR_TYPE_WRBACK;
8930                 else
8931                         cache = MTRR_TYPE_UNCACHABLE;
8932                 goto exit;
8933         }
8934
8935         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8936
8937 exit:
8938         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8939 }
8940
8941 static int vmx_get_lpage_level(void)
8942 {
8943         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8944                 return PT_DIRECTORY_LEVEL;
8945         else
8946                 /* For shadow and EPT supported 1GB page */
8947                 return PT_PDPE_LEVEL;
8948 }
8949
8950 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8951 {
8952         /*
8953          * These bits in the secondary execution controls field
8954          * are dynamic, the others are mostly based on the hypervisor
8955          * architecture and the guest's CPUID.  Do not touch the
8956          * dynamic bits.
8957          */
8958         u32 mask =
8959                 SECONDARY_EXEC_SHADOW_VMCS |
8960                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8961                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8962
8963         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8964
8965         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8966                      (new_ctl & ~mask) | (cur_ctl & mask));
8967 }
8968
8969 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8970 {
8971         struct kvm_cpuid_entry2 *best;
8972         struct vcpu_vmx *vmx = to_vmx(vcpu);
8973         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8974
8975         if (vmx_rdtscp_supported()) {
8976                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8977                 if (!rdtscp_enabled)
8978                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8979
8980                 if (nested) {
8981                         if (rdtscp_enabled)
8982                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8983                                         SECONDARY_EXEC_RDTSCP;
8984                         else
8985                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8986                                         ~SECONDARY_EXEC_RDTSCP;
8987                 }
8988         }
8989
8990         /* Exposing INVPCID only when PCID is exposed */
8991         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8992         if (vmx_invpcid_supported() &&
8993             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8994             !guest_cpuid_has_pcid(vcpu))) {
8995                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8996
8997                 if (best)
8998                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8999         }
9000
9001         if (cpu_has_secondary_exec_ctrls())
9002                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9003
9004         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9005                 if (guest_cpuid_has_pcommit(vcpu))
9006                         vmx->nested.nested_vmx_secondary_ctls_high |=
9007                                 SECONDARY_EXEC_PCOMMIT;
9008                 else
9009                         vmx->nested.nested_vmx_secondary_ctls_high &=
9010                                 ~SECONDARY_EXEC_PCOMMIT;
9011         }
9012 }
9013
9014 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9015 {
9016         if (func == 1 && nested)
9017                 entry->ecx |= bit(X86_FEATURE_VMX);
9018 }
9019
9020 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9021                 struct x86_exception *fault)
9022 {
9023         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9024         u32 exit_reason;
9025
9026         if (fault->error_code & PFERR_RSVD_MASK)
9027                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9028         else
9029                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9030         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9031         vmcs12->guest_physical_address = fault->address;
9032 }
9033
9034 /* Callbacks for nested_ept_init_mmu_context: */
9035
9036 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9037 {
9038         /* return the page table to be shadowed - in our case, EPT12 */
9039         return get_vmcs12(vcpu)->ept_pointer;
9040 }
9041
9042 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9043 {
9044         WARN_ON(mmu_is_nested(vcpu));
9045         kvm_init_shadow_ept_mmu(vcpu,
9046                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9047                         VMX_EPT_EXECUTE_ONLY_BIT);
9048         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9049         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9050         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9051
9052         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9053 }
9054
9055 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9056 {
9057         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9058 }
9059
9060 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9061                                             u16 error_code)
9062 {
9063         bool inequality, bit;
9064
9065         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9066         inequality =
9067                 (error_code & vmcs12->page_fault_error_code_mask) !=
9068                  vmcs12->page_fault_error_code_match;
9069         return inequality ^ bit;
9070 }
9071
9072 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9073                 struct x86_exception *fault)
9074 {
9075         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9076
9077         WARN_ON(!is_guest_mode(vcpu));
9078
9079         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9080                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9081                                   vmcs_read32(VM_EXIT_INTR_INFO),
9082                                   vmcs_readl(EXIT_QUALIFICATION));
9083         else
9084                 kvm_inject_page_fault(vcpu, fault);
9085 }
9086
9087 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9088                                         struct vmcs12 *vmcs12)
9089 {
9090         struct vcpu_vmx *vmx = to_vmx(vcpu);
9091         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9092
9093         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9094                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9095                     vmcs12->apic_access_addr >> maxphyaddr)
9096                         return false;
9097
9098                 /*
9099                  * Translate L1 physical address to host physical
9100                  * address for vmcs02. Keep the page pinned, so this
9101                  * physical address remains valid. We keep a reference
9102                  * to it so we can release it later.
9103                  */
9104                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9105                         nested_release_page(vmx->nested.apic_access_page);
9106                 vmx->nested.apic_access_page =
9107                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9108         }
9109
9110         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9111                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9112                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9113                         return false;
9114
9115                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9116                         nested_release_page(vmx->nested.virtual_apic_page);
9117                 vmx->nested.virtual_apic_page =
9118                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9119
9120                 /*
9121                  * Failing the vm entry is _not_ what the processor does
9122                  * but it's basically the only possibility we have.
9123                  * We could still enter the guest if CR8 load exits are
9124                  * enabled, CR8 store exits are enabled, and virtualize APIC
9125                  * access is disabled; in this case the processor would never
9126                  * use the TPR shadow and we could simply clear the bit from
9127                  * the execution control.  But such a configuration is useless,
9128                  * so let's keep the code simple.
9129                  */
9130                 if (!vmx->nested.virtual_apic_page)
9131                         return false;
9132         }
9133
9134         if (nested_cpu_has_posted_intr(vmcs12)) {
9135                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9136                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9137                         return false;
9138
9139                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9140                         kunmap(vmx->nested.pi_desc_page);
9141                         nested_release_page(vmx->nested.pi_desc_page);
9142                 }
9143                 vmx->nested.pi_desc_page =
9144                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9145                 if (!vmx->nested.pi_desc_page)
9146                         return false;
9147
9148                 vmx->nested.pi_desc =
9149                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9150                 if (!vmx->nested.pi_desc) {
9151                         nested_release_page_clean(vmx->nested.pi_desc_page);
9152                         return false;
9153                 }
9154                 vmx->nested.pi_desc =
9155                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9156                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9157                         (PAGE_SIZE - 1)));
9158         }
9159
9160         return true;
9161 }
9162
9163 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9164 {
9165         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9166         struct vcpu_vmx *vmx = to_vmx(vcpu);
9167
9168         if (vcpu->arch.virtual_tsc_khz == 0)
9169                 return;
9170
9171         /* Make sure short timeouts reliably trigger an immediate vmexit.
9172          * hrtimer_start does not guarantee this. */
9173         if (preemption_timeout <= 1) {
9174                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9175                 return;
9176         }
9177
9178         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9179         preemption_timeout *= 1000000;
9180         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9181         hrtimer_start(&vmx->nested.preemption_timer,
9182                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9183 }
9184
9185 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9186                                                 struct vmcs12 *vmcs12)
9187 {
9188         int maxphyaddr;
9189         u64 addr;
9190
9191         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9192                 return 0;
9193
9194         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9195                 WARN_ON(1);
9196                 return -EINVAL;
9197         }
9198         maxphyaddr = cpuid_maxphyaddr(vcpu);
9199
9200         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9201            ((addr + PAGE_SIZE) >> maxphyaddr))
9202                 return -EINVAL;
9203
9204         return 0;
9205 }
9206
9207 /*
9208  * Merge L0's and L1's MSR bitmap, return false to indicate that
9209  * we do not use the hardware.
9210  */
9211 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9212                                                struct vmcs12 *vmcs12)
9213 {
9214         int msr;
9215         struct page *page;
9216         unsigned long *msr_bitmap;
9217
9218         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9219                 return false;
9220
9221         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9222         if (!page) {
9223                 WARN_ON(1);
9224                 return false;
9225         }
9226         msr_bitmap = (unsigned long *)kmap(page);
9227         if (!msr_bitmap) {
9228                 nested_release_page_clean(page);
9229                 WARN_ON(1);
9230                 return false;
9231         }
9232
9233         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9234                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9235                         for (msr = 0x800; msr <= 0x8ff; msr++)
9236                                 nested_vmx_disable_intercept_for_msr(
9237                                         msr_bitmap,
9238                                         vmx_msr_bitmap_nested,
9239                                         msr, MSR_TYPE_R);
9240                 /* TPR is allowed */
9241                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9242                                 vmx_msr_bitmap_nested,
9243                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9244                                 MSR_TYPE_R | MSR_TYPE_W);
9245                 if (nested_cpu_has_vid(vmcs12)) {
9246                         /* EOI and self-IPI are allowed */
9247                         nested_vmx_disable_intercept_for_msr(
9248                                 msr_bitmap,
9249                                 vmx_msr_bitmap_nested,
9250                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9251                                 MSR_TYPE_W);
9252                         nested_vmx_disable_intercept_for_msr(
9253                                 msr_bitmap,
9254                                 vmx_msr_bitmap_nested,
9255                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9256                                 MSR_TYPE_W);
9257                 }
9258         } else {
9259                 /*
9260                  * Enable reading intercept of all the x2apic
9261                  * MSRs. We should not rely on vmcs12 to do any
9262                  * optimizations here, it may have been modified
9263                  * by L1.
9264                  */
9265                 for (msr = 0x800; msr <= 0x8ff; msr++)
9266                         __vmx_enable_intercept_for_msr(
9267                                 vmx_msr_bitmap_nested,
9268                                 msr,
9269                                 MSR_TYPE_R);
9270
9271                 __vmx_enable_intercept_for_msr(
9272                                 vmx_msr_bitmap_nested,
9273                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9274                                 MSR_TYPE_W);
9275                 __vmx_enable_intercept_for_msr(
9276                                 vmx_msr_bitmap_nested,
9277                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9278                                 MSR_TYPE_W);
9279                 __vmx_enable_intercept_for_msr(
9280                                 vmx_msr_bitmap_nested,
9281                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9282                                 MSR_TYPE_W);
9283         }
9284         kunmap(page);
9285         nested_release_page_clean(page);
9286
9287         return true;
9288 }
9289
9290 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9291                                            struct vmcs12 *vmcs12)
9292 {
9293         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9294             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9295             !nested_cpu_has_vid(vmcs12) &&
9296             !nested_cpu_has_posted_intr(vmcs12))
9297                 return 0;
9298
9299         /*
9300          * If virtualize x2apic mode is enabled,
9301          * virtualize apic access must be disabled.
9302          */
9303         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9304             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9305                 return -EINVAL;
9306
9307         /*
9308          * If virtual interrupt delivery is enabled,
9309          * we must exit on external interrupts.
9310          */
9311         if (nested_cpu_has_vid(vmcs12) &&
9312            !nested_exit_on_intr(vcpu))
9313                 return -EINVAL;
9314
9315         /*
9316          * bits 15:8 should be zero in posted_intr_nv,
9317          * the descriptor address has been already checked
9318          * in nested_get_vmcs12_pages.
9319          */
9320         if (nested_cpu_has_posted_intr(vmcs12) &&
9321            (!nested_cpu_has_vid(vmcs12) ||
9322             !nested_exit_intr_ack_set(vcpu) ||
9323             vmcs12->posted_intr_nv & 0xff00))
9324                 return -EINVAL;
9325
9326         /* tpr shadow is needed by all apicv features. */
9327         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9328                 return -EINVAL;
9329
9330         return 0;
9331 }
9332
9333 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9334                                        unsigned long count_field,
9335                                        unsigned long addr_field)
9336 {
9337         int maxphyaddr;
9338         u64 count, addr;
9339
9340         if (vmcs12_read_any(vcpu, count_field, &count) ||
9341             vmcs12_read_any(vcpu, addr_field, &addr)) {
9342                 WARN_ON(1);
9343                 return -EINVAL;
9344         }
9345         if (count == 0)
9346                 return 0;
9347         maxphyaddr = cpuid_maxphyaddr(vcpu);
9348         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9349             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9350                 pr_warn_ratelimited(
9351                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9352                         addr_field, maxphyaddr, count, addr);
9353                 return -EINVAL;
9354         }
9355         return 0;
9356 }
9357
9358 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9359                                                 struct vmcs12 *vmcs12)
9360 {
9361         if (vmcs12->vm_exit_msr_load_count == 0 &&
9362             vmcs12->vm_exit_msr_store_count == 0 &&
9363             vmcs12->vm_entry_msr_load_count == 0)
9364                 return 0; /* Fast path */
9365         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9366                                         VM_EXIT_MSR_LOAD_ADDR) ||
9367             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9368                                         VM_EXIT_MSR_STORE_ADDR) ||
9369             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9370                                         VM_ENTRY_MSR_LOAD_ADDR))
9371                 return -EINVAL;
9372         return 0;
9373 }
9374
9375 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9376                                        struct vmx_msr_entry *e)
9377 {
9378         /* x2APIC MSR accesses are not allowed */
9379         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9380                 return -EINVAL;
9381         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9382             e->index == MSR_IA32_UCODE_REV)
9383                 return -EINVAL;
9384         if (e->reserved != 0)
9385                 return -EINVAL;
9386         return 0;
9387 }
9388
9389 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9390                                      struct vmx_msr_entry *e)
9391 {
9392         if (e->index == MSR_FS_BASE ||
9393             e->index == MSR_GS_BASE ||
9394             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9395             nested_vmx_msr_check_common(vcpu, e))
9396                 return -EINVAL;
9397         return 0;
9398 }
9399
9400 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9401                                       struct vmx_msr_entry *e)
9402 {
9403         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9404             nested_vmx_msr_check_common(vcpu, e))
9405                 return -EINVAL;
9406         return 0;
9407 }
9408
9409 /*
9410  * Load guest's/host's msr at nested entry/exit.
9411  * return 0 for success, entry index for failure.
9412  */
9413 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9414 {
9415         u32 i;
9416         struct vmx_msr_entry e;
9417         struct msr_data msr;
9418
9419         msr.host_initiated = false;
9420         for (i = 0; i < count; i++) {
9421                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9422                                         &e, sizeof(e))) {
9423                         pr_warn_ratelimited(
9424                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9425                                 __func__, i, gpa + i * sizeof(e));
9426                         goto fail;
9427                 }
9428                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9429                         pr_warn_ratelimited(
9430                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9431                                 __func__, i, e.index, e.reserved);
9432                         goto fail;
9433                 }
9434                 msr.index = e.index;
9435                 msr.data = e.value;
9436                 if (kvm_set_msr(vcpu, &msr)) {
9437                         pr_warn_ratelimited(
9438                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9439                                 __func__, i, e.index, e.value);
9440                         goto fail;
9441                 }
9442         }
9443         return 0;
9444 fail:
9445         return i + 1;
9446 }
9447
9448 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9449 {
9450         u32 i;
9451         struct vmx_msr_entry e;
9452
9453         for (i = 0; i < count; i++) {
9454                 struct msr_data msr_info;
9455                 if (kvm_vcpu_read_guest(vcpu,
9456                                         gpa + i * sizeof(e),
9457                                         &e, 2 * sizeof(u32))) {
9458                         pr_warn_ratelimited(
9459                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9460                                 __func__, i, gpa + i * sizeof(e));
9461                         return -EINVAL;
9462                 }
9463                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9464                         pr_warn_ratelimited(
9465                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9466                                 __func__, i, e.index, e.reserved);
9467                         return -EINVAL;
9468                 }
9469                 msr_info.host_initiated = false;
9470                 msr_info.index = e.index;
9471                 if (kvm_get_msr(vcpu, &msr_info)) {
9472                         pr_warn_ratelimited(
9473                                 "%s cannot read MSR (%u, 0x%x)\n",
9474                                 __func__, i, e.index);
9475                         return -EINVAL;
9476                 }
9477                 if (kvm_vcpu_write_guest(vcpu,
9478                                          gpa + i * sizeof(e) +
9479                                              offsetof(struct vmx_msr_entry, value),
9480                                          &msr_info.data, sizeof(msr_info.data))) {
9481                         pr_warn_ratelimited(
9482                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9483                                 __func__, i, e.index, msr_info.data);
9484                         return -EINVAL;
9485                 }
9486         }
9487         return 0;
9488 }
9489
9490 /*
9491  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9492  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9493  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9494  * guest in a way that will both be appropriate to L1's requests, and our
9495  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9496  * function also has additional necessary side-effects, like setting various
9497  * vcpu->arch fields.
9498  */
9499 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9500 {
9501         struct vcpu_vmx *vmx = to_vmx(vcpu);
9502         u32 exec_control;
9503
9504         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9505         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9506         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9507         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9508         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9509         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9510         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9511         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9512         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9513         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9514         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9515         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9516         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9517         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9518         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9519         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9520         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9521         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9522         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9523         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9524         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9525         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9526         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9527         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9528         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9529         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9530         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9531         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9532         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9533         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9534         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9535         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9536         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9537         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9538         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9539         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9540
9541         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9542                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9543                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9544         } else {
9545                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9546                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9547         }
9548         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9549                 vmcs12->vm_entry_intr_info_field);
9550         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9551                 vmcs12->vm_entry_exception_error_code);
9552         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9553                 vmcs12->vm_entry_instruction_len);
9554         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9555                 vmcs12->guest_interruptibility_info);
9556         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9557         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9558         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9559                 vmcs12->guest_pending_dbg_exceptions);
9560         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9561         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9562
9563         if (nested_cpu_has_xsaves(vmcs12))
9564                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9565         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9566
9567         exec_control = vmcs12->pin_based_vm_exec_control;
9568         exec_control |= vmcs_config.pin_based_exec_ctrl;
9569         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9570
9571         if (nested_cpu_has_posted_intr(vmcs12)) {
9572                 /*
9573                  * Note that we use L0's vector here and in
9574                  * vmx_deliver_nested_posted_interrupt.
9575                  */
9576                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9577                 vmx->nested.pi_pending = false;
9578                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9579                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9580                         page_to_phys(vmx->nested.pi_desc_page) +
9581                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9582                         (PAGE_SIZE - 1)));
9583         } else
9584                 exec_control &= ~PIN_BASED_POSTED_INTR;
9585
9586         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9587
9588         vmx->nested.preemption_timer_expired = false;
9589         if (nested_cpu_has_preemption_timer(vmcs12))
9590                 vmx_start_preemption_timer(vcpu);
9591
9592         /*
9593          * Whether page-faults are trapped is determined by a combination of
9594          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9595          * If enable_ept, L0 doesn't care about page faults and we should
9596          * set all of these to L1's desires. However, if !enable_ept, L0 does
9597          * care about (at least some) page faults, and because it is not easy
9598          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9599          * to exit on each and every L2 page fault. This is done by setting
9600          * MASK=MATCH=0 and (see below) EB.PF=1.
9601          * Note that below we don't need special code to set EB.PF beyond the
9602          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9603          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9604          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9605          *
9606          * A problem with this approach (when !enable_ept) is that L1 may be
9607          * injected with more page faults than it asked for. This could have
9608          * caused problems, but in practice existing hypervisors don't care.
9609          * To fix this, we will need to emulate the PFEC checking (on the L1
9610          * page tables), using walk_addr(), when injecting PFs to L1.
9611          */
9612         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9613                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9614         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9615                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9616
9617         if (cpu_has_secondary_exec_ctrls()) {
9618                 exec_control = vmx_secondary_exec_control(vmx);
9619
9620                 /* Take the following fields only from vmcs12 */
9621                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9622                                   SECONDARY_EXEC_RDTSCP |
9623                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9624                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9625                                   SECONDARY_EXEC_PCOMMIT);
9626                 if (nested_cpu_has(vmcs12,
9627                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9628                         exec_control |= vmcs12->secondary_vm_exec_control;
9629
9630                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9631                         /*
9632                          * If translation failed, no matter: This feature asks
9633                          * to exit when accessing the given address, and if it
9634                          * can never be accessed, this feature won't do
9635                          * anything anyway.
9636                          */
9637                         if (!vmx->nested.apic_access_page)
9638                                 exec_control &=
9639                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9640                         else
9641                                 vmcs_write64(APIC_ACCESS_ADDR,
9642                                   page_to_phys(vmx->nested.apic_access_page));
9643                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9644                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9645                         exec_control |=
9646                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9647                         kvm_vcpu_reload_apic_access_page(vcpu);
9648                 }
9649
9650                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9651                         vmcs_write64(EOI_EXIT_BITMAP0,
9652                                 vmcs12->eoi_exit_bitmap0);
9653                         vmcs_write64(EOI_EXIT_BITMAP1,
9654                                 vmcs12->eoi_exit_bitmap1);
9655                         vmcs_write64(EOI_EXIT_BITMAP2,
9656                                 vmcs12->eoi_exit_bitmap2);
9657                         vmcs_write64(EOI_EXIT_BITMAP3,
9658                                 vmcs12->eoi_exit_bitmap3);
9659                         vmcs_write16(GUEST_INTR_STATUS,
9660                                 vmcs12->guest_intr_status);
9661                 }
9662
9663                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9664         }
9665
9666
9667         /*
9668          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9669          * Some constant fields are set here by vmx_set_constant_host_state().
9670          * Other fields are different per CPU, and will be set later when
9671          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9672          */
9673         vmx_set_constant_host_state(vmx);
9674
9675         /*
9676          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9677          * entry, but only if the current (host) sp changed from the value
9678          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9679          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9680          * here we just force the write to happen on entry.
9681          */
9682         vmx->host_rsp = 0;
9683
9684         exec_control = vmx_exec_control(vmx); /* L0's desires */
9685         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9686         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9687         exec_control &= ~CPU_BASED_TPR_SHADOW;
9688         exec_control |= vmcs12->cpu_based_vm_exec_control;
9689
9690         if (exec_control & CPU_BASED_TPR_SHADOW) {
9691                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9692                                 page_to_phys(vmx->nested.virtual_apic_page));
9693                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9694         }
9695
9696         if (cpu_has_vmx_msr_bitmap() &&
9697             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9698                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9699                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9700         } else
9701                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9702
9703         /*
9704          * Merging of IO bitmap not currently supported.
9705          * Rather, exit every time.
9706          */
9707         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9708         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9709
9710         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9711
9712         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9713          * bitwise-or of what L1 wants to trap for L2, and what we want to
9714          * trap. Note that CR0.TS also needs updating - we do this later.
9715          */
9716         update_exception_bitmap(vcpu);
9717         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9718         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9719
9720         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9721          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9722          * bits are further modified by vmx_set_efer() below.
9723          */
9724         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9725
9726         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9727          * emulated by vmx_set_efer(), below.
9728          */
9729         vm_entry_controls_init(vmx,
9730                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9731                         ~VM_ENTRY_IA32E_MODE) |
9732                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9733
9734         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9735                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9736                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9737         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9738                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9739
9740
9741         set_cr4_guest_host_mask(vmx);
9742
9743         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9744                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9745
9746         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9747                 vmcs_write64(TSC_OFFSET,
9748                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9749         else
9750                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9751
9752         if (enable_vpid) {
9753                 /*
9754                  * There is no direct mapping between vpid02 and vpid12, the
9755                  * vpid02 is per-vCPU for L0 and reused while the value of
9756                  * vpid12 is changed w/ one invvpid during nested vmentry.
9757                  * The vpid12 is allocated by L1 for L2, so it will not
9758                  * influence global bitmap(for vpid01 and vpid02 allocation)
9759                  * even if spawn a lot of nested vCPUs.
9760                  */
9761                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9762                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9763                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9764                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9765                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9766                         }
9767                 } else {
9768                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9769                         vmx_flush_tlb(vcpu);
9770                 }
9771
9772         }
9773
9774         if (nested_cpu_has_ept(vmcs12)) {
9775                 kvm_mmu_unload(vcpu);
9776                 nested_ept_init_mmu_context(vcpu);
9777         }
9778
9779         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9780                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9781         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9782                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9783         else
9784                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9785         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9786         vmx_set_efer(vcpu, vcpu->arch.efer);
9787
9788         /*
9789          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9790          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9791          * The CR0_READ_SHADOW is what L2 should have expected to read given
9792          * the specifications by L1; It's not enough to take
9793          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9794          * have more bits than L1 expected.
9795          */
9796         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9797         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9798
9799         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9800         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9801
9802         /* shadow page tables on either EPT or shadow page tables */
9803         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9804         kvm_mmu_reset_context(vcpu);
9805
9806         if (!enable_ept)
9807                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9808
9809         /*
9810          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9811          */
9812         if (enable_ept) {
9813                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9814                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9815                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9816                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9817         }
9818
9819         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9820         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9821 }
9822
9823 /*
9824  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9825  * for running an L2 nested guest.
9826  */
9827 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9828 {
9829         struct vmcs12 *vmcs12;
9830         struct vcpu_vmx *vmx = to_vmx(vcpu);
9831         int cpu;
9832         struct loaded_vmcs *vmcs02;
9833         bool ia32e;
9834         u32 msr_entry_idx;
9835
9836         if (!nested_vmx_check_permission(vcpu) ||
9837             !nested_vmx_check_vmcs12(vcpu))
9838                 return 1;
9839
9840         skip_emulated_instruction(vcpu);
9841         vmcs12 = get_vmcs12(vcpu);
9842
9843         if (enable_shadow_vmcs)
9844                 copy_shadow_to_vmcs12(vmx);
9845
9846         /*
9847          * The nested entry process starts with enforcing various prerequisites
9848          * on vmcs12 as required by the Intel SDM, and act appropriately when
9849          * they fail: As the SDM explains, some conditions should cause the
9850          * instruction to fail, while others will cause the instruction to seem
9851          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9852          * To speed up the normal (success) code path, we should avoid checking
9853          * for misconfigurations which will anyway be caught by the processor
9854          * when using the merged vmcs02.
9855          */
9856         if (vmcs12->launch_state == launch) {
9857                 nested_vmx_failValid(vcpu,
9858                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9859                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9860                 return 1;
9861         }
9862
9863         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9864             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9865                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9866                 return 1;
9867         }
9868
9869         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9870                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9871                 return 1;
9872         }
9873
9874         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9875                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9876                 return 1;
9877         }
9878
9879         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9880                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9881                 return 1;
9882         }
9883
9884         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9885                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9886                 return 1;
9887         }
9888
9889         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9890                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9891                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9892             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9893                                 vmx->nested.nested_vmx_secondary_ctls_low,
9894                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9895             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9896                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9897                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9898             !vmx_control_verify(vmcs12->vm_exit_controls,
9899                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9900                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9901             !vmx_control_verify(vmcs12->vm_entry_controls,
9902                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9903                                 vmx->nested.nested_vmx_entry_ctls_high))
9904         {
9905                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9906                 return 1;
9907         }
9908
9909         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9910             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9911                 nested_vmx_failValid(vcpu,
9912                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9913                 return 1;
9914         }
9915
9916         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9917             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9918                 nested_vmx_entry_failure(vcpu, vmcs12,
9919                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9920                 return 1;
9921         }
9922         if (vmcs12->vmcs_link_pointer != -1ull) {
9923                 nested_vmx_entry_failure(vcpu, vmcs12,
9924                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9925                 return 1;
9926         }
9927
9928         /*
9929          * If the load IA32_EFER VM-entry control is 1, the following checks
9930          * are performed on the field for the IA32_EFER MSR:
9931          * - Bits reserved in the IA32_EFER MSR must be 0.
9932          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9933          *   the IA-32e mode guest VM-exit control. It must also be identical
9934          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9935          *   CR0.PG) is 1.
9936          */
9937         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9938                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9939                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9940                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9941                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9942                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9943                         nested_vmx_entry_failure(vcpu, vmcs12,
9944                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9945                         return 1;
9946                 }
9947         }
9948
9949         /*
9950          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9951          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9952          * the values of the LMA and LME bits in the field must each be that of
9953          * the host address-space size VM-exit control.
9954          */
9955         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9956                 ia32e = (vmcs12->vm_exit_controls &
9957                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9958                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9959                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9960                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9961                         nested_vmx_entry_failure(vcpu, vmcs12,
9962                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9963                         return 1;
9964                 }
9965         }
9966
9967         /*
9968          * We're finally done with prerequisite checking, and can start with
9969          * the nested entry.
9970          */
9971
9972         vmcs02 = nested_get_current_vmcs02(vmx);
9973         if (!vmcs02)
9974                 return -ENOMEM;
9975
9976         enter_guest_mode(vcpu);
9977
9978         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9979
9980         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9981                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9982
9983         cpu = get_cpu();
9984         vmx->loaded_vmcs = vmcs02;
9985         vmx_vcpu_put(vcpu);
9986         vmx_vcpu_load(vcpu, cpu);
9987         vcpu->cpu = cpu;
9988         put_cpu();
9989
9990         vmx_segment_cache_clear(vmx);
9991
9992         prepare_vmcs02(vcpu, vmcs12);
9993
9994         msr_entry_idx = nested_vmx_load_msr(vcpu,
9995                                             vmcs12->vm_entry_msr_load_addr,
9996                                             vmcs12->vm_entry_msr_load_count);
9997         if (msr_entry_idx) {
9998                 leave_guest_mode(vcpu);
9999                 vmx_load_vmcs01(vcpu);
10000                 nested_vmx_entry_failure(vcpu, vmcs12,
10001                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10002                 return 1;
10003         }
10004
10005         vmcs12->launch_state = 1;
10006
10007         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10008                 return kvm_vcpu_halt(vcpu);
10009
10010         vmx->nested.nested_run_pending = 1;
10011
10012         /*
10013          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10014          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10015          * returned as far as L1 is concerned. It will only return (and set
10016          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10017          */
10018         return 1;
10019 }
10020
10021 /*
10022  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10023  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10024  * This function returns the new value we should put in vmcs12.guest_cr0.
10025  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10026  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10027  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10028  *     didn't trap the bit, because if L1 did, so would L0).
10029  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10030  *     been modified by L2, and L1 knows it. So just leave the old value of
10031  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10032  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10033  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10034  *     changed these bits, and therefore they need to be updated, but L0
10035  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10036  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10037  */
10038 static inline unsigned long
10039 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10040 {
10041         return
10042         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10043         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10044         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10045                         vcpu->arch.cr0_guest_owned_bits));
10046 }
10047
10048 static inline unsigned long
10049 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10050 {
10051         return
10052         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10053         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10054         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10055                         vcpu->arch.cr4_guest_owned_bits));
10056 }
10057
10058 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10059                                        struct vmcs12 *vmcs12)
10060 {
10061         u32 idt_vectoring;
10062         unsigned int nr;
10063
10064         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10065                 nr = vcpu->arch.exception.nr;
10066                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10067
10068                 if (kvm_exception_is_soft(nr)) {
10069                         vmcs12->vm_exit_instruction_len =
10070                                 vcpu->arch.event_exit_inst_len;
10071                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10072                 } else
10073                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10074
10075                 if (vcpu->arch.exception.has_error_code) {
10076                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10077                         vmcs12->idt_vectoring_error_code =
10078                                 vcpu->arch.exception.error_code;
10079                 }
10080
10081                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10082         } else if (vcpu->arch.nmi_injected) {
10083                 vmcs12->idt_vectoring_info_field =
10084                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10085         } else if (vcpu->arch.interrupt.pending) {
10086                 nr = vcpu->arch.interrupt.nr;
10087                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10088
10089                 if (vcpu->arch.interrupt.soft) {
10090                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10091                         vmcs12->vm_entry_instruction_len =
10092                                 vcpu->arch.event_exit_inst_len;
10093                 } else
10094                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10095
10096                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10097         }
10098 }
10099
10100 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10101 {
10102         struct vcpu_vmx *vmx = to_vmx(vcpu);
10103
10104         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10105             vmx->nested.preemption_timer_expired) {
10106                 if (vmx->nested.nested_run_pending)
10107                         return -EBUSY;
10108                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10109                 return 0;
10110         }
10111
10112         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10113                 if (vmx->nested.nested_run_pending ||
10114                     vcpu->arch.interrupt.pending)
10115                         return -EBUSY;
10116                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10117                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10118                                   INTR_INFO_VALID_MASK, 0);
10119                 /*
10120                  * The NMI-triggered VM exit counts as injection:
10121                  * clear this one and block further NMIs.
10122                  */
10123                 vcpu->arch.nmi_pending = 0;
10124                 vmx_set_nmi_mask(vcpu, true);
10125                 return 0;
10126         }
10127
10128         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10129             nested_exit_on_intr(vcpu)) {
10130                 if (vmx->nested.nested_run_pending)
10131                         return -EBUSY;
10132                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10133                 return 0;
10134         }
10135
10136         return vmx_complete_nested_posted_interrupt(vcpu);
10137 }
10138
10139 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10140 {
10141         ktime_t remaining =
10142                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10143         u64 value;
10144
10145         if (ktime_to_ns(remaining) <= 0)
10146                 return 0;
10147
10148         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10149         do_div(value, 1000000);
10150         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10151 }
10152
10153 /*
10154  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10155  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10156  * and this function updates it to reflect the changes to the guest state while
10157  * L2 was running (and perhaps made some exits which were handled directly by L0
10158  * without going back to L1), and to reflect the exit reason.
10159  * Note that we do not have to copy here all VMCS fields, just those that
10160  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10161  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10162  * which already writes to vmcs12 directly.
10163  */
10164 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10165                            u32 exit_reason, u32 exit_intr_info,
10166                            unsigned long exit_qualification)
10167 {
10168         /* update guest state fields: */
10169         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10170         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10171
10172         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10173         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10174         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10175
10176         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10177         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10178         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10179         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10180         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10181         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10182         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10183         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10184         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10185         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10186         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10187         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10188         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10189         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10190         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10191         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10192         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10193         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10194         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10195         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10196         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10197         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10198         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10199         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10200         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10201         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10202         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10203         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10204         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10205         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10206         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10207         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10208         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10209         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10210         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10211         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10212
10213         vmcs12->guest_interruptibility_info =
10214                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10215         vmcs12->guest_pending_dbg_exceptions =
10216                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10217         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10218                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10219         else
10220                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10221
10222         if (nested_cpu_has_preemption_timer(vmcs12)) {
10223                 if (vmcs12->vm_exit_controls &
10224                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10225                         vmcs12->vmx_preemption_timer_value =
10226                                 vmx_get_preemption_timer_value(vcpu);
10227                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10228         }
10229
10230         /*
10231          * In some cases (usually, nested EPT), L2 is allowed to change its
10232          * own CR3 without exiting. If it has changed it, we must keep it.
10233          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10234          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10235          *
10236          * Additionally, restore L2's PDPTR to vmcs12.
10237          */
10238         if (enable_ept) {
10239                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10240                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10241                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10242                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10243                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10244         }
10245
10246         if (nested_cpu_has_vid(vmcs12))
10247                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10248
10249         vmcs12->vm_entry_controls =
10250                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10251                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10252
10253         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10254                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10255                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10256         }
10257
10258         /* TODO: These cannot have changed unless we have MSR bitmaps and
10259          * the relevant bit asks not to trap the change */
10260         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10261                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10262         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10263                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10264         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10265         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10266         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10267         if (kvm_mpx_supported())
10268                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10269         if (nested_cpu_has_xsaves(vmcs12))
10270                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10271
10272         /* update exit information fields: */
10273
10274         vmcs12->vm_exit_reason = exit_reason;
10275         vmcs12->exit_qualification = exit_qualification;
10276
10277         vmcs12->vm_exit_intr_info = exit_intr_info;
10278         if ((vmcs12->vm_exit_intr_info &
10279              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10280             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10281                 vmcs12->vm_exit_intr_error_code =
10282                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10283         vmcs12->idt_vectoring_info_field = 0;
10284         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10285         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10286
10287         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10288                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10289                  * instead of reading the real value. */
10290                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10291
10292                 /*
10293                  * Transfer the event that L0 or L1 may wanted to inject into
10294                  * L2 to IDT_VECTORING_INFO_FIELD.
10295                  */
10296                 vmcs12_save_pending_event(vcpu, vmcs12);
10297         }
10298
10299         /*
10300          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10301          * preserved above and would only end up incorrectly in L1.
10302          */
10303         vcpu->arch.nmi_injected = false;
10304         kvm_clear_exception_queue(vcpu);
10305         kvm_clear_interrupt_queue(vcpu);
10306 }
10307
10308 /*
10309  * A part of what we need to when the nested L2 guest exits and we want to
10310  * run its L1 parent, is to reset L1's guest state to the host state specified
10311  * in vmcs12.
10312  * This function is to be called not only on normal nested exit, but also on
10313  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10314  * Failures During or After Loading Guest State").
10315  * This function should be called when the active VMCS is L1's (vmcs01).
10316  */
10317 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10318                                    struct vmcs12 *vmcs12)
10319 {
10320         struct kvm_segment seg;
10321
10322         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10323                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10324         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10325                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10326         else
10327                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10328         vmx_set_efer(vcpu, vcpu->arch.efer);
10329
10330         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10331         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10332         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10333         /*
10334          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10335          * actually changed, because it depends on the current state of
10336          * fpu_active (which may have changed).
10337          * Note that vmx_set_cr0 refers to efer set above.
10338          */
10339         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10340         /*
10341          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10342          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10343          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10344          */
10345         update_exception_bitmap(vcpu);
10346         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10347         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10348
10349         /*
10350          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10351          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10352          */
10353         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10354         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10355
10356         nested_ept_uninit_mmu_context(vcpu);
10357
10358         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10359         kvm_mmu_reset_context(vcpu);
10360
10361         if (!enable_ept)
10362                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10363
10364         if (enable_vpid) {
10365                 /*
10366                  * Trivially support vpid by letting L2s share their parent
10367                  * L1's vpid. TODO: move to a more elaborate solution, giving
10368                  * each L2 its own vpid and exposing the vpid feature to L1.
10369                  */
10370                 vmx_flush_tlb(vcpu);
10371         }
10372
10373
10374         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10375         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10376         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10377         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10378         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10379
10380         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10381         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10382                 vmcs_write64(GUEST_BNDCFGS, 0);
10383
10384         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10385                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10386                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10387         }
10388         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10389                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10390                         vmcs12->host_ia32_perf_global_ctrl);
10391
10392         /* Set L1 segment info according to Intel SDM
10393             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10394         seg = (struct kvm_segment) {
10395                 .base = 0,
10396                 .limit = 0xFFFFFFFF,
10397                 .selector = vmcs12->host_cs_selector,
10398                 .type = 11,
10399                 .present = 1,
10400                 .s = 1,
10401                 .g = 1
10402         };
10403         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10404                 seg.l = 1;
10405         else
10406                 seg.db = 1;
10407         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10408         seg = (struct kvm_segment) {
10409                 .base = 0,
10410                 .limit = 0xFFFFFFFF,
10411                 .type = 3,
10412                 .present = 1,
10413                 .s = 1,
10414                 .db = 1,
10415                 .g = 1
10416         };
10417         seg.selector = vmcs12->host_ds_selector;
10418         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10419         seg.selector = vmcs12->host_es_selector;
10420         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10421         seg.selector = vmcs12->host_ss_selector;
10422         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10423         seg.selector = vmcs12->host_fs_selector;
10424         seg.base = vmcs12->host_fs_base;
10425         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10426         seg.selector = vmcs12->host_gs_selector;
10427         seg.base = vmcs12->host_gs_base;
10428         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10429         seg = (struct kvm_segment) {
10430                 .base = vmcs12->host_tr_base,
10431                 .limit = 0x67,
10432                 .selector = vmcs12->host_tr_selector,
10433                 .type = 11,
10434                 .present = 1
10435         };
10436         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10437
10438         kvm_set_dr(vcpu, 7, 0x400);
10439         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10440
10441         if (cpu_has_vmx_msr_bitmap())
10442                 vmx_set_msr_bitmap(vcpu);
10443
10444         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10445                                 vmcs12->vm_exit_msr_load_count))
10446                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10447 }
10448
10449 /*
10450  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10451  * and modify vmcs12 to make it see what it would expect to see there if
10452  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10453  */
10454 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10455                               u32 exit_intr_info,
10456                               unsigned long exit_qualification)
10457 {
10458         struct vcpu_vmx *vmx = to_vmx(vcpu);
10459         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10460
10461         /* trying to cancel vmlaunch/vmresume is a bug */
10462         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10463
10464         leave_guest_mode(vcpu);
10465         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10466                        exit_qualification);
10467
10468         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10469                                  vmcs12->vm_exit_msr_store_count))
10470                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10471
10472         vmx_load_vmcs01(vcpu);
10473
10474         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10475             && nested_exit_intr_ack_set(vcpu)) {
10476                 int irq = kvm_cpu_get_interrupt(vcpu);
10477                 WARN_ON(irq < 0);
10478                 vmcs12->vm_exit_intr_info = irq |
10479                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10480         }
10481
10482         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10483                                        vmcs12->exit_qualification,
10484                                        vmcs12->idt_vectoring_info_field,
10485                                        vmcs12->vm_exit_intr_info,
10486                                        vmcs12->vm_exit_intr_error_code,
10487                                        KVM_ISA_VMX);
10488
10489         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10490         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10491         vmx_segment_cache_clear(vmx);
10492
10493         /* if no vmcs02 cache requested, remove the one we used */
10494         if (VMCS02_POOL_SIZE == 0)
10495                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10496
10497         load_vmcs12_host_state(vcpu, vmcs12);
10498
10499         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10500         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10501
10502         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10503         vmx->host_rsp = 0;
10504
10505         /* Unpin physical memory we referred to in vmcs02 */
10506         if (vmx->nested.apic_access_page) {
10507                 nested_release_page(vmx->nested.apic_access_page);
10508                 vmx->nested.apic_access_page = NULL;
10509         }
10510         if (vmx->nested.virtual_apic_page) {
10511                 nested_release_page(vmx->nested.virtual_apic_page);
10512                 vmx->nested.virtual_apic_page = NULL;
10513         }
10514         if (vmx->nested.pi_desc_page) {
10515                 kunmap(vmx->nested.pi_desc_page);
10516                 nested_release_page(vmx->nested.pi_desc_page);
10517                 vmx->nested.pi_desc_page = NULL;
10518                 vmx->nested.pi_desc = NULL;
10519         }
10520
10521         /*
10522          * We are now running in L2, mmu_notifier will force to reload the
10523          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10524          */
10525         kvm_vcpu_reload_apic_access_page(vcpu);
10526
10527         /*
10528          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10529          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10530          * success or failure flag accordingly.
10531          */
10532         if (unlikely(vmx->fail)) {
10533                 vmx->fail = 0;
10534                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10535         } else
10536                 nested_vmx_succeed(vcpu);
10537         if (enable_shadow_vmcs)
10538                 vmx->nested.sync_shadow_vmcs = true;
10539
10540         /* in case we halted in L2 */
10541         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10542 }
10543
10544 /*
10545  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10546  */
10547 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10548 {
10549         if (is_guest_mode(vcpu))
10550                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10551         free_nested(to_vmx(vcpu));
10552 }
10553
10554 /*
10555  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10556  * 23.7 "VM-entry failures during or after loading guest state" (this also
10557  * lists the acceptable exit-reason and exit-qualification parameters).
10558  * It should only be called before L2 actually succeeded to run, and when
10559  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10560  */
10561 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10562                         struct vmcs12 *vmcs12,
10563                         u32 reason, unsigned long qualification)
10564 {
10565         load_vmcs12_host_state(vcpu, vmcs12);
10566         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10567         vmcs12->exit_qualification = qualification;
10568         nested_vmx_succeed(vcpu);
10569         if (enable_shadow_vmcs)
10570                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10571 }
10572
10573 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10574                                struct x86_instruction_info *info,
10575                                enum x86_intercept_stage stage)
10576 {
10577         return X86EMUL_CONTINUE;
10578 }
10579
10580 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10581 {
10582         if (ple_gap)
10583                 shrink_ple_window(vcpu);
10584 }
10585
10586 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10587                                      struct kvm_memory_slot *slot)
10588 {
10589         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10590         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10591 }
10592
10593 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10594                                        struct kvm_memory_slot *slot)
10595 {
10596         kvm_mmu_slot_set_dirty(kvm, slot);
10597 }
10598
10599 static void vmx_flush_log_dirty(struct kvm *kvm)
10600 {
10601         kvm_flush_pml_buffers(kvm);
10602 }
10603
10604 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10605                                            struct kvm_memory_slot *memslot,
10606                                            gfn_t offset, unsigned long mask)
10607 {
10608         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10609 }
10610
10611 /*
10612  * This routine does the following things for vCPU which is going
10613  * to be blocked if VT-d PI is enabled.
10614  * - Store the vCPU to the wakeup list, so when interrupts happen
10615  *   we can find the right vCPU to wake up.
10616  * - Change the Posted-interrupt descriptor as below:
10617  *      'NDST' <-- vcpu->pre_pcpu
10618  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10619  * - If 'ON' is set during this process, which means at least one
10620  *   interrupt is posted for this vCPU, we cannot block it, in
10621  *   this case, return 1, otherwise, return 0.
10622  *
10623  */
10624 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10625 {
10626         unsigned long flags;
10627         unsigned int dest;
10628         struct pi_desc old, new;
10629         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10630
10631         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10632                 !irq_remapping_cap(IRQ_POSTING_CAP))
10633                 return 0;
10634
10635         vcpu->pre_pcpu = vcpu->cpu;
10636         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10637                           vcpu->pre_pcpu), flags);
10638         list_add_tail(&vcpu->blocked_vcpu_list,
10639                       &per_cpu(blocked_vcpu_on_cpu,
10640                       vcpu->pre_pcpu));
10641         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10642                                vcpu->pre_pcpu), flags);
10643
10644         do {
10645                 old.control = new.control = pi_desc->control;
10646
10647                 /*
10648                  * We should not block the vCPU if
10649                  * an interrupt is posted for it.
10650                  */
10651                 if (pi_test_on(pi_desc) == 1) {
10652                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10653                                           vcpu->pre_pcpu), flags);
10654                         list_del(&vcpu->blocked_vcpu_list);
10655                         spin_unlock_irqrestore(
10656                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10657                                         vcpu->pre_pcpu), flags);
10658                         vcpu->pre_pcpu = -1;
10659
10660                         return 1;
10661                 }
10662
10663                 WARN((pi_desc->sn == 1),
10664                      "Warning: SN field of posted-interrupts "
10665                      "is set before blocking\n");
10666
10667                 /*
10668                  * Since vCPU can be preempted during this process,
10669                  * vcpu->cpu could be different with pre_pcpu, we
10670                  * need to set pre_pcpu as the destination of wakeup
10671                  * notification event, then we can find the right vCPU
10672                  * to wakeup in wakeup handler if interrupts happen
10673                  * when the vCPU is in blocked state.
10674                  */
10675                 dest = cpu_physical_id(vcpu->pre_pcpu);
10676
10677                 if (x2apic_enabled())
10678                         new.ndst = dest;
10679                 else
10680                         new.ndst = (dest << 8) & 0xFF00;
10681
10682                 /* set 'NV' to 'wakeup vector' */
10683                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10684         } while (cmpxchg(&pi_desc->control, old.control,
10685                         new.control) != old.control);
10686
10687         return 0;
10688 }
10689
10690 static void vmx_post_block(struct kvm_vcpu *vcpu)
10691 {
10692         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10693         struct pi_desc old, new;
10694         unsigned int dest;
10695         unsigned long flags;
10696
10697         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10698                 !irq_remapping_cap(IRQ_POSTING_CAP))
10699                 return;
10700
10701         do {
10702                 old.control = new.control = pi_desc->control;
10703
10704                 dest = cpu_physical_id(vcpu->cpu);
10705
10706                 if (x2apic_enabled())
10707                         new.ndst = dest;
10708                 else
10709                         new.ndst = (dest << 8) & 0xFF00;
10710
10711                 /* Allow posting non-urgent interrupts */
10712                 new.sn = 0;
10713
10714                 /* set 'NV' to 'notification vector' */
10715                 new.nv = POSTED_INTR_VECTOR;
10716         } while (cmpxchg(&pi_desc->control, old.control,
10717                         new.control) != old.control);
10718
10719         if(vcpu->pre_pcpu != -1) {
10720                 spin_lock_irqsave(
10721                         &per_cpu(blocked_vcpu_on_cpu_lock,
10722                         vcpu->pre_pcpu), flags);
10723                 list_del(&vcpu->blocked_vcpu_list);
10724                 spin_unlock_irqrestore(
10725                         &per_cpu(blocked_vcpu_on_cpu_lock,
10726                         vcpu->pre_pcpu), flags);
10727                 vcpu->pre_pcpu = -1;
10728         }
10729 }
10730
10731 /*
10732  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10733  *
10734  * @kvm: kvm
10735  * @host_irq: host irq of the interrupt
10736  * @guest_irq: gsi of the interrupt
10737  * @set: set or unset PI
10738  * returns 0 on success, < 0 on failure
10739  */
10740 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10741                               uint32_t guest_irq, bool set)
10742 {
10743         struct kvm_kernel_irq_routing_entry *e;
10744         struct kvm_irq_routing_table *irq_rt;
10745         struct kvm_lapic_irq irq;
10746         struct kvm_vcpu *vcpu;
10747         struct vcpu_data vcpu_info;
10748         int idx, ret = -EINVAL;
10749
10750         if (!kvm_arch_has_assigned_device(kvm) ||
10751                 !irq_remapping_cap(IRQ_POSTING_CAP))
10752                 return 0;
10753
10754         idx = srcu_read_lock(&kvm->irq_srcu);
10755         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10756         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10757
10758         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10759                 if (e->type != KVM_IRQ_ROUTING_MSI)
10760                         continue;
10761                 /*
10762                  * VT-d PI cannot support posting multicast/broadcast
10763                  * interrupts to a vCPU, we still use interrupt remapping
10764                  * for these kind of interrupts.
10765                  *
10766                  * For lowest-priority interrupts, we only support
10767                  * those with single CPU as the destination, e.g. user
10768                  * configures the interrupts via /proc/irq or uses
10769                  * irqbalance to make the interrupts single-CPU.
10770                  *
10771                  * We will support full lowest-priority interrupt later.
10772                  */
10773
10774                 kvm_set_msi_irq(e, &irq);
10775                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10776                         /*
10777                          * Make sure the IRTE is in remapped mode if
10778                          * we don't handle it in posted mode.
10779                          */
10780                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10781                         if (ret < 0) {
10782                                 printk(KERN_INFO
10783                                    "failed to back to remapped mode, irq: %u\n",
10784                                    host_irq);
10785                                 goto out;
10786                         }
10787
10788                         continue;
10789                 }
10790
10791                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10792                 vcpu_info.vector = irq.vector;
10793
10794                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10795                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10796
10797                 if (set)
10798                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10799                 else {
10800                         /* suppress notification event before unposting */
10801                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10802                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10803                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10804                 }
10805
10806                 if (ret < 0) {
10807                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10808                                         __func__);
10809                         goto out;
10810                 }
10811         }
10812
10813         ret = 0;
10814 out:
10815         srcu_read_unlock(&kvm->irq_srcu, idx);
10816         return ret;
10817 }
10818
10819 static struct kvm_x86_ops vmx_x86_ops = {
10820         .cpu_has_kvm_support = cpu_has_kvm_support,
10821         .disabled_by_bios = vmx_disabled_by_bios,
10822         .hardware_setup = hardware_setup,
10823         .hardware_unsetup = hardware_unsetup,
10824         .check_processor_compatibility = vmx_check_processor_compat,
10825         .hardware_enable = hardware_enable,
10826         .hardware_disable = hardware_disable,
10827         .cpu_has_accelerated_tpr = report_flexpriority,
10828         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10829
10830         .vcpu_create = vmx_create_vcpu,
10831         .vcpu_free = vmx_free_vcpu,
10832         .vcpu_reset = vmx_vcpu_reset,
10833
10834         .prepare_guest_switch = vmx_save_host_state,
10835         .vcpu_load = vmx_vcpu_load,
10836         .vcpu_put = vmx_vcpu_put,
10837
10838         .update_bp_intercept = update_exception_bitmap,
10839         .get_msr = vmx_get_msr,
10840         .set_msr = vmx_set_msr,
10841         .get_segment_base = vmx_get_segment_base,
10842         .get_segment = vmx_get_segment,
10843         .set_segment = vmx_set_segment,
10844         .get_cpl = vmx_get_cpl,
10845         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10846         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10847         .decache_cr3 = vmx_decache_cr3,
10848         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10849         .set_cr0 = vmx_set_cr0,
10850         .set_cr3 = vmx_set_cr3,
10851         .set_cr4 = vmx_set_cr4,
10852         .set_efer = vmx_set_efer,
10853         .get_idt = vmx_get_idt,
10854         .set_idt = vmx_set_idt,
10855         .get_gdt = vmx_get_gdt,
10856         .set_gdt = vmx_set_gdt,
10857         .get_dr6 = vmx_get_dr6,
10858         .set_dr6 = vmx_set_dr6,
10859         .set_dr7 = vmx_set_dr7,
10860         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10861         .cache_reg = vmx_cache_reg,
10862         .get_rflags = vmx_get_rflags,
10863         .set_rflags = vmx_set_rflags,
10864         .fpu_activate = vmx_fpu_activate,
10865         .fpu_deactivate = vmx_fpu_deactivate,
10866
10867         .tlb_flush = vmx_flush_tlb,
10868
10869         .run = vmx_vcpu_run,
10870         .handle_exit = vmx_handle_exit,
10871         .skip_emulated_instruction = skip_emulated_instruction,
10872         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10873         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10874         .patch_hypercall = vmx_patch_hypercall,
10875         .set_irq = vmx_inject_irq,
10876         .set_nmi = vmx_inject_nmi,
10877         .queue_exception = vmx_queue_exception,
10878         .cancel_injection = vmx_cancel_injection,
10879         .interrupt_allowed = vmx_interrupt_allowed,
10880         .nmi_allowed = vmx_nmi_allowed,
10881         .get_nmi_mask = vmx_get_nmi_mask,
10882         .set_nmi_mask = vmx_set_nmi_mask,
10883         .enable_nmi_window = enable_nmi_window,
10884         .enable_irq_window = enable_irq_window,
10885         .update_cr8_intercept = update_cr8_intercept,
10886         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10887         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10888         .get_enable_apicv = vmx_get_enable_apicv,
10889         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10890         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10891         .hwapic_irr_update = vmx_hwapic_irr_update,
10892         .hwapic_isr_update = vmx_hwapic_isr_update,
10893         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10894         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10895
10896         .set_tss_addr = vmx_set_tss_addr,
10897         .get_tdp_level = get_ept_level,
10898         .get_mt_mask = vmx_get_mt_mask,
10899
10900         .get_exit_info = vmx_get_exit_info,
10901
10902         .get_lpage_level = vmx_get_lpage_level,
10903
10904         .cpuid_update = vmx_cpuid_update,
10905
10906         .rdtscp_supported = vmx_rdtscp_supported,
10907         .invpcid_supported = vmx_invpcid_supported,
10908
10909         .set_supported_cpuid = vmx_set_supported_cpuid,
10910
10911         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10912
10913         .read_tsc_offset = vmx_read_tsc_offset,
10914         .write_tsc_offset = vmx_write_tsc_offset,
10915         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10916         .read_l1_tsc = vmx_read_l1_tsc,
10917
10918         .set_tdp_cr3 = vmx_set_cr3,
10919
10920         .check_intercept = vmx_check_intercept,
10921         .handle_external_intr = vmx_handle_external_intr,
10922         .mpx_supported = vmx_mpx_supported,
10923         .xsaves_supported = vmx_xsaves_supported,
10924
10925         .check_nested_events = vmx_check_nested_events,
10926
10927         .sched_in = vmx_sched_in,
10928
10929         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10930         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10931         .flush_log_dirty = vmx_flush_log_dirty,
10932         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10933
10934         .pre_block = vmx_pre_block,
10935         .post_block = vmx_post_block,
10936
10937         .pmu_ops = &intel_pmu_ops,
10938
10939         .update_pi_irte = vmx_update_pi_irte,
10940 };
10941
10942 static int __init vmx_init(void)
10943 {
10944         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10945                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10946         if (r)
10947                 return r;
10948
10949 #ifdef CONFIG_KEXEC_CORE
10950         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10951                            crash_vmclear_local_loaded_vmcss);
10952 #endif
10953
10954         return 0;
10955 }
10956
10957 static void __exit vmx_exit(void)
10958 {
10959 #ifdef CONFIG_KEXEC_CORE
10960         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10961         synchronize_rcu();
10962 #endif
10963
10964         kvm_exit();
10965 }
10966
10967 module_init(vmx_init)
10968 module_exit(vmx_exit)