arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601
 602         bool guest_pkru_valid;
 603         u32 guest_pkru;
 604         u32 host_pkru;
 605 };
 606
 607 enum segment_cache_field {
 608         SEG_FIELD_SEL = 0,
 609         SEG_FIELD_BASE = 1,
 610         SEG_FIELD_LIMIT = 2,
 611         SEG_FIELD_AR = 3,
 612
 613         SEG_FIELD_NR = 4
 614 };
 615
 616 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 617 {
 618         return container_of(vcpu, struct vcpu_vmx, vcpu);
 619 }
 620
 621 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 622 {
 623         return &(to_vmx(vcpu)->pi_desc);
 624 }
 625
 626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 627 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 628 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 629                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 630
 631
 632 static unsigned long shadow_read_only_fields[] = {
 633         /*
 634          * We do NOT shadow fields that are modified when L0
 635          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 636          * VMXON...) executed by L1.
 637          * For example, VM_INSTRUCTION_ERROR is read
 638          * by L1 if a vmx instruction fails (part of the error path).
 639          * Note the code assumes this logic. If for some reason
 640          * we start shadowing these fields then we need to
 641          * force a shadow sync when L0 emulates vmx instructions
 642          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 643          * by nested_vmx_failValid)
 644          */
 645         VM_EXIT_REASON,
 646         VM_EXIT_INTR_INFO,
 647         VM_EXIT_INSTRUCTION_LEN,
 648         IDT_VECTORING_INFO_FIELD,
 649         IDT_VECTORING_ERROR_CODE,
 650         VM_EXIT_INTR_ERROR_CODE,
 651         EXIT_QUALIFICATION,
 652         GUEST_LINEAR_ADDRESS,
 653         GUEST_PHYSICAL_ADDRESS
 654 };
 655 static int max_shadow_read_only_fields =
 656         ARRAY_SIZE(shadow_read_only_fields);
 657
 658 static unsigned long shadow_read_write_fields[] = {
 659         TPR_THRESHOLD,
 660         GUEST_RIP,
 661         GUEST_RSP,
 662         GUEST_CR0,
 663         GUEST_CR3,
 664         GUEST_CR4,
 665         GUEST_INTERRUPTIBILITY_INFO,
 666         GUEST_RFLAGS,
 667         GUEST_CS_SELECTOR,
 668         GUEST_CS_AR_BYTES,
 669         GUEST_CS_LIMIT,
 670         GUEST_CS_BASE,
 671         GUEST_ES_BASE,
 672         GUEST_BNDCFGS,
 673         CR0_GUEST_HOST_MASK,
 674         CR0_READ_SHADOW,
 675         CR4_READ_SHADOW,
 676         TSC_OFFSET,
 677         EXCEPTION_BITMAP,
 678         CPU_BASED_VM_EXEC_CONTROL,
 679         VM_ENTRY_EXCEPTION_ERROR_CODE,
 680         VM_ENTRY_INTR_INFO_FIELD,
 681         VM_ENTRY_INSTRUCTION_LEN,
 682         VM_ENTRY_EXCEPTION_ERROR_CODE,
 683         HOST_FS_BASE,
 684         HOST_GS_BASE,
 685         HOST_FS_SELECTOR,
 686         HOST_GS_SELECTOR
 687 };
 688 static int max_shadow_read_write_fields =
 689         ARRAY_SIZE(shadow_read_write_fields);
 690
 691 static const unsigned short vmcs_field_to_offset_table[] = {
 692         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 693         FIELD(POSTED_INTR_NV, posted_intr_nv),
 694         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 695         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 696         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 697         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 698         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 699         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 700         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 701         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 702         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 703         FIELD(HOST_ES_SELECTOR, host_es_selector),
 704         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 705         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 706         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 707         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 708         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 709         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 710         FIELD64(IO_BITMAP_A, io_bitmap_a),
 711         FIELD64(IO_BITMAP_B, io_bitmap_b),
 712         FIELD64(MSR_BITMAP, msr_bitmap),
 713         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 714         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 715         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 716         FIELD64(TSC_OFFSET, tsc_offset),
 717         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 718         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 719         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 720         FIELD64(EPT_POINTER, ept_pointer),
 721         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 722         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 723         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 724         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 725         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 726         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 727         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 728         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 729         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 730         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 731         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 732         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 733         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 734         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 735         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 736         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 737         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 738         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 739         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 740         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 741         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 742         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 743         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 744         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 745         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 746         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 747         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 748         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 749         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 750         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 751         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 752         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 753         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 754         FIELD(TPR_THRESHOLD, tpr_threshold),
 755         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 756         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 757         FIELD(VM_EXIT_REASON, vm_exit_reason),
 758         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 759         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 760         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 761         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 762         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 763         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 764         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 765         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 766         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 767         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 768         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 769         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 770         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 771         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 772         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 773         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 774         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 775         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 776         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 777         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 778         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 779         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 780         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 781         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 782         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 783         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 784         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 785         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 786         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 787         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 788         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 789         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 790         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 791         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 792         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 793         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 794         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 795         FIELD(EXIT_QUALIFICATION, exit_qualification),
 796         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 797         FIELD(GUEST_CR0, guest_cr0),
 798         FIELD(GUEST_CR3, guest_cr3),
 799         FIELD(GUEST_CR4, guest_cr4),
 800         FIELD(GUEST_ES_BASE, guest_es_base),
 801         FIELD(GUEST_CS_BASE, guest_cs_base),
 802         FIELD(GUEST_SS_BASE, guest_ss_base),
 803         FIELD(GUEST_DS_BASE, guest_ds_base),
 804         FIELD(GUEST_FS_BASE, guest_fs_base),
 805         FIELD(GUEST_GS_BASE, guest_gs_base),
 806         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 807         FIELD(GUEST_TR_BASE, guest_tr_base),
 808         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 809         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 810         FIELD(GUEST_DR7, guest_dr7),
 811         FIELD(GUEST_RSP, guest_rsp),
 812         FIELD(GUEST_RIP, guest_rip),
 813         FIELD(GUEST_RFLAGS, guest_rflags),
 814         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 815         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 816         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 817         FIELD(HOST_CR0, host_cr0),
 818         FIELD(HOST_CR3, host_cr3),
 819         FIELD(HOST_CR4, host_cr4),
 820         FIELD(HOST_FS_BASE, host_fs_base),
 821         FIELD(HOST_GS_BASE, host_gs_base),
 822         FIELD(HOST_TR_BASE, host_tr_base),
 823         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 824         FIELD(HOST_IDTR_BASE, host_idtr_base),
 825         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 826         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 827         FIELD(HOST_RSP, host_rsp),
 828         FIELD(HOST_RIP, host_rip),
 829 };
 830
 831 static inline short vmcs_field_to_offset(unsigned long field)
 832 {
 833         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 834
 835         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 836             vmcs_field_to_offset_table[field] == 0)
 837                 return -ENOENT;
 838
 839         return vmcs_field_to_offset_table[field];
 840 }
 841
 842 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 843 {
 844         return to_vmx(vcpu)->nested.current_vmcs12;
 845 }
 846
 847 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 848 {
 849         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 850         if (is_error_page(page))
 851                 return NULL;
 852
 853         return page;
 854 }
 855
 856 static void nested_release_page(struct page *page)
 857 {
 858         kvm_release_page_dirty(page);
 859 }
 860
 861 static void nested_release_page_clean(struct page *page)
 862 {
 863         kvm_release_page_clean(page);
 864 }
 865
 866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 867 static u64 construct_eptp(unsigned long root_hpa);
 868 static void kvm_cpu_vmxon(u64 addr);
 869 static void kvm_cpu_vmxoff(void);
 870 static bool vmx_xsaves_supported(void);
 871 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 872 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 873                             struct kvm_segment *var, int seg);
 874 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 875                             struct kvm_segment *var, int seg);
 876 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 877 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 878 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 880 static int alloc_identity_pagetable(struct kvm *kvm);
 881
 882 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 883 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 884 /*
 885  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 886  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 887  */
 888 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 889 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 890
 891 /*
 892  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 893  * can find which vCPU should be waken up.
 894  */
 895 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 896 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 897
 898 static unsigned long *vmx_io_bitmap_a;
 899 static unsigned long *vmx_io_bitmap_b;
 900 static unsigned long *vmx_msr_bitmap_legacy;
 901 static unsigned long *vmx_msr_bitmap_longmode;
 902 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 903 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 904 static unsigned long *vmx_msr_bitmap_nested;
 905 static unsigned long *vmx_vmread_bitmap;
 906 static unsigned long *vmx_vmwrite_bitmap;
 907
 908 static bool cpu_has_load_ia32_efer;
 909 static bool cpu_has_load_perf_global_ctrl;
 910
 911 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 912 static DEFINE_SPINLOCK(vmx_vpid_lock);
 913
 914 static struct vmcs_config {
 915         int size;
 916         int order;
 917         u32 revision_id;
 918         u32 pin_based_exec_ctrl;
 919         u32 cpu_based_exec_ctrl;
 920         u32 cpu_based_2nd_exec_ctrl;
 921         u32 vmexit_ctrl;
 922         u32 vmentry_ctrl;
 923 } vmcs_config;
 924
 925 static struct vmx_capability {
 926         u32 ept;
 927         u32 vpid;
 928 } vmx_capability;
 929
 930 #define VMX_SEGMENT_FIELD(seg)                                  \
 931         [VCPU_SREG_##seg] = {                                   \
 932                 .selector = GUEST_##seg##_SELECTOR,             \
 933                 .base = GUEST_##seg##_BASE,                     \
 934                 .limit = GUEST_##seg##_LIMIT,                   \
 935                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 936         }
 937
 938 static const struct kvm_vmx_segment_field {
 939         unsigned selector;
 940         unsigned base;
 941         unsigned limit;
 942         unsigned ar_bytes;
 943 } kvm_vmx_segment_fields[] = {
 944         VMX_SEGMENT_FIELD(CS),
 945         VMX_SEGMENT_FIELD(DS),
 946         VMX_SEGMENT_FIELD(ES),
 947         VMX_SEGMENT_FIELD(FS),
 948         VMX_SEGMENT_FIELD(GS),
 949         VMX_SEGMENT_FIELD(SS),
 950         VMX_SEGMENT_FIELD(TR),
 951         VMX_SEGMENT_FIELD(LDTR),
 952 };
 953
 954 static u64 host_efer;
 955
 956 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 957
 958 /*
 959  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 960  * away by decrementing the array size.
 961  */
 962 static const u32 vmx_msr_index[] = {
 963 #ifdef CONFIG_X86_64
 964         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 965 #endif
 966         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 967 };
 968
 969 static inline bool is_exception_n(u32 intr_info, u8 vector)
 970 {
 971         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 972                              INTR_INFO_VALID_MASK)) ==
 973                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 974 }
 975
 976 static inline bool is_debug(u32 intr_info)
 977 {
 978         return is_exception_n(intr_info, DB_VECTOR);
 979 }
 980
 981 static inline bool is_breakpoint(u32 intr_info)
 982 {
 983         return is_exception_n(intr_info, BP_VECTOR);
 984 }
 985
 986 static inline bool is_page_fault(u32 intr_info)
 987 {
 988         return is_exception_n(intr_info, PF_VECTOR);
 989 }
 990
 991 static inline bool is_no_device(u32 intr_info)
 992 {
 993         return is_exception_n(intr_info, NM_VECTOR);
 994 }
 995
 996 static inline bool is_invalid_opcode(u32 intr_info)
 997 {
 998         return is_exception_n(intr_info, UD_VECTOR);
 999 }
1000
1001 static inline bool is_external_interrupt(u32 intr_info)
1002 {
1003         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1004                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1005 }
1006
1007 static inline bool is_machine_check(u32 intr_info)
1008 {
1009         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1010                              INTR_INFO_VALID_MASK)) ==
1011                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1012 }
1013
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1017 }
1018
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1020 {
1021         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1022 }
1023
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1025 {
1026         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1027 }
1028
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1030 {
1031         return vmcs_config.cpu_based_exec_ctrl &
1032                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1033 }
1034
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1045 }
1046
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1051 }
1052
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1057 }
1058
1059 static inline bool cpu_has_vmx_posted_intr(void)
1060 {
1061         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1062                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1063 }
1064
1065 static inline bool cpu_has_vmx_apicv(void)
1066 {
1067         return cpu_has_vmx_apic_register_virt() &&
1068                 cpu_has_vmx_virtual_intr_delivery() &&
1069                 cpu_has_vmx_posted_intr();
1070 }
1071
1072 static inline bool cpu_has_vmx_flexpriority(void)
1073 {
1074         return cpu_has_vmx_tpr_shadow() &&
1075                 cpu_has_vmx_virtualize_apic_accesses();
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1099 {
1100         return vmx_capability.ept & VMX_EPT_AD_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invept_context(void)
1104 {
1105         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_invept_global(void)
1109 {
1110         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1111 }
1112
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1114 {
1115         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1116 }
1117
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1119 {
1120         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1121 }
1122
1123 static inline bool cpu_has_vmx_ept(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_ENABLE_EPT;
1127 }
1128
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1133 }
1134
1135 static inline bool cpu_has_vmx_ple(void)
1136 {
1137         return vmcs_config.cpu_based_2nd_exec_ctrl &
1138                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1139 }
1140
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1142 {
1143         return flexpriority_enabled && lapic_in_kernel(vcpu);
1144 }
1145
1146 static inline bool cpu_has_vmx_vpid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_VPID;
1150 }
1151
1152 static inline bool cpu_has_vmx_rdtscp(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_RDTSCP;
1156 }
1157
1158 static inline bool cpu_has_vmx_invpcid(void)
1159 {
1160         return vmcs_config.cpu_based_2nd_exec_ctrl &
1161                 SECONDARY_EXEC_ENABLE_INVPCID;
1162 }
1163
1164 static inline bool cpu_has_virtual_nmis(void)
1165 {
1166         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1167 }
1168
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1170 {
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_WBINVD_EXITING;
1173 }
1174
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1176 {
1177         u64 vmx_msr;
1178         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1179         /* check if the cpu supports writing r/o exit information fields */
1180         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1181                 return false;
1182
1183         return vmcs_config.cpu_based_2nd_exec_ctrl &
1184                 SECONDARY_EXEC_SHADOW_VMCS;
1185 }
1186
1187 static inline bool cpu_has_vmx_pml(void)
1188 {
1189         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1190 }
1191
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1193 {
1194         return vmcs_config.cpu_based_2nd_exec_ctrl &
1195                 SECONDARY_EXEC_TSC_SCALING;
1196 }
1197
1198 static inline bool report_flexpriority(void)
1199 {
1200         return flexpriority_enabled;
1201 }
1202
1203 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205         return vmcs12->cpu_based_vm_exec_control & bit;
1206 }
1207
1208 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1209 {
1210         return (vmcs12->cpu_based_vm_exec_control &
1211                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1212                 (vmcs12->secondary_vm_exec_control & bit);
1213 }
1214
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1216 {
1217         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1218 }
1219
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1221 {
1222         return vmcs12->pin_based_vm_exec_control &
1223                 PIN_BASED_VMX_PREEMPTION_TIMER;
1224 }
1225
1226 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1229 }
1230
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1234                 vmx_xsaves_supported();
1235 }
1236
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1240 }
1241
1242 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1243 {
1244         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1245 }
1246
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1248 {
1249         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1250 }
1251
1252 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1253 {
1254         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1255 }
1256
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1258 {
1259         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1260 }
1261
1262 static inline bool is_exception(u32 intr_info)
1263 {
1264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1265                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1266 }
1267
1268 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1269                               u32 exit_intr_info,
1270                               unsigned long exit_qualification);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1272                         struct vmcs12 *vmcs12,
1273                         u32 reason, unsigned long qualification);
1274
1275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1276 {
1277         int i;
1278
1279         for (i = 0; i < vmx->nmsrs; ++i)
1280                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1281                         return i;
1282         return -1;
1283 }
1284
1285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1286 {
1287     struct {
1288         u64 vpid : 16;
1289         u64 rsvd : 48;
1290         u64 gva;
1291     } operand = { vpid, 0, gva };
1292
1293     asm volatile (__ex(ASM_VMX_INVVPID)
1294                   /* CF==1 or ZF==1 --> rc = -1 */
1295                   "; ja 1f ; ud2 ; 1:"
1296                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1297 }
1298
1299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1300 {
1301         struct {
1302                 u64 eptp, gpa;
1303         } operand = {eptp, gpa};
1304
1305         asm volatile (__ex(ASM_VMX_INVEPT)
1306                         /* CF==1 or ZF==1 --> rc = -1 */
1307                         "; ja 1f ; ud2 ; 1:\n"
1308                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1309 }
1310
1311 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1312 {
1313         int i;
1314
1315         i = __find_msr_index(vmx, msr);
1316         if (i >= 0)
1317                 return &vmx->guest_msrs[i];
1318         return NULL;
1319 }
1320
1321 static void vmcs_clear(struct vmcs *vmcs)
1322 {
1323         u64 phys_addr = __pa(vmcs);
1324         u8 error;
1325
1326         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1327                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1328                       : "cc", "memory");
1329         if (error)
1330                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1331                        vmcs, phys_addr);
1332 }
1333
1334 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1335 {
1336         vmcs_clear(loaded_vmcs->vmcs);
1337         loaded_vmcs->cpu = -1;
1338         loaded_vmcs->launched = 0;
1339 }
1340
1341 static void vmcs_load(struct vmcs *vmcs)
1342 {
1343         u64 phys_addr = __pa(vmcs);
1344         u8 error;
1345
1346         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1347                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1348                         : "cc", "memory");
1349         if (error)
1350                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1351                        vmcs, phys_addr);
1352 }
1353
1354 #ifdef CONFIG_KEXEC_CORE
1355 /*
1356  * This bitmap is used to indicate whether the vmclear
1357  * operation is enabled on all cpus. All disabled by
1358  * default.
1359  */
1360 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1361
1362 static inline void crash_enable_local_vmclear(int cpu)
1363 {
1364         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366
1367 static inline void crash_disable_local_vmclear(int cpu)
1368 {
1369         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371
1372 static inline int crash_local_vmclear_enabled(int cpu)
1373 {
1374         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1375 }
1376
1377 static void crash_vmclear_local_loaded_vmcss(void)
1378 {
1379         int cpu = raw_smp_processor_id();
1380         struct loaded_vmcs *v;
1381
1382         if (!crash_local_vmclear_enabled(cpu))
1383                 return;
1384
1385         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1386                             loaded_vmcss_on_cpu_link)
1387                 vmcs_clear(v->vmcs);
1388 }
1389 #else
1390 static inline void crash_enable_local_vmclear(int cpu) { }
1391 static inline void crash_disable_local_vmclear(int cpu) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1393
1394 static void __loaded_vmcs_clear(void *arg)
1395 {
1396         struct loaded_vmcs *loaded_vmcs = arg;
1397         int cpu = raw_smp_processor_id();
1398
1399         if (loaded_vmcs->cpu != cpu)
1400                 return; /* vcpu migration can race with cpu offline */
1401         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1402                 per_cpu(current_vmcs, cpu) = NULL;
1403         crash_disable_local_vmclear(cpu);
1404         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1405
1406         /*
1407          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408          * is before setting loaded_vmcs->vcpu to -1 which is done in
1409          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410          * then adds the vmcs into percpu list before it is deleted.
1411          */
1412         smp_wmb();
1413
1414         loaded_vmcs_init(loaded_vmcs);
1415         crash_enable_local_vmclear(cpu);
1416 }
1417
1418 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1419 {
1420         int cpu = loaded_vmcs->cpu;
1421
1422         if (cpu != -1)
1423                 smp_call_function_single(cpu,
1424                          __loaded_vmcs_clear, loaded_vmcs, 1);
1425 }
1426
1427 static inline void vpid_sync_vcpu_single(int vpid)
1428 {
1429         if (vpid == 0)
1430                 return;
1431
1432         if (cpu_has_vmx_invvpid_single())
1433                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1434 }
1435
1436 static inline void vpid_sync_vcpu_global(void)
1437 {
1438         if (cpu_has_vmx_invvpid_global())
1439                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1440 }
1441
1442 static inline void vpid_sync_context(int vpid)
1443 {
1444         if (cpu_has_vmx_invvpid_single())
1445                 vpid_sync_vcpu_single(vpid);
1446         else
1447                 vpid_sync_vcpu_global();
1448 }
1449
1450 static inline void ept_sync_global(void)
1451 {
1452         if (cpu_has_vmx_invept_global())
1453                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1454 }
1455
1456 static inline void ept_sync_context(u64 eptp)
1457 {
1458         if (enable_ept) {
1459                 if (cpu_has_vmx_invept_context())
1460                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1461                 else
1462                         ept_sync_global();
1463         }
1464 }
1465
1466 static __always_inline void vmcs_check16(unsigned long field)
1467 {
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1469                          "16-bit accessor invalid for 64-bit field");
1470         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1471                          "16-bit accessor invalid for 64-bit high field");
1472         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1473                          "16-bit accessor invalid for 32-bit high field");
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1475                          "16-bit accessor invalid for natural width field");
1476 }
1477
1478 static __always_inline void vmcs_check32(unsigned long field)
1479 {
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1481                          "32-bit accessor invalid for 16-bit field");
1482         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1483                          "32-bit accessor invalid for natural width field");
1484 }
1485
1486 static __always_inline void vmcs_check64(unsigned long field)
1487 {
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1489                          "64-bit accessor invalid for 16-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "64-bit accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "64-bit accessor invalid for 32-bit field");
1494         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1495                          "64-bit accessor invalid for natural width field");
1496 }
1497
1498 static __always_inline void vmcs_checkl(unsigned long field)
1499 {
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1501                          "Natural width accessor invalid for 16-bit field");
1502         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1503                          "Natural width accessor invalid for 64-bit field");
1504         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1505                          "Natural width accessor invalid for 64-bit high field");
1506         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1507                          "Natural width accessor invalid for 32-bit field");
1508 }
1509
1510 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1511 {
1512         unsigned long value;
1513
1514         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1515                       : "=a"(value) : "d"(field) : "cc");
1516         return value;
1517 }
1518
1519 static __always_inline u16 vmcs_read16(unsigned long field)
1520 {
1521         vmcs_check16(field);
1522         return __vmcs_readl(field);
1523 }
1524
1525 static __always_inline u32 vmcs_read32(unsigned long field)
1526 {
1527         vmcs_check32(field);
1528         return __vmcs_readl(field);
1529 }
1530
1531 static __always_inline u64 vmcs_read64(unsigned long field)
1532 {
1533         vmcs_check64(field);
1534 #ifdef CONFIG_X86_64
1535         return __vmcs_readl(field);
1536 #else
1537         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1538 #endif
1539 }
1540
1541 static __always_inline unsigned long vmcs_readl(unsigned long field)
1542 {
1543         vmcs_checkl(field);
1544         return __vmcs_readl(field);
1545 }
1546
1547 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1548 {
1549         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1550                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1551         dump_stack();
1552 }
1553
1554 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1555 {
1556         u8 error;
1557
1558         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1559                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1560         if (unlikely(error))
1561                 vmwrite_error(field, value);
1562 }
1563
1564 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1565 {
1566         vmcs_check16(field);
1567         __vmcs_writel(field, value);
1568 }
1569
1570 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1571 {
1572         vmcs_check32(field);
1573         __vmcs_writel(field, value);
1574 }
1575
1576 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1577 {
1578         vmcs_check64(field);
1579         __vmcs_writel(field, value);
1580 #ifndef CONFIG_X86_64
1581         asm volatile ("");
1582         __vmcs_writel(field+1, value >> 32);
1583 #endif
1584 }
1585
1586 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1587 {
1588         vmcs_checkl(field);
1589         __vmcs_writel(field, value);
1590 }
1591
1592 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1595                          "vmcs_clear_bits does not support 64-bit fields");
1596         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1597 }
1598
1599 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1600 {
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1602                          "vmcs_set_bits does not support 64-bit fields");
1603         __vmcs_writel(field, __vmcs_readl(field) | mask);
1604 }
1605
1606 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1607 {
1608         vmcs_write32(VM_ENTRY_CONTROLS, val);
1609         vmx->vm_entry_controls_shadow = val;
1610 }
1611
1612 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1613 {
1614         if (vmx->vm_entry_controls_shadow != val)
1615                 vm_entry_controls_init(vmx, val);
1616 }
1617
1618 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1619 {
1620         return vmx->vm_entry_controls_shadow;
1621 }
1622
1623
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1627 }
1628
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1630 {
1631         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1632 }
1633
1634 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1635 {
1636         vmcs_write32(VM_EXIT_CONTROLS, val);
1637         vmx->vm_exit_controls_shadow = val;
1638 }
1639
1640 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1641 {
1642         if (vmx->vm_exit_controls_shadow != val)
1643                 vm_exit_controls_init(vmx, val);
1644 }
1645
1646 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1647 {
1648         return vmx->vm_exit_controls_shadow;
1649 }
1650
1651
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1655 }
1656
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1658 {
1659         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1660 }
1661
1662 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1663 {
1664         vmx->segment_cache.bitmask = 0;
1665 }
1666
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1668                                        unsigned field)
1669 {
1670         bool ret;
1671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1672
1673         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1674                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1675                 vmx->segment_cache.bitmask = 0;
1676         }
1677         ret = vmx->segment_cache.bitmask & mask;
1678         vmx->segment_cache.bitmask |= mask;
1679         return ret;
1680 }
1681
1682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1683 {
1684         u16 *p = &vmx->segment_cache.seg[seg].selector;
1685
1686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1688         return *p;
1689 }
1690
1691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1692 {
1693         ulong *p = &vmx->segment_cache.seg[seg].base;
1694
1695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1697         return *p;
1698 }
1699
1700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1701 {
1702         u32 *p = &vmx->segment_cache.seg[seg].limit;
1703
1704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1706         return *p;
1707 }
1708
1709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1710 {
1711         u32 *p = &vmx->segment_cache.seg[seg].ar;
1712
1713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1715         return *p;
1716 }
1717
1718 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1719 {
1720         u32 eb;
1721
1722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1723              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1724         if ((vcpu->guest_debug &
1725              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1726             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1727                 eb |= 1u << BP_VECTOR;
1728         if (to_vmx(vcpu)->rmode.vm86_active)
1729                 eb = ~0;
1730         if (enable_ept)
1731                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1732         if (vcpu->fpu_active)
1733                 eb &= ~(1u << NM_VECTOR);
1734
1735         /* When we are running a nested L2 guest and L1 specified for it a
1736          * certain exception bitmap, we must trap the same exceptions and pass
1737          * them to L1. When running L2, we will only handle the exceptions
1738          * specified above if L1 did not want them.
1739          */
1740         if (is_guest_mode(vcpu))
1741                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1742
1743         vmcs_write32(EXCEPTION_BITMAP, eb);
1744 }
1745
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1747                 unsigned long entry, unsigned long exit)
1748 {
1749         vm_entry_controls_clearbit(vmx, entry);
1750         vm_exit_controls_clearbit(vmx, exit);
1751 }
1752
1753 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1754 {
1755         unsigned i;
1756         struct msr_autoload *m = &vmx->msr_autoload;
1757
1758         switch (msr) {
1759         case MSR_EFER:
1760                 if (cpu_has_load_ia32_efer) {
1761                         clear_atomic_switch_msr_special(vmx,
1762                                         VM_ENTRY_LOAD_IA32_EFER,
1763                                         VM_EXIT_LOAD_IA32_EFER);
1764                         return;
1765                 }
1766                 break;
1767         case MSR_CORE_PERF_GLOBAL_CTRL:
1768                 if (cpu_has_load_perf_global_ctrl) {
1769                         clear_atomic_switch_msr_special(vmx,
1770                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1771                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1772                         return;
1773                 }
1774                 break;
1775         }
1776
1777         for (i = 0; i < m->nr; ++i)
1778                 if (m->guest[i].index == msr)
1779                         break;
1780
1781         if (i == m->nr)
1782                 return;
1783         --m->nr;
1784         m->guest[i] = m->guest[m->nr];
1785         m->host[i] = m->host[m->nr];
1786         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1787         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1788 }
1789
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1791                 unsigned long entry, unsigned long exit,
1792                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1793                 u64 guest_val, u64 host_val)
1794 {
1795         vmcs_write64(guest_val_vmcs, guest_val);
1796         vmcs_write64(host_val_vmcs, host_val);
1797         vm_entry_controls_setbit(vmx, entry);
1798         vm_exit_controls_setbit(vmx, exit);
1799 }
1800
1801 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1802                                   u64 guest_val, u64 host_val)
1803 {
1804         unsigned i;
1805         struct msr_autoload *m = &vmx->msr_autoload;
1806
1807         switch (msr) {
1808         case MSR_EFER:
1809                 if (cpu_has_load_ia32_efer) {
1810                         add_atomic_switch_msr_special(vmx,
1811                                         VM_ENTRY_LOAD_IA32_EFER,
1812                                         VM_EXIT_LOAD_IA32_EFER,
1813                                         GUEST_IA32_EFER,
1814                                         HOST_IA32_EFER,
1815                                         guest_val, host_val);
1816                         return;
1817                 }
1818                 break;
1819         case MSR_CORE_PERF_GLOBAL_CTRL:
1820                 if (cpu_has_load_perf_global_ctrl) {
1821                         add_atomic_switch_msr_special(vmx,
1822                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1823                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1824                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1825                                         HOST_IA32_PERF_GLOBAL_CTRL,
1826                                         guest_val, host_val);
1827                         return;
1828                 }
1829                 break;
1830         case MSR_IA32_PEBS_ENABLE:
1831                 /* PEBS needs a quiescent period after being disabled (to write
1832                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1833                  * provide that period, so a CPU could write host's record into
1834                  * guest's memory.
1835                  */
1836                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1837         }
1838
1839         for (i = 0; i < m->nr; ++i)
1840                 if (m->guest[i].index == msr)
1841                         break;
1842
1843         if (i == NR_AUTOLOAD_MSRS) {
1844                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1845                                 "Can't add msr %x\n", msr);
1846                 return;
1847         } else if (i == m->nr) {
1848                 ++m->nr;
1849                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1850                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1851         }
1852
1853         m->guest[i].index = msr;
1854         m->guest[i].value = guest_val;
1855         m->host[i].index = msr;
1856         m->host[i].value = host_val;
1857 }
1858
1859 static void reload_tss(void)
1860 {
1861         /*
1862          * VT restores TR but not its size.  Useless.
1863          */
1864         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1865         struct desc_struct *descs;
1866
1867         descs = (void *)gdt->address;
1868         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1869         load_TR_desc();
1870 }
1871
1872 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1873 {
1874         u64 guest_efer = vmx->vcpu.arch.efer;
1875         u64 ignore_bits = 0;
1876
1877         if (!enable_ept) {
1878                 /*
1879                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1880                  * host CPUID is more efficient than testing guest CPUID
1881                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1882                  */
1883                 if (boot_cpu_has(X86_FEATURE_SMEP))
1884                         guest_efer |= EFER_NX;
1885                 else if (!(guest_efer & EFER_NX))
1886                         ignore_bits |= EFER_NX;
1887         }
1888
1889         /*
1890          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1891          */
1892         ignore_bits |= EFER_SCE;
1893 #ifdef CONFIG_X86_64
1894         ignore_bits |= EFER_LMA | EFER_LME;
1895         /* SCE is meaningful only in long mode on Intel */
1896         if (guest_efer & EFER_LMA)
1897                 ignore_bits &= ~(u64)EFER_SCE;
1898 #endif
1899
1900         clear_atomic_switch_msr(vmx, MSR_EFER);
1901
1902         /*
1903          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904          * On CPUs that support "load IA32_EFER", always switch EFER
1905          * atomically, since it's faster than switching it manually.
1906          */
1907         if (cpu_has_load_ia32_efer ||
1908             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1909                 if (!(guest_efer & EFER_LMA))
1910                         guest_efer &= ~EFER_LME;
1911                 if (guest_efer != host_efer)
1912                         add_atomic_switch_msr(vmx, MSR_EFER,
1913                                               guest_efer, host_efer);
1914                 return false;
1915         } else {
1916                 guest_efer &= ~ignore_bits;
1917                 guest_efer |= host_efer & ignore_bits;
1918
1919                 vmx->guest_msrs[efer_offset].data = guest_efer;
1920                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1921
1922                 return true;
1923         }
1924 }
1925
1926 static unsigned long segment_base(u16 selector)
1927 {
1928         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1929         struct desc_struct *d;
1930         unsigned long table_base;
1931         unsigned long v;
1932
1933         if (!(selector & ~3))
1934                 return 0;
1935
1936         table_base = gdt->address;
1937
1938         if (selector & 4) {           /* from ldt */
1939                 u16 ldt_selector = kvm_read_ldt();
1940
1941                 if (!(ldt_selector & ~3))
1942                         return 0;
1943
1944                 table_base = segment_base(ldt_selector);
1945         }
1946         d = (struct desc_struct *)(table_base + (selector & ~7));
1947         v = get_desc_base(d);
1948 #ifdef CONFIG_X86_64
1949        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1950                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1951 #endif
1952         return v;
1953 }
1954
1955 static inline unsigned long kvm_read_tr_base(void)
1956 {
1957         u16 tr;
1958         asm("str %0" : "=g"(tr));
1959         return segment_base(tr);
1960 }
1961
1962 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1963 {
1964         struct vcpu_vmx *vmx = to_vmx(vcpu);
1965         int i;
1966
1967         if (vmx->host_state.loaded)
1968                 return;
1969
1970         vmx->host_state.loaded = 1;
1971         /*
1972          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1973          * allow segment selectors with cpl > 0 or ti == 1.
1974          */
1975         vmx->host_state.ldt_sel = kvm_read_ldt();
1976         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1977         savesegment(fs, vmx->host_state.fs_sel);
1978         if (!(vmx->host_state.fs_sel & 7)) {
1979                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1980                 vmx->host_state.fs_reload_needed = 0;
1981         } else {
1982                 vmcs_write16(HOST_FS_SELECTOR, 0);
1983                 vmx->host_state.fs_reload_needed = 1;
1984         }
1985         savesegment(gs, vmx->host_state.gs_sel);
1986         if (!(vmx->host_state.gs_sel & 7))
1987                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1988         else {
1989                 vmcs_write16(HOST_GS_SELECTOR, 0);
1990                 vmx->host_state.gs_ldt_reload_needed = 1;
1991         }
1992
1993 #ifdef CONFIG_X86_64
1994         savesegment(ds, vmx->host_state.ds_sel);
1995         savesegment(es, vmx->host_state.es_sel);
1996 #endif
1997
1998 #ifdef CONFIG_X86_64
1999         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2000         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2001 #else
2002         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2003         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2004 #endif
2005
2006 #ifdef CONFIG_X86_64
2007         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2008         if (is_long_mode(&vmx->vcpu))
2009                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2010 #endif
2011         if (boot_cpu_has(X86_FEATURE_MPX))
2012                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2013         for (i = 0; i < vmx->save_nmsrs; ++i)
2014                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2015                                    vmx->guest_msrs[i].data,
2016                                    vmx->guest_msrs[i].mask);
2017 }
2018
2019 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2020 {
2021         if (!vmx->host_state.loaded)
2022                 return;
2023
2024         ++vmx->vcpu.stat.host_state_reload;
2025         vmx->host_state.loaded = 0;
2026 #ifdef CONFIG_X86_64
2027         if (is_long_mode(&vmx->vcpu))
2028                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2029 #endif
2030         if (vmx->host_state.gs_ldt_reload_needed) {
2031                 kvm_load_ldt(vmx->host_state.ldt_sel);
2032 #ifdef CONFIG_X86_64
2033                 load_gs_index(vmx->host_state.gs_sel);
2034 #else
2035                 loadsegment(gs, vmx->host_state.gs_sel);
2036 #endif
2037         }
2038         if (vmx->host_state.fs_reload_needed)
2039                 loadsegment(fs, vmx->host_state.fs_sel);
2040 #ifdef CONFIG_X86_64
2041         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2042                 loadsegment(ds, vmx->host_state.ds_sel);
2043                 loadsegment(es, vmx->host_state.es_sel);
2044         }
2045 #endif
2046         reload_tss();
2047 #ifdef CONFIG_X86_64
2048         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2049 #endif
2050         if (vmx->host_state.msr_host_bndcfgs)
2051                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2052         /*
2053          * If the FPU is not active (through the host task or
2054          * the guest vcpu), then restore the cr0.TS bit.
2055          */
2056         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2057                 stts();
2058         load_gdt(this_cpu_ptr(&host_gdt));
2059 }
2060
2061 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2062 {
2063         preempt_disable();
2064         __vmx_load_host_state(vmx);
2065         preempt_enable();
2066 }
2067
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2069 {
2070         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2071         struct pi_desc old, new;
2072         unsigned int dest;
2073
2074         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075                 !irq_remapping_cap(IRQ_POSTING_CAP))
2076                 return;
2077
2078         do {
2079                 old.control = new.control = pi_desc->control;
2080
2081                 /*
2082                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2083                  * are two possible cases:
2084                  * 1. After running 'pre_block', context switch
2085                  *    happened. For this case, 'sn' was set in
2086                  *    vmx_vcpu_put(), so we need to clear it here.
2087                  * 2. After running 'pre_block', we were blocked,
2088                  *    and woken up by some other guy. For this case,
2089                  *    we don't need to do anything, 'pi_post_block'
2090                  *    will do everything for us. However, we cannot
2091                  *    check whether it is case #1 or case #2 here
2092                  *    (maybe, not needed), so we also clear sn here,
2093                  *    I think it is not a big deal.
2094                  */
2095                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2096                         if (vcpu->cpu != cpu) {
2097                                 dest = cpu_physical_id(cpu);
2098
2099                                 if (x2apic_enabled())
2100                                         new.ndst = dest;
2101                                 else
2102                                         new.ndst = (dest << 8) & 0xFF00;
2103                         }
2104
2105                         /* set 'NV' to 'notification vector' */
2106                         new.nv = POSTED_INTR_VECTOR;
2107                 }
2108
2109                 /* Allow posting non-urgent interrupts */
2110                 new.sn = 0;
2111         } while (cmpxchg(&pi_desc->control, old.control,
2112                         new.control) != old.control);
2113 }
2114
2115 /*
2116  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2117  * vcpu mutex is already taken.
2118  */
2119 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2120 {
2121         struct vcpu_vmx *vmx = to_vmx(vcpu);
2122         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2123
2124         if (!vmm_exclusive)
2125                 kvm_cpu_vmxon(phys_addr);
2126         else if (vmx->loaded_vmcs->cpu != cpu)
2127                 loaded_vmcs_clear(vmx->loaded_vmcs);
2128
2129         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2130                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2131                 vmcs_load(vmx->loaded_vmcs->vmcs);
2132         }
2133
2134         if (vmx->loaded_vmcs->cpu != cpu) {
2135                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2136                 unsigned long sysenter_esp;
2137
2138                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2139                 local_irq_disable();
2140                 crash_disable_local_vmclear(cpu);
2141
2142                 /*
2143                  * Read loaded_vmcs->cpu should be before fetching
2144                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2145                  * See the comments in __loaded_vmcs_clear().
2146                  */
2147                 smp_rmb();
2148
2149                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2150                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2151                 crash_enable_local_vmclear(cpu);
2152                 local_irq_enable();
2153
2154                 /*
2155                  * Linux uses per-cpu TSS and GDT, so set these when switching
2156                  * processors.
2157                  */
2158                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2159                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2160
2161                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2162                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2163
2164                 vmx->loaded_vmcs->cpu = cpu;
2165         }
2166
2167         /* Setup TSC multiplier */
2168         if (kvm_has_tsc_control &&
2169             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2170                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2171                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2172         }
2173
2174         vmx_vcpu_pi_load(vcpu, cpu);
2175         vmx->host_pkru = read_pkru();
2176 }
2177
2178 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2179 {
2180         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2181
2182         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2183                 !irq_remapping_cap(IRQ_POSTING_CAP))
2184                 return;
2185
2186         /* Set SN when the vCPU is preempted */
2187         if (vcpu->preempted)
2188                 pi_set_sn(pi_desc);
2189 }
2190
2191 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2192 {
2193         vmx_vcpu_pi_put(vcpu);
2194
2195         __vmx_load_host_state(to_vmx(vcpu));
2196         if (!vmm_exclusive) {
2197                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2198                 vcpu->cpu = -1;
2199                 kvm_cpu_vmxoff();
2200         }
2201 }
2202
2203 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2204 {
2205         ulong cr0;
2206
2207         if (vcpu->fpu_active)
2208                 return;
2209         vcpu->fpu_active = 1;
2210         cr0 = vmcs_readl(GUEST_CR0);
2211         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2212         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2213         vmcs_writel(GUEST_CR0, cr0);
2214         update_exception_bitmap(vcpu);
2215         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2216         if (is_guest_mode(vcpu))
2217                 vcpu->arch.cr0_guest_owned_bits &=
2218                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2219         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2220 }
2221
2222 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2223
2224 /*
2225  * Return the cr0 value that a nested guest would read. This is a combination
2226  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2227  * its hypervisor (cr0_read_shadow).
2228  */
2229 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2230 {
2231         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2232                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2233 }
2234 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2235 {
2236         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2237                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2238 }
2239
2240 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2241 {
2242         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2243          * set this *before* calling this function.
2244          */
2245         vmx_decache_cr0_guest_bits(vcpu);
2246         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2247         update_exception_bitmap(vcpu);
2248         vcpu->arch.cr0_guest_owned_bits = 0;
2249         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2250         if (is_guest_mode(vcpu)) {
2251                 /*
2252                  * L1's specified read shadow might not contain the TS bit,
2253                  * so now that we turned on shadowing of this bit, we need to
2254                  * set this bit of the shadow. Like in nested_vmx_run we need
2255                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2256                  * up-to-date here because we just decached cr0.TS (and we'll
2257                  * only update vmcs12->guest_cr0 on nested exit).
2258                  */
2259                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2260                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2261                         (vcpu->arch.cr0 & X86_CR0_TS);
2262                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2263         } else
2264                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2265 }
2266
2267 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2268 {
2269         unsigned long rflags, save_rflags;
2270
2271         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2272                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2273                 rflags = vmcs_readl(GUEST_RFLAGS);
2274                 if (to_vmx(vcpu)->rmode.vm86_active) {
2275                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2276                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2277                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2278                 }
2279                 to_vmx(vcpu)->rflags = rflags;
2280         }
2281         return to_vmx(vcpu)->rflags;
2282 }
2283
2284 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2285 {
2286         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2287         to_vmx(vcpu)->rflags = rflags;
2288         if (to_vmx(vcpu)->rmode.vm86_active) {
2289                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2290                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2291         }
2292         vmcs_writel(GUEST_RFLAGS, rflags);
2293 }
2294
2295 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2296 {
2297         return to_vmx(vcpu)->guest_pkru;
2298 }
2299
2300 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2301 {
2302         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2303         int ret = 0;
2304
2305         if (interruptibility & GUEST_INTR_STATE_STI)
2306                 ret |= KVM_X86_SHADOW_INT_STI;
2307         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2308                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2309
2310         return ret;
2311 }
2312
2313 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2314 {
2315         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2316         u32 interruptibility = interruptibility_old;
2317
2318         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2319
2320         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2321                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2322         else if (mask & KVM_X86_SHADOW_INT_STI)
2323                 interruptibility |= GUEST_INTR_STATE_STI;
2324
2325         if ((interruptibility != interruptibility_old))
2326                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2327 }
2328
2329 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2330 {
2331         unsigned long rip;
2332
2333         rip = kvm_rip_read(vcpu);
2334         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2335         kvm_rip_write(vcpu, rip);
2336
2337         /* skipping an emulated instruction also counts */
2338         vmx_set_interrupt_shadow(vcpu, 0);
2339 }
2340
2341 /*
2342  * KVM wants to inject page-faults which it got to the guest. This function
2343  * checks whether in a nested guest, we need to inject them to L1 or L2.
2344  */
2345 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2346 {
2347         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2348
2349         if (!(vmcs12->exception_bitmap & (1u << nr)))
2350                 return 0;
2351
2352         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2353                           vmcs_read32(VM_EXIT_INTR_INFO),
2354                           vmcs_readl(EXIT_QUALIFICATION));
2355         return 1;
2356 }
2357
2358 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2359                                 bool has_error_code, u32 error_code,
2360                                 bool reinject)
2361 {
2362         struct vcpu_vmx *vmx = to_vmx(vcpu);
2363         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2364
2365         if (!reinject && is_guest_mode(vcpu) &&
2366             nested_vmx_check_exception(vcpu, nr))
2367                 return;
2368
2369         if (has_error_code) {
2370                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2371                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2372         }
2373
2374         if (vmx->rmode.vm86_active) {
2375                 int inc_eip = 0;
2376                 if (kvm_exception_is_soft(nr))
2377                         inc_eip = vcpu->arch.event_exit_inst_len;
2378                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2379                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2380                 return;
2381         }
2382
2383         if (kvm_exception_is_soft(nr)) {
2384                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2385                              vmx->vcpu.arch.event_exit_inst_len);
2386                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2387         } else
2388                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2389
2390         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2391 }
2392
2393 static bool vmx_rdtscp_supported(void)
2394 {
2395         return cpu_has_vmx_rdtscp();
2396 }
2397
2398 static bool vmx_invpcid_supported(void)
2399 {
2400         return cpu_has_vmx_invpcid() && enable_ept;
2401 }
2402
2403 /*
2404  * Swap MSR entry in host/guest MSR entry array.
2405  */
2406 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2407 {
2408         struct shared_msr_entry tmp;
2409
2410         tmp = vmx->guest_msrs[to];
2411         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2412         vmx->guest_msrs[from] = tmp;
2413 }
2414
2415 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2416 {
2417         unsigned long *msr_bitmap;
2418
2419         if (is_guest_mode(vcpu))
2420                 msr_bitmap = vmx_msr_bitmap_nested;
2421         else if (cpu_has_secondary_exec_ctrls() &&
2422                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2423                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2424                 if (is_long_mode(vcpu))
2425                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2426                 else
2427                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2428         } else {
2429                 if (is_long_mode(vcpu))
2430                         msr_bitmap = vmx_msr_bitmap_longmode;
2431                 else
2432                         msr_bitmap = vmx_msr_bitmap_legacy;
2433         }
2434
2435         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2436 }
2437
2438 /*
2439  * Set up the vmcs to automatically save and restore system
2440  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2441  * mode, as fiddling with msrs is very expensive.
2442  */
2443 static void setup_msrs(struct vcpu_vmx *vmx)
2444 {
2445         int save_nmsrs, index;
2446
2447         save_nmsrs = 0;
2448 #ifdef CONFIG_X86_64
2449         if (is_long_mode(&vmx->vcpu)) {
2450                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2451                 if (index >= 0)
2452                         move_msr_up(vmx, index, save_nmsrs++);
2453                 index = __find_msr_index(vmx, MSR_LSTAR);
2454                 if (index >= 0)
2455                         move_msr_up(vmx, index, save_nmsrs++);
2456                 index = __find_msr_index(vmx, MSR_CSTAR);
2457                 if (index >= 0)
2458                         move_msr_up(vmx, index, save_nmsrs++);
2459                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2460                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2461                         move_msr_up(vmx, index, save_nmsrs++);
2462                 /*
2463                  * MSR_STAR is only needed on long mode guests, and only
2464                  * if efer.sce is enabled.
2465                  */
2466                 index = __find_msr_index(vmx, MSR_STAR);
2467                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2468                         move_msr_up(vmx, index, save_nmsrs++);
2469         }
2470 #endif
2471         index = __find_msr_index(vmx, MSR_EFER);
2472         if (index >= 0 && update_transition_efer(vmx, index))
2473                 move_msr_up(vmx, index, save_nmsrs++);
2474
2475         vmx->save_nmsrs = save_nmsrs;
2476
2477         if (cpu_has_vmx_msr_bitmap())
2478                 vmx_set_msr_bitmap(&vmx->vcpu);
2479 }
2480
2481 /*
2482  * reads and returns guest's timestamp counter "register"
2483  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2484  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2485  */
2486 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2487 {
2488         u64 host_tsc, tsc_offset;
2489
2490         host_tsc = rdtsc();
2491         tsc_offset = vmcs_read64(TSC_OFFSET);
2492         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2493 }
2494
2495 /*
2496  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2497  * counter, even if a nested guest (L2) is currently running.
2498  */
2499 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2500 {
2501         u64 tsc_offset;
2502
2503         tsc_offset = is_guest_mode(vcpu) ?
2504                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2505                 vmcs_read64(TSC_OFFSET);
2506         return host_tsc + tsc_offset;
2507 }
2508
2509 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2510 {
2511         return vmcs_read64(TSC_OFFSET);
2512 }
2513
2514 /*
2515  * writes 'offset' into guest's timestamp counter offset register
2516  */
2517 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2518 {
2519         if (is_guest_mode(vcpu)) {
2520                 /*
2521                  * We're here if L1 chose not to trap WRMSR to TSC. According
2522                  * to the spec, this should set L1's TSC; The offset that L1
2523                  * set for L2 remains unchanged, and still needs to be added
2524                  * to the newly set TSC to get L2's TSC.
2525                  */
2526                 struct vmcs12 *vmcs12;
2527                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2528                 /* recalculate vmcs02.TSC_OFFSET: */
2529                 vmcs12 = get_vmcs12(vcpu);
2530                 vmcs_write64(TSC_OFFSET, offset +
2531                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2532                          vmcs12->tsc_offset : 0));
2533         } else {
2534                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2535                                            vmcs_read64(TSC_OFFSET), offset);
2536                 vmcs_write64(TSC_OFFSET, offset);
2537         }
2538 }
2539
2540 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2541 {
2542         u64 offset = vmcs_read64(TSC_OFFSET);
2543
2544         vmcs_write64(TSC_OFFSET, offset + adjustment);
2545         if (is_guest_mode(vcpu)) {
2546                 /* Even when running L2, the adjustment needs to apply to L1 */
2547                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2548         } else
2549                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2550                                            offset + adjustment);
2551 }
2552
2553 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2554 {
2555         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2556         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2557 }
2558
2559 /*
2560  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2561  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2562  * all guests if the "nested" module option is off, and can also be disabled
2563  * for a single guest by disabling its VMX cpuid bit.
2564  */
2565 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2566 {
2567         return nested && guest_cpuid_has_vmx(vcpu);
2568 }
2569
2570 /*
2571  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2572  * returned for the various VMX controls MSRs when nested VMX is enabled.
2573  * The same values should also be used to verify that vmcs12 control fields are
2574  * valid during nested entry from L1 to L2.
2575  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2576  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2577  * bit in the high half is on if the corresponding bit in the control field
2578  * may be on. See also vmx_control_verify().
2579  */
2580 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2581 {
2582         /*
2583          * Note that as a general rule, the high half of the MSRs (bits in
2584          * the control fields which may be 1) should be initialized by the
2585          * intersection of the underlying hardware's MSR (i.e., features which
2586          * can be supported) and the list of features we want to expose -
2587          * because they are known to be properly supported in our code.
2588          * Also, usually, the low half of the MSRs (bits which must be 1) can
2589          * be set to 0, meaning that L1 may turn off any of these bits. The
2590          * reason is that if one of these bits is necessary, it will appear
2591          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2592          * fields of vmcs01 and vmcs02, will turn these bits off - and
2593          * nested_vmx_exit_handled() will not pass related exits to L1.
2594          * These rules have exceptions below.
2595          */
2596
2597         /* pin-based controls */
2598         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2599                 vmx->nested.nested_vmx_pinbased_ctls_low,
2600                 vmx->nested.nested_vmx_pinbased_ctls_high);
2601         vmx->nested.nested_vmx_pinbased_ctls_low |=
2602                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2603         vmx->nested.nested_vmx_pinbased_ctls_high &=
2604                 PIN_BASED_EXT_INTR_MASK |
2605                 PIN_BASED_NMI_EXITING |
2606                 PIN_BASED_VIRTUAL_NMIS;
2607         vmx->nested.nested_vmx_pinbased_ctls_high |=
2608                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2609                 PIN_BASED_VMX_PREEMPTION_TIMER;
2610         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2611                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2612                         PIN_BASED_POSTED_INTR;
2613
2614         /* exit controls */
2615         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2616                 vmx->nested.nested_vmx_exit_ctls_low,
2617                 vmx->nested.nested_vmx_exit_ctls_high);
2618         vmx->nested.nested_vmx_exit_ctls_low =
2619                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2620
2621         vmx->nested.nested_vmx_exit_ctls_high &=
2622 #ifdef CONFIG_X86_64
2623                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2624 #endif
2625                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2626         vmx->nested.nested_vmx_exit_ctls_high |=
2627                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2628                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2629                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2630
2631         if (kvm_mpx_supported())
2632                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2633
2634         /* We support free control of debug control saving. */
2635         vmx->nested.nested_vmx_true_exit_ctls_low =
2636                 vmx->nested.nested_vmx_exit_ctls_low &
2637                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2638
2639         /* entry controls */
2640         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2641                 vmx->nested.nested_vmx_entry_ctls_low,
2642                 vmx->nested.nested_vmx_entry_ctls_high);
2643         vmx->nested.nested_vmx_entry_ctls_low =
2644                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2645         vmx->nested.nested_vmx_entry_ctls_high &=
2646 #ifdef CONFIG_X86_64
2647                 VM_ENTRY_IA32E_MODE |
2648 #endif
2649                 VM_ENTRY_LOAD_IA32_PAT;
2650         vmx->nested.nested_vmx_entry_ctls_high |=
2651                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2652         if (kvm_mpx_supported())
2653                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2654
2655         /* We support free control of debug control loading. */
2656         vmx->nested.nested_vmx_true_entry_ctls_low =
2657                 vmx->nested.nested_vmx_entry_ctls_low &
2658                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2659
2660         /* cpu-based controls */
2661         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2662                 vmx->nested.nested_vmx_procbased_ctls_low,
2663                 vmx->nested.nested_vmx_procbased_ctls_high);
2664         vmx->nested.nested_vmx_procbased_ctls_low =
2665                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2666         vmx->nested.nested_vmx_procbased_ctls_high &=
2667                 CPU_BASED_VIRTUAL_INTR_PENDING |
2668                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2669                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2670                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2671                 CPU_BASED_CR3_STORE_EXITING |
2672 #ifdef CONFIG_X86_64
2673                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2674 #endif
2675                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2676                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2677                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2678                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2679                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2680         /*
2681          * We can allow some features even when not supported by the
2682          * hardware. For example, L1 can specify an MSR bitmap - and we
2683          * can use it to avoid exits to L1 - even when L0 runs L2
2684          * without MSR bitmaps.
2685          */
2686         vmx->nested.nested_vmx_procbased_ctls_high |=
2687                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2688                 CPU_BASED_USE_MSR_BITMAPS;
2689
2690         /* We support free control of CR3 access interception. */
2691         vmx->nested.nested_vmx_true_procbased_ctls_low =
2692                 vmx->nested.nested_vmx_procbased_ctls_low &
2693                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2694
2695         /* secondary cpu-based controls */
2696         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2697                 vmx->nested.nested_vmx_secondary_ctls_low,
2698                 vmx->nested.nested_vmx_secondary_ctls_high);
2699         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2700         vmx->nested.nested_vmx_secondary_ctls_high &=
2701                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2702                 SECONDARY_EXEC_RDTSCP |
2703                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2704                 SECONDARY_EXEC_ENABLE_VPID |
2705                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2706                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2707                 SECONDARY_EXEC_WBINVD_EXITING |
2708                 SECONDARY_EXEC_XSAVES |
2709                 SECONDARY_EXEC_PCOMMIT;
2710
2711         if (enable_ept) {
2712                 /* nested EPT: emulate EPT also to L1 */
2713                 vmx->nested.nested_vmx_secondary_ctls_high |=
2714                         SECONDARY_EXEC_ENABLE_EPT;
2715                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2716                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2717                          VMX_EPT_INVEPT_BIT;
2718                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2719                 /*
2720                  * For nested guests, we don't do anything specific
2721                  * for single context invalidation. Hence, only advertise
2722                  * support for global context invalidation.
2723                  */
2724                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2725         } else
2726                 vmx->nested.nested_vmx_ept_caps = 0;
2727
2728         /*
2729          * Old versions of KVM use the single-context version without
2730          * checking for support, so declare that it is supported even
2731          * though it is treated as global context.  The alternative is
2732          * not failing the single-context invvpid, and it is worse.
2733          */
2734         if (enable_vpid)
2735                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2736                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2737                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2738         else
2739                 vmx->nested.nested_vmx_vpid_caps = 0;
2740
2741         if (enable_unrestricted_guest)
2742                 vmx->nested.nested_vmx_secondary_ctls_high |=
2743                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2744
2745         /* miscellaneous data */
2746         rdmsr(MSR_IA32_VMX_MISC,
2747                 vmx->nested.nested_vmx_misc_low,
2748                 vmx->nested.nested_vmx_misc_high);
2749         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2750         vmx->nested.nested_vmx_misc_low |=
2751                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2752                 VMX_MISC_ACTIVITY_HLT;
2753         vmx->nested.nested_vmx_misc_high = 0;
2754 }
2755
2756 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2757 {
2758         /*
2759          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2760          */
2761         return ((control & high) | low) == control;
2762 }
2763
2764 static inline u64 vmx_control_msr(u32 low, u32 high)
2765 {
2766         return low | ((u64)high << 32);
2767 }
2768
2769 /* Returns 0 on success, non-0 otherwise. */
2770 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2771 {
2772         struct vcpu_vmx *vmx = to_vmx(vcpu);
2773
2774         switch (msr_index) {
2775         case MSR_IA32_VMX_BASIC:
2776                 /*
2777                  * This MSR reports some information about VMX support. We
2778                  * should return information about the VMX we emulate for the
2779                  * guest, and the VMCS structure we give it - not about the
2780                  * VMX support of the underlying hardware.
2781                  */
2782                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2783                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2784                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2785                 break;
2786         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2787         case MSR_IA32_VMX_PINBASED_CTLS:
2788                 *pdata = vmx_control_msr(
2789                         vmx->nested.nested_vmx_pinbased_ctls_low,
2790                         vmx->nested.nested_vmx_pinbased_ctls_high);
2791                 break;
2792         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2793                 *pdata = vmx_control_msr(
2794                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2795                         vmx->nested.nested_vmx_procbased_ctls_high);
2796                 break;
2797         case MSR_IA32_VMX_PROCBASED_CTLS:
2798                 *pdata = vmx_control_msr(
2799                         vmx->nested.nested_vmx_procbased_ctls_low,
2800                         vmx->nested.nested_vmx_procbased_ctls_high);
2801                 break;
2802         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2803                 *pdata = vmx_control_msr(
2804                         vmx->nested.nested_vmx_true_exit_ctls_low,
2805                         vmx->nested.nested_vmx_exit_ctls_high);
2806                 break;
2807         case MSR_IA32_VMX_EXIT_CTLS:
2808                 *pdata = vmx_control_msr(
2809                         vmx->nested.nested_vmx_exit_ctls_low,
2810                         vmx->nested.nested_vmx_exit_ctls_high);
2811                 break;
2812         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2813                 *pdata = vmx_control_msr(
2814                         vmx->nested.nested_vmx_true_entry_ctls_low,
2815                         vmx->nested.nested_vmx_entry_ctls_high);
2816                 break;
2817         case MSR_IA32_VMX_ENTRY_CTLS:
2818                 *pdata = vmx_control_msr(
2819                         vmx->nested.nested_vmx_entry_ctls_low,
2820                         vmx->nested.nested_vmx_entry_ctls_high);
2821                 break;
2822         case MSR_IA32_VMX_MISC:
2823                 *pdata = vmx_control_msr(
2824                         vmx->nested.nested_vmx_misc_low,
2825                         vmx->nested.nested_vmx_misc_high);
2826                 break;
2827         /*
2828          * These MSRs specify bits which the guest must keep fixed (on or off)
2829          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2830          * We picked the standard core2 setting.
2831          */
2832 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2833 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2834         case MSR_IA32_VMX_CR0_FIXED0:
2835                 *pdata = VMXON_CR0_ALWAYSON;
2836                 break;
2837         case MSR_IA32_VMX_CR0_FIXED1:
2838                 *pdata = -1ULL;
2839                 break;
2840         case MSR_IA32_VMX_CR4_FIXED0:
2841                 *pdata = VMXON_CR4_ALWAYSON;
2842                 break;
2843         case MSR_IA32_VMX_CR4_FIXED1:
2844                 *pdata = -1ULL;
2845                 break;
2846         case MSR_IA32_VMX_VMCS_ENUM:
2847                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2848                 break;
2849         case MSR_IA32_VMX_PROCBASED_CTLS2:
2850                 *pdata = vmx_control_msr(
2851                         vmx->nested.nested_vmx_secondary_ctls_low,
2852                         vmx->nested.nested_vmx_secondary_ctls_high);
2853                 break;
2854         case MSR_IA32_VMX_EPT_VPID_CAP:
2855                 /* Currently, no nested vpid support */
2856                 *pdata = vmx->nested.nested_vmx_ept_caps |
2857                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2858                 break;
2859         default:
2860                 return 1;
2861         }
2862
2863         return 0;
2864 }
2865
2866 /*
2867  * Reads an msr value (of 'msr_index') into 'pdata'.
2868  * Returns 0 on success, non-0 otherwise.
2869  * Assumes vcpu_load() was already called.
2870  */
2871 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2872 {
2873         struct shared_msr_entry *msr;
2874
2875         switch (msr_info->index) {
2876 #ifdef CONFIG_X86_64
2877         case MSR_FS_BASE:
2878                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2879                 break;
2880         case MSR_GS_BASE:
2881                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2882                 break;
2883         case MSR_KERNEL_GS_BASE:
2884                 vmx_load_host_state(to_vmx(vcpu));
2885                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2886                 break;
2887 #endif
2888         case MSR_EFER:
2889                 return kvm_get_msr_common(vcpu, msr_info);
2890         case MSR_IA32_TSC:
2891                 msr_info->data = guest_read_tsc(vcpu);
2892                 break;
2893         case MSR_IA32_SYSENTER_CS:
2894                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2895                 break;
2896         case MSR_IA32_SYSENTER_EIP:
2897                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2898                 break;
2899         case MSR_IA32_SYSENTER_ESP:
2900                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2901                 break;
2902         case MSR_IA32_BNDCFGS:
2903                 if (!kvm_mpx_supported())
2904                         return 1;
2905                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2906                 break;
2907         case MSR_IA32_FEATURE_CONTROL:
2908                 if (!nested_vmx_allowed(vcpu))
2909                         return 1;
2910                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2911                 break;
2912         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2913                 if (!nested_vmx_allowed(vcpu))
2914                         return 1;
2915                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2916         case MSR_IA32_XSS:
2917                 if (!vmx_xsaves_supported())
2918                         return 1;
2919                 msr_info->data = vcpu->arch.ia32_xss;
2920                 break;
2921         case MSR_TSC_AUX:
2922                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2923                         return 1;
2924                 /* Otherwise falls through */
2925         default:
2926                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2927                 if (msr) {
2928                         msr_info->data = msr->data;
2929                         break;
2930                 }
2931                 return kvm_get_msr_common(vcpu, msr_info);
2932         }
2933
2934         return 0;
2935 }
2936
2937 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2938
2939 /*
2940  * Writes msr value into into the appropriate "register".
2941  * Returns 0 on success, non-0 otherwise.
2942  * Assumes vcpu_load() was already called.
2943  */
2944 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2945 {
2946         struct vcpu_vmx *vmx = to_vmx(vcpu);
2947         struct shared_msr_entry *msr;
2948         int ret = 0;
2949         u32 msr_index = msr_info->index;
2950         u64 data = msr_info->data;
2951
2952         switch (msr_index) {
2953         case MSR_EFER:
2954                 ret = kvm_set_msr_common(vcpu, msr_info);
2955                 break;
2956 #ifdef CONFIG_X86_64
2957         case MSR_FS_BASE:
2958                 vmx_segment_cache_clear(vmx);
2959                 vmcs_writel(GUEST_FS_BASE, data);
2960                 break;
2961         case MSR_GS_BASE:
2962                 vmx_segment_cache_clear(vmx);
2963                 vmcs_writel(GUEST_GS_BASE, data);
2964                 break;
2965         case MSR_KERNEL_GS_BASE:
2966                 vmx_load_host_state(vmx);
2967                 vmx->msr_guest_kernel_gs_base = data;
2968                 break;
2969 #endif
2970         case MSR_IA32_SYSENTER_CS:
2971                 vmcs_write32(GUEST_SYSENTER_CS, data);
2972                 break;
2973         case MSR_IA32_SYSENTER_EIP:
2974                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2975                 break;
2976         case MSR_IA32_SYSENTER_ESP:
2977                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2978                 break;
2979         case MSR_IA32_BNDCFGS:
2980                 if (!kvm_mpx_supported())
2981                         return 1;
2982                 vmcs_write64(GUEST_BNDCFGS, data);
2983                 break;
2984         case MSR_IA32_TSC:
2985                 kvm_write_tsc(vcpu, msr_info);
2986                 break;
2987         case MSR_IA32_CR_PAT:
2988                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2989                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2990                                 return 1;
2991                         vmcs_write64(GUEST_IA32_PAT, data);
2992                         vcpu->arch.pat = data;
2993                         break;
2994                 }
2995                 ret = kvm_set_msr_common(vcpu, msr_info);
2996                 break;
2997         case MSR_IA32_TSC_ADJUST:
2998                 ret = kvm_set_msr_common(vcpu, msr_info);
2999                 break;
3000         case MSR_IA32_FEATURE_CONTROL:
3001                 if (!nested_vmx_allowed(vcpu) ||
3002                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
3003                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3004                         return 1;
3005                 vmx->nested.msr_ia32_feature_control = data;
3006                 if (msr_info->host_initiated && data == 0)
3007                         vmx_leave_nested(vcpu);
3008                 break;
3009         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3010                 return 1; /* they are read-only */
3011         case MSR_IA32_XSS:
3012                 if (!vmx_xsaves_supported())
3013                         return 1;
3014                 /*
3015                  * The only supported bit as of Skylake is bit 8, but
3016                  * it is not supported on KVM.
3017                  */
3018                 if (data != 0)
3019                         return 1;
3020                 vcpu->arch.ia32_xss = data;
3021                 if (vcpu->arch.ia32_xss != host_xss)
3022                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3023                                 vcpu->arch.ia32_xss, host_xss);
3024                 else
3025                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3026                 break;
3027         case MSR_TSC_AUX:
3028                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3029                         return 1;
3030                 /* Check reserved bit, higher 32 bits should be zero */
3031                 if ((data >> 32) != 0)
3032                         return 1;
3033                 /* Otherwise falls through */
3034         default:
3035                 msr = find_msr_entry(vmx, msr_index);
3036                 if (msr) {
3037                         u64 old_msr_data = msr->data;
3038                         msr->data = data;
3039                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3040                                 preempt_disable();
3041                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3042                                                          msr->mask);
3043                                 preempt_enable();
3044                                 if (ret)
3045                                         msr->data = old_msr_data;
3046                         }
3047                         break;
3048                 }
3049                 ret = kvm_set_msr_common(vcpu, msr_info);
3050         }
3051
3052         return ret;
3053 }
3054
3055 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3056 {
3057         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3058         switch (reg) {
3059         case VCPU_REGS_RSP:
3060                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3061                 break;
3062         case VCPU_REGS_RIP:
3063                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3064                 break;
3065         case VCPU_EXREG_PDPTR:
3066                 if (enable_ept)
3067                         ept_save_pdptrs(vcpu);
3068                 break;
3069         default:
3070                 break;
3071         }
3072 }
3073
3074 static __init int cpu_has_kvm_support(void)
3075 {
3076         return cpu_has_vmx();
3077 }
3078
3079 static __init int vmx_disabled_by_bios(void)
3080 {
3081         u64 msr;
3082
3083         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3084         if (msr & FEATURE_CONTROL_LOCKED) {
3085                 /* launched w/ TXT and VMX disabled */
3086                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3087                         && tboot_enabled())
3088                         return 1;
3089                 /* launched w/o TXT and VMX only enabled w/ TXT */
3090                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3091                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3092                         && !tboot_enabled()) {
3093                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3094                                 "activate TXT before enabling KVM\n");
3095                         return 1;
3096                 }
3097                 /* launched w/o TXT and VMX disabled */
3098                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3099                         && !tboot_enabled())
3100                         return 1;
3101         }
3102
3103         return 0;
3104 }
3105
3106 static void kvm_cpu_vmxon(u64 addr)
3107 {
3108         intel_pt_handle_vmx(1);
3109
3110         asm volatile (ASM_VMX_VMXON_RAX
3111                         : : "a"(&addr), "m"(addr)
3112                         : "memory", "cc");
3113 }
3114
3115 static int hardware_enable(void)
3116 {
3117         int cpu = raw_smp_processor_id();
3118         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3119         u64 old, test_bits;
3120
3121         if (cr4_read_shadow() & X86_CR4_VMXE)
3122                 return -EBUSY;
3123
3124         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3125         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3126         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3127
3128         /*
3129          * Now we can enable the vmclear operation in kdump
3130          * since the loaded_vmcss_on_cpu list on this cpu
3131          * has been initialized.
3132          *
3133          * Though the cpu is not in VMX operation now, there
3134          * is no problem to enable the vmclear operation
3135          * for the loaded_vmcss_on_cpu list is empty!
3136          */
3137         crash_enable_local_vmclear(cpu);
3138
3139         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3140
3141         test_bits = FEATURE_CONTROL_LOCKED;
3142         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3143         if (tboot_enabled())
3144                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3145
3146         if ((old & test_bits) != test_bits) {
3147                 /* enable and lock */
3148                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3149         }
3150         cr4_set_bits(X86_CR4_VMXE);
3151
3152         if (vmm_exclusive) {
3153                 kvm_cpu_vmxon(phys_addr);
3154                 ept_sync_global();
3155         }
3156
3157         native_store_gdt(this_cpu_ptr(&host_gdt));
3158
3159         return 0;
3160 }
3161
3162 static void vmclear_local_loaded_vmcss(void)
3163 {
3164         int cpu = raw_smp_processor_id();
3165         struct loaded_vmcs *v, *n;
3166
3167         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3168                                  loaded_vmcss_on_cpu_link)
3169                 __loaded_vmcs_clear(v);
3170 }
3171
3172
3173 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3174  * tricks.
3175  */
3176 static void kvm_cpu_vmxoff(void)
3177 {
3178         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3179
3180         intel_pt_handle_vmx(0);
3181 }
3182
3183 static void hardware_disable(void)
3184 {
3185         if (vmm_exclusive) {
3186                 vmclear_local_loaded_vmcss();
3187                 kvm_cpu_vmxoff();
3188         }
3189         cr4_clear_bits(X86_CR4_VMXE);
3190 }
3191
3192 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3193                                       u32 msr, u32 *result)
3194 {
3195         u32 vmx_msr_low, vmx_msr_high;
3196         u32 ctl = ctl_min | ctl_opt;
3197
3198         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3199
3200         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3201         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3202
3203         /* Ensure minimum (required) set of control bits are supported. */
3204         if (ctl_min & ~ctl)
3205                 return -EIO;
3206
3207         *result = ctl;
3208         return 0;
3209 }
3210
3211 static __init bool allow_1_setting(u32 msr, u32 ctl)
3212 {
3213         u32 vmx_msr_low, vmx_msr_high;
3214
3215         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3216         return vmx_msr_high & ctl;
3217 }
3218
3219 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3220 {
3221         u32 vmx_msr_low, vmx_msr_high;
3222         u32 min, opt, min2, opt2;
3223         u32 _pin_based_exec_control = 0;
3224         u32 _cpu_based_exec_control = 0;
3225         u32 _cpu_based_2nd_exec_control = 0;
3226         u32 _vmexit_control = 0;
3227         u32 _vmentry_control = 0;
3228
3229         min = CPU_BASED_HLT_EXITING |
3230 #ifdef CONFIG_X86_64
3231               CPU_BASED_CR8_LOAD_EXITING |
3232               CPU_BASED_CR8_STORE_EXITING |
3233 #endif
3234               CPU_BASED_CR3_LOAD_EXITING |
3235               CPU_BASED_CR3_STORE_EXITING |
3236               CPU_BASED_USE_IO_BITMAPS |
3237               CPU_BASED_MOV_DR_EXITING |
3238               CPU_BASED_USE_TSC_OFFSETING |
3239               CPU_BASED_MWAIT_EXITING |
3240               CPU_BASED_MONITOR_EXITING |
3241               CPU_BASED_INVLPG_EXITING |
3242               CPU_BASED_RDPMC_EXITING;
3243
3244         opt = CPU_BASED_TPR_SHADOW |
3245               CPU_BASED_USE_MSR_BITMAPS |
3246               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3247         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3248                                 &_cpu_based_exec_control) < 0)
3249                 return -EIO;
3250 #ifdef CONFIG_X86_64
3251         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3252                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3253                                            ~CPU_BASED_CR8_STORE_EXITING;
3254 #endif
3255         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3256                 min2 = 0;
3257                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3258                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3259                         SECONDARY_EXEC_WBINVD_EXITING |
3260                         SECONDARY_EXEC_ENABLE_VPID |
3261                         SECONDARY_EXEC_ENABLE_EPT |
3262                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3263                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3264                         SECONDARY_EXEC_RDTSCP |
3265                         SECONDARY_EXEC_ENABLE_INVPCID |
3266                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3267                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3268                         SECONDARY_EXEC_SHADOW_VMCS |
3269                         SECONDARY_EXEC_XSAVES |
3270                         SECONDARY_EXEC_ENABLE_PML |
3271                         SECONDARY_EXEC_PCOMMIT |
3272                         SECONDARY_EXEC_TSC_SCALING;
3273                 if (adjust_vmx_controls(min2, opt2,
3274                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3275                                         &_cpu_based_2nd_exec_control) < 0)
3276                         return -EIO;
3277         }
3278 #ifndef CONFIG_X86_64
3279         if (!(_cpu_based_2nd_exec_control &
3280                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3281                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3282 #endif
3283
3284         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3285                 _cpu_based_2nd_exec_control &= ~(
3286                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3287                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3288                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3289
3290         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3291                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3292                    enabled */
3293                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3294                                              CPU_BASED_CR3_STORE_EXITING |
3295                                              CPU_BASED_INVLPG_EXITING);
3296                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3297                       vmx_capability.ept, vmx_capability.vpid);
3298         }
3299
3300         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3301 #ifdef CONFIG_X86_64
3302         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3303 #endif
3304         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3305                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3306         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3307                                 &_vmexit_control) < 0)
3308                 return -EIO;
3309
3310         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3311         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3312         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3313                                 &_pin_based_exec_control) < 0)
3314                 return -EIO;
3315
3316         if (!(_cpu_based_2nd_exec_control &
3317                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3318                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3319                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3320
3321         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3322         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3323         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3324                                 &_vmentry_control) < 0)
3325                 return -EIO;
3326
3327         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3328
3329         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3330         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3331                 return -EIO;
3332
3333 #ifdef CONFIG_X86_64
3334         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3335         if (vmx_msr_high & (1u<<16))
3336                 return -EIO;
3337 #endif
3338
3339         /* Require Write-Back (WB) memory type for VMCS accesses. */
3340         if (((vmx_msr_high >> 18) & 15) != 6)
3341                 return -EIO;
3342
3343         vmcs_conf->size = vmx_msr_high & 0x1fff;
3344         vmcs_conf->order = get_order(vmcs_config.size);
3345         vmcs_conf->revision_id = vmx_msr_low;
3346
3347         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3348         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3349         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3350         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3351         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3352
3353         cpu_has_load_ia32_efer =
3354                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3355                                 VM_ENTRY_LOAD_IA32_EFER)
3356                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3357                                    VM_EXIT_LOAD_IA32_EFER);
3358
3359         cpu_has_load_perf_global_ctrl =
3360                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3361                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3362                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3363                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3364
3365         /*
3366          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3367          * but due to arrata below it can't be used. Workaround is to use
3368          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3369          *
3370          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3371          *
3372          * AAK155             (model 26)
3373          * AAP115             (model 30)
3374          * AAT100             (model 37)
3375          * BC86,AAY89,BD102   (model 44)
3376          * BA97               (model 46)
3377          *
3378          */
3379         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3380                 switch (boot_cpu_data.x86_model) {
3381                 case 26:
3382                 case 30:
3383                 case 37:
3384                 case 44:
3385                 case 46:
3386                         cpu_has_load_perf_global_ctrl = false;
3387                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3388                                         "does not work properly. Using workaround\n");
3389                         break;
3390                 default:
3391                         break;
3392                 }
3393         }
3394
3395         if (boot_cpu_has(X86_FEATURE_XSAVES))
3396                 rdmsrl(MSR_IA32_XSS, host_xss);
3397
3398         return 0;
3399 }
3400
3401 static struct vmcs *alloc_vmcs_cpu(int cpu)
3402 {
3403         int node = cpu_to_node(cpu);
3404         struct page *pages;
3405         struct vmcs *vmcs;
3406
3407         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3408         if (!pages)
3409                 return NULL;
3410         vmcs = page_address(pages);
3411         memset(vmcs, 0, vmcs_config.size);
3412         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3413         return vmcs;
3414 }
3415
3416 static struct vmcs *alloc_vmcs(void)
3417 {
3418         return alloc_vmcs_cpu(raw_smp_processor_id());
3419 }
3420
3421 static void free_vmcs(struct vmcs *vmcs)
3422 {
3423         free_pages((unsigned long)vmcs, vmcs_config.order);
3424 }
3425
3426 /*
3427  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3428  */
3429 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3430 {
3431         if (!loaded_vmcs->vmcs)
3432                 return;
3433         loaded_vmcs_clear(loaded_vmcs);
3434         free_vmcs(loaded_vmcs->vmcs);
3435         loaded_vmcs->vmcs = NULL;
3436 }
3437
3438 static void free_kvm_area(void)
3439 {
3440         int cpu;
3441
3442         for_each_possible_cpu(cpu) {
3443                 free_vmcs(per_cpu(vmxarea, cpu));
3444                 per_cpu(vmxarea, cpu) = NULL;
3445         }
3446 }
3447
3448 static void init_vmcs_shadow_fields(void)
3449 {
3450         int i, j;
3451
3452         /* No checks for read only fields yet */
3453
3454         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3455                 switch (shadow_read_write_fields[i]) {
3456                 case GUEST_BNDCFGS:
3457                         if (!kvm_mpx_supported())
3458                                 continue;
3459                         break;
3460                 default:
3461                         break;
3462                 }
3463
3464                 if (j < i)
3465                         shadow_read_write_fields[j] =
3466                                 shadow_read_write_fields[i];
3467                 j++;
3468         }
3469         max_shadow_read_write_fields = j;
3470
3471         /* shadowed fields guest access without vmexit */
3472         for (i = 0; i < max_shadow_read_write_fields; i++) {
3473                 clear_bit(shadow_read_write_fields[i],
3474                           vmx_vmwrite_bitmap);
3475                 clear_bit(shadow_read_write_fields[i],
3476                           vmx_vmread_bitmap);
3477         }
3478         for (i = 0; i < max_shadow_read_only_fields; i++)
3479                 clear_bit(shadow_read_only_fields[i],
3480                           vmx_vmread_bitmap);
3481 }
3482
3483 static __init int alloc_kvm_area(void)
3484 {
3485         int cpu;
3486
3487         for_each_possible_cpu(cpu) {
3488                 struct vmcs *vmcs;
3489
3490                 vmcs = alloc_vmcs_cpu(cpu);
3491                 if (!vmcs) {
3492                         free_kvm_area();
3493                         return -ENOMEM;
3494                 }
3495
3496                 per_cpu(vmxarea, cpu) = vmcs;
3497         }
3498         return 0;
3499 }
3500
3501 static bool emulation_required(struct kvm_vcpu *vcpu)
3502 {
3503         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3504 }
3505
3506 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3507                 struct kvm_segment *save)
3508 {
3509         if (!emulate_invalid_guest_state) {
3510                 /*
3511                  * CS and SS RPL should be equal during guest entry according
3512                  * to VMX spec, but in reality it is not always so. Since vcpu
3513                  * is in the middle of the transition from real mode to
3514                  * protected mode it is safe to assume that RPL 0 is a good
3515                  * default value.
3516                  */
3517                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3518                         save->selector &= ~SEGMENT_RPL_MASK;
3519                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3520                 save->s = 1;
3521         }
3522         vmx_set_segment(vcpu, save, seg);
3523 }
3524
3525 static void enter_pmode(struct kvm_vcpu *vcpu)
3526 {
3527         unsigned long flags;
3528         struct vcpu_vmx *vmx = to_vmx(vcpu);
3529
3530         /*
3531          * Update real mode segment cache. It may be not up-to-date if sement
3532          * register was written while vcpu was in a guest mode.
3533          */
3534         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3535         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3536         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3537         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3538         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3539         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3540
3541         vmx->rmode.vm86_active = 0;
3542
3543         vmx_segment_cache_clear(vmx);
3544
3545         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3546
3547         flags = vmcs_readl(GUEST_RFLAGS);
3548         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3549         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3550         vmcs_writel(GUEST_RFLAGS, flags);
3551
3552         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3553                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3554
3555         update_exception_bitmap(vcpu);
3556
3557         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3558         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3559         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3560         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3561         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3562         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3563 }
3564
3565 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3566 {
3567         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3568         struct kvm_segment var = *save;
3569
3570         var.dpl = 0x3;
3571         if (seg == VCPU_SREG_CS)
3572                 var.type = 0x3;
3573
3574         if (!emulate_invalid_guest_state) {
3575                 var.selector = var.base >> 4;
3576                 var.base = var.base & 0xffff0;
3577                 var.limit = 0xffff;
3578                 var.g = 0;
3579                 var.db = 0;
3580                 var.present = 1;
3581                 var.s = 1;
3582                 var.l = 0;
3583                 var.unusable = 0;
3584                 var.type = 0x3;
3585                 var.avl = 0;
3586                 if (save->base & 0xf)
3587                         printk_once(KERN_WARNING "kvm: segment base is not "
3588                                         "paragraph aligned when entering "
3589                                         "protected mode (seg=%d)", seg);
3590         }
3591
3592         vmcs_write16(sf->selector, var.selector);
3593         vmcs_write32(sf->base, var.base);
3594         vmcs_write32(sf->limit, var.limit);
3595         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3596 }
3597
3598 static void enter_rmode(struct kvm_vcpu *vcpu)
3599 {
3600         unsigned long flags;
3601         struct vcpu_vmx *vmx = to_vmx(vcpu);
3602
3603         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3604         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3605         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3606         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3607         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3608         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3609         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3610
3611         vmx->rmode.vm86_active = 1;
3612
3613         /*
3614          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3615          * vcpu. Warn the user that an update is overdue.
3616          */
3617         if (!vcpu->kvm->arch.tss_addr)
3618                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3619                              "called before entering vcpu\n");
3620
3621         vmx_segment_cache_clear(vmx);
3622
3623         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3624         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3625         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3626
3627         flags = vmcs_readl(GUEST_RFLAGS);
3628         vmx->rmode.save_rflags = flags;
3629
3630         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3631
3632         vmcs_writel(GUEST_RFLAGS, flags);
3633         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3634         update_exception_bitmap(vcpu);
3635
3636         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3637         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3638         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3639         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3640         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3641         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3642
3643         kvm_mmu_reset_context(vcpu);
3644 }
3645
3646 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3647 {
3648         struct vcpu_vmx *vmx = to_vmx(vcpu);
3649         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3650
3651         if (!msr)
3652                 return;
3653
3654         /*
3655          * Force kernel_gs_base reloading before EFER changes, as control
3656          * of this msr depends on is_long_mode().
3657          */
3658         vmx_load_host_state(to_vmx(vcpu));
3659         vcpu->arch.efer = efer;
3660         if (efer & EFER_LMA) {
3661                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3662                 msr->data = efer;
3663         } else {
3664                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3665
3666                 msr->data = efer & ~EFER_LME;
3667         }
3668         setup_msrs(vmx);
3669 }
3670
3671 #ifdef CONFIG_X86_64
3672
3673 static void enter_lmode(struct kvm_vcpu *vcpu)
3674 {
3675         u32 guest_tr_ar;
3676
3677         vmx_segment_cache_clear(to_vmx(vcpu));
3678
3679         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3680         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3681                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3682                                      __func__);
3683                 vmcs_write32(GUEST_TR_AR_BYTES,
3684                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3685                              | VMX_AR_TYPE_BUSY_64_TSS);
3686         }
3687         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3688 }
3689
3690 static void exit_lmode(struct kvm_vcpu *vcpu)
3691 {
3692         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3693         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3694 }
3695
3696 #endif
3697
3698 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3699 {
3700         vpid_sync_context(vpid);
3701         if (enable_ept) {
3702                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3703                         return;
3704                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3705         }
3706 }
3707
3708 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3709 {
3710         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3711 }
3712
3713 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3714 {
3715         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3716
3717         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3718         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3719 }
3720
3721 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3722 {
3723         if (enable_ept && is_paging(vcpu))
3724                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3725         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3726 }
3727
3728 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3729 {
3730         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3731
3732         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3733         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3734 }
3735
3736 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3737 {
3738         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3739
3740         if (!test_bit(VCPU_EXREG_PDPTR,
3741                       (unsigned long *)&vcpu->arch.regs_dirty))
3742                 return;
3743
3744         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3745                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3746                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3747                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3748                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3749         }
3750 }
3751
3752 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3753 {
3754         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3755
3756         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3757                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3758                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3759                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3760                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3761         }
3762
3763         __set_bit(VCPU_EXREG_PDPTR,
3764                   (unsigned long *)&vcpu->arch.regs_avail);
3765         __set_bit(VCPU_EXREG_PDPTR,
3766                   (unsigned long *)&vcpu->arch.regs_dirty);
3767 }
3768
3769 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3770
3771 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3772                                         unsigned long cr0,
3773                                         struct kvm_vcpu *vcpu)
3774 {
3775         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3776                 vmx_decache_cr3(vcpu);
3777         if (!(cr0 & X86_CR0_PG)) {
3778                 /* From paging/starting to nonpaging */
3779                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3780                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3781                              (CPU_BASED_CR3_LOAD_EXITING |
3782                               CPU_BASED_CR3_STORE_EXITING));
3783                 vcpu->arch.cr0 = cr0;
3784                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3785         } else if (!is_paging(vcpu)) {
3786                 /* From nonpaging to paging */
3787                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3788                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3789                              ~(CPU_BASED_CR3_LOAD_EXITING |
3790                                CPU_BASED_CR3_STORE_EXITING));
3791                 vcpu->arch.cr0 = cr0;
3792                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3793         }
3794
3795         if (!(cr0 & X86_CR0_WP))
3796                 *hw_cr0 &= ~X86_CR0_WP;
3797 }
3798
3799 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3800 {
3801         struct vcpu_vmx *vmx = to_vmx(vcpu);
3802         unsigned long hw_cr0;
3803
3804         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3805         if (enable_unrestricted_guest)
3806                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3807         else {
3808                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3809
3810                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3811                         enter_pmode(vcpu);
3812
3813                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3814                         enter_rmode(vcpu);
3815         }
3816
3817 #ifdef CONFIG_X86_64
3818         if (vcpu->arch.efer & EFER_LME) {
3819                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3820                         enter_lmode(vcpu);
3821                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3822                         exit_lmode(vcpu);
3823         }
3824 #endif
3825
3826         if (enable_ept)
3827                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3828
3829         if (!vcpu->fpu_active)
3830                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3831
3832         vmcs_writel(CR0_READ_SHADOW, cr0);
3833         vmcs_writel(GUEST_CR0, hw_cr0);
3834         vcpu->arch.cr0 = cr0;
3835
3836         /* depends on vcpu->arch.cr0 to be set to a new value */
3837         vmx->emulation_required = emulation_required(vcpu);
3838 }
3839
3840 static u64 construct_eptp(unsigned long root_hpa)
3841 {
3842         u64 eptp;
3843
3844         /* TODO write the value reading from MSR */
3845         eptp = VMX_EPT_DEFAULT_MT |
3846                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3847         if (enable_ept_ad_bits)
3848                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3849         eptp |= (root_hpa & PAGE_MASK);
3850
3851         return eptp;
3852 }
3853
3854 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3855 {
3856         unsigned long guest_cr3;
3857         u64 eptp;
3858
3859         guest_cr3 = cr3;
3860         if (enable_ept) {
3861                 eptp = construct_eptp(cr3);
3862                 vmcs_write64(EPT_POINTER, eptp);
3863                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3864                         guest_cr3 = kvm_read_cr3(vcpu);
3865                 else
3866                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3867                 ept_load_pdptrs(vcpu);
3868         }
3869
3870         vmx_flush_tlb(vcpu);
3871         vmcs_writel(GUEST_CR3, guest_cr3);
3872 }
3873
3874 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3875 {
3876         /*
3877          * Pass through host's Machine Check Enable value to hw_cr4, which
3878          * is in force while we are in guest mode.  Do not let guests control
3879          * this bit, even if host CR4.MCE == 0.
3880          */
3881         unsigned long hw_cr4 =
3882                 (cr4_read_shadow() & X86_CR4_MCE) |
3883                 (cr4 & ~X86_CR4_MCE) |
3884                 (to_vmx(vcpu)->rmode.vm86_active ?
3885                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3886
3887         if (cr4 & X86_CR4_VMXE) {
3888                 /*
3889                  * To use VMXON (and later other VMX instructions), a guest
3890                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3891                  * So basically the check on whether to allow nested VMX
3892                  * is here.
3893                  */
3894                 if (!nested_vmx_allowed(vcpu))
3895                         return 1;
3896         }
3897         if (to_vmx(vcpu)->nested.vmxon &&
3898             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3899                 return 1;
3900
3901         vcpu->arch.cr4 = cr4;
3902         if (enable_ept) {
3903                 if (!is_paging(vcpu)) {
3904                         hw_cr4 &= ~X86_CR4_PAE;
3905                         hw_cr4 |= X86_CR4_PSE;
3906                 } else if (!(cr4 & X86_CR4_PAE)) {
3907                         hw_cr4 &= ~X86_CR4_PAE;
3908                 }
3909         }
3910
3911         if (!enable_unrestricted_guest && !is_paging(vcpu))
3912                 /*
3913                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3914                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3915                  * to be manually disabled when guest switches to non-paging
3916                  * mode.
3917                  *
3918                  * If !enable_unrestricted_guest, the CPU is always running
3919                  * with CR0.PG=1 and CR4 needs to be modified.
3920                  * If enable_unrestricted_guest, the CPU automatically
3921                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3922                  */
3923                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3924
3925         vmcs_writel(CR4_READ_SHADOW, cr4);
3926         vmcs_writel(GUEST_CR4, hw_cr4);
3927         return 0;
3928 }
3929
3930 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3931                             struct kvm_segment *var, int seg)
3932 {
3933         struct vcpu_vmx *vmx = to_vmx(vcpu);
3934         u32 ar;
3935
3936         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3937                 *var = vmx->rmode.segs[seg];
3938                 if (seg == VCPU_SREG_TR
3939                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3940                         return;
3941                 var->base = vmx_read_guest_seg_base(vmx, seg);
3942                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3943                 return;
3944         }
3945         var->base = vmx_read_guest_seg_base(vmx, seg);
3946         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3947         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3948         ar = vmx_read_guest_seg_ar(vmx, seg);
3949         var->unusable = (ar >> 16) & 1;
3950         var->type = ar & 15;
3951         var->s = (ar >> 4) & 1;
3952         var->dpl = (ar >> 5) & 3;
3953         /*
3954          * Some userspaces do not preserve unusable property. Since usable
3955          * segment has to be present according to VMX spec we can use present
3956          * property to amend userspace bug by making unusable segment always
3957          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3958          * segment as unusable.
3959          */
3960         var->present = !var->unusable;
3961         var->avl = (ar >> 12) & 1;
3962         var->l = (ar >> 13) & 1;
3963         var->db = (ar >> 14) & 1;
3964         var->g = (ar >> 15) & 1;
3965 }
3966
3967 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3968 {
3969         struct kvm_segment s;
3970
3971         if (to_vmx(vcpu)->rmode.vm86_active) {
3972                 vmx_get_segment(vcpu, &s, seg);
3973                 return s.base;
3974         }
3975         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3976 }
3977
3978 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3979 {
3980         struct vcpu_vmx *vmx = to_vmx(vcpu);
3981
3982         if (unlikely(vmx->rmode.vm86_active))
3983                 return 0;
3984         else {
3985                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3986                 return VMX_AR_DPL(ar);
3987         }
3988 }
3989
3990 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3991 {
3992         u32 ar;
3993
3994         if (var->unusable || !var->present)
3995                 ar = 1 << 16;
3996         else {
3997                 ar = var->type & 15;
3998                 ar |= (var->s & 1) << 4;
3999                 ar |= (var->dpl & 3) << 5;
4000                 ar |= (var->present & 1) << 7;
4001                 ar |= (var->avl & 1) << 12;
4002                 ar |= (var->l & 1) << 13;
4003                 ar |= (var->db & 1) << 14;
4004                 ar |= (var->g & 1) << 15;
4005         }
4006
4007         return ar;
4008 }
4009
4010 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4011                             struct kvm_segment *var, int seg)
4012 {
4013         struct vcpu_vmx *vmx = to_vmx(vcpu);
4014         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4015
4016         vmx_segment_cache_clear(vmx);
4017
4018         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4019                 vmx->rmode.segs[seg] = *var;
4020                 if (seg == VCPU_SREG_TR)
4021                         vmcs_write16(sf->selector, var->selector);
4022                 else if (var->s)
4023                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4024                 goto out;
4025         }
4026
4027         vmcs_writel(sf->base, var->base);
4028         vmcs_write32(sf->limit, var->limit);
4029         vmcs_write16(sf->selector, var->selector);
4030
4031         /*
4032          *   Fix the "Accessed" bit in AR field of segment registers for older
4033          * qemu binaries.
4034          *   IA32 arch specifies that at the time of processor reset the
4035          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4036          * is setting it to 0 in the userland code. This causes invalid guest
4037          * state vmexit when "unrestricted guest" mode is turned on.
4038          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4039          * tree. Newer qemu binaries with that qemu fix would not need this
4040          * kvm hack.
4041          */
4042         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4043                 var->type |= 0x1; /* Accessed */
4044
4045         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4046
4047 out:
4048         vmx->emulation_required = emulation_required(vcpu);
4049 }
4050
4051 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4052 {
4053         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4054
4055         *db = (ar >> 14) & 1;
4056         *l = (ar >> 13) & 1;
4057 }
4058
4059 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4060 {
4061         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4062         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4063 }
4064
4065 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4066 {
4067         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4068         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4069 }
4070
4071 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4072 {
4073         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4074         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4075 }
4076
4077 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4078 {
4079         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4080         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4081 }
4082
4083 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4084 {
4085         struct kvm_segment var;
4086         u32 ar;
4087
4088         vmx_get_segment(vcpu, &var, seg);
4089         var.dpl = 0x3;
4090         if (seg == VCPU_SREG_CS)
4091                 var.type = 0x3;
4092         ar = vmx_segment_access_rights(&var);
4093
4094         if (var.base != (var.selector << 4))
4095                 return false;
4096         if (var.limit != 0xffff)
4097                 return false;
4098         if (ar != 0xf3)
4099                 return false;
4100
4101         return true;
4102 }
4103
4104 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4105 {
4106         struct kvm_segment cs;
4107         unsigned int cs_rpl;
4108
4109         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4110         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4111
4112         if (cs.unusable)
4113                 return false;
4114         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4115                 return false;
4116         if (!cs.s)
4117                 return false;
4118         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4119                 if (cs.dpl > cs_rpl)
4120                         return false;
4121         } else {
4122                 if (cs.dpl != cs_rpl)
4123                         return false;
4124         }
4125         if (!cs.present)
4126                 return false;
4127
4128         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4129         return true;
4130 }
4131
4132 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4133 {
4134         struct kvm_segment ss;
4135         unsigned int ss_rpl;
4136
4137         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4138         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4139
4140         if (ss.unusable)
4141                 return true;
4142         if (ss.type != 3 && ss.type != 7)
4143                 return false;
4144         if (!ss.s)
4145                 return false;
4146         if (ss.dpl != ss_rpl) /* DPL != RPL */
4147                 return false;
4148         if (!ss.present)
4149                 return false;
4150
4151         return true;
4152 }
4153
4154 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4155 {
4156         struct kvm_segment var;
4157         unsigned int rpl;
4158
4159         vmx_get_segment(vcpu, &var, seg);
4160         rpl = var.selector & SEGMENT_RPL_MASK;
4161
4162         if (var.unusable)
4163                 return true;
4164         if (!var.s)
4165                 return false;
4166         if (!var.present)
4167                 return false;
4168         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4169                 if (var.dpl < rpl) /* DPL < RPL */
4170                         return false;
4171         }
4172
4173         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4174          * rights flags
4175          */
4176         return true;
4177 }
4178
4179 static bool tr_valid(struct kvm_vcpu *vcpu)
4180 {
4181         struct kvm_segment tr;
4182
4183         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4184
4185         if (tr.unusable)
4186                 return false;
4187         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4188                 return false;
4189         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4190                 return false;
4191         if (!tr.present)
4192                 return false;
4193
4194         return true;
4195 }
4196
4197 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4198 {
4199         struct kvm_segment ldtr;
4200
4201         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4202
4203         if (ldtr.unusable)
4204                 return true;
4205         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4206                 return false;
4207         if (ldtr.type != 2)
4208                 return false;
4209         if (!ldtr.present)
4210                 return false;
4211
4212         return true;
4213 }
4214
4215 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4216 {
4217         struct kvm_segment cs, ss;
4218
4219         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4220         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4221
4222         return ((cs.selector & SEGMENT_RPL_MASK) ==
4223                  (ss.selector & SEGMENT_RPL_MASK));
4224 }
4225
4226 /*
4227  * Check if guest state is valid. Returns true if valid, false if
4228  * not.
4229  * We assume that registers are always usable
4230  */
4231 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4232 {
4233         if (enable_unrestricted_guest)
4234                 return true;
4235
4236         /* real mode guest state checks */
4237         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4238                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4239                         return false;
4240                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4241                         return false;
4242                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4243                         return false;
4244                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4245                         return false;
4246                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4247                         return false;
4248                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4249                         return false;
4250         } else {
4251         /* protected mode guest state checks */
4252                 if (!cs_ss_rpl_check(vcpu))
4253                         return false;
4254                 if (!code_segment_valid(vcpu))
4255                         return false;
4256                 if (!stack_segment_valid(vcpu))
4257                         return false;
4258                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4259                         return false;
4260                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4261                         return false;
4262                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4263                         return false;
4264                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4265                         return false;
4266                 if (!tr_valid(vcpu))
4267                         return false;
4268                 if (!ldtr_valid(vcpu))
4269                         return false;
4270         }
4271         /* TODO:
4272          * - Add checks on RIP
4273          * - Add checks on RFLAGS
4274          */
4275
4276         return true;
4277 }
4278
4279 static int init_rmode_tss(struct kvm *kvm)
4280 {
4281         gfn_t fn;
4282         u16 data = 0;
4283         int idx, r;
4284
4285         idx = srcu_read_lock(&kvm->srcu);
4286         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4287         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4288         if (r < 0)
4289                 goto out;
4290         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4291         r = kvm_write_guest_page(kvm, fn++, &data,
4292                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4293         if (r < 0)
4294                 goto out;
4295         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4296         if (r < 0)
4297                 goto out;
4298         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4299         if (r < 0)
4300                 goto out;
4301         data = ~0;
4302         r = kvm_write_guest_page(kvm, fn, &data,
4303                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4304                                  sizeof(u8));
4305 out:
4306         srcu_read_unlock(&kvm->srcu, idx);
4307         return r;
4308 }
4309
4310 static int init_rmode_identity_map(struct kvm *kvm)
4311 {
4312         int i, idx, r = 0;
4313         kvm_pfn_t identity_map_pfn;
4314         u32 tmp;
4315
4316         if (!enable_ept)
4317                 return 0;
4318
4319         /* Protect kvm->arch.ept_identity_pagetable_done. */
4320         mutex_lock(&kvm->slots_lock);
4321
4322         if (likely(kvm->arch.ept_identity_pagetable_done))
4323                 goto out2;
4324
4325         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4326
4327         r = alloc_identity_pagetable(kvm);
4328         if (r < 0)
4329                 goto out2;
4330
4331         idx = srcu_read_lock(&kvm->srcu);
4332         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4333         if (r < 0)
4334                 goto out;
4335         /* Set up identity-mapping pagetable for EPT in real mode */
4336         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4337                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4338                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4339                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4340                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4341                 if (r < 0)
4342                         goto out;
4343         }
4344         kvm->arch.ept_identity_pagetable_done = true;
4345
4346 out:
4347         srcu_read_unlock(&kvm->srcu, idx);
4348
4349 out2:
4350         mutex_unlock(&kvm->slots_lock);
4351         return r;
4352 }
4353
4354 static void seg_setup(int seg)
4355 {
4356         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4357         unsigned int ar;
4358
4359         vmcs_write16(sf->selector, 0);
4360         vmcs_writel(sf->base, 0);
4361         vmcs_write32(sf->limit, 0xffff);
4362         ar = 0x93;
4363         if (seg == VCPU_SREG_CS)
4364                 ar |= 0x08; /* code segment */
4365
4366         vmcs_write32(sf->ar_bytes, ar);
4367 }
4368
4369 static int alloc_apic_access_page(struct kvm *kvm)
4370 {
4371         struct page *page;
4372         int r = 0;
4373
4374         mutex_lock(&kvm->slots_lock);
4375         if (kvm->arch.apic_access_page_done)
4376                 goto out;
4377         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4378                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4379         if (r)
4380                 goto out;
4381
4382         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4383         if (is_error_page(page)) {
4384                 r = -EFAULT;
4385                 goto out;
4386         }
4387
4388         /*
4389          * Do not pin the page in memory, so that memory hot-unplug
4390          * is able to migrate it.
4391          */
4392         put_page(page);
4393         kvm->arch.apic_access_page_done = true;
4394 out:
4395         mutex_unlock(&kvm->slots_lock);
4396         return r;
4397 }
4398
4399 static int alloc_identity_pagetable(struct kvm *kvm)
4400 {
4401         /* Called with kvm->slots_lock held. */
4402
4403         int r = 0;
4404
4405         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4406
4407         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4408                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4409
4410         return r;
4411 }
4412
4413 static int allocate_vpid(void)
4414 {
4415         int vpid;
4416
4417         if (!enable_vpid)
4418                 return 0;
4419         spin_lock(&vmx_vpid_lock);
4420         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4421         if (vpid < VMX_NR_VPIDS)
4422                 __set_bit(vpid, vmx_vpid_bitmap);
4423         else
4424                 vpid = 0;
4425         spin_unlock(&vmx_vpid_lock);
4426         return vpid;
4427 }
4428
4429 static void free_vpid(int vpid)
4430 {
4431         if (!enable_vpid || vpid == 0)
4432                 return;
4433         spin_lock(&vmx_vpid_lock);
4434         __clear_bit(vpid, vmx_vpid_bitmap);
4435         spin_unlock(&vmx_vpid_lock);
4436 }
4437
4438 #define MSR_TYPE_R      1
4439 #define MSR_TYPE_W      2
4440 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4441                                                 u32 msr, int type)
4442 {
4443         int f = sizeof(unsigned long);
4444
4445         if (!cpu_has_vmx_msr_bitmap())
4446                 return;
4447
4448         /*
4449          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4450          * have the write-low and read-high bitmap offsets the wrong way round.
4451          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4452          */
4453         if (msr <= 0x1fff) {
4454                 if (type & MSR_TYPE_R)
4455                         /* read-low */
4456                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4457
4458                 if (type & MSR_TYPE_W)
4459                         /* write-low */
4460                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4461
4462         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4463                 msr &= 0x1fff;
4464                 if (type & MSR_TYPE_R)
4465                         /* read-high */
4466                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4467
4468                 if (type & MSR_TYPE_W)
4469                         /* write-high */
4470                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4471
4472         }
4473 }
4474
4475 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4476                                                 u32 msr, int type)
4477 {
4478         int f = sizeof(unsigned long);
4479
4480         if (!cpu_has_vmx_msr_bitmap())
4481                 return;
4482
4483         /*
4484          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4485          * have the write-low and read-high bitmap offsets the wrong way round.
4486          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4487          */
4488         if (msr <= 0x1fff) {
4489                 if (type & MSR_TYPE_R)
4490                         /* read-low */
4491                         __set_bit(msr, msr_bitmap + 0x000 / f);
4492
4493                 if (type & MSR_TYPE_W)
4494                         /* write-low */
4495                         __set_bit(msr, msr_bitmap + 0x800 / f);
4496
4497         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4498                 msr &= 0x1fff;
4499                 if (type & MSR_TYPE_R)
4500                         /* read-high */
4501                         __set_bit(msr, msr_bitmap + 0x400 / f);
4502
4503                 if (type & MSR_TYPE_W)
4504                         /* write-high */
4505                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4506
4507         }
4508 }
4509
4510 /*
4511  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4512  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4513  */
4514 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4515                                                unsigned long *msr_bitmap_nested,
4516                                                u32 msr, int type)
4517 {
4518         int f = sizeof(unsigned long);
4519
4520         if (!cpu_has_vmx_msr_bitmap()) {
4521                 WARN_ON(1);
4522                 return;
4523         }
4524
4525         /*
4526          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4527          * have the write-low and read-high bitmap offsets the wrong way round.
4528          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4529          */
4530         if (msr <= 0x1fff) {
4531                 if (type & MSR_TYPE_R &&
4532                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4533                         /* read-low */
4534                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4535
4536                 if (type & MSR_TYPE_W &&
4537                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4538                         /* write-low */
4539                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4540
4541         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4542                 msr &= 0x1fff;
4543                 if (type & MSR_TYPE_R &&
4544                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4545                         /* read-high */
4546                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4547
4548                 if (type & MSR_TYPE_W &&
4549                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4550                         /* write-high */
4551                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4552
4553         }
4554 }
4555
4556 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4557 {
4558         if (!longmode_only)
4559                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4560                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4561         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4562                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4563 }
4564
4565 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4566 {
4567         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4568                         msr, MSR_TYPE_R);
4569         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4570                         msr, MSR_TYPE_R);
4571 }
4572
4573 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4574 {
4575         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4576                         msr, MSR_TYPE_R);
4577         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4578                         msr, MSR_TYPE_R);
4579 }
4580
4581 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4582 {
4583         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4584                         msr, MSR_TYPE_W);
4585         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4586                         msr, MSR_TYPE_W);
4587 }
4588
4589 static bool vmx_get_enable_apicv(void)
4590 {
4591         return enable_apicv;
4592 }
4593
4594 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4595 {
4596         struct vcpu_vmx *vmx = to_vmx(vcpu);
4597         int max_irr;
4598         void *vapic_page;
4599         u16 status;
4600
4601         if (vmx->nested.pi_desc &&
4602             vmx->nested.pi_pending) {
4603                 vmx->nested.pi_pending = false;
4604                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4605                         return 0;
4606
4607                 max_irr = find_last_bit(
4608                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4609
4610                 if (max_irr == 256)
4611                         return 0;
4612
4613                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4614                 if (!vapic_page) {
4615                         WARN_ON(1);
4616                         return -ENOMEM;
4617                 }
4618                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4619                 kunmap(vmx->nested.virtual_apic_page);
4620
4621                 status = vmcs_read16(GUEST_INTR_STATUS);
4622                 if ((u8)max_irr > ((u8)status & 0xff)) {
4623                         status &= ~0xff;
4624                         status |= (u8)max_irr;
4625                         vmcs_write16(GUEST_INTR_STATUS, status);
4626                 }
4627         }
4628         return 0;
4629 }
4630
4631 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4632 {
4633 #ifdef CONFIG_SMP
4634         if (vcpu->mode == IN_GUEST_MODE) {
4635                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4636
4637                 /*
4638                  * Currently, we don't support urgent interrupt,
4639                  * all interrupts are recognized as non-urgent
4640                  * interrupt, so we cannot post interrupts when
4641                  * 'SN' is set.
4642                  *
4643                  * If the vcpu is in guest mode, it means it is
4644                  * running instead of being scheduled out and
4645                  * waiting in the run queue, and that's the only
4646                  * case when 'SN' is set currently, warning if
4647                  * 'SN' is set.
4648                  */
4649                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4650
4651                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4652                                 POSTED_INTR_VECTOR);
4653                 return true;
4654         }
4655 #endif
4656         return false;
4657 }
4658
4659 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4660                                                 int vector)
4661 {
4662         struct vcpu_vmx *vmx = to_vmx(vcpu);
4663
4664         if (is_guest_mode(vcpu) &&
4665             vector == vmx->nested.posted_intr_nv) {
4666                 /* the PIR and ON have been set by L1. */
4667                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4668                 /*
4669                  * If a posted intr is not recognized by hardware,
4670                  * we will accomplish it in the next vmentry.
4671                  */
4672                 vmx->nested.pi_pending = true;
4673                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4674                 return 0;
4675         }
4676         return -1;
4677 }
4678 /*
4679  * Send interrupt to vcpu via posted interrupt way.
4680  * 1. If target vcpu is running(non-root mode), send posted interrupt
4681  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4682  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4683  * interrupt from PIR in next vmentry.
4684  */
4685 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4686 {
4687         struct vcpu_vmx *vmx = to_vmx(vcpu);
4688         int r;
4689
4690         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4691         if (!r)
4692                 return;
4693
4694         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4695                 return;
4696
4697         r = pi_test_and_set_on(&vmx->pi_desc);
4698         kvm_make_request(KVM_REQ_EVENT, vcpu);
4699         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4700                 kvm_vcpu_kick(vcpu);
4701 }
4702
4703 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4704 {
4705         struct vcpu_vmx *vmx = to_vmx(vcpu);
4706
4707         if (!pi_test_and_clear_on(&vmx->pi_desc))
4708                 return;
4709
4710         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4711 }
4712
4713 /*
4714  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4715  * will not change in the lifetime of the guest.
4716  * Note that host-state that does change is set elsewhere. E.g., host-state
4717  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4718  */
4719 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4720 {
4721         u32 low32, high32;
4722         unsigned long tmpl;
4723         struct desc_ptr dt;
4724         unsigned long cr4;
4725
4726         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4727         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4728
4729         /* Save the most likely value for this task's CR4 in the VMCS. */
4730         cr4 = cr4_read_shadow();
4731         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4732         vmx->host_state.vmcs_host_cr4 = cr4;
4733
4734         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4735 #ifdef CONFIG_X86_64
4736         /*
4737          * Load null selectors, so we can avoid reloading them in
4738          * __vmx_load_host_state(), in case userspace uses the null selectors
4739          * too (the expected case).
4740          */
4741         vmcs_write16(HOST_DS_SELECTOR, 0);
4742         vmcs_write16(HOST_ES_SELECTOR, 0);
4743 #else
4744         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4745         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4746 #endif
4747         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4748         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4749
4750         native_store_idt(&dt);
4751         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4752         vmx->host_idt_base = dt.address;
4753
4754         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4755
4756         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4757         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4758         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4759         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4760
4761         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4762                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4763                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4764         }
4765 }
4766
4767 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4768 {
4769         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4770         if (enable_ept)
4771                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4772         if (is_guest_mode(&vmx->vcpu))
4773                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4774                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4775         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4776 }
4777
4778 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4779 {
4780         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4781
4782         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4783                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4784         return pin_based_exec_ctrl;
4785 }
4786
4787 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4788 {
4789         struct vcpu_vmx *vmx = to_vmx(vcpu);
4790
4791         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4792         if (cpu_has_secondary_exec_ctrls()) {
4793                 if (kvm_vcpu_apicv_active(vcpu))
4794                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4795                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4796                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4797                 else
4798                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4799                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4800                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4801         }
4802
4803         if (cpu_has_vmx_msr_bitmap())
4804                 vmx_set_msr_bitmap(vcpu);
4805 }
4806
4807 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4808 {
4809         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4810
4811         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4812                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4813
4814         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4815                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4816 #ifdef CONFIG_X86_64
4817                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4818                                 CPU_BASED_CR8_LOAD_EXITING;
4819 #endif
4820         }
4821         if (!enable_ept)
4822                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4823                                 CPU_BASED_CR3_LOAD_EXITING  |
4824                                 CPU_BASED_INVLPG_EXITING;
4825         return exec_control;
4826 }
4827
4828 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4829 {
4830         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4831         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4832                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4833         if (vmx->vpid == 0)
4834                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4835         if (!enable_ept) {
4836                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4837                 enable_unrestricted_guest = 0;
4838                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4839                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4840         }
4841         if (!enable_unrestricted_guest)
4842                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4843         if (!ple_gap)
4844                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4845         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4846                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4847                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4848         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4849         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4850            (handle_vmptrld).
4851            We can NOT enable shadow_vmcs here because we don't have yet
4852            a current VMCS12
4853         */
4854         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4855
4856         if (!enable_pml)
4857                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4858
4859         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4860         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4861
4862         return exec_control;
4863 }
4864
4865 static void ept_set_mmio_spte_mask(void)
4866 {
4867         /*
4868          * EPT Misconfigurations can be generated if the value of bits 2:0
4869          * of an EPT paging-structure entry is 110b (write/execute).
4870          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4871          * spte.
4872          */
4873         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4874 }
4875
4876 #define VMX_XSS_EXIT_BITMAP 0
4877 /*
4878  * Sets up the vmcs for emulated real mode.
4879  */
4880 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4881 {
4882 #ifdef CONFIG_X86_64
4883         unsigned long a;
4884 #endif
4885         int i;
4886
4887         /* I/O */
4888         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4889         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4890
4891         if (enable_shadow_vmcs) {
4892                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4893                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4894         }
4895         if (cpu_has_vmx_msr_bitmap())
4896                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4897
4898         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4899
4900         /* Control */
4901         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4902
4903         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4904
4905         if (cpu_has_secondary_exec_ctrls())
4906                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4907                                 vmx_secondary_exec_control(vmx));
4908
4909         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4910                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4911                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4912                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4913                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4914
4915                 vmcs_write16(GUEST_INTR_STATUS, 0);
4916
4917                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4918                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4919         }
4920
4921         if (ple_gap) {
4922                 vmcs_write32(PLE_GAP, ple_gap);
4923                 vmx->ple_window = ple_window;
4924                 vmx->ple_window_dirty = true;
4925         }
4926
4927         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4928         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4929         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4930
4931         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4932         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4933         vmx_set_constant_host_state(vmx);
4934 #ifdef CONFIG_X86_64
4935         rdmsrl(MSR_FS_BASE, a);
4936         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4937         rdmsrl(MSR_GS_BASE, a);
4938         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4939 #else
4940         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4941         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4942 #endif
4943
4944         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4945         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4946         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4947         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4948         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4949
4950         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4951                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4952
4953         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4954                 u32 index = vmx_msr_index[i];
4955                 u32 data_low, data_high;
4956                 int j = vmx->nmsrs;
4957
4958                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4959                         continue;
4960                 if (wrmsr_safe(index, data_low, data_high) < 0)
4961                         continue;
4962                 vmx->guest_msrs[j].index = i;
4963                 vmx->guest_msrs[j].data = 0;
4964                 vmx->guest_msrs[j].mask = -1ull;
4965                 ++vmx->nmsrs;
4966         }
4967
4968
4969         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4970
4971         /* 22.2.1, 20.8.1 */
4972         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4973
4974         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4975         set_cr4_guest_host_mask(vmx);
4976
4977         if (vmx_xsaves_supported())
4978                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4979
4980         return 0;
4981 }
4982
4983 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4984 {
4985         struct vcpu_vmx *vmx = to_vmx(vcpu);
4986         struct msr_data apic_base_msr;
4987         u64 cr0;
4988
4989         vmx->rmode.vm86_active = 0;
4990
4991         vmx->soft_vnmi_blocked = 0;
4992
4993         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4994         kvm_set_cr8(vcpu, 0);
4995
4996         if (!init_event) {
4997                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4998                                      MSR_IA32_APICBASE_ENABLE;
4999                 if (kvm_vcpu_is_reset_bsp(vcpu))
5000                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5001                 apic_base_msr.host_initiated = true;
5002                 kvm_set_apic_base(vcpu, &apic_base_msr);
5003         }
5004
5005         vmx_segment_cache_clear(vmx);
5006
5007         seg_setup(VCPU_SREG_CS);
5008         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5009         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5010
5011         seg_setup(VCPU_SREG_DS);
5012         seg_setup(VCPU_SREG_ES);
5013         seg_setup(VCPU_SREG_FS);
5014         seg_setup(VCPU_SREG_GS);
5015         seg_setup(VCPU_SREG_SS);
5016
5017         vmcs_write16(GUEST_TR_SELECTOR, 0);
5018         vmcs_writel(GUEST_TR_BASE, 0);
5019         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5020         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5021
5022         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5023         vmcs_writel(GUEST_LDTR_BASE, 0);
5024         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5025         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5026
5027         if (!init_event) {
5028                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5029                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5030                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5031                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5032         }
5033
5034         vmcs_writel(GUEST_RFLAGS, 0x02);
5035         kvm_rip_write(vcpu, 0xfff0);
5036
5037         vmcs_writel(GUEST_GDTR_BASE, 0);
5038         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5039
5040         vmcs_writel(GUEST_IDTR_BASE, 0);
5041         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5042
5043         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5044         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5045         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5046
5047         setup_msrs(vmx);
5048
5049         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5050
5051         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5052                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5053                 if (cpu_need_tpr_shadow(vcpu))
5054                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5055                                      __pa(vcpu->arch.apic->regs));
5056                 vmcs_write32(TPR_THRESHOLD, 0);
5057         }
5058
5059         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5060
5061         if (kvm_vcpu_apicv_active(vcpu))
5062                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5063
5064         if (vmx->vpid != 0)
5065                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5066
5067         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5068         vmx->vcpu.arch.cr0 = cr0;
5069         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5070         vmx_set_cr4(vcpu, 0);
5071         vmx_set_efer(vcpu, 0);
5072         vmx_fpu_activate(vcpu);
5073         update_exception_bitmap(vcpu);
5074
5075         vpid_sync_context(vmx->vpid);
5076 }
5077
5078 /*
5079  * In nested virtualization, check if L1 asked to exit on external interrupts.
5080  * For most existing hypervisors, this will always return true.
5081  */
5082 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5083 {
5084         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5085                 PIN_BASED_EXT_INTR_MASK;
5086 }
5087
5088 /*
5089  * In nested virtualization, check if L1 has set
5090  * VM_EXIT_ACK_INTR_ON_EXIT
5091  */
5092 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5093 {
5094         return get_vmcs12(vcpu)->vm_exit_controls &
5095                 VM_EXIT_ACK_INTR_ON_EXIT;
5096 }
5097
5098 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5099 {
5100         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5101                 PIN_BASED_NMI_EXITING;
5102 }
5103
5104 static void enable_irq_window(struct kvm_vcpu *vcpu)
5105 {
5106         u32 cpu_based_vm_exec_control;
5107
5108         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5109         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5110         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5111 }
5112
5113 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5114 {
5115         u32 cpu_based_vm_exec_control;
5116
5117         if (!cpu_has_virtual_nmis() ||
5118             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5119                 enable_irq_window(vcpu);
5120                 return;
5121         }
5122
5123         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5124         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5125         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5126 }
5127
5128 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5129 {
5130         struct vcpu_vmx *vmx = to_vmx(vcpu);
5131         uint32_t intr;
5132         int irq = vcpu->arch.interrupt.nr;
5133
5134         trace_kvm_inj_virq(irq);
5135
5136         ++vcpu->stat.irq_injections;
5137         if (vmx->rmode.vm86_active) {
5138                 int inc_eip = 0;
5139                 if (vcpu->arch.interrupt.soft)
5140                         inc_eip = vcpu->arch.event_exit_inst_len;
5141                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5142                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5143                 return;
5144         }
5145         intr = irq | INTR_INFO_VALID_MASK;
5146         if (vcpu->arch.interrupt.soft) {
5147                 intr |= INTR_TYPE_SOFT_INTR;
5148                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5149                              vmx->vcpu.arch.event_exit_inst_len);
5150         } else
5151                 intr |= INTR_TYPE_EXT_INTR;
5152         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5153 }
5154
5155 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5156 {
5157         struct vcpu_vmx *vmx = to_vmx(vcpu);
5158
5159         if (is_guest_mode(vcpu))
5160                 return;
5161
5162         if (!cpu_has_virtual_nmis()) {
5163                 /*
5164                  * Tracking the NMI-blocked state in software is built upon
5165                  * finding the next open IRQ window. This, in turn, depends on
5166                  * well-behaving guests: They have to keep IRQs disabled at
5167                  * least as long as the NMI handler runs. Otherwise we may
5168                  * cause NMI nesting, maybe breaking the guest. But as this is
5169                  * highly unlikely, we can live with the residual risk.
5170                  */
5171                 vmx->soft_vnmi_blocked = 1;
5172                 vmx->vnmi_blocked_time = 0;
5173         }
5174
5175         ++vcpu->stat.nmi_injections;
5176         vmx->nmi_known_unmasked = false;
5177         if (vmx->rmode.vm86_active) {
5178                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5179                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5180                 return;
5181         }
5182         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5183                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5184 }
5185
5186 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5187 {
5188         if (!cpu_has_virtual_nmis())
5189                 return to_vmx(vcpu)->soft_vnmi_blocked;
5190         if (to_vmx(vcpu)->nmi_known_unmasked)
5191                 return false;
5192         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5193 }
5194
5195 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5196 {
5197         struct vcpu_vmx *vmx = to_vmx(vcpu);
5198
5199         if (!cpu_has_virtual_nmis()) {
5200                 if (vmx->soft_vnmi_blocked != masked) {
5201                         vmx->soft_vnmi_blocked = masked;
5202                         vmx->vnmi_blocked_time = 0;
5203                 }
5204         } else {
5205                 vmx->nmi_known_unmasked = !masked;
5206                 if (masked)
5207                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5208                                       GUEST_INTR_STATE_NMI);
5209                 else
5210                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5211                                         GUEST_INTR_STATE_NMI);
5212         }
5213 }
5214
5215 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5216 {
5217         if (to_vmx(vcpu)->nested.nested_run_pending)
5218                 return 0;
5219
5220         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5221                 return 0;
5222
5223         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5224                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5225                    | GUEST_INTR_STATE_NMI));
5226 }
5227
5228 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5229 {
5230         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5231                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5232                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5233                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5234 }
5235
5236 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5237 {
5238         int ret;
5239
5240         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5241                                     PAGE_SIZE * 3);
5242         if (ret)
5243                 return ret;
5244         kvm->arch.tss_addr = addr;
5245         return init_rmode_tss(kvm);
5246 }
5247
5248 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5249 {
5250         switch (vec) {
5251         case BP_VECTOR:
5252                 /*
5253                  * Update instruction length as we may reinject the exception
5254                  * from user space while in guest debugging mode.
5255                  */
5256                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5257                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5258                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5259                         return false;
5260                 /* fall through */
5261         case DB_VECTOR:
5262                 if (vcpu->guest_debug &
5263                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5264                         return false;
5265                 /* fall through */
5266         case DE_VECTOR:
5267         case OF_VECTOR:
5268         case BR_VECTOR:
5269         case UD_VECTOR:
5270         case DF_VECTOR:
5271         case SS_VECTOR:
5272         case GP_VECTOR:
5273         case MF_VECTOR:
5274                 return true;
5275         break;
5276         }
5277         return false;
5278 }
5279
5280 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5281                                   int vec, u32 err_code)
5282 {
5283         /*
5284          * Instruction with address size override prefix opcode 0x67
5285          * Cause the #SS fault with 0 error code in VM86 mode.
5286          */
5287         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5288                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5289                         if (vcpu->arch.halt_request) {
5290                                 vcpu->arch.halt_request = 0;
5291                                 return kvm_vcpu_halt(vcpu);
5292                         }
5293                         return 1;
5294                 }
5295                 return 0;
5296         }
5297
5298         /*
5299          * Forward all other exceptions that are valid in real mode.
5300          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5301          *        the required debugging infrastructure rework.
5302          */
5303         kvm_queue_exception(vcpu, vec);
5304         return 1;
5305 }
5306
5307 /*
5308  * Trigger machine check on the host. We assume all the MSRs are already set up
5309  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5310  * We pass a fake environment to the machine check handler because we want
5311  * the guest to be always treated like user space, no matter what context
5312  * it used internally.
5313  */
5314 static void kvm_machine_check(void)
5315 {
5316 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5317         struct pt_regs regs = {
5318                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5319                 .flags = X86_EFLAGS_IF,
5320         };
5321
5322         do_machine_check(&regs, 0);
5323 #endif
5324 }
5325
5326 static int handle_machine_check(struct kvm_vcpu *vcpu)
5327 {
5328         /* already handled by vcpu_run */
5329         return 1;
5330 }
5331
5332 static int handle_exception(struct kvm_vcpu *vcpu)
5333 {
5334         struct vcpu_vmx *vmx = to_vmx(vcpu);
5335         struct kvm_run *kvm_run = vcpu->run;
5336         u32 intr_info, ex_no, error_code;
5337         unsigned long cr2, rip, dr6;
5338         u32 vect_info;
5339         enum emulation_result er;
5340
5341         vect_info = vmx->idt_vectoring_info;
5342         intr_info = vmx->exit_intr_info;
5343
5344         if (is_machine_check(intr_info))
5345                 return handle_machine_check(vcpu);
5346
5347         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5348                 return 1;  /* already handled by vmx_vcpu_run() */
5349
5350         if (is_no_device(intr_info)) {
5351                 vmx_fpu_activate(vcpu);
5352                 return 1;
5353         }
5354
5355         if (is_invalid_opcode(intr_info)) {
5356                 if (is_guest_mode(vcpu)) {
5357                         kvm_queue_exception(vcpu, UD_VECTOR);
5358                         return 1;
5359                 }
5360                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5361                 if (er != EMULATE_DONE)
5362                         kvm_queue_exception(vcpu, UD_VECTOR);
5363                 return 1;
5364         }
5365
5366         error_code = 0;
5367         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5368                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5369
5370         /*
5371          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5372          * MMIO, it is better to report an internal error.
5373          * See the comments in vmx_handle_exit.
5374          */
5375         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5376             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5377                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5378                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5379                 vcpu->run->internal.ndata = 3;
5380                 vcpu->run->internal.data[0] = vect_info;
5381                 vcpu->run->internal.data[1] = intr_info;
5382                 vcpu->run->internal.data[2] = error_code;
5383                 return 0;
5384         }
5385
5386         if (is_page_fault(intr_info)) {
5387                 /* EPT won't cause page fault directly */
5388                 BUG_ON(enable_ept);
5389                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5390                 trace_kvm_page_fault(cr2, error_code);
5391
5392                 if (kvm_event_needs_reinjection(vcpu))
5393                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5394                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5395         }
5396
5397         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5398
5399         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5400                 return handle_rmode_exception(vcpu, ex_no, error_code);
5401
5402         switch (ex_no) {
5403         case AC_VECTOR:
5404                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5405                 return 1;
5406         case DB_VECTOR:
5407                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5408                 if (!(vcpu->guest_debug &
5409                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5410                         vcpu->arch.dr6 &= ~15;
5411                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5412                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5413                                 skip_emulated_instruction(vcpu);
5414
5415                         kvm_queue_exception(vcpu, DB_VECTOR);
5416                         return 1;
5417                 }
5418                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5419                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5420                 /* fall through */
5421         case BP_VECTOR:
5422                 /*
5423                  * Update instruction length as we may reinject #BP from
5424                  * user space while in guest debugging mode. Reading it for
5425                  * #DB as well causes no harm, it is not used in that case.
5426                  */
5427                 vmx->vcpu.arch.event_exit_inst_len =
5428                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5429                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5430                 rip = kvm_rip_read(vcpu);
5431                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5432                 kvm_run->debug.arch.exception = ex_no;
5433                 break;
5434         default:
5435                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5436                 kvm_run->ex.exception = ex_no;
5437                 kvm_run->ex.error_code = error_code;
5438                 break;
5439         }
5440         return 0;
5441 }
5442
5443 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5444 {
5445         ++vcpu->stat.irq_exits;
5446         return 1;
5447 }
5448
5449 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5450 {
5451         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5452         return 0;
5453 }
5454
5455 static int handle_io(struct kvm_vcpu *vcpu)
5456 {
5457         unsigned long exit_qualification;
5458         int size, in, string;
5459         unsigned port;
5460
5461         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5462         string = (exit_qualification & 16) != 0;
5463         in = (exit_qualification & 8) != 0;
5464
5465         ++vcpu->stat.io_exits;
5466
5467         if (string || in)
5468                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5469
5470         port = exit_qualification >> 16;
5471         size = (exit_qualification & 7) + 1;
5472         skip_emulated_instruction(vcpu);
5473
5474         return kvm_fast_pio_out(vcpu, size, port);
5475 }
5476
5477 static void
5478 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5479 {
5480         /*
5481          * Patch in the VMCALL instruction:
5482          */
5483         hypercall[0] = 0x0f;
5484         hypercall[1] = 0x01;
5485         hypercall[2] = 0xc1;
5486 }
5487
5488 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5489 {
5490         unsigned long always_on = VMXON_CR0_ALWAYSON;
5491         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5492
5493         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5494                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5495             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5496                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5497         return (val & always_on) == always_on;
5498 }
5499
5500 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5501 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5502 {
5503         if (is_guest_mode(vcpu)) {
5504                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5505                 unsigned long orig_val = val;
5506
5507                 /*
5508                  * We get here when L2 changed cr0 in a way that did not change
5509                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5510                  * but did change L0 shadowed bits. So we first calculate the
5511                  * effective cr0 value that L1 would like to write into the
5512                  * hardware. It consists of the L2-owned bits from the new
5513                  * value combined with the L1-owned bits from L1's guest_cr0.
5514                  */
5515                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5516                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5517
5518                 if (!nested_cr0_valid(vcpu, val))
5519                         return 1;
5520
5521                 if (kvm_set_cr0(vcpu, val))
5522                         return 1;
5523                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5524                 return 0;
5525         } else {
5526                 if (to_vmx(vcpu)->nested.vmxon &&
5527                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5528                         return 1;
5529                 return kvm_set_cr0(vcpu, val);
5530         }
5531 }
5532
5533 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5534 {
5535         if (is_guest_mode(vcpu)) {
5536                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5537                 unsigned long orig_val = val;
5538
5539                 /* analogously to handle_set_cr0 */
5540                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5541                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5542                 if (kvm_set_cr4(vcpu, val))
5543                         return 1;
5544                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5545                 return 0;
5546         } else
5547                 return kvm_set_cr4(vcpu, val);
5548 }
5549
5550 /* called to set cr0 as appropriate for clts instruction exit. */
5551 static void handle_clts(struct kvm_vcpu *vcpu)
5552 {
5553         if (is_guest_mode(vcpu)) {
5554                 /*
5555                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5556                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5557                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5558                  */
5559                 vmcs_writel(CR0_READ_SHADOW,
5560                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5561                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5562         } else
5563                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5564 }
5565
5566 static int handle_cr(struct kvm_vcpu *vcpu)
5567 {
5568         unsigned long exit_qualification, val;
5569         int cr;
5570         int reg;
5571         int err;
5572
5573         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5574         cr = exit_qualification & 15;
5575         reg = (exit_qualification >> 8) & 15;
5576         switch ((exit_qualification >> 4) & 3) {
5577         case 0: /* mov to cr */
5578                 val = kvm_register_readl(vcpu, reg);
5579                 trace_kvm_cr_write(cr, val);
5580                 switch (cr) {
5581                 case 0:
5582                         err = handle_set_cr0(vcpu, val);
5583                         kvm_complete_insn_gp(vcpu, err);
5584                         return 1;
5585                 case 3:
5586                         err = kvm_set_cr3(vcpu, val);
5587                         kvm_complete_insn_gp(vcpu, err);
5588                         return 1;
5589                 case 4:
5590                         err = handle_set_cr4(vcpu, val);
5591                         kvm_complete_insn_gp(vcpu, err);
5592                         return 1;
5593                 case 8: {
5594                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5595                                 u8 cr8 = (u8)val;
5596                                 err = kvm_set_cr8(vcpu, cr8);
5597                                 kvm_complete_insn_gp(vcpu, err);
5598                                 if (lapic_in_kernel(vcpu))
5599                                         return 1;
5600                                 if (cr8_prev <= cr8)
5601                                         return 1;
5602                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5603                                 return 0;
5604                         }
5605                 }
5606                 break;
5607         case 2: /* clts */
5608                 handle_clts(vcpu);
5609                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5610                 skip_emulated_instruction(vcpu);
5611                 vmx_fpu_activate(vcpu);
5612                 return 1;
5613         case 1: /*mov from cr*/
5614                 switch (cr) {
5615                 case 3:
5616                         val = kvm_read_cr3(vcpu);
5617                         kvm_register_write(vcpu, reg, val);
5618                         trace_kvm_cr_read(cr, val);
5619                         skip_emulated_instruction(vcpu);
5620                         return 1;
5621                 case 8:
5622                         val = kvm_get_cr8(vcpu);
5623                         kvm_register_write(vcpu, reg, val);
5624                         trace_kvm_cr_read(cr, val);
5625                         skip_emulated_instruction(vcpu);
5626                         return 1;
5627                 }
5628                 break;
5629         case 3: /* lmsw */
5630                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5631                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5632                 kvm_lmsw(vcpu, val);
5633
5634                 skip_emulated_instruction(vcpu);
5635                 return 1;
5636         default:
5637                 break;
5638         }
5639         vcpu->run->exit_reason = 0;
5640         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5641                (int)(exit_qualification >> 4) & 3, cr);
5642         return 0;
5643 }
5644
5645 static int handle_dr(struct kvm_vcpu *vcpu)
5646 {
5647         unsigned long exit_qualification;
5648         int dr, dr7, reg;
5649
5650         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5651         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5652
5653         /* First, if DR does not exist, trigger UD */
5654         if (!kvm_require_dr(vcpu, dr))
5655                 return 1;
5656
5657         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5658         if (!kvm_require_cpl(vcpu, 0))
5659                 return 1;
5660         dr7 = vmcs_readl(GUEST_DR7);
5661         if (dr7 & DR7_GD) {
5662                 /*
5663                  * As the vm-exit takes precedence over the debug trap, we
5664                  * need to emulate the latter, either for the host or the
5665                  * guest debugging itself.
5666                  */
5667                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5668                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5669                         vcpu->run->debug.arch.dr7 = dr7;
5670                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5671                         vcpu->run->debug.arch.exception = DB_VECTOR;
5672                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5673                         return 0;
5674                 } else {
5675                         vcpu->arch.dr6 &= ~15;
5676                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5677                         kvm_queue_exception(vcpu, DB_VECTOR);
5678                         return 1;
5679                 }
5680         }
5681
5682         if (vcpu->guest_debug == 0) {
5683                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5684                                 CPU_BASED_MOV_DR_EXITING);
5685
5686                 /*
5687                  * No more DR vmexits; force a reload of the debug registers
5688                  * and reenter on this instruction.  The next vmexit will
5689                  * retrieve the full state of the debug registers.
5690                  */
5691                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5692                 return 1;
5693         }
5694
5695         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5696         if (exit_qualification & TYPE_MOV_FROM_DR) {
5697                 unsigned long val;
5698
5699                 if (kvm_get_dr(vcpu, dr, &val))
5700                         return 1;
5701                 kvm_register_write(vcpu, reg, val);
5702         } else
5703                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5704                         return 1;
5705
5706         skip_emulated_instruction(vcpu);
5707         return 1;
5708 }
5709
5710 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5711 {
5712         return vcpu->arch.dr6;
5713 }
5714
5715 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5716 {
5717 }
5718
5719 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5720 {
5721         get_debugreg(vcpu->arch.db[0], 0);
5722         get_debugreg(vcpu->arch.db[1], 1);
5723         get_debugreg(vcpu->arch.db[2], 2);
5724         get_debugreg(vcpu->arch.db[3], 3);
5725         get_debugreg(vcpu->arch.dr6, 6);
5726         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5727
5728         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5729         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5730 }
5731
5732 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5733 {
5734         vmcs_writel(GUEST_DR7, val);
5735 }
5736
5737 static int handle_cpuid(struct kvm_vcpu *vcpu)
5738 {
5739         kvm_emulate_cpuid(vcpu);
5740         return 1;
5741 }
5742
5743 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5744 {
5745         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5746         struct msr_data msr_info;
5747
5748         msr_info.index = ecx;
5749         msr_info.host_initiated = false;
5750         if (vmx_get_msr(vcpu, &msr_info)) {
5751                 trace_kvm_msr_read_ex(ecx);
5752                 kvm_inject_gp(vcpu, 0);
5753                 return 1;
5754         }
5755
5756         trace_kvm_msr_read(ecx, msr_info.data);
5757
5758         /* FIXME: handling of bits 32:63 of rax, rdx */
5759         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5760         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5761         skip_emulated_instruction(vcpu);
5762         return 1;
5763 }
5764
5765 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5766 {
5767         struct msr_data msr;
5768         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5769         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5770                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5771
5772         msr.data = data;
5773         msr.index = ecx;
5774         msr.host_initiated = false;
5775         if (kvm_set_msr(vcpu, &msr) != 0) {
5776                 trace_kvm_msr_write_ex(ecx, data);
5777                 kvm_inject_gp(vcpu, 0);
5778                 return 1;
5779         }
5780
5781         trace_kvm_msr_write(ecx, data);
5782         skip_emulated_instruction(vcpu);
5783         return 1;
5784 }
5785
5786 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5787 {
5788         kvm_make_request(KVM_REQ_EVENT, vcpu);
5789         return 1;
5790 }
5791
5792 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5793 {
5794         u32 cpu_based_vm_exec_control;
5795
5796         /* clear pending irq */
5797         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5798         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5799         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5800
5801         kvm_make_request(KVM_REQ_EVENT, vcpu);
5802
5803         ++vcpu->stat.irq_window_exits;
5804         return 1;
5805 }
5806
5807 static int handle_halt(struct kvm_vcpu *vcpu)
5808 {
5809         return kvm_emulate_halt(vcpu);
5810 }
5811
5812 static int handle_vmcall(struct kvm_vcpu *vcpu)
5813 {
5814         return kvm_emulate_hypercall(vcpu);
5815 }
5816
5817 static int handle_invd(struct kvm_vcpu *vcpu)
5818 {
5819         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5820 }
5821
5822 static int handle_invlpg(struct kvm_vcpu *vcpu)
5823 {
5824         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5825
5826         kvm_mmu_invlpg(vcpu, exit_qualification);
5827         skip_emulated_instruction(vcpu);
5828         return 1;
5829 }
5830
5831 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5832 {
5833         int err;
5834
5835         err = kvm_rdpmc(vcpu);
5836         kvm_complete_insn_gp(vcpu, err);
5837
5838         return 1;
5839 }
5840
5841 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5842 {
5843         kvm_emulate_wbinvd(vcpu);
5844         return 1;
5845 }
5846
5847 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5848 {
5849         u64 new_bv = kvm_read_edx_eax(vcpu);
5850         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5851
5852         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5853                 skip_emulated_instruction(vcpu);
5854         return 1;
5855 }
5856
5857 static int handle_xsaves(struct kvm_vcpu *vcpu)
5858 {
5859         skip_emulated_instruction(vcpu);
5860         WARN(1, "this should never happen\n");
5861         return 1;
5862 }
5863
5864 static int handle_xrstors(struct kvm_vcpu *vcpu)
5865 {
5866         skip_emulated_instruction(vcpu);
5867         WARN(1, "this should never happen\n");
5868         return 1;
5869 }
5870
5871 static int handle_apic_access(struct kvm_vcpu *vcpu)
5872 {
5873         if (likely(fasteoi)) {
5874                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5875                 int access_type, offset;
5876
5877                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5878                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5879                 /*
5880                  * Sane guest uses MOV to write EOI, with written value
5881                  * not cared. So make a short-circuit here by avoiding
5882                  * heavy instruction emulation.
5883                  */
5884                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5885                     (offset == APIC_EOI)) {
5886                         kvm_lapic_set_eoi(vcpu);
5887                         skip_emulated_instruction(vcpu);
5888                         return 1;
5889                 }
5890         }
5891         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5892 }
5893
5894 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5895 {
5896         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5897         int vector = exit_qualification & 0xff;
5898
5899         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5900         kvm_apic_set_eoi_accelerated(vcpu, vector);
5901         return 1;
5902 }
5903
5904 static int handle_apic_write(struct kvm_vcpu *vcpu)
5905 {
5906         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5907         u32 offset = exit_qualification & 0xfff;
5908
5909         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5910         kvm_apic_write_nodecode(vcpu, offset);
5911         return 1;
5912 }
5913
5914 static int handle_task_switch(struct kvm_vcpu *vcpu)
5915 {
5916         struct vcpu_vmx *vmx = to_vmx(vcpu);
5917         unsigned long exit_qualification;
5918         bool has_error_code = false;
5919         u32 error_code = 0;
5920         u16 tss_selector;
5921         int reason, type, idt_v, idt_index;
5922
5923         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5924         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5925         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5926
5927         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5928
5929         reason = (u32)exit_qualification >> 30;
5930         if (reason == TASK_SWITCH_GATE && idt_v) {
5931                 switch (type) {
5932                 case INTR_TYPE_NMI_INTR:
5933                         vcpu->arch.nmi_injected = false;
5934                         vmx_set_nmi_mask(vcpu, true);
5935                         break;
5936                 case INTR_TYPE_EXT_INTR:
5937                 case INTR_TYPE_SOFT_INTR:
5938                         kvm_clear_interrupt_queue(vcpu);
5939                         break;
5940                 case INTR_TYPE_HARD_EXCEPTION:
5941                         if (vmx->idt_vectoring_info &
5942                             VECTORING_INFO_DELIVER_CODE_MASK) {
5943                                 has_error_code = true;
5944                                 error_code =
5945                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5946                         }
5947                         /* fall through */
5948                 case INTR_TYPE_SOFT_EXCEPTION:
5949                         kvm_clear_exception_queue(vcpu);
5950                         break;
5951                 default:
5952                         break;
5953                 }
5954         }
5955         tss_selector = exit_qualification;
5956
5957         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5958                        type != INTR_TYPE_EXT_INTR &&
5959                        type != INTR_TYPE_NMI_INTR))
5960                 skip_emulated_instruction(vcpu);
5961
5962         if (kvm_task_switch(vcpu, tss_selector,
5963                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5964                             has_error_code, error_code) == EMULATE_FAIL) {
5965                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5966                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5967                 vcpu->run->internal.ndata = 0;
5968                 return 0;
5969         }
5970
5971         /*
5972          * TODO: What about debug traps on tss switch?
5973          *       Are we supposed to inject them and update dr6?
5974          */
5975
5976         return 1;
5977 }
5978
5979 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5980 {
5981         unsigned long exit_qualification;
5982         gpa_t gpa;
5983         u32 error_code;
5984         int gla_validity;
5985
5986         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5987
5988         gla_validity = (exit_qualification >> 7) & 0x3;
5989         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5990                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5991                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5992                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5993                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5994                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5995                         (long unsigned int)exit_qualification);
5996                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5997                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5998                 return 0;
5999         }
6000
6001         /*
6002          * EPT violation happened while executing iret from NMI,
6003          * "blocked by NMI" bit has to be set before next VM entry.
6004          * There are errata that may cause this bit to not be set:
6005          * AAK134, BY25.
6006          */
6007         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6008                         cpu_has_virtual_nmis() &&
6009                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6010                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6011
6012         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6013         trace_kvm_page_fault(gpa, exit_qualification);
6014
6015         /* It is a write fault? */
6016         error_code = exit_qualification & PFERR_WRITE_MASK;
6017         /* It is a fetch fault? */
6018         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6019         /* ept page table is present? */
6020         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6021
6022         vcpu->arch.exit_qualification = exit_qualification;
6023
6024         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6025 }
6026
6027 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6028 {
6029         int ret;
6030         gpa_t gpa;
6031
6032         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6033         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6034                 skip_emulated_instruction(vcpu);
6035                 trace_kvm_fast_mmio(gpa);
6036                 return 1;
6037         }
6038
6039         ret = handle_mmio_page_fault(vcpu, gpa, true);
6040         if (likely(ret == RET_MMIO_PF_EMULATE))
6041                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6042                                               EMULATE_DONE;
6043
6044         if (unlikely(ret == RET_MMIO_PF_INVALID))
6045                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6046
6047         if (unlikely(ret == RET_MMIO_PF_RETRY))
6048                 return 1;
6049
6050         /* It is the real ept misconfig */
6051         WARN_ON(1);
6052
6053         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6054         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6055
6056         return 0;
6057 }
6058
6059 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6060 {
6061         u32 cpu_based_vm_exec_control;
6062
6063         /* clear pending NMI */
6064         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6065         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6066         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6067         ++vcpu->stat.nmi_window_exits;
6068         kvm_make_request(KVM_REQ_EVENT, vcpu);
6069
6070         return 1;
6071 }
6072
6073 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6074 {
6075         struct vcpu_vmx *vmx = to_vmx(vcpu);
6076         enum emulation_result err = EMULATE_DONE;
6077         int ret = 1;
6078         u32 cpu_exec_ctrl;
6079         bool intr_window_requested;
6080         unsigned count = 130;
6081
6082         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6083         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6084
6085         while (vmx->emulation_required && count-- != 0) {
6086                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6087                         return handle_interrupt_window(&vmx->vcpu);
6088
6089                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6090                         return 1;
6091
6092                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6093
6094                 if (err == EMULATE_USER_EXIT) {
6095                         ++vcpu->stat.mmio_exits;
6096                         ret = 0;
6097                         goto out;
6098                 }
6099
6100                 if (err != EMULATE_DONE) {
6101                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6102                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6103                         vcpu->run->internal.ndata = 0;
6104                         return 0;
6105                 }
6106
6107                 if (vcpu->arch.halt_request) {
6108                         vcpu->arch.halt_request = 0;
6109                         ret = kvm_vcpu_halt(vcpu);
6110                         goto out;
6111                 }
6112
6113                 if (signal_pending(current))
6114                         goto out;
6115                 if (need_resched())
6116                         schedule();
6117         }
6118
6119 out:
6120         return ret;
6121 }
6122
6123 static int __grow_ple_window(int val)
6124 {
6125         if (ple_window_grow < 1)
6126                 return ple_window;
6127
6128         val = min(val, ple_window_actual_max);
6129
6130         if (ple_window_grow < ple_window)
6131                 val *= ple_window_grow;
6132         else
6133                 val += ple_window_grow;
6134
6135         return val;
6136 }
6137
6138 static int __shrink_ple_window(int val, int modifier, int minimum)
6139 {
6140         if (modifier < 1)
6141                 return ple_window;
6142
6143         if (modifier < ple_window)
6144                 val /= modifier;
6145         else
6146                 val -= modifier;
6147
6148         return max(val, minimum);
6149 }
6150
6151 static void grow_ple_window(struct kvm_vcpu *vcpu)
6152 {
6153         struct vcpu_vmx *vmx = to_vmx(vcpu);
6154         int old = vmx->ple_window;
6155
6156         vmx->ple_window = __grow_ple_window(old);
6157
6158         if (vmx->ple_window != old)
6159                 vmx->ple_window_dirty = true;
6160
6161         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6162 }
6163
6164 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6165 {
6166         struct vcpu_vmx *vmx = to_vmx(vcpu);
6167         int old = vmx->ple_window;
6168
6169         vmx->ple_window = __shrink_ple_window(old,
6170                                               ple_window_shrink, ple_window);
6171
6172         if (vmx->ple_window != old)
6173                 vmx->ple_window_dirty = true;
6174
6175         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6176 }
6177
6178 /*
6179  * ple_window_actual_max is computed to be one grow_ple_window() below
6180  * ple_window_max. (See __grow_ple_window for the reason.)
6181  * This prevents overflows, because ple_window_max is int.
6182  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6183  * this process.
6184  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6185  */
6186 static void update_ple_window_actual_max(void)
6187 {
6188         ple_window_actual_max =
6189                         __shrink_ple_window(max(ple_window_max, ple_window),
6190                                             ple_window_grow, INT_MIN);
6191 }
6192
6193 /*
6194  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6195  */
6196 static void wakeup_handler(void)
6197 {
6198         struct kvm_vcpu *vcpu;
6199         int cpu = smp_processor_id();
6200
6201         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6202         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6203                         blocked_vcpu_list) {
6204                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6205
6206                 if (pi_test_on(pi_desc) == 1)
6207                         kvm_vcpu_kick(vcpu);
6208         }
6209         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6210 }
6211
6212 static __init int hardware_setup(void)
6213 {
6214         int r = -ENOMEM, i, msr;
6215
6216         rdmsrl_safe(MSR_EFER, &host_efer);
6217
6218         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6219                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6220
6221         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6222         if (!vmx_io_bitmap_a)
6223                 return r;
6224
6225         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6226         if (!vmx_io_bitmap_b)
6227                 goto out;
6228
6229         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6230         if (!vmx_msr_bitmap_legacy)
6231                 goto out1;
6232
6233         vmx_msr_bitmap_legacy_x2apic =
6234                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6235         if (!vmx_msr_bitmap_legacy_x2apic)
6236                 goto out2;
6237
6238         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6239         if (!vmx_msr_bitmap_longmode)
6240                 goto out3;
6241
6242         vmx_msr_bitmap_longmode_x2apic =
6243                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6244         if (!vmx_msr_bitmap_longmode_x2apic)
6245                 goto out4;
6246
6247         if (nested) {
6248                 vmx_msr_bitmap_nested =
6249                         (unsigned long *)__get_free_page(GFP_KERNEL);
6250                 if (!vmx_msr_bitmap_nested)
6251                         goto out5;
6252         }
6253
6254         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6255         if (!vmx_vmread_bitmap)
6256                 goto out6;
6257
6258         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6259         if (!vmx_vmwrite_bitmap)
6260                 goto out7;
6261
6262         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6263         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6264
6265         /*
6266          * Allow direct access to the PC debug port (it is often used for I/O
6267          * delays, but the vmexits simply slow things down).
6268          */
6269         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6270         clear_bit(0x80, vmx_io_bitmap_a);
6271
6272         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6273
6274         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6275         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6276         if (nested)
6277                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6278
6279         if (setup_vmcs_config(&vmcs_config) < 0) {
6280                 r = -EIO;
6281                 goto out8;
6282         }
6283
6284         if (boot_cpu_has(X86_FEATURE_NX))
6285                 kvm_enable_efer_bits(EFER_NX);
6286
6287         if (!cpu_has_vmx_vpid())
6288                 enable_vpid = 0;
6289         if (!cpu_has_vmx_shadow_vmcs())
6290                 enable_shadow_vmcs = 0;
6291         if (enable_shadow_vmcs)
6292                 init_vmcs_shadow_fields();
6293
6294         if (!cpu_has_vmx_ept() ||
6295             !cpu_has_vmx_ept_4levels()) {
6296                 enable_ept = 0;
6297                 enable_unrestricted_guest = 0;
6298                 enable_ept_ad_bits = 0;
6299         }
6300
6301         if (!cpu_has_vmx_ept_ad_bits())
6302                 enable_ept_ad_bits = 0;
6303
6304         if (!cpu_has_vmx_unrestricted_guest())
6305                 enable_unrestricted_guest = 0;
6306
6307         if (!cpu_has_vmx_flexpriority())
6308                 flexpriority_enabled = 0;
6309
6310         /*
6311          * set_apic_access_page_addr() is used to reload apic access
6312          * page upon invalidation.  No need to do anything if not
6313          * using the APIC_ACCESS_ADDR VMCS field.
6314          */
6315         if (!flexpriority_enabled)
6316                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6317
6318         if (!cpu_has_vmx_tpr_shadow())
6319                 kvm_x86_ops->update_cr8_intercept = NULL;
6320
6321         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6322                 kvm_disable_largepages();
6323
6324         if (!cpu_has_vmx_ple())
6325                 ple_gap = 0;
6326
6327         if (!cpu_has_vmx_apicv())
6328                 enable_apicv = 0;
6329
6330         if (cpu_has_vmx_tsc_scaling()) {
6331                 kvm_has_tsc_control = true;
6332                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6333                 kvm_tsc_scaling_ratio_frac_bits = 48;
6334         }
6335
6336         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6337         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6338         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6339         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6340         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6341         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6342         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6343
6344         memcpy(vmx_msr_bitmap_legacy_x2apic,
6345                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6346         memcpy(vmx_msr_bitmap_longmode_x2apic,
6347                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6348
6349         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6350
6351         for (msr = 0x800; msr <= 0x8ff; msr++)
6352                 vmx_disable_intercept_msr_read_x2apic(msr);
6353
6354         /* According SDM, in x2apic mode, the whole id reg is used.  But in
6355          * KVM, it only use the highest eight bits. Need to intercept it */
6356         vmx_enable_intercept_msr_read_x2apic(0x802);
6357         /* TMCCT */
6358         vmx_enable_intercept_msr_read_x2apic(0x839);
6359         /* TPR */
6360         vmx_disable_intercept_msr_write_x2apic(0x808);
6361         /* EOI */
6362         vmx_disable_intercept_msr_write_x2apic(0x80b);
6363         /* SELF-IPI */
6364         vmx_disable_intercept_msr_write_x2apic(0x83f);
6365
6366         if (enable_ept) {
6367                 kvm_mmu_set_mask_ptes(0ull,
6368                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6369                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6370                         0ull, VMX_EPT_EXECUTABLE_MASK);
6371                 ept_set_mmio_spte_mask();
6372                 kvm_enable_tdp();
6373         } else
6374                 kvm_disable_tdp();
6375
6376         update_ple_window_actual_max();
6377
6378         /*
6379          * Only enable PML when hardware supports PML feature, and both EPT
6380          * and EPT A/D bit features are enabled -- PML depends on them to work.
6381          */
6382         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6383                 enable_pml = 0;
6384
6385         if (!enable_pml) {
6386                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6387                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6388                 kvm_x86_ops->flush_log_dirty = NULL;
6389                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6390         }
6391
6392         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6393
6394         return alloc_kvm_area();
6395
6396 out8:
6397         free_page((unsigned long)vmx_vmwrite_bitmap);
6398 out7:
6399         free_page((unsigned long)vmx_vmread_bitmap);
6400 out6:
6401         if (nested)
6402                 free_page((unsigned long)vmx_msr_bitmap_nested);
6403 out5:
6404         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6405 out4:
6406         free_page((unsigned long)vmx_msr_bitmap_longmode);
6407 out3:
6408         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6409 out2:
6410         free_page((unsigned long)vmx_msr_bitmap_legacy);
6411 out1:
6412         free_page((unsigned long)vmx_io_bitmap_b);
6413 out:
6414         free_page((unsigned long)vmx_io_bitmap_a);
6415
6416     return r;
6417 }
6418
6419 static __exit void hardware_unsetup(void)
6420 {
6421         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6422         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6423         free_page((unsigned long)vmx_msr_bitmap_legacy);
6424         free_page((unsigned long)vmx_msr_bitmap_longmode);
6425         free_page((unsigned long)vmx_io_bitmap_b);
6426         free_page((unsigned long)vmx_io_bitmap_a);
6427         free_page((unsigned long)vmx_vmwrite_bitmap);
6428         free_page((unsigned long)vmx_vmread_bitmap);
6429         if (nested)
6430                 free_page((unsigned long)vmx_msr_bitmap_nested);
6431
6432         free_kvm_area();
6433 }
6434
6435 /*
6436  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6437  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6438  */
6439 static int handle_pause(struct kvm_vcpu *vcpu)
6440 {
6441         if (ple_gap)
6442                 grow_ple_window(vcpu);
6443
6444         skip_emulated_instruction(vcpu);
6445         kvm_vcpu_on_spin(vcpu);
6446
6447         return 1;
6448 }
6449
6450 static int handle_nop(struct kvm_vcpu *vcpu)
6451 {
6452         skip_emulated_instruction(vcpu);
6453         return 1;
6454 }
6455
6456 static int handle_mwait(struct kvm_vcpu *vcpu)
6457 {
6458         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6459         return handle_nop(vcpu);
6460 }
6461
6462 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6463 {
6464         return 1;
6465 }
6466
6467 static int handle_monitor(struct kvm_vcpu *vcpu)
6468 {
6469         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6470         return handle_nop(vcpu);
6471 }
6472
6473 /*
6474  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6475  * We could reuse a single VMCS for all the L2 guests, but we also want the
6476  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6477  * allows keeping them loaded on the processor, and in the future will allow
6478  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6479  * every entry if they never change.
6480  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6481  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6482  *
6483  * The following functions allocate and free a vmcs02 in this pool.
6484  */
6485
6486 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6487 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6488 {
6489         struct vmcs02_list *item;
6490         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6491                 if (item->vmptr == vmx->nested.current_vmptr) {
6492                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6493                         return &item->vmcs02;
6494                 }
6495
6496         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6497                 /* Recycle the least recently used VMCS. */
6498                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6499                                        struct vmcs02_list, list);
6500                 item->vmptr = vmx->nested.current_vmptr;
6501                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6502                 return &item->vmcs02;
6503         }
6504
6505         /* Create a new VMCS */
6506         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6507         if (!item)
6508                 return NULL;
6509         item->vmcs02.vmcs = alloc_vmcs();
6510         if (!item->vmcs02.vmcs) {
6511                 kfree(item);
6512                 return NULL;
6513         }
6514         loaded_vmcs_init(&item->vmcs02);
6515         item->vmptr = vmx->nested.current_vmptr;
6516         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6517         vmx->nested.vmcs02_num++;
6518         return &item->vmcs02;
6519 }
6520
6521 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6522 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6523 {
6524         struct vmcs02_list *item;
6525         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6526                 if (item->vmptr == vmptr) {
6527                         free_loaded_vmcs(&item->vmcs02);
6528                         list_del(&item->list);
6529                         kfree(item);
6530                         vmx->nested.vmcs02_num--;
6531                         return;
6532                 }
6533 }
6534
6535 /*
6536  * Free all VMCSs saved for this vcpu, except the one pointed by
6537  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6538  * must be &vmx->vmcs01.
6539  */
6540 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6541 {
6542         struct vmcs02_list *item, *n;
6543
6544         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6545         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6546                 /*
6547                  * Something will leak if the above WARN triggers.  Better than
6548                  * a use-after-free.
6549                  */
6550                 if (vmx->loaded_vmcs == &item->vmcs02)
6551                         continue;
6552
6553                 free_loaded_vmcs(&item->vmcs02);
6554                 list_del(&item->list);
6555                 kfree(item);
6556                 vmx->nested.vmcs02_num--;
6557         }
6558 }
6559
6560 /*
6561  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6562  * set the success or error code of an emulated VMX instruction, as specified
6563  * by Vol 2B, VMX Instruction Reference, "Conventions".
6564  */
6565 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6566 {
6567         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6568                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6569                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6570 }
6571
6572 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6573 {
6574         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6575                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6576                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6577                         | X86_EFLAGS_CF);
6578 }
6579
6580 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6581                                         u32 vm_instruction_error)
6582 {
6583         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6584                 /*
6585                  * failValid writes the error number to the current VMCS, which
6586                  * can't be done there isn't a current VMCS.
6587                  */
6588                 nested_vmx_failInvalid(vcpu);
6589                 return;
6590         }
6591         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6592                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6593                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6594                         | X86_EFLAGS_ZF);
6595         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6596         /*
6597          * We don't need to force a shadow sync because
6598          * VM_INSTRUCTION_ERROR is not shadowed
6599          */
6600 }
6601
6602 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6603 {
6604         /* TODO: not to reset guest simply here. */
6605         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6606         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6607 }
6608
6609 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6610 {
6611         struct vcpu_vmx *vmx =
6612                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6613
6614         vmx->nested.preemption_timer_expired = true;
6615         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6616         kvm_vcpu_kick(&vmx->vcpu);
6617
6618         return HRTIMER_NORESTART;
6619 }
6620
6621 /*
6622  * Decode the memory-address operand of a vmx instruction, as recorded on an
6623  * exit caused by such an instruction (run by a guest hypervisor).
6624  * On success, returns 0. When the operand is invalid, returns 1 and throws
6625  * #UD or #GP.
6626  */
6627 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6628                                  unsigned long exit_qualification,
6629                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6630 {
6631         gva_t off;
6632         bool exn;
6633         struct kvm_segment s;
6634
6635         /*
6636          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6637          * Execution", on an exit, vmx_instruction_info holds most of the
6638          * addressing components of the operand. Only the displacement part
6639          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6640          * For how an actual address is calculated from all these components,
6641          * refer to Vol. 1, "Operand Addressing".
6642          */
6643         int  scaling = vmx_instruction_info & 3;
6644         int  addr_size = (vmx_instruction_info >> 7) & 7;
6645         bool is_reg = vmx_instruction_info & (1u << 10);
6646         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6647         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6648         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6649         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6650         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6651
6652         if (is_reg) {
6653                 kvm_queue_exception(vcpu, UD_VECTOR);
6654                 return 1;
6655         }
6656
6657         /* Addr = segment_base + offset */
6658         /* offset = base + [index * scale] + displacement */
6659         off = exit_qualification; /* holds the displacement */
6660         if (base_is_valid)
6661                 off += kvm_register_read(vcpu, base_reg);
6662         if (index_is_valid)
6663                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6664         vmx_get_segment(vcpu, &s, seg_reg);
6665         *ret = s.base + off;
6666
6667         if (addr_size == 1) /* 32 bit */
6668                 *ret &= 0xffffffff;
6669
6670         /* Checks for #GP/#SS exceptions. */
6671         exn = false;
6672         if (is_protmode(vcpu)) {
6673                 /* Protected mode: apply checks for segment validity in the
6674                  * following order:
6675                  * - segment type check (#GP(0) may be thrown)
6676                  * - usability check (#GP(0)/#SS(0))
6677                  * - limit check (#GP(0)/#SS(0))
6678                  */
6679                 if (wr)
6680                         /* #GP(0) if the destination operand is located in a
6681                          * read-only data segment or any code segment.
6682                          */
6683                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6684                 else
6685                         /* #GP(0) if the source operand is located in an
6686                          * execute-only code segment
6687                          */
6688                         exn = ((s.type & 0xa) == 8);
6689         }
6690         if (exn) {
6691                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6692                 return 1;
6693         }
6694         if (is_long_mode(vcpu)) {
6695                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6696                  * non-canonical form. This is an only check for long mode.
6697                  */
6698                 exn = is_noncanonical_address(*ret);
6699         } else if (is_protmode(vcpu)) {
6700                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6701                  */
6702                 exn = (s.unusable != 0);
6703                 /* Protected mode: #GP(0)/#SS(0) if the memory
6704                  * operand is outside the segment limit.
6705                  */
6706                 exn = exn || (off + sizeof(u64) > s.limit);
6707         }
6708         if (exn) {
6709                 kvm_queue_exception_e(vcpu,
6710                                       seg_reg == VCPU_SREG_SS ?
6711                                                 SS_VECTOR : GP_VECTOR,
6712                                       0);
6713                 return 1;
6714         }
6715
6716         return 0;
6717 }
6718
6719 /*
6720  * This function performs the various checks including
6721  * - if it's 4KB aligned
6722  * - No bits beyond the physical address width are set
6723  * - Returns 0 on success or else 1
6724  * (Intel SDM Section 30.3)
6725  */
6726 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6727                                   gpa_t *vmpointer)
6728 {
6729         gva_t gva;
6730         gpa_t vmptr;
6731         struct x86_exception e;
6732         struct page *page;
6733         struct vcpu_vmx *vmx = to_vmx(vcpu);
6734         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6735
6736         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6737                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6738                 return 1;
6739
6740         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6741                                 sizeof(vmptr), &e)) {
6742                 kvm_inject_page_fault(vcpu, &e);
6743                 return 1;
6744         }
6745
6746         switch (exit_reason) {
6747         case EXIT_REASON_VMON:
6748                 /*
6749                  * SDM 3: 24.11.5
6750                  * The first 4 bytes of VMXON region contain the supported
6751                  * VMCS revision identifier
6752                  *
6753                  * Note - IA32_VMX_BASIC[48] will never be 1
6754                  * for the nested case;
6755                  * which replaces physical address width with 32
6756                  *
6757                  */
6758                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6759                         nested_vmx_failInvalid(vcpu);
6760                         skip_emulated_instruction(vcpu);
6761                         return 1;
6762                 }
6763
6764                 page = nested_get_page(vcpu, vmptr);
6765                 if (page == NULL ||
6766                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6767                         nested_vmx_failInvalid(vcpu);
6768                         kunmap(page);
6769                         skip_emulated_instruction(vcpu);
6770                         return 1;
6771                 }
6772                 kunmap(page);
6773                 vmx->nested.vmxon_ptr = vmptr;
6774                 break;
6775         case EXIT_REASON_VMCLEAR:
6776                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6777                         nested_vmx_failValid(vcpu,
6778                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6779                         skip_emulated_instruction(vcpu);
6780                         return 1;
6781                 }
6782
6783                 if (vmptr == vmx->nested.vmxon_ptr) {
6784                         nested_vmx_failValid(vcpu,
6785                                              VMXERR_VMCLEAR_VMXON_POINTER);
6786                         skip_emulated_instruction(vcpu);
6787                         return 1;
6788                 }
6789                 break;
6790         case EXIT_REASON_VMPTRLD:
6791                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6792                         nested_vmx_failValid(vcpu,
6793                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6794                         skip_emulated_instruction(vcpu);
6795                         return 1;
6796                 }
6797
6798                 if (vmptr == vmx->nested.vmxon_ptr) {
6799                         nested_vmx_failValid(vcpu,
6800                                              VMXERR_VMCLEAR_VMXON_POINTER);
6801                         skip_emulated_instruction(vcpu);
6802                         return 1;
6803                 }
6804                 break;
6805         default:
6806                 return 1; /* shouldn't happen */
6807         }
6808
6809         if (vmpointer)
6810                 *vmpointer = vmptr;
6811         return 0;
6812 }
6813
6814 /*
6815  * Emulate the VMXON instruction.
6816  * Currently, we just remember that VMX is active, and do not save or even
6817  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6818  * do not currently need to store anything in that guest-allocated memory
6819  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6820  * argument is different from the VMXON pointer (which the spec says they do).
6821  */
6822 static int handle_vmon(struct kvm_vcpu *vcpu)
6823 {
6824         struct kvm_segment cs;
6825         struct vcpu_vmx *vmx = to_vmx(vcpu);
6826         struct vmcs *shadow_vmcs;
6827         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6828                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6829
6830         /* The Intel VMX Instruction Reference lists a bunch of bits that
6831          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6832          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6833          * Otherwise, we should fail with #UD. We test these now:
6834          */
6835         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6836             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6837             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6838                 kvm_queue_exception(vcpu, UD_VECTOR);
6839                 return 1;
6840         }
6841
6842         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6843         if (is_long_mode(vcpu) && !cs.l) {
6844                 kvm_queue_exception(vcpu, UD_VECTOR);
6845                 return 1;
6846         }
6847
6848         if (vmx_get_cpl(vcpu)) {
6849                 kvm_inject_gp(vcpu, 0);
6850                 return 1;
6851         }
6852
6853         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6854                 return 1;
6855
6856         if (vmx->nested.vmxon) {
6857                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6858                 skip_emulated_instruction(vcpu);
6859                 return 1;
6860         }
6861
6862         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6863                         != VMXON_NEEDED_FEATURES) {
6864                 kvm_inject_gp(vcpu, 0);
6865                 return 1;
6866         }
6867
6868         if (enable_shadow_vmcs) {
6869                 shadow_vmcs = alloc_vmcs();
6870                 if (!shadow_vmcs)
6871                         return -ENOMEM;
6872                 /* mark vmcs as shadow */
6873                 shadow_vmcs->revision_id |= (1u << 31);
6874                 /* init shadow vmcs */
6875                 vmcs_clear(shadow_vmcs);
6876                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6877         }
6878
6879         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6880         vmx->nested.vmcs02_num = 0;
6881
6882         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6883                      HRTIMER_MODE_REL);
6884         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6885
6886         vmx->nested.vmxon = true;
6887
6888         skip_emulated_instruction(vcpu);
6889         nested_vmx_succeed(vcpu);
6890         return 1;
6891 }
6892
6893 /*
6894  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6895  * for running VMX instructions (except VMXON, whose prerequisites are
6896  * slightly different). It also specifies what exception to inject otherwise.
6897  */
6898 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6899 {
6900         struct kvm_segment cs;
6901         struct vcpu_vmx *vmx = to_vmx(vcpu);
6902
6903         if (!vmx->nested.vmxon) {
6904                 kvm_queue_exception(vcpu, UD_VECTOR);
6905                 return 0;
6906         }
6907
6908         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6909         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6910             (is_long_mode(vcpu) && !cs.l)) {
6911                 kvm_queue_exception(vcpu, UD_VECTOR);
6912                 return 0;
6913         }
6914
6915         if (vmx_get_cpl(vcpu)) {
6916                 kvm_inject_gp(vcpu, 0);
6917                 return 0;
6918         }
6919
6920         return 1;
6921 }
6922
6923 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6924 {
6925         if (vmx->nested.current_vmptr == -1ull)
6926                 return;
6927
6928         /* current_vmptr and current_vmcs12 are always set/reset together */
6929         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6930                 return;
6931
6932         if (enable_shadow_vmcs) {
6933                 /* copy to memory all shadowed fields in case
6934                    they were modified */
6935                 copy_shadow_to_vmcs12(vmx);
6936                 vmx->nested.sync_shadow_vmcs = false;
6937                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6938                                 SECONDARY_EXEC_SHADOW_VMCS);
6939                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6940         }
6941         vmx->nested.posted_intr_nv = -1;
6942         kunmap(vmx->nested.current_vmcs12_page);
6943         nested_release_page(vmx->nested.current_vmcs12_page);
6944         vmx->nested.current_vmptr = -1ull;
6945         vmx->nested.current_vmcs12 = NULL;
6946 }
6947
6948 /*
6949  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6950  * just stops using VMX.
6951  */
6952 static void free_nested(struct vcpu_vmx *vmx)
6953 {
6954         if (!vmx->nested.vmxon)
6955                 return;
6956
6957         vmx->nested.vmxon = false;
6958         free_vpid(vmx->nested.vpid02);
6959         nested_release_vmcs12(vmx);
6960         if (enable_shadow_vmcs)
6961                 free_vmcs(vmx->nested.current_shadow_vmcs);
6962         /* Unpin physical memory we referred to in current vmcs02 */
6963         if (vmx->nested.apic_access_page) {
6964                 nested_release_page(vmx->nested.apic_access_page);
6965                 vmx->nested.apic_access_page = NULL;
6966         }
6967         if (vmx->nested.virtual_apic_page) {
6968                 nested_release_page(vmx->nested.virtual_apic_page);
6969                 vmx->nested.virtual_apic_page = NULL;
6970         }
6971         if (vmx->nested.pi_desc_page) {
6972                 kunmap(vmx->nested.pi_desc_page);
6973                 nested_release_page(vmx->nested.pi_desc_page);
6974                 vmx->nested.pi_desc_page = NULL;
6975                 vmx->nested.pi_desc = NULL;
6976         }
6977
6978         nested_free_all_saved_vmcss(vmx);
6979 }
6980
6981 /* Emulate the VMXOFF instruction */
6982 static int handle_vmoff(struct kvm_vcpu *vcpu)
6983 {
6984         if (!nested_vmx_check_permission(vcpu))
6985                 return 1;
6986         free_nested(to_vmx(vcpu));
6987         skip_emulated_instruction(vcpu);
6988         nested_vmx_succeed(vcpu);
6989         return 1;
6990 }
6991
6992 /* Emulate the VMCLEAR instruction */
6993 static int handle_vmclear(struct kvm_vcpu *vcpu)
6994 {
6995         struct vcpu_vmx *vmx = to_vmx(vcpu);
6996         gpa_t vmptr;
6997         struct vmcs12 *vmcs12;
6998         struct page *page;
6999
7000         if (!nested_vmx_check_permission(vcpu))
7001                 return 1;
7002
7003         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7004                 return 1;
7005
7006         if (vmptr == vmx->nested.current_vmptr)
7007                 nested_release_vmcs12(vmx);
7008
7009         page = nested_get_page(vcpu, vmptr);
7010         if (page == NULL) {
7011                 /*
7012                  * For accurate processor emulation, VMCLEAR beyond available
7013                  * physical memory should do nothing at all. However, it is
7014                  * possible that a nested vmx bug, not a guest hypervisor bug,
7015                  * resulted in this case, so let's shut down before doing any
7016                  * more damage:
7017                  */
7018                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7019                 return 1;
7020         }
7021         vmcs12 = kmap(page);
7022         vmcs12->launch_state = 0;
7023         kunmap(page);
7024         nested_release_page(page);
7025
7026         nested_free_vmcs02(vmx, vmptr);
7027
7028         skip_emulated_instruction(vcpu);
7029         nested_vmx_succeed(vcpu);
7030         return 1;
7031 }
7032
7033 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7034
7035 /* Emulate the VMLAUNCH instruction */
7036 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7037 {
7038         return nested_vmx_run(vcpu, true);
7039 }
7040
7041 /* Emulate the VMRESUME instruction */
7042 static int handle_vmresume(struct kvm_vcpu *vcpu)
7043 {
7044
7045         return nested_vmx_run(vcpu, false);
7046 }
7047
7048 enum vmcs_field_type {
7049         VMCS_FIELD_TYPE_U16 = 0,
7050         VMCS_FIELD_TYPE_U64 = 1,
7051         VMCS_FIELD_TYPE_U32 = 2,
7052         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7053 };
7054
7055 static inline int vmcs_field_type(unsigned long field)
7056 {
7057         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7058                 return VMCS_FIELD_TYPE_U32;
7059         return (field >> 13) & 0x3 ;
7060 }
7061
7062 static inline int vmcs_field_readonly(unsigned long field)
7063 {
7064         return (((field >> 10) & 0x3) == 1);
7065 }
7066
7067 /*
7068  * Read a vmcs12 field. Since these can have varying lengths and we return
7069  * one type, we chose the biggest type (u64) and zero-extend the return value
7070  * to that size. Note that the caller, handle_vmread, might need to use only
7071  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7072  * 64-bit fields are to be returned).
7073  */
7074 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7075                                   unsigned long field, u64 *ret)
7076 {
7077         short offset = vmcs_field_to_offset(field);
7078         char *p;
7079
7080         if (offset < 0)
7081                 return offset;
7082
7083         p = ((char *)(get_vmcs12(vcpu))) + offset;
7084
7085         switch (vmcs_field_type(field)) {
7086         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7087                 *ret = *((natural_width *)p);
7088                 return 0;
7089         case VMCS_FIELD_TYPE_U16:
7090                 *ret = *((u16 *)p);
7091                 return 0;
7092         case VMCS_FIELD_TYPE_U32:
7093                 *ret = *((u32 *)p);
7094                 return 0;
7095         case VMCS_FIELD_TYPE_U64:
7096                 *ret = *((u64 *)p);
7097                 return 0;
7098         default:
7099                 WARN_ON(1);
7100                 return -ENOENT;
7101         }
7102 }
7103
7104
7105 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7106                                    unsigned long field, u64 field_value){
7107         short offset = vmcs_field_to_offset(field);
7108         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7109         if (offset < 0)
7110                 return offset;
7111
7112         switch (vmcs_field_type(field)) {
7113         case VMCS_FIELD_TYPE_U16:
7114                 *(u16 *)p = field_value;
7115                 return 0;
7116         case VMCS_FIELD_TYPE_U32:
7117                 *(u32 *)p = field_value;
7118                 return 0;
7119         case VMCS_FIELD_TYPE_U64:
7120                 *(u64 *)p = field_value;
7121                 return 0;
7122         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7123                 *(natural_width *)p = field_value;
7124                 return 0;
7125         default:
7126                 WARN_ON(1);
7127                 return -ENOENT;
7128         }
7129
7130 }
7131
7132 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7133 {
7134         int i;
7135         unsigned long field;
7136         u64 field_value;
7137         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7138         const unsigned long *fields = shadow_read_write_fields;
7139         const int num_fields = max_shadow_read_write_fields;
7140
7141         preempt_disable();
7142
7143         vmcs_load(shadow_vmcs);
7144
7145         for (i = 0; i < num_fields; i++) {
7146                 field = fields[i];
7147                 switch (vmcs_field_type(field)) {
7148                 case VMCS_FIELD_TYPE_U16:
7149                         field_value = vmcs_read16(field);
7150                         break;
7151                 case VMCS_FIELD_TYPE_U32:
7152                         field_value = vmcs_read32(field);
7153                         break;
7154                 case VMCS_FIELD_TYPE_U64:
7155                         field_value = vmcs_read64(field);
7156                         break;
7157                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7158                         field_value = vmcs_readl(field);
7159                         break;
7160                 default:
7161                         WARN_ON(1);
7162                         continue;
7163                 }
7164                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7165         }
7166
7167         vmcs_clear(shadow_vmcs);
7168         vmcs_load(vmx->loaded_vmcs->vmcs);
7169
7170         preempt_enable();
7171 }
7172
7173 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7174 {
7175         const unsigned long *fields[] = {
7176                 shadow_read_write_fields,
7177                 shadow_read_only_fields
7178         };
7179         const int max_fields[] = {
7180                 max_shadow_read_write_fields,
7181                 max_shadow_read_only_fields
7182         };
7183         int i, q;
7184         unsigned long field;
7185         u64 field_value = 0;
7186         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7187
7188         vmcs_load(shadow_vmcs);
7189
7190         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7191                 for (i = 0; i < max_fields[q]; i++) {
7192                         field = fields[q][i];
7193                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7194
7195                         switch (vmcs_field_type(field)) {
7196                         case VMCS_FIELD_TYPE_U16:
7197                                 vmcs_write16(field, (u16)field_value);
7198                                 break;
7199                         case VMCS_FIELD_TYPE_U32:
7200                                 vmcs_write32(field, (u32)field_value);
7201                                 break;
7202                         case VMCS_FIELD_TYPE_U64:
7203                                 vmcs_write64(field, (u64)field_value);
7204                                 break;
7205                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7206                                 vmcs_writel(field, (long)field_value);
7207                                 break;
7208                         default:
7209                                 WARN_ON(1);
7210                                 break;
7211                         }
7212                 }
7213         }
7214
7215         vmcs_clear(shadow_vmcs);
7216         vmcs_load(vmx->loaded_vmcs->vmcs);
7217 }
7218
7219 /*
7220  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7221  * used before) all generate the same failure when it is missing.
7222  */
7223 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7224 {
7225         struct vcpu_vmx *vmx = to_vmx(vcpu);
7226         if (vmx->nested.current_vmptr == -1ull) {
7227                 nested_vmx_failInvalid(vcpu);
7228                 skip_emulated_instruction(vcpu);
7229                 return 0;
7230         }
7231         return 1;
7232 }
7233
7234 static int handle_vmread(struct kvm_vcpu *vcpu)
7235 {
7236         unsigned long field;
7237         u64 field_value;
7238         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7239         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7240         gva_t gva = 0;
7241
7242         if (!nested_vmx_check_permission(vcpu) ||
7243             !nested_vmx_check_vmcs12(vcpu))
7244                 return 1;
7245
7246         /* Decode instruction info and find the field to read */
7247         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7248         /* Read the field, zero-extended to a u64 field_value */
7249         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7250                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7251                 skip_emulated_instruction(vcpu);
7252                 return 1;
7253         }
7254         /*
7255          * Now copy part of this value to register or memory, as requested.
7256          * Note that the number of bits actually copied is 32 or 64 depending
7257          * on the guest's mode (32 or 64 bit), not on the given field's length.
7258          */
7259         if (vmx_instruction_info & (1u << 10)) {
7260                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7261                         field_value);
7262         } else {
7263                 if (get_vmx_mem_address(vcpu, exit_qualification,
7264                                 vmx_instruction_info, true, &gva))
7265                         return 1;
7266                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7267                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7268                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7269         }
7270
7271         nested_vmx_succeed(vcpu);
7272         skip_emulated_instruction(vcpu);
7273         return 1;
7274 }
7275
7276
7277 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7278 {
7279         unsigned long field;
7280         gva_t gva;
7281         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7282         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7283         /* The value to write might be 32 or 64 bits, depending on L1's long
7284          * mode, and eventually we need to write that into a field of several
7285          * possible lengths. The code below first zero-extends the value to 64
7286          * bit (field_value), and then copies only the appropriate number of
7287          * bits into the vmcs12 field.
7288          */
7289         u64 field_value = 0;
7290         struct x86_exception e;
7291
7292         if (!nested_vmx_check_permission(vcpu) ||
7293             !nested_vmx_check_vmcs12(vcpu))
7294                 return 1;
7295
7296         if (vmx_instruction_info & (1u << 10))
7297                 field_value = kvm_register_readl(vcpu,
7298                         (((vmx_instruction_info) >> 3) & 0xf));
7299         else {
7300                 if (get_vmx_mem_address(vcpu, exit_qualification,
7301                                 vmx_instruction_info, false, &gva))
7302                         return 1;
7303                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7304                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7305                         kvm_inject_page_fault(vcpu, &e);
7306                         return 1;
7307                 }
7308         }
7309
7310
7311         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7312         if (vmcs_field_readonly(field)) {
7313                 nested_vmx_failValid(vcpu,
7314                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7315                 skip_emulated_instruction(vcpu);
7316                 return 1;
7317         }
7318
7319         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7320                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7321                 skip_emulated_instruction(vcpu);
7322                 return 1;
7323         }
7324
7325         nested_vmx_succeed(vcpu);
7326         skip_emulated_instruction(vcpu);
7327         return 1;
7328 }
7329
7330 /* Emulate the VMPTRLD instruction */
7331 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7332 {
7333         struct vcpu_vmx *vmx = to_vmx(vcpu);
7334         gpa_t vmptr;
7335
7336         if (!nested_vmx_check_permission(vcpu))
7337                 return 1;
7338
7339         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7340                 return 1;
7341
7342         if (vmx->nested.current_vmptr != vmptr) {
7343                 struct vmcs12 *new_vmcs12;
7344                 struct page *page;
7345                 page = nested_get_page(vcpu, vmptr);
7346                 if (page == NULL) {
7347                         nested_vmx_failInvalid(vcpu);
7348                         skip_emulated_instruction(vcpu);
7349                         return 1;
7350                 }
7351                 new_vmcs12 = kmap(page);
7352                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7353                         kunmap(page);
7354                         nested_release_page_clean(page);
7355                         nested_vmx_failValid(vcpu,
7356                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7357                         skip_emulated_instruction(vcpu);
7358                         return 1;
7359                 }
7360
7361                 nested_release_vmcs12(vmx);
7362                 vmx->nested.current_vmptr = vmptr;
7363                 vmx->nested.current_vmcs12 = new_vmcs12;
7364                 vmx->nested.current_vmcs12_page = page;
7365                 if (enable_shadow_vmcs) {
7366                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7367                                       SECONDARY_EXEC_SHADOW_VMCS);
7368                         vmcs_write64(VMCS_LINK_POINTER,
7369                                      __pa(vmx->nested.current_shadow_vmcs));
7370                         vmx->nested.sync_shadow_vmcs = true;
7371                 }
7372         }
7373
7374         nested_vmx_succeed(vcpu);
7375         skip_emulated_instruction(vcpu);
7376         return 1;
7377 }
7378
7379 /* Emulate the VMPTRST instruction */
7380 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7381 {
7382         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7383         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7384         gva_t vmcs_gva;
7385         struct x86_exception e;
7386
7387         if (!nested_vmx_check_permission(vcpu))
7388                 return 1;
7389
7390         if (get_vmx_mem_address(vcpu, exit_qualification,
7391                         vmx_instruction_info, true, &vmcs_gva))
7392                 return 1;
7393         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7394         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7395                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7396                                  sizeof(u64), &e)) {
7397                 kvm_inject_page_fault(vcpu, &e);
7398                 return 1;
7399         }
7400         nested_vmx_succeed(vcpu);
7401         skip_emulated_instruction(vcpu);
7402         return 1;
7403 }
7404
7405 /* Emulate the INVEPT instruction */
7406 static int handle_invept(struct kvm_vcpu *vcpu)
7407 {
7408         struct vcpu_vmx *vmx = to_vmx(vcpu);
7409         u32 vmx_instruction_info, types;
7410         unsigned long type;
7411         gva_t gva;
7412         struct x86_exception e;
7413         struct {
7414                 u64 eptp, gpa;
7415         } operand;
7416
7417         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7418               SECONDARY_EXEC_ENABLE_EPT) ||
7419             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7420                 kvm_queue_exception(vcpu, UD_VECTOR);
7421                 return 1;
7422         }
7423
7424         if (!nested_vmx_check_permission(vcpu))
7425                 return 1;
7426
7427         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7428                 kvm_queue_exception(vcpu, UD_VECTOR);
7429                 return 1;
7430         }
7431
7432         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7433         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7434
7435         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7436
7437         if (!(types & (1UL << type))) {
7438                 nested_vmx_failValid(vcpu,
7439                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7440                 skip_emulated_instruction(vcpu);
7441                 return 1;
7442         }
7443
7444         /* According to the Intel VMX instruction reference, the memory
7445          * operand is read even if it isn't needed (e.g., for type==global)
7446          */
7447         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7448                         vmx_instruction_info, false, &gva))
7449                 return 1;
7450         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7451                                 sizeof(operand), &e)) {
7452                 kvm_inject_page_fault(vcpu, &e);
7453                 return 1;
7454         }
7455
7456         switch (type) {
7457         case VMX_EPT_EXTENT_GLOBAL:
7458                 kvm_mmu_sync_roots(vcpu);
7459                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7460                 nested_vmx_succeed(vcpu);
7461                 break;
7462         default:
7463                 /* Trap single context invalidation invept calls */
7464                 BUG_ON(1);
7465                 break;
7466         }
7467
7468         skip_emulated_instruction(vcpu);
7469         return 1;
7470 }
7471
7472 static int handle_invvpid(struct kvm_vcpu *vcpu)
7473 {
7474         struct vcpu_vmx *vmx = to_vmx(vcpu);
7475         u32 vmx_instruction_info;
7476         unsigned long type, types;
7477         gva_t gva;
7478         struct x86_exception e;
7479         int vpid;
7480
7481         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7482               SECONDARY_EXEC_ENABLE_VPID) ||
7483                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7484                 kvm_queue_exception(vcpu, UD_VECTOR);
7485                 return 1;
7486         }
7487
7488         if (!nested_vmx_check_permission(vcpu))
7489                 return 1;
7490
7491         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7492         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7493
7494         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7495
7496         if (!(types & (1UL << type))) {
7497                 nested_vmx_failValid(vcpu,
7498                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7499                 skip_emulated_instruction(vcpu);
7500                 return 1;
7501         }
7502
7503         /* according to the intel vmx instruction reference, the memory
7504          * operand is read even if it isn't needed (e.g., for type==global)
7505          */
7506         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7507                         vmx_instruction_info, false, &gva))
7508                 return 1;
7509         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7510                                 sizeof(u32), &e)) {
7511                 kvm_inject_page_fault(vcpu, &e);
7512                 return 1;
7513         }
7514
7515         switch (type) {
7516         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7517                 /*
7518                  * Old versions of KVM use the single-context version so we
7519                  * have to support it; just treat it the same as all-context.
7520                  */
7521         case VMX_VPID_EXTENT_ALL_CONTEXT:
7522                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7523                 nested_vmx_succeed(vcpu);
7524                 break;
7525         default:
7526                 /* Trap individual address invalidation invvpid calls */
7527                 BUG_ON(1);
7528                 break;
7529         }
7530
7531         skip_emulated_instruction(vcpu);
7532         return 1;
7533 }
7534
7535 static int handle_pml_full(struct kvm_vcpu *vcpu)
7536 {
7537         unsigned long exit_qualification;
7538
7539         trace_kvm_pml_full(vcpu->vcpu_id);
7540
7541         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7542
7543         /*
7544          * PML buffer FULL happened while executing iret from NMI,
7545          * "blocked by NMI" bit has to be set before next VM entry.
7546          */
7547         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7548                         cpu_has_virtual_nmis() &&
7549                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7550                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7551                                 GUEST_INTR_STATE_NMI);
7552
7553         /*
7554          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7555          * here.., and there's no userspace involvement needed for PML.
7556          */
7557         return 1;
7558 }
7559
7560 static int handle_pcommit(struct kvm_vcpu *vcpu)
7561 {
7562         /* we never catch pcommit instruct for L1 guest. */
7563         WARN_ON(1);
7564         return 1;
7565 }
7566
7567 /*
7568  * The exit handlers return 1 if the exit was handled fully and guest execution
7569  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7570  * to be done to userspace and return 0.
7571  */
7572 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7573         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7574         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7575         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7576         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7577         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7578         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7579         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7580         [EXIT_REASON_CPUID]                   = handle_cpuid,
7581         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7582         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7583         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7584         [EXIT_REASON_HLT]                     = handle_halt,
7585         [EXIT_REASON_INVD]                    = handle_invd,
7586         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7587         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7588         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7589         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7590         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7591         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7592         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7593         [EXIT_REASON_VMREAD]                  = handle_vmread,
7594         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7595         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7596         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7597         [EXIT_REASON_VMON]                    = handle_vmon,
7598         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7599         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7600         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7601         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7602         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7603         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7604         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7605         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7606         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7607         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7608         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7609         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7610         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7611         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7612         [EXIT_REASON_INVEPT]                  = handle_invept,
7613         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7614         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7615         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7616         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7617         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7618 };
7619
7620 static const int kvm_vmx_max_exit_handlers =
7621         ARRAY_SIZE(kvm_vmx_exit_handlers);
7622
7623 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7624                                        struct vmcs12 *vmcs12)
7625 {
7626         unsigned long exit_qualification;
7627         gpa_t bitmap, last_bitmap;
7628         unsigned int port;
7629         int size;
7630         u8 b;
7631
7632         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7633                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7634
7635         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7636
7637         port = exit_qualification >> 16;
7638         size = (exit_qualification & 7) + 1;
7639
7640         last_bitmap = (gpa_t)-1;
7641         b = -1;
7642
7643         while (size > 0) {
7644                 if (port < 0x8000)
7645                         bitmap = vmcs12->io_bitmap_a;
7646                 else if (port < 0x10000)
7647                         bitmap = vmcs12->io_bitmap_b;
7648                 else
7649                         return true;
7650                 bitmap += (port & 0x7fff) / 8;
7651
7652                 if (last_bitmap != bitmap)
7653                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7654                                 return true;
7655                 if (b & (1 << (port & 7)))
7656                         return true;
7657
7658                 port++;
7659                 size--;
7660                 last_bitmap = bitmap;
7661         }
7662
7663         return false;
7664 }
7665
7666 /*
7667  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7668  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7669  * disinterest in the current event (read or write a specific MSR) by using an
7670  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7671  */
7672 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7673         struct vmcs12 *vmcs12, u32 exit_reason)
7674 {
7675         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7676         gpa_t bitmap;
7677
7678         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7679                 return true;
7680
7681         /*
7682          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7683          * for the four combinations of read/write and low/high MSR numbers.
7684          * First we need to figure out which of the four to use:
7685          */
7686         bitmap = vmcs12->msr_bitmap;
7687         if (exit_reason == EXIT_REASON_MSR_WRITE)
7688                 bitmap += 2048;
7689         if (msr_index >= 0xc0000000) {
7690                 msr_index -= 0xc0000000;
7691                 bitmap += 1024;
7692         }
7693
7694         /* Then read the msr_index'th bit from this bitmap: */
7695         if (msr_index < 1024*8) {
7696                 unsigned char b;
7697                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7698                         return true;
7699                 return 1 & (b >> (msr_index & 7));
7700         } else
7701                 return true; /* let L1 handle the wrong parameter */
7702 }
7703
7704 /*
7705  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7706  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7707  * intercept (via guest_host_mask etc.) the current event.
7708  */
7709 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7710         struct vmcs12 *vmcs12)
7711 {
7712         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7713         int cr = exit_qualification & 15;
7714         int reg = (exit_qualification >> 8) & 15;
7715         unsigned long val = kvm_register_readl(vcpu, reg);
7716
7717         switch ((exit_qualification >> 4) & 3) {
7718         case 0: /* mov to cr */
7719                 switch (cr) {
7720                 case 0:
7721                         if (vmcs12->cr0_guest_host_mask &
7722                             (val ^ vmcs12->cr0_read_shadow))
7723                                 return true;
7724                         break;
7725                 case 3:
7726                         if ((vmcs12->cr3_target_count >= 1 &&
7727                                         vmcs12->cr3_target_value0 == val) ||
7728                                 (vmcs12->cr3_target_count >= 2 &&
7729                                         vmcs12->cr3_target_value1 == val) ||
7730                                 (vmcs12->cr3_target_count >= 3 &&
7731                                         vmcs12->cr3_target_value2 == val) ||
7732                                 (vmcs12->cr3_target_count >= 4 &&
7733                                         vmcs12->cr3_target_value3 == val))
7734                                 return false;
7735                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7736                                 return true;
7737                         break;
7738                 case 4:
7739                         if (vmcs12->cr4_guest_host_mask &
7740                             (vmcs12->cr4_read_shadow ^ val))
7741                                 return true;
7742                         break;
7743                 case 8:
7744                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7745                                 return true;
7746                         break;
7747                 }
7748                 break;
7749         case 2: /* clts */
7750                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7751                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7752                         return true;
7753                 break;
7754         case 1: /* mov from cr */
7755                 switch (cr) {
7756                 case 3:
7757                         if (vmcs12->cpu_based_vm_exec_control &
7758                             CPU_BASED_CR3_STORE_EXITING)
7759                                 return true;
7760                         break;
7761                 case 8:
7762                         if (vmcs12->cpu_based_vm_exec_control &
7763                             CPU_BASED_CR8_STORE_EXITING)
7764                                 return true;
7765                         break;
7766                 }
7767                 break;
7768         case 3: /* lmsw */
7769                 /*
7770                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7771                  * cr0. Other attempted changes are ignored, with no exit.
7772                  */
7773                 if (vmcs12->cr0_guest_host_mask & 0xe &
7774                     (val ^ vmcs12->cr0_read_shadow))
7775                         return true;
7776                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7777                     !(vmcs12->cr0_read_shadow & 0x1) &&
7778                     (val & 0x1))
7779                         return true;
7780                 break;
7781         }
7782         return false;
7783 }
7784
7785 /*
7786  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7787  * should handle it ourselves in L0 (and then continue L2). Only call this
7788  * when in is_guest_mode (L2).
7789  */
7790 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7791 {
7792         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7793         struct vcpu_vmx *vmx = to_vmx(vcpu);
7794         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7795         u32 exit_reason = vmx->exit_reason;
7796
7797         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7798                                 vmcs_readl(EXIT_QUALIFICATION),
7799                                 vmx->idt_vectoring_info,
7800                                 intr_info,
7801                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7802                                 KVM_ISA_VMX);
7803
7804         if (vmx->nested.nested_run_pending)
7805                 return false;
7806
7807         if (unlikely(vmx->fail)) {
7808                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7809                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7810                 return true;
7811         }
7812
7813         switch (exit_reason) {
7814         case EXIT_REASON_EXCEPTION_NMI:
7815                 if (!is_exception(intr_info))
7816                         return false;
7817                 else if (is_page_fault(intr_info))
7818                         return enable_ept;
7819                 else if (is_no_device(intr_info) &&
7820                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7821                         return false;
7822                 else if (is_debug(intr_info) &&
7823                          vcpu->guest_debug &
7824                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7825                         return false;
7826                 else if (is_breakpoint(intr_info) &&
7827                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7828                         return false;
7829                 return vmcs12->exception_bitmap &
7830                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7831         case EXIT_REASON_EXTERNAL_INTERRUPT:
7832                 return false;
7833         case EXIT_REASON_TRIPLE_FAULT:
7834                 return true;
7835         case EXIT_REASON_PENDING_INTERRUPT:
7836                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7837         case EXIT_REASON_NMI_WINDOW:
7838                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7839         case EXIT_REASON_TASK_SWITCH:
7840                 return true;
7841         case EXIT_REASON_CPUID:
7842                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7843                         return false;
7844                 return true;
7845         case EXIT_REASON_HLT:
7846                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7847         case EXIT_REASON_INVD:
7848                 return true;
7849         case EXIT_REASON_INVLPG:
7850                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7851         case EXIT_REASON_RDPMC:
7852                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7853         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7854                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7855         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7856         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7857         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7858         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7859         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7860         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7861                 /*
7862                  * VMX instructions trap unconditionally. This allows L1 to
7863                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7864                  */
7865                 return true;
7866         case EXIT_REASON_CR_ACCESS:
7867                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7868         case EXIT_REASON_DR_ACCESS:
7869                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7870         case EXIT_REASON_IO_INSTRUCTION:
7871                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7872         case EXIT_REASON_MSR_READ:
7873         case EXIT_REASON_MSR_WRITE:
7874                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7875         case EXIT_REASON_INVALID_STATE:
7876                 return true;
7877         case EXIT_REASON_MWAIT_INSTRUCTION:
7878                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7879         case EXIT_REASON_MONITOR_TRAP_FLAG:
7880                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7881         case EXIT_REASON_MONITOR_INSTRUCTION:
7882                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7883         case EXIT_REASON_PAUSE_INSTRUCTION:
7884                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7885                         nested_cpu_has2(vmcs12,
7886                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7887         case EXIT_REASON_MCE_DURING_VMENTRY:
7888                 return false;
7889         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7890                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7891         case EXIT_REASON_APIC_ACCESS:
7892                 return nested_cpu_has2(vmcs12,
7893                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7894         case EXIT_REASON_APIC_WRITE:
7895         case EXIT_REASON_EOI_INDUCED:
7896                 /* apic_write and eoi_induced should exit unconditionally. */
7897                 return true;
7898         case EXIT_REASON_EPT_VIOLATION:
7899                 /*
7900                  * L0 always deals with the EPT violation. If nested EPT is
7901                  * used, and the nested mmu code discovers that the address is
7902                  * missing in the guest EPT table (EPT12), the EPT violation
7903                  * will be injected with nested_ept_inject_page_fault()
7904                  */
7905                 return false;
7906         case EXIT_REASON_EPT_MISCONFIG:
7907                 /*
7908                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7909                  * table (shadow on EPT) or a merged EPT table that L0 built
7910                  * (EPT on EPT). So any problems with the structure of the
7911                  * table is L0's fault.
7912                  */
7913                 return false;
7914         case EXIT_REASON_WBINVD:
7915                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7916         case EXIT_REASON_XSETBV:
7917                 return true;
7918         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7919                 /*
7920                  * This should never happen, since it is not possible to
7921                  * set XSS to a non-zero value---neither in L1 nor in L2.
7922                  * If if it were, XSS would have to be checked against
7923                  * the XSS exit bitmap in vmcs12.
7924                  */
7925                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7926         case EXIT_REASON_PCOMMIT:
7927                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7928         default:
7929                 return true;
7930         }
7931 }
7932
7933 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7934 {
7935         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7936         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7937 }
7938
7939 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7940 {
7941         struct page *pml_pg;
7942
7943         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7944         if (!pml_pg)
7945                 return -ENOMEM;
7946
7947         vmx->pml_pg = pml_pg;
7948
7949         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7950         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7951
7952         return 0;
7953 }
7954
7955 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7956 {
7957         if (vmx->pml_pg) {
7958                 __free_page(vmx->pml_pg);
7959                 vmx->pml_pg = NULL;
7960         }
7961 }
7962
7963 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7964 {
7965         struct vcpu_vmx *vmx = to_vmx(vcpu);
7966         u64 *pml_buf;
7967         u16 pml_idx;
7968
7969         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7970
7971         /* Do nothing if PML buffer is empty */
7972         if (pml_idx == (PML_ENTITY_NUM - 1))
7973                 return;
7974
7975         /* PML index always points to next available PML buffer entity */
7976         if (pml_idx >= PML_ENTITY_NUM)
7977                 pml_idx = 0;
7978         else
7979                 pml_idx++;
7980
7981         pml_buf = page_address(vmx->pml_pg);
7982         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7983                 u64 gpa;
7984
7985                 gpa = pml_buf[pml_idx];
7986                 WARN_ON(gpa & (PAGE_SIZE - 1));
7987                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7988         }
7989
7990         /* reset PML index */
7991         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7992 }
7993
7994 /*
7995  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7996  * Called before reporting dirty_bitmap to userspace.
7997  */
7998 static void kvm_flush_pml_buffers(struct kvm *kvm)
7999 {
8000         int i;
8001         struct kvm_vcpu *vcpu;
8002         /*
8003          * We only need to kick vcpu out of guest mode here, as PML buffer
8004          * is flushed at beginning of all VMEXITs, and it's obvious that only
8005          * vcpus running in guest are possible to have unflushed GPAs in PML
8006          * buffer.
8007          */
8008         kvm_for_each_vcpu(i, vcpu, kvm)
8009                 kvm_vcpu_kick(vcpu);
8010 }
8011
8012 static void vmx_dump_sel(char *name, uint32_t sel)
8013 {
8014         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8015                name, vmcs_read32(sel),
8016                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8017                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8018                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8019 }
8020
8021 static void vmx_dump_dtsel(char *name, uint32_t limit)
8022 {
8023         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8024                name, vmcs_read32(limit),
8025                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8026 }
8027
8028 static void dump_vmcs(void)
8029 {
8030         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8031         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8032         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8033         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8034         u32 secondary_exec_control = 0;
8035         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8036         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8037         int i, n;
8038
8039         if (cpu_has_secondary_exec_ctrls())
8040                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8041
8042         pr_err("*** Guest State ***\n");
8043         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8044                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8045                vmcs_readl(CR0_GUEST_HOST_MASK));
8046         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8047                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8048         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8049         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8050             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8051         {
8052                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8053                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8054                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8055                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8056         }
8057         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8058                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8059         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8060                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8061         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8062                vmcs_readl(GUEST_SYSENTER_ESP),
8063                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8064         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8065         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8066         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8067         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8068         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8069         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8070         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8071         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8072         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8073         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8074         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8075             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8076                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8077                        efer, vmcs_read64(GUEST_IA32_PAT));
8078         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8079                vmcs_read64(GUEST_IA32_DEBUGCTL),
8080                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8081         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8082                 pr_err("PerfGlobCtl = 0x%016llx\n",
8083                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8084         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8085                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8086         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8087                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8088                vmcs_read32(GUEST_ACTIVITY_STATE));
8089         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8090                 pr_err("InterruptStatus = %04x\n",
8091                        vmcs_read16(GUEST_INTR_STATUS));
8092
8093         pr_err("*** Host State ***\n");
8094         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8095                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8096         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8097                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8098                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8099                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8100                vmcs_read16(HOST_TR_SELECTOR));
8101         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8102                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8103                vmcs_readl(HOST_TR_BASE));
8104         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8105                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8106         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8107                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8108                vmcs_readl(HOST_CR4));
8109         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8110                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8111                vmcs_read32(HOST_IA32_SYSENTER_CS),
8112                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8113         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8114                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8115                        vmcs_read64(HOST_IA32_EFER),
8116                        vmcs_read64(HOST_IA32_PAT));
8117         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8118                 pr_err("PerfGlobCtl = 0x%016llx\n",
8119                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8120
8121         pr_err("*** Control State ***\n");
8122         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8123                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8124         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8125         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8126                vmcs_read32(EXCEPTION_BITMAP),
8127                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8128                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8129         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8130                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8131                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8132                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8133         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8134                vmcs_read32(VM_EXIT_INTR_INFO),
8135                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8136                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8137         pr_err("        reason=%08x qualification=%016lx\n",
8138                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8139         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8140                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8141                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8142         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8143         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8144                 pr_err("TSC Multiplier = 0x%016llx\n",
8145                        vmcs_read64(TSC_MULTIPLIER));
8146         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8147                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8148         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8149                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8150         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8151                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8152         n = vmcs_read32(CR3_TARGET_COUNT);
8153         for (i = 0; i + 1 < n; i += 4)
8154                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8155                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8156                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8157         if (i < n)
8158                 pr_err("CR3 target%u=%016lx\n",
8159                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8160         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8161                 pr_err("PLE Gap=%08x Window=%08x\n",
8162                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8163         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8164                 pr_err("Virtual processor ID = 0x%04x\n",
8165                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8166 }
8167
8168 /*
8169  * The guest has exited.  See if we can fix it or if we need userspace
8170  * assistance.
8171  */
8172 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8173 {
8174         struct vcpu_vmx *vmx = to_vmx(vcpu);
8175         u32 exit_reason = vmx->exit_reason;
8176         u32 vectoring_info = vmx->idt_vectoring_info;
8177
8178         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8179
8180         /*
8181          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8182          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8183          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8184          * mode as if vcpus is in root mode, the PML buffer must has been
8185          * flushed already.
8186          */
8187         if (enable_pml)
8188                 vmx_flush_pml_buffer(vcpu);
8189
8190         /* If guest state is invalid, start emulating */
8191         if (vmx->emulation_required)
8192                 return handle_invalid_guest_state(vcpu);
8193
8194         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8195                 nested_vmx_vmexit(vcpu, exit_reason,
8196                                   vmcs_read32(VM_EXIT_INTR_INFO),
8197                                   vmcs_readl(EXIT_QUALIFICATION));
8198                 return 1;
8199         }
8200
8201         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8202                 dump_vmcs();
8203                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8204                 vcpu->run->fail_entry.hardware_entry_failure_reason
8205                         = exit_reason;
8206                 return 0;
8207         }
8208
8209         if (unlikely(vmx->fail)) {
8210                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8211                 vcpu->run->fail_entry.hardware_entry_failure_reason
8212                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8213                 return 0;
8214         }
8215
8216         /*
8217          * Note:
8218          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8219          * delivery event since it indicates guest is accessing MMIO.
8220          * The vm-exit can be triggered again after return to guest that
8221          * will cause infinite loop.
8222          */
8223         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8224                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8225                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8226                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8227                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8228                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8229                 vcpu->run->internal.ndata = 2;
8230                 vcpu->run->internal.data[0] = vectoring_info;
8231                 vcpu->run->internal.data[1] = exit_reason;
8232                 return 0;
8233         }
8234
8235         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8236             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8237                                         get_vmcs12(vcpu))))) {
8238                 if (vmx_interrupt_allowed(vcpu)) {
8239                         vmx->soft_vnmi_blocked = 0;
8240                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8241                            vcpu->arch.nmi_pending) {
8242                         /*
8243                          * This CPU don't support us in finding the end of an
8244                          * NMI-blocked window if the guest runs with IRQs
8245                          * disabled. So we pull the trigger after 1 s of
8246                          * futile waiting, but inform the user about this.
8247                          */
8248                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8249                                "state on VCPU %d after 1 s timeout\n",
8250                                __func__, vcpu->vcpu_id);
8251                         vmx->soft_vnmi_blocked = 0;
8252                 }
8253         }
8254
8255         if (exit_reason < kvm_vmx_max_exit_handlers
8256             && kvm_vmx_exit_handlers[exit_reason])
8257                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8258         else {
8259                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8260                 kvm_queue_exception(vcpu, UD_VECTOR);
8261                 return 1;
8262         }
8263 }
8264
8265 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8266 {
8267         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8268
8269         if (is_guest_mode(vcpu) &&
8270                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8271                 return;
8272
8273         if (irr == -1 || tpr < irr) {
8274                 vmcs_write32(TPR_THRESHOLD, 0);
8275                 return;
8276         }
8277
8278         vmcs_write32(TPR_THRESHOLD, irr);
8279 }
8280
8281 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8282 {
8283         u32 sec_exec_control;
8284
8285         /*
8286          * There is not point to enable virtualize x2apic without enable
8287          * apicv
8288          */
8289         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8290                                 !kvm_vcpu_apicv_active(vcpu))
8291                 return;
8292
8293         if (!cpu_need_tpr_shadow(vcpu))
8294                 return;
8295
8296         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8297
8298         if (set) {
8299                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8300                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8301         } else {
8302                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8303                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8304         }
8305         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8306
8307         vmx_set_msr_bitmap(vcpu);
8308 }
8309
8310 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8311 {
8312         struct vcpu_vmx *vmx = to_vmx(vcpu);
8313
8314         /*
8315          * Currently we do not handle the nested case where L2 has an
8316          * APIC access page of its own; that page is still pinned.
8317          * Hence, we skip the case where the VCPU is in guest mode _and_
8318          * L1 prepared an APIC access page for L2.
8319          *
8320          * For the case where L1 and L2 share the same APIC access page
8321          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8322          * in the vmcs12), this function will only update either the vmcs01
8323          * or the vmcs02.  If the former, the vmcs02 will be updated by
8324          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8325          * the next L2->L1 exit.
8326          */
8327         if (!is_guest_mode(vcpu) ||
8328             !nested_cpu_has2(vmx->nested.current_vmcs12,
8329                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8330                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8331 }
8332
8333 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8334 {
8335         u16 status;
8336         u8 old;
8337
8338         if (max_isr == -1)
8339                 max_isr = 0;
8340
8341         status = vmcs_read16(GUEST_INTR_STATUS);
8342         old = status >> 8;
8343         if (max_isr != old) {
8344                 status &= 0xff;
8345                 status |= max_isr << 8;
8346                 vmcs_write16(GUEST_INTR_STATUS, status);
8347         }
8348 }
8349
8350 static void vmx_set_rvi(int vector)
8351 {
8352         u16 status;
8353         u8 old;
8354
8355         if (vector == -1)
8356                 vector = 0;
8357
8358         status = vmcs_read16(GUEST_INTR_STATUS);
8359         old = (u8)status & 0xff;
8360         if ((u8)vector != old) {
8361                 status &= ~0xff;
8362                 status |= (u8)vector;
8363                 vmcs_write16(GUEST_INTR_STATUS, status);
8364         }
8365 }
8366
8367 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8368 {
8369         if (!is_guest_mode(vcpu)) {
8370                 vmx_set_rvi(max_irr);
8371                 return;
8372         }
8373
8374         if (max_irr == -1)
8375                 return;
8376
8377         /*
8378          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8379          * handles it.
8380          */
8381         if (nested_exit_on_intr(vcpu))
8382                 return;
8383
8384         /*
8385          * Else, fall back to pre-APICv interrupt injection since L2
8386          * is run without virtual interrupt delivery.
8387          */
8388         if (!kvm_event_needs_reinjection(vcpu) &&
8389             vmx_interrupt_allowed(vcpu)) {
8390                 kvm_queue_interrupt(vcpu, max_irr, false);
8391                 vmx_inject_irq(vcpu);
8392         }
8393 }
8394
8395 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8396 {
8397         if (!kvm_vcpu_apicv_active(vcpu))
8398                 return;
8399
8400         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8401         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8402         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8403         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8404 }
8405
8406 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8407 {
8408         u32 exit_intr_info;
8409
8410         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8411               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8412                 return;
8413
8414         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8415         exit_intr_info = vmx->exit_intr_info;
8416
8417         /* Handle machine checks before interrupts are enabled */
8418         if (is_machine_check(exit_intr_info))
8419                 kvm_machine_check();
8420
8421         /* We need to handle NMIs before interrupts are enabled */
8422         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8423             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8424                 kvm_before_handle_nmi(&vmx->vcpu);
8425                 asm("int $2");
8426                 kvm_after_handle_nmi(&vmx->vcpu);
8427         }
8428 }
8429
8430 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8431 {
8432         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8433         register void *__sp asm(_ASM_SP);
8434
8435         /*
8436          * If external interrupt exists, IF bit is set in rflags/eflags on the
8437          * interrupt stack frame, and interrupt will be enabled on a return
8438          * from interrupt handler.
8439          */
8440         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8441                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8442                 unsigned int vector;
8443                 unsigned long entry;
8444                 gate_desc *desc;
8445                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8446 #ifdef CONFIG_X86_64
8447                 unsigned long tmp;
8448 #endif
8449
8450                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8451                 desc = (gate_desc *)vmx->host_idt_base + vector;
8452                 entry = gate_offset(*desc);
8453                 asm volatile(
8454 #ifdef CONFIG_X86_64
8455                         "mov %%" _ASM_SP ", %[sp]\n\t"
8456                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8457                         "push $%c[ss]\n\t"
8458                         "push %[sp]\n\t"
8459 #endif
8460                         "pushf\n\t"
8461                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8462                         __ASM_SIZE(push) " $%c[cs]\n\t"
8463                         "call *%[entry]\n\t"
8464                         :
8465 #ifdef CONFIG_X86_64
8466                         [sp]"=&r"(tmp),
8467 #endif
8468                         "+r"(__sp)
8469                         :
8470                         [entry]"r"(entry),
8471                         [ss]"i"(__KERNEL_DS),
8472                         [cs]"i"(__KERNEL_CS)
8473                         );
8474         } else
8475                 local_irq_enable();
8476 }
8477
8478 static bool vmx_has_high_real_mode_segbase(void)
8479 {
8480         return enable_unrestricted_guest || emulate_invalid_guest_state;
8481 }
8482
8483 static bool vmx_mpx_supported(void)
8484 {
8485         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8486                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8487 }
8488
8489 static bool vmx_xsaves_supported(void)
8490 {
8491         return vmcs_config.cpu_based_2nd_exec_ctrl &
8492                 SECONDARY_EXEC_XSAVES;
8493 }
8494
8495 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8496 {
8497         u32 exit_intr_info;
8498         bool unblock_nmi;
8499         u8 vector;
8500         bool idtv_info_valid;
8501
8502         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8503
8504         if (cpu_has_virtual_nmis()) {
8505                 if (vmx->nmi_known_unmasked)
8506                         return;
8507                 /*
8508                  * Can't use vmx->exit_intr_info since we're not sure what
8509                  * the exit reason is.
8510                  */
8511                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8512                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8513                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8514                 /*
8515                  * SDM 3: 27.7.1.2 (September 2008)
8516                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8517                  * a guest IRET fault.
8518                  * SDM 3: 23.2.2 (September 2008)
8519                  * Bit 12 is undefined in any of the following cases:
8520                  *  If the VM exit sets the valid bit in the IDT-vectoring
8521                  *   information field.
8522                  *  If the VM exit is due to a double fault.
8523                  */
8524                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8525                     vector != DF_VECTOR && !idtv_info_valid)
8526                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8527                                       GUEST_INTR_STATE_NMI);
8528                 else
8529                         vmx->nmi_known_unmasked =
8530                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8531                                   & GUEST_INTR_STATE_NMI);
8532         } else if (unlikely(vmx->soft_vnmi_blocked))
8533                 vmx->vnmi_blocked_time +=
8534                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8535 }
8536
8537 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8538                                       u32 idt_vectoring_info,
8539                                       int instr_len_field,
8540                                       int error_code_field)
8541 {
8542         u8 vector;
8543         int type;
8544         bool idtv_info_valid;
8545
8546         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8547
8548         vcpu->arch.nmi_injected = false;
8549         kvm_clear_exception_queue(vcpu);
8550         kvm_clear_interrupt_queue(vcpu);
8551
8552         if (!idtv_info_valid)
8553                 return;
8554
8555         kvm_make_request(KVM_REQ_EVENT, vcpu);
8556
8557         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8558         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8559
8560         switch (type) {
8561         case INTR_TYPE_NMI_INTR:
8562                 vcpu->arch.nmi_injected = true;
8563                 /*
8564                  * SDM 3: 27.7.1.2 (September 2008)
8565                  * Clear bit "block by NMI" before VM entry if a NMI
8566                  * delivery faulted.
8567                  */
8568                 vmx_set_nmi_mask(vcpu, false);
8569                 break;
8570         case INTR_TYPE_SOFT_EXCEPTION:
8571                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8572                 /* fall through */
8573         case INTR_TYPE_HARD_EXCEPTION:
8574                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8575                         u32 err = vmcs_read32(error_code_field);
8576                         kvm_requeue_exception_e(vcpu, vector, err);
8577                 } else
8578                         kvm_requeue_exception(vcpu, vector);
8579                 break;
8580         case INTR_TYPE_SOFT_INTR:
8581                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8582                 /* fall through */
8583         case INTR_TYPE_EXT_INTR:
8584                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8585                 break;
8586         default:
8587                 break;
8588         }
8589 }
8590
8591 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8592 {
8593         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8594                                   VM_EXIT_INSTRUCTION_LEN,
8595                                   IDT_VECTORING_ERROR_CODE);
8596 }
8597
8598 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8599 {
8600         __vmx_complete_interrupts(vcpu,
8601                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8602                                   VM_ENTRY_INSTRUCTION_LEN,
8603                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8604
8605         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8606 }
8607
8608 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8609 {
8610         int i, nr_msrs;
8611         struct perf_guest_switch_msr *msrs;
8612
8613         msrs = perf_guest_get_msrs(&nr_msrs);
8614
8615         if (!msrs)
8616                 return;
8617
8618         for (i = 0; i < nr_msrs; i++)
8619                 if (msrs[i].host == msrs[i].guest)
8620                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8621                 else
8622                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8623                                         msrs[i].host);
8624 }
8625
8626 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8627 {
8628         struct vcpu_vmx *vmx = to_vmx(vcpu);
8629         unsigned long debugctlmsr, cr4;
8630
8631         /* Record the guest's net vcpu time for enforced NMI injections. */
8632         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8633                 vmx->entry_time = ktime_get();
8634
8635         /* Don't enter VMX if guest state is invalid, let the exit handler
8636            start emulation until we arrive back to a valid state */
8637         if (vmx->emulation_required)
8638                 return;
8639
8640         if (vmx->ple_window_dirty) {
8641                 vmx->ple_window_dirty = false;
8642                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8643         }
8644
8645         if (vmx->nested.sync_shadow_vmcs) {
8646                 copy_vmcs12_to_shadow(vmx);
8647                 vmx->nested.sync_shadow_vmcs = false;
8648         }
8649
8650         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8651                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8652         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8653                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8654
8655         cr4 = cr4_read_shadow();
8656         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8657                 vmcs_writel(HOST_CR4, cr4);
8658                 vmx->host_state.vmcs_host_cr4 = cr4;
8659         }
8660
8661         /* When single-stepping over STI and MOV SS, we must clear the
8662          * corresponding interruptibility bits in the guest state. Otherwise
8663          * vmentry fails as it then expects bit 14 (BS) in pending debug
8664          * exceptions being set, but that's not correct for the guest debugging
8665          * case. */
8666         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8667                 vmx_set_interrupt_shadow(vcpu, 0);
8668
8669         if (vmx->guest_pkru_valid)
8670                 __write_pkru(vmx->guest_pkru);
8671
8672         atomic_switch_perf_msrs(vmx);
8673         debugctlmsr = get_debugctlmsr();
8674
8675         vmx->__launched = vmx->loaded_vmcs->launched;
8676         asm(
8677                 /* Store host registers */
8678                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8679                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8680                 "push %%" _ASM_CX " \n\t"
8681                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8682                 "je 1f \n\t"
8683                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8684                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8685                 "1: \n\t"
8686                 /* Reload cr2 if changed */
8687                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8688                 "mov %%cr2, %%" _ASM_DX " \n\t"
8689                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8690                 "je 2f \n\t"
8691                 "mov %%" _ASM_AX", %%cr2 \n\t"
8692                 "2: \n\t"
8693                 /* Check if vmlaunch of vmresume is needed */
8694                 "cmpl $0, %c[launched](%0) \n\t"
8695                 /* Load guest registers.  Don't clobber flags. */
8696                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8697                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8698                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8699                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8700                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8701                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8702 #ifdef CONFIG_X86_64
8703                 "mov %c[r8](%0),  %%r8  \n\t"
8704                 "mov %c[r9](%0),  %%r9  \n\t"
8705                 "mov %c[r10](%0), %%r10 \n\t"
8706                 "mov %c[r11](%0), %%r11 \n\t"
8707                 "mov %c[r12](%0), %%r12 \n\t"
8708                 "mov %c[r13](%0), %%r13 \n\t"
8709                 "mov %c[r14](%0), %%r14 \n\t"
8710                 "mov %c[r15](%0), %%r15 \n\t"
8711 #endif
8712                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8713
8714                 /* Enter guest mode */
8715                 "jne 1f \n\t"
8716                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8717                 "jmp 2f \n\t"
8718                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8719                 "2: "
8720                 /* Save guest registers, load host registers, keep flags */
8721                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8722                 "pop %0 \n\t"
8723                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8724                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8725                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8726                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8727                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8728                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8729                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8730 #ifdef CONFIG_X86_64
8731                 "mov %%r8,  %c[r8](%0) \n\t"
8732                 "mov %%r9,  %c[r9](%0) \n\t"
8733                 "mov %%r10, %c[r10](%0) \n\t"
8734                 "mov %%r11, %c[r11](%0) \n\t"
8735                 "mov %%r12, %c[r12](%0) \n\t"
8736                 "mov %%r13, %c[r13](%0) \n\t"
8737                 "mov %%r14, %c[r14](%0) \n\t"
8738                 "mov %%r15, %c[r15](%0) \n\t"
8739 #endif
8740                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8741                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8742
8743                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8744                 "setbe %c[fail](%0) \n\t"
8745                 ".pushsection .rodata \n\t"
8746                 ".global vmx_return \n\t"
8747                 "vmx_return: " _ASM_PTR " 2b \n\t"
8748                 ".popsection"
8749               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8750                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8751                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8752                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8753                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8754                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8755                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8756                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8757                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8758                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8759                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8760 #ifdef CONFIG_X86_64
8761                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8762                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8763                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8764                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8765                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8766                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8767                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8768                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8769 #endif
8770                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8771                 [wordsize]"i"(sizeof(ulong))
8772               : "cc", "memory"
8773 #ifdef CONFIG_X86_64
8774                 , "rax", "rbx", "rdi", "rsi"
8775                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8776 #else
8777                 , "eax", "ebx", "edi", "esi"
8778 #endif
8779               );
8780
8781         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8782         if (debugctlmsr)
8783                 update_debugctlmsr(debugctlmsr);
8784
8785 #ifndef CONFIG_X86_64
8786         /*
8787          * The sysexit path does not restore ds/es, so we must set them to
8788          * a reasonable value ourselves.
8789          *
8790          * We can't defer this to vmx_load_host_state() since that function
8791          * may be executed in interrupt context, which saves and restore segments
8792          * around it, nullifying its effect.
8793          */
8794         loadsegment(ds, __USER_DS);
8795         loadsegment(es, __USER_DS);
8796 #endif
8797
8798         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8799                                   | (1 << VCPU_EXREG_RFLAGS)
8800                                   | (1 << VCPU_EXREG_PDPTR)
8801                                   | (1 << VCPU_EXREG_SEGMENTS)
8802                                   | (1 << VCPU_EXREG_CR3));
8803         vcpu->arch.regs_dirty = 0;
8804
8805         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8806
8807         vmx->loaded_vmcs->launched = 1;
8808
8809         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8810
8811         /*
8812          * eager fpu is enabled if PKEY is supported and CR4 is switched
8813          * back on host, so it is safe to read guest PKRU from current
8814          * XSAVE.
8815          */
8816         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8817                 vmx->guest_pkru = __read_pkru();
8818                 if (vmx->guest_pkru != vmx->host_pkru) {
8819                         vmx->guest_pkru_valid = true;
8820                         __write_pkru(vmx->host_pkru);
8821                 } else
8822                         vmx->guest_pkru_valid = false;
8823         }
8824
8825         /*
8826          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8827          * we did not inject a still-pending event to L1 now because of
8828          * nested_run_pending, we need to re-enable this bit.
8829          */
8830         if (vmx->nested.nested_run_pending)
8831                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8832
8833         vmx->nested.nested_run_pending = 0;
8834
8835         vmx_complete_atomic_exit(vmx);
8836         vmx_recover_nmi_blocking(vmx);
8837         vmx_complete_interrupts(vmx);
8838 }
8839
8840 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8841 {
8842         struct vcpu_vmx *vmx = to_vmx(vcpu);
8843         int cpu;
8844
8845         if (vmx->loaded_vmcs == &vmx->vmcs01)
8846                 return;
8847
8848         cpu = get_cpu();
8849         vmx->loaded_vmcs = &vmx->vmcs01;
8850         vmx_vcpu_put(vcpu);
8851         vmx_vcpu_load(vcpu, cpu);
8852         vcpu->cpu = cpu;
8853         put_cpu();
8854 }
8855
8856 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8857 {
8858         struct vcpu_vmx *vmx = to_vmx(vcpu);
8859
8860         if (enable_pml)
8861                 vmx_destroy_pml_buffer(vmx);
8862         free_vpid(vmx->vpid);
8863         leave_guest_mode(vcpu);
8864         vmx_load_vmcs01(vcpu);
8865         free_nested(vmx);
8866         free_loaded_vmcs(vmx->loaded_vmcs);
8867         kfree(vmx->guest_msrs);
8868         kvm_vcpu_uninit(vcpu);
8869         kmem_cache_free(kvm_vcpu_cache, vmx);
8870 }
8871
8872 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8873 {
8874         int err;
8875         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8876         int cpu;
8877
8878         if (!vmx)
8879                 return ERR_PTR(-ENOMEM);
8880
8881         vmx->vpid = allocate_vpid();
8882
8883         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8884         if (err)
8885                 goto free_vcpu;
8886
8887         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8888         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8889                      > PAGE_SIZE);
8890
8891         err = -ENOMEM;
8892         if (!vmx->guest_msrs) {
8893                 goto uninit_vcpu;
8894         }
8895
8896         vmx->loaded_vmcs = &vmx->vmcs01;
8897         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8898         if (!vmx->loaded_vmcs->vmcs)
8899                 goto free_msrs;
8900         if (!vmm_exclusive)
8901                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8902         loaded_vmcs_init(vmx->loaded_vmcs);
8903         if (!vmm_exclusive)
8904                 kvm_cpu_vmxoff();
8905
8906         cpu = get_cpu();
8907         vmx_vcpu_load(&vmx->vcpu, cpu);
8908         vmx->vcpu.cpu = cpu;
8909         err = vmx_vcpu_setup(vmx);
8910         vmx_vcpu_put(&vmx->vcpu);
8911         put_cpu();
8912         if (err)
8913                 goto free_vmcs;
8914         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8915                 err = alloc_apic_access_page(kvm);
8916                 if (err)
8917                         goto free_vmcs;
8918         }
8919
8920         if (enable_ept) {
8921                 if (!kvm->arch.ept_identity_map_addr)
8922                         kvm->arch.ept_identity_map_addr =
8923                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8924                 err = init_rmode_identity_map(kvm);
8925                 if (err)
8926                         goto free_vmcs;
8927         }
8928
8929         if (nested) {
8930                 nested_vmx_setup_ctls_msrs(vmx);
8931                 vmx->nested.vpid02 = allocate_vpid();
8932         }
8933
8934         vmx->nested.posted_intr_nv = -1;
8935         vmx->nested.current_vmptr = -1ull;
8936         vmx->nested.current_vmcs12 = NULL;
8937
8938         /*
8939          * If PML is turned on, failure on enabling PML just results in failure
8940          * of creating the vcpu, therefore we can simplify PML logic (by
8941          * avoiding dealing with cases, such as enabling PML partially on vcpus
8942          * for the guest, etc.
8943          */
8944         if (enable_pml) {
8945                 err = vmx_create_pml_buffer(vmx);
8946                 if (err)
8947                         goto free_vmcs;
8948         }
8949
8950         return &vmx->vcpu;
8951
8952 free_vmcs:
8953         free_vpid(vmx->nested.vpid02);
8954         free_loaded_vmcs(vmx->loaded_vmcs);
8955 free_msrs:
8956         kfree(vmx->guest_msrs);
8957 uninit_vcpu:
8958         kvm_vcpu_uninit(&vmx->vcpu);
8959 free_vcpu:
8960         free_vpid(vmx->vpid);
8961         kmem_cache_free(kvm_vcpu_cache, vmx);
8962         return ERR_PTR(err);
8963 }
8964
8965 static void __init vmx_check_processor_compat(void *rtn)
8966 {
8967         struct vmcs_config vmcs_conf;
8968
8969         *(int *)rtn = 0;
8970         if (setup_vmcs_config(&vmcs_conf) < 0)
8971                 *(int *)rtn = -EIO;
8972         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8973                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8974                                 smp_processor_id());
8975                 *(int *)rtn = -EIO;
8976         }
8977 }
8978
8979 static int get_ept_level(void)
8980 {
8981         return VMX_EPT_DEFAULT_GAW + 1;
8982 }
8983
8984 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8985 {
8986         u8 cache;
8987         u64 ipat = 0;
8988
8989         /* For VT-d and EPT combination
8990          * 1. MMIO: always map as UC
8991          * 2. EPT with VT-d:
8992          *   a. VT-d without snooping control feature: can't guarantee the
8993          *      result, try to trust guest.
8994          *   b. VT-d with snooping control feature: snooping control feature of
8995          *      VT-d engine can guarantee the cache correctness. Just set it
8996          *      to WB to keep consistent with host. So the same as item 3.
8997          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8998          *    consistent with host MTRR
8999          */
9000         if (is_mmio) {
9001                 cache = MTRR_TYPE_UNCACHABLE;
9002                 goto exit;
9003         }
9004
9005         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9006                 ipat = VMX_EPT_IPAT_BIT;
9007                 cache = MTRR_TYPE_WRBACK;
9008                 goto exit;
9009         }
9010
9011         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9012                 ipat = VMX_EPT_IPAT_BIT;
9013                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9014                         cache = MTRR_TYPE_WRBACK;
9015                 else
9016                         cache = MTRR_TYPE_UNCACHABLE;
9017                 goto exit;
9018         }
9019
9020         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9021
9022 exit:
9023         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9024 }
9025
9026 static int vmx_get_lpage_level(void)
9027 {
9028         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9029                 return PT_DIRECTORY_LEVEL;
9030         else
9031                 /* For shadow and EPT supported 1GB page */
9032                 return PT_PDPE_LEVEL;
9033 }
9034
9035 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9036 {
9037         /*
9038          * These bits in the secondary execution controls field
9039          * are dynamic, the others are mostly based on the hypervisor
9040          * architecture and the guest's CPUID.  Do not touch the
9041          * dynamic bits.
9042          */
9043         u32 mask =
9044                 SECONDARY_EXEC_SHADOW_VMCS |
9045                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9046                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9047
9048         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9049
9050         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9051                      (new_ctl & ~mask) | (cur_ctl & mask));
9052 }
9053
9054 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9055 {
9056         struct kvm_cpuid_entry2 *best;
9057         struct vcpu_vmx *vmx = to_vmx(vcpu);
9058         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9059
9060         if (vmx_rdtscp_supported()) {
9061                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9062                 if (!rdtscp_enabled)
9063                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9064
9065                 if (nested) {
9066                         if (rdtscp_enabled)
9067                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9068                                         SECONDARY_EXEC_RDTSCP;
9069                         else
9070                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9071                                         ~SECONDARY_EXEC_RDTSCP;
9072                 }
9073         }
9074
9075         /* Exposing INVPCID only when PCID is exposed */
9076         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9077         if (vmx_invpcid_supported() &&
9078             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9079             !guest_cpuid_has_pcid(vcpu))) {
9080                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9081
9082                 if (best)
9083                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9084         }
9085
9086         if (cpu_has_secondary_exec_ctrls())
9087                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9088
9089         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9090                 if (guest_cpuid_has_pcommit(vcpu))
9091                         vmx->nested.nested_vmx_secondary_ctls_high |=
9092                                 SECONDARY_EXEC_PCOMMIT;
9093                 else
9094                         vmx->nested.nested_vmx_secondary_ctls_high &=
9095                                 ~SECONDARY_EXEC_PCOMMIT;
9096         }
9097 }
9098
9099 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9100 {
9101         if (func == 1 && nested)
9102                 entry->ecx |= bit(X86_FEATURE_VMX);
9103 }
9104
9105 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9106                 struct x86_exception *fault)
9107 {
9108         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9109         u32 exit_reason;
9110
9111         if (fault->error_code & PFERR_RSVD_MASK)
9112                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9113         else
9114                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9115         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9116         vmcs12->guest_physical_address = fault->address;
9117 }
9118
9119 /* Callbacks for nested_ept_init_mmu_context: */
9120
9121 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9122 {
9123         /* return the page table to be shadowed - in our case, EPT12 */
9124         return get_vmcs12(vcpu)->ept_pointer;
9125 }
9126
9127 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9128 {
9129         WARN_ON(mmu_is_nested(vcpu));
9130         kvm_init_shadow_ept_mmu(vcpu,
9131                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9132                         VMX_EPT_EXECUTE_ONLY_BIT);
9133         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9134         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9135         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9136
9137         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9138 }
9139
9140 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9141 {
9142         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9143 }
9144
9145 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9146                                             u16 error_code)
9147 {
9148         bool inequality, bit;
9149
9150         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9151         inequality =
9152                 (error_code & vmcs12->page_fault_error_code_mask) !=
9153                  vmcs12->page_fault_error_code_match;
9154         return inequality ^ bit;
9155 }
9156
9157 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9158                 struct x86_exception *fault)
9159 {
9160         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9161
9162         WARN_ON(!is_guest_mode(vcpu));
9163
9164         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9165                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9166                                   vmcs_read32(VM_EXIT_INTR_INFO),
9167                                   vmcs_readl(EXIT_QUALIFICATION));
9168         else
9169                 kvm_inject_page_fault(vcpu, fault);
9170 }
9171
9172 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9173                                         struct vmcs12 *vmcs12)
9174 {
9175         struct vcpu_vmx *vmx = to_vmx(vcpu);
9176         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9177
9178         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9179                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9180                     vmcs12->apic_access_addr >> maxphyaddr)
9181                         return false;
9182
9183                 /*
9184                  * Translate L1 physical address to host physical
9185                  * address for vmcs02. Keep the page pinned, so this
9186                  * physical address remains valid. We keep a reference
9187                  * to it so we can release it later.
9188                  */
9189                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9190                         nested_release_page(vmx->nested.apic_access_page);
9191                 vmx->nested.apic_access_page =
9192                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9193         }
9194
9195         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9196                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9197                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9198                         return false;
9199
9200                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9201                         nested_release_page(vmx->nested.virtual_apic_page);
9202                 vmx->nested.virtual_apic_page =
9203                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9204
9205                 /*
9206                  * Failing the vm entry is _not_ what the processor does
9207                  * but it's basically the only possibility we have.
9208                  * We could still enter the guest if CR8 load exits are
9209                  * enabled, CR8 store exits are enabled, and virtualize APIC
9210                  * access is disabled; in this case the processor would never
9211                  * use the TPR shadow and we could simply clear the bit from
9212                  * the execution control.  But such a configuration is useless,
9213                  * so let's keep the code simple.
9214                  */
9215                 if (!vmx->nested.virtual_apic_page)
9216                         return false;
9217         }
9218
9219         if (nested_cpu_has_posted_intr(vmcs12)) {
9220                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9221                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9222                         return false;
9223
9224                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9225                         kunmap(vmx->nested.pi_desc_page);
9226                         nested_release_page(vmx->nested.pi_desc_page);
9227                 }
9228                 vmx->nested.pi_desc_page =
9229                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9230                 if (!vmx->nested.pi_desc_page)
9231                         return false;
9232
9233                 vmx->nested.pi_desc =
9234                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9235                 if (!vmx->nested.pi_desc) {
9236                         nested_release_page_clean(vmx->nested.pi_desc_page);
9237                         return false;
9238                 }
9239                 vmx->nested.pi_desc =
9240                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9241                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9242                         (PAGE_SIZE - 1)));
9243         }
9244
9245         return true;
9246 }
9247
9248 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9249 {
9250         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9251         struct vcpu_vmx *vmx = to_vmx(vcpu);
9252
9253         if (vcpu->arch.virtual_tsc_khz == 0)
9254                 return;
9255
9256         /* Make sure short timeouts reliably trigger an immediate vmexit.
9257          * hrtimer_start does not guarantee this. */
9258         if (preemption_timeout <= 1) {
9259                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9260                 return;
9261         }
9262
9263         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9264         preemption_timeout *= 1000000;
9265         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9266         hrtimer_start(&vmx->nested.preemption_timer,
9267                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9268 }
9269
9270 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9271                                                 struct vmcs12 *vmcs12)
9272 {
9273         int maxphyaddr;
9274         u64 addr;
9275
9276         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9277                 return 0;
9278
9279         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9280                 WARN_ON(1);
9281                 return -EINVAL;
9282         }
9283         maxphyaddr = cpuid_maxphyaddr(vcpu);
9284
9285         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9286            ((addr + PAGE_SIZE) >> maxphyaddr))
9287                 return -EINVAL;
9288
9289         return 0;
9290 }
9291
9292 /*
9293  * Merge L0's and L1's MSR bitmap, return false to indicate that
9294  * we do not use the hardware.
9295  */
9296 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9297                                                struct vmcs12 *vmcs12)
9298 {
9299         int msr;
9300         struct page *page;
9301         unsigned long *msr_bitmap;
9302
9303         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9304                 return false;
9305
9306         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9307         if (!page) {
9308                 WARN_ON(1);
9309                 return false;
9310         }
9311         msr_bitmap = (unsigned long *)kmap(page);
9312         if (!msr_bitmap) {
9313                 nested_release_page_clean(page);
9314                 WARN_ON(1);
9315                 return false;
9316         }
9317
9318         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9319                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9320                         for (msr = 0x800; msr <= 0x8ff; msr++)
9321                                 nested_vmx_disable_intercept_for_msr(
9322                                         msr_bitmap,
9323                                         vmx_msr_bitmap_nested,
9324                                         msr, MSR_TYPE_R);
9325                 /* TPR is allowed */
9326                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9327                                 vmx_msr_bitmap_nested,
9328                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9329                                 MSR_TYPE_R | MSR_TYPE_W);
9330                 if (nested_cpu_has_vid(vmcs12)) {
9331                         /* EOI and self-IPI are allowed */
9332                         nested_vmx_disable_intercept_for_msr(
9333                                 msr_bitmap,
9334                                 vmx_msr_bitmap_nested,
9335                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9336                                 MSR_TYPE_W);
9337                         nested_vmx_disable_intercept_for_msr(
9338                                 msr_bitmap,
9339                                 vmx_msr_bitmap_nested,
9340                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9341                                 MSR_TYPE_W);
9342                 }
9343         } else {
9344                 /*
9345                  * Enable reading intercept of all the x2apic
9346                  * MSRs. We should not rely on vmcs12 to do any
9347                  * optimizations here, it may have been modified
9348                  * by L1.
9349                  */
9350                 for (msr = 0x800; msr <= 0x8ff; msr++)
9351                         __vmx_enable_intercept_for_msr(
9352                                 vmx_msr_bitmap_nested,
9353                                 msr,
9354                                 MSR_TYPE_R);
9355
9356                 __vmx_enable_intercept_for_msr(
9357                                 vmx_msr_bitmap_nested,
9358                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9359                                 MSR_TYPE_W);
9360                 __vmx_enable_intercept_for_msr(
9361                                 vmx_msr_bitmap_nested,
9362                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9363                                 MSR_TYPE_W);
9364                 __vmx_enable_intercept_for_msr(
9365                                 vmx_msr_bitmap_nested,
9366                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9367                                 MSR_TYPE_W);
9368         }
9369         kunmap(page);
9370         nested_release_page_clean(page);
9371
9372         return true;
9373 }
9374
9375 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9376                                            struct vmcs12 *vmcs12)
9377 {
9378         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9379             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9380             !nested_cpu_has_vid(vmcs12) &&
9381             !nested_cpu_has_posted_intr(vmcs12))
9382                 return 0;
9383
9384         /*
9385          * If virtualize x2apic mode is enabled,
9386          * virtualize apic access must be disabled.
9387          */
9388         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9389             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9390                 return -EINVAL;
9391
9392         /*
9393          * If virtual interrupt delivery is enabled,
9394          * we must exit on external interrupts.
9395          */
9396         if (nested_cpu_has_vid(vmcs12) &&
9397            !nested_exit_on_intr(vcpu))
9398                 return -EINVAL;
9399
9400         /*
9401          * bits 15:8 should be zero in posted_intr_nv,
9402          * the descriptor address has been already checked
9403          * in nested_get_vmcs12_pages.
9404          */
9405         if (nested_cpu_has_posted_intr(vmcs12) &&
9406            (!nested_cpu_has_vid(vmcs12) ||
9407             !nested_exit_intr_ack_set(vcpu) ||
9408             vmcs12->posted_intr_nv & 0xff00))
9409                 return -EINVAL;
9410
9411         /* tpr shadow is needed by all apicv features. */
9412         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9413                 return -EINVAL;
9414
9415         return 0;
9416 }
9417
9418 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9419                                        unsigned long count_field,
9420                                        unsigned long addr_field)
9421 {
9422         int maxphyaddr;
9423         u64 count, addr;
9424
9425         if (vmcs12_read_any(vcpu, count_field, &count) ||
9426             vmcs12_read_any(vcpu, addr_field, &addr)) {
9427                 WARN_ON(1);
9428                 return -EINVAL;
9429         }
9430         if (count == 0)
9431                 return 0;
9432         maxphyaddr = cpuid_maxphyaddr(vcpu);
9433         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9434             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9435                 pr_warn_ratelimited(
9436                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9437                         addr_field, maxphyaddr, count, addr);
9438                 return -EINVAL;
9439         }
9440         return 0;
9441 }
9442
9443 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9444                                                 struct vmcs12 *vmcs12)
9445 {
9446         if (vmcs12->vm_exit_msr_load_count == 0 &&
9447             vmcs12->vm_exit_msr_store_count == 0 &&
9448             vmcs12->vm_entry_msr_load_count == 0)
9449                 return 0; /* Fast path */
9450         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9451                                         VM_EXIT_MSR_LOAD_ADDR) ||
9452             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9453                                         VM_EXIT_MSR_STORE_ADDR) ||
9454             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9455                                         VM_ENTRY_MSR_LOAD_ADDR))
9456                 return -EINVAL;
9457         return 0;
9458 }
9459
9460 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9461                                        struct vmx_msr_entry *e)
9462 {
9463         /* x2APIC MSR accesses are not allowed */
9464         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9465                 return -EINVAL;
9466         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9467             e->index == MSR_IA32_UCODE_REV)
9468                 return -EINVAL;
9469         if (e->reserved != 0)
9470                 return -EINVAL;
9471         return 0;
9472 }
9473
9474 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9475                                      struct vmx_msr_entry *e)
9476 {
9477         if (e->index == MSR_FS_BASE ||
9478             e->index == MSR_GS_BASE ||
9479             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9480             nested_vmx_msr_check_common(vcpu, e))
9481                 return -EINVAL;
9482         return 0;
9483 }
9484
9485 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9486                                       struct vmx_msr_entry *e)
9487 {
9488         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9489             nested_vmx_msr_check_common(vcpu, e))
9490                 return -EINVAL;
9491         return 0;
9492 }
9493
9494 /*
9495  * Load guest's/host's msr at nested entry/exit.
9496  * return 0 for success, entry index for failure.
9497  */
9498 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9499 {
9500         u32 i;
9501         struct vmx_msr_entry e;
9502         struct msr_data msr;
9503
9504         msr.host_initiated = false;
9505         for (i = 0; i < count; i++) {
9506                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9507                                         &e, sizeof(e))) {
9508                         pr_warn_ratelimited(
9509                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9510                                 __func__, i, gpa + i * sizeof(e));
9511                         goto fail;
9512                 }
9513                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9514                         pr_warn_ratelimited(
9515                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9516                                 __func__, i, e.index, e.reserved);
9517                         goto fail;
9518                 }
9519                 msr.index = e.index;
9520                 msr.data = e.value;
9521                 if (kvm_set_msr(vcpu, &msr)) {
9522                         pr_warn_ratelimited(
9523                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9524                                 __func__, i, e.index, e.value);
9525                         goto fail;
9526                 }
9527         }
9528         return 0;
9529 fail:
9530         return i + 1;
9531 }
9532
9533 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9534 {
9535         u32 i;
9536         struct vmx_msr_entry e;
9537
9538         for (i = 0; i < count; i++) {
9539                 struct msr_data msr_info;
9540                 if (kvm_vcpu_read_guest(vcpu,
9541                                         gpa + i * sizeof(e),
9542                                         &e, 2 * sizeof(u32))) {
9543                         pr_warn_ratelimited(
9544                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9545                                 __func__, i, gpa + i * sizeof(e));
9546                         return -EINVAL;
9547                 }
9548                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9549                         pr_warn_ratelimited(
9550                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9551                                 __func__, i, e.index, e.reserved);
9552                         return -EINVAL;
9553                 }
9554                 msr_info.host_initiated = false;
9555                 msr_info.index = e.index;
9556                 if (kvm_get_msr(vcpu, &msr_info)) {
9557                         pr_warn_ratelimited(
9558                                 "%s cannot read MSR (%u, 0x%x)\n",
9559                                 __func__, i, e.index);
9560                         return -EINVAL;
9561                 }
9562                 if (kvm_vcpu_write_guest(vcpu,
9563                                          gpa + i * sizeof(e) +
9564                                              offsetof(struct vmx_msr_entry, value),
9565                                          &msr_info.data, sizeof(msr_info.data))) {
9566                         pr_warn_ratelimited(
9567                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9568                                 __func__, i, e.index, msr_info.data);
9569                         return -EINVAL;
9570                 }
9571         }
9572         return 0;
9573 }
9574
9575 /*
9576  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9577  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9578  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9579  * guest in a way that will both be appropriate to L1's requests, and our
9580  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9581  * function also has additional necessary side-effects, like setting various
9582  * vcpu->arch fields.
9583  */
9584 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9585 {
9586         struct vcpu_vmx *vmx = to_vmx(vcpu);
9587         u32 exec_control;
9588
9589         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9590         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9591         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9592         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9593         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9594         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9595         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9596         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9597         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9598         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9599         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9600         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9601         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9602         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9603         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9604         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9605         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9606         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9607         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9608         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9609         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9610         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9611         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9612         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9613         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9614         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9615         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9616         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9617         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9618         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9619         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9620         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9621         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9622         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9623         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9624         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9625
9626         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9627                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9628                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9629         } else {
9630                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9631                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9632         }
9633         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9634                 vmcs12->vm_entry_intr_info_field);
9635         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9636                 vmcs12->vm_entry_exception_error_code);
9637         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9638                 vmcs12->vm_entry_instruction_len);
9639         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9640                 vmcs12->guest_interruptibility_info);
9641         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9642         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9643         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9644                 vmcs12->guest_pending_dbg_exceptions);
9645         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9646         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9647
9648         if (nested_cpu_has_xsaves(vmcs12))
9649                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9650         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9651
9652         exec_control = vmcs12->pin_based_vm_exec_control;
9653         exec_control |= vmcs_config.pin_based_exec_ctrl;
9654         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9655
9656         if (nested_cpu_has_posted_intr(vmcs12)) {
9657                 /*
9658                  * Note that we use L0's vector here and in
9659                  * vmx_deliver_nested_posted_interrupt.
9660                  */
9661                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9662                 vmx->nested.pi_pending = false;
9663                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9664                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9665                         page_to_phys(vmx->nested.pi_desc_page) +
9666                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9667                         (PAGE_SIZE - 1)));
9668         } else
9669                 exec_control &= ~PIN_BASED_POSTED_INTR;
9670
9671         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9672
9673         vmx->nested.preemption_timer_expired = false;
9674         if (nested_cpu_has_preemption_timer(vmcs12))
9675                 vmx_start_preemption_timer(vcpu);
9676
9677         /*
9678          * Whether page-faults are trapped is determined by a combination of
9679          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9680          * If enable_ept, L0 doesn't care about page faults and we should
9681          * set all of these to L1's desires. However, if !enable_ept, L0 does
9682          * care about (at least some) page faults, and because it is not easy
9683          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9684          * to exit on each and every L2 page fault. This is done by setting
9685          * MASK=MATCH=0 and (see below) EB.PF=1.
9686          * Note that below we don't need special code to set EB.PF beyond the
9687          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9688          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9689          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9690          *
9691          * A problem with this approach (when !enable_ept) is that L1 may be
9692          * injected with more page faults than it asked for. This could have
9693          * caused problems, but in practice existing hypervisors don't care.
9694          * To fix this, we will need to emulate the PFEC checking (on the L1
9695          * page tables), using walk_addr(), when injecting PFs to L1.
9696          */
9697         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9698                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9699         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9700                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9701
9702         if (cpu_has_secondary_exec_ctrls()) {
9703                 exec_control = vmx_secondary_exec_control(vmx);
9704
9705                 /* Take the following fields only from vmcs12 */
9706                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9707                                   SECONDARY_EXEC_RDTSCP |
9708                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9709                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9710                                   SECONDARY_EXEC_PCOMMIT);
9711                 if (nested_cpu_has(vmcs12,
9712                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9713                         exec_control |= vmcs12->secondary_vm_exec_control;
9714
9715                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9716                         /*
9717                          * If translation failed, no matter: This feature asks
9718                          * to exit when accessing the given address, and if it
9719                          * can never be accessed, this feature won't do
9720                          * anything anyway.
9721                          */
9722                         if (!vmx->nested.apic_access_page)
9723                                 exec_control &=
9724                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9725                         else
9726                                 vmcs_write64(APIC_ACCESS_ADDR,
9727                                   page_to_phys(vmx->nested.apic_access_page));
9728                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9729                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9730                         exec_control |=
9731                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9732                         kvm_vcpu_reload_apic_access_page(vcpu);
9733                 }
9734
9735                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9736                         vmcs_write64(EOI_EXIT_BITMAP0,
9737                                 vmcs12->eoi_exit_bitmap0);
9738                         vmcs_write64(EOI_EXIT_BITMAP1,
9739                                 vmcs12->eoi_exit_bitmap1);
9740                         vmcs_write64(EOI_EXIT_BITMAP2,
9741                                 vmcs12->eoi_exit_bitmap2);
9742                         vmcs_write64(EOI_EXIT_BITMAP3,
9743                                 vmcs12->eoi_exit_bitmap3);
9744                         vmcs_write16(GUEST_INTR_STATUS,
9745                                 vmcs12->guest_intr_status);
9746                 }
9747
9748                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9749         }
9750
9751
9752         /*
9753          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9754          * Some constant fields are set here by vmx_set_constant_host_state().
9755          * Other fields are different per CPU, and will be set later when
9756          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9757          */
9758         vmx_set_constant_host_state(vmx);
9759
9760         /*
9761          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9762          * entry, but only if the current (host) sp changed from the value
9763          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9764          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9765          * here we just force the write to happen on entry.
9766          */
9767         vmx->host_rsp = 0;
9768
9769         exec_control = vmx_exec_control(vmx); /* L0's desires */
9770         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9771         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9772         exec_control &= ~CPU_BASED_TPR_SHADOW;
9773         exec_control |= vmcs12->cpu_based_vm_exec_control;
9774
9775         if (exec_control & CPU_BASED_TPR_SHADOW) {
9776                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9777                                 page_to_phys(vmx->nested.virtual_apic_page));
9778                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9779         }
9780
9781         if (cpu_has_vmx_msr_bitmap() &&
9782             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9783                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9784                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9785         } else
9786                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9787
9788         /*
9789          * Merging of IO bitmap not currently supported.
9790          * Rather, exit every time.
9791          */
9792         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9793         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9794
9795         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9796
9797         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9798          * bitwise-or of what L1 wants to trap for L2, and what we want to
9799          * trap. Note that CR0.TS also needs updating - we do this later.
9800          */
9801         update_exception_bitmap(vcpu);
9802         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9803         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9804
9805         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9806          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9807          * bits are further modified by vmx_set_efer() below.
9808          */
9809         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9810
9811         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9812          * emulated by vmx_set_efer(), below.
9813          */
9814         vm_entry_controls_init(vmx,
9815                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9816                         ~VM_ENTRY_IA32E_MODE) |
9817                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9818
9819         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9820                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9821                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9822         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9823                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9824
9825
9826         set_cr4_guest_host_mask(vmx);
9827
9828         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9829                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9830
9831         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9832                 vmcs_write64(TSC_OFFSET,
9833                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9834         else
9835                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9836
9837         if (enable_vpid) {
9838                 /*
9839                  * There is no direct mapping between vpid02 and vpid12, the
9840                  * vpid02 is per-vCPU for L0 and reused while the value of
9841                  * vpid12 is changed w/ one invvpid during nested vmentry.
9842                  * The vpid12 is allocated by L1 for L2, so it will not
9843                  * influence global bitmap(for vpid01 and vpid02 allocation)
9844                  * even if spawn a lot of nested vCPUs.
9845                  */
9846                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9847                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9848                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9849                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9850                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9851                         }
9852                 } else {
9853                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9854                         vmx_flush_tlb(vcpu);
9855                 }
9856
9857         }
9858
9859         if (nested_cpu_has_ept(vmcs12)) {
9860                 kvm_mmu_unload(vcpu);
9861                 nested_ept_init_mmu_context(vcpu);
9862         }
9863
9864         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9865                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9866         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9867                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9868         else
9869                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9870         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9871         vmx_set_efer(vcpu, vcpu->arch.efer);
9872
9873         /*
9874          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9875          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9876          * The CR0_READ_SHADOW is what L2 should have expected to read given
9877          * the specifications by L1; It's not enough to take
9878          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9879          * have more bits than L1 expected.
9880          */
9881         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9882         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9883
9884         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9885         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9886
9887         /* shadow page tables on either EPT or shadow page tables */
9888         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9889         kvm_mmu_reset_context(vcpu);
9890
9891         if (!enable_ept)
9892                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9893
9894         /*
9895          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9896          */
9897         if (enable_ept) {
9898                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9899                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9900                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9901                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9902         }
9903
9904         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9905         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9906 }
9907
9908 /*
9909  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9910  * for running an L2 nested guest.
9911  */
9912 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9913 {
9914         struct vmcs12 *vmcs12;
9915         struct vcpu_vmx *vmx = to_vmx(vcpu);
9916         int cpu;
9917         struct loaded_vmcs *vmcs02;
9918         bool ia32e;
9919         u32 msr_entry_idx;
9920
9921         if (!nested_vmx_check_permission(vcpu) ||
9922             !nested_vmx_check_vmcs12(vcpu))
9923                 return 1;
9924
9925         skip_emulated_instruction(vcpu);
9926         vmcs12 = get_vmcs12(vcpu);
9927
9928         if (enable_shadow_vmcs)
9929                 copy_shadow_to_vmcs12(vmx);
9930
9931         /*
9932          * The nested entry process starts with enforcing various prerequisites
9933          * on vmcs12 as required by the Intel SDM, and act appropriately when
9934          * they fail: As the SDM explains, some conditions should cause the
9935          * instruction to fail, while others will cause the instruction to seem
9936          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9937          * To speed up the normal (success) code path, we should avoid checking
9938          * for misconfigurations which will anyway be caught by the processor
9939          * when using the merged vmcs02.
9940          */
9941         if (vmcs12->launch_state == launch) {
9942                 nested_vmx_failValid(vcpu,
9943                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9944                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9945                 return 1;
9946         }
9947
9948         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9949             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9950                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9951                 return 1;
9952         }
9953
9954         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9955                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9956                 return 1;
9957         }
9958
9959         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9960                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9961                 return 1;
9962         }
9963
9964         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9965                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9966                 return 1;
9967         }
9968
9969         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9970                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9971                 return 1;
9972         }
9973
9974         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9975                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9976                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9977             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9978                                 vmx->nested.nested_vmx_secondary_ctls_low,
9979                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9980             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9981                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9982                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9983             !vmx_control_verify(vmcs12->vm_exit_controls,
9984                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9985                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9986             !vmx_control_verify(vmcs12->vm_entry_controls,
9987                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9988                                 vmx->nested.nested_vmx_entry_ctls_high))
9989         {
9990                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9991                 return 1;
9992         }
9993
9994         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9995             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9996                 nested_vmx_failValid(vcpu,
9997                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9998                 return 1;
9999         }
10000
10001         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10002             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10003                 nested_vmx_entry_failure(vcpu, vmcs12,
10004                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10005                 return 1;
10006         }
10007         if (vmcs12->vmcs_link_pointer != -1ull) {
10008                 nested_vmx_entry_failure(vcpu, vmcs12,
10009                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10010                 return 1;
10011         }
10012
10013         /*
10014          * If the load IA32_EFER VM-entry control is 1, the following checks
10015          * are performed on the field for the IA32_EFER MSR:
10016          * - Bits reserved in the IA32_EFER MSR must be 0.
10017          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10018          *   the IA-32e mode guest VM-exit control. It must also be identical
10019          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10020          *   CR0.PG) is 1.
10021          */
10022         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10023                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10024                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10025                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10026                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10027                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10028                         nested_vmx_entry_failure(vcpu, vmcs12,
10029                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10030                         return 1;
10031                 }
10032         }
10033
10034         /*
10035          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10036          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10037          * the values of the LMA and LME bits in the field must each be that of
10038          * the host address-space size VM-exit control.
10039          */
10040         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10041                 ia32e = (vmcs12->vm_exit_controls &
10042                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10043                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10044                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10045                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10046                         nested_vmx_entry_failure(vcpu, vmcs12,
10047                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10048                         return 1;
10049                 }
10050         }
10051
10052         /*
10053          * We're finally done with prerequisite checking, and can start with
10054          * the nested entry.
10055          */
10056
10057         vmcs02 = nested_get_current_vmcs02(vmx);
10058         if (!vmcs02)
10059                 return -ENOMEM;
10060
10061         enter_guest_mode(vcpu);
10062
10063         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10064
10065         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10066                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10067
10068         cpu = get_cpu();
10069         vmx->loaded_vmcs = vmcs02;
10070         vmx_vcpu_put(vcpu);
10071         vmx_vcpu_load(vcpu, cpu);
10072         vcpu->cpu = cpu;
10073         put_cpu();
10074
10075         vmx_segment_cache_clear(vmx);
10076
10077         prepare_vmcs02(vcpu, vmcs12);
10078
10079         msr_entry_idx = nested_vmx_load_msr(vcpu,
10080                                             vmcs12->vm_entry_msr_load_addr,
10081                                             vmcs12->vm_entry_msr_load_count);
10082         if (msr_entry_idx) {
10083                 leave_guest_mode(vcpu);
10084                 vmx_load_vmcs01(vcpu);
10085                 nested_vmx_entry_failure(vcpu, vmcs12,
10086                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10087                 return 1;
10088         }
10089
10090         vmcs12->launch_state = 1;
10091
10092         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10093                 return kvm_vcpu_halt(vcpu);
10094
10095         vmx->nested.nested_run_pending = 1;
10096
10097         /*
10098          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10099          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10100          * returned as far as L1 is concerned. It will only return (and set
10101          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10102          */
10103         return 1;
10104 }
10105
10106 /*
10107  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10108  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10109  * This function returns the new value we should put in vmcs12.guest_cr0.
10110  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10111  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10112  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10113  *     didn't trap the bit, because if L1 did, so would L0).
10114  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10115  *     been modified by L2, and L1 knows it. So just leave the old value of
10116  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10117  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10118  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10119  *     changed these bits, and therefore they need to be updated, but L0
10120  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10121  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10122  */
10123 static inline unsigned long
10124 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10125 {
10126         return
10127         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10128         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10129         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10130                         vcpu->arch.cr0_guest_owned_bits));
10131 }
10132
10133 static inline unsigned long
10134 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10135 {
10136         return
10137         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10138         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10139         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10140                         vcpu->arch.cr4_guest_owned_bits));
10141 }
10142
10143 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10144                                        struct vmcs12 *vmcs12)
10145 {
10146         u32 idt_vectoring;
10147         unsigned int nr;
10148
10149         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10150                 nr = vcpu->arch.exception.nr;
10151                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10152
10153                 if (kvm_exception_is_soft(nr)) {
10154                         vmcs12->vm_exit_instruction_len =
10155                                 vcpu->arch.event_exit_inst_len;
10156                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10157                 } else
10158                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10159
10160                 if (vcpu->arch.exception.has_error_code) {
10161                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10162                         vmcs12->idt_vectoring_error_code =
10163                                 vcpu->arch.exception.error_code;
10164                 }
10165
10166                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10167         } else if (vcpu->arch.nmi_injected) {
10168                 vmcs12->idt_vectoring_info_field =
10169                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10170         } else if (vcpu->arch.interrupt.pending) {
10171                 nr = vcpu->arch.interrupt.nr;
10172                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10173
10174                 if (vcpu->arch.interrupt.soft) {
10175                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10176                         vmcs12->vm_entry_instruction_len =
10177                                 vcpu->arch.event_exit_inst_len;
10178                 } else
10179                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10180
10181                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10182         }
10183 }
10184
10185 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10186 {
10187         struct vcpu_vmx *vmx = to_vmx(vcpu);
10188
10189         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10190             vmx->nested.preemption_timer_expired) {
10191                 if (vmx->nested.nested_run_pending)
10192                         return -EBUSY;
10193                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10194                 return 0;
10195         }
10196
10197         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10198                 if (vmx->nested.nested_run_pending ||
10199                     vcpu->arch.interrupt.pending)
10200                         return -EBUSY;
10201                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10202                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10203                                   INTR_INFO_VALID_MASK, 0);
10204                 /*
10205                  * The NMI-triggered VM exit counts as injection:
10206                  * clear this one and block further NMIs.
10207                  */
10208                 vcpu->arch.nmi_pending = 0;
10209                 vmx_set_nmi_mask(vcpu, true);
10210                 return 0;
10211         }
10212
10213         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10214             nested_exit_on_intr(vcpu)) {
10215                 if (vmx->nested.nested_run_pending)
10216                         return -EBUSY;
10217                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10218                 return 0;
10219         }
10220
10221         return vmx_complete_nested_posted_interrupt(vcpu);
10222 }
10223
10224 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10225 {
10226         ktime_t remaining =
10227                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10228         u64 value;
10229
10230         if (ktime_to_ns(remaining) <= 0)
10231                 return 0;
10232
10233         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10234         do_div(value, 1000000);
10235         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10236 }
10237
10238 /*
10239  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10240  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10241  * and this function updates it to reflect the changes to the guest state while
10242  * L2 was running (and perhaps made some exits which were handled directly by L0
10243  * without going back to L1), and to reflect the exit reason.
10244  * Note that we do not have to copy here all VMCS fields, just those that
10245  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10246  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10247  * which already writes to vmcs12 directly.
10248  */
10249 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10250                            u32 exit_reason, u32 exit_intr_info,
10251                            unsigned long exit_qualification)
10252 {
10253         /* update guest state fields: */
10254         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10255         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10256
10257         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10258         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10259         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10260
10261         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10262         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10263         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10264         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10265         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10266         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10267         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10268         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10269         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10270         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10271         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10272         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10273         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10274         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10275         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10276         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10277         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10278         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10279         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10280         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10281         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10282         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10283         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10284         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10285         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10286         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10287         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10288         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10289         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10290         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10291         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10292         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10293         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10294         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10295         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10296         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10297
10298         vmcs12->guest_interruptibility_info =
10299                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10300         vmcs12->guest_pending_dbg_exceptions =
10301                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10302         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10303                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10304         else
10305                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10306
10307         if (nested_cpu_has_preemption_timer(vmcs12)) {
10308                 if (vmcs12->vm_exit_controls &
10309                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10310                         vmcs12->vmx_preemption_timer_value =
10311                                 vmx_get_preemption_timer_value(vcpu);
10312                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10313         }
10314
10315         /*
10316          * In some cases (usually, nested EPT), L2 is allowed to change its
10317          * own CR3 without exiting. If it has changed it, we must keep it.
10318          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10319          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10320          *
10321          * Additionally, restore L2's PDPTR to vmcs12.
10322          */
10323         if (enable_ept) {
10324                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10325                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10326                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10327                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10328                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10329         }
10330
10331         if (nested_cpu_has_vid(vmcs12))
10332                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10333
10334         vmcs12->vm_entry_controls =
10335                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10336                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10337
10338         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10339                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10340                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10341         }
10342
10343         /* TODO: These cannot have changed unless we have MSR bitmaps and
10344          * the relevant bit asks not to trap the change */
10345         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10346                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10347         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10348                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10349         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10350         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10351         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10352         if (kvm_mpx_supported())
10353                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10354         if (nested_cpu_has_xsaves(vmcs12))
10355                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10356
10357         /* update exit information fields: */
10358
10359         vmcs12->vm_exit_reason = exit_reason;
10360         vmcs12->exit_qualification = exit_qualification;
10361
10362         vmcs12->vm_exit_intr_info = exit_intr_info;
10363         if ((vmcs12->vm_exit_intr_info &
10364              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10365             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10366                 vmcs12->vm_exit_intr_error_code =
10367                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10368         vmcs12->idt_vectoring_info_field = 0;
10369         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10370         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10371
10372         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10373                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10374                  * instead of reading the real value. */
10375                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10376
10377                 /*
10378                  * Transfer the event that L0 or L1 may wanted to inject into
10379                  * L2 to IDT_VECTORING_INFO_FIELD.
10380                  */
10381                 vmcs12_save_pending_event(vcpu, vmcs12);
10382         }
10383
10384         /*
10385          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10386          * preserved above and would only end up incorrectly in L1.
10387          */
10388         vcpu->arch.nmi_injected = false;
10389         kvm_clear_exception_queue(vcpu);
10390         kvm_clear_interrupt_queue(vcpu);
10391 }
10392
10393 /*
10394  * A part of what we need to when the nested L2 guest exits and we want to
10395  * run its L1 parent, is to reset L1's guest state to the host state specified
10396  * in vmcs12.
10397  * This function is to be called not only on normal nested exit, but also on
10398  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10399  * Failures During or After Loading Guest State").
10400  * This function should be called when the active VMCS is L1's (vmcs01).
10401  */
10402 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10403                                    struct vmcs12 *vmcs12)
10404 {
10405         struct kvm_segment seg;
10406
10407         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10408                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10409         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10410                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10411         else
10412                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10413         vmx_set_efer(vcpu, vcpu->arch.efer);
10414
10415         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10416         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10417         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10418         /*
10419          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10420          * actually changed, because it depends on the current state of
10421          * fpu_active (which may have changed).
10422          * Note that vmx_set_cr0 refers to efer set above.
10423          */
10424         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10425         /*
10426          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10427          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10428          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10429          */
10430         update_exception_bitmap(vcpu);
10431         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10432         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10433
10434         /*
10435          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10436          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10437          */
10438         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10439         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10440
10441         nested_ept_uninit_mmu_context(vcpu);
10442
10443         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10444         kvm_mmu_reset_context(vcpu);
10445
10446         if (!enable_ept)
10447                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10448
10449         if (enable_vpid) {
10450                 /*
10451                  * Trivially support vpid by letting L2s share their parent
10452                  * L1's vpid. TODO: move to a more elaborate solution, giving
10453                  * each L2 its own vpid and exposing the vpid feature to L1.
10454                  */
10455                 vmx_flush_tlb(vcpu);
10456         }
10457
10458
10459         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10460         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10461         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10462         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10463         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10464
10465         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10466         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10467                 vmcs_write64(GUEST_BNDCFGS, 0);
10468
10469         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10470                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10471                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10472         }
10473         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10474                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10475                         vmcs12->host_ia32_perf_global_ctrl);
10476
10477         /* Set L1 segment info according to Intel SDM
10478             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10479         seg = (struct kvm_segment) {
10480                 .base = 0,
10481                 .limit = 0xFFFFFFFF,
10482                 .selector = vmcs12->host_cs_selector,
10483                 .type = 11,
10484                 .present = 1,
10485                 .s = 1,
10486                 .g = 1
10487         };
10488         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10489                 seg.l = 1;
10490         else
10491                 seg.db = 1;
10492         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10493         seg = (struct kvm_segment) {
10494                 .base = 0,
10495                 .limit = 0xFFFFFFFF,
10496                 .type = 3,
10497                 .present = 1,
10498                 .s = 1,
10499                 .db = 1,
10500                 .g = 1
10501         };
10502         seg.selector = vmcs12->host_ds_selector;
10503         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10504         seg.selector = vmcs12->host_es_selector;
10505         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10506         seg.selector = vmcs12->host_ss_selector;
10507         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10508         seg.selector = vmcs12->host_fs_selector;
10509         seg.base = vmcs12->host_fs_base;
10510         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10511         seg.selector = vmcs12->host_gs_selector;
10512         seg.base = vmcs12->host_gs_base;
10513         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10514         seg = (struct kvm_segment) {
10515                 .base = vmcs12->host_tr_base,
10516                 .limit = 0x67,
10517                 .selector = vmcs12->host_tr_selector,
10518                 .type = 11,
10519                 .present = 1
10520         };
10521         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10522
10523         kvm_set_dr(vcpu, 7, 0x400);
10524         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10525
10526         if (cpu_has_vmx_msr_bitmap())
10527                 vmx_set_msr_bitmap(vcpu);
10528
10529         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10530                                 vmcs12->vm_exit_msr_load_count))
10531                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10532 }
10533
10534 /*
10535  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10536  * and modify vmcs12 to make it see what it would expect to see there if
10537  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10538  */
10539 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10540                               u32 exit_intr_info,
10541                               unsigned long exit_qualification)
10542 {
10543         struct vcpu_vmx *vmx = to_vmx(vcpu);
10544         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10545
10546         /* trying to cancel vmlaunch/vmresume is a bug */
10547         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10548
10549         leave_guest_mode(vcpu);
10550         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10551                        exit_qualification);
10552
10553         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10554                                  vmcs12->vm_exit_msr_store_count))
10555                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10556
10557         vmx_load_vmcs01(vcpu);
10558
10559         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10560             && nested_exit_intr_ack_set(vcpu)) {
10561                 int irq = kvm_cpu_get_interrupt(vcpu);
10562                 WARN_ON(irq < 0);
10563                 vmcs12->vm_exit_intr_info = irq |
10564                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10565         }
10566
10567         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10568                                        vmcs12->exit_qualification,
10569                                        vmcs12->idt_vectoring_info_field,
10570                                        vmcs12->vm_exit_intr_info,
10571                                        vmcs12->vm_exit_intr_error_code,
10572                                        KVM_ISA_VMX);
10573
10574         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10575         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10576         vmx_segment_cache_clear(vmx);
10577
10578         /* if no vmcs02 cache requested, remove the one we used */
10579         if (VMCS02_POOL_SIZE == 0)
10580                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10581
10582         load_vmcs12_host_state(vcpu, vmcs12);
10583
10584         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10585         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10586
10587         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10588         vmx->host_rsp = 0;
10589
10590         /* Unpin physical memory we referred to in vmcs02 */
10591         if (vmx->nested.apic_access_page) {
10592                 nested_release_page(vmx->nested.apic_access_page);
10593                 vmx->nested.apic_access_page = NULL;
10594         }
10595         if (vmx->nested.virtual_apic_page) {
10596                 nested_release_page(vmx->nested.virtual_apic_page);
10597                 vmx->nested.virtual_apic_page = NULL;
10598         }
10599         if (vmx->nested.pi_desc_page) {
10600                 kunmap(vmx->nested.pi_desc_page);
10601                 nested_release_page(vmx->nested.pi_desc_page);
10602                 vmx->nested.pi_desc_page = NULL;
10603                 vmx->nested.pi_desc = NULL;
10604         }
10605
10606         /*
10607          * We are now running in L2, mmu_notifier will force to reload the
10608          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10609          */
10610         kvm_vcpu_reload_apic_access_page(vcpu);
10611
10612         /*
10613          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10614          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10615          * success or failure flag accordingly.
10616          */
10617         if (unlikely(vmx->fail)) {
10618                 vmx->fail = 0;
10619                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10620         } else
10621                 nested_vmx_succeed(vcpu);
10622         if (enable_shadow_vmcs)
10623                 vmx->nested.sync_shadow_vmcs = true;
10624
10625         /* in case we halted in L2 */
10626         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10627 }
10628
10629 /*
10630  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10631  */
10632 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10633 {
10634         if (is_guest_mode(vcpu))
10635                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10636         free_nested(to_vmx(vcpu));
10637 }
10638
10639 /*
10640  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10641  * 23.7 "VM-entry failures during or after loading guest state" (this also
10642  * lists the acceptable exit-reason and exit-qualification parameters).
10643  * It should only be called before L2 actually succeeded to run, and when
10644  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10645  */
10646 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10647                         struct vmcs12 *vmcs12,
10648                         u32 reason, unsigned long qualification)
10649 {
10650         load_vmcs12_host_state(vcpu, vmcs12);
10651         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10652         vmcs12->exit_qualification = qualification;
10653         nested_vmx_succeed(vcpu);
10654         if (enable_shadow_vmcs)
10655                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10656 }
10657
10658 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10659                                struct x86_instruction_info *info,
10660                                enum x86_intercept_stage stage)
10661 {
10662         return X86EMUL_CONTINUE;
10663 }
10664
10665 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10666 {
10667         if (ple_gap)
10668                 shrink_ple_window(vcpu);
10669 }
10670
10671 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10672                                      struct kvm_memory_slot *slot)
10673 {
10674         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10675         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10676 }
10677
10678 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10679                                        struct kvm_memory_slot *slot)
10680 {
10681         kvm_mmu_slot_set_dirty(kvm, slot);
10682 }
10683
10684 static void vmx_flush_log_dirty(struct kvm *kvm)
10685 {
10686         kvm_flush_pml_buffers(kvm);
10687 }
10688
10689 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10690                                            struct kvm_memory_slot *memslot,
10691                                            gfn_t offset, unsigned long mask)
10692 {
10693         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10694 }
10695
10696 /*
10697  * This routine does the following things for vCPU which is going
10698  * to be blocked if VT-d PI is enabled.
10699  * - Store the vCPU to the wakeup list, so when interrupts happen
10700  *   we can find the right vCPU to wake up.
10701  * - Change the Posted-interrupt descriptor as below:
10702  *      'NDST' <-- vcpu->pre_pcpu
10703  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10704  * - If 'ON' is set during this process, which means at least one
10705  *   interrupt is posted for this vCPU, we cannot block it, in
10706  *   this case, return 1, otherwise, return 0.
10707  *
10708  */
10709 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10710 {
10711         unsigned long flags;
10712         unsigned int dest;
10713         struct pi_desc old, new;
10714         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10715
10716         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10717                 !irq_remapping_cap(IRQ_POSTING_CAP))
10718                 return 0;
10719
10720         vcpu->pre_pcpu = vcpu->cpu;
10721         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10722                           vcpu->pre_pcpu), flags);
10723         list_add_tail(&vcpu->blocked_vcpu_list,
10724                       &per_cpu(blocked_vcpu_on_cpu,
10725                       vcpu->pre_pcpu));
10726         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10727                                vcpu->pre_pcpu), flags);
10728
10729         do {
10730                 old.control = new.control = pi_desc->control;
10731
10732                 /*
10733                  * We should not block the vCPU if
10734                  * an interrupt is posted for it.
10735                  */
10736                 if (pi_test_on(pi_desc) == 1) {
10737                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10738                                           vcpu->pre_pcpu), flags);
10739                         list_del(&vcpu->blocked_vcpu_list);
10740                         spin_unlock_irqrestore(
10741                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10742                                         vcpu->pre_pcpu), flags);
10743                         vcpu->pre_pcpu = -1;
10744
10745                         return 1;
10746                 }
10747
10748                 WARN((pi_desc->sn == 1),
10749                      "Warning: SN field of posted-interrupts "
10750                      "is set before blocking\n");
10751
10752                 /*
10753                  * Since vCPU can be preempted during this process,
10754                  * vcpu->cpu could be different with pre_pcpu, we
10755                  * need to set pre_pcpu as the destination of wakeup
10756                  * notification event, then we can find the right vCPU
10757                  * to wakeup in wakeup handler if interrupts happen
10758                  * when the vCPU is in blocked state.
10759                  */
10760                 dest = cpu_physical_id(vcpu->pre_pcpu);
10761
10762                 if (x2apic_enabled())
10763                         new.ndst = dest;
10764                 else
10765                         new.ndst = (dest << 8) & 0xFF00;
10766
10767                 /* set 'NV' to 'wakeup vector' */
10768                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10769         } while (cmpxchg(&pi_desc->control, old.control,
10770                         new.control) != old.control);
10771
10772         return 0;
10773 }
10774
10775 static void vmx_post_block(struct kvm_vcpu *vcpu)
10776 {
10777         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10778         struct pi_desc old, new;
10779         unsigned int dest;
10780         unsigned long flags;
10781
10782         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10783                 !irq_remapping_cap(IRQ_POSTING_CAP))
10784                 return;
10785
10786         do {
10787                 old.control = new.control = pi_desc->control;
10788
10789                 dest = cpu_physical_id(vcpu->cpu);
10790
10791                 if (x2apic_enabled())
10792                         new.ndst = dest;
10793                 else
10794                         new.ndst = (dest << 8) & 0xFF00;
10795
10796                 /* Allow posting non-urgent interrupts */
10797                 new.sn = 0;
10798
10799                 /* set 'NV' to 'notification vector' */
10800                 new.nv = POSTED_INTR_VECTOR;
10801         } while (cmpxchg(&pi_desc->control, old.control,
10802                         new.control) != old.control);
10803
10804         if(vcpu->pre_pcpu != -1) {
10805                 spin_lock_irqsave(
10806                         &per_cpu(blocked_vcpu_on_cpu_lock,
10807                         vcpu->pre_pcpu), flags);
10808                 list_del(&vcpu->blocked_vcpu_list);
10809                 spin_unlock_irqrestore(
10810                         &per_cpu(blocked_vcpu_on_cpu_lock,
10811                         vcpu->pre_pcpu), flags);
10812                 vcpu->pre_pcpu = -1;
10813         }
10814 }
10815
10816 /*
10817  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10818  *
10819  * @kvm: kvm
10820  * @host_irq: host irq of the interrupt
10821  * @guest_irq: gsi of the interrupt
10822  * @set: set or unset PI
10823  * returns 0 on success, < 0 on failure
10824  */
10825 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10826                               uint32_t guest_irq, bool set)
10827 {
10828         struct kvm_kernel_irq_routing_entry *e;
10829         struct kvm_irq_routing_table *irq_rt;
10830         struct kvm_lapic_irq irq;
10831         struct kvm_vcpu *vcpu;
10832         struct vcpu_data vcpu_info;
10833         int idx, ret = -EINVAL;
10834
10835         if (!kvm_arch_has_assigned_device(kvm) ||
10836                 !irq_remapping_cap(IRQ_POSTING_CAP))
10837                 return 0;
10838
10839         idx = srcu_read_lock(&kvm->irq_srcu);
10840         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10841         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10842
10843         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10844                 if (e->type != KVM_IRQ_ROUTING_MSI)
10845                         continue;
10846                 /*
10847                  * VT-d PI cannot support posting multicast/broadcast
10848                  * interrupts to a vCPU, we still use interrupt remapping
10849                  * for these kind of interrupts.
10850                  *
10851                  * For lowest-priority interrupts, we only support
10852                  * those with single CPU as the destination, e.g. user
10853                  * configures the interrupts via /proc/irq or uses
10854                  * irqbalance to make the interrupts single-CPU.
10855                  *
10856                  * We will support full lowest-priority interrupt later.
10857                  */
10858
10859                 kvm_set_msi_irq(e, &irq);
10860                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10861                         /*
10862                          * Make sure the IRTE is in remapped mode if
10863                          * we don't handle it in posted mode.
10864                          */
10865                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10866                         if (ret < 0) {
10867                                 printk(KERN_INFO
10868                                    "failed to back to remapped mode, irq: %u\n",
10869                                    host_irq);
10870                                 goto out;
10871                         }
10872
10873                         continue;
10874                 }
10875
10876                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10877                 vcpu_info.vector = irq.vector;
10878
10879                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10880                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10881
10882                 if (set)
10883                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10884                 else {
10885                         /* suppress notification event before unposting */
10886                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10887                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10888                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10889                 }
10890
10891                 if (ret < 0) {
10892                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10893                                         __func__);
10894                         goto out;
10895                 }
10896         }
10897
10898         ret = 0;
10899 out:
10900         srcu_read_unlock(&kvm->irq_srcu, idx);
10901         return ret;
10902 }
10903
10904 static struct kvm_x86_ops vmx_x86_ops = {
10905         .cpu_has_kvm_support = cpu_has_kvm_support,
10906         .disabled_by_bios = vmx_disabled_by_bios,
10907         .hardware_setup = hardware_setup,
10908         .hardware_unsetup = hardware_unsetup,
10909         .check_processor_compatibility = vmx_check_processor_compat,
10910         .hardware_enable = hardware_enable,
10911         .hardware_disable = hardware_disable,
10912         .cpu_has_accelerated_tpr = report_flexpriority,
10913         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10914
10915         .vcpu_create = vmx_create_vcpu,
10916         .vcpu_free = vmx_free_vcpu,
10917         .vcpu_reset = vmx_vcpu_reset,
10918
10919         .prepare_guest_switch = vmx_save_host_state,
10920         .vcpu_load = vmx_vcpu_load,
10921         .vcpu_put = vmx_vcpu_put,
10922
10923         .update_bp_intercept = update_exception_bitmap,
10924         .get_msr = vmx_get_msr,
10925         .set_msr = vmx_set_msr,
10926         .get_segment_base = vmx_get_segment_base,
10927         .get_segment = vmx_get_segment,
10928         .set_segment = vmx_set_segment,
10929         .get_cpl = vmx_get_cpl,
10930         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10931         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10932         .decache_cr3 = vmx_decache_cr3,
10933         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10934         .set_cr0 = vmx_set_cr0,
10935         .set_cr3 = vmx_set_cr3,
10936         .set_cr4 = vmx_set_cr4,
10937         .set_efer = vmx_set_efer,
10938         .get_idt = vmx_get_idt,
10939         .set_idt = vmx_set_idt,
10940         .get_gdt = vmx_get_gdt,
10941         .set_gdt = vmx_set_gdt,
10942         .get_dr6 = vmx_get_dr6,
10943         .set_dr6 = vmx_set_dr6,
10944         .set_dr7 = vmx_set_dr7,
10945         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10946         .cache_reg = vmx_cache_reg,
10947         .get_rflags = vmx_get_rflags,
10948         .set_rflags = vmx_set_rflags,
10949
10950         .get_pkru = vmx_get_pkru,
10951
10952         .fpu_activate = vmx_fpu_activate,
10953         .fpu_deactivate = vmx_fpu_deactivate,
10954
10955         .tlb_flush = vmx_flush_tlb,
10956
10957         .run = vmx_vcpu_run,
10958         .handle_exit = vmx_handle_exit,
10959         .skip_emulated_instruction = skip_emulated_instruction,
10960         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10961         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10962         .patch_hypercall = vmx_patch_hypercall,
10963         .set_irq = vmx_inject_irq,
10964         .set_nmi = vmx_inject_nmi,
10965         .queue_exception = vmx_queue_exception,
10966         .cancel_injection = vmx_cancel_injection,
10967         .interrupt_allowed = vmx_interrupt_allowed,
10968         .nmi_allowed = vmx_nmi_allowed,
10969         .get_nmi_mask = vmx_get_nmi_mask,
10970         .set_nmi_mask = vmx_set_nmi_mask,
10971         .enable_nmi_window = enable_nmi_window,
10972         .enable_irq_window = enable_irq_window,
10973         .update_cr8_intercept = update_cr8_intercept,
10974         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10975         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10976         .get_enable_apicv = vmx_get_enable_apicv,
10977         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10978         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10979         .hwapic_irr_update = vmx_hwapic_irr_update,
10980         .hwapic_isr_update = vmx_hwapic_isr_update,
10981         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10982         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10983
10984         .set_tss_addr = vmx_set_tss_addr,
10985         .get_tdp_level = get_ept_level,
10986         .get_mt_mask = vmx_get_mt_mask,
10987
10988         .get_exit_info = vmx_get_exit_info,
10989
10990         .get_lpage_level = vmx_get_lpage_level,
10991
10992         .cpuid_update = vmx_cpuid_update,
10993
10994         .rdtscp_supported = vmx_rdtscp_supported,
10995         .invpcid_supported = vmx_invpcid_supported,
10996
10997         .set_supported_cpuid = vmx_set_supported_cpuid,
10998
10999         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11000
11001         .read_tsc_offset = vmx_read_tsc_offset,
11002         .write_tsc_offset = vmx_write_tsc_offset,
11003         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11004         .read_l1_tsc = vmx_read_l1_tsc,
11005
11006         .set_tdp_cr3 = vmx_set_cr3,
11007
11008         .check_intercept = vmx_check_intercept,
11009         .handle_external_intr = vmx_handle_external_intr,
11010         .mpx_supported = vmx_mpx_supported,
11011         .xsaves_supported = vmx_xsaves_supported,
11012
11013         .check_nested_events = vmx_check_nested_events,
11014
11015         .sched_in = vmx_sched_in,
11016
11017         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11018         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11019         .flush_log_dirty = vmx_flush_log_dirty,
11020         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11021
11022         .pre_block = vmx_pre_block,
11023         .post_block = vmx_post_block,
11024
11025         .pmu_ops = &intel_pmu_ops,
11026
11027         .update_pi_irte = vmx_update_pi_irte,
11028 };
11029
11030 static int __init vmx_init(void)
11031 {
11032         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11033                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11034         if (r)
11035                 return r;
11036
11037 #ifdef CONFIG_KEXEC_CORE
11038         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11039                            crash_vmclear_local_loaded_vmcss);
11040 #endif
11041
11042         return 0;
11043 }
11044
11045 static void __exit vmx_exit(void)
11046 {
11047 #ifdef CONFIG_KEXEC_CORE
11048         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11049         synchronize_rcu();
11050 #endif
11051
11052         kvm_exit();
11053 }
11054
11055 module_init(vmx_init)
11056 module_exit(vmx_exit)