2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include "assigned-dev.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
58 #define CREATE_TRACE_POINTS
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
126 static bool __read_mostly vector_hashing = true;
127 module_param(vector_hashing, bool, S_IRUGO);
129 static bool __read_mostly backwards_tsc_observed = false;
131 #define KVM_NR_SHARED_MSRS 16
133 struct kvm_shared_msrs_global {
135 u32 msrs[KVM_NR_SHARED_MSRS];
138 struct kvm_shared_msrs {
139 struct user_return_notifier urn;
141 struct kvm_shared_msr_values {
144 } values[KVM_NR_SHARED_MSRS];
147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
148 static struct kvm_shared_msrs __percpu *shared_msrs;
150 struct kvm_stats_debugfs_item debugfs_entries[] = {
151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
161 { "halt_exits", VCPU_STAT(halt_exits) },
162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
164 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
165 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
166 { "hypercalls", VCPU_STAT(hypercalls) },
167 { "request_irq", VCPU_STAT(request_irq_exits) },
168 { "irq_exits", VCPU_STAT(irq_exits) },
169 { "host_state_reload", VCPU_STAT(host_state_reload) },
170 { "efer_reload", VCPU_STAT(efer_reload) },
171 { "fpu_reload", VCPU_STAT(fpu_reload) },
172 { "insn_emulation", VCPU_STAT(insn_emulation) },
173 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
174 { "irq_injections", VCPU_STAT(irq_injections) },
175 { "nmi_injections", VCPU_STAT(nmi_injections) },
176 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
177 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
178 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
179 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
180 { "mmu_flooded", VM_STAT(mmu_flooded) },
181 { "mmu_recycled", VM_STAT(mmu_recycled) },
182 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
183 { "mmu_unsync", VM_STAT(mmu_unsync) },
184 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
185 { "largepages", VM_STAT(lpages) },
189 u64 __read_mostly host_xcr0;
191 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
193 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
197 vcpu->arch.apf.gfns[i] = ~0;
200 static void kvm_on_user_return(struct user_return_notifier *urn)
203 struct kvm_shared_msrs *locals
204 = container_of(urn, struct kvm_shared_msrs, urn);
205 struct kvm_shared_msr_values *values;
207 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
208 values = &locals->values[slot];
209 if (values->host != values->curr) {
210 wrmsrl(shared_msrs_global.msrs[slot], values->host);
211 values->curr = values->host;
214 locals->registered = false;
215 user_return_notifier_unregister(urn);
218 static void shared_msr_update(unsigned slot, u32 msr)
221 unsigned int cpu = smp_processor_id();
222 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
224 /* only read, and nobody should modify it at this time,
225 * so don't need lock */
226 if (slot >= shared_msrs_global.nr) {
227 printk(KERN_ERR "kvm: invalid MSR slot!");
230 rdmsrl_safe(msr, &value);
231 smsr->values[slot].host = value;
232 smsr->values[slot].curr = value;
235 void kvm_define_shared_msr(unsigned slot, u32 msr)
237 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
238 shared_msrs_global.msrs[slot] = msr;
239 if (slot >= shared_msrs_global.nr)
240 shared_msrs_global.nr = slot + 1;
242 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
244 static void kvm_shared_msr_cpu_online(void)
248 for (i = 0; i < shared_msrs_global.nr; ++i)
249 shared_msr_update(i, shared_msrs_global.msrs[i]);
252 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
254 unsigned int cpu = smp_processor_id();
255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
258 if (((value ^ smsr->values[slot].curr) & mask) == 0)
260 smsr->values[slot].curr = value;
261 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
265 if (!smsr->registered) {
266 smsr->urn.on_user_return = kvm_on_user_return;
267 user_return_notifier_register(&smsr->urn);
268 smsr->registered = true;
272 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
274 static void drop_user_return_notifiers(void)
276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
279 if (smsr->registered)
280 kvm_on_user_return(&smsr->urn);
283 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
285 return vcpu->arch.apic_base;
287 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
289 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
291 u64 old_state = vcpu->arch.apic_base &
292 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
293 u64 new_state = msr_info->data &
294 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
295 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
296 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
298 if (!msr_info->host_initiated &&
299 ((msr_info->data & reserved_bits) != 0 ||
300 new_state == X2APIC_ENABLE ||
301 (new_state == MSR_IA32_APICBASE_ENABLE &&
302 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
303 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
307 kvm_lapic_set_base(vcpu, msr_info->data);
310 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
312 asmlinkage __visible void kvm_spurious_fault(void)
314 /* Fault while not rebooting. We want the trace. */
317 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
319 #define EXCPT_BENIGN 0
320 #define EXCPT_CONTRIBUTORY 1
323 static int exception_class(int vector)
333 return EXCPT_CONTRIBUTORY;
340 #define EXCPT_FAULT 0
342 #define EXCPT_ABORT 2
343 #define EXCPT_INTERRUPT 3
345 static int exception_type(int vector)
349 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
350 return EXCPT_INTERRUPT;
354 /* #DB is trap, as instruction watchpoints are handled elsewhere */
355 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
358 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
361 /* Reserved exceptions will result in fault */
365 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
366 unsigned nr, bool has_error, u32 error_code,
372 kvm_make_request(KVM_REQ_EVENT, vcpu);
374 if (!vcpu->arch.exception.pending) {
376 if (has_error && !is_protmode(vcpu))
378 vcpu->arch.exception.pending = true;
379 vcpu->arch.exception.has_error_code = has_error;
380 vcpu->arch.exception.nr = nr;
381 vcpu->arch.exception.error_code = error_code;
382 vcpu->arch.exception.reinject = reinject;
386 /* to check exception */
387 prev_nr = vcpu->arch.exception.nr;
388 if (prev_nr == DF_VECTOR) {
389 /* triple fault -> shutdown */
390 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
393 class1 = exception_class(prev_nr);
394 class2 = exception_class(nr);
395 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
396 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
397 /* generate double fault per SDM Table 5-5 */
398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = true;
400 vcpu->arch.exception.nr = DF_VECTOR;
401 vcpu->arch.exception.error_code = 0;
403 /* replace previous exception with a new one in a hope
404 that instruction re-execution will regenerate lost
409 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
411 kvm_multiple_exception(vcpu, nr, false, 0, false);
413 EXPORT_SYMBOL_GPL(kvm_queue_exception);
415 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417 kvm_multiple_exception(vcpu, nr, false, 0, true);
419 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
421 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
424 kvm_inject_gp(vcpu, 0);
426 kvm_x86_ops->skip_emulated_instruction(vcpu);
428 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
430 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
432 ++vcpu->stat.pf_guest;
433 vcpu->arch.cr2 = fault->address;
434 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
436 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
438 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
440 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
441 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
443 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
445 return fault->nested_page_fault;
448 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
450 atomic_inc(&vcpu->arch.nmi_queued);
451 kvm_make_request(KVM_REQ_NMI, vcpu);
453 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
455 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
457 kvm_multiple_exception(vcpu, nr, true, error_code, false);
459 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
461 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463 kvm_multiple_exception(vcpu, nr, true, error_code, true);
465 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
468 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
469 * a #GP and return false.
471 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
473 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
475 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
478 EXPORT_SYMBOL_GPL(kvm_require_cpl);
480 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
482 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
485 kvm_queue_exception(vcpu, UD_VECTOR);
488 EXPORT_SYMBOL_GPL(kvm_require_dr);
491 * This function will be used to read from the physical memory of the currently
492 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
493 * can read from guest physical or from the guest's guest physical memory.
495 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
496 gfn_t ngfn, void *data, int offset, int len,
499 struct x86_exception exception;
503 ngpa = gfn_to_gpa(ngfn);
504 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
505 if (real_gfn == UNMAPPED_GVA)
508 real_gfn = gpa_to_gfn(real_gfn);
510 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
512 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
514 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
515 void *data, int offset, int len, u32 access)
517 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
518 data, offset, len, access);
522 * Load the pae pdptrs. Return true is they are all valid.
524 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
526 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
527 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
530 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
532 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
533 offset * sizeof(u64), sizeof(pdpte),
534 PFERR_USER_MASK|PFERR_WRITE_MASK);
539 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
540 if (is_present_gpte(pdpte[i]) &&
542 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
549 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
550 __set_bit(VCPU_EXREG_PDPTR,
551 (unsigned long *)&vcpu->arch.regs_avail);
552 __set_bit(VCPU_EXREG_PDPTR,
553 (unsigned long *)&vcpu->arch.regs_dirty);
558 EXPORT_SYMBOL_GPL(load_pdptrs);
560 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
562 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
568 if (is_long_mode(vcpu) || !is_pae(vcpu))
571 if (!test_bit(VCPU_EXREG_PDPTR,
572 (unsigned long *)&vcpu->arch.regs_avail))
575 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
576 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
577 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
578 PFERR_USER_MASK | PFERR_WRITE_MASK);
581 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
587 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
589 unsigned long old_cr0 = kvm_read_cr0(vcpu);
590 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
595 if (cr0 & 0xffffffff00000000UL)
599 cr0 &= ~CR0_RESERVED_BITS;
601 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
604 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
607 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
609 if ((vcpu->arch.efer & EFER_LME)) {
614 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
619 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
624 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
627 kvm_x86_ops->set_cr0(vcpu, cr0);
629 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
630 kvm_clear_async_pf_completion_queue(vcpu);
631 kvm_async_pf_hash_reset(vcpu);
634 if ((cr0 ^ old_cr0) & update_bits)
635 kvm_mmu_reset_context(vcpu);
637 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
638 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
639 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
640 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
644 EXPORT_SYMBOL_GPL(kvm_set_cr0);
646 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
648 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
650 EXPORT_SYMBOL_GPL(kvm_lmsw);
652 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
655 !vcpu->guest_xcr0_loaded) {
656 /* kvm_set_xcr() also depends on this */
657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
658 vcpu->guest_xcr0_loaded = 1;
662 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
664 if (vcpu->guest_xcr0_loaded) {
665 if (vcpu->arch.xcr0 != host_xcr0)
666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
667 vcpu->guest_xcr0_loaded = 0;
671 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
674 u64 old_xcr0 = vcpu->arch.xcr0;
677 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
678 if (index != XCR_XFEATURE_ENABLED_MASK)
680 if (!(xcr0 & XFEATURE_MASK_FP))
682 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
686 * Do not allow the guest to set bits that we do not support
687 * saving. However, xcr0 bit 0 is always set, even if the
688 * emulated CPU does not support XSAVE (see fx_init).
690 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
691 if (xcr0 & ~valid_bits)
694 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
695 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
698 if (xcr0 & XFEATURE_MASK_AVX512) {
699 if (!(xcr0 & XFEATURE_MASK_YMM))
701 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
704 vcpu->arch.xcr0 = xcr0;
706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
707 kvm_update_cpuid(vcpu);
711 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
715 kvm_inject_gp(vcpu, 0);
720 EXPORT_SYMBOL_GPL(kvm_set_xcr);
722 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
728 if (cr4 & CR4_RESERVED_BITS)
731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
746 if (is_long_mode(vcpu)) {
747 if (!(cr4 & X86_CR4_PAE))
749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
769 kvm_mmu_reset_context(vcpu);
771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
772 kvm_update_cpuid(vcpu);
776 EXPORT_SYMBOL_GPL(kvm_set_cr4);
778 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
781 cr3 &= ~CR3_PCID_INVD;
784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
785 kvm_mmu_sync_roots(vcpu);
786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
790 if (is_long_mode(vcpu)) {
791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
797 vcpu->arch.cr3 = cr3;
798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
799 kvm_mmu_new_cr3(vcpu);
802 EXPORT_SYMBOL_GPL(kvm_set_cr3);
804 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
806 if (cr8 & CR8_RESERVED_BITS)
808 if (lapic_in_kernel(vcpu))
809 kvm_lapic_set_tpr(vcpu, cr8);
811 vcpu->arch.cr8 = cr8;
814 EXPORT_SYMBOL_GPL(kvm_set_cr8);
816 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
818 if (lapic_in_kernel(vcpu))
819 return kvm_lapic_get_cr8(vcpu);
821 return vcpu->arch.cr8;
823 EXPORT_SYMBOL_GPL(kvm_get_cr8);
825 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
836 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
842 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
856 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
858 u64 fixed = DR6_FIXED_1;
860 if (!guest_cpuid_has_rtm(vcpu))
865 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
876 if (val & 0xffffffff00000000ULL)
878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
879 kvm_update_dr6(vcpu);
884 if (val & 0xffffffff00000000ULL)
886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
887 kvm_update_dr7(vcpu);
894 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
896 if (__kvm_set_dr(vcpu, dr, val)) {
897 kvm_inject_gp(vcpu, 0);
902 EXPORT_SYMBOL_GPL(kvm_set_dr);
904 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
908 *val = vcpu->arch.db[dr];
913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
916 *val = kvm_x86_ops->get_dr6(vcpu);
921 *val = vcpu->arch.dr7;
926 EXPORT_SYMBOL_GPL(kvm_get_dr);
928 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
941 EXPORT_SYMBOL_GPL(kvm_rdpmc);
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
947 * This list is modified at module load time to reflect the
948 * capabilities of the host cpu. This capabilities test skips MSRs that are
949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
953 static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
963 static unsigned num_msrs_to_save;
965 static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
974 HV_X64_MSR_VP_RUNTIME,
976 HV_X64_MSR_STIMER0_CONFIG,
977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
981 MSR_IA32_TSCDEADLINE,
982 MSR_IA32_MISC_ENABLE,
988 static unsigned num_emulated_msrs;
990 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
992 if (efer & efer_reserved_bits)
995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1013 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1015 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1017 u64 old_efer = vcpu->arch.efer;
1019 if (!kvm_valid_efer(vcpu, efer))
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1027 efer |= vcpu->arch.efer & EFER_LMA;
1029 kvm_x86_ops->set_efer(vcpu, efer);
1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1038 void kvm_enable_efer_bits(u64 mask)
1040 efer_reserved_bits &= ~mask;
1042 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1049 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1051 switch (msr->index) {
1054 case MSR_KERNEL_GS_BASE:
1057 if (is_noncanonical_address(msr->data))
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1074 msr->data = get_canonical(msr->data);
1076 return kvm_x86_ops->set_msr(vcpu, msr);
1078 EXPORT_SYMBOL_GPL(kvm_set_msr);
1081 * Adapt set_msr() to msr_io()'s calling convention
1083 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1085 struct msr_data msr;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1098 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1100 struct msr_data msr;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
1108 #ifdef CONFIG_X86_64
1109 struct pvclock_gtod_data {
1112 struct { /* extract of a clocksource struct */
1124 static struct pvclock_gtod_data pvclock_gtod_data;
1126 static void update_pvclock_gtod(struct timekeeper *tk)
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1133 write_seqcount_begin(&vdata->seq);
1135 /* copy pvclock gtod data */
1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
1142 vdata->boot_ns = boot_ns;
1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1145 write_seqcount_end(&vdata->seq);
1149 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1159 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1163 struct pvclock_wall_clock wc;
1164 struct timespec boot;
1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1174 ++version; /* first time write, random junk */
1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1182 * The guest calculates current wall clock time by adding
1183 * system time (updated by kvm_guest_time_update below) to the
1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1203 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1205 do_shl32_div32(dividend, divisor);
1209 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1210 s8 *pshift, u32 *pmultiplier)
1218 scaled64 = scaled_hz;
1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1224 tps32 = (uint32_t)tps64;
1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1234 *pmultiplier = div_frac(scaled64, tps32);
1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1240 #ifdef CONFIG_X86_64
1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1245 static unsigned long max_tsc_khz;
1247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
1253 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1255 u64 v = (u64)khz * (1000000 + ppm);
1260 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1264 /* Guest TSC same frequency as host TSC? */
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1296 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
1301 /* tsc_khz can be zero if TSC calibration fails */
1302 if (user_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1329 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
1334 tsc += vcpu->arch.this_tsc_write;
1338 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1340 #ifdef CONFIG_X86_64
1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1366 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1373 * Multiply tsc by a fixed point number represented by ratio.
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1382 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1397 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1399 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1405 return target_tsc - tsc;
1408 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1412 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1414 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1416 struct kvm *kvm = vcpu->kvm;
1417 u64 offset, ns, elapsed;
1418 unsigned long flags;
1421 bool already_matched;
1422 u64 data = msr->data;
1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1425 offset = kvm_compute_tsc_offset(vcpu, data);
1426 ns = get_kernel_ns();
1427 elapsed = ns - kvm->arch.last_tsc_nsec;
1429 if (vcpu->arch.virtual_tsc_khz) {
1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
1434 #ifdef CONFIG_X86_64
1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1437 /* do_div() only does unsigned */
1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1447 _ASM_EXTABLE(1b, 4b)
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1453 do_div(elapsed, 1000);
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1460 usdiff = USEC_PER_SEC;
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1474 if (usdiff < USEC_PER_SEC &&
1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1476 if (!check_tsc_unstable()) {
1477 offset = kvm->arch.cur_tsc_offset;
1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
1482 offset = kvm_compute_tsc_offset(vcpu, data);
1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
1493 * exact software computation in compute_guest_tsc()
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1503 kvm->arch.cur_tsc_generation, data);
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1514 vcpu->arch.last_guest_tsc = data;
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1528 kvm->arch.nr_vcpus_matched_tsc = 0;
1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1537 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1539 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1545 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1553 #ifdef CONFIG_X86_64
1555 static cycle_t read_tsc(void)
1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
1560 if (likely(ret >= last))
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a function of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1575 static inline u64 vgettsc(cycle_t *cycle_now)
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1580 *cycle_now = read_tsc();
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1586 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1594 seq = read_seqcount_begin(>od->seq);
1595 mode = gtod->clock.vclock_mode;
1596 ns = gtod->nsec_base;
1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
1599 ns += gtod->boot_ns;
1600 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1606 /* returns true if host is using tsc clocksource */
1607 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
1622 * CPUs at the next numbered event.
1624 * "timespecX" represents host monotonic time. "tscX" represents
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1642 * - 0 < N - M => M < N
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1658 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1660 #ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1663 bool host_tsc_clocksource, vcpus_matched;
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
1669 * If the host uses TSC clock, then passthrough TSC as stable
1672 host_tsc_clocksource = kvm_get_time_and_clockread(
1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1689 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1694 static void kvm_gen_update_masterclock(struct kvm *kvm)
1696 #ifdef CONFIG_X86_64
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1706 kvm_for_each_vcpu(i, vcpu, kvm)
1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1717 static int kvm_guest_time_update(struct kvm_vcpu *v)
1719 unsigned long flags, tgt_tsc_khz;
1720 struct kvm_vcpu_arch *vcpu = &v->arch;
1721 struct kvm_arch *ka = &v->kvm->arch;
1723 u64 tsc_timestamp, host_tsc;
1724 struct pvclock_vcpu_time_info guest_hv_clock;
1726 bool use_master_clock;
1732 * If the host uses TSC clock, then passthrough TSC as stable
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1751 if (!use_master_clock) {
1753 kernel_ns = get_kernel_ns();
1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1772 tsc_timestamp = tsc;
1776 local_irq_restore(flags);
1778 if (!vcpu->pv_time_enabled)
1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
1791 /* With all the info we got, fill in the values */
1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1794 vcpu->last_guest_tsc = tsc_timestamp;
1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1819 sizeof(vcpu->hv_clock.version));
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1835 vcpu->hv_clock.flags = pvclock_flags;
1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1841 sizeof(vcpu->hv_clock));
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 sizeof(vcpu->hv_clock.version));
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1859 * So in those cases, request a kvmclock update for all vcpus.
1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
1866 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1868 static void kvmclock_update_fn(struct work_struct *work)
1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
1875 struct kvm_vcpu *vcpu;
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1879 kvm_vcpu_kick(vcpu);
1883 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1885 struct kvm *kvm = v->kvm;
1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1892 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1894 static void kvmclock_sync_fn(struct work_struct *work)
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1901 if (!kvmclock_periodic_sync)
1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1909 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1915 case MSR_IA32_MCG_STATUS:
1916 vcpu->arch.mcg_status = data;
1918 case MSR_IA32_MCG_CTL:
1919 if (!(mcg_cap & MCG_CTL_P))
1921 if (data != 0 && data != ~(u64)0)
1923 vcpu->arch.mcg_ctl = data;
1926 if (msr >= MSR_IA32_MC0_CTL &&
1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
1928 u32 offset = msr - MSR_IA32_MC0_CTL;
1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1934 if ((offset & 0x3) == 0 &&
1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
1937 vcpu->arch.mce_banks[offset] = data;
1945 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1959 if (page_num >= blob_size)
1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1976 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1978 gpa_t gpa = data & ~0x3f;
1980 /* Bits 2:5 are reserved, Should be zero */
1984 vcpu->arch.apf.msr_val = data;
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1997 kvm_async_pf_wakeup_all(vcpu);
2001 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2003 vcpu->arch.pv_time_enabled = false;
2006 static void record_steal_time(struct kvm_vcpu *vcpu)
2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2011 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2012 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2015 if (vcpu->arch.st.steal.version & 1)
2016 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2018 vcpu->arch.st.steal.version += 1;
2020 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2021 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2025 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2026 vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2034 vcpu->arch.st.steal.version += 1;
2036 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2040 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2043 u32 msr = msr_info->index;
2044 u64 data = msr_info->data;
2047 case MSR_AMD64_NB_CFG:
2048 case MSR_IA32_UCODE_REV:
2049 case MSR_IA32_UCODE_WRITE:
2050 case MSR_VM_HSAVE_PA:
2051 case MSR_AMD64_PATCH_LOADER:
2052 case MSR_AMD64_BU_CFG2:
2056 return set_efer(vcpu, data);
2058 data &= ~(u64)0x40; /* ignore flush filter disable */
2059 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2060 data &= ~(u64)0x8; /* ignore TLB cache disable */
2061 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2068 case MSR_FAM10H_MMIO_CONF_BASE:
2070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2075 case MSR_IA32_DEBUGCTLMSR:
2077 /* We support the non-activated case already */
2079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2080 /* Values other than LBR and BTF are vendor-specific,
2081 thus reserved and should throw a #GP */
2084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2087 case 0x200 ... 0x2ff:
2088 return kvm_mtrr_set_msr(vcpu, msr, data);
2089 case MSR_IA32_APICBASE:
2090 return kvm_set_apic_base(vcpu, msr_info);
2091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2092 return kvm_x2apic_msr_write(vcpu, msr, data);
2093 case MSR_IA32_TSCDEADLINE:
2094 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2096 case MSR_IA32_TSC_ADJUST:
2097 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2098 if (!msr_info->host_initiated) {
2099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2100 adjust_tsc_offset_guest(vcpu, adj);
2102 vcpu->arch.ia32_tsc_adjust_msr = data;
2105 case MSR_IA32_MISC_ENABLE:
2106 vcpu->arch.ia32_misc_enable_msr = data;
2108 case MSR_IA32_SMBASE:
2109 if (!msr_info->host_initiated)
2111 vcpu->arch.smbase = data;
2113 case MSR_KVM_WALL_CLOCK_NEW:
2114 case MSR_KVM_WALL_CLOCK:
2115 vcpu->kvm->arch.wall_clock = data;
2116 kvm_write_wall_clock(vcpu->kvm, data);
2118 case MSR_KVM_SYSTEM_TIME_NEW:
2119 case MSR_KVM_SYSTEM_TIME: {
2121 struct kvm_arch *ka = &vcpu->kvm->arch;
2123 kvmclock_reset(vcpu);
2125 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2126 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2128 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2129 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2132 ka->boot_vcpu_runs_old_kvmclock = tmp;
2135 vcpu->arch.time = data;
2136 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2138 /* we verify if the enable bit is set... */
2142 gpa_offset = data & ~(PAGE_MASK | 1);
2144 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2145 &vcpu->arch.pv_time, data & ~1ULL,
2146 sizeof(struct pvclock_vcpu_time_info)))
2147 vcpu->arch.pv_time_enabled = false;
2149 vcpu->arch.pv_time_enabled = true;
2153 case MSR_KVM_ASYNC_PF_EN:
2154 if (kvm_pv_enable_async_pf(vcpu, data))
2157 case MSR_KVM_STEAL_TIME:
2159 if (unlikely(!sched_info_on()))
2162 if (data & KVM_STEAL_RESERVED_MASK)
2165 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2166 data & KVM_STEAL_VALID_BITS,
2167 sizeof(struct kvm_steal_time)))
2170 vcpu->arch.st.msr_val = data;
2172 if (!(data & KVM_MSR_ENABLED))
2175 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2178 case MSR_KVM_PV_EOI_EN:
2179 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2183 case MSR_IA32_MCG_CTL:
2184 case MSR_IA32_MCG_STATUS:
2185 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2186 return set_msr_mce(vcpu, msr, data);
2188 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2189 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2190 pr = true; /* fall through */
2191 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2192 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2193 if (kvm_pmu_is_valid_msr(vcpu, msr))
2194 return kvm_pmu_set_msr(vcpu, msr_info);
2196 if (pr || data != 0)
2197 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2198 "0x%x data 0x%llx\n", msr, data);
2200 case MSR_K7_CLK_CTL:
2202 * Ignore all writes to this no longer documented MSR.
2203 * Writes are only relevant for old K7 processors,
2204 * all pre-dating SVM, but a recommended workaround from
2205 * AMD for these chips. It is possible to specify the
2206 * affected processor models on the command line, hence
2207 * the need to ignore the workaround.
2210 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2211 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2212 case HV_X64_MSR_CRASH_CTL:
2213 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2214 return kvm_hv_set_msr_common(vcpu, msr, data,
2215 msr_info->host_initiated);
2216 case MSR_IA32_BBL_CR_CTL3:
2217 /* Drop writes to this legacy MSR -- see rdmsr
2218 * counterpart for further detail.
2220 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2222 case MSR_AMD64_OSVW_ID_LENGTH:
2223 if (!guest_cpuid_has_osvw(vcpu))
2225 vcpu->arch.osvw.length = data;
2227 case MSR_AMD64_OSVW_STATUS:
2228 if (!guest_cpuid_has_osvw(vcpu))
2230 vcpu->arch.osvw.status = data;
2233 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2234 return xen_hvm_config(vcpu, data);
2235 if (kvm_pmu_is_valid_msr(vcpu, msr))
2236 return kvm_pmu_set_msr(vcpu, msr_info);
2238 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2242 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2249 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2253 * Reads an msr value (of 'msr_index') into 'pdata'.
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2257 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2259 return kvm_x86_ops->get_msr(vcpu, msr);
2261 EXPORT_SYMBOL_GPL(kvm_get_msr);
2263 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2266 u64 mcg_cap = vcpu->arch.mcg_cap;
2267 unsigned bank_num = mcg_cap & 0xff;
2270 case MSR_IA32_P5_MC_ADDR:
2271 case MSR_IA32_P5_MC_TYPE:
2274 case MSR_IA32_MCG_CAP:
2275 data = vcpu->arch.mcg_cap;
2277 case MSR_IA32_MCG_CTL:
2278 if (!(mcg_cap & MCG_CTL_P))
2280 data = vcpu->arch.mcg_ctl;
2282 case MSR_IA32_MCG_STATUS:
2283 data = vcpu->arch.mcg_status;
2286 if (msr >= MSR_IA32_MC0_CTL &&
2287 msr < MSR_IA32_MCx_CTL(bank_num)) {
2288 u32 offset = msr - MSR_IA32_MC0_CTL;
2289 data = vcpu->arch.mce_banks[offset];
2298 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2300 switch (msr_info->index) {
2301 case MSR_IA32_PLATFORM_ID:
2302 case MSR_IA32_EBL_CR_POWERON:
2303 case MSR_IA32_DEBUGCTLMSR:
2304 case MSR_IA32_LASTBRANCHFROMIP:
2305 case MSR_IA32_LASTBRANCHTOIP:
2306 case MSR_IA32_LASTINTFROMIP:
2307 case MSR_IA32_LASTINTTOIP:
2309 case MSR_K8_TSEG_ADDR:
2310 case MSR_K8_TSEG_MASK:
2312 case MSR_VM_HSAVE_PA:
2313 case MSR_K8_INT_PENDING_MSG:
2314 case MSR_AMD64_NB_CFG:
2315 case MSR_FAM10H_MMIO_CONF_BASE:
2316 case MSR_AMD64_BU_CFG2:
2317 case MSR_IA32_PERF_CTL:
2320 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2321 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2322 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2323 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2324 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2325 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2328 case MSR_IA32_UCODE_REV:
2329 msr_info->data = 0x100000000ULL;
2332 case 0x200 ... 0x2ff:
2333 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2334 case 0xcd: /* fsb frequency */
2338 * MSR_EBC_FREQUENCY_ID
2339 * Conservative value valid for even the basic CPU models.
2340 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2341 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2342 * and 266MHz for model 3, or 4. Set Core Clock
2343 * Frequency to System Bus Frequency Ratio to 1 (bits
2344 * 31:24) even though these are only valid for CPU
2345 * models > 2, however guests may end up dividing or
2346 * multiplying by zero otherwise.
2348 case MSR_EBC_FREQUENCY_ID:
2349 msr_info->data = 1 << 24;
2351 case MSR_IA32_APICBASE:
2352 msr_info->data = kvm_get_apic_base(vcpu);
2354 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2355 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2357 case MSR_IA32_TSCDEADLINE:
2358 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2360 case MSR_IA32_TSC_ADJUST:
2361 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2363 case MSR_IA32_MISC_ENABLE:
2364 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2366 case MSR_IA32_SMBASE:
2367 if (!msr_info->host_initiated)
2369 msr_info->data = vcpu->arch.smbase;
2371 case MSR_IA32_PERF_STATUS:
2372 /* TSC increment by tick */
2373 msr_info->data = 1000ULL;
2374 /* CPU multiplier */
2375 msr_info->data |= (((uint64_t)4ULL) << 40);
2378 msr_info->data = vcpu->arch.efer;
2380 case MSR_KVM_WALL_CLOCK:
2381 case MSR_KVM_WALL_CLOCK_NEW:
2382 msr_info->data = vcpu->kvm->arch.wall_clock;
2384 case MSR_KVM_SYSTEM_TIME:
2385 case MSR_KVM_SYSTEM_TIME_NEW:
2386 msr_info->data = vcpu->arch.time;
2388 case MSR_KVM_ASYNC_PF_EN:
2389 msr_info->data = vcpu->arch.apf.msr_val;
2391 case MSR_KVM_STEAL_TIME:
2392 msr_info->data = vcpu->arch.st.msr_val;
2394 case MSR_KVM_PV_EOI_EN:
2395 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2397 case MSR_IA32_P5_MC_ADDR:
2398 case MSR_IA32_P5_MC_TYPE:
2399 case MSR_IA32_MCG_CAP:
2400 case MSR_IA32_MCG_CTL:
2401 case MSR_IA32_MCG_STATUS:
2402 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2403 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2404 case MSR_K7_CLK_CTL:
2406 * Provide expected ramp-up count for K7. All other
2407 * are set to zero, indicating minimum divisors for
2410 * This prevents guest kernels on AMD host with CPU
2411 * type 6, model 8 and higher from exploding due to
2412 * the rdmsr failing.
2414 msr_info->data = 0x20000000;
2416 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2417 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2418 case HV_X64_MSR_CRASH_CTL:
2419 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2420 return kvm_hv_get_msr_common(vcpu,
2421 msr_info->index, &msr_info->data);
2423 case MSR_IA32_BBL_CR_CTL3:
2424 /* This legacy MSR exists but isn't fully documented in current
2425 * silicon. It is however accessed by winxp in very narrow
2426 * scenarios where it sets bit #19, itself documented as
2427 * a "reserved" bit. Best effort attempt to source coherent
2428 * read data here should the balance of the register be
2429 * interpreted by the guest:
2431 * L2 cache control register 3: 64GB range, 256KB size,
2432 * enabled, latency 0x1, configured
2434 msr_info->data = 0xbe702111;
2436 case MSR_AMD64_OSVW_ID_LENGTH:
2437 if (!guest_cpuid_has_osvw(vcpu))
2439 msr_info->data = vcpu->arch.osvw.length;
2441 case MSR_AMD64_OSVW_STATUS:
2442 if (!guest_cpuid_has_osvw(vcpu))
2444 msr_info->data = vcpu->arch.osvw.status;
2447 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2448 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2450 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2453 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2460 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2463 * Read or write a bunch of msrs. All parameters are kernel addresses.
2465 * @return number of msrs set successfully.
2467 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2468 struct kvm_msr_entry *entries,
2469 int (*do_msr)(struct kvm_vcpu *vcpu,
2470 unsigned index, u64 *data))
2474 idx = srcu_read_lock(&vcpu->kvm->srcu);
2475 for (i = 0; i < msrs->nmsrs; ++i)
2476 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2478 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2484 * Read or write a bunch of msrs. Parameters are user addresses.
2486 * @return number of msrs set successfully.
2488 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2489 int (*do_msr)(struct kvm_vcpu *vcpu,
2490 unsigned index, u64 *data),
2493 struct kvm_msrs msrs;
2494 struct kvm_msr_entry *entries;
2499 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2503 if (msrs.nmsrs >= MAX_IO_MSRS)
2506 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2507 entries = memdup_user(user_msrs->entries, size);
2508 if (IS_ERR(entries)) {
2509 r = PTR_ERR(entries);
2513 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2518 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2529 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2534 case KVM_CAP_IRQCHIP:
2536 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2537 case KVM_CAP_SET_TSS_ADDR:
2538 case KVM_CAP_EXT_CPUID:
2539 case KVM_CAP_EXT_EMUL_CPUID:
2540 case KVM_CAP_CLOCKSOURCE:
2542 case KVM_CAP_NOP_IO_DELAY:
2543 case KVM_CAP_MP_STATE:
2544 case KVM_CAP_SYNC_MMU:
2545 case KVM_CAP_USER_NMI:
2546 case KVM_CAP_REINJECT_CONTROL:
2547 case KVM_CAP_IRQ_INJECT_STATUS:
2548 case KVM_CAP_IOEVENTFD:
2549 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2551 case KVM_CAP_PIT_STATE2:
2552 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2553 case KVM_CAP_XEN_HVM:
2554 case KVM_CAP_ADJUST_CLOCK:
2555 case KVM_CAP_VCPU_EVENTS:
2556 case KVM_CAP_HYPERV:
2557 case KVM_CAP_HYPERV_VAPIC:
2558 case KVM_CAP_HYPERV_SPIN:
2559 case KVM_CAP_HYPERV_SYNIC:
2560 case KVM_CAP_PCI_SEGMENT:
2561 case KVM_CAP_DEBUGREGS:
2562 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2564 case KVM_CAP_ASYNC_PF:
2565 case KVM_CAP_GET_TSC_KHZ:
2566 case KVM_CAP_KVMCLOCK_CTRL:
2567 case KVM_CAP_READONLY_MEM:
2568 case KVM_CAP_HYPERV_TIME:
2569 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2570 case KVM_CAP_TSC_DEADLINE_TIMER:
2571 case KVM_CAP_ENABLE_CAP_VM:
2572 case KVM_CAP_DISABLE_QUIRKS:
2573 case KVM_CAP_SET_BOOT_CPU_ID:
2574 case KVM_CAP_SPLIT_IRQCHIP:
2575 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2576 case KVM_CAP_ASSIGN_DEV_IRQ:
2577 case KVM_CAP_PCI_2_3:
2581 case KVM_CAP_X86_SMM:
2582 /* SMBASE is usually relocated above 1M on modern chipsets,
2583 * and SMM handlers might indeed rely on 4G segment limits,
2584 * so do not report SMM to be available if real mode is
2585 * emulated via vm86 mode. Still, do not go to great lengths
2586 * to avoid userspace's usage of the feature, because it is a
2587 * fringe case that is not enabled except via specific settings
2588 * of the module parameters.
2590 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2592 case KVM_CAP_COALESCED_MMIO:
2593 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2596 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2598 case KVM_CAP_NR_VCPUS:
2599 r = KVM_SOFT_MAX_VCPUS;
2601 case KVM_CAP_MAX_VCPUS:
2604 case KVM_CAP_NR_MEMSLOTS:
2605 r = KVM_USER_MEM_SLOTS;
2607 case KVM_CAP_PV_MMU: /* obsolete */
2610 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2612 r = iommu_present(&pci_bus_type);
2616 r = KVM_MAX_MCE_BANKS;
2619 r = boot_cpu_has(X86_FEATURE_XSAVE);
2621 case KVM_CAP_TSC_CONTROL:
2622 r = kvm_has_tsc_control;
2632 long kvm_arch_dev_ioctl(struct file *filp,
2633 unsigned int ioctl, unsigned long arg)
2635 void __user *argp = (void __user *)arg;
2639 case KVM_GET_MSR_INDEX_LIST: {
2640 struct kvm_msr_list __user *user_msr_list = argp;
2641 struct kvm_msr_list msr_list;
2645 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2648 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2649 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2652 if (n < msr_list.nmsrs)
2655 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2656 num_msrs_to_save * sizeof(u32)))
2658 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2660 num_emulated_msrs * sizeof(u32)))
2665 case KVM_GET_SUPPORTED_CPUID:
2666 case KVM_GET_EMULATED_CPUID: {
2667 struct kvm_cpuid2 __user *cpuid_arg = argp;
2668 struct kvm_cpuid2 cpuid;
2671 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2674 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2680 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2685 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2688 mce_cap = KVM_MCE_CAP_SUPPORTED;
2690 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2702 static void wbinvd_ipi(void *garbage)
2707 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2709 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2712 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2714 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2717 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2719 /* Address WBINVD may be executed by guest */
2720 if (need_emulate_wbinvd(vcpu)) {
2721 if (kvm_x86_ops->has_wbinvd_exit())
2722 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2723 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2724 smp_call_function_single(vcpu->cpu,
2725 wbinvd_ipi, NULL, 1);
2728 kvm_x86_ops->vcpu_load(vcpu, cpu);
2730 /* Apply any externally detected TSC adjustments (due to suspend) */
2731 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2732 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2733 vcpu->arch.tsc_offset_adjustment = 0;
2734 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2737 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2738 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2739 rdtsc() - vcpu->arch.last_host_tsc;
2741 mark_tsc_unstable("KVM discovered backwards TSC");
2742 if (check_tsc_unstable()) {
2743 u64 offset = kvm_compute_tsc_offset(vcpu,
2744 vcpu->arch.last_guest_tsc);
2745 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2746 vcpu->arch.tsc_catchup = 1;
2749 * On a host with synchronized TSC, there is no need to update
2750 * kvmclock on vcpu->cpu migration
2752 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2753 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2754 if (vcpu->cpu != cpu)
2755 kvm_migrate_timers(vcpu);
2759 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2762 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2764 kvm_x86_ops->vcpu_put(vcpu);
2765 kvm_put_guest_fpu(vcpu);
2766 vcpu->arch.last_host_tsc = rdtsc();
2769 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2770 struct kvm_lapic_state *s)
2772 if (vcpu->arch.apicv_active)
2773 kvm_x86_ops->sync_pir_to_irr(vcpu);
2775 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2780 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2781 struct kvm_lapic_state *s)
2783 kvm_apic_post_state_restore(vcpu, s);
2784 update_cr8_intercept(vcpu);
2789 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2791 return (!lapic_in_kernel(vcpu) ||
2792 kvm_apic_accept_pic_intr(vcpu));
2796 * if userspace requested an interrupt window, check that the
2797 * interrupt window is open.
2799 * No need to exit to userspace if we already have an interrupt queued.
2801 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2803 return kvm_arch_interrupt_allowed(vcpu) &&
2804 !kvm_cpu_has_interrupt(vcpu) &&
2805 !kvm_event_needs_reinjection(vcpu) &&
2806 kvm_cpu_accept_dm_intr(vcpu);
2809 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2810 struct kvm_interrupt *irq)
2812 if (irq->irq >= KVM_NR_INTERRUPTS)
2815 if (!irqchip_in_kernel(vcpu->kvm)) {
2816 kvm_queue_interrupt(vcpu, irq->irq, false);
2817 kvm_make_request(KVM_REQ_EVENT, vcpu);
2822 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2823 * fail for in-kernel 8259.
2825 if (pic_in_kernel(vcpu->kvm))
2828 if (vcpu->arch.pending_external_vector != -1)
2831 vcpu->arch.pending_external_vector = irq->irq;
2832 kvm_make_request(KVM_REQ_EVENT, vcpu);
2836 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2838 kvm_inject_nmi(vcpu);
2843 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2845 kvm_make_request(KVM_REQ_SMI, vcpu);
2850 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2851 struct kvm_tpr_access_ctl *tac)
2855 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2859 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2863 unsigned bank_num = mcg_cap & 0xff, bank;
2866 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2868 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2871 vcpu->arch.mcg_cap = mcg_cap;
2872 /* Init IA32_MCG_CTL to all 1s */
2873 if (mcg_cap & MCG_CTL_P)
2874 vcpu->arch.mcg_ctl = ~(u64)0;
2875 /* Init IA32_MCi_CTL to all 1s */
2876 for (bank = 0; bank < bank_num; bank++)
2877 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2882 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2883 struct kvm_x86_mce *mce)
2885 u64 mcg_cap = vcpu->arch.mcg_cap;
2886 unsigned bank_num = mcg_cap & 0xff;
2887 u64 *banks = vcpu->arch.mce_banks;
2889 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2892 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2893 * reporting is disabled
2895 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2896 vcpu->arch.mcg_ctl != ~(u64)0)
2898 banks += 4 * mce->bank;
2900 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2901 * reporting is disabled for the bank
2903 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2905 if (mce->status & MCI_STATUS_UC) {
2906 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2907 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2908 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2911 if (banks[1] & MCI_STATUS_VAL)
2912 mce->status |= MCI_STATUS_OVER;
2913 banks[2] = mce->addr;
2914 banks[3] = mce->misc;
2915 vcpu->arch.mcg_status = mce->mcg_status;
2916 banks[1] = mce->status;
2917 kvm_queue_exception(vcpu, MC_VECTOR);
2918 } else if (!(banks[1] & MCI_STATUS_VAL)
2919 || !(banks[1] & MCI_STATUS_UC)) {
2920 if (banks[1] & MCI_STATUS_VAL)
2921 mce->status |= MCI_STATUS_OVER;
2922 banks[2] = mce->addr;
2923 banks[3] = mce->misc;
2924 banks[1] = mce->status;
2926 banks[1] |= MCI_STATUS_OVER;
2930 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2931 struct kvm_vcpu_events *events)
2934 events->exception.injected =
2935 vcpu->arch.exception.pending &&
2936 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2937 events->exception.nr = vcpu->arch.exception.nr;
2938 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2939 events->exception.pad = 0;
2940 events->exception.error_code = vcpu->arch.exception.error_code;
2942 events->interrupt.injected =
2943 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2944 events->interrupt.nr = vcpu->arch.interrupt.nr;
2945 events->interrupt.soft = 0;
2946 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2948 events->nmi.injected = vcpu->arch.nmi_injected;
2949 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2950 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2951 events->nmi.pad = 0;
2953 events->sipi_vector = 0; /* never valid when reporting to user space */
2955 events->smi.smm = is_smm(vcpu);
2956 events->smi.pending = vcpu->arch.smi_pending;
2957 events->smi.smm_inside_nmi =
2958 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2959 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2961 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2962 | KVM_VCPUEVENT_VALID_SHADOW
2963 | KVM_VCPUEVENT_VALID_SMM);
2964 memset(&events->reserved, 0, sizeof(events->reserved));
2967 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2968 struct kvm_vcpu_events *events)
2970 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2971 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2972 | KVM_VCPUEVENT_VALID_SHADOW
2973 | KVM_VCPUEVENT_VALID_SMM))
2976 if (events->exception.injected &&
2977 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2981 vcpu->arch.exception.pending = events->exception.injected;
2982 vcpu->arch.exception.nr = events->exception.nr;
2983 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2984 vcpu->arch.exception.error_code = events->exception.error_code;
2986 vcpu->arch.interrupt.pending = events->interrupt.injected;
2987 vcpu->arch.interrupt.nr = events->interrupt.nr;
2988 vcpu->arch.interrupt.soft = events->interrupt.soft;
2989 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2990 kvm_x86_ops->set_interrupt_shadow(vcpu,
2991 events->interrupt.shadow);
2993 vcpu->arch.nmi_injected = events->nmi.injected;
2994 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2995 vcpu->arch.nmi_pending = events->nmi.pending;
2996 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2998 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2999 lapic_in_kernel(vcpu))
3000 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3002 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3003 if (events->smi.smm)
3004 vcpu->arch.hflags |= HF_SMM_MASK;
3006 vcpu->arch.hflags &= ~HF_SMM_MASK;
3007 vcpu->arch.smi_pending = events->smi.pending;
3008 if (events->smi.smm_inside_nmi)
3009 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3011 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3012 if (lapic_in_kernel(vcpu)) {
3013 if (events->smi.latched_init)
3014 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3016 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3020 kvm_make_request(KVM_REQ_EVENT, vcpu);
3025 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3026 struct kvm_debugregs *dbgregs)
3030 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3031 kvm_get_dr(vcpu, 6, &val);
3033 dbgregs->dr7 = vcpu->arch.dr7;
3035 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3038 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3039 struct kvm_debugregs *dbgregs)
3044 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3045 kvm_update_dr0123(vcpu);
3046 vcpu->arch.dr6 = dbgregs->dr6;
3047 kvm_update_dr6(vcpu);
3048 vcpu->arch.dr7 = dbgregs->dr7;
3049 kvm_update_dr7(vcpu);
3054 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3056 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3058 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3059 u64 xstate_bv = xsave->header.xfeatures;
3063 * Copy legacy XSAVE area, to avoid complications with CPUID
3064 * leaves 0 and 1 in the loop below.
3066 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3069 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3072 * Copy each region from the possibly compacted offset to the
3073 * non-compacted offset.
3075 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3077 u64 feature = valid & -valid;
3078 int index = fls64(feature) - 1;
3079 void *src = get_xsave_addr(xsave, feature);
3082 u32 size, offset, ecx, edx;
3083 cpuid_count(XSTATE_CPUID, index,
3084 &size, &offset, &ecx, &edx);
3085 memcpy(dest + offset, src, size);
3092 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3094 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3095 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3099 * Copy legacy XSAVE area, to avoid complications with CPUID
3100 * leaves 0 and 1 in the loop below.
3102 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3104 /* Set XSTATE_BV and possibly XCOMP_BV. */
3105 xsave->header.xfeatures = xstate_bv;
3106 if (boot_cpu_has(X86_FEATURE_XSAVES))
3107 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3110 * Copy each region from the non-compacted offset to the
3111 * possibly compacted offset.
3113 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3115 u64 feature = valid & -valid;
3116 int index = fls64(feature) - 1;
3117 void *dest = get_xsave_addr(xsave, feature);
3120 u32 size, offset, ecx, edx;
3121 cpuid_count(XSTATE_CPUID, index,
3122 &size, &offset, &ecx, &edx);
3123 memcpy(dest, src + offset, size);
3130 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3131 struct kvm_xsave *guest_xsave)
3133 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3134 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3135 fill_xsave((u8 *) guest_xsave->region, vcpu);
3137 memcpy(guest_xsave->region,
3138 &vcpu->arch.guest_fpu.state.fxsave,
3139 sizeof(struct fxregs_state));
3140 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3141 XFEATURE_MASK_FPSSE;
3145 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3146 struct kvm_xsave *guest_xsave)
3149 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3151 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3153 * Here we allow setting states that are not present in
3154 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3155 * with old userspace.
3157 if (xstate_bv & ~kvm_supported_xcr0())
3159 load_xsave(vcpu, (u8 *)guest_xsave->region);
3161 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3163 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3164 guest_xsave->region, sizeof(struct fxregs_state));
3169 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3170 struct kvm_xcrs *guest_xcrs)
3172 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3173 guest_xcrs->nr_xcrs = 0;
3177 guest_xcrs->nr_xcrs = 1;
3178 guest_xcrs->flags = 0;
3179 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3180 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3183 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3184 struct kvm_xcrs *guest_xcrs)
3188 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3191 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3194 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3195 /* Only support XCR0 currently */
3196 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3197 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3198 guest_xcrs->xcrs[i].value);
3207 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3208 * stopped by the hypervisor. This function will be called from the host only.
3209 * EINVAL is returned when the host attempts to set the flag for a guest that
3210 * does not support pv clocks.
3212 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3214 if (!vcpu->arch.pv_time_enabled)
3216 vcpu->arch.pvclock_set_guest_stopped_request = true;
3217 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3221 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3222 struct kvm_enable_cap *cap)
3228 case KVM_CAP_HYPERV_SYNIC:
3229 return kvm_hv_activate_synic(vcpu);
3235 long kvm_arch_vcpu_ioctl(struct file *filp,
3236 unsigned int ioctl, unsigned long arg)
3238 struct kvm_vcpu *vcpu = filp->private_data;
3239 void __user *argp = (void __user *)arg;
3242 struct kvm_lapic_state *lapic;
3243 struct kvm_xsave *xsave;
3244 struct kvm_xcrs *xcrs;
3250 case KVM_GET_LAPIC: {
3252 if (!lapic_in_kernel(vcpu))
3254 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3259 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3263 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3268 case KVM_SET_LAPIC: {
3270 if (!lapic_in_kernel(vcpu))
3272 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3273 if (IS_ERR(u.lapic))
3274 return PTR_ERR(u.lapic);
3276 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3279 case KVM_INTERRUPT: {
3280 struct kvm_interrupt irq;
3283 if (copy_from_user(&irq, argp, sizeof irq))
3285 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3289 r = kvm_vcpu_ioctl_nmi(vcpu);
3293 r = kvm_vcpu_ioctl_smi(vcpu);
3296 case KVM_SET_CPUID: {
3297 struct kvm_cpuid __user *cpuid_arg = argp;
3298 struct kvm_cpuid cpuid;
3301 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3303 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3306 case KVM_SET_CPUID2: {
3307 struct kvm_cpuid2 __user *cpuid_arg = argp;
3308 struct kvm_cpuid2 cpuid;
3311 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3313 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3314 cpuid_arg->entries);
3317 case KVM_GET_CPUID2: {
3318 struct kvm_cpuid2 __user *cpuid_arg = argp;
3319 struct kvm_cpuid2 cpuid;
3322 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3324 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3325 cpuid_arg->entries);
3329 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3335 r = msr_io(vcpu, argp, do_get_msr, 1);
3338 r = msr_io(vcpu, argp, do_set_msr, 0);
3340 case KVM_TPR_ACCESS_REPORTING: {
3341 struct kvm_tpr_access_ctl tac;
3344 if (copy_from_user(&tac, argp, sizeof tac))
3346 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3350 if (copy_to_user(argp, &tac, sizeof tac))
3355 case KVM_SET_VAPIC_ADDR: {
3356 struct kvm_vapic_addr va;
3359 if (!lapic_in_kernel(vcpu))
3362 if (copy_from_user(&va, argp, sizeof va))
3364 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3367 case KVM_X86_SETUP_MCE: {
3371 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3373 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3376 case KVM_X86_SET_MCE: {
3377 struct kvm_x86_mce mce;
3380 if (copy_from_user(&mce, argp, sizeof mce))
3382 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3385 case KVM_GET_VCPU_EVENTS: {
3386 struct kvm_vcpu_events events;
3388 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3391 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3396 case KVM_SET_VCPU_EVENTS: {
3397 struct kvm_vcpu_events events;
3400 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3403 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3406 case KVM_GET_DEBUGREGS: {
3407 struct kvm_debugregs dbgregs;
3409 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3412 if (copy_to_user(argp, &dbgregs,
3413 sizeof(struct kvm_debugregs)))
3418 case KVM_SET_DEBUGREGS: {
3419 struct kvm_debugregs dbgregs;
3422 if (copy_from_user(&dbgregs, argp,
3423 sizeof(struct kvm_debugregs)))
3426 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3429 case KVM_GET_XSAVE: {
3430 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3435 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3438 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3443 case KVM_SET_XSAVE: {
3444 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3445 if (IS_ERR(u.xsave))
3446 return PTR_ERR(u.xsave);
3448 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3451 case KVM_GET_XCRS: {
3452 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3457 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3460 if (copy_to_user(argp, u.xcrs,
3461 sizeof(struct kvm_xcrs)))
3466 case KVM_SET_XCRS: {
3467 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3469 return PTR_ERR(u.xcrs);
3471 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3474 case KVM_SET_TSC_KHZ: {
3478 user_tsc_khz = (u32)arg;
3480 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3483 if (user_tsc_khz == 0)
3484 user_tsc_khz = tsc_khz;
3486 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3491 case KVM_GET_TSC_KHZ: {
3492 r = vcpu->arch.virtual_tsc_khz;
3495 case KVM_KVMCLOCK_CTRL: {
3496 r = kvm_set_guest_paused(vcpu);
3499 case KVM_ENABLE_CAP: {
3500 struct kvm_enable_cap cap;
3503 if (copy_from_user(&cap, argp, sizeof(cap)))
3505 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3516 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3518 return VM_FAULT_SIGBUS;
3521 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3525 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3527 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3531 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3534 kvm->arch.ept_identity_map_addr = ident_addr;
3538 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3539 u32 kvm_nr_mmu_pages)
3541 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3544 mutex_lock(&kvm->slots_lock);
3546 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3547 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3549 mutex_unlock(&kvm->slots_lock);
3553 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3555 return kvm->arch.n_max_mmu_pages;
3558 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3563 switch (chip->chip_id) {
3564 case KVM_IRQCHIP_PIC_MASTER:
3565 memcpy(&chip->chip.pic,
3566 &pic_irqchip(kvm)->pics[0],
3567 sizeof(struct kvm_pic_state));
3569 case KVM_IRQCHIP_PIC_SLAVE:
3570 memcpy(&chip->chip.pic,
3571 &pic_irqchip(kvm)->pics[1],
3572 sizeof(struct kvm_pic_state));
3574 case KVM_IRQCHIP_IOAPIC:
3575 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3584 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3589 switch (chip->chip_id) {
3590 case KVM_IRQCHIP_PIC_MASTER:
3591 spin_lock(&pic_irqchip(kvm)->lock);
3592 memcpy(&pic_irqchip(kvm)->pics[0],
3594 sizeof(struct kvm_pic_state));
3595 spin_unlock(&pic_irqchip(kvm)->lock);
3597 case KVM_IRQCHIP_PIC_SLAVE:
3598 spin_lock(&pic_irqchip(kvm)->lock);
3599 memcpy(&pic_irqchip(kvm)->pics[1],
3601 sizeof(struct kvm_pic_state));
3602 spin_unlock(&pic_irqchip(kvm)->lock);
3604 case KVM_IRQCHIP_IOAPIC:
3605 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3611 kvm_pic_update_irq(pic_irqchip(kvm));
3615 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3617 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3619 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3621 mutex_lock(&kps->lock);
3622 memcpy(ps, &kps->channels, sizeof(*ps));
3623 mutex_unlock(&kps->lock);
3627 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3630 struct kvm_pit *pit = kvm->arch.vpit;
3632 mutex_lock(&pit->pit_state.lock);
3633 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3634 for (i = 0; i < 3; i++)
3635 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3636 mutex_unlock(&pit->pit_state.lock);
3640 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3642 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3643 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3644 sizeof(ps->channels));
3645 ps->flags = kvm->arch.vpit->pit_state.flags;
3646 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3647 memset(&ps->reserved, 0, sizeof(ps->reserved));
3651 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3655 u32 prev_legacy, cur_legacy;
3656 struct kvm_pit *pit = kvm->arch.vpit;
3658 mutex_lock(&pit->pit_state.lock);
3659 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3660 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3661 if (!prev_legacy && cur_legacy)
3663 memcpy(&pit->pit_state.channels, &ps->channels,
3664 sizeof(pit->pit_state.channels));
3665 pit->pit_state.flags = ps->flags;
3666 for (i = 0; i < 3; i++)
3667 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3669 mutex_unlock(&pit->pit_state.lock);
3673 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3674 struct kvm_reinject_control *control)
3676 struct kvm_pit *pit = kvm->arch.vpit;
3681 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3682 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3683 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3685 mutex_lock(&pit->pit_state.lock);
3686 kvm_pit_set_reinject(pit, control->pit_reinject);
3687 mutex_unlock(&pit->pit_state.lock);
3693 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3694 * @kvm: kvm instance
3695 * @log: slot id and address to which we copy the log
3697 * Steps 1-4 below provide general overview of dirty page logging. See
3698 * kvm_get_dirty_log_protect() function description for additional details.
3700 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3701 * always flush the TLB (step 4) even if previous step failed and the dirty
3702 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3703 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3704 * writes will be marked dirty for next log read.
3706 * 1. Take a snapshot of the bit and clear it if needed.
3707 * 2. Write protect the corresponding page.
3708 * 3. Copy the snapshot to the userspace.
3709 * 4. Flush TLB's if needed.
3711 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3713 bool is_dirty = false;
3716 mutex_lock(&kvm->slots_lock);
3719 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3721 if (kvm_x86_ops->flush_log_dirty)
3722 kvm_x86_ops->flush_log_dirty(kvm);
3724 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3727 * All the TLBs can be flushed out of mmu lock, see the comments in
3728 * kvm_mmu_slot_remove_write_access().
3730 lockdep_assert_held(&kvm->slots_lock);
3732 kvm_flush_remote_tlbs(kvm);
3734 mutex_unlock(&kvm->slots_lock);
3738 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3741 if (!irqchip_in_kernel(kvm))
3744 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3745 irq_event->irq, irq_event->level,
3750 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3751 struct kvm_enable_cap *cap)
3759 case KVM_CAP_DISABLE_QUIRKS:
3760 kvm->arch.disabled_quirks = cap->args[0];
3763 case KVM_CAP_SPLIT_IRQCHIP: {
3764 mutex_lock(&kvm->lock);
3766 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3767 goto split_irqchip_unlock;
3769 if (irqchip_in_kernel(kvm))
3770 goto split_irqchip_unlock;
3771 if (atomic_read(&kvm->online_vcpus))
3772 goto split_irqchip_unlock;
3773 r = kvm_setup_empty_irq_routing(kvm);
3775 goto split_irqchip_unlock;
3776 /* Pairs with irqchip_in_kernel. */
3778 kvm->arch.irqchip_split = true;
3779 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3781 split_irqchip_unlock:
3782 mutex_unlock(&kvm->lock);
3792 long kvm_arch_vm_ioctl(struct file *filp,
3793 unsigned int ioctl, unsigned long arg)
3795 struct kvm *kvm = filp->private_data;
3796 void __user *argp = (void __user *)arg;
3799 * This union makes it completely explicit to gcc-3.x
3800 * that these two variables' stack usage should be
3801 * combined, not added together.
3804 struct kvm_pit_state ps;
3805 struct kvm_pit_state2 ps2;
3806 struct kvm_pit_config pit_config;
3810 case KVM_SET_TSS_ADDR:
3811 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3813 case KVM_SET_IDENTITY_MAP_ADDR: {
3817 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3819 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3822 case KVM_SET_NR_MMU_PAGES:
3823 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3825 case KVM_GET_NR_MMU_PAGES:
3826 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3828 case KVM_CREATE_IRQCHIP: {
3829 struct kvm_pic *vpic;
3831 mutex_lock(&kvm->lock);
3834 goto create_irqchip_unlock;
3836 if (atomic_read(&kvm->online_vcpus))
3837 goto create_irqchip_unlock;
3839 vpic = kvm_create_pic(kvm);
3841 r = kvm_ioapic_init(kvm);
3843 mutex_lock(&kvm->slots_lock);
3844 kvm_destroy_pic(vpic);
3845 mutex_unlock(&kvm->slots_lock);
3846 goto create_irqchip_unlock;
3849 goto create_irqchip_unlock;
3850 r = kvm_setup_default_irq_routing(kvm);
3852 mutex_lock(&kvm->slots_lock);
3853 mutex_lock(&kvm->irq_lock);
3854 kvm_ioapic_destroy(kvm);
3855 kvm_destroy_pic(vpic);
3856 mutex_unlock(&kvm->irq_lock);
3857 mutex_unlock(&kvm->slots_lock);
3858 goto create_irqchip_unlock;
3860 /* Write kvm->irq_routing before kvm->arch.vpic. */
3862 kvm->arch.vpic = vpic;
3863 create_irqchip_unlock:
3864 mutex_unlock(&kvm->lock);
3867 case KVM_CREATE_PIT:
3868 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3870 case KVM_CREATE_PIT2:
3872 if (copy_from_user(&u.pit_config, argp,
3873 sizeof(struct kvm_pit_config)))
3876 mutex_lock(&kvm->slots_lock);
3879 goto create_pit_unlock;
3881 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3885 mutex_unlock(&kvm->slots_lock);
3887 case KVM_GET_IRQCHIP: {
3888 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3889 struct kvm_irqchip *chip;
3891 chip = memdup_user(argp, sizeof(*chip));
3898 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3899 goto get_irqchip_out;
3900 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3902 goto get_irqchip_out;
3904 if (copy_to_user(argp, chip, sizeof *chip))
3905 goto get_irqchip_out;
3911 case KVM_SET_IRQCHIP: {
3912 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3913 struct kvm_irqchip *chip;
3915 chip = memdup_user(argp, sizeof(*chip));
3922 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3923 goto set_irqchip_out;
3924 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3926 goto set_irqchip_out;
3934 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3937 if (!kvm->arch.vpit)
3939 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3943 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3950 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3953 if (!kvm->arch.vpit)
3955 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3958 case KVM_GET_PIT2: {
3960 if (!kvm->arch.vpit)
3962 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3966 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3971 case KVM_SET_PIT2: {
3973 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3976 if (!kvm->arch.vpit)
3978 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3981 case KVM_REINJECT_CONTROL: {
3982 struct kvm_reinject_control control;
3984 if (copy_from_user(&control, argp, sizeof(control)))
3986 r = kvm_vm_ioctl_reinject(kvm, &control);
3989 case KVM_SET_BOOT_CPU_ID:
3991 mutex_lock(&kvm->lock);
3992 if (atomic_read(&kvm->online_vcpus) != 0)
3995 kvm->arch.bsp_vcpu_id = arg;
3996 mutex_unlock(&kvm->lock);
3998 case KVM_XEN_HVM_CONFIG: {
4000 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4001 sizeof(struct kvm_xen_hvm_config)))
4004 if (kvm->arch.xen_hvm_config.flags)
4009 case KVM_SET_CLOCK: {
4010 struct kvm_clock_data user_ns;
4015 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4023 local_irq_disable();
4024 now_ns = get_kernel_ns();
4025 delta = user_ns.clock - now_ns;
4027 kvm->arch.kvmclock_offset = delta;
4028 kvm_gen_update_masterclock(kvm);
4031 case KVM_GET_CLOCK: {
4032 struct kvm_clock_data user_ns;
4035 local_irq_disable();
4036 now_ns = get_kernel_ns();
4037 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4040 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4043 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4048 case KVM_ENABLE_CAP: {
4049 struct kvm_enable_cap cap;
4052 if (copy_from_user(&cap, argp, sizeof(cap)))
4054 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4058 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4064 static void kvm_init_msr_list(void)
4069 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4070 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4074 * Even MSRs that are valid in the host may not be exposed
4075 * to the guests in some cases.
4077 switch (msrs_to_save[i]) {
4078 case MSR_IA32_BNDCFGS:
4079 if (!kvm_x86_ops->mpx_supported())
4083 if (!kvm_x86_ops->rdtscp_supported())
4091 msrs_to_save[j] = msrs_to_save[i];
4094 num_msrs_to_save = j;
4096 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4097 switch (emulated_msrs[i]) {
4098 case MSR_IA32_SMBASE:
4099 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4107 emulated_msrs[j] = emulated_msrs[i];
4110 num_emulated_msrs = j;
4113 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4121 if (!(lapic_in_kernel(vcpu) &&
4122 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4123 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4134 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4141 if (!(lapic_in_kernel(vcpu) &&
4142 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4144 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4146 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4156 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4157 struct kvm_segment *var, int seg)
4159 kvm_x86_ops->set_segment(vcpu, var, seg);
4162 void kvm_get_segment(struct kvm_vcpu *vcpu,
4163 struct kvm_segment *var, int seg)
4165 kvm_x86_ops->get_segment(vcpu, var, seg);
4168 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4169 struct x86_exception *exception)
4173 BUG_ON(!mmu_is_nested(vcpu));
4175 /* NPT walks are always user-walks */
4176 access |= PFERR_USER_MASK;
4177 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4182 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4183 struct x86_exception *exception)
4185 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4186 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4189 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4190 struct x86_exception *exception)
4192 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4193 access |= PFERR_FETCH_MASK;
4194 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4197 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4198 struct x86_exception *exception)
4200 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4201 access |= PFERR_WRITE_MASK;
4202 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4205 /* uses this to access any guest's mapped memory without checking CPL */
4206 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4207 struct x86_exception *exception)
4209 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4212 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4213 struct kvm_vcpu *vcpu, u32 access,
4214 struct x86_exception *exception)
4217 int r = X86EMUL_CONTINUE;
4220 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4222 unsigned offset = addr & (PAGE_SIZE-1);
4223 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4226 if (gpa == UNMAPPED_GVA)
4227 return X86EMUL_PROPAGATE_FAULT;
4228 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4231 r = X86EMUL_IO_NEEDED;
4243 /* used for instruction fetching */
4244 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4245 gva_t addr, void *val, unsigned int bytes,
4246 struct x86_exception *exception)
4248 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4249 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4253 /* Inline kvm_read_guest_virt_helper for speed. */
4254 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4256 if (unlikely(gpa == UNMAPPED_GVA))
4257 return X86EMUL_PROPAGATE_FAULT;
4259 offset = addr & (PAGE_SIZE-1);
4260 if (WARN_ON(offset + bytes > PAGE_SIZE))
4261 bytes = (unsigned)PAGE_SIZE - offset;
4262 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4264 if (unlikely(ret < 0))
4265 return X86EMUL_IO_NEEDED;
4267 return X86EMUL_CONTINUE;
4270 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4271 gva_t addr, void *val, unsigned int bytes,
4272 struct x86_exception *exception)
4274 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4275 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4277 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4280 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4282 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4283 gva_t addr, void *val, unsigned int bytes,
4284 struct x86_exception *exception)
4286 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4287 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4290 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4291 unsigned long addr, void *val, unsigned int bytes)
4293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4294 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4296 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4299 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4300 gva_t addr, void *val,
4302 struct x86_exception *exception)
4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4306 int r = X86EMUL_CONTINUE;
4309 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4312 unsigned offset = addr & (PAGE_SIZE-1);
4313 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4316 if (gpa == UNMAPPED_GVA)
4317 return X86EMUL_PROPAGATE_FAULT;
4318 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4320 r = X86EMUL_IO_NEEDED;
4331 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4333 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4334 gpa_t *gpa, struct x86_exception *exception,
4337 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4338 | (write ? PFERR_WRITE_MASK : 0);
4341 * currently PKRU is only applied to ept enabled guest so
4342 * there is no pkey in EPT page table for L1 guest or EPT
4343 * shadow page table for L2 guest.
4345 if (vcpu_match_mmio_gva(vcpu, gva)
4346 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4347 vcpu->arch.access, 0, access)) {
4348 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4349 (gva & (PAGE_SIZE - 1));
4350 trace_vcpu_match_mmio(gva, *gpa, write, false);
4354 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4356 if (*gpa == UNMAPPED_GVA)
4359 /* For APIC access vmexit */
4360 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4363 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4364 trace_vcpu_match_mmio(gva, *gpa, write, true);
4371 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4372 const void *val, int bytes)
4376 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4379 kvm_page_track_write(vcpu, gpa, val, bytes);
4383 struct read_write_emulator_ops {
4384 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4386 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4387 void *val, int bytes);
4388 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4389 int bytes, void *val);
4390 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4391 void *val, int bytes);
4395 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4397 if (vcpu->mmio_read_completed) {
4398 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4399 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4400 vcpu->mmio_read_completed = 0;
4407 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes)
4410 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4413 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4414 void *val, int bytes)
4416 return emulator_write_phys(vcpu, gpa, val, bytes);
4419 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4421 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4422 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4425 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4426 void *val, int bytes)
4428 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4429 return X86EMUL_IO_NEEDED;
4432 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4433 void *val, int bytes)
4435 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4437 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4438 return X86EMUL_CONTINUE;
4441 static const struct read_write_emulator_ops read_emultor = {
4442 .read_write_prepare = read_prepare,
4443 .read_write_emulate = read_emulate,
4444 .read_write_mmio = vcpu_mmio_read,
4445 .read_write_exit_mmio = read_exit_mmio,
4448 static const struct read_write_emulator_ops write_emultor = {
4449 .read_write_emulate = write_emulate,
4450 .read_write_mmio = write_mmio,
4451 .read_write_exit_mmio = write_exit_mmio,
4455 static int emulator_read_write_onepage(unsigned long addr, void *val,
4457 struct x86_exception *exception,
4458 struct kvm_vcpu *vcpu,
4459 const struct read_write_emulator_ops *ops)
4463 bool write = ops->write;
4464 struct kvm_mmio_fragment *frag;
4466 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4469 return X86EMUL_PROPAGATE_FAULT;
4471 /* For APIC access vmexit */
4475 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4476 return X86EMUL_CONTINUE;
4480 * Is this MMIO handled locally?
4482 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4483 if (handled == bytes)
4484 return X86EMUL_CONTINUE;
4490 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4491 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4495 return X86EMUL_CONTINUE;
4498 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4500 void *val, unsigned int bytes,
4501 struct x86_exception *exception,
4502 const struct read_write_emulator_ops *ops)
4504 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4508 if (ops->read_write_prepare &&
4509 ops->read_write_prepare(vcpu, val, bytes))
4510 return X86EMUL_CONTINUE;
4512 vcpu->mmio_nr_fragments = 0;
4514 /* Crossing a page boundary? */
4515 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4518 now = -addr & ~PAGE_MASK;
4519 rc = emulator_read_write_onepage(addr, val, now, exception,
4522 if (rc != X86EMUL_CONTINUE)
4525 if (ctxt->mode != X86EMUL_MODE_PROT64)
4531 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4533 if (rc != X86EMUL_CONTINUE)
4536 if (!vcpu->mmio_nr_fragments)
4539 gpa = vcpu->mmio_fragments[0].gpa;
4541 vcpu->mmio_needed = 1;
4542 vcpu->mmio_cur_fragment = 0;
4544 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4545 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4546 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4547 vcpu->run->mmio.phys_addr = gpa;
4549 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4552 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4556 struct x86_exception *exception)
4558 return emulator_read_write(ctxt, addr, val, bytes,
4559 exception, &read_emultor);
4562 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4566 struct x86_exception *exception)
4568 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4569 exception, &write_emultor);
4572 #define CMPXCHG_TYPE(t, ptr, old, new) \
4573 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4575 #ifdef CONFIG_X86_64
4576 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4578 # define CMPXCHG64(ptr, old, new) \
4579 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4582 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4587 struct x86_exception *exception)
4589 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4595 /* guests cmpxchg8b have to be emulated atomically */
4596 if (bytes > 8 || (bytes & (bytes - 1)))
4599 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4601 if (gpa == UNMAPPED_GVA ||
4602 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4605 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4608 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4609 if (is_error_page(page))
4612 kaddr = kmap_atomic(page);
4613 kaddr += offset_in_page(gpa);
4616 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4619 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4622 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4625 exchanged = CMPXCHG64(kaddr, old, new);
4630 kunmap_atomic(kaddr);
4631 kvm_release_page_dirty(page);
4634 return X86EMUL_CMPXCHG_FAILED;
4636 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4637 kvm_page_track_write(vcpu, gpa, new, bytes);
4639 return X86EMUL_CONTINUE;
4642 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4644 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4647 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4649 /* TODO: String I/O for in kernel device */
4652 if (vcpu->arch.pio.in)
4653 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4654 vcpu->arch.pio.size, pd);
4656 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4657 vcpu->arch.pio.port, vcpu->arch.pio.size,
4662 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4663 unsigned short port, void *val,
4664 unsigned int count, bool in)
4666 vcpu->arch.pio.port = port;
4667 vcpu->arch.pio.in = in;
4668 vcpu->arch.pio.count = count;
4669 vcpu->arch.pio.size = size;
4671 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4672 vcpu->arch.pio.count = 0;
4676 vcpu->run->exit_reason = KVM_EXIT_IO;
4677 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4678 vcpu->run->io.size = size;
4679 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4680 vcpu->run->io.count = count;
4681 vcpu->run->io.port = port;
4686 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4687 int size, unsigned short port, void *val,
4690 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4693 if (vcpu->arch.pio.count)
4696 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4699 memcpy(val, vcpu->arch.pio_data, size * count);
4700 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4701 vcpu->arch.pio.count = 0;
4708 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4709 int size, unsigned short port,
4710 const void *val, unsigned int count)
4712 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4714 memcpy(vcpu->arch.pio_data, val, size * count);
4715 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4716 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4719 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4721 return kvm_x86_ops->get_segment_base(vcpu, seg);
4724 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4726 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4729 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4731 if (!need_emulate_wbinvd(vcpu))
4732 return X86EMUL_CONTINUE;
4734 if (kvm_x86_ops->has_wbinvd_exit()) {
4735 int cpu = get_cpu();
4737 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4738 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4739 wbinvd_ipi, NULL, 1);
4741 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4744 return X86EMUL_CONTINUE;
4747 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4749 kvm_x86_ops->skip_emulated_instruction(vcpu);
4750 return kvm_emulate_wbinvd_noskip(vcpu);
4752 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4756 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4758 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4761 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4762 unsigned long *dest)
4764 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4767 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4768 unsigned long value)
4771 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4774 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4776 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4779 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4782 unsigned long value;
4786 value = kvm_read_cr0(vcpu);
4789 value = vcpu->arch.cr2;
4792 value = kvm_read_cr3(vcpu);
4795 value = kvm_read_cr4(vcpu);
4798 value = kvm_get_cr8(vcpu);
4801 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4808 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4810 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4815 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4818 vcpu->arch.cr2 = val;
4821 res = kvm_set_cr3(vcpu, val);
4824 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4827 res = kvm_set_cr8(vcpu, val);
4830 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4837 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4839 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4842 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4844 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4847 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4849 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4852 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4854 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4857 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4859 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4862 static unsigned long emulator_get_cached_segment_base(
4863 struct x86_emulate_ctxt *ctxt, int seg)
4865 return get_segment_base(emul_to_vcpu(ctxt), seg);
4868 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4869 struct desc_struct *desc, u32 *base3,
4872 struct kvm_segment var;
4874 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4875 *selector = var.selector;
4878 memset(desc, 0, sizeof(*desc));
4884 set_desc_limit(desc, var.limit);
4885 set_desc_base(desc, (unsigned long)var.base);
4886 #ifdef CONFIG_X86_64
4888 *base3 = var.base >> 32;
4890 desc->type = var.type;
4892 desc->dpl = var.dpl;
4893 desc->p = var.present;
4894 desc->avl = var.avl;
4902 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4903 struct desc_struct *desc, u32 base3,
4906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4907 struct kvm_segment var;
4909 var.selector = selector;
4910 var.base = get_desc_base(desc);
4911 #ifdef CONFIG_X86_64
4912 var.base |= ((u64)base3) << 32;
4914 var.limit = get_desc_limit(desc);
4916 var.limit = (var.limit << 12) | 0xfff;
4917 var.type = desc->type;
4918 var.dpl = desc->dpl;
4923 var.avl = desc->avl;
4924 var.present = desc->p;
4925 var.unusable = !var.present;
4928 kvm_set_segment(vcpu, &var, seg);
4932 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4933 u32 msr_index, u64 *pdata)
4935 struct msr_data msr;
4938 msr.index = msr_index;
4939 msr.host_initiated = false;
4940 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4948 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4949 u32 msr_index, u64 data)
4951 struct msr_data msr;
4954 msr.index = msr_index;
4955 msr.host_initiated = false;
4956 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4959 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4961 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4963 return vcpu->arch.smbase;
4966 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4968 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4970 vcpu->arch.smbase = smbase;
4973 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4976 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4979 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4980 u32 pmc, u64 *pdata)
4982 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4985 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4987 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4990 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4993 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4995 * CR0.TS may reference the host fpu state, not the guest fpu state,
4996 * so it may be clear at this point.
5001 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5006 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5007 struct x86_instruction_info *info,
5008 enum x86_intercept_stage stage)
5010 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5013 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5014 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5016 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5019 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5021 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5024 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5026 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5029 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5031 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5034 static const struct x86_emulate_ops emulate_ops = {
5035 .read_gpr = emulator_read_gpr,
5036 .write_gpr = emulator_write_gpr,
5037 .read_std = kvm_read_guest_virt_system,
5038 .write_std = kvm_write_guest_virt_system,
5039 .read_phys = kvm_read_guest_phys_system,
5040 .fetch = kvm_fetch_guest_virt,
5041 .read_emulated = emulator_read_emulated,
5042 .write_emulated = emulator_write_emulated,
5043 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5044 .invlpg = emulator_invlpg,
5045 .pio_in_emulated = emulator_pio_in_emulated,
5046 .pio_out_emulated = emulator_pio_out_emulated,
5047 .get_segment = emulator_get_segment,
5048 .set_segment = emulator_set_segment,
5049 .get_cached_segment_base = emulator_get_cached_segment_base,
5050 .get_gdt = emulator_get_gdt,
5051 .get_idt = emulator_get_idt,
5052 .set_gdt = emulator_set_gdt,
5053 .set_idt = emulator_set_idt,
5054 .get_cr = emulator_get_cr,
5055 .set_cr = emulator_set_cr,
5056 .cpl = emulator_get_cpl,
5057 .get_dr = emulator_get_dr,
5058 .set_dr = emulator_set_dr,
5059 .get_smbase = emulator_get_smbase,
5060 .set_smbase = emulator_set_smbase,
5061 .set_msr = emulator_set_msr,
5062 .get_msr = emulator_get_msr,
5063 .check_pmc = emulator_check_pmc,
5064 .read_pmc = emulator_read_pmc,
5065 .halt = emulator_halt,
5066 .wbinvd = emulator_wbinvd,
5067 .fix_hypercall = emulator_fix_hypercall,
5068 .get_fpu = emulator_get_fpu,
5069 .put_fpu = emulator_put_fpu,
5070 .intercept = emulator_intercept,
5071 .get_cpuid = emulator_get_cpuid,
5072 .set_nmi_mask = emulator_set_nmi_mask,
5075 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5077 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5079 * an sti; sti; sequence only disable interrupts for the first
5080 * instruction. So, if the last instruction, be it emulated or
5081 * not, left the system with the INT_STI flag enabled, it
5082 * means that the last instruction is an sti. We should not
5083 * leave the flag on in this case. The same goes for mov ss
5085 if (int_shadow & mask)
5087 if (unlikely(int_shadow || mask)) {
5088 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5090 kvm_make_request(KVM_REQ_EVENT, vcpu);
5094 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5096 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5097 if (ctxt->exception.vector == PF_VECTOR)
5098 return kvm_propagate_fault(vcpu, &ctxt->exception);
5100 if (ctxt->exception.error_code_valid)
5101 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5102 ctxt->exception.error_code);
5104 kvm_queue_exception(vcpu, ctxt->exception.vector);
5108 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5110 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5113 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5115 ctxt->eflags = kvm_get_rflags(vcpu);
5116 ctxt->eip = kvm_rip_read(vcpu);
5117 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5118 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5119 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5120 cs_db ? X86EMUL_MODE_PROT32 :
5121 X86EMUL_MODE_PROT16;
5122 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5123 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5124 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5125 ctxt->emul_flags = vcpu->arch.hflags;
5127 init_decode_cache(ctxt);
5128 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5131 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5133 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5136 init_emulate_ctxt(vcpu);
5140 ctxt->_eip = ctxt->eip + inc_eip;
5141 ret = emulate_int_real(ctxt, irq);
5143 if (ret != X86EMUL_CONTINUE)
5144 return EMULATE_FAIL;
5146 ctxt->eip = ctxt->_eip;
5147 kvm_rip_write(vcpu, ctxt->eip);
5148 kvm_set_rflags(vcpu, ctxt->eflags);
5150 if (irq == NMI_VECTOR)
5151 vcpu->arch.nmi_pending = 0;
5153 vcpu->arch.interrupt.pending = false;
5155 return EMULATE_DONE;
5157 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5159 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5161 int r = EMULATE_DONE;
5163 ++vcpu->stat.insn_emulation_fail;
5164 trace_kvm_emulate_insn_failed(vcpu);
5165 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5166 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5167 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5168 vcpu->run->internal.ndata = 0;
5171 kvm_queue_exception(vcpu, UD_VECTOR);
5176 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5177 bool write_fault_to_shadow_pgtable,
5183 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5186 if (!vcpu->arch.mmu.direct_map) {
5188 * Write permission should be allowed since only
5189 * write access need to be emulated.
5191 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5194 * If the mapping is invalid in guest, let cpu retry
5195 * it to generate fault.
5197 if (gpa == UNMAPPED_GVA)
5202 * Do not retry the unhandleable instruction if it faults on the
5203 * readonly host memory, otherwise it will goto a infinite loop:
5204 * retry instruction -> write #PF -> emulation fail -> retry
5205 * instruction -> ...
5207 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5210 * If the instruction failed on the error pfn, it can not be fixed,
5211 * report the error to userspace.
5213 if (is_error_noslot_pfn(pfn))
5216 kvm_release_pfn_clean(pfn);
5218 /* The instructions are well-emulated on direct mmu. */
5219 if (vcpu->arch.mmu.direct_map) {
5220 unsigned int indirect_shadow_pages;
5222 spin_lock(&vcpu->kvm->mmu_lock);
5223 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5224 spin_unlock(&vcpu->kvm->mmu_lock);
5226 if (indirect_shadow_pages)
5227 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5233 * if emulation was due to access to shadowed page table
5234 * and it failed try to unshadow page and re-enter the
5235 * guest to let CPU execute the instruction.
5237 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5240 * If the access faults on its page table, it can not
5241 * be fixed by unprotecting shadow page and it should
5242 * be reported to userspace.
5244 return !write_fault_to_shadow_pgtable;
5247 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5248 unsigned long cr2, int emulation_type)
5250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5251 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5253 last_retry_eip = vcpu->arch.last_retry_eip;
5254 last_retry_addr = vcpu->arch.last_retry_addr;
5257 * If the emulation is caused by #PF and it is non-page_table
5258 * writing instruction, it means the VM-EXIT is caused by shadow
5259 * page protected, we can zap the shadow page and retry this
5260 * instruction directly.
5262 * Note: if the guest uses a non-page-table modifying instruction
5263 * on the PDE that points to the instruction, then we will unmap
5264 * the instruction and go to an infinite loop. So, we cache the
5265 * last retried eip and the last fault address, if we meet the eip
5266 * and the address again, we can break out of the potential infinite
5269 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5271 if (!(emulation_type & EMULTYPE_RETRY))
5274 if (x86_page_table_writing_insn(ctxt))
5277 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5280 vcpu->arch.last_retry_eip = ctxt->eip;
5281 vcpu->arch.last_retry_addr = cr2;
5283 if (!vcpu->arch.mmu.direct_map)
5284 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5286 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5291 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5292 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5294 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5296 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5297 /* This is a good place to trace that we are exiting SMM. */
5298 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5300 if (unlikely(vcpu->arch.smi_pending)) {
5301 kvm_make_request(KVM_REQ_SMI, vcpu);
5302 vcpu->arch.smi_pending = 0;
5304 /* Process a latched INIT, if any. */
5305 kvm_make_request(KVM_REQ_EVENT, vcpu);
5309 kvm_mmu_reset_context(vcpu);
5312 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5314 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5316 vcpu->arch.hflags = emul_flags;
5318 if (changed & HF_SMM_MASK)
5319 kvm_smm_changed(vcpu);
5322 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5331 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5332 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5337 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5339 struct kvm_run *kvm_run = vcpu->run;
5342 * rflags is the old, "raw" value of the flags. The new value has
5343 * not been saved yet.
5345 * This is correct even for TF set by the guest, because "the
5346 * processor will not generate this exception after the instruction
5347 * that sets the TF flag".
5349 if (unlikely(rflags & X86_EFLAGS_TF)) {
5350 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5351 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5353 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5354 kvm_run->debug.arch.exception = DB_VECTOR;
5355 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5356 *r = EMULATE_USER_EXIT;
5358 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5360 * "Certain debug exceptions may clear bit 0-3. The
5361 * remaining contents of the DR6 register are never
5362 * cleared by the processor".
5364 vcpu->arch.dr6 &= ~15;
5365 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5366 kvm_queue_exception(vcpu, DB_VECTOR);
5371 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5373 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5374 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5375 struct kvm_run *kvm_run = vcpu->run;
5376 unsigned long eip = kvm_get_linear_rip(vcpu);
5377 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5378 vcpu->arch.guest_debug_dr7,
5382 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5383 kvm_run->debug.arch.pc = eip;
5384 kvm_run->debug.arch.exception = DB_VECTOR;
5385 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5386 *r = EMULATE_USER_EXIT;
5391 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5392 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5393 unsigned long eip = kvm_get_linear_rip(vcpu);
5394 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5399 vcpu->arch.dr6 &= ~15;
5400 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5401 kvm_queue_exception(vcpu, DB_VECTOR);
5410 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5417 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5418 bool writeback = true;
5419 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5422 * Clear write_fault_to_shadow_pgtable here to ensure it is
5425 vcpu->arch.write_fault_to_shadow_pgtable = false;
5426 kvm_clear_exception_queue(vcpu);
5428 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5429 init_emulate_ctxt(vcpu);
5432 * We will reenter on the same instruction since
5433 * we do not set complete_userspace_io. This does not
5434 * handle watchpoints yet, those would be handled in
5437 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5440 ctxt->interruptibility = 0;
5441 ctxt->have_exception = false;
5442 ctxt->exception.vector = -1;
5443 ctxt->perm_ok = false;
5445 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5447 r = x86_decode_insn(ctxt, insn, insn_len);
5449 trace_kvm_emulate_insn_start(vcpu);
5450 ++vcpu->stat.insn_emulation;
5451 if (r != EMULATION_OK) {
5452 if (emulation_type & EMULTYPE_TRAP_UD)
5453 return EMULATE_FAIL;
5454 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5456 return EMULATE_DONE;
5457 if (emulation_type & EMULTYPE_SKIP)
5458 return EMULATE_FAIL;
5459 return handle_emulation_failure(vcpu);
5463 if (emulation_type & EMULTYPE_SKIP) {
5464 kvm_rip_write(vcpu, ctxt->_eip);
5465 if (ctxt->eflags & X86_EFLAGS_RF)
5466 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5467 return EMULATE_DONE;
5470 if (retry_instruction(ctxt, cr2, emulation_type))
5471 return EMULATE_DONE;
5473 /* this is needed for vmware backdoor interface to work since it
5474 changes registers values during IO operation */
5475 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5476 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5477 emulator_invalidate_register_cache(ctxt);
5481 r = x86_emulate_insn(ctxt);
5483 if (r == EMULATION_INTERCEPTED)
5484 return EMULATE_DONE;
5486 if (r == EMULATION_FAILED) {
5487 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5489 return EMULATE_DONE;
5491 return handle_emulation_failure(vcpu);
5494 if (ctxt->have_exception) {
5496 if (inject_emulated_exception(vcpu))
5498 } else if (vcpu->arch.pio.count) {
5499 if (!vcpu->arch.pio.in) {
5500 /* FIXME: return into emulator if single-stepping. */
5501 vcpu->arch.pio.count = 0;
5504 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5506 r = EMULATE_USER_EXIT;
5507 } else if (vcpu->mmio_needed) {
5508 if (!vcpu->mmio_is_write)
5510 r = EMULATE_USER_EXIT;
5511 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5512 } else if (r == EMULATION_RESTART)
5518 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5519 toggle_interruptibility(vcpu, ctxt->interruptibility);
5520 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5521 if (vcpu->arch.hflags != ctxt->emul_flags)
5522 kvm_set_hflags(vcpu, ctxt->emul_flags);
5523 kvm_rip_write(vcpu, ctxt->eip);
5524 if (r == EMULATE_DONE)
5525 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5526 if (!ctxt->have_exception ||
5527 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5528 __kvm_set_rflags(vcpu, ctxt->eflags);
5531 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5532 * do nothing, and it will be requested again as soon as
5533 * the shadow expires. But we still need to check here,
5534 * because POPF has no interrupt shadow.
5536 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5537 kvm_make_request(KVM_REQ_EVENT, vcpu);
5539 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5543 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5545 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5547 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5548 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5549 size, port, &val, 1);
5550 /* do not return to emulator after return from userspace */
5551 vcpu->arch.pio.count = 0;
5554 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5556 static void tsc_bad(void *info)
5558 __this_cpu_write(cpu_tsc_khz, 0);
5561 static void tsc_khz_changed(void *data)
5563 struct cpufreq_freqs *freq = data;
5564 unsigned long khz = 0;
5568 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5569 khz = cpufreq_quick_get(raw_smp_processor_id());
5572 __this_cpu_write(cpu_tsc_khz, khz);
5575 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5578 struct cpufreq_freqs *freq = data;
5580 struct kvm_vcpu *vcpu;
5581 int i, send_ipi = 0;
5584 * We allow guests to temporarily run on slowing clocks,
5585 * provided we notify them after, or to run on accelerating
5586 * clocks, provided we notify them before. Thus time never
5589 * However, we have a problem. We can't atomically update
5590 * the frequency of a given CPU from this function; it is
5591 * merely a notifier, which can be called from any CPU.
5592 * Changing the TSC frequency at arbitrary points in time
5593 * requires a recomputation of local variables related to
5594 * the TSC for each VCPU. We must flag these local variables
5595 * to be updated and be sure the update takes place with the
5596 * new frequency before any guests proceed.
5598 * Unfortunately, the combination of hotplug CPU and frequency
5599 * change creates an intractable locking scenario; the order
5600 * of when these callouts happen is undefined with respect to
5601 * CPU hotplug, and they can race with each other. As such,
5602 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5603 * undefined; you can actually have a CPU frequency change take
5604 * place in between the computation of X and the setting of the
5605 * variable. To protect against this problem, all updates of
5606 * the per_cpu tsc_khz variable are done in an interrupt
5607 * protected IPI, and all callers wishing to update the value
5608 * must wait for a synchronous IPI to complete (which is trivial
5609 * if the caller is on the CPU already). This establishes the
5610 * necessary total order on variable updates.
5612 * Note that because a guest time update may take place
5613 * anytime after the setting of the VCPU's request bit, the
5614 * correct TSC value must be set before the request. However,
5615 * to ensure the update actually makes it to any guest which
5616 * starts running in hardware virtualization between the set
5617 * and the acquisition of the spinlock, we must also ping the
5618 * CPU after setting the request bit.
5622 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5624 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5627 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5629 spin_lock(&kvm_lock);
5630 list_for_each_entry(kvm, &vm_list, vm_list) {
5631 kvm_for_each_vcpu(i, vcpu, kvm) {
5632 if (vcpu->cpu != freq->cpu)
5634 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5635 if (vcpu->cpu != smp_processor_id())
5639 spin_unlock(&kvm_lock);
5641 if (freq->old < freq->new && send_ipi) {
5643 * We upscale the frequency. Must make the guest
5644 * doesn't see old kvmclock values while running with
5645 * the new frequency, otherwise we risk the guest sees
5646 * time go backwards.
5648 * In case we update the frequency for another cpu
5649 * (which might be in guest context) send an interrupt
5650 * to kick the cpu out of guest context. Next time
5651 * guest context is entered kvmclock will be updated,
5652 * so the guest will not see stale values.
5654 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5659 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5660 .notifier_call = kvmclock_cpufreq_notifier
5663 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5664 unsigned long action, void *hcpu)
5666 unsigned int cpu = (unsigned long)hcpu;
5670 case CPU_DOWN_FAILED:
5671 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5673 case CPU_DOWN_PREPARE:
5674 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5680 static struct notifier_block kvmclock_cpu_notifier_block = {
5681 .notifier_call = kvmclock_cpu_notifier,
5682 .priority = -INT_MAX
5685 static void kvm_timer_init(void)
5689 max_tsc_khz = tsc_khz;
5691 cpu_notifier_register_begin();
5692 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5693 #ifdef CONFIG_CPU_FREQ
5694 struct cpufreq_policy policy;
5695 memset(&policy, 0, sizeof(policy));
5697 cpufreq_get_policy(&policy, cpu);
5698 if (policy.cpuinfo.max_freq)
5699 max_tsc_khz = policy.cpuinfo.max_freq;
5702 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5703 CPUFREQ_TRANSITION_NOTIFIER);
5705 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5706 for_each_online_cpu(cpu)
5707 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5709 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5710 cpu_notifier_register_done();
5714 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5716 int kvm_is_in_guest(void)
5718 return __this_cpu_read(current_vcpu) != NULL;
5721 static int kvm_is_user_mode(void)
5725 if (__this_cpu_read(current_vcpu))
5726 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5728 return user_mode != 0;
5731 static unsigned long kvm_get_guest_ip(void)
5733 unsigned long ip = 0;
5735 if (__this_cpu_read(current_vcpu))
5736 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5741 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5742 .is_in_guest = kvm_is_in_guest,
5743 .is_user_mode = kvm_is_user_mode,
5744 .get_guest_ip = kvm_get_guest_ip,
5747 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5749 __this_cpu_write(current_vcpu, vcpu);
5751 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5753 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5755 __this_cpu_write(current_vcpu, NULL);
5757 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5759 static void kvm_set_mmio_spte_mask(void)
5762 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5765 * Set the reserved bits and the present bit of an paging-structure
5766 * entry to generate page fault with PFER.RSV = 1.
5768 /* Mask the reserved physical address bits. */
5769 mask = rsvd_bits(maxphyaddr, 51);
5771 /* Bit 62 is always reserved for 32bit host. */
5772 mask |= 0x3ull << 62;
5774 /* Set the present bit. */
5777 #ifdef CONFIG_X86_64
5779 * If reserved bit is not supported, clear the present bit to disable
5782 if (maxphyaddr == 52)
5786 kvm_mmu_set_mmio_spte_mask(mask);
5789 #ifdef CONFIG_X86_64
5790 static void pvclock_gtod_update_fn(struct work_struct *work)
5794 struct kvm_vcpu *vcpu;
5797 spin_lock(&kvm_lock);
5798 list_for_each_entry(kvm, &vm_list, vm_list)
5799 kvm_for_each_vcpu(i, vcpu, kvm)
5800 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5801 atomic_set(&kvm_guest_has_master_clock, 0);
5802 spin_unlock(&kvm_lock);
5805 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5808 * Notification about pvclock gtod data update.
5810 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5813 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5814 struct timekeeper *tk = priv;
5816 update_pvclock_gtod(tk);
5818 /* disable master clock if host does not trust, or does not
5819 * use, TSC clocksource
5821 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5822 atomic_read(&kvm_guest_has_master_clock) != 0)
5823 queue_work(system_long_wq, &pvclock_gtod_work);
5828 static struct notifier_block pvclock_gtod_notifier = {
5829 .notifier_call = pvclock_gtod_notify,
5833 int kvm_arch_init(void *opaque)
5836 struct kvm_x86_ops *ops = opaque;
5839 printk(KERN_ERR "kvm: already loaded the other module\n");
5844 if (!ops->cpu_has_kvm_support()) {
5845 printk(KERN_ERR "kvm: no hardware support\n");
5849 if (ops->disabled_by_bios()) {
5850 printk(KERN_ERR "kvm: disabled by bios\n");
5856 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5858 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5862 r = kvm_mmu_module_init();
5864 goto out_free_percpu;
5866 kvm_set_mmio_spte_mask();
5870 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5871 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5875 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5877 if (boot_cpu_has(X86_FEATURE_XSAVE))
5878 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5881 #ifdef CONFIG_X86_64
5882 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5888 free_percpu(shared_msrs);
5893 void kvm_arch_exit(void)
5895 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5897 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5898 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5899 CPUFREQ_TRANSITION_NOTIFIER);
5900 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5901 #ifdef CONFIG_X86_64
5902 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5905 kvm_mmu_module_exit();
5906 free_percpu(shared_msrs);
5909 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5911 ++vcpu->stat.halt_exits;
5912 if (lapic_in_kernel(vcpu)) {
5913 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5916 vcpu->run->exit_reason = KVM_EXIT_HLT;
5920 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5922 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5924 kvm_x86_ops->skip_emulated_instruction(vcpu);
5925 return kvm_vcpu_halt(vcpu);
5927 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5930 * kvm_pv_kick_cpu_op: Kick a vcpu.
5932 * @apicid - apicid of vcpu to be kicked.
5934 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5936 struct kvm_lapic_irq lapic_irq;
5938 lapic_irq.shorthand = 0;
5939 lapic_irq.dest_mode = 0;
5940 lapic_irq.dest_id = apicid;
5941 lapic_irq.msi_redir_hint = false;
5943 lapic_irq.delivery_mode = APIC_DM_REMRD;
5944 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5947 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5949 vcpu->arch.apicv_active = false;
5950 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5953 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5955 unsigned long nr, a0, a1, a2, a3, ret;
5956 int op_64_bit, r = 1;
5958 kvm_x86_ops->skip_emulated_instruction(vcpu);
5960 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5961 return kvm_hv_hypercall(vcpu);
5963 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5964 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5965 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5966 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5967 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5969 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5971 op_64_bit = is_64_bit_mode(vcpu);
5980 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5986 case KVM_HC_VAPIC_POLL_IRQ:
5989 case KVM_HC_KICK_CPU:
5990 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6000 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6001 ++vcpu->stat.hypercalls;
6004 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6006 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6008 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6009 char instruction[3];
6010 unsigned long rip = kvm_rip_read(vcpu);
6012 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6014 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6017 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6019 return vcpu->run->request_interrupt_window &&
6020 likely(!pic_in_kernel(vcpu->kvm));
6023 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6025 struct kvm_run *kvm_run = vcpu->run;
6027 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6028 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6029 kvm_run->cr8 = kvm_get_cr8(vcpu);
6030 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6031 kvm_run->ready_for_interrupt_injection =
6032 pic_in_kernel(vcpu->kvm) ||
6033 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6036 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6040 if (!kvm_x86_ops->update_cr8_intercept)
6043 if (!lapic_in_kernel(vcpu))
6046 if (vcpu->arch.apicv_active)
6049 if (!vcpu->arch.apic->vapic_addr)
6050 max_irr = kvm_lapic_find_highest_irr(vcpu);
6057 tpr = kvm_lapic_get_cr8(vcpu);
6059 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6062 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6066 /* try to reinject previous events if any */
6067 if (vcpu->arch.exception.pending) {
6068 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6069 vcpu->arch.exception.has_error_code,
6070 vcpu->arch.exception.error_code);
6072 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6073 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6076 if (vcpu->arch.exception.nr == DB_VECTOR &&
6077 (vcpu->arch.dr7 & DR7_GD)) {
6078 vcpu->arch.dr7 &= ~DR7_GD;
6079 kvm_update_dr7(vcpu);
6082 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6083 vcpu->arch.exception.has_error_code,
6084 vcpu->arch.exception.error_code,
6085 vcpu->arch.exception.reinject);
6089 if (vcpu->arch.nmi_injected) {
6090 kvm_x86_ops->set_nmi(vcpu);
6094 if (vcpu->arch.interrupt.pending) {
6095 kvm_x86_ops->set_irq(vcpu);
6099 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6100 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6105 /* try to inject new event if pending */
6106 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6107 --vcpu->arch.nmi_pending;
6108 vcpu->arch.nmi_injected = true;
6109 kvm_x86_ops->set_nmi(vcpu);
6110 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6112 * Because interrupts can be injected asynchronously, we are
6113 * calling check_nested_events again here to avoid a race condition.
6114 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6115 * proposal and current concerns. Perhaps we should be setting
6116 * KVM_REQ_EVENT only on certain events and not unconditionally?
6118 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6119 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6123 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6124 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6126 kvm_x86_ops->set_irq(vcpu);
6132 static void process_nmi(struct kvm_vcpu *vcpu)
6137 * x86 is limited to one NMI running, and one NMI pending after it.
6138 * If an NMI is already in progress, limit further NMIs to just one.
6139 * Otherwise, allow two (and we'll inject the first one immediately).
6141 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6144 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6145 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6146 kvm_make_request(KVM_REQ_EVENT, vcpu);
6149 #define put_smstate(type, buf, offset, val) \
6150 *(type *)((buf) + (offset) - 0x7e00) = val
6152 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6155 flags |= seg->g << 23;
6156 flags |= seg->db << 22;
6157 flags |= seg->l << 21;
6158 flags |= seg->avl << 20;
6159 flags |= seg->present << 15;
6160 flags |= seg->dpl << 13;
6161 flags |= seg->s << 12;
6162 flags |= seg->type << 8;
6166 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6168 struct kvm_segment seg;
6171 kvm_get_segment(vcpu, &seg, n);
6172 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6175 offset = 0x7f84 + n * 12;
6177 offset = 0x7f2c + (n - 3) * 12;
6179 put_smstate(u32, buf, offset + 8, seg.base);
6180 put_smstate(u32, buf, offset + 4, seg.limit);
6181 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6184 #ifdef CONFIG_X86_64
6185 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6187 struct kvm_segment seg;
6191 kvm_get_segment(vcpu, &seg, n);
6192 offset = 0x7e00 + n * 16;
6194 flags = process_smi_get_segment_flags(&seg) >> 8;
6195 put_smstate(u16, buf, offset, seg.selector);
6196 put_smstate(u16, buf, offset + 2, flags);
6197 put_smstate(u32, buf, offset + 4, seg.limit);
6198 put_smstate(u64, buf, offset + 8, seg.base);
6202 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6205 struct kvm_segment seg;
6209 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6210 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6211 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6212 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6214 for (i = 0; i < 8; i++)
6215 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6217 kvm_get_dr(vcpu, 6, &val);
6218 put_smstate(u32, buf, 0x7fcc, (u32)val);
6219 kvm_get_dr(vcpu, 7, &val);
6220 put_smstate(u32, buf, 0x7fc8, (u32)val);
6222 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6223 put_smstate(u32, buf, 0x7fc4, seg.selector);
6224 put_smstate(u32, buf, 0x7f64, seg.base);
6225 put_smstate(u32, buf, 0x7f60, seg.limit);
6226 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6228 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6229 put_smstate(u32, buf, 0x7fc0, seg.selector);
6230 put_smstate(u32, buf, 0x7f80, seg.base);
6231 put_smstate(u32, buf, 0x7f7c, seg.limit);
6232 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6234 kvm_x86_ops->get_gdt(vcpu, &dt);
6235 put_smstate(u32, buf, 0x7f74, dt.address);
6236 put_smstate(u32, buf, 0x7f70, dt.size);
6238 kvm_x86_ops->get_idt(vcpu, &dt);
6239 put_smstate(u32, buf, 0x7f58, dt.address);
6240 put_smstate(u32, buf, 0x7f54, dt.size);
6242 for (i = 0; i < 6; i++)
6243 process_smi_save_seg_32(vcpu, buf, i);
6245 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6248 put_smstate(u32, buf, 0x7efc, 0x00020000);
6249 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6252 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6254 #ifdef CONFIG_X86_64
6256 struct kvm_segment seg;
6260 for (i = 0; i < 16; i++)
6261 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6263 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6264 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6266 kvm_get_dr(vcpu, 6, &val);
6267 put_smstate(u64, buf, 0x7f68, val);
6268 kvm_get_dr(vcpu, 7, &val);
6269 put_smstate(u64, buf, 0x7f60, val);
6271 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6272 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6273 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6275 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6278 put_smstate(u32, buf, 0x7efc, 0x00020064);
6280 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6282 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6283 put_smstate(u16, buf, 0x7e90, seg.selector);
6284 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6285 put_smstate(u32, buf, 0x7e94, seg.limit);
6286 put_smstate(u64, buf, 0x7e98, seg.base);
6288 kvm_x86_ops->get_idt(vcpu, &dt);
6289 put_smstate(u32, buf, 0x7e84, dt.size);
6290 put_smstate(u64, buf, 0x7e88, dt.address);
6292 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6293 put_smstate(u16, buf, 0x7e70, seg.selector);
6294 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6295 put_smstate(u32, buf, 0x7e74, seg.limit);
6296 put_smstate(u64, buf, 0x7e78, seg.base);
6298 kvm_x86_ops->get_gdt(vcpu, &dt);
6299 put_smstate(u32, buf, 0x7e64, dt.size);
6300 put_smstate(u64, buf, 0x7e68, dt.address);
6302 for (i = 0; i < 6; i++)
6303 process_smi_save_seg_64(vcpu, buf, i);
6309 static void process_smi(struct kvm_vcpu *vcpu)
6311 struct kvm_segment cs, ds;
6317 vcpu->arch.smi_pending = true;
6321 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6322 vcpu->arch.hflags |= HF_SMM_MASK;
6323 memset(buf, 0, 512);
6324 if (guest_cpuid_has_longmode(vcpu))
6325 process_smi_save_state_64(vcpu, buf);
6327 process_smi_save_state_32(vcpu, buf);
6329 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6331 if (kvm_x86_ops->get_nmi_mask(vcpu))
6332 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6334 kvm_x86_ops->set_nmi_mask(vcpu, true);
6336 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6337 kvm_rip_write(vcpu, 0x8000);
6339 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6340 kvm_x86_ops->set_cr0(vcpu, cr0);
6341 vcpu->arch.cr0 = cr0;
6343 kvm_x86_ops->set_cr4(vcpu, 0);
6345 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6346 dt.address = dt.size = 0;
6347 kvm_x86_ops->set_idt(vcpu, &dt);
6349 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6351 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6352 cs.base = vcpu->arch.smbase;
6357 cs.limit = ds.limit = 0xffffffff;
6358 cs.type = ds.type = 0x3;
6359 cs.dpl = ds.dpl = 0;
6364 cs.avl = ds.avl = 0;
6365 cs.present = ds.present = 1;
6366 cs.unusable = ds.unusable = 0;
6367 cs.padding = ds.padding = 0;
6369 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6370 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6371 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6372 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6373 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6374 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6376 if (guest_cpuid_has_longmode(vcpu))
6377 kvm_x86_ops->set_efer(vcpu, 0);
6379 kvm_update_cpuid(vcpu);
6380 kvm_mmu_reset_context(vcpu);
6383 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6385 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6388 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6390 u64 eoi_exit_bitmap[4];
6392 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6395 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6397 if (irqchip_split(vcpu->kvm))
6398 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6400 if (vcpu->arch.apicv_active)
6401 kvm_x86_ops->sync_pir_to_irr(vcpu);
6402 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6404 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6405 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6406 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6409 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6411 ++vcpu->stat.tlb_flush;
6412 kvm_x86_ops->tlb_flush(vcpu);
6415 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6417 struct page *page = NULL;
6419 if (!lapic_in_kernel(vcpu))
6422 if (!kvm_x86_ops->set_apic_access_page_addr)
6425 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6426 if (is_error_page(page))
6428 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6431 * Do not pin apic access page in memory, the MMU notifier
6432 * will call us again if it is migrated or swapped out.
6436 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6438 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6439 unsigned long address)
6442 * The physical address of apic access page is stored in the VMCS.
6443 * Update it when it becomes invalid.
6445 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6446 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6450 * Returns 1 to let vcpu_run() continue the guest execution loop without
6451 * exiting to the userspace. Otherwise, the value will be returned to the
6454 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6458 dm_request_for_irq_injection(vcpu) &&
6459 kvm_cpu_accept_dm_intr(vcpu);
6461 bool req_immediate_exit = false;
6463 if (vcpu->requests) {
6464 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6465 kvm_mmu_unload(vcpu);
6466 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6467 __kvm_migrate_timers(vcpu);
6468 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6469 kvm_gen_update_masterclock(vcpu->kvm);
6470 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6471 kvm_gen_kvmclock_update(vcpu);
6472 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6473 r = kvm_guest_time_update(vcpu);
6477 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6478 kvm_mmu_sync_roots(vcpu);
6479 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6480 kvm_vcpu_flush_tlb(vcpu);
6481 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6482 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6486 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6487 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6491 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6492 vcpu->fpu_active = 0;
6493 kvm_x86_ops->fpu_deactivate(vcpu);
6495 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6496 /* Page is swapped out. Do synthetic halt */
6497 vcpu->arch.apf.halted = true;
6501 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6502 record_steal_time(vcpu);
6503 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6505 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6507 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6508 kvm_pmu_handle_event(vcpu);
6509 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6510 kvm_pmu_deliver_pmi(vcpu);
6511 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6512 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6513 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6514 vcpu->arch.ioapic_handled_vectors)) {
6515 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6516 vcpu->run->eoi.vector =
6517 vcpu->arch.pending_ioapic_eoi;
6522 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6523 vcpu_scan_ioapic(vcpu);
6524 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6525 kvm_vcpu_reload_apic_access_page(vcpu);
6526 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6527 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6528 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6532 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6533 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6534 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6538 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6539 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6540 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6546 * KVM_REQ_HV_STIMER has to be processed after
6547 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6548 * depend on the guest clock being up-to-date
6550 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6551 kvm_hv_process_stimers(vcpu);
6555 * KVM_REQ_EVENT is not set when posted interrupts are set by
6556 * VT-d hardware, so we have to update RVI unconditionally.
6558 if (kvm_lapic_enabled(vcpu)) {
6560 * Update architecture specific hints for APIC
6561 * virtual interrupt delivery.
6563 if (vcpu->arch.apicv_active)
6564 kvm_x86_ops->hwapic_irr_update(vcpu,
6565 kvm_lapic_find_highest_irr(vcpu));
6568 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6569 kvm_apic_accept_events(vcpu);
6570 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6575 if (inject_pending_event(vcpu, req_int_win) != 0)
6576 req_immediate_exit = true;
6577 /* enable NMI/IRQ window open exits if needed */
6579 if (vcpu->arch.nmi_pending)
6580 kvm_x86_ops->enable_nmi_window(vcpu);
6581 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6582 kvm_x86_ops->enable_irq_window(vcpu);
6585 if (kvm_lapic_enabled(vcpu)) {
6586 update_cr8_intercept(vcpu);
6587 kvm_lapic_sync_to_vapic(vcpu);
6591 r = kvm_mmu_reload(vcpu);
6593 goto cancel_injection;
6598 kvm_x86_ops->prepare_guest_switch(vcpu);
6599 if (vcpu->fpu_active)
6600 kvm_load_guest_fpu(vcpu);
6601 vcpu->mode = IN_GUEST_MODE;
6603 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6606 * We should set ->mode before check ->requests,
6607 * Please see the comment in kvm_make_all_cpus_request.
6608 * This also orders the write to mode from any reads
6609 * to the page tables done while the VCPU is running.
6610 * Please see the comment in kvm_flush_remote_tlbs.
6612 smp_mb__after_srcu_read_unlock();
6614 local_irq_disable();
6616 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6617 || need_resched() || signal_pending(current)) {
6618 vcpu->mode = OUTSIDE_GUEST_MODE;
6622 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6624 goto cancel_injection;
6627 kvm_load_guest_xcr0(vcpu);
6629 if (req_immediate_exit)
6630 smp_send_reschedule(vcpu->cpu);
6632 trace_kvm_entry(vcpu->vcpu_id);
6633 wait_lapic_expire(vcpu);
6634 __kvm_guest_enter();
6636 if (unlikely(vcpu->arch.switch_db_regs)) {
6638 set_debugreg(vcpu->arch.eff_db[0], 0);
6639 set_debugreg(vcpu->arch.eff_db[1], 1);
6640 set_debugreg(vcpu->arch.eff_db[2], 2);
6641 set_debugreg(vcpu->arch.eff_db[3], 3);
6642 set_debugreg(vcpu->arch.dr6, 6);
6643 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6646 kvm_x86_ops->run(vcpu);
6649 * Do this here before restoring debug registers on the host. And
6650 * since we do this before handling the vmexit, a DR access vmexit
6651 * can (a) read the correct value of the debug registers, (b) set
6652 * KVM_DEBUGREG_WONT_EXIT again.
6654 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6655 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6656 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6657 kvm_update_dr0123(vcpu);
6658 kvm_update_dr6(vcpu);
6659 kvm_update_dr7(vcpu);
6660 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6664 * If the guest has used debug registers, at least dr7
6665 * will be disabled while returning to the host.
6666 * If we don't have active breakpoints in the host, we don't
6667 * care about the messed up debug address registers. But if
6668 * we have some of them active, restore the old state.
6670 if (hw_breakpoint_active())
6671 hw_breakpoint_restore();
6673 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6675 vcpu->mode = OUTSIDE_GUEST_MODE;
6678 kvm_put_guest_xcr0(vcpu);
6680 /* Interrupt is enabled by handle_external_intr() */
6681 kvm_x86_ops->handle_external_intr(vcpu);
6686 * We must have an instruction between local_irq_enable() and
6687 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6688 * the interrupt shadow. The stat.exits increment will do nicely.
6689 * But we need to prevent reordering, hence this barrier():
6697 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6700 * Profile KVM exit RIPs:
6702 if (unlikely(prof_on == KVM_PROFILING)) {
6703 unsigned long rip = kvm_rip_read(vcpu);
6704 profile_hit(KVM_PROFILING, (void *)rip);
6707 if (unlikely(vcpu->arch.tsc_always_catchup))
6708 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6710 if (vcpu->arch.apic_attention)
6711 kvm_lapic_sync_from_vapic(vcpu);
6713 r = kvm_x86_ops->handle_exit(vcpu);
6717 kvm_x86_ops->cancel_injection(vcpu);
6718 if (unlikely(vcpu->arch.apic_attention))
6719 kvm_lapic_sync_from_vapic(vcpu);
6724 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6726 if (!kvm_arch_vcpu_runnable(vcpu) &&
6727 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6728 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6729 kvm_vcpu_block(vcpu);
6730 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6732 if (kvm_x86_ops->post_block)
6733 kvm_x86_ops->post_block(vcpu);
6735 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6739 kvm_apic_accept_events(vcpu);
6740 switch(vcpu->arch.mp_state) {
6741 case KVM_MP_STATE_HALTED:
6742 vcpu->arch.pv.pv_unhalted = false;
6743 vcpu->arch.mp_state =
6744 KVM_MP_STATE_RUNNABLE;
6745 case KVM_MP_STATE_RUNNABLE:
6746 vcpu->arch.apf.halted = false;
6748 case KVM_MP_STATE_INIT_RECEIVED:
6757 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6759 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6760 !vcpu->arch.apf.halted);
6763 static int vcpu_run(struct kvm_vcpu *vcpu)
6766 struct kvm *kvm = vcpu->kvm;
6768 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6771 if (kvm_vcpu_running(vcpu)) {
6772 r = vcpu_enter_guest(vcpu);
6774 r = vcpu_block(kvm, vcpu);
6780 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6781 if (kvm_cpu_has_pending_timer(vcpu))
6782 kvm_inject_pending_timer_irqs(vcpu);
6784 if (dm_request_for_irq_injection(vcpu) &&
6785 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6787 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6788 ++vcpu->stat.request_irq_exits;
6792 kvm_check_async_pf_completion(vcpu);
6794 if (signal_pending(current)) {
6796 vcpu->run->exit_reason = KVM_EXIT_INTR;
6797 ++vcpu->stat.signal_exits;
6800 if (need_resched()) {
6801 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6803 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6807 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6812 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6815 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6816 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6817 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6818 if (r != EMULATE_DONE)
6823 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6825 BUG_ON(!vcpu->arch.pio.count);
6827 return complete_emulated_io(vcpu);
6831 * Implements the following, as a state machine:
6835 * for each mmio piece in the fragment
6843 * for each mmio piece in the fragment
6848 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6850 struct kvm_run *run = vcpu->run;
6851 struct kvm_mmio_fragment *frag;
6854 BUG_ON(!vcpu->mmio_needed);
6856 /* Complete previous fragment */
6857 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6858 len = min(8u, frag->len);
6859 if (!vcpu->mmio_is_write)
6860 memcpy(frag->data, run->mmio.data, len);
6862 if (frag->len <= 8) {
6863 /* Switch to the next fragment. */
6865 vcpu->mmio_cur_fragment++;
6867 /* Go forward to the next mmio piece. */
6873 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6874 vcpu->mmio_needed = 0;
6876 /* FIXME: return into emulator if single-stepping. */
6877 if (vcpu->mmio_is_write)
6879 vcpu->mmio_read_completed = 1;
6880 return complete_emulated_io(vcpu);
6883 run->exit_reason = KVM_EXIT_MMIO;
6884 run->mmio.phys_addr = frag->gpa;
6885 if (vcpu->mmio_is_write)
6886 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6887 run->mmio.len = min(8u, frag->len);
6888 run->mmio.is_write = vcpu->mmio_is_write;
6889 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6894 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6896 struct fpu *fpu = ¤t->thread.fpu;
6900 fpu__activate_curr(fpu);
6902 if (vcpu->sigset_active)
6903 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6905 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6906 kvm_vcpu_block(vcpu);
6907 kvm_apic_accept_events(vcpu);
6908 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6913 /* re-sync apic's tpr */
6914 if (!lapic_in_kernel(vcpu)) {
6915 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6921 if (unlikely(vcpu->arch.complete_userspace_io)) {
6922 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6923 vcpu->arch.complete_userspace_io = NULL;
6928 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6933 post_kvm_run_save(vcpu);
6934 if (vcpu->sigset_active)
6935 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6940 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6942 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6944 * We are here if userspace calls get_regs() in the middle of
6945 * instruction emulation. Registers state needs to be copied
6946 * back from emulation context to vcpu. Userspace shouldn't do
6947 * that usually, but some bad designed PV devices (vmware
6948 * backdoor interface) need this to work
6950 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6951 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6953 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6954 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6955 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6956 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6957 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6958 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6959 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6960 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6961 #ifdef CONFIG_X86_64
6962 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6963 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6964 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6965 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6966 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6967 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6968 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6969 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6972 regs->rip = kvm_rip_read(vcpu);
6973 regs->rflags = kvm_get_rflags(vcpu);
6978 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6980 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6981 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6983 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6984 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6985 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6986 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6987 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6988 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6989 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6990 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6991 #ifdef CONFIG_X86_64
6992 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6993 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6994 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6995 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6996 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6997 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6998 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6999 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7002 kvm_rip_write(vcpu, regs->rip);
7003 kvm_set_rflags(vcpu, regs->rflags);
7005 vcpu->arch.exception.pending = false;
7007 kvm_make_request(KVM_REQ_EVENT, vcpu);
7012 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7014 struct kvm_segment cs;
7016 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7020 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7022 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7023 struct kvm_sregs *sregs)
7027 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7028 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7029 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7030 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7031 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7032 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7034 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7035 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7037 kvm_x86_ops->get_idt(vcpu, &dt);
7038 sregs->idt.limit = dt.size;
7039 sregs->idt.base = dt.address;
7040 kvm_x86_ops->get_gdt(vcpu, &dt);
7041 sregs->gdt.limit = dt.size;
7042 sregs->gdt.base = dt.address;
7044 sregs->cr0 = kvm_read_cr0(vcpu);
7045 sregs->cr2 = vcpu->arch.cr2;
7046 sregs->cr3 = kvm_read_cr3(vcpu);
7047 sregs->cr4 = kvm_read_cr4(vcpu);
7048 sregs->cr8 = kvm_get_cr8(vcpu);
7049 sregs->efer = vcpu->arch.efer;
7050 sregs->apic_base = kvm_get_apic_base(vcpu);
7052 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7054 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7055 set_bit(vcpu->arch.interrupt.nr,
7056 (unsigned long *)sregs->interrupt_bitmap);
7061 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7062 struct kvm_mp_state *mp_state)
7064 kvm_apic_accept_events(vcpu);
7065 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7066 vcpu->arch.pv.pv_unhalted)
7067 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7069 mp_state->mp_state = vcpu->arch.mp_state;
7074 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7075 struct kvm_mp_state *mp_state)
7077 if (!lapic_in_kernel(vcpu) &&
7078 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7081 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7082 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7083 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7085 vcpu->arch.mp_state = mp_state->mp_state;
7086 kvm_make_request(KVM_REQ_EVENT, vcpu);
7090 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7091 int reason, bool has_error_code, u32 error_code)
7093 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7096 init_emulate_ctxt(vcpu);
7098 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7099 has_error_code, error_code);
7102 return EMULATE_FAIL;
7104 kvm_rip_write(vcpu, ctxt->eip);
7105 kvm_set_rflags(vcpu, ctxt->eflags);
7106 kvm_make_request(KVM_REQ_EVENT, vcpu);
7107 return EMULATE_DONE;
7109 EXPORT_SYMBOL_GPL(kvm_task_switch);
7111 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7112 struct kvm_sregs *sregs)
7114 struct msr_data apic_base_msr;
7115 int mmu_reset_needed = 0;
7116 int pending_vec, max_bits, idx;
7119 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7122 dt.size = sregs->idt.limit;
7123 dt.address = sregs->idt.base;
7124 kvm_x86_ops->set_idt(vcpu, &dt);
7125 dt.size = sregs->gdt.limit;
7126 dt.address = sregs->gdt.base;
7127 kvm_x86_ops->set_gdt(vcpu, &dt);
7129 vcpu->arch.cr2 = sregs->cr2;
7130 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7131 vcpu->arch.cr3 = sregs->cr3;
7132 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7134 kvm_set_cr8(vcpu, sregs->cr8);
7136 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7137 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7138 apic_base_msr.data = sregs->apic_base;
7139 apic_base_msr.host_initiated = true;
7140 kvm_set_apic_base(vcpu, &apic_base_msr);
7142 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7143 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7144 vcpu->arch.cr0 = sregs->cr0;
7146 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7147 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7148 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7149 kvm_update_cpuid(vcpu);
7151 idx = srcu_read_lock(&vcpu->kvm->srcu);
7152 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7153 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7154 mmu_reset_needed = 1;
7156 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7158 if (mmu_reset_needed)
7159 kvm_mmu_reset_context(vcpu);
7161 max_bits = KVM_NR_INTERRUPTS;
7162 pending_vec = find_first_bit(
7163 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7164 if (pending_vec < max_bits) {
7165 kvm_queue_interrupt(vcpu, pending_vec, false);
7166 pr_debug("Set back pending irq %d\n", pending_vec);
7169 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7170 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7171 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7172 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7173 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7174 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7176 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7177 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7179 update_cr8_intercept(vcpu);
7181 /* Older userspace won't unhalt the vcpu on reset. */
7182 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7183 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7185 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7187 kvm_make_request(KVM_REQ_EVENT, vcpu);
7192 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7193 struct kvm_guest_debug *dbg)
7195 unsigned long rflags;
7198 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7200 if (vcpu->arch.exception.pending)
7202 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7203 kvm_queue_exception(vcpu, DB_VECTOR);
7205 kvm_queue_exception(vcpu, BP_VECTOR);
7209 * Read rflags as long as potentially injected trace flags are still
7212 rflags = kvm_get_rflags(vcpu);
7214 vcpu->guest_debug = dbg->control;
7215 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7216 vcpu->guest_debug = 0;
7218 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7219 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7220 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7221 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7223 for (i = 0; i < KVM_NR_DB_REGS; i++)
7224 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7226 kvm_update_dr7(vcpu);
7228 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7229 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7230 get_segment_base(vcpu, VCPU_SREG_CS);
7233 * Trigger an rflags update that will inject or remove the trace
7236 kvm_set_rflags(vcpu, rflags);
7238 kvm_x86_ops->update_bp_intercept(vcpu);
7248 * Translate a guest virtual address to a guest physical address.
7250 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7251 struct kvm_translation *tr)
7253 unsigned long vaddr = tr->linear_address;
7257 idx = srcu_read_lock(&vcpu->kvm->srcu);
7258 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7259 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7260 tr->physical_address = gpa;
7261 tr->valid = gpa != UNMAPPED_GVA;
7268 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7270 struct fxregs_state *fxsave =
7271 &vcpu->arch.guest_fpu.state.fxsave;
7273 memcpy(fpu->fpr, fxsave->st_space, 128);
7274 fpu->fcw = fxsave->cwd;
7275 fpu->fsw = fxsave->swd;
7276 fpu->ftwx = fxsave->twd;
7277 fpu->last_opcode = fxsave->fop;
7278 fpu->last_ip = fxsave->rip;
7279 fpu->last_dp = fxsave->rdp;
7280 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7285 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7287 struct fxregs_state *fxsave =
7288 &vcpu->arch.guest_fpu.state.fxsave;
7290 memcpy(fxsave->st_space, fpu->fpr, 128);
7291 fxsave->cwd = fpu->fcw;
7292 fxsave->swd = fpu->fsw;
7293 fxsave->twd = fpu->ftwx;
7294 fxsave->fop = fpu->last_opcode;
7295 fxsave->rip = fpu->last_ip;
7296 fxsave->rdp = fpu->last_dp;
7297 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7302 static void fx_init(struct kvm_vcpu *vcpu)
7304 fpstate_init(&vcpu->arch.guest_fpu.state);
7305 if (boot_cpu_has(X86_FEATURE_XSAVES))
7306 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7307 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7310 * Ensure guest xcr0 is valid for loading
7312 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7314 vcpu->arch.cr0 |= X86_CR0_ET;
7317 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7319 if (vcpu->guest_fpu_loaded)
7323 * Restore all possible states in the guest,
7324 * and assume host would use all available bits.
7325 * Guest xcr0 would be loaded later.
7327 vcpu->guest_fpu_loaded = 1;
7328 __kernel_fpu_begin();
7329 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7333 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7335 if (!vcpu->guest_fpu_loaded) {
7336 vcpu->fpu_counter = 0;
7340 vcpu->guest_fpu_loaded = 0;
7341 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7343 ++vcpu->stat.fpu_reload;
7345 * If using eager FPU mode, or if the guest is a frequent user
7346 * of the FPU, just leave the FPU active for next time.
7347 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7348 * the FPU in bursts will revert to loading it on demand.
7350 if (!use_eager_fpu()) {
7351 if (++vcpu->fpu_counter < 5)
7352 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7357 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7359 kvmclock_reset(vcpu);
7361 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7362 kvm_x86_ops->vcpu_free(vcpu);
7365 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7368 struct kvm_vcpu *vcpu;
7370 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7371 printk_once(KERN_WARNING
7372 "kvm: SMP vm created on host with unstable TSC; "
7373 "guest TSC will not be reliable\n");
7375 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7380 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7384 kvm_vcpu_mtrr_init(vcpu);
7385 r = vcpu_load(vcpu);
7388 kvm_vcpu_reset(vcpu, false);
7389 kvm_mmu_setup(vcpu);
7394 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7396 struct msr_data msr;
7397 struct kvm *kvm = vcpu->kvm;
7399 if (vcpu_load(vcpu))
7402 msr.index = MSR_IA32_TSC;
7403 msr.host_initiated = true;
7404 kvm_write_tsc(vcpu, &msr);
7407 if (!kvmclock_periodic_sync)
7410 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7411 KVMCLOCK_SYNC_PERIOD);
7414 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7417 vcpu->arch.apf.msr_val = 0;
7419 r = vcpu_load(vcpu);
7421 kvm_mmu_unload(vcpu);
7424 kvm_x86_ops->vcpu_free(vcpu);
7427 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7429 vcpu->arch.hflags = 0;
7431 atomic_set(&vcpu->arch.nmi_queued, 0);
7432 vcpu->arch.nmi_pending = 0;
7433 vcpu->arch.nmi_injected = false;
7434 kvm_clear_interrupt_queue(vcpu);
7435 kvm_clear_exception_queue(vcpu);
7437 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7438 kvm_update_dr0123(vcpu);
7439 vcpu->arch.dr6 = DR6_INIT;
7440 kvm_update_dr6(vcpu);
7441 vcpu->arch.dr7 = DR7_FIXED_1;
7442 kvm_update_dr7(vcpu);
7446 kvm_make_request(KVM_REQ_EVENT, vcpu);
7447 vcpu->arch.apf.msr_val = 0;
7448 vcpu->arch.st.msr_val = 0;
7450 kvmclock_reset(vcpu);
7452 kvm_clear_async_pf_completion_queue(vcpu);
7453 kvm_async_pf_hash_reset(vcpu);
7454 vcpu->arch.apf.halted = false;
7457 kvm_pmu_reset(vcpu);
7458 vcpu->arch.smbase = 0x30000;
7461 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7462 vcpu->arch.regs_avail = ~0;
7463 vcpu->arch.regs_dirty = ~0;
7465 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7468 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7470 struct kvm_segment cs;
7472 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7473 cs.selector = vector << 8;
7474 cs.base = vector << 12;
7475 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7476 kvm_rip_write(vcpu, 0);
7479 int kvm_arch_hardware_enable(void)
7482 struct kvm_vcpu *vcpu;
7487 bool stable, backwards_tsc = false;
7489 kvm_shared_msr_cpu_online();
7490 ret = kvm_x86_ops->hardware_enable();
7494 local_tsc = rdtsc();
7495 stable = !check_tsc_unstable();
7496 list_for_each_entry(kvm, &vm_list, vm_list) {
7497 kvm_for_each_vcpu(i, vcpu, kvm) {
7498 if (!stable && vcpu->cpu == smp_processor_id())
7499 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7500 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7501 backwards_tsc = true;
7502 if (vcpu->arch.last_host_tsc > max_tsc)
7503 max_tsc = vcpu->arch.last_host_tsc;
7509 * Sometimes, even reliable TSCs go backwards. This happens on
7510 * platforms that reset TSC during suspend or hibernate actions, but
7511 * maintain synchronization. We must compensate. Fortunately, we can
7512 * detect that condition here, which happens early in CPU bringup,
7513 * before any KVM threads can be running. Unfortunately, we can't
7514 * bring the TSCs fully up to date with real time, as we aren't yet far
7515 * enough into CPU bringup that we know how much real time has actually
7516 * elapsed; our helper function, get_kernel_ns() will be using boot
7517 * variables that haven't been updated yet.
7519 * So we simply find the maximum observed TSC above, then record the
7520 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7521 * the adjustment will be applied. Note that we accumulate
7522 * adjustments, in case multiple suspend cycles happen before some VCPU
7523 * gets a chance to run again. In the event that no KVM threads get a
7524 * chance to run, we will miss the entire elapsed period, as we'll have
7525 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7526 * loose cycle time. This isn't too big a deal, since the loss will be
7527 * uniform across all VCPUs (not to mention the scenario is extremely
7528 * unlikely). It is possible that a second hibernate recovery happens
7529 * much faster than a first, causing the observed TSC here to be
7530 * smaller; this would require additional padding adjustment, which is
7531 * why we set last_host_tsc to the local tsc observed here.
7533 * N.B. - this code below runs only on platforms with reliable TSC,
7534 * as that is the only way backwards_tsc is set above. Also note
7535 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7536 * have the same delta_cyc adjustment applied if backwards_tsc
7537 * is detected. Note further, this adjustment is only done once,
7538 * as we reset last_host_tsc on all VCPUs to stop this from being
7539 * called multiple times (one for each physical CPU bringup).
7541 * Platforms with unreliable TSCs don't have to deal with this, they
7542 * will be compensated by the logic in vcpu_load, which sets the TSC to
7543 * catchup mode. This will catchup all VCPUs to real time, but cannot
7544 * guarantee that they stay in perfect synchronization.
7546 if (backwards_tsc) {
7547 u64 delta_cyc = max_tsc - local_tsc;
7548 backwards_tsc_observed = true;
7549 list_for_each_entry(kvm, &vm_list, vm_list) {
7550 kvm_for_each_vcpu(i, vcpu, kvm) {
7551 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7552 vcpu->arch.last_host_tsc = local_tsc;
7553 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7557 * We have to disable TSC offset matching.. if you were
7558 * booting a VM while issuing an S4 host suspend....
7559 * you may have some problem. Solving this issue is
7560 * left as an exercise to the reader.
7562 kvm->arch.last_tsc_nsec = 0;
7563 kvm->arch.last_tsc_write = 0;
7570 void kvm_arch_hardware_disable(void)
7572 kvm_x86_ops->hardware_disable();
7573 drop_user_return_notifiers();
7576 int kvm_arch_hardware_setup(void)
7580 r = kvm_x86_ops->hardware_setup();
7584 if (kvm_has_tsc_control) {
7586 * Make sure the user can only configure tsc_khz values that
7587 * fit into a signed integer.
7588 * A min value is not calculated needed because it will always
7589 * be 1 on all machines.
7591 u64 max = min(0x7fffffffULL,
7592 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7593 kvm_max_guest_tsc_khz = max;
7595 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7598 kvm_init_msr_list();
7602 void kvm_arch_hardware_unsetup(void)
7604 kvm_x86_ops->hardware_unsetup();
7607 void kvm_arch_check_processor_compat(void *rtn)
7609 kvm_x86_ops->check_processor_compatibility(rtn);
7612 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7614 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7616 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7618 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7620 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7623 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7625 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7628 struct static_key kvm_no_apic_vcpu __read_mostly;
7629 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7631 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7637 BUG_ON(vcpu->kvm == NULL);
7640 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7641 vcpu->arch.pv.pv_unhalted = false;
7642 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7643 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7644 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7646 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7648 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7653 vcpu->arch.pio_data = page_address(page);
7655 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7657 r = kvm_mmu_create(vcpu);
7659 goto fail_free_pio_data;
7661 if (irqchip_in_kernel(kvm)) {
7662 r = kvm_create_lapic(vcpu);
7664 goto fail_mmu_destroy;
7666 static_key_slow_inc(&kvm_no_apic_vcpu);
7668 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7670 if (!vcpu->arch.mce_banks) {
7672 goto fail_free_lapic;
7674 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7676 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7678 goto fail_free_mce_banks;
7683 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7684 vcpu->arch.pv_time_enabled = false;
7686 vcpu->arch.guest_supported_xcr0 = 0;
7687 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7689 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7691 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7693 kvm_async_pf_hash_reset(vcpu);
7696 vcpu->arch.pending_external_vector = -1;
7698 kvm_hv_vcpu_init(vcpu);
7702 fail_free_mce_banks:
7703 kfree(vcpu->arch.mce_banks);
7705 kvm_free_lapic(vcpu);
7707 kvm_mmu_destroy(vcpu);
7709 free_page((unsigned long)vcpu->arch.pio_data);
7714 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7718 kvm_hv_vcpu_uninit(vcpu);
7719 kvm_pmu_destroy(vcpu);
7720 kfree(vcpu->arch.mce_banks);
7721 kvm_free_lapic(vcpu);
7722 idx = srcu_read_lock(&vcpu->kvm->srcu);
7723 kvm_mmu_destroy(vcpu);
7724 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7725 free_page((unsigned long)vcpu->arch.pio_data);
7726 if (!lapic_in_kernel(vcpu))
7727 static_key_slow_dec(&kvm_no_apic_vcpu);
7730 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7732 kvm_x86_ops->sched_in(vcpu, cpu);
7735 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7740 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7741 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7742 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7743 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7744 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7746 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7747 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7748 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7749 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7750 &kvm->arch.irq_sources_bitmap);
7752 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7753 mutex_init(&kvm->arch.apic_map_lock);
7754 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7756 pvclock_update_vm_gtod_copy(kvm);
7758 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7759 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7761 kvm_page_track_init(kvm);
7762 kvm_mmu_init_vm(kvm);
7764 if (kvm_x86_ops->vm_init)
7765 return kvm_x86_ops->vm_init(kvm);
7770 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7773 r = vcpu_load(vcpu);
7775 kvm_mmu_unload(vcpu);
7779 static void kvm_free_vcpus(struct kvm *kvm)
7782 struct kvm_vcpu *vcpu;
7785 * Unpin any mmu pages first.
7787 kvm_for_each_vcpu(i, vcpu, kvm) {
7788 kvm_clear_async_pf_completion_queue(vcpu);
7789 kvm_unload_vcpu_mmu(vcpu);
7791 kvm_for_each_vcpu(i, vcpu, kvm)
7792 kvm_arch_vcpu_free(vcpu);
7794 mutex_lock(&kvm->lock);
7795 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7796 kvm->vcpus[i] = NULL;
7798 atomic_set(&kvm->online_vcpus, 0);
7799 mutex_unlock(&kvm->lock);
7802 void kvm_arch_sync_events(struct kvm *kvm)
7804 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7805 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7806 kvm_free_all_assigned_devices(kvm);
7810 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7814 struct kvm_memslots *slots = kvm_memslots(kvm);
7815 struct kvm_memory_slot *slot, old;
7817 /* Called with kvm->slots_lock held. */
7818 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7821 slot = id_to_memslot(slots, id);
7827 * MAP_SHARED to prevent internal slot pages from being moved
7830 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7831 MAP_SHARED | MAP_ANONYMOUS, 0);
7832 if (IS_ERR((void *)hva))
7833 return PTR_ERR((void *)hva);
7842 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7843 struct kvm_userspace_memory_region m;
7845 m.slot = id | (i << 16);
7847 m.guest_phys_addr = gpa;
7848 m.userspace_addr = hva;
7849 m.memory_size = size;
7850 r = __kvm_set_memory_region(kvm, &m);
7856 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7862 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7864 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7868 mutex_lock(&kvm->slots_lock);
7869 r = __x86_set_memory_region(kvm, id, gpa, size);
7870 mutex_unlock(&kvm->slots_lock);
7874 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7876 void kvm_arch_destroy_vm(struct kvm *kvm)
7878 if (current->mm == kvm->mm) {
7880 * Free memory regions allocated on behalf of userspace,
7881 * unless the the memory map has changed due to process exit
7884 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7885 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7886 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7888 if (kvm_x86_ops->vm_destroy)
7889 kvm_x86_ops->vm_destroy(kvm);
7890 kvm_iommu_unmap_guest(kvm);
7891 kfree(kvm->arch.vpic);
7892 kfree(kvm->arch.vioapic);
7893 kvm_free_vcpus(kvm);
7894 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7895 kvm_mmu_uninit_vm(kvm);
7898 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7899 struct kvm_memory_slot *dont)
7903 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7904 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7905 kvfree(free->arch.rmap[i]);
7906 free->arch.rmap[i] = NULL;
7911 if (!dont || free->arch.lpage_info[i - 1] !=
7912 dont->arch.lpage_info[i - 1]) {
7913 kvfree(free->arch.lpage_info[i - 1]);
7914 free->arch.lpage_info[i - 1] = NULL;
7918 kvm_page_track_free_memslot(free, dont);
7921 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7922 unsigned long npages)
7926 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7927 struct kvm_lpage_info *linfo;
7932 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7933 slot->base_gfn, level) + 1;
7935 slot->arch.rmap[i] =
7936 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7937 if (!slot->arch.rmap[i])
7942 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7946 slot->arch.lpage_info[i - 1] = linfo;
7948 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7949 linfo[0].disallow_lpage = 1;
7950 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7951 linfo[lpages - 1].disallow_lpage = 1;
7952 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7954 * If the gfn and userspace address are not aligned wrt each
7955 * other, or if explicitly asked to, disable large page
7956 * support for this slot
7958 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7959 !kvm_largepages_enabled()) {
7962 for (j = 0; j < lpages; ++j)
7963 linfo[j].disallow_lpage = 1;
7967 if (kvm_page_track_create_memslot(slot, npages))
7973 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7974 kvfree(slot->arch.rmap[i]);
7975 slot->arch.rmap[i] = NULL;
7979 kvfree(slot->arch.lpage_info[i - 1]);
7980 slot->arch.lpage_info[i - 1] = NULL;
7985 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7988 * memslots->generation has been incremented.
7989 * mmio generation may have reached its maximum value.
7991 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7994 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7995 struct kvm_memory_slot *memslot,
7996 const struct kvm_userspace_memory_region *mem,
7997 enum kvm_mr_change change)
8002 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8003 struct kvm_memory_slot *new)
8005 /* Still write protect RO slot */
8006 if (new->flags & KVM_MEM_READONLY) {
8007 kvm_mmu_slot_remove_write_access(kvm, new);
8012 * Call kvm_x86_ops dirty logging hooks when they are valid.
8014 * kvm_x86_ops->slot_disable_log_dirty is called when:
8016 * - KVM_MR_CREATE with dirty logging is disabled
8017 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8019 * The reason is, in case of PML, we need to set D-bit for any slots
8020 * with dirty logging disabled in order to eliminate unnecessary GPA
8021 * logging in PML buffer (and potential PML buffer full VMEXT). This
8022 * guarantees leaving PML enabled during guest's lifetime won't have
8023 * any additonal overhead from PML when guest is running with dirty
8024 * logging disabled for memory slots.
8026 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8027 * to dirty logging mode.
8029 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8031 * In case of write protect:
8033 * Write protect all pages for dirty logging.
8035 * All the sptes including the large sptes which point to this
8036 * slot are set to readonly. We can not create any new large
8037 * spte on this slot until the end of the logging.
8039 * See the comments in fast_page_fault().
8041 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8042 if (kvm_x86_ops->slot_enable_log_dirty)
8043 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8045 kvm_mmu_slot_remove_write_access(kvm, new);
8047 if (kvm_x86_ops->slot_disable_log_dirty)
8048 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8052 void kvm_arch_commit_memory_region(struct kvm *kvm,
8053 const struct kvm_userspace_memory_region *mem,
8054 const struct kvm_memory_slot *old,
8055 const struct kvm_memory_slot *new,
8056 enum kvm_mr_change change)
8058 int nr_mmu_pages = 0;
8060 if (!kvm->arch.n_requested_mmu_pages)
8061 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8064 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8067 * Dirty logging tracks sptes in 4k granularity, meaning that large
8068 * sptes have to be split. If live migration is successful, the guest
8069 * in the source machine will be destroyed and large sptes will be
8070 * created in the destination. However, if the guest continues to run
8071 * in the source machine (for example if live migration fails), small
8072 * sptes will remain around and cause bad performance.
8074 * Scan sptes if dirty logging has been stopped, dropping those
8075 * which can be collapsed into a single large-page spte. Later
8076 * page faults will create the large-page sptes.
8078 if ((change != KVM_MR_DELETE) &&
8079 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8080 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8081 kvm_mmu_zap_collapsible_sptes(kvm, new);
8084 * Set up write protection and/or dirty logging for the new slot.
8086 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8087 * been zapped so no dirty logging staff is needed for old slot. For
8088 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8089 * new and it's also covered when dealing with the new slot.
8091 * FIXME: const-ify all uses of struct kvm_memory_slot.
8093 if (change != KVM_MR_DELETE)
8094 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8097 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8099 kvm_mmu_invalidate_zap_all_pages(kvm);
8102 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8103 struct kvm_memory_slot *slot)
8105 kvm_mmu_invalidate_zap_all_pages(kvm);
8108 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8110 if (!list_empty_careful(&vcpu->async_pf.done))
8113 if (kvm_apic_has_events(vcpu))
8116 if (vcpu->arch.pv.pv_unhalted)
8119 if (atomic_read(&vcpu->arch.nmi_queued))
8122 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8125 if (kvm_arch_interrupt_allowed(vcpu) &&
8126 kvm_cpu_has_interrupt(vcpu))
8129 if (kvm_hv_has_stimer_pending(vcpu))
8135 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8137 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8138 kvm_x86_ops->check_nested_events(vcpu, false);
8140 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8143 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8145 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8148 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8150 return kvm_x86_ops->interrupt_allowed(vcpu);
8153 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8155 if (is_64_bit_mode(vcpu))
8156 return kvm_rip_read(vcpu);
8157 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8158 kvm_rip_read(vcpu));
8160 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8162 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8164 return kvm_get_linear_rip(vcpu) == linear_rip;
8166 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8168 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8170 unsigned long rflags;
8172 rflags = kvm_x86_ops->get_rflags(vcpu);
8173 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8174 rflags &= ~X86_EFLAGS_TF;
8177 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8179 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8181 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8182 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8183 rflags |= X86_EFLAGS_TF;
8184 kvm_x86_ops->set_rflags(vcpu, rflags);
8187 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8189 __kvm_set_rflags(vcpu, rflags);
8190 kvm_make_request(KVM_REQ_EVENT, vcpu);
8192 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8194 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8198 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8202 r = kvm_mmu_reload(vcpu);
8206 if (!vcpu->arch.mmu.direct_map &&
8207 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8210 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8213 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8215 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8218 static inline u32 kvm_async_pf_next_probe(u32 key)
8220 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8223 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8225 u32 key = kvm_async_pf_hash_fn(gfn);
8227 while (vcpu->arch.apf.gfns[key] != ~0)
8228 key = kvm_async_pf_next_probe(key);
8230 vcpu->arch.apf.gfns[key] = gfn;
8233 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8236 u32 key = kvm_async_pf_hash_fn(gfn);
8238 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8239 (vcpu->arch.apf.gfns[key] != gfn &&
8240 vcpu->arch.apf.gfns[key] != ~0); i++)
8241 key = kvm_async_pf_next_probe(key);
8246 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8248 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8251 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8255 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8257 vcpu->arch.apf.gfns[i] = ~0;
8259 j = kvm_async_pf_next_probe(j);
8260 if (vcpu->arch.apf.gfns[j] == ~0)
8262 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8264 * k lies cyclically in ]i,j]
8266 * |....j i.k.| or |.k..j i...|
8268 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8269 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8274 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8277 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8281 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8282 struct kvm_async_pf *work)
8284 struct x86_exception fault;
8286 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8287 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8289 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8290 (vcpu->arch.apf.send_user_only &&
8291 kvm_x86_ops->get_cpl(vcpu) == 0))
8292 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8293 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8294 fault.vector = PF_VECTOR;
8295 fault.error_code_valid = true;
8296 fault.error_code = 0;
8297 fault.nested_page_fault = false;
8298 fault.address = work->arch.token;
8299 kvm_inject_page_fault(vcpu, &fault);
8303 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8304 struct kvm_async_pf *work)
8306 struct x86_exception fault;
8308 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8309 if (work->wakeup_all)
8310 work->arch.token = ~0; /* broadcast wakeup */
8312 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8314 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8315 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8316 fault.vector = PF_VECTOR;
8317 fault.error_code_valid = true;
8318 fault.error_code = 0;
8319 fault.nested_page_fault = false;
8320 fault.address = work->arch.token;
8321 kvm_inject_page_fault(vcpu, &fault);
8323 vcpu->arch.apf.halted = false;
8324 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8327 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8329 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8332 return !kvm_event_needs_reinjection(vcpu) &&
8333 kvm_x86_ops->interrupt_allowed(vcpu);
8336 void kvm_arch_start_assignment(struct kvm *kvm)
8338 atomic_inc(&kvm->arch.assigned_device_count);
8340 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8342 void kvm_arch_end_assignment(struct kvm *kvm)
8344 atomic_dec(&kvm->arch.assigned_device_count);
8346 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8348 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8350 return atomic_read(&kvm->arch.assigned_device_count);
8352 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8354 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8356 atomic_inc(&kvm->arch.noncoherent_dma_count);
8358 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8360 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8362 atomic_dec(&kvm->arch.noncoherent_dma_count);
8364 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8366 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8368 return atomic_read(&kvm->arch.noncoherent_dma_count);
8370 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8372 bool kvm_arch_has_irq_bypass(void)
8374 return kvm_x86_ops->update_pi_irte != NULL;
8377 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8378 struct irq_bypass_producer *prod)
8380 struct kvm_kernel_irqfd *irqfd =
8381 container_of(cons, struct kvm_kernel_irqfd, consumer);
8383 irqfd->producer = prod;
8385 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8386 prod->irq, irqfd->gsi, 1);
8389 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8390 struct irq_bypass_producer *prod)
8393 struct kvm_kernel_irqfd *irqfd =
8394 container_of(cons, struct kvm_kernel_irqfd, consumer);
8396 WARN_ON(irqfd->producer != prod);
8397 irqfd->producer = NULL;
8400 * When producer of consumer is unregistered, we change back to
8401 * remapped mode, so we can re-use the current implementation
8402 * when the irq is masked/disabed or the consumer side (KVM
8403 * int this case doesn't want to receive the interrupts.
8405 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8407 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8408 " fails: %d\n", irqfd->consumer.token, ret);
8411 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8412 uint32_t guest_irq, bool set)
8414 if (!kvm_x86_ops->update_pi_irte)
8417 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8420 bool kvm_vector_hashing_enabled(void)
8422 return vector_hashing;
8424 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8434 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8435 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8436 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8437 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8438 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8439 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8440 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8441 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8442 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8443 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8444 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);