drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_i2c.h"
  31
  32 #include "atom.h"
  33 #include "atom-bits.h"
  34 #include "atombios_encoders.h"
  35 #include "bif/bif_4_1_d.h"
  36
  37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                           u8 index)
  40 {
  41
  42 }
  43
  44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45 {
  46         struct amdgpu_i2c_bus_rec i2c;
  47
  48         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                 i2c.hw_capable = true;
  69         else
  70                 i2c.hw_capable = false;
  71
  72         if (gpio->sucI2cId.ucAccess == 0xa0)
  73                 i2c.mm_i2c = true;
  74         else
  75                 i2c.mm_i2c = false;
  76
  77         i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79         if (i2c.mask_clk_reg)
  80                 i2c.valid = true;
  81         else
  82                 i2c.valid = false;
  83
  84         return i2c;
  85 }
  86
  87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                           uint8_t id)
  89 {
  90         struct atom_context *ctx = adev->mode_info.atom_context;
  91         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92         struct amdgpu_i2c_bus_rec i2c;
  93         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95         uint16_t data_offset, size;
  96         int i, num_indices;
  97
  98         memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99         i2c.valid = false;
 100
 101         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                 gpio = &i2c_info->asGPIO_Info[0];
 108                 for (i = 0; i < num_indices; i++) {
 109
 110                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                         if (gpio->sucI2cId.ucAccess == id) {
 113                                 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                 break;
 115                         }
 116                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                 }
 119         }
 120
 121         return i2c;
 122 }
 123
 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125 {
 126         struct atom_context *ctx = adev->mode_info.atom_context;
 127         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128         struct amdgpu_i2c_bus_rec i2c;
 129         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131         uint16_t data_offset, size;
 132         int i, num_indices;
 133         char stmp[32];
 134
 135         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                 gpio = &i2c_info->asGPIO_Info[0];
 142                 for (i = 0; i < num_indices; i++) {
 143                         amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                         i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                         if (i2c.valid) {
 148                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                         }
 151                         gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                 }
 154         }
 155 }
 156
 157 struct amdgpu_gpio_rec
 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                             u8 id)
 160 {
 161         struct atom_context *ctx = adev->mode_info.atom_context;
 162         struct amdgpu_gpio_rec gpio;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166         u16 data_offset, size;
 167         int i, num_indices;
 168
 169         memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170         gpio.valid = false;
 171
 172         if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                 pin = gpio_info->asGPIO_Pin;
 179                 for (i = 0; i < num_indices; i++) {
 180                         if (id == pin->ucGPIO_ID) {
 181                                 gpio.id = pin->ucGPIO_ID;
 182                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                 gpio.shift = pin->ucGpioPinBitShift;
 184                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                 gpio.valid = true;
 186                                 break;
 187                         }
 188                         pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                 }
 191         }
 192
 193         return gpio;
 194 }
 195
 196 static struct amdgpu_hpd
 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                        struct amdgpu_gpio_rec *gpio)
 199 {
 200         struct amdgpu_hpd hpd;
 201         u32 reg;
 202
 203         memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205         reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207         hpd.gpio = *gpio;
 208         if (gpio->reg == reg) {
 209                 switch(gpio->mask) {
 210                 case (1 << 0):
 211                         hpd.hpd = AMDGPU_HPD_1;
 212                         break;
 213                 case (1 << 8):
 214                         hpd.hpd = AMDGPU_HPD_2;
 215                         break;
 216                 case (1 << 16):
 217                         hpd.hpd = AMDGPU_HPD_3;
 218                         break;
 219                 case (1 << 24):
 220                         hpd.hpd = AMDGPU_HPD_4;
 221                         break;
 222                 case (1 << 26):
 223                         hpd.hpd = AMDGPU_HPD_5;
 224                         break;
 225                 case (1 << 28):
 226                         hpd.hpd = AMDGPU_HPD_6;
 227                         break;
 228                 default:
 229                         hpd.hpd = AMDGPU_HPD_NONE;
 230                         break;
 231                 }
 232         } else
 233                 hpd.hpd = AMDGPU_HPD_NONE;
 234         return hpd;
 235 }
 236
 237 static const int object_connector_convert[] = {
 238         DRM_MODE_CONNECTOR_Unknown,
 239         DRM_MODE_CONNECTOR_DVII,
 240         DRM_MODE_CONNECTOR_DVII,
 241         DRM_MODE_CONNECTOR_DVID,
 242         DRM_MODE_CONNECTOR_DVID,
 243         DRM_MODE_CONNECTOR_VGA,
 244         DRM_MODE_CONNECTOR_Composite,
 245         DRM_MODE_CONNECTOR_SVIDEO,
 246         DRM_MODE_CONNECTOR_Unknown,
 247         DRM_MODE_CONNECTOR_Unknown,
 248         DRM_MODE_CONNECTOR_9PinDIN,
 249         DRM_MODE_CONNECTOR_Unknown,
 250         DRM_MODE_CONNECTOR_HDMIA,
 251         DRM_MODE_CONNECTOR_HDMIB,
 252         DRM_MODE_CONNECTOR_LVDS,
 253         DRM_MODE_CONNECTOR_9PinDIN,
 254         DRM_MODE_CONNECTOR_Unknown,
 255         DRM_MODE_CONNECTOR_Unknown,
 256         DRM_MODE_CONNECTOR_Unknown,
 257         DRM_MODE_CONNECTOR_DisplayPort,
 258         DRM_MODE_CONNECTOR_eDP,
 259         DRM_MODE_CONNECTOR_Unknown
 260 };
 261
 262 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 265         struct atom_context *ctx = mode_info->atom_context;
 266         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 267         u16 size, data_offset;
 268         u8 frev, crev;
 269         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 270         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 271         ATOM_OBJECT_TABLE *router_obj;
 272         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 273         ATOM_OBJECT_HEADER *obj_header;
 274         int i, j, k, path_size, device_support;
 275         int connector_type;
 276         u16 conn_id, connector_object_id;
 277         struct amdgpu_i2c_bus_rec ddc_bus;
 278         struct amdgpu_router router;
 279         struct amdgpu_gpio_rec gpio;
 280         struct amdgpu_hpd hpd;
 281
 282         if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 283                 return false;
 284
 285         if (crev < 2)
 286                 return false;
 287
 288         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 289         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 290             (ctx->bios + data_offset +
 291              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 292         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 293             (ctx->bios + data_offset +
 294              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 295         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 296             (ctx->bios + data_offset +
 297              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 298         router_obj = (ATOM_OBJECT_TABLE *)
 299                 (ctx->bios + data_offset +
 300                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 301         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 302
 303         path_size = 0;
 304         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 305                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 306                 ATOM_DISPLAY_OBJECT_PATH *path;
 307                 addr += path_size;
 308                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 309                 path_size += le16_to_cpu(path->usSize);
 310
 311                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 312                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 313
 314                         con_obj_id =
 315                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 316                             >> OBJECT_ID_SHIFT;
 317                         con_obj_num =
 318                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 319                             >> ENUM_ID_SHIFT;
 320                         con_obj_type =
 321                             (le16_to_cpu(path->usConnObjectId) &
 322                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 323
 324                         if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
 325                                 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
 326                                           con_obj_id, le16_to_cpu(path->usDeviceTag));
 327                                 continue;
 328                         }
 329
 330                         connector_type =
 331                                 object_connector_convert[con_obj_id];
 332                         connector_object_id = con_obj_id;
 333
 334                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 335                                 continue;
 336
 337                         router.ddc_valid = false;
 338                         router.cd_valid = false;
 339                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 340                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 341
 342                                 grph_obj_id =
 343                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 344                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 345                                 grph_obj_num =
 346                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 347                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 348                                 grph_obj_type =
 349                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 350                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 351
 352                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 353                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 354                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 355                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 356                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 357                                                                 (ctx->bios + data_offset +
 358                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 359                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 360                                                         u16 caps = 0;
 361
 362                                                         while (record->ucRecordSize > 0 &&
 363                                                                record->ucRecordType > 0 &&
 364                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 365                                                                 switch (record->ucRecordType) {
 366                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 367                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 368                                                                                 record;
 369                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 370                                                                         break;
 371                                                                 }
 372                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 373                                                                         ((char *)record + record->ucRecordSize);
 374                                                         }
 375                                                         amdgpu_display_add_encoder(adev, encoder_obj,
 376                                                                                     le16_to_cpu(path->usDeviceTag),
 377                                                                                     caps);
 378                                                 }
 379                                         }
 380                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 381                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 382                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 383                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 384                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 385                                                                 (ctx->bios + data_offset +
 386                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 387                                                         ATOM_I2C_RECORD *i2c_record;
 388                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 389                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 390                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 391                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 392                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 393                                                                 (ctx->bios + data_offset +
 394                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 395                                                         u8 *num_dst_objs = (u8 *)
 396                                                                 ((u8 *)router_src_dst_table + 1 +
 397                                                                  (router_src_dst_table->ucNumberOfSrc * 2));
 398                                                         u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 399                                                         int enum_id;
 400
 401                                                         router.router_id = router_obj_id;
 402                                                         for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 403                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 404                                                                     le16_to_cpu(dst_objs[enum_id]))
 405                                                                         break;
 406                                                         }
 407
 408                                                         while (record->ucRecordSize > 0 &&
 409                                                                record->ucRecordType > 0 &&
 410                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 411                                                                 switch (record->ucRecordType) {
 412                                                                 case ATOM_I2C_RECORD_TYPE:
 413                                                                         i2c_record =
 414                                                                                 (ATOM_I2C_RECORD *)
 415                                                                                 record;
 416                                                                         i2c_config =
 417                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 418                                                                                 &i2c_record->sucI2cId;
 419                                                                         router.i2c_info =
 420                                                                                 amdgpu_atombios_lookup_i2c_gpio(adev,
 421                                                                                                        i2c_config->
 422                                                                                                        ucAccess);
 423                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 424                                                                         break;
 425                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 426                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 427                                                                                 record;
 428                                                                         router.ddc_valid = true;
 429                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 430                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 431                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 432                                                                         break;
 433                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 434                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 435                                                                                 record;
 436                                                                         router.cd_valid = true;
 437                                                                         router.cd_mux_type = cd_path->ucMuxType;
 438                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 439                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 440                                                                         break;
 441                                                                 }
 442                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 443                                                                         ((char *)record + record->ucRecordSize);
 444                                                         }
 445                                                 }
 446                                         }
 447                                 }
 448                         }
 449
 450                         /* look up gpio for ddc, hpd */
 451                         ddc_bus.valid = false;
 452                         hpd.hpd = AMDGPU_HPD_NONE;
 453                         if ((le16_to_cpu(path->usDeviceTag) &
 454                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 455                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 456                                         if (le16_to_cpu(path->usConnObjectId) ==
 457                                             le16_to_cpu(con_obj->asObjects[j].
 458                                                         usObjectID)) {
 459                                                 ATOM_COMMON_RECORD_HEADER
 460                                                     *record =
 461                                                     (ATOM_COMMON_RECORD_HEADER
 462                                                      *)
 463                                                     (ctx->bios + data_offset +
 464                                                      le16_to_cpu(con_obj->
 465                                                                  asObjects[j].
 466                                                                  usRecordOffset));
 467                                                 ATOM_I2C_RECORD *i2c_record;
 468                                                 ATOM_HPD_INT_RECORD *hpd_record;
 469                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 470
 471                                                 while (record->ucRecordSize > 0 &&
 472                                                        record->ucRecordType > 0 &&
 473                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 474                                                         switch (record->ucRecordType) {
 475                                                         case ATOM_I2C_RECORD_TYPE:
 476                                                                 i2c_record =
 477                                                                     (ATOM_I2C_RECORD *)
 478                                                                         record;
 479                                                                 i2c_config =
 480                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 481                                                                         &i2c_record->sucI2cId;
 482                                                                 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 483                                                                                                  i2c_config->
 484                                                                                                  ucAccess);
 485                                                                 break;
 486                                                         case ATOM_HPD_INT_RECORD_TYPE:
 487                                                                 hpd_record =
 488                                                                         (ATOM_HPD_INT_RECORD *)
 489                                                                         record;
 490                                                                 gpio = amdgpu_atombios_lookup_gpio(adev,
 491                                                                                           hpd_record->ucHPDIntGPIOID);
 492                                                                 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 493                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 494                                                                 break;
 495                                                         }
 496                                                         record =
 497                                                             (ATOM_COMMON_RECORD_HEADER
 498                                                              *) ((char *)record
 499                                                                  +
 500                                                                  record->
 501                                                                  ucRecordSize);
 502                                                 }
 503                                                 break;
 504                                         }
 505                                 }
 506                         }
 507
 508                         /* needed for aux chan transactions */
 509                         ddc_bus.hpd = hpd.hpd;
 510
 511                         conn_id = le16_to_cpu(path->usConnObjectId);
 512
 513                         amdgpu_display_add_connector(adev,
 514                                                       conn_id,
 515                                                       le16_to_cpu(path->usDeviceTag),
 516                                                       connector_type, &ddc_bus,
 517                                                       connector_object_id,
 518                                                       &hpd,
 519                                                       &router);
 520
 521                 }
 522         }
 523
 524         amdgpu_link_encoder_connector(adev->ddev);
 525
 526         return true;
 527 }
 528
 529 union firmware_info {
 530         ATOM_FIRMWARE_INFO info;
 531         ATOM_FIRMWARE_INFO_V1_2 info_12;
 532         ATOM_FIRMWARE_INFO_V1_3 info_13;
 533         ATOM_FIRMWARE_INFO_V1_4 info_14;
 534         ATOM_FIRMWARE_INFO_V2_1 info_21;
 535         ATOM_FIRMWARE_INFO_V2_2 info_22;
 536 };
 537
 538 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 539 {
 540         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 541         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 542         uint8_t frev, crev;
 543         uint16_t data_offset;
 544         int ret = -EINVAL;
 545
 546         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 547                                    &frev, &crev, &data_offset)) {
 548                 int i;
 549                 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 550                 struct amdgpu_pll *spll = &adev->clock.spll;
 551                 struct amdgpu_pll *mpll = &adev->clock.mpll;
 552                 union firmware_info *firmware_info =
 553                         (union firmware_info *)(mode_info->atom_context->bios +
 554                                                 data_offset);
 555                 /* pixel clocks */
 556                 ppll->reference_freq =
 557                     le16_to_cpu(firmware_info->info.usReferenceClock);
 558                 ppll->reference_div = 0;
 559
 560                 ppll->pll_out_min =
 561                         le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 562                 ppll->pll_out_max =
 563                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 564
 565                 ppll->lcd_pll_out_min =
 566                         le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 567                 if (ppll->lcd_pll_out_min == 0)
 568                         ppll->lcd_pll_out_min = ppll->pll_out_min;
 569                 ppll->lcd_pll_out_max =
 570                         le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 571                 if (ppll->lcd_pll_out_max == 0)
 572                         ppll->lcd_pll_out_max = ppll->pll_out_max;
 573
 574                 if (ppll->pll_out_min == 0)
 575                         ppll->pll_out_min = 64800;
 576
 577                 ppll->pll_in_min =
 578                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 579                 ppll->pll_in_max =
 580                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 581
 582                 ppll->min_post_div = 2;
 583                 ppll->max_post_div = 0x7f;
 584                 ppll->min_frac_feedback_div = 0;
 585                 ppll->max_frac_feedback_div = 9;
 586                 ppll->min_ref_div = 2;
 587                 ppll->max_ref_div = 0x3ff;
 588                 ppll->min_feedback_div = 4;
 589                 ppll->max_feedback_div = 0xfff;
 590                 ppll->best_vco = 0;
 591
 592                 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 593                         adev->clock.ppll[i] = *ppll;
 594
 595                 /* system clock */
 596                 spll->reference_freq =
 597                         le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 598                 spll->reference_div = 0;
 599
 600                 spll->pll_out_min =
 601                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 602                 spll->pll_out_max =
 603                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 604
 605                 /* ??? */
 606                 if (spll->pll_out_min == 0)
 607                         spll->pll_out_min = 64800;
 608
 609                 spll->pll_in_min =
 610                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 611                 spll->pll_in_max =
 612                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 613
 614                 spll->min_post_div = 1;
 615                 spll->max_post_div = 1;
 616                 spll->min_ref_div = 2;
 617                 spll->max_ref_div = 0xff;
 618                 spll->min_feedback_div = 4;
 619                 spll->max_feedback_div = 0xff;
 620                 spll->best_vco = 0;
 621
 622                 /* memory clock */
 623                 mpll->reference_freq =
 624                         le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 625                 mpll->reference_div = 0;
 626
 627                 mpll->pll_out_min =
 628                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 629                 mpll->pll_out_max =
 630                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 631
 632                 /* ??? */
 633                 if (mpll->pll_out_min == 0)
 634                         mpll->pll_out_min = 64800;
 635
 636                 mpll->pll_in_min =
 637                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 638                 mpll->pll_in_max =
 639                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 640
 641                 adev->clock.default_sclk =
 642                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 643                 adev->clock.default_mclk =
 644                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 645
 646                 mpll->min_post_div = 1;
 647                 mpll->max_post_div = 1;
 648                 mpll->min_ref_div = 2;
 649                 mpll->max_ref_div = 0xff;
 650                 mpll->min_feedback_div = 4;
 651                 mpll->max_feedback_div = 0xff;
 652                 mpll->best_vco = 0;
 653
 654                 /* disp clock */
 655                 adev->clock.default_dispclk =
 656                         le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 657                 /* set a reasonable default for DP */
 658                 if (adev->clock.default_dispclk < 53900) {
 659                         DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 660                                  adev->clock.default_dispclk / 100);
 661                         adev->clock.default_dispclk = 60000;
 662                 }
 663                 adev->clock.dp_extclk =
 664                         le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 665                 adev->clock.current_dispclk = adev->clock.default_dispclk;
 666
 667                 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 668                 if (adev->clock.max_pixel_clock == 0)
 669                         adev->clock.max_pixel_clock = 40000;
 670
 671                 /* not technically a clock, but... */
 672                 adev->mode_info.firmware_flags =
 673                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 674
 675                 ret = 0;
 676         }
 677
 678         adev->pm.current_sclk = adev->clock.default_sclk;
 679         adev->pm.current_mclk = adev->clock.default_mclk;
 680
 681         return ret;
 682 }
 683
 684 union gfx_info {
 685         ATOM_GFX_INFO_V2_1 info;
 686 };
 687
 688 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
 689 {
 690         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 691         int index = GetIndexIntoMasterTable(DATA, GFX_Info);
 692         uint8_t frev, crev;
 693         uint16_t data_offset;
 694         int ret = -EINVAL;
 695
 696         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 697                                    &frev, &crev, &data_offset)) {
 698                 union gfx_info *gfx_info = (union gfx_info *)
 699                         (mode_info->atom_context->bios + data_offset);
 700
 701                 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
 702                 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
 703                 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
 704                 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
 705                 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
 706                 adev->gfx.config.max_texture_channel_caches =
 707                         gfx_info->info.max_texture_channel_caches;
 708
 709                 ret = 0;
 710         }
 711         return ret;
 712 }
 713
 714 union igp_info {
 715         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 716         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 717         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 718         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 719         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 720         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 721 };
 722
 723 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 724                                                  struct amdgpu_atom_ss *ss,
 725                                                  int id)
 726 {
 727         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 728         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 729         u16 data_offset, size;
 730         union igp_info *igp_info;
 731         u8 frev, crev;
 732         u16 percentage = 0, rate = 0;
 733
 734         /* get any igp specific overrides */
 735         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 736                                    &frev, &crev, &data_offset)) {
 737                 igp_info = (union igp_info *)
 738                         (mode_info->atom_context->bios + data_offset);
 739                 switch (crev) {
 740                 case 6:
 741                         switch (id) {
 742                         case ASIC_INTERNAL_SS_ON_TMDS:
 743                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 744                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 745                                 break;
 746                         case ASIC_INTERNAL_SS_ON_HDMI:
 747                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 748                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 749                                 break;
 750                         case ASIC_INTERNAL_SS_ON_LVDS:
 751                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 752                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 753                                 break;
 754                         }
 755                         break;
 756                 case 7:
 757                         switch (id) {
 758                         case ASIC_INTERNAL_SS_ON_TMDS:
 759                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 760                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 761                                 break;
 762                         case ASIC_INTERNAL_SS_ON_HDMI:
 763                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 764                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 765                                 break;
 766                         case ASIC_INTERNAL_SS_ON_LVDS:
 767                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 768                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 769                                 break;
 770                         }
 771                         break;
 772                 case 8:
 773                         switch (id) {
 774                         case ASIC_INTERNAL_SS_ON_TMDS:
 775                                 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 776                                 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 777                                 break;
 778                         case ASIC_INTERNAL_SS_ON_HDMI:
 779                                 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 780                                 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 781                                 break;
 782                         case ASIC_INTERNAL_SS_ON_LVDS:
 783                                 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 784                                 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 785                                 break;
 786                         }
 787                         break;
 788                 case 9:
 789                         switch (id) {
 790                         case ASIC_INTERNAL_SS_ON_TMDS:
 791                                 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 792                                 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 793                                 break;
 794                         case ASIC_INTERNAL_SS_ON_HDMI:
 795                                 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 796                                 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 797                                 break;
 798                         case ASIC_INTERNAL_SS_ON_LVDS:
 799                                 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 800                                 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 801                                 break;
 802                         }
 803                         break;
 804                 default:
 805                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 806                         break;
 807                 }
 808                 if (percentage)
 809                         ss->percentage = percentage;
 810                 if (rate)
 811                         ss->rate = rate;
 812         }
 813 }
 814
 815 union asic_ss_info {
 816         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 817         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 818         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 819 };
 820
 821 union asic_ss_assignment {
 822         struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 823         struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 824         struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 825 };
 826
 827 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 828                                       struct amdgpu_atom_ss *ss,
 829                                       int id, u32 clock)
 830 {
 831         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 832         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 833         uint16_t data_offset, size;
 834         union asic_ss_info *ss_info;
 835         union asic_ss_assignment *ss_assign;
 836         uint8_t frev, crev;
 837         int i, num_indices;
 838
 839         if (id == ASIC_INTERNAL_MEMORY_SS) {
 840                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 841                         return false;
 842         }
 843         if (id == ASIC_INTERNAL_ENGINE_SS) {
 844                 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 845                         return false;
 846         }
 847
 848         memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 849         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 850                                    &frev, &crev, &data_offset)) {
 851
 852                 ss_info =
 853                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 854
 855                 switch (frev) {
 856                 case 1:
 857                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 858                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 859
 860                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 861                         for (i = 0; i < num_indices; i++) {
 862                                 if ((ss_assign->v1.ucClockIndication == id) &&
 863                                     (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 864                                         ss->percentage =
 865                                                 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 866                                         ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 867                                         ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 868                                         ss->percentage_divider = 100;
 869                                         return true;
 870                                 }
 871                                 ss_assign = (union asic_ss_assignment *)
 872                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 873                         }
 874                         break;
 875                 case 2:
 876                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 877                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 878                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 879                         for (i = 0; i < num_indices; i++) {
 880                                 if ((ss_assign->v2.ucClockIndication == id) &&
 881                                     (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 882                                         ss->percentage =
 883                                                 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 884                                         ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 885                                         ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 886                                         ss->percentage_divider = 100;
 887                                         if ((crev == 2) &&
 888                                             ((id == ASIC_INTERNAL_ENGINE_SS) ||
 889                                              (id == ASIC_INTERNAL_MEMORY_SS)))
 890                                                 ss->rate /= 100;
 891                                         return true;
 892                                 }
 893                                 ss_assign = (union asic_ss_assignment *)
 894                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 895                         }
 896                         break;
 897                 case 3:
 898                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 899                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 900                         ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 901                         for (i = 0; i < num_indices; i++) {
 902                                 if ((ss_assign->v3.ucClockIndication == id) &&
 903                                     (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 904                                         ss->percentage =
 905                                                 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 906                                         ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 907                                         ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 908                                         if (ss_assign->v3.ucSpreadSpectrumMode &
 909                                             SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 910                                                 ss->percentage_divider = 1000;
 911                                         else
 912                                                 ss->percentage_divider = 100;
 913                                         if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 914                                             (id == ASIC_INTERNAL_MEMORY_SS))
 915                                                 ss->rate /= 100;
 916                                         if (adev->flags & AMD_IS_APU)
 917                                                 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 918                                         return true;
 919                                 }
 920                                 ss_assign = (union asic_ss_assignment *)
 921                                         ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 922                         }
 923                         break;
 924                 default:
 925                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 926                         break;
 927                 }
 928
 929         }
 930         return false;
 931 }
 932
 933 union get_clock_dividers {
 934         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
 935         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
 936         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
 937         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
 938         struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
 939         struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
 940         struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
 941 };
 942
 943 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
 944                                        u8 clock_type,
 945                                        u32 clock,
 946                                        bool strobe_mode,
 947                                        struct atom_clock_dividers *dividers)
 948 {
 949         union get_clock_dividers args;
 950         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
 951         u8 frev, crev;
 952
 953         memset(&args, 0, sizeof(args));
 954         memset(dividers, 0, sizeof(struct atom_clock_dividers));
 955
 956         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
 957                 return -EINVAL;
 958
 959         switch (crev) {
 960         case 4:
 961                 /* fusion */
 962                 args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
 963
 964                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 965
 966                 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
 967                 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
 968                 break;
 969         case 6:
 970                 /* CI */
 971                 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
 972                 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
 973                 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
 974
 975                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 976
 977                 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
 978                 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
 979                 dividers->ref_div = args.v6_out.ucPllRefDiv;
 980                 dividers->post_div = args.v6_out.ucPllPostDiv;
 981                 dividers->flags = args.v6_out.ucPllCntlFlag;
 982                 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
 983                 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
 984                 break;
 985         default:
 986                 return -EINVAL;
 987         }
 988         return 0;
 989 }
 990
 991 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
 992                                             u32 clock,
 993                                             bool strobe_mode,
 994                                             struct atom_mpll_param *mpll_param)
 995 {
 996         COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
 997         int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
 998         u8 frev, crev;
 999
1000         memset(&args, 0, sizeof(args));
1001         memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1002
1003         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1004                 return -EINVAL;
1005
1006         switch (frev) {
1007         case 2:
1008                 switch (crev) {
1009                 case 1:
1010                         /* SI */
1011                         args.ulClock = cpu_to_le32(clock);      /* 10 khz */
1012                         args.ucInputFlag = 0;
1013                         if (strobe_mode)
1014                                 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1015
1016                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1017
1018                         mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1019                         mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1020                         mpll_param->post_div = args.ucPostDiv;
1021                         mpll_param->dll_speed = args.ucDllSpeed;
1022                         mpll_param->bwcntl = args.ucBWCntl;
1023                         mpll_param->vco_mode =
1024                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1025                         mpll_param->yclk_sel =
1026                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1027                         mpll_param->qdr =
1028                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1029                         mpll_param->half_rate =
1030                                 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1031                         break;
1032                 default:
1033                         return -EINVAL;
1034                 }
1035                 break;
1036         default:
1037                 return -EINVAL;
1038         }
1039         return 0;
1040 }
1041
1042 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1043 {
1044         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1045         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1046
1047         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1048         return le32_to_cpu(args.ulReturnEngineClock);
1049 }
1050
1051 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1052 {
1053         GET_MEMORY_CLOCK_PS_ALLOCATION args;
1054         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1055
1056         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1057         return le32_to_cpu(args.ulReturnMemoryClock);
1058 }
1059
1060 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1061                                       uint32_t eng_clock)
1062 {
1063         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1064         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1065
1066         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
1067
1068         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1069 }
1070
1071 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1072                                       uint32_t mem_clock)
1073 {
1074         SET_MEMORY_CLOCK_PS_ALLOCATION args;
1075         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1076
1077         if (adev->flags & AMD_IS_APU)
1078                 return;
1079
1080         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
1081
1082         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1083 }
1084
1085 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1086                                              u32 eng_clock, u32 mem_clock)
1087 {
1088         SET_ENGINE_CLOCK_PS_ALLOCATION args;
1089         int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1090         u32 tmp;
1091
1092         memset(&args, 0, sizeof(args));
1093
1094         tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1095         tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1096
1097         args.ulTargetEngineClock = cpu_to_le32(tmp);
1098         if (mem_clock)
1099                 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1100
1101         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1102 }
1103
1104 union set_voltage {
1105         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1106         struct _SET_VOLTAGE_PARAMETERS v1;
1107         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1108         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1109 };
1110
1111 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1112                                  u16 voltage_level,
1113                                  u8 voltage_type)
1114 {
1115         union set_voltage args;
1116         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1117         u8 frev, crev, volt_index = voltage_level;
1118
1119         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1120                 return;
1121
1122         /* 0xff01 is a flag rather then an actual voltage */
1123         if (voltage_level == 0xff01)
1124                 return;
1125
1126         switch (crev) {
1127         case 1:
1128                 args.v1.ucVoltageType = voltage_type;
1129                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1130                 args.v1.ucVoltageIndex = volt_index;
1131                 break;
1132         case 2:
1133                 args.v2.ucVoltageType = voltage_type;
1134                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1135                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1136                 break;
1137         case 3:
1138                 args.v3.ucVoltageType = voltage_type;
1139                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1140                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1141                 break;
1142         default:
1143                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1144                 return;
1145         }
1146
1147         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1148 }
1149
1150 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1151                                               u16 *leakage_id)
1152 {
1153         union set_voltage args;
1154         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1155         u8 frev, crev;
1156
1157         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1158                 return -EINVAL;
1159
1160         switch (crev) {
1161         case 3:
1162         case 4:
1163                 args.v3.ucVoltageType = 0;
1164                 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1165                 args.v3.usVoltageLevel = 0;
1166
1167                 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1168
1169                 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1170                 break;
1171         default:
1172                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1173                 return -EINVAL;
1174         }
1175
1176         return 0;
1177 }
1178
1179 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1180                                                              u16 *vddc, u16 *vddci,
1181                                                              u16 virtual_voltage_id,
1182                                                              u16 vbios_voltage_id)
1183 {
1184         int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1185         u8 frev, crev;
1186         u16 data_offset, size;
1187         int i, j;
1188         ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1189         u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1190
1191         *vddc = 0;
1192         *vddci = 0;
1193
1194         if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1195                                     &frev, &crev, &data_offset))
1196                 return -EINVAL;
1197
1198         profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1199                 (adev->mode_info.atom_context->bios + data_offset);
1200
1201         switch (frev) {
1202         case 1:
1203                 return -EINVAL;
1204         case 2:
1205                 switch (crev) {
1206                 case 1:
1207                         if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1208                                 return -EINVAL;
1209                         leakage_bin = (u16 *)
1210                                 (adev->mode_info.atom_context->bios + data_offset +
1211                                  le16_to_cpu(profile->usLeakageBinArrayOffset));
1212                         vddc_id_buf = (u16 *)
1213                                 (adev->mode_info.atom_context->bios + data_offset +
1214                                  le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1215                         vddc_buf = (u16 *)
1216                                 (adev->mode_info.atom_context->bios + data_offset +
1217                                  le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1218                         vddci_id_buf = (u16 *)
1219                                 (adev->mode_info.atom_context->bios + data_offset +
1220                                  le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1221                         vddci_buf = (u16 *)
1222                                 (adev->mode_info.atom_context->bios + data_offset +
1223                                  le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1224
1225                         if (profile->ucElbVDDC_Num > 0) {
1226                                 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1227                                         if (vddc_id_buf[i] == virtual_voltage_id) {
1228                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1229                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1230                                                                 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1231                                                                 break;
1232                                                         }
1233                                                 }
1234                                                 break;
1235                                         }
1236                                 }
1237                         }
1238                         if (profile->ucElbVDDCI_Num > 0) {
1239                                 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1240                                         if (vddci_id_buf[i] == virtual_voltage_id) {
1241                                                 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1242                                                         if (vbios_voltage_id <= leakage_bin[j]) {
1243                                                                 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1244                                                                 break;
1245                                                         }
1246                                                 }
1247                                                 break;
1248                                         }
1249                                 }
1250                         }
1251                         break;
1252                 default:
1253                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1254                         return -EINVAL;
1255                 }
1256                 break;
1257         default:
1258                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1259                 return -EINVAL;
1260         }
1261
1262         return 0;
1263 }
1264
1265 union get_voltage_info {
1266         struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1267         struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1268 };
1269
1270 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1271                                     u16 virtual_voltage_id,
1272                                     u16 *voltage)
1273 {
1274         int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1275         u32 entry_id;
1276         u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1277         union get_voltage_info args;
1278
1279         for (entry_id = 0; entry_id < count; entry_id++) {
1280                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1281                     virtual_voltage_id)
1282                         break;
1283         }
1284
1285         if (entry_id >= count)
1286                 return -EINVAL;
1287
1288         args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1289         args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1290         args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1291         args.in.ulSCLKFreq =
1292                 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1293
1294         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1295
1296         *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1297
1298         return 0;
1299 }
1300
1301 union voltage_object_info {
1302         struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1303         struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1304         struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1305 };
1306
1307 union voltage_object {
1308         struct _ATOM_VOLTAGE_OBJECT v1;
1309         struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1310         union _ATOM_VOLTAGE_OBJECT_V3 v3;
1311 };
1312
1313
1314 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1315                                                                         u8 voltage_type, u8 voltage_mode)
1316 {
1317         u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1318         u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1319         u8 *start = (u8*)v3;
1320
1321         while (offset < size) {
1322                 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1323                 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1324                     (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1325                         return vo;
1326                 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1327         }
1328         return NULL;
1329 }
1330
1331 bool
1332 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1333                                 u8 voltage_type, u8 voltage_mode)
1334 {
1335         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1336         u8 frev, crev;
1337         u16 data_offset, size;
1338         union voltage_object_info *voltage_info;
1339
1340         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1341                                    &frev, &crev, &data_offset)) {
1342                 voltage_info = (union voltage_object_info *)
1343                         (adev->mode_info.atom_context->bios + data_offset);
1344
1345                 switch (frev) {
1346                 case 3:
1347                         switch (crev) {
1348                         case 1:
1349                                 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1350                                                                   voltage_type, voltage_mode))
1351                                         return true;
1352                                 break;
1353                         default:
1354                                 DRM_ERROR("unknown voltage object table\n");
1355                                 return false;
1356                         }
1357                         break;
1358                 default:
1359                         DRM_ERROR("unknown voltage object table\n");
1360                         return false;
1361                 }
1362
1363         }
1364         return false;
1365 }
1366
1367 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1368                                       u8 voltage_type, u8 voltage_mode,
1369                                       struct atom_voltage_table *voltage_table)
1370 {
1371         int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1372         u8 frev, crev;
1373         u16 data_offset, size;
1374         int i;
1375         union voltage_object_info *voltage_info;
1376         union voltage_object *voltage_object = NULL;
1377
1378         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1379                                    &frev, &crev, &data_offset)) {
1380                 voltage_info = (union voltage_object_info *)
1381                         (adev->mode_info.atom_context->bios + data_offset);
1382
1383                 switch (frev) {
1384                 case 3:
1385                         switch (crev) {
1386                         case 1:
1387                                 voltage_object = (union voltage_object *)
1388                                         amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1389                                                                       voltage_type, voltage_mode);
1390                                 if (voltage_object) {
1391                                         ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1392                                                 &voltage_object->v3.asGpioVoltageObj;
1393                                         VOLTAGE_LUT_ENTRY_V2 *lut;
1394                                         if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1395                                                 return -EINVAL;
1396                                         lut = &gpio->asVolGpioLut[0];
1397                                         for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1398                                                 voltage_table->entries[i].value =
1399                                                         le16_to_cpu(lut->usVoltageValue);
1400                                                 voltage_table->entries[i].smio_low =
1401                                                         le32_to_cpu(lut->ulVoltageId);
1402                                                 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1403                                                         ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1404                                         }
1405                                         voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1406                                         voltage_table->count = gpio->ucGpioEntryNum;
1407                                         voltage_table->phase_delay = gpio->ucPhaseDelay;
1408                                         return 0;
1409                                 }
1410                                 break;
1411                         default:
1412                                 DRM_ERROR("unknown voltage object table\n");
1413                                 return -EINVAL;
1414                         }
1415                         break;
1416                 default:
1417                         DRM_ERROR("unknown voltage object table\n");
1418                         return -EINVAL;
1419                 }
1420         }
1421         return -EINVAL;
1422 }
1423
1424 union vram_info {
1425         struct _ATOM_VRAM_INFO_V3 v1_3;
1426         struct _ATOM_VRAM_INFO_V4 v1_4;
1427         struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1428 };
1429
1430 #define MEM_ID_MASK           0xff000000
1431 #define MEM_ID_SHIFT          24
1432 #define CLOCK_RANGE_MASK      0x00ffffff
1433 #define CLOCK_RANGE_SHIFT     0
1434 #define LOW_NIBBLE_MASK       0xf
1435 #define DATA_EQU_PREV         0
1436 #define DATA_FROM_TABLE       4
1437
1438 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1439                                       u8 module_index,
1440                                       struct atom_mc_reg_table *reg_table)
1441 {
1442         int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1443         u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1444         u32 i = 0, j;
1445         u16 data_offset, size;
1446         union vram_info *vram_info;
1447
1448         memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1449
1450         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1451                                    &frev, &crev, &data_offset)) {
1452                 vram_info = (union vram_info *)
1453                         (adev->mode_info.atom_context->bios + data_offset);
1454                 switch (frev) {
1455                 case 1:
1456                         DRM_ERROR("old table version %d, %d\n", frev, crev);
1457                         return -EINVAL;
1458                 case 2:
1459                         switch (crev) {
1460                         case 1:
1461                                 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1462                                         ATOM_INIT_REG_BLOCK *reg_block =
1463                                                 (ATOM_INIT_REG_BLOCK *)
1464                                                 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1465                                         ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1466                                                 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1467                                                 ((u8 *)reg_block + (2 * sizeof(u16)) +
1468                                                  le16_to_cpu(reg_block->usRegIndexTblSize));
1469                                         ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1470                                         num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1471                                                            sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1472                                         if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1473                                                 return -EINVAL;
1474                                         while (i < num_entries) {
1475                                                 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1476                                                         break;
1477                                                 reg_table->mc_reg_address[i].s1 =
1478                                                         (u16)(le16_to_cpu(format->usRegIndex));
1479                                                 reg_table->mc_reg_address[i].pre_reg_data =
1480                                                         (u8)(format->ucPreRegDataLength);
1481                                                 i++;
1482                                                 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1483                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1484                                         }
1485                                         reg_table->last = i;
1486                                         while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1487                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1488                                                 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1489                                                                 >> MEM_ID_SHIFT);
1490                                                 if (module_index == t_mem_id) {
1491                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1492                                                                 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1493                                                                       >> CLOCK_RANGE_SHIFT);
1494                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
1495                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1496                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1497                                                                                 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1498                                                                         j++;
1499                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1500                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1501                                                                                 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1502                                                                 }
1503                                                         }
1504                                                         num_ranges++;
1505                                                 }
1506                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1507                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1508                                         }
1509                                         if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1510                                                 return -EINVAL;
1511                                         reg_table->num_entries = num_ranges;
1512                                 } else
1513                                         return -EINVAL;
1514                                 break;
1515                         default:
1516                                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1517                                 return -EINVAL;
1518                         }
1519                         break;
1520                 default:
1521                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1522                         return -EINVAL;
1523                 }
1524                 return 0;
1525         }
1526         return -EINVAL;
1527 }
1528
1529 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1530 {
1531         int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1532         u8 frev, crev;
1533         u16 data_offset, size;
1534
1535         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1536                                           &frev, &crev, &data_offset))
1537                 return true;
1538
1539         return false;
1540 }
1541
1542 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1543 {
1544         uint32_t bios_6_scratch;
1545
1546         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1547
1548         if (lock) {
1549                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1550                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1551         } else {
1552                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1553                 bios_6_scratch |= ATOM_S6_ACC_MODE;
1554         }
1555
1556         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1557 }
1558
1559 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1560 {
1561         uint32_t bios_2_scratch, bios_6_scratch;
1562
1563         bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1564         bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1565
1566         /* let the bios control the backlight */
1567         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1568
1569         /* tell the bios not to handle mode switching */
1570         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1571
1572         /* clear the vbios dpms state */
1573         bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1574
1575         WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1576         WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1577 }
1578
1579 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1580 {
1581         int i;
1582
1583         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1584                 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1585 }
1586
1587 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1588 {
1589         int i;
1590
1591         for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1592                 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1593 }
1594
1595 /* Atom needs data in little endian format
1596  * so swap as appropriate when copying data to
1597  * or from atom. Note that atom operates on
1598  * dw units.
1599  */
1600 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1601 {
1602 #ifdef __BIG_ENDIAN
1603         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1604         u32 *dst32, *src32;
1605         int i;
1606
1607         memcpy(src_tmp, src, num_bytes);
1608         src32 = (u32 *)src_tmp;
1609         dst32 = (u32 *)dst_tmp;
1610         if (to_le) {
1611                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1612                         dst32[i] = cpu_to_le32(src32[i]);
1613                 memcpy(dst, dst_tmp, num_bytes);
1614         } else {
1615                 u8 dws = num_bytes & ~3;
1616                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1617                         dst32[i] = le32_to_cpu(src32[i]);
1618                 memcpy(dst, dst_tmp, dws);
1619                 if (num_bytes % 4) {
1620                         for (i = 0; i < (num_bytes % 4); i++)
1621                                 dst[dws+i] = dst_tmp[dws+i];
1622                 }
1623         }
1624 #else
1625         memcpy(dst, src, num_bytes);
1626 #endif
1627 }