drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #include "amd_pcie.h"
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #include "cik.h"
  44 #endif
  45 #include "vi.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  49 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  50
  51 static const char *amdgpu_asic_name[] = {
  52         "BONAIRE",
  53         "KAVERI",
  54         "KABINI",
  55         "HAWAII",
  56         "MULLINS",
  57         "TOPAZ",
  58         "TONGA",
  59         "FIJI",
  60         "CARRIZO",
  61         "STONEY",
  62         "POLARIS10",
  63         "POLARIS11",
  64         "LAST",
  65 };
  66
  67 bool amdgpu_device_is_px(struct drm_device *dev)
  68 {
  69         struct amdgpu_device *adev = dev->dev_private;
  70
  71         if (adev->flags & AMD_IS_PX)
  72                 return true;
  73         return false;
  74 }
  75
  76 /*
  77  * MMIO register access helper functions.
  78  */
  79 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  80                         bool always_indirect)
  81 {
  82         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  83                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  84         else {
  85                 unsigned long flags;
  86                 uint32_t ret;
  87
  88                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  89                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  90                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  91                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  92
  93                 return ret;
  94         }
  95 }
  96
  97 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  98                     bool always_indirect)
  99 {
 100         if ((reg * 4) < adev->rmmio_size && !always_indirect)
 101                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 102         else {
 103                 unsigned long flags;
 104
 105                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 106                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 107                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 108                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 109         }
 110 }
 111
 112 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 113 {
 114         if ((reg * 4) < adev->rio_mem_size)
 115                 return ioread32(adev->rio_mem + (reg * 4));
 116         else {
 117                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 118                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 119         }
 120 }
 121
 122 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 123 {
 124
 125         if ((reg * 4) < adev->rio_mem_size)
 126                 iowrite32(v, adev->rio_mem + (reg * 4));
 127         else {
 128                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 129                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 130         }
 131 }
 132
 133 /**
 134  * amdgpu_mm_rdoorbell - read a doorbell dword
 135  *
 136  * @adev: amdgpu_device pointer
 137  * @index: doorbell index
 138  *
 139  * Returns the value in the doorbell aperture at the
 140  * requested doorbell index (CIK).
 141  */
 142 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 143 {
 144         if (index < adev->doorbell.num_doorbells) {
 145                 return readl(adev->doorbell.ptr + index);
 146         } else {
 147                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 148                 return 0;
 149         }
 150 }
 151
 152 /**
 153  * amdgpu_mm_wdoorbell - write a doorbell dword
 154  *
 155  * @adev: amdgpu_device pointer
 156  * @index: doorbell index
 157  * @v: value to write
 158  *
 159  * Writes @v to the doorbell aperture at the
 160  * requested doorbell index (CIK).
 161  */
 162 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 163 {
 164         if (index < adev->doorbell.num_doorbells) {
 165                 writel(v, adev->doorbell.ptr + index);
 166         } else {
 167                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 168         }
 169 }
 170
 171 /**
 172  * amdgpu_invalid_rreg - dummy reg read function
 173  *
 174  * @adev: amdgpu device pointer
 175  * @reg: offset of register
 176  *
 177  * Dummy register read function.  Used for register blocks
 178  * that certain asics don't have (all asics).
 179  * Returns the value in the register.
 180  */
 181 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 182 {
 183         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 184         BUG();
 185         return 0;
 186 }
 187
 188 /**
 189  * amdgpu_invalid_wreg - dummy reg write function
 190  *
 191  * @adev: amdgpu device pointer
 192  * @reg: offset of register
 193  * @v: value to write to the register
 194  *
 195  * Dummy register read function.  Used for register blocks
 196  * that certain asics don't have (all asics).
 197  */
 198 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 199 {
 200         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 201                   reg, v);
 202         BUG();
 203 }
 204
 205 /**
 206  * amdgpu_block_invalid_rreg - dummy reg read function
 207  *
 208  * @adev: amdgpu device pointer
 209  * @block: offset of instance
 210  * @reg: offset of register
 211  *
 212  * Dummy register read function.  Used for register blocks
 213  * that certain asics don't have (all asics).
 214  * Returns the value in the register.
 215  */
 216 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 217                                           uint32_t block, uint32_t reg)
 218 {
 219         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 220                   reg, block);
 221         BUG();
 222         return 0;
 223 }
 224
 225 /**
 226  * amdgpu_block_invalid_wreg - dummy reg write function
 227  *
 228  * @adev: amdgpu device pointer
 229  * @block: offset of instance
 230  * @reg: offset of register
 231  * @v: value to write to the register
 232  *
 233  * Dummy register read function.  Used for register blocks
 234  * that certain asics don't have (all asics).
 235  */
 236 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 237                                       uint32_t block,
 238                                       uint32_t reg, uint32_t v)
 239 {
 240         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 241                   reg, block, v);
 242         BUG();
 243 }
 244
 245 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 246 {
 247         int r;
 248
 249         if (adev->vram_scratch.robj == NULL) {
 250                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 251                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 252                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 253                                      NULL, NULL, &adev->vram_scratch.robj);
 254                 if (r) {
 255                         return r;
 256                 }
 257         }
 258
 259         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 260         if (unlikely(r != 0))
 261                 return r;
 262         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 263                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 264         if (r) {
 265                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 266                 return r;
 267         }
 268         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 269                                 (void **)&adev->vram_scratch.ptr);
 270         if (r)
 271                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 272         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 273
 274         return r;
 275 }
 276
 277 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 278 {
 279         int r;
 280
 281         if (adev->vram_scratch.robj == NULL) {
 282                 return;
 283         }
 284         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 285         if (likely(r == 0)) {
 286                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 287                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 288                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 289         }
 290         amdgpu_bo_unref(&adev->vram_scratch.robj);
 291 }
 292
 293 /**
 294  * amdgpu_program_register_sequence - program an array of registers.
 295  *
 296  * @adev: amdgpu_device pointer
 297  * @registers: pointer to the register array
 298  * @array_size: size of the register array
 299  *
 300  * Programs an array or registers with and and or masks.
 301  * This is a helper for setting golden registers.
 302  */
 303 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 304                                       const u32 *registers,
 305                                       const u32 array_size)
 306 {
 307         u32 tmp, reg, and_mask, or_mask;
 308         int i;
 309
 310         if (array_size % 3)
 311                 return;
 312
 313         for (i = 0; i < array_size; i +=3) {
 314                 reg = registers[i + 0];
 315                 and_mask = registers[i + 1];
 316                 or_mask = registers[i + 2];
 317
 318                 if (and_mask == 0xffffffff) {
 319                         tmp = or_mask;
 320                 } else {
 321                         tmp = RREG32(reg);
 322                         tmp &= ~and_mask;
 323                         tmp |= or_mask;
 324                 }
 325                 WREG32(reg, tmp);
 326         }
 327 }
 328
 329 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 330 {
 331         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 332 }
 333
 334 /*
 335  * GPU doorbell aperture helpers function.
 336  */
 337 /**
 338  * amdgpu_doorbell_init - Init doorbell driver information.
 339  *
 340  * @adev: amdgpu_device pointer
 341  *
 342  * Init doorbell driver information (CIK)
 343  * Returns 0 on success, error on failure.
 344  */
 345 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 346 {
 347         /* doorbell bar mapping */
 348         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 349         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 350
 351         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 352                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 353         if (adev->doorbell.num_doorbells == 0)
 354                 return -EINVAL;
 355
 356         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 357         if (adev->doorbell.ptr == NULL) {
 358                 return -ENOMEM;
 359         }
 360         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 361         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 362
 363         return 0;
 364 }
 365
 366 /**
 367  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 368  *
 369  * @adev: amdgpu_device pointer
 370  *
 371  * Tear down doorbell driver information (CIK)
 372  */
 373 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 374 {
 375         iounmap(adev->doorbell.ptr);
 376         adev->doorbell.ptr = NULL;
 377 }
 378
 379 /**
 380  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 381  *                                setup amdkfd
 382  *
 383  * @adev: amdgpu_device pointer
 384  * @aperture_base: output returning doorbell aperture base physical address
 385  * @aperture_size: output returning doorbell aperture size in bytes
 386  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 387  *
 388  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 389  * takes doorbells required for its own rings and reports the setup to amdkfd.
 390  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 391  */
 392 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 393                                 phys_addr_t *aperture_base,
 394                                 size_t *aperture_size,
 395                                 size_t *start_offset)
 396 {
 397         /*
 398          * The first num_doorbells are used by amdgpu.
 399          * amdkfd takes whatever's left in the aperture.
 400          */
 401         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 402                 *aperture_base = adev->doorbell.base;
 403                 *aperture_size = adev->doorbell.size;
 404                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 405         } else {
 406                 *aperture_base = 0;
 407                 *aperture_size = 0;
 408                 *start_offset = 0;
 409         }
 410 }
 411
 412 /*
 413  * amdgpu_wb_*()
 414  * Writeback is the the method by which the the GPU updates special pages
 415  * in memory with the status of certain GPU events (fences, ring pointers,
 416  * etc.).
 417  */
 418
 419 /**
 420  * amdgpu_wb_fini - Disable Writeback and free memory
 421  *
 422  * @adev: amdgpu_device pointer
 423  *
 424  * Disables Writeback and frees the Writeback memory (all asics).
 425  * Used at driver shutdown.
 426  */
 427 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 428 {
 429         if (adev->wb.wb_obj) {
 430                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 431                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 432                         amdgpu_bo_unpin(adev->wb.wb_obj);
 433                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 434                 }
 435                 amdgpu_bo_unref(&adev->wb.wb_obj);
 436                 adev->wb.wb = NULL;
 437                 adev->wb.wb_obj = NULL;
 438         }
 439 }
 440
 441 /**
 442  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 443  *
 444  * @adev: amdgpu_device pointer
 445  *
 446  * Disables Writeback and frees the Writeback memory (all asics).
 447  * Used at driver startup.
 448  * Returns 0 on success or an -error on failure.
 449  */
 450 static int amdgpu_wb_init(struct amdgpu_device *adev)
 451 {
 452         int r;
 453
 454         if (adev->wb.wb_obj == NULL) {
 455                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 456                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
 457                                      &adev->wb.wb_obj);
 458                 if (r) {
 459                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 460                         return r;
 461                 }
 462                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 463                 if (unlikely(r != 0)) {
 464                         amdgpu_wb_fini(adev);
 465                         return r;
 466                 }
 467                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 468                                 &adev->wb.gpu_addr);
 469                 if (r) {
 470                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 471                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 472                         amdgpu_wb_fini(adev);
 473                         return r;
 474                 }
 475                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 476                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 477                 if (r) {
 478                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 479                         amdgpu_wb_fini(adev);
 480                         return r;
 481                 }
 482
 483                 adev->wb.num_wb = AMDGPU_MAX_WB;
 484                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 485
 486                 /* clear wb memory */
 487                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 488         }
 489
 490         return 0;
 491 }
 492
 493 /**
 494  * amdgpu_wb_get - Allocate a wb entry
 495  *
 496  * @adev: amdgpu_device pointer
 497  * @wb: wb index
 498  *
 499  * Allocate a wb slot for use by the driver (all asics).
 500  * Returns 0 on success or -EINVAL on failure.
 501  */
 502 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 503 {
 504         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 505         if (offset < adev->wb.num_wb) {
 506                 __set_bit(offset, adev->wb.used);
 507                 *wb = offset;
 508                 return 0;
 509         } else {
 510                 return -EINVAL;
 511         }
 512 }
 513
 514 /**
 515  * amdgpu_wb_free - Free a wb entry
 516  *
 517  * @adev: amdgpu_device pointer
 518  * @wb: wb index
 519  *
 520  * Free a wb slot allocated for use by the driver (all asics)
 521  */
 522 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 523 {
 524         if (wb < adev->wb.num_wb)
 525                 __clear_bit(wb, adev->wb.used);
 526 }
 527
 528 /**
 529  * amdgpu_vram_location - try to find VRAM location
 530  * @adev: amdgpu device structure holding all necessary informations
 531  * @mc: memory controller structure holding memory informations
 532  * @base: base address at which to put VRAM
 533  *
 534  * Function will place try to place VRAM at base address provided
 535  * as parameter (which is so far either PCI aperture address or
 536  * for IGP TOM base address).
 537  *
 538  * If there is not enough space to fit the unvisible VRAM in the 32bits
 539  * address space then we limit the VRAM size to the aperture.
 540  *
 541  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 542  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 543  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 544  * not IGP.
 545  *
 546  * Note: we use mc_vram_size as on some board we need to program the mc to
 547  * cover the whole aperture even if VRAM size is inferior to aperture size
 548  * Novell bug 204882 + along with lots of ubuntu ones
 549  *
 550  * Note: when limiting vram it's safe to overwritte real_vram_size because
 551  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 552  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 553  * ones)
 554  *
 555  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 556  * explicitly check for that thought.
 557  *
 558  * FIXME: when reducing VRAM size align new size on power of 2.
 559  */
 560 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 561 {
 562         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 563
 564         mc->vram_start = base;
 565         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 566                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 567                 mc->real_vram_size = mc->aper_size;
 568                 mc->mc_vram_size = mc->aper_size;
 569         }
 570         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 571         if (limit && limit < mc->real_vram_size)
 572                 mc->real_vram_size = limit;
 573         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 574                         mc->mc_vram_size >> 20, mc->vram_start,
 575                         mc->vram_end, mc->real_vram_size >> 20);
 576 }
 577
 578 /**
 579  * amdgpu_gtt_location - try to find GTT location
 580  * @adev: amdgpu device structure holding all necessary informations
 581  * @mc: memory controller structure holding memory informations
 582  *
 583  * Function will place try to place GTT before or after VRAM.
 584  *
 585  * If GTT size is bigger than space left then we ajust GTT size.
 586  * Thus function will never fails.
 587  *
 588  * FIXME: when reducing GTT size align new size on power of 2.
 589  */
 590 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 591 {
 592         u64 size_af, size_bf;
 593
 594         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 595         size_bf = mc->vram_start & ~mc->gtt_base_align;
 596         if (size_bf > size_af) {
 597                 if (mc->gtt_size > size_bf) {
 598                         dev_warn(adev->dev, "limiting GTT\n");
 599                         mc->gtt_size = size_bf;
 600                 }
 601                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 602         } else {
 603                 if (mc->gtt_size > size_af) {
 604                         dev_warn(adev->dev, "limiting GTT\n");
 605                         mc->gtt_size = size_af;
 606                 }
 607                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 608         }
 609         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 610         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 611                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 612 }
 613
 614 /*
 615  * GPU helpers function.
 616  */
 617 /**
 618  * amdgpu_card_posted - check if the hw has already been initialized
 619  *
 620  * @adev: amdgpu_device pointer
 621  *
 622  * Check if the asic has been initialized (all asics).
 623  * Used at driver startup.
 624  * Returns true if initialized or false if not.
 625  */
 626 bool amdgpu_card_posted(struct amdgpu_device *adev)
 627 {
 628         uint32_t reg;
 629
 630         /* then check MEM_SIZE, in case the crtcs are off */
 631         reg = RREG32(mmCONFIG_MEMSIZE);
 632
 633         if (reg)
 634                 return true;
 635
 636         return false;
 637
 638 }
 639
 640 /**
 641  * amdgpu_dummy_page_init - init dummy page used by the driver
 642  *
 643  * @adev: amdgpu_device pointer
 644  *
 645  * Allocate the dummy page used by the driver (all asics).
 646  * This dummy page is used by the driver as a filler for gart entries
 647  * when pages are taken out of the GART
 648  * Returns 0 on sucess, -ENOMEM on failure.
 649  */
 650 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 651 {
 652         if (adev->dummy_page.page)
 653                 return 0;
 654         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 655         if (adev->dummy_page.page == NULL)
 656                 return -ENOMEM;
 657         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 658                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 659         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 660                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 661                 __free_page(adev->dummy_page.page);
 662                 adev->dummy_page.page = NULL;
 663                 return -ENOMEM;
 664         }
 665         return 0;
 666 }
 667
 668 /**
 669  * amdgpu_dummy_page_fini - free dummy page used by the driver
 670  *
 671  * @adev: amdgpu_device pointer
 672  *
 673  * Frees the dummy page used by the driver (all asics).
 674  */
 675 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 676 {
 677         if (adev->dummy_page.page == NULL)
 678                 return;
 679         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 680                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 681         __free_page(adev->dummy_page.page);
 682         adev->dummy_page.page = NULL;
 683 }
 684
 685
 686 /* ATOM accessor methods */
 687 /*
 688  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 689  * driver registers callbacks to access registers and the interpreter
 690  * in the driver parses the tables and executes then to program specific
 691  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 692  * atombios.h, and atom.c
 693  */
 694
 695 /**
 696  * cail_pll_read - read PLL register
 697  *
 698  * @info: atom card_info pointer
 699  * @reg: PLL register offset
 700  *
 701  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 702  * Returns the value of the PLL register.
 703  */
 704 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 705 {
 706         return 0;
 707 }
 708
 709 /**
 710  * cail_pll_write - write PLL register
 711  *
 712  * @info: atom card_info pointer
 713  * @reg: PLL register offset
 714  * @val: value to write to the pll register
 715  *
 716  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 717  */
 718 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 719 {
 720
 721 }
 722
 723 /**
 724  * cail_mc_read - read MC (Memory Controller) register
 725  *
 726  * @info: atom card_info pointer
 727  * @reg: MC register offset
 728  *
 729  * Provides an MC register accessor for the atom interpreter (r4xx+).
 730  * Returns the value of the MC register.
 731  */
 732 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 733 {
 734         return 0;
 735 }
 736
 737 /**
 738  * cail_mc_write - write MC (Memory Controller) register
 739  *
 740  * @info: atom card_info pointer
 741  * @reg: MC register offset
 742  * @val: value to write to the pll register
 743  *
 744  * Provides a MC register accessor for the atom interpreter (r4xx+).
 745  */
 746 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 747 {
 748
 749 }
 750
 751 /**
 752  * cail_reg_write - write MMIO register
 753  *
 754  * @info: atom card_info pointer
 755  * @reg: MMIO register offset
 756  * @val: value to write to the pll register
 757  *
 758  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 759  */
 760 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 761 {
 762         struct amdgpu_device *adev = info->dev->dev_private;
 763
 764         WREG32(reg, val);
 765 }
 766
 767 /**
 768  * cail_reg_read - read MMIO register
 769  *
 770  * @info: atom card_info pointer
 771  * @reg: MMIO register offset
 772  *
 773  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 774  * Returns the value of the MMIO register.
 775  */
 776 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 777 {
 778         struct amdgpu_device *adev = info->dev->dev_private;
 779         uint32_t r;
 780
 781         r = RREG32(reg);
 782         return r;
 783 }
 784
 785 /**
 786  * cail_ioreg_write - write IO register
 787  *
 788  * @info: atom card_info pointer
 789  * @reg: IO register offset
 790  * @val: value to write to the pll register
 791  *
 792  * Provides a IO register accessor for the atom interpreter (r4xx+).
 793  */
 794 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 795 {
 796         struct amdgpu_device *adev = info->dev->dev_private;
 797
 798         WREG32_IO(reg, val);
 799 }
 800
 801 /**
 802  * cail_ioreg_read - read IO register
 803  *
 804  * @info: atom card_info pointer
 805  * @reg: IO register offset
 806  *
 807  * Provides an IO register accessor for the atom interpreter (r4xx+).
 808  * Returns the value of the IO register.
 809  */
 810 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 811 {
 812         struct amdgpu_device *adev = info->dev->dev_private;
 813         uint32_t r;
 814
 815         r = RREG32_IO(reg);
 816         return r;
 817 }
 818
 819 /**
 820  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * Frees the driver info and register access callbacks for the ATOM
 825  * interpreter (r4xx+).
 826  * Called at driver shutdown.
 827  */
 828 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 829 {
 830         if (adev->mode_info.atom_context)
 831                 kfree(adev->mode_info.atom_context->scratch);
 832         kfree(adev->mode_info.atom_context);
 833         adev->mode_info.atom_context = NULL;
 834         kfree(adev->mode_info.atom_card_info);
 835         adev->mode_info.atom_card_info = NULL;
 836 }
 837
 838 /**
 839  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 840  *
 841  * @adev: amdgpu_device pointer
 842  *
 843  * Initializes the driver info and register access callbacks for the
 844  * ATOM interpreter (r4xx+).
 845  * Returns 0 on sucess, -ENOMEM on failure.
 846  * Called at driver startup.
 847  */
 848 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 849 {
 850         struct card_info *atom_card_info =
 851             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 852
 853         if (!atom_card_info)
 854                 return -ENOMEM;
 855
 856         adev->mode_info.atom_card_info = atom_card_info;
 857         atom_card_info->dev = adev->ddev;
 858         atom_card_info->reg_read = cail_reg_read;
 859         atom_card_info->reg_write = cail_reg_write;
 860         /* needed for iio ops */
 861         if (adev->rio_mem) {
 862                 atom_card_info->ioreg_read = cail_ioreg_read;
 863                 atom_card_info->ioreg_write = cail_ioreg_write;
 864         } else {
 865                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 866                 atom_card_info->ioreg_read = cail_reg_read;
 867                 atom_card_info->ioreg_write = cail_reg_write;
 868         }
 869         atom_card_info->mc_read = cail_mc_read;
 870         atom_card_info->mc_write = cail_mc_write;
 871         atom_card_info->pll_read = cail_pll_read;
 872         atom_card_info->pll_write = cail_pll_write;
 873
 874         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 875         if (!adev->mode_info.atom_context) {
 876                 amdgpu_atombios_fini(adev);
 877                 return -ENOMEM;
 878         }
 879
 880         mutex_init(&adev->mode_info.atom_context->mutex);
 881         amdgpu_atombios_scratch_regs_init(adev);
 882         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 883         return 0;
 884 }
 885
 886 /* if we get transitioned to only one device, take VGA back */
 887 /**
 888  * amdgpu_vga_set_decode - enable/disable vga decode
 889  *
 890  * @cookie: amdgpu_device pointer
 891  * @state: enable/disable vga decode
 892  *
 893  * Enable/disable vga decode (all asics).
 894  * Returns VGA resource flags.
 895  */
 896 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 897 {
 898         struct amdgpu_device *adev = cookie;
 899         amdgpu_asic_set_vga_state(adev, state);
 900         if (state)
 901                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 902                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 903         else
 904                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 905 }
 906
 907 /**
 908  * amdgpu_check_pot_argument - check that argument is a power of two
 909  *
 910  * @arg: value to check
 911  *
 912  * Validates that a certain argument is a power of two (all asics).
 913  * Returns true if argument is valid.
 914  */
 915 static bool amdgpu_check_pot_argument(int arg)
 916 {
 917         return (arg & (arg - 1)) == 0;
 918 }
 919
 920 /**
 921  * amdgpu_check_arguments - validate module params
 922  *
 923  * @adev: amdgpu_device pointer
 924  *
 925  * Validates certain module parameters and updates
 926  * the associated values used by the driver (all asics).
 927  */
 928 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 929 {
 930         if (amdgpu_sched_jobs < 4) {
 931                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 932                          amdgpu_sched_jobs);
 933                 amdgpu_sched_jobs = 4;
 934         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 935                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 936                          amdgpu_sched_jobs);
 937                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 938         }
 939
 940         if (amdgpu_gart_size != -1) {
 941                 /* gtt size must be greater or equal to 32M */
 942                 if (amdgpu_gart_size < 32) {
 943                         dev_warn(adev->dev, "gart size (%d) too small\n",
 944                                  amdgpu_gart_size);
 945                         amdgpu_gart_size = -1;
 946                 }
 947         }
 948
 949         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 950                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 951                          amdgpu_vm_size);
 952                 amdgpu_vm_size = 8;
 953         }
 954
 955         if (amdgpu_vm_size < 1) {
 956                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 957                          amdgpu_vm_size);
 958                 amdgpu_vm_size = 8;
 959         }
 960
 961         /*
 962          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 963          */
 964         if (amdgpu_vm_size > 1024) {
 965                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 966                          amdgpu_vm_size);
 967                 amdgpu_vm_size = 8;
 968         }
 969
 970         /* defines number of bits in page table versus page directory,
 971          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 972          * page table and the remaining bits are in the page directory */
 973         if (amdgpu_vm_block_size == -1) {
 974
 975                 /* Total bits covered by PD + PTs */
 976                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 977
 978                 /* Make sure the PD is 4K in size up to 8GB address space.
 979                    Above that split equal between PD and PTs */
 980                 if (amdgpu_vm_size <= 8)
 981                         amdgpu_vm_block_size = bits - 9;
 982                 else
 983                         amdgpu_vm_block_size = (bits + 3) / 2;
 984
 985         } else if (amdgpu_vm_block_size < 9) {
 986                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 987                          amdgpu_vm_block_size);
 988                 amdgpu_vm_block_size = 9;
 989         }
 990
 991         if (amdgpu_vm_block_size > 24 ||
 992             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
 993                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
 994                          amdgpu_vm_block_size);
 995                 amdgpu_vm_block_size = 9;
 996         }
 997 }
 998
 999 /**
1000  * amdgpu_switcheroo_set_state - set switcheroo state
1001  *
1002  * @pdev: pci dev pointer
1003  * @state: vga_switcheroo state
1004  *
1005  * Callback for the switcheroo driver.  Suspends or resumes the
1006  * the asics before or after it is powered up using ACPI methods.
1007  */
1008 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1009 {
1010         struct drm_device *dev = pci_get_drvdata(pdev);
1011
1012         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1013                 return;
1014
1015         if (state == VGA_SWITCHEROO_ON) {
1016                 unsigned d3_delay = dev->pdev->d3_delay;
1017
1018                 printk(KERN_INFO "amdgpu: switched on\n");
1019                 /* don't suspend or resume card normally */
1020                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1021
1022                 amdgpu_resume_kms(dev, true, true);
1023
1024                 dev->pdev->d3_delay = d3_delay;
1025
1026                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1027                 drm_kms_helper_poll_enable(dev);
1028         } else {
1029                 printk(KERN_INFO "amdgpu: switched off\n");
1030                 drm_kms_helper_poll_disable(dev);
1031                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1032                 amdgpu_suspend_kms(dev, true, true);
1033                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1034         }
1035 }
1036
1037 /**
1038  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1039  *
1040  * @pdev: pci dev pointer
1041  *
1042  * Callback for the switcheroo driver.  Check of the switcheroo
1043  * state can be changed.
1044  * Returns true if the state can be changed, false if not.
1045  */
1046 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1047 {
1048         struct drm_device *dev = pci_get_drvdata(pdev);
1049
1050         /*
1051         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1052         * locking inversion with the driver load path. And the access here is
1053         * completely racy anyway. So don't bother with locking for now.
1054         */
1055         return dev->open_count == 0;
1056 }
1057
1058 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1059         .set_gpu_state = amdgpu_switcheroo_set_state,
1060         .reprobe = NULL,
1061         .can_switch = amdgpu_switcheroo_can_switch,
1062 };
1063
1064 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1065                                   enum amd_ip_block_type block_type,
1066                                   enum amd_clockgating_state state)
1067 {
1068         int i, r = 0;
1069
1070         for (i = 0; i < adev->num_ip_blocks; i++) {
1071                 if (adev->ip_blocks[i].type == block_type) {
1072                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1073                                                                             state);
1074                         if (r)
1075                                 return r;
1076                 }
1077         }
1078         return r;
1079 }
1080
1081 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1082                                   enum amd_ip_block_type block_type,
1083                                   enum amd_powergating_state state)
1084 {
1085         int i, r = 0;
1086
1087         for (i = 0; i < adev->num_ip_blocks; i++) {
1088                 if (adev->ip_blocks[i].type == block_type) {
1089                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1090                                                                             state);
1091                         if (r)
1092                                 return r;
1093                 }
1094         }
1095         return r;
1096 }
1097
1098 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1099                                         struct amdgpu_device *adev,
1100                                         enum amd_ip_block_type type)
1101 {
1102         int i;
1103
1104         for (i = 0; i < adev->num_ip_blocks; i++)
1105                 if (adev->ip_blocks[i].type == type)
1106                         return &adev->ip_blocks[i];
1107
1108         return NULL;
1109 }
1110
1111 /**
1112  * amdgpu_ip_block_version_cmp
1113  *
1114  * @adev: amdgpu_device pointer
1115  * @type: enum amd_ip_block_type
1116  * @major: major version
1117  * @minor: minor version
1118  *
1119  * return 0 if equal or greater
1120  * return 1 if smaller or the ip_block doesn't exist
1121  */
1122 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1123                                 enum amd_ip_block_type type,
1124                                 u32 major, u32 minor)
1125 {
1126         const struct amdgpu_ip_block_version *ip_block;
1127         ip_block = amdgpu_get_ip_block(adev, type);
1128
1129         if (ip_block && ((ip_block->major > major) ||
1130                         ((ip_block->major == major) &&
1131                         (ip_block->minor >= minor))))
1132                 return 0;
1133
1134         return 1;
1135 }
1136
1137 static int amdgpu_early_init(struct amdgpu_device *adev)
1138 {
1139         int i, r;
1140
1141         switch (adev->asic_type) {
1142         case CHIP_TOPAZ:
1143         case CHIP_TONGA:
1144         case CHIP_FIJI:
1145         case CHIP_POLARIS11:
1146         case CHIP_POLARIS10:
1147         case CHIP_CARRIZO:
1148         case CHIP_STONEY:
1149                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1150                         adev->family = AMDGPU_FAMILY_CZ;
1151                 else
1152                         adev->family = AMDGPU_FAMILY_VI;
1153
1154                 r = vi_set_ip_blocks(adev);
1155                 if (r)
1156                         return r;
1157                 break;
1158 #ifdef CONFIG_DRM_AMDGPU_CIK
1159         case CHIP_BONAIRE:
1160         case CHIP_HAWAII:
1161         case CHIP_KAVERI:
1162         case CHIP_KABINI:
1163         case CHIP_MULLINS:
1164                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1165                         adev->family = AMDGPU_FAMILY_CI;
1166                 else
1167                         adev->family = AMDGPU_FAMILY_KV;
1168
1169                 r = cik_set_ip_blocks(adev);
1170                 if (r)
1171                         return r;
1172                 break;
1173 #endif
1174         default:
1175                 /* FIXME: not supported yet */
1176                 return -EINVAL;
1177         }
1178
1179         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1180                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1181         if (adev->ip_block_status == NULL)
1182                 return -ENOMEM;
1183
1184         if (adev->ip_blocks == NULL) {
1185                 DRM_ERROR("No IP blocks found!\n");
1186                 return r;
1187         }
1188
1189         for (i = 0; i < adev->num_ip_blocks; i++) {
1190                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1191                         DRM_ERROR("disabled ip block: %d\n", i);
1192                         adev->ip_block_status[i].valid = false;
1193                 } else {
1194                         if (adev->ip_blocks[i].funcs->early_init) {
1195                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1196                                 if (r == -ENOENT) {
1197                                         adev->ip_block_status[i].valid = false;
1198                                 } else if (r) {
1199                                         DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1200                                         return r;
1201                                 } else {
1202                                         adev->ip_block_status[i].valid = true;
1203                                 }
1204                         } else {
1205                                 adev->ip_block_status[i].valid = true;
1206                         }
1207                 }
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int amdgpu_init(struct amdgpu_device *adev)
1214 {
1215         int i, r;
1216
1217         for (i = 0; i < adev->num_ip_blocks; i++) {
1218                 if (!adev->ip_block_status[i].valid)
1219                         continue;
1220                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1221                 if (r) {
1222                         DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1223                         return r;
1224                 }
1225                 adev->ip_block_status[i].sw = true;
1226                 /* need to do gmc hw init early so we can allocate gpu mem */
1227                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1228                         r = amdgpu_vram_scratch_init(adev);
1229                         if (r) {
1230                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1231                                 return r;
1232                         }
1233                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1234                         if (r) {
1235                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1236                                 return r;
1237                         }
1238                         r = amdgpu_wb_init(adev);
1239                         if (r) {
1240                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1241                                 return r;
1242                         }
1243                         adev->ip_block_status[i].hw = true;
1244                 }
1245         }
1246
1247         for (i = 0; i < adev->num_ip_blocks; i++) {
1248                 if (!adev->ip_block_status[i].sw)
1249                         continue;
1250                 /* gmc hw init is done early */
1251                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1252                         continue;
1253                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1254                 if (r) {
1255                         DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1256                         return r;
1257                 }
1258                 adev->ip_block_status[i].hw = true;
1259         }
1260
1261         return 0;
1262 }
1263
1264 static int amdgpu_late_init(struct amdgpu_device *adev)
1265 {
1266         int i = 0, r;
1267
1268         for (i = 0; i < adev->num_ip_blocks; i++) {
1269                 if (!adev->ip_block_status[i].valid)
1270                         continue;
1271                 /* enable clockgating to save power */
1272                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1273                                                                     AMD_CG_STATE_GATE);
1274                 if (r) {
1275                         DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1276                         return r;
1277                 }
1278                 if (adev->ip_blocks[i].funcs->late_init) {
1279                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1280                         if (r) {
1281                                 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1282                                 return r;
1283                         }
1284                 }
1285         }
1286
1287         return 0;
1288 }
1289
1290 static int amdgpu_fini(struct amdgpu_device *adev)
1291 {
1292         int i, r;
1293
1294         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1295                 if (!adev->ip_block_status[i].hw)
1296                         continue;
1297                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1298                         amdgpu_wb_fini(adev);
1299                         amdgpu_vram_scratch_fini(adev);
1300                 }
1301                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1302                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1303                                                                     AMD_CG_STATE_UNGATE);
1304                 if (r) {
1305                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1306                         return r;
1307                 }
1308                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1309                 /* XXX handle errors */
1310                 if (r) {
1311                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1312                 }
1313                 adev->ip_block_status[i].hw = false;
1314         }
1315
1316         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1317                 if (!adev->ip_block_status[i].sw)
1318                         continue;
1319                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1320                 /* XXX handle errors */
1321                 if (r) {
1322                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1323                 }
1324                 adev->ip_block_status[i].sw = false;
1325                 adev->ip_block_status[i].valid = false;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int amdgpu_suspend(struct amdgpu_device *adev)
1332 {
1333         int i, r;
1334
1335         /* ungate SMC block first */
1336         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1337                                          AMD_CG_STATE_UNGATE);
1338         if (r) {
1339                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1340         }
1341
1342         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1343                 if (!adev->ip_block_status[i].valid)
1344                         continue;
1345                 /* ungate blocks so that suspend can properly shut them down */
1346                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1347                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1348                                                                             AMD_CG_STATE_UNGATE);
1349                         if (r) {
1350                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1351                         }
1352                 }
1353                 /* XXX handle errors */
1354                 r = adev->ip_blocks[i].funcs->suspend(adev);
1355                 /* XXX handle errors */
1356                 if (r) {
1357                         DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1358                 }
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int amdgpu_resume(struct amdgpu_device *adev)
1365 {
1366         int i, r;
1367
1368         for (i = 0; i < adev->num_ip_blocks; i++) {
1369                 if (!adev->ip_block_status[i].valid)
1370                         continue;
1371                 r = adev->ip_blocks[i].funcs->resume(adev);
1372                 if (r) {
1373                         DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1374                         return r;
1375                 }
1376         }
1377
1378         return 0;
1379 }
1380
1381 /**
1382  * amdgpu_device_init - initialize the driver
1383  *
1384  * @adev: amdgpu_device pointer
1385  * @pdev: drm dev pointer
1386  * @pdev: pci dev pointer
1387  * @flags: driver flags
1388  *
1389  * Initializes the driver info and hw (all asics).
1390  * Returns 0 for success or an error on failure.
1391  * Called at driver startup.
1392  */
1393 int amdgpu_device_init(struct amdgpu_device *adev,
1394                        struct drm_device *ddev,
1395                        struct pci_dev *pdev,
1396                        uint32_t flags)
1397 {
1398         int r, i;
1399         bool runtime = false;
1400
1401         adev->shutdown = false;
1402         adev->dev = &pdev->dev;
1403         adev->ddev = ddev;
1404         adev->pdev = pdev;
1405         adev->flags = flags;
1406         adev->asic_type = flags & AMD_ASIC_MASK;
1407         adev->is_atom_bios = false;
1408         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1409         adev->mc.gtt_size = 512 * 1024 * 1024;
1410         adev->accel_working = false;
1411         adev->num_rings = 0;
1412         adev->mman.buffer_funcs = NULL;
1413         adev->mman.buffer_funcs_ring = NULL;
1414         adev->vm_manager.vm_pte_funcs = NULL;
1415         adev->vm_manager.vm_pte_num_rings = 0;
1416         adev->gart.gart_funcs = NULL;
1417         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1418
1419         adev->smc_rreg = &amdgpu_invalid_rreg;
1420         adev->smc_wreg = &amdgpu_invalid_wreg;
1421         adev->pcie_rreg = &amdgpu_invalid_rreg;
1422         adev->pcie_wreg = &amdgpu_invalid_wreg;
1423         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1424         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1425         adev->didt_rreg = &amdgpu_invalid_rreg;
1426         adev->didt_wreg = &amdgpu_invalid_wreg;
1427         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1428         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1429
1430         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1431                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1432                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1433
1434         /* mutex initialization are all done here so we
1435          * can recall function without having locking issues */
1436         mutex_init(&adev->vm_manager.lock);
1437         atomic_set(&adev->irq.ih.lock, 0);
1438         mutex_init(&adev->pm.mutex);
1439         mutex_init(&adev->gfx.gpu_clock_mutex);
1440         mutex_init(&adev->srbm_mutex);
1441         mutex_init(&adev->grbm_idx_mutex);
1442         mutex_init(&adev->mn_lock);
1443         hash_init(adev->mn_hash);
1444
1445         amdgpu_check_arguments(adev);
1446
1447         /* Registers mapping */
1448         /* TODO: block userspace mapping of io register */
1449         spin_lock_init(&adev->mmio_idx_lock);
1450         spin_lock_init(&adev->smc_idx_lock);
1451         spin_lock_init(&adev->pcie_idx_lock);
1452         spin_lock_init(&adev->uvd_ctx_idx_lock);
1453         spin_lock_init(&adev->didt_idx_lock);
1454         spin_lock_init(&adev->audio_endpt_idx_lock);
1455
1456         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1457         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1458         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1459         if (adev->rmmio == NULL) {
1460                 return -ENOMEM;
1461         }
1462         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1463         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1464
1465         /* doorbell bar mapping */
1466         amdgpu_doorbell_init(adev);
1467
1468         /* io port mapping */
1469         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1470                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1471                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1472                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1473                         break;
1474                 }
1475         }
1476         if (adev->rio_mem == NULL)
1477                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1478
1479         /* early init functions */
1480         r = amdgpu_early_init(adev);
1481         if (r)
1482                 return r;
1483
1484         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1485         /* this will fail for cards that aren't VGA class devices, just
1486          * ignore it */
1487         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1488
1489         if (amdgpu_runtime_pm == 1)
1490                 runtime = true;
1491         if (amdgpu_device_is_px(ddev))
1492                 runtime = true;
1493         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1494         if (runtime)
1495                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1496
1497         /* Read BIOS */
1498         if (!amdgpu_get_bios(adev))
1499                 return -EINVAL;
1500         /* Must be an ATOMBIOS */
1501         if (!adev->is_atom_bios) {
1502                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1503                 return -EINVAL;
1504         }
1505         r = amdgpu_atombios_init(adev);
1506         if (r) {
1507                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1508                 return r;
1509         }
1510
1511         /* See if the asic supports SR-IOV */
1512         adev->virtualization.supports_sr_iov =
1513                 amdgpu_atombios_has_gpu_virtualization_table(adev);
1514
1515         /* Post card if necessary */
1516         if (!amdgpu_card_posted(adev) ||
1517             adev->virtualization.supports_sr_iov) {
1518                 if (!adev->bios) {
1519                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1520                         return -EINVAL;
1521                 }
1522                 DRM_INFO("GPU not posted. posting now...\n");
1523                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1524         }
1525
1526         /* Initialize clocks */
1527         r = amdgpu_atombios_get_clock_info(adev);
1528         if (r) {
1529                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1530                 return r;
1531         }
1532         /* init i2c buses */
1533         amdgpu_atombios_i2c_init(adev);
1534
1535         /* Fence driver */
1536         r = amdgpu_fence_driver_init(adev);
1537         if (r) {
1538                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1539                 return r;
1540         }
1541
1542         /* init the mode config */
1543         drm_mode_config_init(adev->ddev);
1544
1545         r = amdgpu_init(adev);
1546         if (r) {
1547                 dev_err(adev->dev, "amdgpu_init failed\n");
1548                 amdgpu_fini(adev);
1549                 return r;
1550         }
1551
1552         adev->accel_working = true;
1553
1554         amdgpu_fbdev_init(adev);
1555
1556         r = amdgpu_ib_pool_init(adev);
1557         if (r) {
1558                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1559                 return r;
1560         }
1561
1562         r = amdgpu_ib_ring_tests(adev);
1563         if (r)
1564                 DRM_ERROR("ib ring test failed (%d).\n", r);
1565
1566         r = amdgpu_gem_debugfs_init(adev);
1567         if (r) {
1568                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1569         }
1570
1571         r = amdgpu_debugfs_regs_init(adev);
1572         if (r) {
1573                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1574         }
1575
1576         if ((amdgpu_testing & 1)) {
1577                 if (adev->accel_working)
1578                         amdgpu_test_moves(adev);
1579                 else
1580                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1581         }
1582         if ((amdgpu_testing & 2)) {
1583                 if (adev->accel_working)
1584                         amdgpu_test_syncing(adev);
1585                 else
1586                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1587         }
1588         if (amdgpu_benchmarking) {
1589                 if (adev->accel_working)
1590                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1591                 else
1592                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1593         }
1594
1595         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1596          * explicit gating rather than handling it automatically.
1597          */
1598         r = amdgpu_late_init(adev);
1599         if (r) {
1600                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1601                 return r;
1602         }
1603
1604         return 0;
1605 }
1606
1607 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1608
1609 /**
1610  * amdgpu_device_fini - tear down the driver
1611  *
1612  * @adev: amdgpu_device pointer
1613  *
1614  * Tear down the driver info (all asics).
1615  * Called at driver shutdown.
1616  */
1617 void amdgpu_device_fini(struct amdgpu_device *adev)
1618 {
1619         int r;
1620
1621         DRM_INFO("amdgpu: finishing device.\n");
1622         adev->shutdown = true;
1623         /* evict vram memory */
1624         amdgpu_bo_evict_vram(adev);
1625         amdgpu_ib_pool_fini(adev);
1626         amdgpu_fence_driver_fini(adev);
1627         drm_crtc_force_disable_all(adev->ddev);
1628         amdgpu_fbdev_fini(adev);
1629         r = amdgpu_fini(adev);
1630         kfree(adev->ip_block_status);
1631         adev->ip_block_status = NULL;
1632         adev->accel_working = false;
1633         /* free i2c buses */
1634         amdgpu_i2c_fini(adev);
1635         amdgpu_atombios_fini(adev);
1636         kfree(adev->bios);
1637         adev->bios = NULL;
1638         vga_switcheroo_unregister_client(adev->pdev);
1639         vga_client_register(adev->pdev, NULL, NULL, NULL);
1640         if (adev->rio_mem)
1641                 pci_iounmap(adev->pdev, adev->rio_mem);
1642         adev->rio_mem = NULL;
1643         iounmap(adev->rmmio);
1644         adev->rmmio = NULL;
1645         amdgpu_doorbell_fini(adev);
1646         amdgpu_debugfs_regs_cleanup(adev);
1647         amdgpu_debugfs_remove_files(adev);
1648 }
1649
1650
1651 /*
1652  * Suspend & resume.
1653  */
1654 /**
1655  * amdgpu_suspend_kms - initiate device suspend
1656  *
1657  * @pdev: drm dev pointer
1658  * @state: suspend state
1659  *
1660  * Puts the hw in the suspend state (all asics).
1661  * Returns 0 for success or an error on failure.
1662  * Called at driver suspend.
1663  */
1664 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1665 {
1666         struct amdgpu_device *adev;
1667         struct drm_crtc *crtc;
1668         struct drm_connector *connector;
1669         int r;
1670
1671         if (dev == NULL || dev->dev_private == NULL) {
1672                 return -ENODEV;
1673         }
1674
1675         adev = dev->dev_private;
1676
1677         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1678                 return 0;
1679
1680         drm_kms_helper_poll_disable(dev);
1681
1682         /* turn off display hw */
1683         drm_modeset_lock_all(dev);
1684         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1685                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1686         }
1687         drm_modeset_unlock_all(dev);
1688
1689         /* unpin the front buffers and cursors */
1690         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1691                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1692                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1693                 struct amdgpu_bo *robj;
1694
1695                 if (amdgpu_crtc->cursor_bo) {
1696                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1697                         r = amdgpu_bo_reserve(aobj, false);
1698                         if (r == 0) {
1699                                 amdgpu_bo_unpin(aobj);
1700                                 amdgpu_bo_unreserve(aobj);
1701                         }
1702                 }
1703
1704                 if (rfb == NULL || rfb->obj == NULL) {
1705                         continue;
1706                 }
1707                 robj = gem_to_amdgpu_bo(rfb->obj);
1708                 /* don't unpin kernel fb objects */
1709                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1710                         r = amdgpu_bo_reserve(robj, false);
1711                         if (r == 0) {
1712                                 amdgpu_bo_unpin(robj);
1713                                 amdgpu_bo_unreserve(robj);
1714                         }
1715                 }
1716         }
1717         /* evict vram memory */
1718         amdgpu_bo_evict_vram(adev);
1719
1720         amdgpu_fence_driver_suspend(adev);
1721
1722         r = amdgpu_suspend(adev);
1723
1724         /* evict remaining vram memory */
1725         amdgpu_bo_evict_vram(adev);
1726
1727         pci_save_state(dev->pdev);
1728         if (suspend) {
1729                 /* Shut down the device */
1730                 pci_disable_device(dev->pdev);
1731                 pci_set_power_state(dev->pdev, PCI_D3hot);
1732         }
1733
1734         if (fbcon) {
1735                 console_lock();
1736                 amdgpu_fbdev_set_suspend(adev, 1);
1737                 console_unlock();
1738         }
1739         return 0;
1740 }
1741
1742 /**
1743  * amdgpu_resume_kms - initiate device resume
1744  *
1745  * @pdev: drm dev pointer
1746  *
1747  * Bring the hw back to operating state (all asics).
1748  * Returns 0 for success or an error on failure.
1749  * Called at driver resume.
1750  */
1751 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1752 {
1753         struct drm_connector *connector;
1754         struct amdgpu_device *adev = dev->dev_private;
1755         struct drm_crtc *crtc;
1756         int r;
1757
1758         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1759                 return 0;
1760
1761         if (fbcon) {
1762                 console_lock();
1763         }
1764         if (resume) {
1765                 pci_set_power_state(dev->pdev, PCI_D0);
1766                 pci_restore_state(dev->pdev);
1767                 if (pci_enable_device(dev->pdev)) {
1768                         if (fbcon)
1769                                 console_unlock();
1770                         return -1;
1771                 }
1772         }
1773
1774         /* post card */
1775         if (!amdgpu_card_posted(adev))
1776                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1777
1778         r = amdgpu_resume(adev);
1779         if (r)
1780                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1781
1782         amdgpu_fence_driver_resume(adev);
1783
1784         if (resume) {
1785                 r = amdgpu_ib_ring_tests(adev);
1786                 if (r)
1787                         DRM_ERROR("ib ring test failed (%d).\n", r);
1788         }
1789
1790         r = amdgpu_late_init(adev);
1791         if (r)
1792                 return r;
1793
1794         /* pin cursors */
1795         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1796                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1797
1798                 if (amdgpu_crtc->cursor_bo) {
1799                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1800                         r = amdgpu_bo_reserve(aobj, false);
1801                         if (r == 0) {
1802                                 r = amdgpu_bo_pin(aobj,
1803                                                   AMDGPU_GEM_DOMAIN_VRAM,
1804                                                   &amdgpu_crtc->cursor_addr);
1805                                 if (r != 0)
1806                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1807                                 amdgpu_bo_unreserve(aobj);
1808                         }
1809                 }
1810         }
1811
1812         /* blat the mode back in */
1813         if (fbcon) {
1814                 drm_helper_resume_force_mode(dev);
1815                 /* turn on display hw */
1816                 drm_modeset_lock_all(dev);
1817                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1818                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1819                 }
1820                 drm_modeset_unlock_all(dev);
1821         }
1822
1823         drm_kms_helper_poll_enable(dev);
1824         drm_helper_hpd_irq_event(dev);
1825
1826         if (fbcon) {
1827                 amdgpu_fbdev_set_suspend(adev, 0);
1828                 console_unlock();
1829         }
1830
1831         return 0;
1832 }
1833
1834 /**
1835  * amdgpu_gpu_reset - reset the asic
1836  *
1837  * @adev: amdgpu device pointer
1838  *
1839  * Attempt the reset the GPU if it has hung (all asics).
1840  * Returns 0 for success or an error on failure.
1841  */
1842 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1843 {
1844         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1845         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1846
1847         bool saved = false;
1848
1849         int i, r;
1850         int resched;
1851
1852         atomic_inc(&adev->gpu_reset_counter);
1853
1854         /* block TTM */
1855         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1856
1857         r = amdgpu_suspend(adev);
1858
1859         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1860                 struct amdgpu_ring *ring = adev->rings[i];
1861                 if (!ring)
1862                         continue;
1863
1864                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1865                 if (ring_sizes[i]) {
1866                         saved = true;
1867                         dev_info(adev->dev, "Saved %d dwords of commands "
1868                                  "on ring %d.\n", ring_sizes[i], i);
1869                 }
1870         }
1871
1872 retry:
1873         r = amdgpu_asic_reset(adev);
1874         /* post card */
1875         amdgpu_atom_asic_init(adev->mode_info.atom_context);
1876
1877         if (!r) {
1878                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1879                 r = amdgpu_resume(adev);
1880         }
1881
1882         if (!r) {
1883                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1884                         struct amdgpu_ring *ring = adev->rings[i];
1885                         if (!ring)
1886                                 continue;
1887
1888                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1889                         ring_sizes[i] = 0;
1890                         ring_data[i] = NULL;
1891                 }
1892
1893                 r = amdgpu_ib_ring_tests(adev);
1894                 if (r) {
1895                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1896                         if (saved) {
1897                                 saved = false;
1898                                 r = amdgpu_suspend(adev);
1899                                 goto retry;
1900                         }
1901                 }
1902         } else {
1903                 amdgpu_fence_driver_force_completion(adev);
1904                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1905                         if (adev->rings[i])
1906                                 kfree(ring_data[i]);
1907                 }
1908         }
1909
1910         drm_helper_resume_force_mode(adev->ddev);
1911
1912         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1913         if (r) {
1914                 /* bad news, how to tell it to userspace ? */
1915                 dev_info(adev->dev, "GPU reset failed\n");
1916         }
1917
1918         return r;
1919 }
1920
1921 #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */
1922 #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1923
1924 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1925 {
1926         u32 mask;
1927         int ret;
1928
1929         if (amdgpu_pcie_gen_cap)
1930                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1931
1932         if (amdgpu_pcie_lane_cap)
1933                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1934
1935         /* covers APUs as well */
1936         if (pci_is_root_bus(adev->pdev->bus)) {
1937                 if (adev->pm.pcie_gen_mask == 0)
1938                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1939                 if (adev->pm.pcie_mlw_mask == 0)
1940                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1941                 return;
1942         }
1943
1944         if (adev->pm.pcie_gen_mask == 0) {
1945                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1946                 if (!ret) {
1947                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1948                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1949                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1950
1951                         if (mask & DRM_PCIE_SPEED_25)
1952                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1953                         if (mask & DRM_PCIE_SPEED_50)
1954                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1955                         if (mask & DRM_PCIE_SPEED_80)
1956                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1957                 } else {
1958                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1959                 }
1960         }
1961         if (adev->pm.pcie_mlw_mask == 0) {
1962                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1963                 if (!ret) {
1964                         switch (mask) {
1965                         case 32:
1966                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1967                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1968                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1969                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1970                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1971                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1972                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1973                                 break;
1974                         case 16:
1975                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1976                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1977                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1978                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1979                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1980                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1981                                 break;
1982                         case 12:
1983                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1984                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1985                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1986                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1987                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1988                                 break;
1989                         case 8:
1990                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1991                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1992                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1993                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1994                                 break;
1995                         case 4:
1996                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1997                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1998                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1999                                 break;
2000                         case 2:
2001                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2002                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2003                                 break;
2004                         case 1:
2005                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2006                                 break;
2007                         default:
2008                                 break;
2009                         }
2010                 } else {
2011                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2012                 }
2013         }
2014 }
2015
2016 /*
2017  * Debugfs
2018  */
2019 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2020                              const struct drm_info_list *files,
2021                              unsigned nfiles)
2022 {
2023         unsigned i;
2024
2025         for (i = 0; i < adev->debugfs_count; i++) {
2026                 if (adev->debugfs[i].files == files) {
2027                         /* Already registered */
2028                         return 0;
2029                 }
2030         }
2031
2032         i = adev->debugfs_count + 1;
2033         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2034                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2035                 DRM_ERROR("Report so we increase "
2036                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2037                 return -EINVAL;
2038         }
2039         adev->debugfs[adev->debugfs_count].files = files;
2040         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2041         adev->debugfs_count = i;
2042 #if defined(CONFIG_DEBUG_FS)
2043         drm_debugfs_create_files(files, nfiles,
2044                                  adev->ddev->control->debugfs_root,
2045                                  adev->ddev->control);
2046         drm_debugfs_create_files(files, nfiles,
2047                                  adev->ddev->primary->debugfs_root,
2048                                  adev->ddev->primary);
2049 #endif
2050         return 0;
2051 }
2052
2053 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2054 {
2055 #if defined(CONFIG_DEBUG_FS)
2056         unsigned i;
2057
2058         for (i = 0; i < adev->debugfs_count; i++) {
2059                 drm_debugfs_remove_files(adev->debugfs[i].files,
2060                                          adev->debugfs[i].num_files,
2061                                          adev->ddev->control);
2062                 drm_debugfs_remove_files(adev->debugfs[i].files,
2063                                          adev->debugfs[i].num_files,
2064                                          adev->ddev->primary);
2065         }
2066 #endif
2067 }
2068
2069 #if defined(CONFIG_DEBUG_FS)
2070
2071 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2072                                         size_t size, loff_t *pos)
2073 {
2074         struct amdgpu_device *adev = f->f_inode->i_private;
2075         ssize_t result = 0;
2076         int r;
2077
2078         if (size & 0x3 || *pos & 0x3)
2079                 return -EINVAL;
2080
2081         while (size) {
2082                 uint32_t value;
2083
2084                 if (*pos > adev->rmmio_size)
2085                         return result;
2086
2087                 value = RREG32(*pos >> 2);
2088                 r = put_user(value, (uint32_t *)buf);
2089                 if (r)
2090                         return r;
2091
2092                 result += 4;
2093                 buf += 4;
2094                 *pos += 4;
2095                 size -= 4;
2096         }
2097
2098         return result;
2099 }
2100
2101 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2102                                          size_t size, loff_t *pos)
2103 {
2104         struct amdgpu_device *adev = f->f_inode->i_private;
2105         ssize_t result = 0;
2106         int r;
2107
2108         if (size & 0x3 || *pos & 0x3)
2109                 return -EINVAL;
2110
2111         while (size) {
2112                 uint32_t value;
2113
2114                 if (*pos > adev->rmmio_size)
2115                         return result;
2116
2117                 r = get_user(value, (uint32_t *)buf);
2118                 if (r)
2119                         return r;
2120
2121                 WREG32(*pos >> 2, value);
2122
2123                 result += 4;
2124                 buf += 4;
2125                 *pos += 4;
2126                 size -= 4;
2127         }
2128
2129         return result;
2130 }
2131
2132 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2133                                         size_t size, loff_t *pos)
2134 {
2135         struct amdgpu_device *adev = f->f_inode->i_private;
2136         ssize_t result = 0;
2137         int r;
2138
2139         if (size & 0x3 || *pos & 0x3)
2140                 return -EINVAL;
2141
2142         while (size) {
2143                 uint32_t value;
2144
2145                 value = RREG32_PCIE(*pos >> 2);
2146                 r = put_user(value, (uint32_t *)buf);
2147                 if (r)
2148                         return r;
2149
2150                 result += 4;
2151                 buf += 4;
2152                 *pos += 4;
2153                 size -= 4;
2154         }
2155
2156         return result;
2157 }
2158
2159 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2160                                          size_t size, loff_t *pos)
2161 {
2162         struct amdgpu_device *adev = f->f_inode->i_private;
2163         ssize_t result = 0;
2164         int r;
2165
2166         if (size & 0x3 || *pos & 0x3)
2167                 return -EINVAL;
2168
2169         while (size) {
2170                 uint32_t value;
2171
2172                 r = get_user(value, (uint32_t *)buf);
2173                 if (r)
2174                         return r;
2175
2176                 WREG32_PCIE(*pos >> 2, value);
2177
2178                 result += 4;
2179                 buf += 4;
2180                 *pos += 4;
2181                 size -= 4;
2182         }
2183
2184         return result;
2185 }
2186
2187 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2188                                         size_t size, loff_t *pos)
2189 {
2190         struct amdgpu_device *adev = f->f_inode->i_private;
2191         ssize_t result = 0;
2192         int r;
2193
2194         if (size & 0x3 || *pos & 0x3)
2195                 return -EINVAL;
2196
2197         while (size) {
2198                 uint32_t value;
2199
2200                 value = RREG32_DIDT(*pos >> 2);
2201                 r = put_user(value, (uint32_t *)buf);
2202                 if (r)
2203                         return r;
2204
2205                 result += 4;
2206                 buf += 4;
2207                 *pos += 4;
2208                 size -= 4;
2209         }
2210
2211         return result;
2212 }
2213
2214 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2215                                          size_t size, loff_t *pos)
2216 {
2217         struct amdgpu_device *adev = f->f_inode->i_private;
2218         ssize_t result = 0;
2219         int r;
2220
2221         if (size & 0x3 || *pos & 0x3)
2222                 return -EINVAL;
2223
2224         while (size) {
2225                 uint32_t value;
2226
2227                 r = get_user(value, (uint32_t *)buf);
2228                 if (r)
2229                         return r;
2230
2231                 WREG32_DIDT(*pos >> 2, value);
2232
2233                 result += 4;
2234                 buf += 4;
2235                 *pos += 4;
2236                 size -= 4;
2237         }
2238
2239         return result;
2240 }
2241
2242 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2243                                         size_t size, loff_t *pos)
2244 {
2245         struct amdgpu_device *adev = f->f_inode->i_private;
2246         ssize_t result = 0;
2247         int r;
2248
2249         if (size & 0x3 || *pos & 0x3)
2250                 return -EINVAL;
2251
2252         while (size) {
2253                 uint32_t value;
2254
2255                 value = RREG32_SMC(*pos >> 2);
2256                 r = put_user(value, (uint32_t *)buf);
2257                 if (r)
2258                         return r;
2259
2260                 result += 4;
2261                 buf += 4;
2262                 *pos += 4;
2263                 size -= 4;
2264         }
2265
2266         return result;
2267 }
2268
2269 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2270                                          size_t size, loff_t *pos)
2271 {
2272         struct amdgpu_device *adev = f->f_inode->i_private;
2273         ssize_t result = 0;
2274         int r;
2275
2276         if (size & 0x3 || *pos & 0x3)
2277                 return -EINVAL;
2278
2279         while (size) {
2280                 uint32_t value;
2281
2282                 r = get_user(value, (uint32_t *)buf);
2283                 if (r)
2284                         return r;
2285
2286                 WREG32_SMC(*pos >> 2, value);
2287
2288                 result += 4;
2289                 buf += 4;
2290                 *pos += 4;
2291                 size -= 4;
2292         }
2293
2294         return result;
2295 }
2296
2297 static const struct file_operations amdgpu_debugfs_regs_fops = {
2298         .owner = THIS_MODULE,
2299         .read = amdgpu_debugfs_regs_read,
2300         .write = amdgpu_debugfs_regs_write,
2301         .llseek = default_llseek
2302 };
2303 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2304         .owner = THIS_MODULE,
2305         .read = amdgpu_debugfs_regs_didt_read,
2306         .write = amdgpu_debugfs_regs_didt_write,
2307         .llseek = default_llseek
2308 };
2309 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2310         .owner = THIS_MODULE,
2311         .read = amdgpu_debugfs_regs_pcie_read,
2312         .write = amdgpu_debugfs_regs_pcie_write,
2313         .llseek = default_llseek
2314 };
2315 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2316         .owner = THIS_MODULE,
2317         .read = amdgpu_debugfs_regs_smc_read,
2318         .write = amdgpu_debugfs_regs_smc_write,
2319         .llseek = default_llseek
2320 };
2321
2322 static const struct file_operations *debugfs_regs[] = {
2323         &amdgpu_debugfs_regs_fops,
2324         &amdgpu_debugfs_regs_didt_fops,
2325         &amdgpu_debugfs_regs_pcie_fops,
2326         &amdgpu_debugfs_regs_smc_fops,
2327 };
2328
2329 static const char *debugfs_regs_names[] = {
2330         "amdgpu_regs",
2331         "amdgpu_regs_didt",
2332         "amdgpu_regs_pcie",
2333         "amdgpu_regs_smc",
2334 };
2335
2336 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2337 {
2338         struct drm_minor *minor = adev->ddev->primary;
2339         struct dentry *ent, *root = minor->debugfs_root;
2340         unsigned i, j;
2341
2342         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2343                 ent = debugfs_create_file(debugfs_regs_names[i],
2344                                           S_IFREG | S_IRUGO, root,
2345                                           adev, debugfs_regs[i]);
2346                 if (IS_ERR(ent)) {
2347                         for (j = 0; j < i; j++) {
2348                                 debugfs_remove(adev->debugfs_regs[i]);
2349                                 adev->debugfs_regs[i] = NULL;
2350                         }
2351                         return PTR_ERR(ent);
2352                 }
2353
2354                 if (!i)
2355                         i_size_write(ent->d_inode, adev->rmmio_size);
2356                 adev->debugfs_regs[i] = ent;
2357         }
2358
2359         return 0;
2360 }
2361
2362 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2363 {
2364         unsigned i;
2365
2366         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2367                 if (adev->debugfs_regs[i]) {
2368                         debugfs_remove(adev->debugfs_regs[i]);
2369                         adev->debugfs_regs[i] = NULL;
2370                 }
2371         }
2372 }
2373
2374 int amdgpu_debugfs_init(struct drm_minor *minor)
2375 {
2376         return 0;
2377 }
2378
2379 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2380 {
2381 }
2382 #else
2383 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2384 {
2385         return 0;
2386 }
2387 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2388 #endif