drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101 #define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
 102
 103 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 104 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 105
 106 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 107 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 108 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 109   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 110
 111 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 112 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 113 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 114
 115 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 116 enum DPM_EVENT_SRC {
 117         DPM_EVENT_SRC_ANALOG = 0,
 118         DPM_EVENT_SRC_EXTERNAL = 1,
 119         DPM_EVENT_SRC_DIGITAL = 2,
 120         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 121         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 122 };
 123
 124 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 125
 126 struct polaris10_power_state *cast_phw_polaris10_power_state(
 127                                   struct pp_hw_power_state *hw_ps)
 128 {
 129         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 130                                 "Invalid Powerstate Type!",
 131                                  return NULL);
 132
 133         return (struct polaris10_power_state *)hw_ps;
 134 }
 135
 136 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 137                                  const struct pp_hw_power_state *hw_ps)
 138 {
 139         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 140                                 "Invalid Powerstate Type!",
 141                                  return NULL);
 142
 143         return (const struct polaris10_power_state *)hw_ps;
 144 }
 145
 146 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 147 {
 148         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 149                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 150                         ? true : false;
 151 }
 152
 153 /**
 154  * Find the MC microcode version and store it in the HwMgr struct
 155  *
 156  * @param    hwmgr  the address of the powerplay hardware manager.
 157  * @return   always 0
 158  */
 159 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 160 {
 161         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 162
 163         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 164
 165         return 0;
 166 }
 167
 168 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 169 {
 170         uint32_t speedCntl = 0;
 171
 172         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 173         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 174                         ixPCIE_LC_SPEED_CNTL);
 175         return((uint16_t)PHM_GET_FIELD(speedCntl,
 176                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 177 }
 178
 179 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 180 {
 181         uint32_t link_width;
 182
 183         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 184         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 185                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 186
 187         PP_ASSERT_WITH_CODE((7 >= link_width),
 188                         "Invalid PCIe lane width!", return 0);
 189
 190         return decode_pcie_lane_width(link_width);
 191 }
 192
 193 /**
 194 * Enable voltage control
 195 *
 196 * @param    pHwMgr  the address of the powerplay hardware manager.
 197 * @return   always PP_Result_OK
 198 */
 199 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 200 {
 201         PP_ASSERT_WITH_CODE(
 202                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 203                 "Failed to enable voltage DPM during DPM Start Function!",
 204                 return 1;
 205         );
 206
 207         return 0;
 208 }
 209
 210 /**
 211 * Checks if we want to support voltage control
 212 *
 213 * @param    hwmgr  the address of the powerplay hardware manager.
 214 */
 215 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 216 {
 217         const struct polaris10_hwmgr *data =
 218                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 219
 220         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 221 }
 222
 223 /**
 224 * Enable voltage control
 225 *
 226 * @param    hwmgr  the address of the powerplay hardware manager.
 227 * @return   always 0
 228 */
 229 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 230 {
 231         /* enable voltage control */
 232         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 233                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 234
 235         return 0;
 236 }
 237
 238 /**
 239 * Create Voltage Tables.
 240 *
 241 * @param    hwmgr  the address of the powerplay hardware manager.
 242 * @return   always 0
 243 */
 244 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 245 {
 246         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 247         struct phm_ppt_v1_information *table_info =
 248                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 249         int result;
 250
 251         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 252                 result = atomctrl_get_voltage_table_v3(hwmgr,
 253                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 254                                 &(data->mvdd_voltage_table));
 255                 PP_ASSERT_WITH_CODE((0 == result),
 256                                 "Failed to retrieve MVDD table.",
 257                                 return result);
 258         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 259                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 260                                 table_info->vdd_dep_on_mclk);
 261                 PP_ASSERT_WITH_CODE((0 == result),
 262                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 263                                 return result;);
 264         }
 265
 266         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 267                 result = atomctrl_get_voltage_table_v3(hwmgr,
 268                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 269                                 &(data->vddci_voltage_table));
 270                 PP_ASSERT_WITH_CODE((0 == result),
 271                                 "Failed to retrieve VDDCI table.",
 272                                 return result);
 273         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 274                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 275                                 table_info->vdd_dep_on_mclk);
 276                 PP_ASSERT_WITH_CODE((0 == result),
 277                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 278                                 return result);
 279         }
 280
 281         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 282                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 283                                 table_info->vddc_lookup_table);
 284                 PP_ASSERT_WITH_CODE((0 == result),
 285                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 286                                 return result);
 287         }
 288
 289         PP_ASSERT_WITH_CODE(
 290                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 291                         "Too many voltage values for VDDC. Trimming to fit state table.",
 292                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 293                                                                 &(data->vddc_voltage_table)));
 294
 295         PP_ASSERT_WITH_CODE(
 296                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 297                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 298                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 299                                         &(data->vddci_voltage_table)));
 300
 301         PP_ASSERT_WITH_CODE(
 302                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 303                         "Too many voltage values for MVDD. Trimming to fit state table.",
 304                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 305                                                            &(data->mvdd_voltage_table)));
 306
 307         return 0;
 308 }
 309
 310 /**
 311 * Programs static screed detection parameters
 312 *
 313 * @param    hwmgr  the address of the powerplay hardware manager.
 314 * @return   always 0
 315 */
 316 static int polaris10_program_static_screen_threshold_parameters(
 317                                                         struct pp_hwmgr *hwmgr)
 318 {
 319         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 320
 321         /* Set static screen threshold unit */
 322         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 323                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 324                         data->static_screen_threshold_unit);
 325         /* Set static screen threshold */
 326         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 327                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 328                         data->static_screen_threshold);
 329
 330         return 0;
 331 }
 332
 333 /**
 334 * Setup display gap for glitch free memory clock switching.
 335 *
 336 * @param    hwmgr  the address of the powerplay hardware manager.
 337 * @return   always  0
 338 */
 339 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 340 {
 341         uint32_t display_gap =
 342                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 343                                         ixCG_DISPLAY_GAP_CNTL);
 344
 345         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 346                         DISP_GAP, DISPLAY_GAP_IGNORE);
 347
 348         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 349                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 350
 351         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 352                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 353
 354         return 0;
 355 }
 356
 357 /**
 358 * Programs activity state transition voting clients
 359 *
 360 * @param    hwmgr  the address of the powerplay hardware manager.
 361 * @return   always  0
 362 */
 363 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 364 {
 365         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 366
 367         /* Clear reset for voting clients before enabling DPM */
 368         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 369                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 370         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 371                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 372
 373         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 374                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 375         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 376                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 377         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 378                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 379         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 380                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 381         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 382                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 383         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 384                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 385         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 386                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 387         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 388                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 389
 390         return 0;
 391 }
 392
 393 /**
 394 * Get the location of various tables inside the FW image.
 395 *
 396 * @param    hwmgr  the address of the powerplay hardware manager.
 397 * @return   always  0
 398 */
 399 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 400 {
 401         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 402         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 403         uint32_t tmp;
 404         int result;
 405         bool error = false;
 406
 407         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 408                         SMU7_FIRMWARE_HEADER_LOCATION +
 409                         offsetof(SMU74_Firmware_Header, DpmTable),
 410                         &tmp, data->sram_end);
 411
 412         if (0 == result)
 413                 data->dpm_table_start = tmp;
 414
 415         error |= (0 != result);
 416
 417         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 418                         SMU7_FIRMWARE_HEADER_LOCATION +
 419                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 420                         &tmp, data->sram_end);
 421
 422         if (!result) {
 423                 data->soft_regs_start = tmp;
 424                 smu_data->soft_regs_start = tmp;
 425         }
 426
 427         error |= (0 != result);
 428
 429         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 430                         SMU7_FIRMWARE_HEADER_LOCATION +
 431                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 432                         &tmp, data->sram_end);
 433
 434         if (!result)
 435                 data->mc_reg_table_start = tmp;
 436
 437         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 438                         SMU7_FIRMWARE_HEADER_LOCATION +
 439                         offsetof(SMU74_Firmware_Header, FanTable),
 440                         &tmp, data->sram_end);
 441
 442         if (!result)
 443                 data->fan_table_start = tmp;
 444
 445         error |= (0 != result);
 446
 447         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 448                         SMU7_FIRMWARE_HEADER_LOCATION +
 449                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 450                         &tmp, data->sram_end);
 451
 452         if (!result)
 453                 data->arb_table_start = tmp;
 454
 455         error |= (0 != result);
 456
 457         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 458                         SMU7_FIRMWARE_HEADER_LOCATION +
 459                         offsetof(SMU74_Firmware_Header, Version),
 460                         &tmp, data->sram_end);
 461
 462         if (!result)
 463                 hwmgr->microcode_version_info.SMC = tmp;
 464
 465         error |= (0 != result);
 466
 467         return error ? -1 : 0;
 468 }
 469
 470 /* Copy one arb setting to another and then switch the active set.
 471  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 472  */
 473 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 474                 uint32_t arb_src, uint32_t arb_dest)
 475 {
 476         uint32_t mc_arb_dram_timing;
 477         uint32_t mc_arb_dram_timing2;
 478         uint32_t burst_time;
 479         uint32_t mc_cg_config;
 480
 481         switch (arb_src) {
 482         case MC_CG_ARB_FREQ_F0:
 483                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 484                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 485                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 486                 break;
 487         case MC_CG_ARB_FREQ_F1:
 488                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 489                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 490                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 491                 break;
 492         default:
 493                 return -EINVAL;
 494         }
 495
 496         switch (arb_dest) {
 497         case MC_CG_ARB_FREQ_F0:
 498                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 499                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 500                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 501                 break;
 502         case MC_CG_ARB_FREQ_F1:
 503                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 504                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 505                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 506                 break;
 507         default:
 508                 return -EINVAL;
 509         }
 510
 511         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 512         mc_cg_config |= 0x0000000F;
 513         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 514         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 515
 516         return 0;
 517 }
 518
 519 /**
 520 * Initial switch from ARB F0->F1
 521 *
 522 * @param    hwmgr  the address of the powerplay hardware manager.
 523 * @return   always 0
 524 * This function is to be called from the SetPowerState table.
 525 */
 526 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 527 {
 528         return polaris10_copy_and_switch_arb_sets(hwmgr,
 529                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 530 }
 531
 532 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 533 {
 534         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 535         struct phm_ppt_v1_information *table_info =
 536                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 537         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 538         uint32_t i, max_entry;
 539
 540         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 541                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 542                         return -EINVAL);
 543
 544         if (data->use_pcie_performance_levels &&
 545                         !data->use_pcie_power_saving_levels) {
 546                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 547                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 548         } else if (!data->use_pcie_performance_levels &&
 549                         data->use_pcie_power_saving_levels) {
 550                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 551                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 552         }
 553
 554         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 555                                         SMU74_MAX_LEVELS_LINK,
 556                                         MAX_REGULAR_DPM_NUMBER);
 557
 558         if (pcie_table != NULL) {
 559                 /* max_entry is used to make sure we reserve one PCIE level
 560                  * for boot level (fix for A+A PSPP issue).
 561                  * If PCIE table from PPTable have ULV entry + 8 entries,
 562                  * then ignore the last entry.*/
 563                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 564                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 565                 for (i = 1; i < max_entry; i++) {
 566                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 567                                         get_pcie_gen_support(data->pcie_gen_cap,
 568                                                         pcie_table->entries[i].gen_speed),
 569                                         get_pcie_lane_support(data->pcie_lane_cap,
 570                                                         pcie_table->entries[i].lane_width));
 571                 }
 572                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 573
 574                 /* Setup BIF_SCLK levels */
 575                 for (i = 0; i < max_entry; i++)
 576                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 577         } else {
 578                 /* Hardcode Pcie Table */
 579                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 580                                 get_pcie_gen_support(data->pcie_gen_cap,
 581                                                 PP_Min_PCIEGen),
 582                                 get_pcie_lane_support(data->pcie_lane_cap,
 583                                                 PP_Max_PCIELane));
 584                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 585                                 get_pcie_gen_support(data->pcie_gen_cap,
 586                                                 PP_Min_PCIEGen),
 587                                 get_pcie_lane_support(data->pcie_lane_cap,
 588                                                 PP_Max_PCIELane));
 589                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 590                                 get_pcie_gen_support(data->pcie_gen_cap,
 591                                                 PP_Max_PCIEGen),
 592                                 get_pcie_lane_support(data->pcie_lane_cap,
 593                                                 PP_Max_PCIELane));
 594                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 595                                 get_pcie_gen_support(data->pcie_gen_cap,
 596                                                 PP_Max_PCIEGen),
 597                                 get_pcie_lane_support(data->pcie_lane_cap,
 598                                                 PP_Max_PCIELane));
 599                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 600                                 get_pcie_gen_support(data->pcie_gen_cap,
 601                                                 PP_Max_PCIEGen),
 602                                 get_pcie_lane_support(data->pcie_lane_cap,
 603                                                 PP_Max_PCIELane));
 604                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 605                                 get_pcie_gen_support(data->pcie_gen_cap,
 606                                                 PP_Max_PCIEGen),
 607                                 get_pcie_lane_support(data->pcie_lane_cap,
 608                                                 PP_Max_PCIELane));
 609
 610                 data->dpm_table.pcie_speed_table.count = 6;
 611         }
 612         /* Populate last level for boot PCIE level, but do not increment count. */
 613         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 614                         data->dpm_table.pcie_speed_table.count,
 615                         get_pcie_gen_support(data->pcie_gen_cap,
 616                                         PP_Min_PCIEGen),
 617                         get_pcie_lane_support(data->pcie_lane_cap,
 618                                         PP_Max_PCIELane));
 619
 620         return 0;
 621 }
 622
 623 /*
 624  * This function is to initalize all DPM state tables
 625  * for SMU7 based on the dependency table.
 626  * Dynamic state patching function will then trim these
 627  * state tables to the allowed range based
 628  * on the power policy or external client requests,
 629  * such as UVD request, etc.
 630  */
 631 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 632 {
 633         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 634         struct phm_ppt_v1_information *table_info =
 635                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 636         uint32_t i;
 637
 638         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 639                         table_info->vdd_dep_on_sclk;
 640         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 641                         table_info->vdd_dep_on_mclk;
 642
 643         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 644                         "SCLK dependency table is missing. This table is mandatory",
 645                         return -EINVAL);
 646         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 647                         "SCLK dependency table has to have is missing."
 648                         "This table is mandatory",
 649                         return -EINVAL);
 650
 651         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 652                         "MCLK dependency table is missing. This table is mandatory",
 653                         return -EINVAL);
 654         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 655                         "MCLK dependency table has to have is missing."
 656                         "This table is mandatory",
 657                         return -EINVAL);
 658
 659         /* clear the state table to reset everything to default */
 660         phm_reset_single_dpm_table(
 661                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 662         phm_reset_single_dpm_table(
 663                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 664
 665
 666         /* Initialize Sclk DPM table based on allow Sclk values */
 667         data->dpm_table.sclk_table.count = 0;
 668         for (i = 0; i < dep_sclk_table->count; i++) {
 669                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 670                                                 dep_sclk_table->entries[i].clk) {
 671
 672                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 673                                         dep_sclk_table->entries[i].clk;
 674
 675                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 676                                         (i == 0) ? true : false;
 677                         data->dpm_table.sclk_table.count++;
 678                 }
 679         }
 680
 681         /* Initialize Mclk DPM table based on allow Mclk values */
 682         data->dpm_table.mclk_table.count = 0;
 683         for (i = 0; i < dep_mclk_table->count; i++) {
 684                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 685                                 [data->dpm_table.mclk_table.count - 1].value !=
 686                                                 dep_mclk_table->entries[i].clk) {
 687                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 688                                                         dep_mclk_table->entries[i].clk;
 689                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 690                                                         (i == 0) ? true : false;
 691                         data->dpm_table.mclk_table.count++;
 692                 }
 693         }
 694
 695         /* setup PCIE gen speed levels */
 696         polaris10_setup_default_pcie_table(hwmgr);
 697
 698         /* save a copy of the default DPM table */
 699         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 700                         sizeof(struct polaris10_dpm_table));
 701
 702         return 0;
 703 }
 704
 705 uint8_t convert_to_vid(uint16_t vddc)
 706 {
 707         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 708 }
 709
 710 /**
 711  * Mvdd table preparation for SMC.
 712  *
 713  * @param    *hwmgr The address of the hardware manager.
 714  * @param    *table The SMC DPM table structure to be populated.
 715  * @return   0
 716  */
 717 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 718                         SMU74_Discrete_DpmTable *table)
 719 {
 720         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 721         uint32_t count, level;
 722
 723         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 724                 count = data->mvdd_voltage_table.count;
 725                 if (count > SMU_MAX_SMIO_LEVELS)
 726                         count = SMU_MAX_SMIO_LEVELS;
 727                 for (level = 0; level < count; level++) {
 728                         table->SmioTable2.Pattern[level].Voltage =
 729                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 730                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 731                         table->SmioTable2.Pattern[level].Smio =
 732                                 (uint8_t) level;
 733                         table->Smio[level] |=
 734                                 data->mvdd_voltage_table.entries[level].smio_low;
 735                 }
 736                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 737
 738                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 739         }
 740
 741         return 0;
 742 }
 743
 744 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 745                                         struct SMU74_Discrete_DpmTable *table)
 746 {
 747         uint32_t count, level;
 748         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 749
 750         count = data->vddci_voltage_table.count;
 751
 752         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 753                 if (count > SMU_MAX_SMIO_LEVELS)
 754                         count = SMU_MAX_SMIO_LEVELS;
 755                 for (level = 0; level < count; ++level) {
 756                         table->SmioTable1.Pattern[level].Voltage =
 757                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 758                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 759
 760                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 761                 }
 762         }
 763
 764         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 765
 766         return 0;
 767 }
 768
 769 /**
 770 * Preparation of vddc and vddgfx CAC tables for SMC.
 771 *
 772 * @param    hwmgr  the address of the hardware manager
 773 * @param    table  the SMC DPM table structure to be populated
 774 * @return   always 0
 775 */
 776 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 777                 struct SMU74_Discrete_DpmTable *table)
 778 {
 779         uint32_t count;
 780         uint8_t index;
 781         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 782         struct phm_ppt_v1_information *table_info =
 783                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 784         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 785                         table_info->vddc_lookup_table;
 786         /* tables is already swapped, so in order to use the value from it,
 787          * we need to swap it back.
 788          * We are populating vddc CAC data to BapmVddc table
 789          * in split and merged mode
 790          */
 791         for (count = 0; count < lookup_table->count; count++) {
 792                 index = phm_get_voltage_index(lookup_table,
 793                                 data->vddc_voltage_table.entries[count].value);
 794                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 795                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 796                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 797         }
 798
 799         return 0;
 800 }
 801
 802 /**
 803 * Preparation of voltage tables for SMC.
 804 *
 805 * @param    hwmgr   the address of the hardware manager
 806 * @param    table   the SMC DPM table structure to be populated
 807 * @return   always  0
 808 */
 809
 810 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 811                 struct SMU74_Discrete_DpmTable *table)
 812 {
 813         polaris10_populate_smc_vddci_table(hwmgr, table);
 814         polaris10_populate_smc_mvdd_table(hwmgr, table);
 815         polaris10_populate_cac_table(hwmgr, table);
 816
 817         return 0;
 818 }
 819
 820 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 821                 struct SMU74_Discrete_Ulv *state)
 822 {
 823         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 824         struct phm_ppt_v1_information *table_info =
 825                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 826
 827         state->CcPwrDynRm = 0;
 828         state->CcPwrDynRm1 = 0;
 829
 830         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 831         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 832                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 833
 834         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 835
 836         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 837         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 838         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 839
 840         return 0;
 841 }
 842
 843 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 844                 struct SMU74_Discrete_DpmTable *table)
 845 {
 846         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 847 }
 848
 849 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 850                 struct SMU74_Discrete_DpmTable *table)
 851 {
 852         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 853         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 854         int i;
 855
 856         /* Index (dpm_table->pcie_speed_table.count)
 857          * is reserved for PCIE boot level. */
 858         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 859                 table->LinkLevel[i].PcieGenSpeed  =
 860                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 861                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 862                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 863                 table->LinkLevel[i].EnabledForActivity = 1;
 864                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 865                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 866                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 867         }
 868
 869         data->smc_state_table.LinkLevelCount =
 870                         (uint8_t)dpm_table->pcie_speed_table.count;
 871         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 872                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 873
 874         return 0;
 875 }
 876
 877 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 878 {
 879         uint32_t reference_clock, tmp;
 880         struct cgs_display_info info = {0};
 881         struct cgs_mode_info mode_info;
 882
 883         info.mode_info = &mode_info;
 884
 885         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 886
 887         if (tmp)
 888                 return TCLK;
 889
 890         cgs_get_active_displays_info(hwmgr->device, &info);
 891         reference_clock = mode_info.ref_clock;
 892
 893         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 894
 895         if (0 != tmp)
 896                 return reference_clock / 4;
 897
 898         return reference_clock;
 899 }
 900
 901 /**
 902 * Calculates the SCLK dividers using the provided engine clock
 903 *
 904 * @param    hwmgr  the address of the hardware manager
 905 * @param    clock  the engine clock to use to populate the structure
 906 * @param    sclk   the SMC SCLK structure to be populated
 907 */
 908 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 909                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 910 {
 911         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 912         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 913         struct pp_atomctrl_clock_dividers_ai dividers;
 914
 915         uint32_t ref_clock;
 916         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 917         uint8_t i;
 918         int result;
 919         uint64_t temp;
 920
 921         sclk_setting->SclkFrequency = clock;
 922         /* get the engine clock dividers for this clock value */
 923         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 924         if (result == 0) {
 925                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 926                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 927                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 928                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 929                 sclk_setting->Sclk_slew_rate = 0x400;
 930                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 931                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 932                 sclk_setting->SSc_En = dividers.ucSscEnable;
 933                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 934                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 935                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 936                 return result;
 937         }
 938
 939         ref_clock = polaris10_get_xclk(hwmgr);
 940
 941         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 942                 if (clock > data->range_table[i].trans_lower_frequency
 943                 && clock <= data->range_table[i].trans_upper_frequency) {
 944                         sclk_setting->PllRange = i;
 945                         break;
 946                 }
 947         }
 948
 949         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 950         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 951         temp <<= 0x10;
 952         do_div(temp, ref_clock);
 953         sclk_setting->Fcw_frac = temp & 0xffff;
 954
 955         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 956         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 957         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 958
 959         ss_target_percent = 2; /*  Hardcode 2% for now. */
 960         sclk_setting->SSc_En = 0;
 961         if (ss_target_percent) {
 962                 sclk_setting->SSc_En = 1;
 963                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 964                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 965                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 966                 temp <<= 0x10;
 967                 do_div(temp, ref_clock);
 968                 sclk_setting->Fcw1_frac = temp & 0xffff;
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 975                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 976                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 977 {
 978         uint32_t i;
 979         uint16_t vddci;
 980         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 981
 982         *voltage = *mvdd = 0;
 983
 984         /* clock - voltage dependency table is empty table */
 985         if (dep_table->count == 0)
 986                 return -EINVAL;
 987
 988         for (i = 0; i < dep_table->count; i++) {
 989                 /* find first sclk bigger than request */
 990                 if (dep_table->entries[i].clk >= clock) {
 991                         *voltage |= (dep_table->entries[i].vddc *
 992                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 993                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
 994                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 995                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 996                         else if (dep_table->entries[i].vddci)
 997                                 *voltage |= (dep_table->entries[i].vddci *
 998                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 999                         else {
1000                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1001                                                 (dep_table->entries[i].vddc -
1002                                                                 (uint16_t)data->vddc_vddci_delta));
1003                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1004                         }
1005
1006                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1007                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1008                                         VOLTAGE_SCALE;
1009                         else if (dep_table->entries[i].mvdd)
1010                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1011                                         VOLTAGE_SCALE;
1012
1013                         *voltage |= 1 << PHASES_SHIFT;
1014                         return 0;
1015                 }
1016         }
1017
1018         /* sclk is bigger than max sclk in the dependence table */
1019         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1020
1021         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1022                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1023                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1024         else if (dep_table->entries[i-1].vddci) {
1025                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1026                                 (dep_table->entries[i].vddc -
1027                                                 (uint16_t)data->vddc_vddci_delta));
1028                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1029         }
1030
1031         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1032                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1033         else if (dep_table->entries[i].mvdd)
1034                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1035
1036         return 0;
1037 }
1038
1039 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1040 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1041   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1042   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1043   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1044   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1045   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1046   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1047   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1048
1049 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1050 {
1051         uint32_t i, ref_clk;
1052         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1053         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1054         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1055
1056         ref_clk = polaris10_get_xclk(hwmgr);
1057
1058         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1059                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1060                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1061                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1062                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1063
1064                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1065                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1066
1067                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1068                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1069                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1070                 }
1071                 return;
1072         }
1073
1074         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1075
1076                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1077                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1078
1079                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1080                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1081                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1082
1083                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1084                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1085
1086                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1087                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1088                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1089         }
1090 }
1091
1092 /**
1093 * Populates single SMC SCLK structure using the provided engine clock
1094 *
1095 * @param    hwmgr      the address of the hardware manager
1096 * @param    clock the engine clock to use to populate the structure
1097 * @param    sclk        the SMC SCLK structure to be populated
1098 */
1099
1100 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1101                 uint32_t clock, uint16_t sclk_al_threshold,
1102                 struct SMU74_Discrete_GraphicsLevel *level)
1103 {
1104         int result, i, temp;
1105         /* PP_Clocks minClocks; */
1106         uint32_t mvdd;
1107         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1108         struct phm_ppt_v1_information *table_info =
1109                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1110         SMU_SclkSetting curr_sclk_setting = { 0 };
1111
1112         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1113
1114         /* populate graphics levels */
1115         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1116                         table_info->vdd_dep_on_sclk, clock,
1117                         &level->MinVoltage, &mvdd);
1118
1119         PP_ASSERT_WITH_CODE((0 == result),
1120                         "can not find VDDC voltage value for "
1121                         "VDDC engine clock dependency table",
1122                         return result);
1123         level->ActivityLevel = sclk_al_threshold;
1124
1125         level->CcPwrDynRm = 0;
1126         level->CcPwrDynRm1 = 0;
1127         level->EnabledForActivity = 0;
1128         level->EnabledForThrottle = 1;
1129         level->UpHyst = 10;
1130         level->DownHyst = 0;
1131         level->VoltageDownHyst = 0;
1132         level->PowerThrottle = 0;
1133
1134         /*
1135         * TODO: get minimum clocks from dal configaration
1136         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1137         */
1138         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1139
1140         /* get level->DeepSleepDivId
1141         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1142                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1143         */
1144         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1145         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1146                 temp = clock >> i;
1147
1148                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1149                         break;
1150         }
1151
1152         level->DeepSleepDivId = i;
1153
1154         /* Default to slow, highest DPM level will be
1155          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1156          */
1157         if (data->update_up_hyst)
1158                 level->UpHyst = (uint8_t)data->up_hyst;
1159         if (data->update_down_hyst)
1160                 level->DownHyst = (uint8_t)data->down_hyst;
1161
1162         level->SclkSetting = curr_sclk_setting;
1163
1164         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1165         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1166         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1167         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1168         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1169         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1170         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1171         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1172         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1173         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1174         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1175         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1176         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1177         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1178         return 0;
1179 }
1180
1181 /**
1182 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1183 *
1184 * @param    hwmgr      the address of the hardware manager
1185 */
1186 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1187 {
1188         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1189         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1190         struct phm_ppt_v1_information *table_info =
1191                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1192         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1193         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1194         int result = 0;
1195         uint32_t array = data->dpm_table_start +
1196                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1197         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1198                         SMU74_MAX_LEVELS_GRAPHICS;
1199         struct SMU74_Discrete_GraphicsLevel *levels =
1200                         data->smc_state_table.GraphicsLevel;
1201         uint32_t i, max_entry;
1202         uint8_t hightest_pcie_level_enabled = 0,
1203                 lowest_pcie_level_enabled = 0,
1204                 mid_pcie_level_enabled = 0,
1205                 count = 0;
1206
1207         polaris10_get_sclk_range_table(hwmgr);
1208
1209         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1210
1211                 result = polaris10_populate_single_graphic_level(hwmgr,
1212                                 dpm_table->sclk_table.dpm_levels[i].value,
1213                                 (uint16_t)data->activity_target[i],
1214                                 &(data->smc_state_table.GraphicsLevel[i]));
1215                 if (result)
1216                         return result;
1217
1218                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1219                 if (i > 1)
1220                         levels[i].DeepSleepDivId = 0;
1221         }
1222         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1223                                         PHM_PlatformCaps_SPLLShutdownSupport))
1224                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1225
1226         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1227         data->smc_state_table.GraphicsDpmLevelCount =
1228                         (uint8_t)dpm_table->sclk_table.count;
1229         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1230                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1231
1232
1233         if (pcie_table != NULL) {
1234                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1235                                 "There must be 1 or more PCIE levels defined in PPTable.",
1236                                 return -EINVAL);
1237                 max_entry = pcie_entry_cnt - 1;
1238                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1239                         levels[i].pcieDpmLevel =
1240                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1241         } else {
1242                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1243                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1244                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1245                         hightest_pcie_level_enabled++;
1246
1247                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1248                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1249                                                 (1 << lowest_pcie_level_enabled)) == 0))
1250                         lowest_pcie_level_enabled++;
1251
1252                 while ((count < hightest_pcie_level_enabled) &&
1253                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1254                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1255                         count++;
1256
1257                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1258                                 hightest_pcie_level_enabled ?
1259                                                 (lowest_pcie_level_enabled + 1 + count) :
1260                                                 hightest_pcie_level_enabled;
1261
1262                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1263                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1264                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1265
1266                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1267                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1268
1269                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1270                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1271         }
1272         /* level count will send to smc once at init smc table and never change */
1273         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1274                         (uint32_t)array_size, data->sram_end);
1275
1276         return result;
1277 }
1278
1279 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1280                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1281 {
1282         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1283         struct phm_ppt_v1_information *table_info =
1284                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1285         int result = 0;
1286         struct cgs_display_info info = {0, 0, NULL};
1287
1288         cgs_get_active_displays_info(hwmgr->device, &info);
1289
1290         if (table_info->vdd_dep_on_mclk) {
1291                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1292                                 table_info->vdd_dep_on_mclk, clock,
1293                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1294                 PP_ASSERT_WITH_CODE((0 == result),
1295                                 "can not find MinVddc voltage value from memory "
1296                                 "VDDC voltage dependency table", return result);
1297         }
1298
1299         mem_level->MclkFrequency = clock;
1300         mem_level->EnabledForThrottle = 1;
1301         mem_level->EnabledForActivity = 0;
1302         mem_level->UpHyst = 0;
1303         mem_level->DownHyst = 100;
1304         mem_level->VoltageDownHyst = 0;
1305         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1306         mem_level->StutterEnable = false;
1307         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1308
1309         data->display_timing.num_existing_displays = info.display_count;
1310
1311         if ((data->mclk_stutter_mode_threshold) &&
1312                 (clock <= data->mclk_stutter_mode_threshold) &&
1313                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1314                                 STUTTER_ENABLE) & 0x1))
1315                 mem_level->StutterEnable = true;
1316
1317         if (!result) {
1318                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1319                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1320                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1321                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1322         }
1323         return result;
1324 }
1325
1326 /**
1327 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1328 *
1329 * @param    hwmgr      the address of the hardware manager
1330 */
1331 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1332 {
1333         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1334         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1335         int result;
1336         /* populate MCLK dpm table to SMU7 */
1337         uint32_t array = data->dpm_table_start +
1338                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1339         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1340                         SMU74_MAX_LEVELS_MEMORY;
1341         struct SMU74_Discrete_MemoryLevel *levels =
1342                         data->smc_state_table.MemoryLevel;
1343         uint32_t i;
1344
1345         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1346                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1347                                 "can not populate memory level as memory clock is zero",
1348                                 return -EINVAL);
1349                 result = polaris10_populate_single_memory_level(hwmgr,
1350                                 dpm_table->mclk_table.dpm_levels[i].value,
1351                                 &levels[i]);
1352                 if (i == dpm_table->mclk_table.count - 1) {
1353                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1354                         levels[i].EnabledForActivity = 1;
1355                 }
1356                 if (result)
1357                         return result;
1358         }
1359
1360         /* in order to prevent MC activity from stutter mode to push DPM up.
1361          * the UVD change complements this by putting the MCLK in
1362          * a higher state by default such that we are not effected by
1363          * up threshold or and MCLK DPM latency.
1364          */
1365         levels[0].ActivityLevel = 0x1f;
1366         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1367
1368         data->smc_state_table.MemoryDpmLevelCount =
1369                         (uint8_t)dpm_table->mclk_table.count;
1370         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1371                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1372
1373         /* level count will send to smc once at init smc table and never change */
1374         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1375                         (uint32_t)array_size, data->sram_end);
1376
1377         return result;
1378 }
1379
1380 /**
1381 * Populates the SMC MVDD structure using the provided memory clock.
1382 *
1383 * @param    hwmgr      the address of the hardware manager
1384 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1385 * @param    voltage     the SMC VOLTAGE structure to be populated
1386 */
1387 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1388                 uint32_t mclk, SMIO_Pattern *smio_pat)
1389 {
1390         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1391         struct phm_ppt_v1_information *table_info =
1392                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1393         uint32_t i = 0;
1394
1395         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1396                 /* find mvdd value which clock is more than request */
1397                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1398                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1399                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1400                                 break;
1401                         }
1402                 }
1403                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1404                                 "MVDD Voltage is outside the supported range.",
1405                                 return -EINVAL);
1406         } else
1407                 return -EINVAL;
1408
1409         return 0;
1410 }
1411
1412 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1413                 SMU74_Discrete_DpmTable *table)
1414 {
1415         int result = 0;
1416         uint32_t sclk_frequency;
1417         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1418         struct phm_ppt_v1_information *table_info =
1419                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1420         SMIO_Pattern vol_level;
1421         uint32_t mvdd;
1422         uint16_t us_mvdd;
1423
1424         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1425
1426
1427         /* Get MinVoltage and Frequency from DPM0,
1428          * already converted to SMC_UL */
1429         sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1430         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1431                         table_info->vdd_dep_on_sclk,
1432                         sclk_frequency,
1433                         &table->ACPILevel.MinVoltage, &mvdd);
1434         PP_ASSERT_WITH_CODE((0 == result),
1435                         "Cannot find ACPI VDDC voltage value "
1436                         "in Clock Dependency Table",
1437                         );
1438
1439
1440         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1441         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1442
1443         table->ACPILevel.DeepSleepDivId = 0;
1444         table->ACPILevel.CcPwrDynRm = 0;
1445         table->ACPILevel.CcPwrDynRm1 = 0;
1446
1447         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1448         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1449         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1450         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1451
1452         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1453         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1454         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1455         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1456         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1457         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1458         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1459         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1460         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1461         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1462
1463
1464         /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1465         table->MemoryACPILevel.MclkFrequency =
1466                         data->dpm_table.mclk_table.dpm_levels[0].value;
1467         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1468                         table_info->vdd_dep_on_mclk,
1469                         table->MemoryACPILevel.MclkFrequency,
1470                         &table->MemoryACPILevel.MinVoltage, &mvdd);
1471         PP_ASSERT_WITH_CODE((0 == result),
1472                         "Cannot find ACPI VDDCI voltage value "
1473                         "in Clock Dependency Table",
1474                         );
1475
1476         us_mvdd = 0;
1477         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1478                         (data->mclk_dpm_key_disabled))
1479                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1480         else {
1481                 if (!polaris10_populate_mvdd_value(hwmgr,
1482                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1483                                 &vol_level))
1484                         us_mvdd = vol_level.Voltage;
1485         }
1486
1487         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1488                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1489         else
1490                 table->MemoryACPILevel.MinMvdd = 0;
1491
1492         table->MemoryACPILevel.StutterEnable = false;
1493
1494         table->MemoryACPILevel.EnabledForThrottle = 0;
1495         table->MemoryACPILevel.EnabledForActivity = 0;
1496         table->MemoryACPILevel.UpHyst = 0;
1497         table->MemoryACPILevel.DownHyst = 100;
1498         table->MemoryACPILevel.VoltageDownHyst = 0;
1499         table->MemoryACPILevel.ActivityLevel =
1500                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1501
1502         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1503         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1504
1505         return result;
1506 }
1507
1508 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1509                 SMU74_Discrete_DpmTable *table)
1510 {
1511         int result = -EINVAL;
1512         uint8_t count;
1513         struct pp_atomctrl_clock_dividers_vi dividers;
1514         struct phm_ppt_v1_information *table_info =
1515                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1516         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1517                         table_info->mm_dep_table;
1518         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1519         uint32_t vddci;
1520
1521         table->VceLevelCount = (uint8_t)(mm_table->count);
1522         table->VceBootLevel = 0;
1523
1524         for (count = 0; count < table->VceLevelCount; count++) {
1525                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1526                 table->VceLevel[count].MinVoltage = 0;
1527                 table->VceLevel[count].MinVoltage |=
1528                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1529
1530                 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1531                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1532                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1533                 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1534                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1535                 else
1536                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1537
1538
1539                 table->VceLevel[count].MinVoltage |=
1540                                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1541                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1542
1543                 /*retrieve divider value for VBIOS */
1544                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1545                                 table->VceLevel[count].Frequency, &dividers);
1546                 PP_ASSERT_WITH_CODE((0 == result),
1547                                 "can not find divide id for VCE engine clock",
1548                                 return result);
1549
1550                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1551
1552                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1553                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1554         }
1555         return result;
1556 }
1557
1558 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1559                 SMU74_Discrete_DpmTable *table)
1560 {
1561         int result = -EINVAL;
1562         uint8_t count;
1563         struct pp_atomctrl_clock_dividers_vi dividers;
1564         struct phm_ppt_v1_information *table_info =
1565                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1566         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1567                         table_info->mm_dep_table;
1568         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1569         uint32_t vddci;
1570
1571         table->SamuBootLevel = 0;
1572         table->SamuLevelCount = (uint8_t)(mm_table->count);
1573
1574         for (count = 0; count < table->SamuLevelCount; count++) {
1575                 /* not sure whether we need evclk or not */
1576                 table->SamuLevel[count].MinVoltage = 0;
1577                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1578                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1579                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1580
1581                 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1582                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1583                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1584                 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1585                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1586                 else
1587                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1588
1589                 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1590                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1591
1592                 /* retrieve divider value for VBIOS */
1593                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1594                                 table->SamuLevel[count].Frequency, &dividers);
1595                 PP_ASSERT_WITH_CODE((0 == result),
1596                                 "can not find divide id for samu clock", return result);
1597
1598                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1599
1600                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1601                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1602         }
1603         return result;
1604 }
1605
1606 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1607                 int32_t eng_clock, int32_t mem_clock,
1608                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1609 {
1610         uint32_t dram_timing;
1611         uint32_t dram_timing2;
1612         uint32_t burst_time;
1613         int result;
1614
1615         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1616                         eng_clock, mem_clock);
1617         PP_ASSERT_WITH_CODE(result == 0,
1618                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1619
1620         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1621         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1622         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1623
1624
1625         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1626         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1627         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1628
1629         return 0;
1630 }
1631
1632 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1633 {
1634         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1635         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1636         uint32_t i, j;
1637         int result = 0;
1638
1639         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1640                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1641                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1642                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1643                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1644                                         &arb_regs.entries[i][j]);
1645                         if (result == 0)
1646                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1647                         if (result != 0)
1648                                 return result;
1649                 }
1650         }
1651
1652         result = polaris10_copy_bytes_to_smc(
1653                         hwmgr->smumgr,
1654                         data->arb_table_start,
1655                         (uint8_t *)&arb_regs,
1656                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1657                         data->sram_end);
1658         return result;
1659 }
1660
1661 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1662                 struct SMU74_Discrete_DpmTable *table)
1663 {
1664         int result = -EINVAL;
1665         uint8_t count;
1666         struct pp_atomctrl_clock_dividers_vi dividers;
1667         struct phm_ppt_v1_information *table_info =
1668                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1669         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1670                         table_info->mm_dep_table;
1671         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1672         uint32_t vddci;
1673
1674         table->UvdLevelCount = (uint8_t)(mm_table->count);
1675         table->UvdBootLevel = 0;
1676
1677         for (count = 0; count < table->UvdLevelCount; count++) {
1678                 table->UvdLevel[count].MinVoltage = 0;
1679                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1680                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1681                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1682                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1683
1684                 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1685                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1686                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1687                 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1688                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1689                 else
1690                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1691
1692                 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1693                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1694
1695                 /* retrieve divider value for VBIOS */
1696                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1697                                 table->UvdLevel[count].VclkFrequency, &dividers);
1698                 PP_ASSERT_WITH_CODE((0 == result),
1699                                 "can not find divide id for Vclk clock", return result);
1700
1701                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1702
1703                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1704                                 table->UvdLevel[count].DclkFrequency, &dividers);
1705                 PP_ASSERT_WITH_CODE((0 == result),
1706                                 "can not find divide id for Dclk clock", return result);
1707
1708                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1709
1710                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1711                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1712                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1713         }
1714
1715         return result;
1716 }
1717
1718 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1719                 struct SMU74_Discrete_DpmTable *table)
1720 {
1721         int result = 0;
1722         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1723
1724         table->GraphicsBootLevel = 0;
1725         table->MemoryBootLevel = 0;
1726
1727         /* find boot level from dpm table */
1728         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1729                         data->vbios_boot_state.sclk_bootup_value,
1730                         (uint32_t *)&(table->GraphicsBootLevel));
1731
1732         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1733                         data->vbios_boot_state.mclk_bootup_value,
1734                         (uint32_t *)&(table->MemoryBootLevel));
1735
1736         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1737                         VOLTAGE_SCALE;
1738         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1739                         VOLTAGE_SCALE;
1740         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1741                         VOLTAGE_SCALE;
1742
1743         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1744         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1745         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1746
1747         return 0;
1748 }
1749
1750
1751 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1752 {
1753         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1754         struct phm_ppt_v1_information *table_info =
1755                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1756         uint8_t count, level;
1757
1758         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1759
1760         for (level = 0; level < count; level++) {
1761                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1762                                 data->vbios_boot_state.sclk_bootup_value) {
1763                         data->smc_state_table.GraphicsBootLevel = level;
1764                         break;
1765                 }
1766         }
1767
1768         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1769         for (level = 0; level < count; level++) {
1770                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1771                                 data->vbios_boot_state.mclk_bootup_value) {
1772                         data->smc_state_table.MemoryBootLevel = level;
1773                         break;
1774                 }
1775         }
1776
1777         return 0;
1778 }
1779
1780 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1781 {
1782         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1783         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1784         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1785         struct phm_ppt_v1_information *table_info =
1786                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1787         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1788                         table_info->vdd_dep_on_sclk;
1789
1790         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1791
1792         /* Read SMU_Eefuse to read and calculate RO and determine
1793          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1794          */
1795         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1796                         ixSMU_EFUSE_0 + (67 * 4));
1797         efuse &= 0xFF000000;
1798         efuse = efuse >> 24;
1799
1800         if (hwmgr->chip_id == CHIP_POLARIS10) {
1801                 min = 1000;
1802                 max = 2300;
1803         } else {
1804                 min = 1100;
1805                 max = 2100;
1806         }
1807
1808         ro = efuse * (max -min)/255 + min;
1809
1810         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
1811          * there is a little difference in calculating
1812          * volt_with_cks with windows */
1813         for (i = 0; i < sclk_table->count; i++) {
1814                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1815                                 sclk_table->entries[i].cks_enable << i;
1816                 if (hwmgr->chip_id == CHIP_POLARIS10) {
1817                         volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1818                                                 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1819                         volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
1820                                         (252248000 - sclk_table->entries[i].clk/100 * 115764));
1821                 } else {
1822                         volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1823                                                 (2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
1824                         volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
1825                                         (3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
1826                 }
1827
1828                 if (volt_without_cks >= volt_with_cks)
1829                         volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
1830                                         sclk_table->entries[i].cks_voffset) * 100 / 625);
1831
1832                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1833         }
1834
1835         data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1836         /* Populate CKS Lookup Table */
1837         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1838                 stretch_amount2 = 0;
1839         else if (stretch_amount == 3 || stretch_amount == 4)
1840                 stretch_amount2 = 1;
1841         else {
1842                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1843                                 PHM_PlatformCaps_ClockStretcher);
1844                 PP_ASSERT_WITH_CODE(false,
1845                                 "Stretch Amount in PPTable not supported\n",
1846                                 return -EINVAL);
1847         }
1848
1849         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1850         value &= 0xFFFFFFFE;
1851         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1852
1853         return 0;
1854 }
1855
1856 /**
1857 * Populates the SMC VRConfig field in DPM table.
1858 *
1859 * @param    hwmgr   the address of the hardware manager
1860 * @param    table   the SMC DPM table structure to be populated
1861 * @return   always 0
1862 */
1863 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1864                 struct SMU74_Discrete_DpmTable *table)
1865 {
1866         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1867         uint16_t config;
1868
1869         config = VR_MERGED_WITH_VDDC;
1870         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1871
1872         /* Set Vddc Voltage Controller */
1873         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1874                 config = VR_SVI2_PLANE_1;
1875                 table->VRConfig |= config;
1876         } else {
1877                 PP_ASSERT_WITH_CODE(false,
1878                                 "VDDC should be on SVI2 control in merged mode!",
1879                                 );
1880         }
1881         /* Set Vddci Voltage Controller */
1882         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1883                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1884                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1885         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1886                 config = VR_SMIO_PATTERN_1;
1887                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1888         } else {
1889                 config = VR_STATIC_VOLTAGE;
1890                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1891         }
1892         /* Set Mvdd Voltage Controller */
1893         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1894                 config = VR_SVI2_PLANE_2;
1895                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1896         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1897                 config = VR_SMIO_PATTERN_2;
1898                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1899         } else {
1900                 config = VR_STATIC_VOLTAGE;
1901                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1902         }
1903
1904         return 0;
1905 }
1906
1907
1908 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1909 {
1910         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1911         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1912         int result = 0;
1913         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1914         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1915         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1916         uint32_t tmp, i;
1917         struct pp_smumgr *smumgr = hwmgr->smumgr;
1918         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1919
1920         struct phm_ppt_v1_information *table_info =
1921                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1922         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1923                         table_info->vdd_dep_on_sclk;
1924
1925
1926         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1927                 return result;
1928
1929         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1930
1931         if (0 == result) {
1932                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1933                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1934                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1935                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1936                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1937                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1938                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1939                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1940                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1941                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1942                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1943                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1944                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1945                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1946                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1947                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1948                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1949                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1950                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1951                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1952                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1953                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1954                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1955                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1956
1957                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1958                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1959                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1960                 }
1961
1962                 result = polaris10_read_smc_sram_dword(smumgr,
1963                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1964                                 &tmp, data->sram_end);
1965
1966                 polaris10_copy_bytes_to_smc(smumgr,
1967                                         tmp,
1968                                         (uint8_t *)&AVFS_meanNsigma,
1969                                         sizeof(AVFS_meanNsigma_t),
1970                                         data->sram_end);
1971
1972                 result = polaris10_read_smc_sram_dword(smumgr,
1973                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1974                                 &tmp, data->sram_end);
1975                 polaris10_copy_bytes_to_smc(smumgr,
1976                                         tmp,
1977                                         (uint8_t *)&AVFS_SclkOffset,
1978                                         sizeof(AVFS_Sclk_Offset_t),
1979                                         data->sram_end);
1980
1981                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1982                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1983                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1984                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1985                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1986         }
1987         return result;
1988 }
1989
1990
1991 /**
1992 * Initializes the SMC table and uploads it
1993 *
1994 * @param    hwmgr  the address of the powerplay hardware manager.
1995 * @return   always 0
1996 */
1997 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1998 {
1999         int result;
2000         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2001         struct phm_ppt_v1_information *table_info =
2002                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2003         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2004         const struct polaris10_ulv_parm *ulv = &(data->ulv);
2005         uint8_t i;
2006         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2007         pp_atomctrl_clock_dividers_vi dividers;
2008
2009         result = polaris10_setup_default_dpm_tables(hwmgr);
2010         PP_ASSERT_WITH_CODE(0 == result,
2011                         "Failed to setup default DPM tables!", return result);
2012
2013         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2014                 polaris10_populate_smc_voltage_tables(hwmgr, table);
2015
2016         table->SystemFlags = 0;
2017         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2018                         PHM_PlatformCaps_AutomaticDCTransition))
2019                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2020
2021         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2022                         PHM_PlatformCaps_StepVddc))
2023                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2024
2025         if (data->is_memory_gddr5)
2026                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2027
2028         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2029                 result = polaris10_populate_ulv_state(hwmgr, table);
2030                 PP_ASSERT_WITH_CODE(0 == result,
2031                                 "Failed to initialize ULV state!", return result);
2032                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2033                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2034         }
2035
2036         result = polaris10_populate_smc_link_level(hwmgr, table);
2037         PP_ASSERT_WITH_CODE(0 == result,
2038                         "Failed to initialize Link Level!", return result);
2039
2040         result = polaris10_populate_all_graphic_levels(hwmgr);
2041         PP_ASSERT_WITH_CODE(0 == result,
2042                         "Failed to initialize Graphics Level!", return result);
2043
2044         result = polaris10_populate_all_memory_levels(hwmgr);
2045         PP_ASSERT_WITH_CODE(0 == result,
2046                         "Failed to initialize Memory Level!", return result);
2047
2048         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2049         PP_ASSERT_WITH_CODE(0 == result,
2050                         "Failed to initialize ACPI Level!", return result);
2051
2052         result = polaris10_populate_smc_vce_level(hwmgr, table);
2053         PP_ASSERT_WITH_CODE(0 == result,
2054                         "Failed to initialize VCE Level!", return result);
2055
2056         result = polaris10_populate_smc_samu_level(hwmgr, table);
2057         PP_ASSERT_WITH_CODE(0 == result,
2058                         "Failed to initialize SAMU Level!", return result);
2059
2060         /* Since only the initial state is completely set up at this point
2061          * (the other states are just copies of the boot state) we only
2062          * need to populate the  ARB settings for the initial state.
2063          */
2064         result = polaris10_program_memory_timing_parameters(hwmgr);
2065         PP_ASSERT_WITH_CODE(0 == result,
2066                         "Failed to Write ARB settings for the initial state.", return result);
2067
2068         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2069         PP_ASSERT_WITH_CODE(0 == result,
2070                         "Failed to initialize UVD Level!", return result);
2071
2072         result = polaris10_populate_smc_boot_level(hwmgr, table);
2073         PP_ASSERT_WITH_CODE(0 == result,
2074                         "Failed to initialize Boot Level!", return result);
2075
2076         result = polaris10_populate_smc_initailial_state(hwmgr);
2077         PP_ASSERT_WITH_CODE(0 == result,
2078                         "Failed to initialize Boot State!", return result);
2079
2080         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2081         PP_ASSERT_WITH_CODE(0 == result,
2082                         "Failed to populate BAPM Parameters!", return result);
2083
2084         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2085                         PHM_PlatformCaps_ClockStretcher)) {
2086                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2087                 PP_ASSERT_WITH_CODE(0 == result,
2088                                 "Failed to populate Clock Stretcher Data Table!",
2089                                 return result);
2090         }
2091
2092         result = polaris10_populate_avfs_parameters(hwmgr);
2093         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2094
2095         table->CurrSclkPllRange = 0xff;
2096         table->GraphicsVoltageChangeEnable  = 1;
2097         table->GraphicsThermThrottleEnable  = 1;
2098         table->GraphicsInterval = 1;
2099         table->VoltageInterval  = 1;
2100         table->ThermalInterval  = 1;
2101         table->TemperatureLimitHigh =
2102                         table_info->cac_dtp_table->usTargetOperatingTemp *
2103                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2104         table->TemperatureLimitLow  =
2105                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2106                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2107         table->MemoryVoltageChangeEnable = 1;
2108         table->MemoryInterval = 1;
2109         table->VoltageResponseTime = 0;
2110         table->PhaseResponseTime = 0;
2111         table->MemoryThermThrottleEnable = 1;
2112         table->PCIeBootLinkLevel = 0;
2113         table->PCIeGenInterval = 1;
2114         table->VRConfig = 0;
2115
2116         result = polaris10_populate_vr_config(hwmgr, table);
2117         PP_ASSERT_WITH_CODE(0 == result,
2118                         "Failed to populate VRConfig setting!", return result);
2119
2120         table->ThermGpio = 17;
2121         table->SclkStepSize = 0x4000;
2122
2123         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2124                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2125         } else {
2126                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2127                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2128                                 PHM_PlatformCaps_RegulatorHot);
2129         }
2130
2131         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2132                         &gpio_pin)) {
2133                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2134                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2135                                 PHM_PlatformCaps_AutomaticDCTransition);
2136         } else {
2137                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2138                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2139                                 PHM_PlatformCaps_AutomaticDCTransition);
2140         }
2141
2142         /* Thermal Output GPIO */
2143         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2144                         &gpio_pin)) {
2145                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2146                                 PHM_PlatformCaps_ThermalOutGPIO);
2147
2148                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2149
2150                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2151                  * since VBIOS will program this register to set 'inactive state',
2152                  * driver can then determine 'active state' from this and
2153                  * program SMU with correct polarity
2154                  */
2155                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2156                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2157                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2158
2159                 /* if required, combine VRHot/PCC with thermal out GPIO */
2160                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2161                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2162                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2163         } else {
2164                 table->ThermOutGpio = 17;
2165                 table->ThermOutPolarity = 1;
2166                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2167         }
2168
2169         /* Populate BIF_SCLK levels into SMC DPM table */
2170         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2171                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2172                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2173
2174                 if (i == 0)
2175                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2176                 else
2177                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2178         }
2179
2180         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2181                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2182
2183         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2184         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2185         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2186         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2187         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2188         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2189         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2190         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2191         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2192         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2193
2194         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2195         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2196                         data->dpm_table_start +
2197                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2198                         (uint8_t *)&(table->SystemFlags),
2199                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2200                         data->sram_end);
2201         PP_ASSERT_WITH_CODE(0 == result,
2202                         "Failed to upload dpm data to SMC memory!", return result);
2203
2204         return 0;
2205 }
2206
2207 /**
2208 * Initialize the ARB DRAM timing table's index field.
2209 *
2210 * @param    hwmgr  the address of the powerplay hardware manager.
2211 * @return   always 0
2212 */
2213 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2214 {
2215         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2216         uint32_t tmp;
2217         int result;
2218
2219         /* This is a read-modify-write on the first byte of the ARB table.
2220          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2221          * is the field 'current'.
2222          * This solution is ugly, but we never write the whole table only
2223          * individual fields in it.
2224          * In reality this field should not be in that structure
2225          * but in a soft register.
2226          */
2227         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2228                         data->arb_table_start, &tmp, data->sram_end);
2229
2230         if (result)
2231                 return result;
2232
2233         tmp &= 0x00FFFFFF;
2234         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2235
2236         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2237                         data->arb_table_start, tmp, data->sram_end);
2238 }
2239
2240 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2241 {
2242         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2243                         PHM_PlatformCaps_RegulatorHot))
2244                 return smum_send_msg_to_smc(hwmgr->smumgr,
2245                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2246
2247         return 0;
2248 }
2249
2250 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2251 {
2252         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2253                         SCLK_PWRMGT_OFF, 0);
2254         return 0;
2255 }
2256
2257 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2258 {
2259         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2260         struct polaris10_ulv_parm *ulv = &(data->ulv);
2261
2262         if (ulv->ulv_supported)
2263                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2264
2265         return 0;
2266 }
2267
2268 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2269 {
2270         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2271                         PHM_PlatformCaps_SclkDeepSleep)) {
2272                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2273                         PP_ASSERT_WITH_CODE(false,
2274                                         "Attempt to enable Master Deep Sleep switch failed!",
2275                                         return -1);
2276         } else {
2277                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2278                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2279                         PP_ASSERT_WITH_CODE(false,
2280                                         "Attempt to disable Master Deep Sleep switch failed!",
2281                                         return -1);
2282                 }
2283         }
2284
2285         return 0;
2286 }
2287
2288 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2289 {
2290         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2291         uint32_t soft_register_value = 0;
2292         uint32_t handshake_disables_offset = data->soft_regs_start
2293                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2294
2295         /* enable SCLK dpm */
2296         if (!data->sclk_dpm_key_disabled)
2297                 PP_ASSERT_WITH_CODE(
2298                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2299                 "Failed to enable SCLK DPM during DPM Start Function!",
2300                 return -1);
2301
2302         /* enable MCLK dpm */
2303         if (0 == data->mclk_dpm_key_disabled) {
2304 /* Disable UVD - SMU handshake for MCLK. */
2305                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2306                                         CGS_IND_REG__SMC, handshake_disables_offset);
2307                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2308                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2309                                 handshake_disables_offset, soft_register_value);
2310
2311                 PP_ASSERT_WITH_CODE(
2312                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2313                                                 PPSMC_MSG_MCLKDPM_Enable)),
2314                                 "Failed to enable MCLK DPM during DPM Start Function!",
2315                                 return -1);
2316
2317                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2318
2319                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2320                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2321                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2322                 udelay(10);
2323                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2324                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2325                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2326         }
2327
2328         return 0;
2329 }
2330
2331 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2332 {
2333         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2334
2335         /*enable general power management */
2336
2337         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2338                         GLOBAL_PWRMGT_EN, 1);
2339
2340         /* enable sclk deep sleep */
2341
2342         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2343                         DYNAMIC_PM_EN, 1);
2344
2345         /* prepare for PCIE DPM */
2346
2347         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2348                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2349                                         VoltageChangeTimeout), 0x1000);
2350         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2351                         SWRST_COMMAND_1, RESETLC, 0x0);
2352 /*
2353         PP_ASSERT_WITH_CODE(
2354                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2355                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2356                         "Failed to enable voltage DPM during DPM Start Function!",
2357                         return -1);
2358 */
2359
2360         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2361                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2362                 return -1;
2363         }
2364
2365         /* enable PCIE dpm */
2366         if (0 == data->pcie_dpm_key_disabled) {
2367                 PP_ASSERT_WITH_CODE(
2368                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2369                                                 PPSMC_MSG_PCIeDPM_Enable)),
2370                                 "Failed to enable pcie DPM during DPM Start Function!",
2371                                 return -1);
2372         }
2373
2374         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2375                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2376                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2377                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2378                                 "Failed to enable AC DC GPIO Interrupt!",
2379                                 );
2380         }
2381
2382         return 0;
2383 }
2384
2385 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2386 {
2387         bool protection;
2388         enum DPM_EVENT_SRC src;
2389
2390         switch (sources) {
2391         default:
2392                 printk(KERN_ERR "Unknown throttling event sources.");
2393                 /* fall through */
2394         case 0:
2395                 protection = false;
2396                 /* src is unused */
2397                 break;
2398         case (1 << PHM_AutoThrottleSource_Thermal):
2399                 protection = true;
2400                 src = DPM_EVENT_SRC_DIGITAL;
2401                 break;
2402         case (1 << PHM_AutoThrottleSource_External):
2403                 protection = true;
2404                 src = DPM_EVENT_SRC_EXTERNAL;
2405                 break;
2406         case (1 << PHM_AutoThrottleSource_External) |
2407                         (1 << PHM_AutoThrottleSource_Thermal):
2408                 protection = true;
2409                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2410                 break;
2411         }
2412         /* Order matters - don't enable thermal protection for the wrong source. */
2413         if (protection) {
2414                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2415                                 DPM_EVENT_SRC, src);
2416                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2417                                 THERMAL_PROTECTION_DIS,
2418                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2419                                                 PHM_PlatformCaps_ThermalController));
2420         } else
2421                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2422                                 THERMAL_PROTECTION_DIS, 1);
2423 }
2424
2425 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2426                 PHM_AutoThrottleSource source)
2427 {
2428         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2429
2430         if (!(data->active_auto_throttle_sources & (1 << source))) {
2431                 data->active_auto_throttle_sources |= 1 << source;
2432                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2433         }
2434         return 0;
2435 }
2436
2437 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2438 {
2439         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2440 }
2441
2442 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2443 {
2444         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2445         data->pcie_performance_request = true;
2446
2447         return 0;
2448 }
2449
2450 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2451 {
2452         int tmp_result, result = 0;
2453         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2454         PP_ASSERT_WITH_CODE(result == 0,
2455                         "DPM is already running right now, no need to enable DPM!",
2456                         return 0);
2457
2458         if (polaris10_voltage_control(hwmgr)) {
2459                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2460                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2461                                 "Failed to enable voltage control!",
2462                                 result = tmp_result);
2463
2464                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2465                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2466                                 "Failed to contruct voltage tables!",
2467                                 result = tmp_result);
2468         }
2469
2470         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2471                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2472                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2473                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2474
2475         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2476                         PHM_PlatformCaps_ThermalController))
2477                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2478                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2479
2480         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2481         PP_ASSERT_WITH_CODE((0 == tmp_result),
2482                         "Failed to program static screen threshold parameters!",
2483                         result = tmp_result);
2484
2485         tmp_result = polaris10_enable_display_gap(hwmgr);
2486         PP_ASSERT_WITH_CODE((0 == tmp_result),
2487                         "Failed to enable display gap!", result = tmp_result);
2488
2489         tmp_result = polaris10_program_voting_clients(hwmgr);
2490         PP_ASSERT_WITH_CODE((0 == tmp_result),
2491                         "Failed to program voting clients!", result = tmp_result);
2492
2493         tmp_result = polaris10_process_firmware_header(hwmgr);
2494         PP_ASSERT_WITH_CODE((0 == tmp_result),
2495                         "Failed to process firmware header!", result = tmp_result);
2496
2497         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2498         PP_ASSERT_WITH_CODE((0 == tmp_result),
2499                         "Failed to initialize switch from ArbF0 to F1!",
2500                         result = tmp_result);
2501
2502         tmp_result = polaris10_init_smc_table(hwmgr);
2503         PP_ASSERT_WITH_CODE((0 == tmp_result),
2504                         "Failed to initialize SMC table!", result = tmp_result);
2505
2506         tmp_result = polaris10_init_arb_table_index(hwmgr);
2507         PP_ASSERT_WITH_CODE((0 == tmp_result),
2508                         "Failed to initialize ARB table index!", result = tmp_result);
2509
2510         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2511         PP_ASSERT_WITH_CODE((0 == tmp_result),
2512                         "Failed to populate PM fuses!", result = tmp_result);
2513
2514         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2515         PP_ASSERT_WITH_CODE((0 == tmp_result),
2516                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2517
2518         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2519
2520         tmp_result = polaris10_enable_sclk_control(hwmgr);
2521         PP_ASSERT_WITH_CODE((0 == tmp_result),
2522                         "Failed to enable SCLK control!", result = tmp_result);
2523
2524         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2525         PP_ASSERT_WITH_CODE((0 == tmp_result),
2526                         "Failed to enable voltage control!", result = tmp_result);
2527
2528         tmp_result = polaris10_enable_ulv(hwmgr);
2529         PP_ASSERT_WITH_CODE((0 == tmp_result),
2530                         "Failed to enable ULV!", result = tmp_result);
2531
2532         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2533         PP_ASSERT_WITH_CODE((0 == tmp_result),
2534                         "Failed to enable deep sleep master switch!", result = tmp_result);
2535
2536         tmp_result = polaris10_start_dpm(hwmgr);
2537         PP_ASSERT_WITH_CODE((0 == tmp_result),
2538                         "Failed to start DPM!", result = tmp_result);
2539
2540         tmp_result = polaris10_enable_smc_cac(hwmgr);
2541         PP_ASSERT_WITH_CODE((0 == tmp_result),
2542                         "Failed to enable SMC CAC!", result = tmp_result);
2543
2544         tmp_result = polaris10_enable_power_containment(hwmgr);
2545         PP_ASSERT_WITH_CODE((0 == tmp_result),
2546                         "Failed to enable power containment!", result = tmp_result);
2547
2548         tmp_result = polaris10_power_control_set_level(hwmgr);
2549         PP_ASSERT_WITH_CODE((0 == tmp_result),
2550                         "Failed to power control set level!", result = tmp_result);
2551
2552         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2553         PP_ASSERT_WITH_CODE((0 == tmp_result),
2554                         "Failed to enable thermal auto throttle!", result = tmp_result);
2555
2556         tmp_result = polaris10_pcie_performance_request(hwmgr);
2557         PP_ASSERT_WITH_CODE((0 == tmp_result),
2558                         "pcie performance request failed!", result = tmp_result);
2559
2560         return result;
2561 }
2562
2563 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2564 {
2565
2566         return 0;
2567 }
2568
2569 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2570 {
2571
2572         return 0;
2573 }
2574
2575 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2576 {
2577         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2578
2579         if (data->soft_pp_table) {
2580                 kfree(data->soft_pp_table);
2581                 data->soft_pp_table = NULL;
2582         }
2583
2584         return phm_hwmgr_backend_fini(hwmgr);
2585 }
2586
2587 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2588 {
2589         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2590
2591         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2592                         PHM_PlatformCaps_SclkDeepSleep);
2593
2594         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2595                 PHM_PlatformCaps_DynamicPatchPowerState);
2596
2597         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2598                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2599                                 PHM_PlatformCaps_EnableMVDDControl);
2600
2601         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2602                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2603                                 PHM_PlatformCaps_ControlVDDCI);
2604
2605         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2606                          PHM_PlatformCaps_TablelessHardwareInterface);
2607
2608         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2609                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2610
2611         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2612                         PHM_PlatformCaps_DynamicPowerManagement);
2613
2614         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2615                         PHM_PlatformCaps_UnTabledHardwareInterface);
2616
2617         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2618                         PHM_PlatformCaps_TablelessHardwareInterface);
2619
2620         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2621                                         PHM_PlatformCaps_SMC);
2622
2623         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2624                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2625
2626         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2627                                         PHM_PlatformCaps_DynamicUVDState);
2628
2629         /* power tune caps Assume disabled */
2630         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2631                                                 PHM_PlatformCaps_SQRamping);
2632         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2633                                                 PHM_PlatformCaps_DBRamping);
2634         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2635                                                 PHM_PlatformCaps_TDRamping);
2636         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2637                                                 PHM_PlatformCaps_TCPRamping);
2638
2639         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2640                                         PHM_PlatformCaps_PowerContainment);
2641         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2642                                                         PHM_PlatformCaps_CAC);
2643
2644         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2645                                                 PHM_PlatformCaps_RegulatorHot);
2646
2647         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2648                                                 PHM_PlatformCaps_AutomaticDCTransition);
2649
2650         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2651                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2652
2653         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2654                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2655
2656         if (hwmgr->chip_id == CHIP_POLARIS11)
2657                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2658                                         PHM_PlatformCaps_SPLLShutdownSupport);
2659         return 0;
2660 }
2661
2662 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2663 {
2664         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2665
2666         polaris10_initialize_power_tune_defaults(hwmgr);
2667
2668         data->pcie_gen_performance.max = PP_PCIEGen1;
2669         data->pcie_gen_performance.min = PP_PCIEGen3;
2670         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2671         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2672         data->pcie_lane_performance.max = 0;
2673         data->pcie_lane_performance.min = 16;
2674         data->pcie_lane_power_saving.max = 0;
2675         data->pcie_lane_power_saving.min = 16;
2676 }
2677
2678 /**
2679 * Get Leakage VDDC based on leakage ID.
2680 *
2681 * @param    hwmgr  the address of the powerplay hardware manager.
2682 * @return   always 0
2683 */
2684 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2685 {
2686         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2687         uint16_t vv_id;
2688         uint16_t vddc = 0;
2689         uint16_t i, j;
2690         uint32_t sclk = 0;
2691         struct phm_ppt_v1_information *table_info =
2692                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2693         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2694                         table_info->vdd_dep_on_sclk;
2695         int result;
2696
2697         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2698                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2699                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2700                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2701                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2702                                         PHM_PlatformCaps_ClockStretcher)) {
2703                                 for (j = 1; j < sclk_table->count; j++) {
2704                                         if (sclk_table->entries[j].clk == sclk &&
2705                                                         sclk_table->entries[j].cks_enable == 0) {
2706                                                 sclk += 5000;
2707                                                 break;
2708                                         }
2709                                 }
2710                         }
2711
2712
2713                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2714                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2715                                                 "Error retrieving EVV voltage value!",
2716                                                 continue);
2717
2718
2719                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2720                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2721                                         "Invalid VDDC value", result = -EINVAL;);
2722
2723                         /* the voltage should not be zero nor equal to leakage ID */
2724                         if (vddc != 0 && vddc != vv_id) {
2725                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2726                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2727                                 data->vddc_leakage.count++;
2728                         }
2729                 }
2730         }
2731
2732         return 0;
2733 }
2734
2735 /**
2736  * Change virtual leakage voltage to actual value.
2737  *
2738  * @param     hwmgr  the address of the powerplay hardware manager.
2739  * @param     pointer to changing voltage
2740  * @param     pointer to leakage table
2741  */
2742 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2743                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2744 {
2745         uint32_t index;
2746
2747         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2748         for (index = 0; index < leakage_table->count; index++) {
2749                 /* if this voltage matches a leakage voltage ID */
2750                 /* patch with actual leakage voltage */
2751                 if (leakage_table->leakage_id[index] == *voltage) {
2752                         *voltage = leakage_table->actual_voltage[index];
2753                         break;
2754                 }
2755         }
2756
2757         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2758                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2759 }
2760
2761 /**
2762 * Patch voltage lookup table by EVV leakages.
2763 *
2764 * @param     hwmgr  the address of the powerplay hardware manager.
2765 * @param     pointer to voltage lookup table
2766 * @param     pointer to leakage table
2767 * @return     always 0
2768 */
2769 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2770                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2771                 struct polaris10_leakage_voltage *leakage_table)
2772 {
2773         uint32_t i;
2774
2775         for (i = 0; i < lookup_table->count; i++)
2776                 polaris10_patch_with_vdd_leakage(hwmgr,
2777                                 &lookup_table->entries[i].us_vdd, leakage_table);
2778
2779         return 0;
2780 }
2781
2782 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2783                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2784                 uint16_t *vddc)
2785 {
2786         struct phm_ppt_v1_information *table_info =
2787                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2788         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2789         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2790                         table_info->max_clock_voltage_on_dc.vddc;
2791         return 0;
2792 }
2793
2794 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2795                 struct pp_hwmgr *hwmgr)
2796 {
2797         uint8_t entryId;
2798         uint8_t voltageId;
2799         struct phm_ppt_v1_information *table_info =
2800                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2801
2802         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2803                         table_info->vdd_dep_on_sclk;
2804         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2805                         table_info->vdd_dep_on_mclk;
2806         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2807                         table_info->mm_dep_table;
2808
2809         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2810                 voltageId = sclk_table->entries[entryId].vddInd;
2811                 sclk_table->entries[entryId].vddc =
2812                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2813         }
2814
2815         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2816                 voltageId = mclk_table->entries[entryId].vddInd;
2817                 mclk_table->entries[entryId].vddc =
2818                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2819         }
2820
2821         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2822                 voltageId = mm_table->entries[entryId].vddcInd;
2823                 mm_table->entries[entryId].vddc =
2824                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2825         }
2826
2827         return 0;
2828
2829 }
2830
2831 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2832 {
2833         /* Need to determine if we need calculated voltage. */
2834         return 0;
2835 }
2836
2837 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2838 {
2839         /* Need to determine if we need calculated voltage from mm table. */
2840         return 0;
2841 }
2842
2843 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2844                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2845 {
2846         uint32_t table_size, i, j;
2847         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2848         table_size = lookup_table->count;
2849
2850         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2851                 "Lookup table is empty", return -EINVAL);
2852
2853         /* Sorting voltages */
2854         for (i = 0; i < table_size - 1; i++) {
2855                 for (j = i + 1; j > 0; j--) {
2856                         if (lookup_table->entries[j].us_vdd <
2857                                         lookup_table->entries[j - 1].us_vdd) {
2858                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2859                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2860                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2861                         }
2862                 }
2863         }
2864
2865         return 0;
2866 }
2867
2868 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2869 {
2870         int result = 0;
2871         int tmp_result;
2872         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2873         struct phm_ppt_v1_information *table_info =
2874                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2875
2876         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2877                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2878         if (tmp_result)
2879                 result = tmp_result;
2880
2881         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2882                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2883         if (tmp_result)
2884                 result = tmp_result;
2885
2886         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2887         if (tmp_result)
2888                 result = tmp_result;
2889
2890         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2891         if (tmp_result)
2892                 result = tmp_result;
2893
2894         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2895         if (tmp_result)
2896                 result = tmp_result;
2897
2898         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2899         if (tmp_result)
2900                 result = tmp_result;
2901
2902         return result;
2903 }
2904
2905 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2906 {
2907         struct phm_ppt_v1_information *table_info =
2908                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2909
2910         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2911                                                 table_info->vdd_dep_on_sclk;
2912         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2913                                                 table_info->vdd_dep_on_mclk;
2914
2915         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2916                 "VDD dependency on SCLK table is missing.       \
2917                 This table is mandatory", return -EINVAL);
2918         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2919                 "VDD dependency on SCLK table has to have is missing.   \
2920                 This table is mandatory", return -EINVAL);
2921
2922         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2923                 "VDD dependency on MCLK table is missing.       \
2924                 This table is mandatory", return -EINVAL);
2925         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2926                 "VDD dependency on MCLK table has to have is missing.    \
2927                 This table is mandatory", return -EINVAL);
2928
2929         table_info->max_clock_voltage_on_ac.sclk =
2930                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2931         table_info->max_clock_voltage_on_ac.mclk =
2932                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2933         table_info->max_clock_voltage_on_ac.vddc =
2934                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2935         table_info->max_clock_voltage_on_ac.vddci =
2936                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2937
2938         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2939         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2940         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2941         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2942
2943         return 0;
2944 }
2945
2946 int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2947 {
2948         struct phm_ppt_v1_information *table_info =
2949                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2950         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
2951                         table_info->vdd_dep_on_mclk;
2952         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
2953                         table_info->vddc_lookup_table;
2954         uint32_t i;
2955
2956         if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
2957                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2958                         return 0;
2959
2960                 for (i = 0; i < lookup_table->count; i++) {
2961                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2962                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2963                                 return 0;
2964                         }
2965                 }
2966         }
2967         return 0;
2968 }
2969
2970
2971 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2972 {
2973         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2974         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2975         uint32_t temp_reg;
2976         int result;
2977         struct phm_ppt_v1_information *table_info =
2978                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2979
2980         data->dll_default_on = false;
2981         data->sram_end = SMC_RAM_END;
2982         data->mclk_dpm0_activity_target = 0xa;
2983         data->disable_dpm_mask = 0xFF;
2984         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2985         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2986         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2987         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2988         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2989         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2990         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2991         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2992         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2993         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2994
2995         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2996         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2997         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2998         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2999         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3000         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3001         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3002         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3003
3004         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3005
3006         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3007
3008         /* need to set voltage control types before EVV patching */
3009         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3010         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3011         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3012
3013         data->enable_tdc_limit_feature = true;
3014         data->enable_pkg_pwr_tracking_feature = true;
3015         data->force_pcie_gen = PP_PCIEGenInvalid;
3016         data->mclk_stutter_mode_threshold = 40000;
3017
3018         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3019                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3020                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3021
3022         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3023                         PHM_PlatformCaps_EnableMVDDControl)) {
3024                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3025                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3026                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3027                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3028                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3029                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3030         }
3031
3032         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3033                         PHM_PlatformCaps_ControlVDDCI)) {
3034                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3035                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3036                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3037                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3038                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3039                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3040         }
3041
3042         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3043                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3044                                         PHM_PlatformCaps_ClockStretcher);
3045
3046         polaris10_set_features_platform_caps(hwmgr);
3047
3048         polaris10_patch_voltage_workaround(hwmgr);
3049         polaris10_init_dpm_defaults(hwmgr);
3050
3051         /* Get leakage voltage based on leakage ID. */
3052         result = polaris10_get_evv_voltages(hwmgr);
3053
3054         if (result) {
3055                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3056                 return -1;
3057         }
3058
3059         polaris10_complete_dependency_tables(hwmgr);
3060         polaris10_set_private_data_based_on_pptable(hwmgr);
3061
3062         /* Initalize Dynamic State Adjustment Rule Settings */
3063         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3064
3065         if (0 == result) {
3066                 struct cgs_system_info sys_info = {0};
3067
3068                 data->is_tlu_enabled = 0;
3069
3070                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3071                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3072                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3073                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3074
3075
3076                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3077                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3078                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3079                         case 0:
3080                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3081                                 break;
3082                         case 1:
3083                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3084                                 break;
3085                         case 2:
3086                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3087                                 break;
3088                         case 3:
3089                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3090                                 break;
3091                         case 4:
3092                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3093                                 break;
3094                         default:
3095                                 PP_ASSERT_WITH_CODE(0,
3096                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3097                                 );
3098                                 break;
3099                         }
3100                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3101                 }
3102
3103                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3104                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3105                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3106                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3107
3108                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3109                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3110
3111                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3112
3113                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3114
3115                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3116                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3117
3118                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3119
3120                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3121                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3122
3123                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3124                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3125                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3126
3127                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3128                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3129
3130                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3131                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3132
3133                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3134                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3135
3136                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3137                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3138
3139                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3140                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3141
3142                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3143                                        table_info->cac_dtp_table->usOperatingTempStep;
3144
3145                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3146                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3147                 }
3148
3149                 sys_info.size = sizeof(struct cgs_system_info);
3150                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3151                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3152                 if (result)
3153                         data->pcie_gen_cap = 0x30007;
3154                 else
3155                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3156                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3157                         data->pcie_spc_cap = 20;
3158                 sys_info.size = sizeof(struct cgs_system_info);
3159                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3160                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3161                 if (result)
3162                         data->pcie_lane_cap = 0x2f0000;
3163                 else
3164                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3165
3166                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3167 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3168                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3169                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3170         } else {
3171                 /* Ignore return value in here, we are cleaning up a mess. */
3172                 polaris10_hwmgr_backend_fini(hwmgr);
3173         }
3174
3175         return 0;
3176 }
3177
3178 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3179 {
3180         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3181         uint32_t level, tmp;
3182
3183         if (!data->pcie_dpm_key_disabled) {
3184                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3185                         level = 0;
3186                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3187                         while (tmp >>= 1)
3188                                 level++;
3189
3190                         if (level)
3191                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3192                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3193                 }
3194         }
3195
3196         if (!data->sclk_dpm_key_disabled) {
3197                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3198                         level = 0;
3199                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3200                         while (tmp >>= 1)
3201                                 level++;
3202
3203                         if (level)
3204                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3205                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3206                                                 (1 << level));
3207                 }
3208         }
3209
3210         if (!data->mclk_dpm_key_disabled) {
3211                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3212                         level = 0;
3213                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3214                         while (tmp >>= 1)
3215                                 level++;
3216
3217                         if (level)
3218                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3219                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3220                                                 (1 << level));
3221                 }
3222         }
3223
3224         return 0;
3225 }
3226
3227 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3228 {
3229         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3230
3231         phm_apply_dal_min_voltage_request(hwmgr);
3232
3233         if (!data->sclk_dpm_key_disabled) {
3234                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3235                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3236                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3237                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3238         }
3239
3240         if (!data->mclk_dpm_key_disabled) {
3241                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3242                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3243                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3244                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3245         }
3246
3247         return 0;
3248 }
3249
3250 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3251 {
3252         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3253
3254         if (!polaris10_is_dpm_running(hwmgr))
3255                 return -EINVAL;
3256
3257         if (!data->pcie_dpm_key_disabled) {
3258                 smum_send_msg_to_smc(hwmgr->smumgr,
3259                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3260         }
3261
3262         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3263 }
3264
3265 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3266 {
3267         struct polaris10_hwmgr *data =
3268                         (struct polaris10_hwmgr *)(hwmgr->backend);
3269         uint32_t level;
3270
3271         if (!data->sclk_dpm_key_disabled)
3272                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3273                         level = phm_get_lowest_enabled_level(hwmgr,
3274                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3275                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3276                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3277                                                             (1 << level));
3278
3279         }
3280
3281         if (!data->mclk_dpm_key_disabled) {
3282                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3283                         level = phm_get_lowest_enabled_level(hwmgr,
3284                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3285                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3286                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3287                                                             (1 << level));
3288                 }
3289         }
3290
3291         if (!data->pcie_dpm_key_disabled) {
3292                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3293                         level = phm_get_lowest_enabled_level(hwmgr,
3294                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3295                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3296                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3297                                                             (level));
3298                 }
3299         }
3300
3301         return 0;
3302
3303 }
3304 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3305                                 enum amd_dpm_forced_level level)
3306 {
3307         int ret = 0;
3308
3309         switch (level) {
3310         case AMD_DPM_FORCED_LEVEL_HIGH:
3311                 ret = polaris10_force_dpm_highest(hwmgr);
3312                 if (ret)
3313                         return ret;
3314                 break;
3315         case AMD_DPM_FORCED_LEVEL_LOW:
3316                 ret = polaris10_force_dpm_lowest(hwmgr);
3317                 if (ret)
3318                         return ret;
3319                 break;
3320         case AMD_DPM_FORCED_LEVEL_AUTO:
3321                 ret = polaris10_unforce_dpm_levels(hwmgr);
3322                 if (ret)
3323                         return ret;
3324                 break;
3325         default:
3326                 break;
3327         }
3328
3329         hwmgr->dpm_level = level;
3330
3331         return ret;
3332 }
3333
3334 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3335 {
3336         return sizeof(struct polaris10_power_state);
3337 }
3338
3339
3340 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3341                                 struct pp_power_state *request_ps,
3342                         const struct pp_power_state *current_ps)
3343 {
3344
3345         struct polaris10_power_state *polaris10_ps =
3346                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3347         uint32_t sclk;
3348         uint32_t mclk;
3349         struct PP_Clocks minimum_clocks = {0};
3350         bool disable_mclk_switching;
3351         bool disable_mclk_switching_for_frame_lock;
3352         struct cgs_display_info info = {0};
3353         const struct phm_clock_and_voltage_limits *max_limits;
3354         uint32_t i;
3355         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3356         struct phm_ppt_v1_information *table_info =
3357                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3358         int32_t count;
3359         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3360
3361         data->battery_state = (PP_StateUILabel_Battery ==
3362                         request_ps->classification.ui_label);
3363
3364         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3365                                  "VI should always have 2 performance levels",
3366                                 );
3367
3368         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3369                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3370                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3371
3372         /* Cap clock DPM tables at DC MAX if it is in DC. */
3373         if (PP_PowerSource_DC == hwmgr->power_source) {
3374                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3375                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3376                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3377                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3378                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3379                 }
3380         }
3381
3382         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3383         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3384
3385         cgs_get_active_displays_info(hwmgr->device, &info);
3386
3387         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3388
3389         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3390
3391         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3392                         PHM_PlatformCaps_StablePState)) {
3393                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3394                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3395
3396                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3397                                 count >= 0; count--) {
3398                         if (stable_pstate_sclk >=
3399                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3400                                 stable_pstate_sclk =
3401                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3402                                 break;
3403                         }
3404                 }
3405
3406                 if (count < 0)
3407                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3408
3409                 stable_pstate_mclk = max_limits->mclk;
3410
3411                 minimum_clocks.engineClock = stable_pstate_sclk;
3412                 minimum_clocks.memoryClock = stable_pstate_mclk;
3413         }
3414
3415         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3416                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3417
3418         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3419                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3420
3421         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3422
3423         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3424                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3425                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3426                                 "Overdrive sclk exceeds limit",
3427                                 hwmgr->gfx_arbiter.sclk_over_drive =
3428                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3429
3430                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3431                         polaris10_ps->performance_levels[1].engine_clock =
3432                                         hwmgr->gfx_arbiter.sclk_over_drive;
3433         }
3434
3435         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3436                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3437                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3438                                 "Overdrive mclk exceeds limit",
3439                                 hwmgr->gfx_arbiter.mclk_over_drive =
3440                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3441
3442                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3443                         polaris10_ps->performance_levels[1].memory_clock =
3444                                         hwmgr->gfx_arbiter.mclk_over_drive;
3445         }
3446
3447         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3448                                     hwmgr->platform_descriptor.platformCaps,
3449                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3450
3451         disable_mclk_switching = (1 < info.display_count) ||
3452                                     disable_mclk_switching_for_frame_lock;
3453
3454         sclk = polaris10_ps->performance_levels[0].engine_clock;
3455         mclk = polaris10_ps->performance_levels[0].memory_clock;
3456
3457         if (disable_mclk_switching)
3458                 mclk = polaris10_ps->performance_levels
3459                 [polaris10_ps->performance_level_count - 1].memory_clock;
3460
3461         if (sclk < minimum_clocks.engineClock)
3462                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3463                                 max_limits->sclk : minimum_clocks.engineClock;
3464
3465         if (mclk < minimum_clocks.memoryClock)
3466                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3467                                 max_limits->mclk : minimum_clocks.memoryClock;
3468
3469         polaris10_ps->performance_levels[0].engine_clock = sclk;
3470         polaris10_ps->performance_levels[0].memory_clock = mclk;
3471
3472         polaris10_ps->performance_levels[1].engine_clock =
3473                 (polaris10_ps->performance_levels[1].engine_clock >=
3474                                 polaris10_ps->performance_levels[0].engine_clock) ?
3475                                                 polaris10_ps->performance_levels[1].engine_clock :
3476                                                 polaris10_ps->performance_levels[0].engine_clock;
3477
3478         if (disable_mclk_switching) {
3479                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3480                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3481
3482                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3483                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3484         } else {
3485                 if (polaris10_ps->performance_levels[1].memory_clock <
3486                                 polaris10_ps->performance_levels[0].memory_clock)
3487                         polaris10_ps->performance_levels[1].memory_clock =
3488                                         polaris10_ps->performance_levels[0].memory_clock;
3489         }
3490
3491         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3492                         PHM_PlatformCaps_StablePState)) {
3493                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3494                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3495                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3496                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3497                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3498                 }
3499         }
3500         return 0;
3501 }
3502
3503
3504 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3505 {
3506         struct pp_power_state  *ps;
3507         struct polaris10_power_state  *polaris10_ps;
3508
3509         if (hwmgr == NULL)
3510                 return -EINVAL;
3511
3512         ps = hwmgr->request_ps;
3513
3514         if (ps == NULL)
3515                 return -EINVAL;
3516
3517         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3518
3519         if (low)
3520                 return polaris10_ps->performance_levels[0].memory_clock;
3521         else
3522                 return polaris10_ps->performance_levels
3523                                 [polaris10_ps->performance_level_count-1].memory_clock;
3524 }
3525
3526 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3527 {
3528         struct pp_power_state  *ps;
3529         struct polaris10_power_state  *polaris10_ps;
3530
3531         if (hwmgr == NULL)
3532                 return -EINVAL;
3533
3534         ps = hwmgr->request_ps;
3535
3536         if (ps == NULL)
3537                 return -EINVAL;
3538
3539         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3540
3541         if (low)
3542                 return polaris10_ps->performance_levels[0].engine_clock;
3543         else
3544                 return polaris10_ps->performance_levels
3545                                 [polaris10_ps->performance_level_count-1].engine_clock;
3546 }
3547
3548 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3549                                         struct pp_hw_power_state *hw_ps)
3550 {
3551         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3552         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3553         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3554         uint16_t size;
3555         uint8_t frev, crev;
3556         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3557
3558         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3559          * We assume here that fw_info is unchanged if this call fails.
3560          */
3561         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3562                         hwmgr->device, index,
3563                         &size, &frev, &crev);
3564         if (!fw_info)
3565                 /* During a test, there is no firmware info table. */
3566                 return 0;
3567
3568         /* Patch the state. */
3569         data->vbios_boot_state.sclk_bootup_value =
3570                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3571         data->vbios_boot_state.mclk_bootup_value =
3572                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3573         data->vbios_boot_state.mvdd_bootup_value =
3574                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3575         data->vbios_boot_state.vddc_bootup_value =
3576                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3577         data->vbios_boot_state.vddci_bootup_value =
3578                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3579         data->vbios_boot_state.pcie_gen_bootup_value =
3580                         phm_get_current_pcie_speed(hwmgr);
3581
3582         data->vbios_boot_state.pcie_lane_bootup_value =
3583                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3584
3585         /* set boot power state */
3586         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3587         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3588         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3589         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3590
3591         return 0;
3592 }
3593
3594 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3595                 void *state, struct pp_power_state *power_state,
3596                 void *pp_table, uint32_t classification_flag)
3597 {
3598         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3599         struct polaris10_power_state  *polaris10_power_state =
3600                         (struct polaris10_power_state *)(&(power_state->hardware));
3601         struct polaris10_performance_level *performance_level;
3602         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3603         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3604                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3605         PPTable_Generic_SubTable_Header *sclk_dep_table =
3606                         (PPTable_Generic_SubTable_Header *)
3607                         (((unsigned long)powerplay_table) +
3608                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3609
3610         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3611                         (ATOM_Tonga_MCLK_Dependency_Table *)
3612                         (((unsigned long)powerplay_table) +
3613                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3614
3615         /* The following fields are not initialized here: id orderedList allStatesList */
3616         power_state->classification.ui_label =
3617                         (le16_to_cpu(state_entry->usClassification) &
3618                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3619                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3620         power_state->classification.flags = classification_flag;
3621         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3622
3623         power_state->classification.temporary_state = false;
3624         power_state->classification.to_be_deleted = false;
3625
3626         power_state->validation.disallowOnDC =
3627                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3628                                         ATOM_Tonga_DISALLOW_ON_DC));
3629
3630         power_state->pcie.lanes = 0;
3631
3632         power_state->display.disableFrameModulation = false;
3633         power_state->display.limitRefreshrate = false;
3634         power_state->display.enableVariBright =
3635                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3636                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3637
3638         power_state->validation.supportedPowerLevels = 0;
3639         power_state->uvd_clocks.VCLK = 0;
3640         power_state->uvd_clocks.DCLK = 0;
3641         power_state->temperatures.min = 0;
3642         power_state->temperatures.max = 0;
3643
3644         performance_level = &(polaris10_power_state->performance_levels
3645                         [polaris10_power_state->performance_level_count++]);
3646
3647         PP_ASSERT_WITH_CODE(
3648                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3649                         "Performance levels exceeds SMC limit!",
3650                         return -1);
3651
3652         PP_ASSERT_WITH_CODE(
3653                         (polaris10_power_state->performance_level_count <=
3654                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3655                         "Performance levels exceeds Driver limit!",
3656                         return -1);
3657
3658         /* Performance levels are arranged from low to high. */
3659         performance_level->memory_clock = mclk_dep_table->entries
3660                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3661         if (sclk_dep_table->ucRevId == 0)
3662                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3663                         [state_entry->ucEngineClockIndexLow].ulSclk;
3664         else if (sclk_dep_table->ucRevId == 1)
3665                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3666                         [state_entry->ucEngineClockIndexLow].ulSclk;
3667         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3668                         state_entry->ucPCIEGenLow);
3669         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3670                         state_entry->ucPCIELaneHigh);
3671
3672         performance_level = &(polaris10_power_state->performance_levels
3673                         [polaris10_power_state->performance_level_count++]);
3674         performance_level->memory_clock = mclk_dep_table->entries
3675                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3676
3677         if (sclk_dep_table->ucRevId == 0)
3678                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3679                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3680         else if (sclk_dep_table->ucRevId == 1)
3681                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3682                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3683
3684         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3685                         state_entry->ucPCIEGenHigh);
3686         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3687                         state_entry->ucPCIELaneHigh);
3688
3689         return 0;
3690 }
3691
3692 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3693                 unsigned long entry_index, struct pp_power_state *state)
3694 {
3695         int result;
3696         struct polaris10_power_state *ps;
3697         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3698         struct phm_ppt_v1_information *table_info =
3699                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3700         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3701                         table_info->vdd_dep_on_mclk;
3702
3703         state->hardware.magic = PHM_VIslands_Magic;
3704
3705         ps = (struct polaris10_power_state *)(&state->hardware);
3706
3707         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3708                         polaris10_get_pp_table_entry_callback_func);
3709
3710         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3711          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3712          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3713          */
3714         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3715                 if (dep_mclk_table->entries[0].clk !=
3716                                 data->vbios_boot_state.mclk_bootup_value)
3717                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3718                                         "does not match VBIOS boot MCLK level");
3719                 if (dep_mclk_table->entries[0].vddci !=
3720                                 data->vbios_boot_state.vddci_bootup_value)
3721                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3722                                         "does not match VBIOS boot VDDCI level");
3723         }
3724
3725         /* set DC compatible flag if this state supports DC */
3726         if (!state->validation.disallowOnDC)
3727                 ps->dc_compatible = true;
3728
3729         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3730                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3731
3732         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3733         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3734
3735         if (!result) {
3736                 uint32_t i;
3737
3738                 switch (state->classification.ui_label) {
3739                 case PP_StateUILabel_Performance:
3740                         data->use_pcie_performance_levels = true;
3741                         for (i = 0; i < ps->performance_level_count; i++) {
3742                                 if (data->pcie_gen_performance.max <
3743                                                 ps->performance_levels[i].pcie_gen)
3744                                         data->pcie_gen_performance.max =
3745                                                         ps->performance_levels[i].pcie_gen;
3746
3747                                 if (data->pcie_gen_performance.min >
3748                                                 ps->performance_levels[i].pcie_gen)
3749                                         data->pcie_gen_performance.min =
3750                                                         ps->performance_levels[i].pcie_gen;
3751
3752                                 if (data->pcie_lane_performance.max <
3753                                                 ps->performance_levels[i].pcie_lane)
3754                                         data->pcie_lane_performance.max =
3755                                                         ps->performance_levels[i].pcie_lane;
3756                                 if (data->pcie_lane_performance.min >
3757                                                 ps->performance_levels[i].pcie_lane)
3758                                         data->pcie_lane_performance.min =
3759                                                         ps->performance_levels[i].pcie_lane;
3760                         }
3761                         break;
3762                 case PP_StateUILabel_Battery:
3763                         data->use_pcie_power_saving_levels = true;
3764
3765                         for (i = 0; i < ps->performance_level_count; i++) {
3766                                 if (data->pcie_gen_power_saving.max <
3767                                                 ps->performance_levels[i].pcie_gen)
3768                                         data->pcie_gen_power_saving.max =
3769                                                         ps->performance_levels[i].pcie_gen;
3770
3771                                 if (data->pcie_gen_power_saving.min >
3772                                                 ps->performance_levels[i].pcie_gen)
3773                                         data->pcie_gen_power_saving.min =
3774                                                         ps->performance_levels[i].pcie_gen;
3775
3776                                 if (data->pcie_lane_power_saving.max <
3777                                                 ps->performance_levels[i].pcie_lane)
3778                                         data->pcie_lane_power_saving.max =
3779                                                         ps->performance_levels[i].pcie_lane;
3780
3781                                 if (data->pcie_lane_power_saving.min >
3782                                                 ps->performance_levels[i].pcie_lane)
3783                                         data->pcie_lane_power_saving.min =
3784                                                         ps->performance_levels[i].pcie_lane;
3785                         }
3786                         break;
3787                 default:
3788                         break;
3789                 }
3790         }
3791         return 0;
3792 }
3793
3794 static void
3795 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3796 {
3797         uint32_t sclk, mclk, activity_percent;
3798         uint32_t offset;
3799         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3800
3801         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3802
3803         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3804
3805         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3806
3807         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3808         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3809                         mclk / 100, sclk / 100);
3810
3811         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3812         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3813         activity_percent += 0x80;
3814         activity_percent >>= 8;
3815
3816         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3817
3818         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3819
3820         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3821 }
3822
3823 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3824 {
3825         const struct phm_set_power_state_input *states =
3826                         (const struct phm_set_power_state_input *)input;
3827         const struct polaris10_power_state *polaris10_ps =
3828                         cast_const_phw_polaris10_power_state(states->pnew_state);
3829         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3830         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3831         uint32_t sclk = polaris10_ps->performance_levels
3832                         [polaris10_ps->performance_level_count - 1].engine_clock;
3833         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3834         uint32_t mclk = polaris10_ps->performance_levels
3835                         [polaris10_ps->performance_level_count - 1].memory_clock;
3836         struct PP_Clocks min_clocks = {0};
3837         uint32_t i;
3838         struct cgs_display_info info = {0};
3839
3840         data->need_update_smu7_dpm_table = 0;
3841
3842         for (i = 0; i < sclk_table->count; i++) {
3843                 if (sclk == sclk_table->dpm_levels[i].value)
3844                         break;
3845         }
3846
3847         if (i >= sclk_table->count)
3848                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3849         else {
3850         /* TODO: Check SCLK in DAL's minimum clocks
3851          * in case DeepSleep divider update is required.
3852          */
3853                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3854                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3855                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3856                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3857         }
3858
3859         for (i = 0; i < mclk_table->count; i++) {
3860                 if (mclk == mclk_table->dpm_levels[i].value)
3861                         break;
3862         }
3863
3864         if (i >= mclk_table->count)
3865                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3866
3867         cgs_get_active_displays_info(hwmgr->device, &info);
3868
3869         if (data->display_timing.num_existing_displays != info.display_count)
3870                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3871
3872         return 0;
3873 }
3874
3875 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3876                 const struct polaris10_power_state *polaris10_ps)
3877 {
3878         uint32_t i;
3879         uint32_t sclk, max_sclk = 0;
3880         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3881         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3882
3883         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3884                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3885                 if (max_sclk < sclk)
3886                         max_sclk = sclk;
3887         }
3888
3889         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3890                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3891                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3892                                         dpm_table->pcie_speed_table.dpm_levels
3893                                         [dpm_table->pcie_speed_table.count - 1].value :
3894                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3895         }
3896
3897         return 0;
3898 }
3899
3900 static int polaris10_request_link_speed_change_before_state_change(
3901                 struct pp_hwmgr *hwmgr, const void *input)
3902 {
3903         const struct phm_set_power_state_input *states =
3904                         (const struct phm_set_power_state_input *)input;
3905         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3906         const struct polaris10_power_state *polaris10_nps =
3907                         cast_const_phw_polaris10_power_state(states->pnew_state);
3908         const struct polaris10_power_state *polaris10_cps =
3909                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3910
3911         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3912         uint16_t current_link_speed;
3913
3914         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3915                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3916         else
3917                 current_link_speed = data->force_pcie_gen;
3918
3919         data->force_pcie_gen = PP_PCIEGenInvalid;
3920         data->pspp_notify_required = false;
3921
3922         if (target_link_speed > current_link_speed) {
3923                 switch (target_link_speed) {
3924                 case PP_PCIEGen3:
3925                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3926                                 break;
3927                         data->force_pcie_gen = PP_PCIEGen2;
3928                         if (current_link_speed == PP_PCIEGen2)
3929                                 break;
3930                 case PP_PCIEGen2:
3931                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3932                                 break;
3933                 default:
3934                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3935                         break;
3936                 }
3937         } else {
3938                 if (target_link_speed < current_link_speed)
3939                         data->pspp_notify_required = true;
3940         }
3941
3942         return 0;
3943 }
3944
3945 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3946 {
3947         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3948
3949         if (0 == data->need_update_smu7_dpm_table)
3950                 return 0;
3951
3952         if ((0 == data->sclk_dpm_key_disabled) &&
3953                 (data->need_update_smu7_dpm_table &
3954                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3955                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3956                                 "Trying to freeze SCLK DPM when DPM is disabled",
3957                                 );
3958                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3959                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3960                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3961                                 return -1);
3962         }
3963
3964         if ((0 == data->mclk_dpm_key_disabled) &&
3965                 (data->need_update_smu7_dpm_table &
3966                  DPMTABLE_OD_UPDATE_MCLK)) {
3967                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3968                                 "Trying to freeze MCLK DPM when DPM is disabled",
3969                                 );
3970                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3971                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3972                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3973                                 return -1);
3974         }
3975
3976         return 0;
3977 }
3978
3979 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3980                 struct pp_hwmgr *hwmgr, const void *input)
3981 {
3982         int result = 0;
3983         const struct phm_set_power_state_input *states =
3984                         (const struct phm_set_power_state_input *)input;
3985         const struct polaris10_power_state *polaris10_ps =
3986                         cast_const_phw_polaris10_power_state(states->pnew_state);
3987         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3988         uint32_t sclk = polaris10_ps->performance_levels
3989                         [polaris10_ps->performance_level_count - 1].engine_clock;
3990         uint32_t mclk = polaris10_ps->performance_levels
3991                         [polaris10_ps->performance_level_count - 1].memory_clock;
3992         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3993
3994         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3995         uint32_t dpm_count, clock_percent;
3996         uint32_t i;
3997
3998         if (0 == data->need_update_smu7_dpm_table)
3999                 return 0;
4000
4001         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4002                 dpm_table->sclk_table.dpm_levels
4003                 [dpm_table->sclk_table.count - 1].value = sclk;
4004
4005                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4006                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4007                 /* Need to do calculation based on the golden DPM table
4008                  * as the Heatmap GPU Clock axis is also based on the default values
4009                  */
4010                         PP_ASSERT_WITH_CODE(
4011                                 (golden_dpm_table->sclk_table.dpm_levels
4012                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4013                                 "Divide by 0!",
4014                                 return -1);
4015                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4016
4017                         for (i = dpm_count; i > 1; i--) {
4018                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4019                                         clock_percent =
4020                                               ((sclk
4021                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4022                                                 ) * 100)
4023                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4024
4025                                         dpm_table->sclk_table.dpm_levels[i].value =
4026                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4027                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4028                                                                 clock_percent)/100;
4029
4030                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4031                                         clock_percent =
4032                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4033                                                 - sclk) * 100)
4034                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4035
4036                                         dpm_table->sclk_table.dpm_levels[i].value =
4037                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4038                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4039                                                                         clock_percent) / 100;
4040                                 } else
4041                                         dpm_table->sclk_table.dpm_levels[i].value =
4042                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4043                         }
4044                 }
4045         }
4046
4047         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4048                 dpm_table->mclk_table.dpm_levels
4049                         [dpm_table->mclk_table.count - 1].value = mclk;
4050
4051                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4052                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4053
4054                         PP_ASSERT_WITH_CODE(
4055                                         (golden_dpm_table->mclk_table.dpm_levels
4056                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4057                                         "Divide by 0!",
4058                                         return -1);
4059                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4060                         for (i = dpm_count; i > 1; i--) {
4061                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4062                                         clock_percent = ((mclk -
4063                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4064                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4065
4066                                         dpm_table->mclk_table.dpm_levels[i].value =
4067                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4068                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4069                                                         clock_percent) / 100;
4070
4071                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4072                                         clock_percent = (
4073                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4074                                         * 100)
4075                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4076
4077                                         dpm_table->mclk_table.dpm_levels[i].value =
4078                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4079                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4080                                                                         clock_percent) / 100;
4081                                 } else
4082                                         dpm_table->mclk_table.dpm_levels[i].value =
4083                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4084                         }
4085                 }
4086         }
4087
4088         if (data->need_update_smu7_dpm_table &
4089                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4090                 result = polaris10_populate_all_graphic_levels(hwmgr);
4091                 PP_ASSERT_WITH_CODE((0 == result),
4092                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4093                                 return result);
4094         }
4095
4096         if (data->need_update_smu7_dpm_table &
4097                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4098                 /*populate MCLK dpm table to SMU7 */
4099                 result = polaris10_populate_all_memory_levels(hwmgr);
4100                 PP_ASSERT_WITH_CODE((0 == result),
4101                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4102                                 return result);
4103         }
4104
4105         return result;
4106 }
4107
4108 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4109                           struct polaris10_single_dpm_table *dpm_table,
4110                         uint32_t low_limit, uint32_t high_limit)
4111 {
4112         uint32_t i;
4113
4114         for (i = 0; i < dpm_table->count; i++) {
4115                 if ((dpm_table->dpm_levels[i].value < low_limit)
4116                 || (dpm_table->dpm_levels[i].value > high_limit))
4117                         dpm_table->dpm_levels[i].enabled = false;
4118                 else
4119                         dpm_table->dpm_levels[i].enabled = true;
4120         }
4121
4122         return 0;
4123 }
4124
4125 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4126                 const struct polaris10_power_state *polaris10_ps)
4127 {
4128         int result = 0;
4129         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4130         uint32_t high_limit_count;
4131
4132         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4133                         "power state did not have any performance level",
4134                         return -1);
4135
4136         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4137
4138         polaris10_trim_single_dpm_states(hwmgr,
4139                         &(data->dpm_table.sclk_table),
4140                         polaris10_ps->performance_levels[0].engine_clock,
4141                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4142
4143         polaris10_trim_single_dpm_states(hwmgr,
4144                         &(data->dpm_table.mclk_table),
4145                         polaris10_ps->performance_levels[0].memory_clock,
4146                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4147
4148         return result;
4149 }
4150
4151 static int polaris10_generate_dpm_level_enable_mask(
4152                 struct pp_hwmgr *hwmgr, const void *input)
4153 {
4154         int result;
4155         const struct phm_set_power_state_input *states =
4156                         (const struct phm_set_power_state_input *)input;
4157         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4158         const struct polaris10_power_state *polaris10_ps =
4159                         cast_const_phw_polaris10_power_state(states->pnew_state);
4160
4161         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4162         if (result)
4163                 return result;
4164
4165         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4166                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4167         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4168                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4169         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4170                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4171
4172         return 0;
4173 }
4174
4175 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4176 {
4177         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4178                         PPSMC_MSG_UVDDPM_Enable :
4179                         PPSMC_MSG_UVDDPM_Disable);
4180 }
4181
4182 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4183 {
4184         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4185                         PPSMC_MSG_VCEDPM_Enable :
4186                         PPSMC_MSG_VCEDPM_Disable);
4187 }
4188
4189 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4190 {
4191         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4192                         PPSMC_MSG_SAMUDPM_Enable :
4193                         PPSMC_MSG_SAMUDPM_Disable);
4194 }
4195
4196 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4197 {
4198         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4199         uint32_t mm_boot_level_offset, mm_boot_level_value;
4200         struct phm_ppt_v1_information *table_info =
4201                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4202
4203         if (!bgate) {
4204                 data->smc_state_table.UvdBootLevel = 0;
4205                 if (table_info->mm_dep_table->count > 0)
4206                         data->smc_state_table.UvdBootLevel =
4207                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4208                 mm_boot_level_offset = data->dpm_table_start +
4209                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4210                 mm_boot_level_offset /= 4;
4211                 mm_boot_level_offset *= 4;
4212                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4213                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4214                 mm_boot_level_value &= 0x00FFFFFF;
4215                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4216                 cgs_write_ind_register(hwmgr->device,
4217                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4218
4219                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4220                                 PHM_PlatformCaps_UVDDPM) ||
4221                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4222                                 PHM_PlatformCaps_StablePState))
4223                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4224                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4225                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4226         }
4227
4228         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4229 }
4230
4231 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4232 {
4233         const struct phm_set_power_state_input *states =
4234                         (const struct phm_set_power_state_input *)input;
4235         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4236         const struct polaris10_power_state *polaris10_nps =
4237                         cast_const_phw_polaris10_power_state(states->pnew_state);
4238         const struct polaris10_power_state *polaris10_cps =
4239                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4240
4241         uint32_t mm_boot_level_offset, mm_boot_level_value;
4242         struct phm_ppt_v1_information *table_info =
4243                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4244
4245         if (polaris10_nps->vce_clks.evclk > 0 &&
4246         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4247
4248                 data->smc_state_table.VceBootLevel =
4249                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4250
4251                 mm_boot_level_offset = data->dpm_table_start +
4252                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4253                 mm_boot_level_offset /= 4;
4254                 mm_boot_level_offset *= 4;
4255                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4256                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4257                 mm_boot_level_value &= 0xFF00FFFF;
4258                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4259                 cgs_write_ind_register(hwmgr->device,
4260                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4261
4262                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4263                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4264                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4265                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4266
4267                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4268                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4269                                 polaris10_cps != NULL &&
4270                                 polaris10_cps->vce_clks.evclk > 0)
4271                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4272         }
4273
4274         return 0;
4275 }
4276
4277 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4278 {
4279         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4280         uint32_t mm_boot_level_offset, mm_boot_level_value;
4281
4282         if (!bgate) {
4283                 data->smc_state_table.SamuBootLevel = 0;
4284                 mm_boot_level_offset = data->dpm_table_start +
4285                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4286                 mm_boot_level_offset /= 4;
4287                 mm_boot_level_offset *= 4;
4288                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4289                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4290                 mm_boot_level_value &= 0xFFFFFF00;
4291                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4292                 cgs_write_ind_register(hwmgr->device,
4293                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4294
4295                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4296                                 PHM_PlatformCaps_StablePState))
4297                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4298                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4299                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4300         }
4301
4302         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4303 }
4304
4305 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4306 {
4307         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4308
4309         int result = 0;
4310         uint32_t low_sclk_interrupt_threshold = 0;
4311
4312         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4313                         PHM_PlatformCaps_SclkThrottleLowNotification)
4314                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4315                                 data->low_sclk_interrupt_threshold)) {
4316                 data->low_sclk_interrupt_threshold =
4317                                 hwmgr->gfx_arbiter.sclk_threshold;
4318                 low_sclk_interrupt_threshold =
4319                                 data->low_sclk_interrupt_threshold;
4320
4321                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4322
4323                 result = polaris10_copy_bytes_to_smc(
4324                                 hwmgr->smumgr,
4325                                 data->dpm_table_start +
4326                                 offsetof(SMU74_Discrete_DpmTable,
4327                                         LowSclkInterruptThreshold),
4328                                 (uint8_t *)&low_sclk_interrupt_threshold,
4329                                 sizeof(uint32_t),
4330                                 data->sram_end);
4331         }
4332
4333         return result;
4334 }
4335
4336 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4337 {
4338         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4339
4340         if (data->need_update_smu7_dpm_table &
4341                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4342                 return polaris10_program_memory_timing_parameters(hwmgr);
4343
4344         return 0;
4345 }
4346
4347 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4348 {
4349         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4350
4351         if (0 == data->need_update_smu7_dpm_table)
4352                 return 0;
4353
4354         if ((0 == data->sclk_dpm_key_disabled) &&
4355                 (data->need_update_smu7_dpm_table &
4356                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4357
4358                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4359                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4360                                 );
4361                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4362                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4363                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4364                         return -1);
4365         }
4366
4367         if ((0 == data->mclk_dpm_key_disabled) &&
4368                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4369
4370                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4371                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4372                                 );
4373                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4374                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4375                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4376                     return -1);
4377         }
4378
4379         data->need_update_smu7_dpm_table = 0;
4380
4381         return 0;
4382 }
4383
4384 static int polaris10_notify_link_speed_change_after_state_change(
4385                 struct pp_hwmgr *hwmgr, const void *input)
4386 {
4387         const struct phm_set_power_state_input *states =
4388                         (const struct phm_set_power_state_input *)input;
4389         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4390         const struct polaris10_power_state *polaris10_ps =
4391                         cast_const_phw_polaris10_power_state(states->pnew_state);
4392         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4393         uint8_t  request;
4394
4395         if (data->pspp_notify_required) {
4396                 if (target_link_speed == PP_PCIEGen3)
4397                         request = PCIE_PERF_REQ_GEN3;
4398                 else if (target_link_speed == PP_PCIEGen2)
4399                         request = PCIE_PERF_REQ_GEN2;
4400                 else
4401                         request = PCIE_PERF_REQ_GEN1;
4402
4403                 if (request == PCIE_PERF_REQ_GEN1 &&
4404                                 phm_get_current_pcie_speed(hwmgr) > 0)
4405                         return 0;
4406
4407                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4408                         if (PP_PCIEGen2 == target_link_speed)
4409                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4410                         else
4411                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4412                 }
4413         }
4414
4415         return 0;
4416 }
4417
4418 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4419 {
4420         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4421
4422         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4423                 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4424         return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
4425 }
4426
4427 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4428 {
4429         int tmp_result, result = 0;
4430         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4431
4432         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4433         PP_ASSERT_WITH_CODE((0 == tmp_result),
4434                         "Failed to find DPM states clocks in DPM table!",
4435                         result = tmp_result);
4436
4437         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4438                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4439                 tmp_result =
4440                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4441                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4442                                 "Failed to request link speed change before state change!",
4443                                 result = tmp_result);
4444         }
4445
4446         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4447         PP_ASSERT_WITH_CODE((0 == tmp_result),
4448                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4449
4450         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4451         PP_ASSERT_WITH_CODE((0 == tmp_result),
4452                         "Failed to populate and upload SCLK MCLK DPM levels!",
4453                         result = tmp_result);
4454
4455         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4456         PP_ASSERT_WITH_CODE((0 == tmp_result),
4457                         "Failed to generate DPM level enabled mask!",
4458                         result = tmp_result);
4459
4460         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4461         PP_ASSERT_WITH_CODE((0 == tmp_result),
4462                         "Failed to update VCE DPM!",
4463                         result = tmp_result);
4464
4465         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4466         PP_ASSERT_WITH_CODE((0 == tmp_result),
4467                         "Failed to update SCLK threshold!",
4468                         result = tmp_result);
4469
4470         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4471         PP_ASSERT_WITH_CODE((0 == tmp_result),
4472                         "Failed to program memory timing parameters!",
4473                         result = tmp_result);
4474
4475         tmp_result = polaris10_notify_smc_display(hwmgr);
4476         PP_ASSERT_WITH_CODE((0 == tmp_result),
4477                         "Failed to notify smc display settings!",
4478                         result = tmp_result);
4479
4480         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4481         PP_ASSERT_WITH_CODE((0 == tmp_result),
4482                         "Failed to unfreeze SCLK MCLK DPM!",
4483                         result = tmp_result);
4484
4485         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4486         PP_ASSERT_WITH_CODE((0 == tmp_result),
4487                         "Failed to upload DPM level enabled mask!",
4488                         result = tmp_result);
4489
4490         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4491                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4492                 tmp_result =
4493                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4494                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4495                                 "Failed to notify link speed change after state change!",
4496                                 result = tmp_result);
4497         }
4498         data->apply_optimized_settings = false;
4499         return result;
4500 }
4501
4502 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4503 {
4504         hwmgr->thermal_controller.
4505         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4506
4507         if (phm_is_hw_access_blocked(hwmgr))
4508                 return 0;
4509
4510         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4511                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4512 }
4513
4514
4515 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4516 {
4517         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4518
4519         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4520 }
4521
4522 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4523 {
4524         uint32_t num_active_displays = 0;
4525         struct cgs_display_info info = {0};
4526         info.mode_info = NULL;
4527
4528         cgs_get_active_displays_info(hwmgr->device, &info);
4529
4530         num_active_displays = info.display_count;
4531
4532         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4533                 polaris10_notify_smc_display_change(hwmgr, false);
4534
4535         return 0;
4536 }
4537
4538 /**
4539 * Programs the display gap
4540 *
4541 * @param    hwmgr  the address of the powerplay hardware manager.
4542 * @return   always OK
4543 */
4544 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4545 {
4546         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4547         uint32_t num_active_displays = 0;
4548         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4549         uint32_t display_gap2;
4550         uint32_t pre_vbi_time_in_us;
4551         uint32_t frame_time_in_us;
4552         uint32_t ref_clock;
4553         uint32_t refresh_rate = 0;
4554         struct cgs_display_info info = {0};
4555         struct cgs_mode_info mode_info;
4556
4557         info.mode_info = &mode_info;
4558
4559         cgs_get_active_displays_info(hwmgr->device, &info);
4560         num_active_displays = info.display_count;
4561
4562         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4563         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4564
4565         ref_clock = mode_info.ref_clock;
4566         refresh_rate = mode_info.refresh_rate;
4567
4568         if (0 == refresh_rate)
4569                 refresh_rate = 60;
4570
4571         frame_time_in_us = 1000000 / refresh_rate;
4572
4573         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4574         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4575
4576         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4577
4578         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4579
4580         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4581
4582         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4583
4584         return 0;
4585 }
4586
4587
4588 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4589 {
4590         return polaris10_program_display_gap(hwmgr);
4591 }
4592
4593 /**
4594 *  Set maximum target operating fan output RPM
4595 *
4596 * @param    hwmgr:  the address of the powerplay hardware manager.
4597 * @param    usMaxFanRpm:  max operating fan RPM value.
4598 * @return   The response that came from the SMC.
4599 */
4600 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4601 {
4602         hwmgr->thermal_controller.
4603         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4604
4605         if (phm_is_hw_access_blocked(hwmgr))
4606                 return 0;
4607
4608         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4609                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4610 }
4611
4612 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4613                                         const void *thermal_interrupt_info)
4614 {
4615         return 0;
4616 }
4617
4618 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4619 {
4620         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4621         bool is_update_required = false;
4622         struct cgs_display_info info = {0, 0, NULL};
4623
4624         cgs_get_active_displays_info(hwmgr->device, &info);
4625
4626         if (data->display_timing.num_existing_displays != info.display_count)
4627                 is_update_required = true;
4628 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4629         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4630                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4631                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4632                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4633                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4634                         is_update_required = true;
4635 */
4636         return is_update_required;
4637 }
4638
4639 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4640                                                            const struct polaris10_performance_level *pl2)
4641 {
4642         return ((pl1->memory_clock == pl2->memory_clock) &&
4643                   (pl1->engine_clock == pl2->engine_clock) &&
4644                   (pl1->pcie_gen == pl2->pcie_gen) &&
4645                   (pl1->pcie_lane == pl2->pcie_lane));
4646 }
4647
4648 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4649 {
4650         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4651         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4652         int i;
4653
4654         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4655                 return -EINVAL;
4656
4657         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4658         if (psa->performance_level_count != psb->performance_level_count) {
4659                 *equal = false;
4660                 return 0;
4661         }
4662
4663         for (i = 0; i < psa->performance_level_count; i++) {
4664                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4665                         /* If we have found even one performance level pair that is different the states are different. */
4666                         *equal = false;
4667                         return 0;
4668                 }
4669         }
4670
4671         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4672         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4673         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4674         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4675
4676         return 0;
4677 }
4678
4679 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4680 {
4681         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4682
4683         uint32_t vbios_version;
4684
4685         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4686
4687         phm_get_mc_microcode_version(hwmgr);
4688         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4689         /*  Full version of MC ucode has already been loaded. */
4690         if (vbios_version == 0) {
4691                 data->need_long_memory_training = false;
4692                 return 0;
4693         }
4694
4695         data->need_long_memory_training = false;
4696
4697 /*
4698  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4699         pfd = &tonga_mcmeFirmware;
4700         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4701                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4702                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4703                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4704 */
4705         return 0;
4706 }
4707
4708 /**
4709  * Read clock related registers.
4710  *
4711  * @param    hwmgr  the address of the powerplay hardware manager.
4712  * @return   always 0
4713  */
4714 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4715 {
4716         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4717
4718         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4719                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4720                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4721
4722         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4723                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4724                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4725
4726         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4727                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4728                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4729
4730         return 0;
4731 }
4732
4733 /**
4734  * Find out if memory is GDDR5.
4735  *
4736  * @param    hwmgr  the address of the powerplay hardware manager.
4737  * @return   always 0
4738  */
4739 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4740 {
4741         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4742         uint32_t temp;
4743
4744         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4745
4746         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4747                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4748                          MC_SEQ_MISC0_GDDR5_SHIFT));
4749
4750         return 0;
4751 }
4752
4753 /**
4754  * Enables Dynamic Power Management by SMC
4755  *
4756  * @param    hwmgr  the address of the powerplay hardware manager.
4757  * @return   always 0
4758  */
4759 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4760 {
4761         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4762                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4763
4764         return 0;
4765 }
4766
4767 /**
4768  * Initialize PowerGating States for different engines
4769  *
4770  * @param    hwmgr  the address of the powerplay hardware manager.
4771  * @return   always 0
4772  */
4773 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4774 {
4775         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4776
4777         data->uvd_power_gated = false;
4778         data->vce_power_gated = false;
4779         data->samu_power_gated = false;
4780
4781         return 0;
4782 }
4783
4784 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4785 {
4786         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4787         data->low_sclk_interrupt_threshold = 0;
4788
4789         return 0;
4790 }
4791
4792 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4793 {
4794         int tmp_result, result = 0;
4795
4796         polaris10_upload_mc_firmware(hwmgr);
4797
4798         tmp_result = polaris10_read_clock_registers(hwmgr);
4799         PP_ASSERT_WITH_CODE((0 == tmp_result),
4800                         "Failed to read clock registers!", result = tmp_result);
4801
4802         tmp_result = polaris10_get_memory_type(hwmgr);
4803         PP_ASSERT_WITH_CODE((0 == tmp_result),
4804                         "Failed to get memory type!", result = tmp_result);
4805
4806         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4807         PP_ASSERT_WITH_CODE((0 == tmp_result),
4808                         "Failed to enable ACPI power management!", result = tmp_result);
4809
4810         tmp_result = polaris10_init_power_gate_state(hwmgr);
4811         PP_ASSERT_WITH_CODE((0 == tmp_result),
4812                         "Failed to init power gate state!", result = tmp_result);
4813
4814         tmp_result = phm_get_mc_microcode_version(hwmgr);
4815         PP_ASSERT_WITH_CODE((0 == tmp_result),
4816                         "Failed to get MC microcode version!", result = tmp_result);
4817
4818         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4819         PP_ASSERT_WITH_CODE((0 == tmp_result),
4820                         "Failed to init sclk threshold!", result = tmp_result);
4821
4822         return result;
4823 }
4824
4825 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4826 {
4827         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4828
4829         if (!data->soft_pp_table) {
4830                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4831                                               hwmgr->soft_pp_table_size,
4832                                               GFP_KERNEL);
4833                 if (!data->soft_pp_table)
4834                         return -ENOMEM;
4835         }
4836
4837         *table = (char *)&data->soft_pp_table;
4838
4839         return hwmgr->soft_pp_table_size;
4840 }
4841
4842 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4843 {
4844         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4845
4846         if (!data->soft_pp_table) {
4847                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4848                 if (!data->soft_pp_table)
4849                         return -ENOMEM;
4850         }
4851
4852         memcpy(data->soft_pp_table, buf, size);
4853
4854         hwmgr->soft_pp_table = data->soft_pp_table;
4855
4856         /* TODO: re-init powerplay to implement modified pptable */
4857
4858         return 0;
4859 }
4860
4861 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4862                 enum pp_clock_type type, uint32_t mask)
4863 {
4864         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4865
4866         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4867                 return -EINVAL;
4868
4869         switch (type) {
4870         case PP_SCLK:
4871                 if (!data->sclk_dpm_key_disabled)
4872                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4873                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4874                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4875                 break;
4876         case PP_MCLK:
4877                 if (!data->mclk_dpm_key_disabled)
4878                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4879                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4880                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4881                 break;
4882         case PP_PCIE:
4883         {
4884                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4885                 uint32_t level = 0;
4886
4887                 while (tmp >>= 1)
4888                         level++;
4889
4890                 if (!data->pcie_dpm_key_disabled)
4891                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4892                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4893                                         level);
4894                 break;
4895         }
4896         default:
4897                 break;
4898         }
4899
4900         return 0;
4901 }
4902
4903 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4904 {
4905         uint32_t speedCntl = 0;
4906
4907         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4908         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4909                         ixPCIE_LC_SPEED_CNTL);
4910         return((uint16_t)PHM_GET_FIELD(speedCntl,
4911                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4912 }
4913
4914 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4915                 enum pp_clock_type type, char *buf)
4916 {
4917         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4918         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4919         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4920         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4921         int i, now, size = 0;
4922         uint32_t clock, pcie_speed;
4923
4924         switch (type) {
4925         case PP_SCLK:
4926                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4927                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4928
4929                 for (i = 0; i < sclk_table->count; i++) {
4930                         if (clock > sclk_table->dpm_levels[i].value)
4931                                 continue;
4932                         break;
4933                 }
4934                 now = i;
4935
4936                 for (i = 0; i < sclk_table->count; i++)
4937                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4938                                         i, sclk_table->dpm_levels[i].value / 100,
4939                                         (i == now) ? "*" : "");
4940                 break;
4941         case PP_MCLK:
4942                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4943                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4944
4945                 for (i = 0; i < mclk_table->count; i++) {
4946                         if (clock > mclk_table->dpm_levels[i].value)
4947                                 continue;
4948                         break;
4949                 }
4950                 now = i;
4951
4952                 for (i = 0; i < mclk_table->count; i++)
4953                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4954                                         i, mclk_table->dpm_levels[i].value / 100,
4955                                         (i == now) ? "*" : "");
4956                 break;
4957         case PP_PCIE:
4958                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4959                 for (i = 0; i < pcie_table->count; i++) {
4960                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4961                                 continue;
4962                         break;
4963                 }
4964                 now = i;
4965
4966                 for (i = 0; i < pcie_table->count; i++)
4967                         size += sprintf(buf + size, "%d: %s %s\n", i,
4968                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4969                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4970                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4971                                         (i == now) ? "*" : "");
4972                 break;
4973         default:
4974                 break;
4975         }
4976         return size;
4977 }
4978
4979 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4980 {
4981         if (mode) {
4982                 /* stop auto-manage */
4983                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4984                                 PHM_PlatformCaps_MicrocodeFanControl))
4985                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4986                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4987         } else
4988                 /* restart auto-manage */
4989                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4990
4991         return 0;
4992 }
4993
4994 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4995 {
4996         if (hwmgr->fan_ctrl_is_in_default_mode)
4997                 return hwmgr->fan_ctrl_default_mode;
4998         else
4999                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5000                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5001 }
5002
5003 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5004         .backend_init = &polaris10_hwmgr_backend_init,
5005         .backend_fini = &polaris10_hwmgr_backend_fini,
5006         .asic_setup = &polaris10_setup_asic_task,
5007         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5008         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5009         .force_dpm_level = &polaris10_force_dpm_level,
5010         .power_state_set = polaris10_set_power_state_tasks,
5011         .get_power_state_size = polaris10_get_power_state_size,
5012         .get_mclk = polaris10_dpm_get_mclk,
5013         .get_sclk = polaris10_dpm_get_sclk,
5014         .patch_boot_state = polaris10_dpm_patch_boot_state,
5015         .get_pp_table_entry = polaris10_get_pp_table_entry,
5016         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5017         .print_current_perforce_level = polaris10_print_current_perforce_level,
5018         .powerdown_uvd = polaris10_phm_powerdown_uvd,
5019         .powergate_uvd = polaris10_phm_powergate_uvd,
5020         .powergate_vce = polaris10_phm_powergate_vce,
5021         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5022         .update_clock_gatings = polaris10_phm_update_clock_gatings,
5023         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5024         .display_config_changed = polaris10_display_configuration_changed_task,
5025         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5026         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5027         .get_temperature = polaris10_thermal_get_temperature,
5028         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5029         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5030         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5031         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5032         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5033         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5034         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5035         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5036         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5037         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5038         .check_states_equal = polaris10_check_states_equal,
5039         .set_fan_control_mode = polaris10_set_fan_control_mode,
5040         .get_fan_control_mode = polaris10_get_fan_control_mode,
5041         .get_pp_table = polaris10_get_pp_table,
5042         .set_pp_table = polaris10_set_pp_table,
5043         .force_clock_level = polaris10_force_clock_level,
5044         .print_clock_levels = polaris10_print_clock_levels,
5045         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5046 };
5047
5048 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5049 {
5050         struct polaris10_hwmgr  *data;
5051
5052         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
5053         if (data == NULL)
5054                 return -ENOMEM;
5055
5056         hwmgr->backend = data;
5057         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5058         hwmgr->pptable_func = &tonga_pptable_funcs;
5059         pp_polaris10_thermal_initialize(hwmgr);
5060
5061         return 0;
5062 }