drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/clk.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of.h>
  37 #include <linux/of_i2c.h>
  38 #include <linux/of_gpio.h>
  39 #include <plat/gpio-cfg.h>
  40
  41 #include <drm/exynos_drm.h>
  42
  43 #include "exynos_drm_drv.h"
  44 #include "exynos_drm_display.h"
  45
  46 #include "exynos_hdmi.h"
  47
  48 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  49
  50 struct hdmi_resources {
  51         struct clk                      *hdmi;
  52         struct clk                      *sclk_hdmi;
  53         struct clk                      *sclk_pixel;
  54         struct clk                      *sclk_hdmiphy;
  55         struct clk                      *hdmiphy;
  56         struct regulator_bulk_data      *regul_bulk;
  57         int                             regul_count;
  58 };
  59
  60 struct hdmi_tg_regs {
  61         u8 cmd[1];
  62         u8 h_fsz[2];
  63         u8 hact_st[2];
  64         u8 hact_sz[2];
  65         u8 v_fsz[2];
  66         u8 vsync[2];
  67         u8 vsync2[2];
  68         u8 vact_st[2];
  69         u8 vact_sz[2];
  70         u8 field_chg[2];
  71         u8 vact_st2[2];
  72         u8 vact_st3[2];
  73         u8 vact_st4[2];
  74         u8 vsync_top_hdmi[2];
  75         u8 vsync_bot_hdmi[2];
  76         u8 field_top_hdmi[2];
  77         u8 field_bot_hdmi[2];
  78         u8 tg_3d[1];
  79 };
  80
  81 struct hdmi_core_regs {
  82         u8 h_blank[2];
  83         u8 v2_blank[2];
  84         u8 v1_blank[2];
  85         u8 v_line[2];
  86         u8 h_line[2];
  87         u8 hsync_pol[1];
  88         u8 vsync_pol[1];
  89         u8 int_pro_mode[1];
  90         u8 v_blank_f0[2];
  91         u8 v_blank_f1[2];
  92         u8 h_sync_start[2];
  93         u8 h_sync_end[2];
  94         u8 v_sync_line_bef_2[2];
  95         u8 v_sync_line_bef_1[2];
  96         u8 v_sync_line_aft_2[2];
  97         u8 v_sync_line_aft_1[2];
  98         u8 v_sync_line_aft_pxl_2[2];
  99         u8 v_sync_line_aft_pxl_1[2];
 100         u8 v_blank_f2[2]; /* for 3D mode */
 101         u8 v_blank_f3[2]; /* for 3D mode */
 102         u8 v_blank_f4[2]; /* for 3D mode */
 103         u8 v_blank_f5[2]; /* for 3D mode */
 104         u8 v_sync_line_aft_3[2];
 105         u8 v_sync_line_aft_4[2];
 106         u8 v_sync_line_aft_5[2];
 107         u8 v_sync_line_aft_6[2];
 108         u8 v_sync_line_aft_pxl_3[2];
 109         u8 v_sync_line_aft_pxl_4[2];
 110         u8 v_sync_line_aft_pxl_5[2];
 111         u8 v_sync_line_aft_pxl_6[2];
 112         u8 vact_space_1[2];
 113         u8 vact_space_2[2];
 114         u8 vact_space_3[2];
 115         u8 vact_space_4[2];
 116         u8 vact_space_5[2];
 117         u8 vact_space_6[2];
 118 };
 119
 120 struct hdmi_mode_conf {
 121         int pixel_clock;
 122         struct hdmi_core_regs core;
 123         struct hdmi_tg_regs tg;
 124         u8 vic;
 125 };
 126
 127 struct hdmi_context {
 128         struct device                   *dev;
 129         struct drm_device               *drm_dev;
 130         struct fb_videomode             *default_timing;
 131         struct hdmi_mode_conf           mode_conf;
 132         unsigned int                    is_v13:1;
 133         unsigned int                    default_win;
 134         unsigned int                    default_bpp;
 135         bool                            hpd_handle;
 136         bool                            has_hdmi_sink;
 137         bool                            has_hdmi_audio;
 138         bool                            is_soc_exynos5;
 139         bool                            is_hdmi_powered_on;
 140         bool                            video_enabled;
 141
 142         struct resource                 *regs_res;
 143         void __iomem                    *regs;
 144         unsigned int                    external_irq;
 145         unsigned int                    internal_irq;
 146         unsigned int                    curr_irq;
 147         struct workqueue_struct         *wq;
 148         struct work_struct              hotplug_work;
 149
 150         struct i2c_client               *ddc_port;
 151         struct i2c_client               *hdmiphy_port;
 152         int                             hpd_gpio;
 153         /* current hdmiphy conf index */
 154         int cur_conf;
 155
 156         struct hdmi_resources           res;
 157 };
 158
 159 /* HDMI Version 1.3 */
 160 static const u8 hdmiphy_v13_conf27[32] = {
 161         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 162         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 163         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 164         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 165 };
 166
 167 static const u8 hdmiphy_v13_conf27_027[32] = {
 168         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 169         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 170         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 171         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 172 };
 173
 174 static const u8 hdmiphy_v13_conf74_175[32] = {
 175         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 176         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 177         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 178         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 179 };
 180
 181 static const u8 hdmiphy_v13_conf74_25[32] = {
 182         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 183         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 184         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 185         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 186 };
 187
 188 static const u8 hdmiphy_v13_conf148_5[32] = {
 189         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 190         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 191         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 192         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 193 };
 194
 195 struct hdmi_v13_tg_regs {
 196         u8 cmd;
 197         u8 h_fsz_l;
 198         u8 h_fsz_h;
 199         u8 hact_st_l;
 200         u8 hact_st_h;
 201         u8 hact_sz_l;
 202         u8 hact_sz_h;
 203         u8 v_fsz_l;
 204         u8 v_fsz_h;
 205         u8 vsync_l;
 206         u8 vsync_h;
 207         u8 vsync2_l;
 208         u8 vsync2_h;
 209         u8 vact_st_l;
 210         u8 vact_st_h;
 211         u8 vact_sz_l;
 212         u8 vact_sz_h;
 213         u8 field_chg_l;
 214         u8 field_chg_h;
 215         u8 vact_st2_l;
 216         u8 vact_st2_h;
 217         u8 vsync_top_hdmi_l;
 218         u8 vsync_top_hdmi_h;
 219         u8 vsync_bot_hdmi_l;
 220         u8 vsync_bot_hdmi_h;
 221         u8 field_top_hdmi_l;
 222         u8 field_top_hdmi_h;
 223         u8 field_bot_hdmi_l;
 224         u8 field_bot_hdmi_h;
 225 };
 226
 227 struct hdmi_v13_core_regs {
 228         u8 h_blank[2];
 229         u8 v_blank[3];
 230         u8 h_v_line[3];
 231         u8 vsync_pol[1];
 232         u8 int_pro_mode[1];
 233         u8 v_blank_f[3];
 234         u8 h_sync_gen[3];
 235         u8 v_sync_gen1[3];
 236         u8 v_sync_gen2[3];
 237         u8 v_sync_gen3[3];
 238 };
 239
 240 struct hdmi_v13_preset_conf {
 241         struct hdmi_v13_core_regs core;
 242         struct hdmi_v13_tg_regs tg;
 243 };
 244
 245 struct hdmi_v13_conf {
 246         int width;
 247         int height;
 248         int vrefresh;
 249         bool interlace;
 250         const u8 *hdmiphy_data;
 251         const struct hdmi_v13_preset_conf *conf;
 252 };
 253
 254 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 255         .core = {
 256                 .h_blank = {0x8a, 0x00},
 257                 .v_blank = {0x0d, 0x6a, 0x01},
 258                 .h_v_line = {0x0d, 0xa2, 0x35},
 259                 .vsync_pol = {0x01},
 260                 .int_pro_mode = {0x00},
 261                 .v_blank_f = {0x00, 0x00, 0x00},
 262                 .h_sync_gen = {0x0e, 0x30, 0x11},
 263                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 264                 /* other don't care */
 265         },
 266         .tg = {
 267                 0x00, /* cmd */
 268                 0x5a, 0x03, /* h_fsz */
 269                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 270                 0x0d, 0x02, /* v_fsz */
 271                 0x01, 0x00, 0x33, 0x02, /* vsync */
 272                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 273                 0x33, 0x02, /* field_chg */
 274                 0x49, 0x02, /* vact_st2 */
 275                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 276                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 277         },
 278 };
 279
 280 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 281         .core = {
 282                 .h_blank = {0x72, 0x01},
 283                 .v_blank = {0xee, 0xf2, 0x00},
 284                 .h_v_line = {0xee, 0x22, 0x67},
 285                 .vsync_pol = {0x00},
 286                 .int_pro_mode = {0x00},
 287                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 288                 .h_sync_gen = {0x6c, 0x50, 0x02},
 289                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 290                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 291                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 292                 /* other don't care */
 293         },
 294         .tg = {
 295                 0x00, /* cmd */
 296                 0x72, 0x06, /* h_fsz */
 297                 0x71, 0x01, 0x01, 0x05, /* hact */
 298                 0xee, 0x02, /* v_fsz */
 299                 0x01, 0x00, 0x33, 0x02, /* vsync */
 300                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 301                 0x33, 0x02, /* field_chg */
 302                 0x49, 0x02, /* vact_st2 */
 303                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 304                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 305         },
 306 };
 307
 308 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 309         .core = {
 310                 .h_blank = {0xd0, 0x02},
 311                 .v_blank = {0x32, 0xB2, 0x00},
 312                 .h_v_line = {0x65, 0x04, 0xa5},
 313                 .vsync_pol = {0x00},
 314                 .int_pro_mode = {0x01},
 315                 .v_blank_f = {0x49, 0x2A, 0x23},
 316                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 317                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 318                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 319                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 320                 /* other don't care */
 321         },
 322         .tg = {
 323                 0x00, /* cmd */
 324                 0x50, 0x0A, /* h_fsz */
 325                 0xCF, 0x02, 0x81, 0x07, /* hact */
 326                 0x65, 0x04, /* v_fsz */
 327                 0x01, 0x00, 0x33, 0x02, /* vsync */
 328                 0x16, 0x00, 0x1c, 0x02, /* vact */
 329                 0x33, 0x02, /* field_chg */
 330                 0x49, 0x02, /* vact_st2 */
 331                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 332                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 333         },
 334 };
 335
 336 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 337         .core = {
 338                 .h_blank = {0xd0, 0x02},
 339                 .v_blank = {0x65, 0x6c, 0x01},
 340                 .h_v_line = {0x65, 0x04, 0xa5},
 341                 .vsync_pol = {0x00},
 342                 .int_pro_mode = {0x00},
 343                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 344                 .h_sync_gen = {0x0e, 0xea, 0x08},
 345                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 346                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 347                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 348                 /* other don't care */
 349         },
 350         .tg = {
 351                 0x00, /* cmd */
 352                 0x50, 0x0A, /* h_fsz */
 353                 0xCF, 0x02, 0x81, 0x07, /* hact */
 354                 0x65, 0x04, /* v_fsz */
 355                 0x01, 0x00, 0x33, 0x02, /* vsync */
 356                 0x2d, 0x00, 0x38, 0x04, /* vact */
 357                 0x33, 0x02, /* field_chg */
 358                 0x48, 0x02, /* vact_st2 */
 359                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 360                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 361         },
 362 };
 363
 364 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 365         .core = {
 366                 .h_blank = {0x18, 0x01},
 367                 .v_blank = {0x32, 0xB2, 0x00},
 368                 .h_v_line = {0x65, 0x84, 0x89},
 369                 .vsync_pol = {0x00},
 370                 .int_pro_mode = {0x01},
 371                 .v_blank_f = {0x49, 0x2A, 0x23},
 372                 .h_sync_gen = {0x56, 0x08, 0x02},
 373                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 374                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 375                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 376                 /* other don't care */
 377         },
 378         .tg = {
 379                 0x00, /* cmd */
 380                 0x98, 0x08, /* h_fsz */
 381                 0x17, 0x01, 0x81, 0x07, /* hact */
 382                 0x65, 0x04, /* v_fsz */
 383                 0x01, 0x00, 0x33, 0x02, /* vsync */
 384                 0x16, 0x00, 0x1c, 0x02, /* vact */
 385                 0x33, 0x02, /* field_chg */
 386                 0x49, 0x02, /* vact_st2 */
 387                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 388                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 389         },
 390 };
 391
 392 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 393         .core = {
 394                 .h_blank = {0x18, 0x01},
 395                 .v_blank = {0x65, 0x6c, 0x01},
 396                 .h_v_line = {0x65, 0x84, 0x89},
 397                 .vsync_pol = {0x00},
 398                 .int_pro_mode = {0x00},
 399                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 400                 .h_sync_gen = {0x56, 0x08, 0x02},
 401                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 402                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 403                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 404                 /* other don't care */
 405         },
 406         .tg = {
 407                 0x00, /* cmd */
 408                 0x98, 0x08, /* h_fsz */
 409                 0x17, 0x01, 0x81, 0x07, /* hact */
 410                 0x65, 0x04, /* v_fsz */
 411                 0x01, 0x00, 0x33, 0x02, /* vsync */
 412                 0x2d, 0x00, 0x38, 0x04, /* vact */
 413                 0x33, 0x02, /* field_chg */
 414                 0x48, 0x02, /* vact_st2 */
 415                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 416                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 417         },
 418 };
 419
 420 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 421         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 422         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 423         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 424         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 425         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 426                                  &hdmi_v13_conf_1080p50 },
 427         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 428         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 429                                  &hdmi_v13_conf_1080p60 },
 430 };
 431
 432 struct hdmiphy_config {
 433         int pixel_clock;
 434         u8 conf[32];
 435 };
 436
 437 static const struct hdmiphy_config phy_configs[] = {
 438         {
 439                 .pixel_clock = 25200000,
 440                 .conf = {
 441                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 442                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 443                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 444                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 445                 },
 446         },
 447         {
 448                 .pixel_clock = 27000000,
 449                 .conf = {
 450                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 451                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 452                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 453                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 454                 },
 455         },
 456         {
 457                 .pixel_clock = 27027000,
 458                 .conf = {
 459                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 460                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 461                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 462                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 463                 },
 464         },
 465         {
 466                 .pixel_clock = 36000000,
 467                 .conf = {
 468                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 469                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 470                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 471                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 472                 },
 473         },
 474         {
 475                 .pixel_clock = 40000000,
 476                 .conf = {
 477                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 478                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 479                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 480                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 481                 },
 482         },
 483         {
 484                 .pixel_clock = 65000000,
 485                 .conf = {
 486                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 487                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 488                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 489                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 490                 },
 491         },
 492         {
 493                 .pixel_clock = 74176000,
 494                 .conf = {
 495                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 496                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 497                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 498                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 499                 },
 500         },
 501         {
 502                 .pixel_clock = 74250000,
 503                 .conf = {
 504                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 505                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 506                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 507                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 508                 },
 509         },
 510         {
 511                 .pixel_clock = 83500000,
 512                 .conf = {
 513                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 514                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 515                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 516                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 517                 },
 518         },
 519         {
 520                 .pixel_clock = 106500000,
 521                 .conf = {
 522                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 523                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 524                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 525                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 526                 },
 527         },
 528         {
 529                 .pixel_clock = 108000000,
 530                 .conf = {
 531                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 532                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 533                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 534                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 535                 },
 536         },
 537         {
 538                 .pixel_clock = 146250000,
 539                 .conf = {
 540                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 541                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 542                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 543                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 544                 },
 545         },
 546         {
 547                 .pixel_clock = 148500000,
 548                 .conf = {
 549                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 550                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 551                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 552                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 553                 },
 554         },
 555 };
 556
 557 struct hdmi_infoframe {
 558         enum HDMI_PACKET_TYPE type;
 559         u8 ver;
 560         u8 len;
 561 };
 562
 563 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 564 {
 565         return readl(hdata->regs + reg_id);
 566 }
 567
 568 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 569                                  u32 reg_id, u8 value)
 570 {
 571         writeb(value, hdata->regs + reg_id);
 572 }
 573
 574 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 575                                  u32 reg_id, u32 value, u32 mask)
 576 {
 577         u32 old = readl(hdata->regs + reg_id);
 578         value = (value & mask) | (old & ~mask);
 579         writel(value, hdata->regs + reg_id);
 580 }
 581
 582 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 583 {
 584         if (external) {
 585                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 586                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 587         } else {
 588                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 589                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 590         }
 591 }
 592
 593 static int hdmi_get_hpd(struct hdmi_context *hdata)
 594 {
 595         return gpio_get_value(hdata->hpd_gpio);
 596 }
 597
 598 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 599 {
 600 #define DUMPREG(reg_id) \
 601         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 602         readl(hdata->regs + reg_id))
 603         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 604         DUMPREG(HDMI_INTC_FLAG);
 605         DUMPREG(HDMI_INTC_CON);
 606         DUMPREG(HDMI_HPD_STATUS);
 607         DUMPREG(HDMI_V13_PHY_RSTOUT);
 608         DUMPREG(HDMI_V13_PHY_VPLL);
 609         DUMPREG(HDMI_V13_PHY_CMU);
 610         DUMPREG(HDMI_V13_CORE_RSTOUT);
 611
 612         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 613         DUMPREG(HDMI_CON_0);
 614         DUMPREG(HDMI_CON_1);
 615         DUMPREG(HDMI_CON_2);
 616         DUMPREG(HDMI_SYS_STATUS);
 617         DUMPREG(HDMI_V13_PHY_STATUS);
 618         DUMPREG(HDMI_STATUS_EN);
 619         DUMPREG(HDMI_HPD);
 620         DUMPREG(HDMI_MODE_SEL);
 621         DUMPREG(HDMI_V13_HPD_GEN);
 622         DUMPREG(HDMI_V13_DC_CONTROL);
 623         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 624
 625         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 626         DUMPREG(HDMI_H_BLANK_0);
 627         DUMPREG(HDMI_H_BLANK_1);
 628         DUMPREG(HDMI_V13_V_BLANK_0);
 629         DUMPREG(HDMI_V13_V_BLANK_1);
 630         DUMPREG(HDMI_V13_V_BLANK_2);
 631         DUMPREG(HDMI_V13_H_V_LINE_0);
 632         DUMPREG(HDMI_V13_H_V_LINE_1);
 633         DUMPREG(HDMI_V13_H_V_LINE_2);
 634         DUMPREG(HDMI_VSYNC_POL);
 635         DUMPREG(HDMI_INT_PRO_MODE);
 636         DUMPREG(HDMI_V13_V_BLANK_F_0);
 637         DUMPREG(HDMI_V13_V_BLANK_F_1);
 638         DUMPREG(HDMI_V13_V_BLANK_F_2);
 639         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 640         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 641         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 642         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 643         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 644         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 645         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 646         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 647         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 648         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 649         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 650         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 651
 652         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 653         DUMPREG(HDMI_TG_CMD);
 654         DUMPREG(HDMI_TG_H_FSZ_L);
 655         DUMPREG(HDMI_TG_H_FSZ_H);
 656         DUMPREG(HDMI_TG_HACT_ST_L);
 657         DUMPREG(HDMI_TG_HACT_ST_H);
 658         DUMPREG(HDMI_TG_HACT_SZ_L);
 659         DUMPREG(HDMI_TG_HACT_SZ_H);
 660         DUMPREG(HDMI_TG_V_FSZ_L);
 661         DUMPREG(HDMI_TG_V_FSZ_H);
 662         DUMPREG(HDMI_TG_VSYNC_L);
 663         DUMPREG(HDMI_TG_VSYNC_H);
 664         DUMPREG(HDMI_TG_VSYNC2_L);
 665         DUMPREG(HDMI_TG_VSYNC2_H);
 666         DUMPREG(HDMI_TG_VACT_ST_L);
 667         DUMPREG(HDMI_TG_VACT_ST_H);
 668         DUMPREG(HDMI_TG_VACT_SZ_L);
 669         DUMPREG(HDMI_TG_VACT_SZ_H);
 670         DUMPREG(HDMI_TG_FIELD_CHG_L);
 671         DUMPREG(HDMI_TG_FIELD_CHG_H);
 672         DUMPREG(HDMI_TG_VACT_ST2_L);
 673         DUMPREG(HDMI_TG_VACT_ST2_H);
 674         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 675         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 676         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 677         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 678         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 679         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 680         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 681         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 682 #undef DUMPREG
 683 }
 684
 685 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 686 {
 687         int i;
 688
 689 #define DUMPREG(reg_id) \
 690         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 691         readl(hdata->regs + reg_id))
 692
 693         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 694         DUMPREG(HDMI_INTC_CON);
 695         DUMPREG(HDMI_INTC_FLAG);
 696         DUMPREG(HDMI_HPD_STATUS);
 697         DUMPREG(HDMI_INTC_CON_1);
 698         DUMPREG(HDMI_INTC_FLAG_1);
 699         DUMPREG(HDMI_PHY_STATUS_0);
 700         DUMPREG(HDMI_PHY_STATUS_PLL);
 701         DUMPREG(HDMI_PHY_CON_0);
 702         DUMPREG(HDMI_PHY_RSTOUT);
 703         DUMPREG(HDMI_PHY_VPLL);
 704         DUMPREG(HDMI_PHY_CMU);
 705         DUMPREG(HDMI_CORE_RSTOUT);
 706
 707         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 708         DUMPREG(HDMI_CON_0);
 709         DUMPREG(HDMI_CON_1);
 710         DUMPREG(HDMI_CON_2);
 711         DUMPREG(HDMI_SYS_STATUS);
 712         DUMPREG(HDMI_PHY_STATUS_0);
 713         DUMPREG(HDMI_STATUS_EN);
 714         DUMPREG(HDMI_HPD);
 715         DUMPREG(HDMI_MODE_SEL);
 716         DUMPREG(HDMI_ENC_EN);
 717         DUMPREG(HDMI_DC_CONTROL);
 718         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 719
 720         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 721         DUMPREG(HDMI_H_BLANK_0);
 722         DUMPREG(HDMI_H_BLANK_1);
 723         DUMPREG(HDMI_V2_BLANK_0);
 724         DUMPREG(HDMI_V2_BLANK_1);
 725         DUMPREG(HDMI_V1_BLANK_0);
 726         DUMPREG(HDMI_V1_BLANK_1);
 727         DUMPREG(HDMI_V_LINE_0);
 728         DUMPREG(HDMI_V_LINE_1);
 729         DUMPREG(HDMI_H_LINE_0);
 730         DUMPREG(HDMI_H_LINE_1);
 731         DUMPREG(HDMI_HSYNC_POL);
 732
 733         DUMPREG(HDMI_VSYNC_POL);
 734         DUMPREG(HDMI_INT_PRO_MODE);
 735         DUMPREG(HDMI_V_BLANK_F0_0);
 736         DUMPREG(HDMI_V_BLANK_F0_1);
 737         DUMPREG(HDMI_V_BLANK_F1_0);
 738         DUMPREG(HDMI_V_BLANK_F1_1);
 739
 740         DUMPREG(HDMI_H_SYNC_START_0);
 741         DUMPREG(HDMI_H_SYNC_START_1);
 742         DUMPREG(HDMI_H_SYNC_END_0);
 743         DUMPREG(HDMI_H_SYNC_END_1);
 744
 745         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 746         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 747         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 748         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 749
 750         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 751         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 752         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 753         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 754
 755         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 756         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 757         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 758         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 759
 760         DUMPREG(HDMI_V_BLANK_F2_0);
 761         DUMPREG(HDMI_V_BLANK_F2_1);
 762         DUMPREG(HDMI_V_BLANK_F3_0);
 763         DUMPREG(HDMI_V_BLANK_F3_1);
 764         DUMPREG(HDMI_V_BLANK_F4_0);
 765         DUMPREG(HDMI_V_BLANK_F4_1);
 766         DUMPREG(HDMI_V_BLANK_F5_0);
 767         DUMPREG(HDMI_V_BLANK_F5_1);
 768
 769         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 776         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 777
 778         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 779         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 780         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 781         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 782         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 783         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 784         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 785         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 786
 787         DUMPREG(HDMI_VACT_SPACE_1_0);
 788         DUMPREG(HDMI_VACT_SPACE_1_1);
 789         DUMPREG(HDMI_VACT_SPACE_2_0);
 790         DUMPREG(HDMI_VACT_SPACE_2_1);
 791         DUMPREG(HDMI_VACT_SPACE_3_0);
 792         DUMPREG(HDMI_VACT_SPACE_3_1);
 793         DUMPREG(HDMI_VACT_SPACE_4_0);
 794         DUMPREG(HDMI_VACT_SPACE_4_1);
 795         DUMPREG(HDMI_VACT_SPACE_5_0);
 796         DUMPREG(HDMI_VACT_SPACE_5_1);
 797         DUMPREG(HDMI_VACT_SPACE_6_0);
 798         DUMPREG(HDMI_VACT_SPACE_6_1);
 799
 800         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 801         DUMPREG(HDMI_TG_CMD);
 802         DUMPREG(HDMI_TG_H_FSZ_L);
 803         DUMPREG(HDMI_TG_H_FSZ_H);
 804         DUMPREG(HDMI_TG_HACT_ST_L);
 805         DUMPREG(HDMI_TG_HACT_ST_H);
 806         DUMPREG(HDMI_TG_HACT_SZ_L);
 807         DUMPREG(HDMI_TG_HACT_SZ_H);
 808         DUMPREG(HDMI_TG_V_FSZ_L);
 809         DUMPREG(HDMI_TG_V_FSZ_H);
 810         DUMPREG(HDMI_TG_VSYNC_L);
 811         DUMPREG(HDMI_TG_VSYNC_H);
 812         DUMPREG(HDMI_TG_VSYNC2_L);
 813         DUMPREG(HDMI_TG_VSYNC2_H);
 814         DUMPREG(HDMI_TG_VACT_ST_L);
 815         DUMPREG(HDMI_TG_VACT_ST_H);
 816         DUMPREG(HDMI_TG_VACT_SZ_L);
 817         DUMPREG(HDMI_TG_VACT_SZ_H);
 818         DUMPREG(HDMI_TG_FIELD_CHG_L);
 819         DUMPREG(HDMI_TG_FIELD_CHG_H);
 820         DUMPREG(HDMI_TG_VACT_ST2_L);
 821         DUMPREG(HDMI_TG_VACT_ST2_H);
 822         DUMPREG(HDMI_TG_VACT_ST3_L);
 823         DUMPREG(HDMI_TG_VACT_ST3_H);
 824         DUMPREG(HDMI_TG_VACT_ST4_L);
 825         DUMPREG(HDMI_TG_VACT_ST4_H);
 826         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 827         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 828         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 829         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 830         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 831         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 832         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 833         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 834         DUMPREG(HDMI_TG_3D);
 835
 836         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 837         DUMPREG(HDMI_AVI_CON);
 838         DUMPREG(HDMI_AVI_HEADER0);
 839         DUMPREG(HDMI_AVI_HEADER1);
 840         DUMPREG(HDMI_AVI_HEADER2);
 841         DUMPREG(HDMI_AVI_CHECK_SUM);
 842         DUMPREG(HDMI_VSI_CON);
 843         DUMPREG(HDMI_VSI_HEADER0);
 844         DUMPREG(HDMI_VSI_HEADER1);
 845         DUMPREG(HDMI_VSI_HEADER2);
 846         for (i = 0; i < 7; ++i)
 847                 DUMPREG(HDMI_VSI_DATA(i));
 848
 849 #undef DUMPREG
 850 }
 851
 852 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 853 {
 854         if (hdata->is_v13)
 855                 hdmi_v13_regs_dump(hdata, prefix);
 856         else
 857                 hdmi_v14_regs_dump(hdata, prefix);
 858 }
 859
 860 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 861 {
 862         int i;
 863
 864         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 865                 if (hdmi_v13_confs[i].width == mode->hdisplay &&
 866                                 hdmi_v13_confs[i].height == mode->vdisplay &&
 867                                 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 868                                 hdmi_v13_confs[i].interlace ==
 869                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 870                                  true : false))
 871                         return i;
 872
 873         return -EINVAL;
 874 }
 875
 876 static bool hdmi_is_connected(void *ctx)
 877 {
 878         struct hdmi_context *hdata = ctx;
 879         if (hdata->is_hdmi_powered_on) {
 880                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 881                         DRM_DEBUG_KMS("hdmi is not connected\n");
 882                         return false;
 883                 }
 884         } else if (!hdmi_get_hpd(hdata)) {
 885                         DRM_DEBUG_KMS("hdmi is not connected\n");
 886                         return false;
 887         }
 888
 889         return true;
 890 }
 891
 892 static struct edid *hdmi_get_edid(void *ctx, struct drm_connector *connector)
 893 {
 894         struct hdmi_context *hdata = ctx;
 895         struct edid *edid;
 896
 897         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", DRM_BASE_ID(connector),
 898                         drm_get_connector_name(connector));
 899
 900         if (!hdata->ddc_port)
 901                 return ERR_PTR(-ENODEV);
 902
 903         edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 904         if (!edid)
 905                 return ERR_PTR(-ENODEV);
 906
 907         /*
 908          * TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 909          * to get the edid and then call drm_detect_hdmi_monitor.
 910          */
 911         hdata->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
 912         hdata->has_hdmi_audio = drm_detect_monitor_audio(edid);
 913         DRM_DEBUG_KMS("%s monitor\n", hdata->has_hdmi_sink ? "hdmi" : "dvi");
 914
 915         return edid;
 916 }
 917
 918 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 919 {
 920         int i;
 921
 922         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 923                         check_timing->xres, check_timing->yres,
 924                         check_timing->refresh, (check_timing->vmode &
 925                         FB_VMODE_INTERLACED) ? true : false);
 926
 927         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 928                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 929                         hdmi_v13_confs[i].height == check_timing->yres &&
 930                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 931                         hdmi_v13_confs[i].interlace ==
 932                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 933                          true : false))
 934                                 return 0;
 935
 936         /* TODO */
 937
 938         return -EINVAL;
 939 }
 940
 941 static int find_hdmiphy_conf(int pixel_clock)
 942 {
 943         int i;
 944
 945         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 946                 if (phy_configs[i].pixel_clock == pixel_clock)
 947                         return i;
 948         }
 949         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 950         return -EINVAL;
 951 }
 952
 953 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 954 {
 955         int ret;
 956         enum exynos_mixer_mode_type mode_type;
 957
 958         /* Make sure the mixer can generate this mode */
 959         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 960         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 961                 return -EINVAL;
 962
 963         ret = find_hdmiphy_conf(mode->pixclock);
 964         return ret < 0 ? ret : 0;
 965 }
 966
 967 static u8 hdmi_chksum(struct hdmi_context *hdata,
 968                         u32 start, u8 len, u32 hdr_sum)
 969 {
 970         int i;
 971         /* hdr_sum : header0 + header1 + header2
 972         * start : start address of packet byte1
 973         * len : packet bytes - 1 */
 974         for (i = 0; i < len; ++i)
 975                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 976
 977         return (u8)(0x100 - (hdr_sum & 0xff));
 978 }
 979
 980 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 981                         struct hdmi_infoframe *infoframe)
 982 {
 983         u32 hdr_sum;
 984         u8 chksum;
 985         u32 aspect_ratio;
 986         u32 mod;
 987
 988         /* TODO: stringify HDMI_PACKET_TYPE */
 989         DRM_DEBUG_KMS("type: %d ver: %d len: %d\n", infoframe->type,
 990                         infoframe->ver, infoframe->len);
 991         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 992         if (!hdata->has_hdmi_sink) {
 993                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 994                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 995                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 996                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 997                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 998                 return;
 999         }
1000
1001         switch (infoframe->type) {
1002
1003         case HDMI_PACKET_TYPE_AVI:
1004                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1005                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
1006                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
1007                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
1008                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1009                 /* Output format zero hardcoded ,RGB YBCR selection */
1010                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1011                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
1012
1013                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
1014
1015                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
1016                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
1017                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
1018
1019                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1020                                         infoframe->len, hdr_sum);
1021                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1022                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1023                 break;
1024
1025         case HDMI_PACKET_TYPE_AUI:
1026                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1027                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
1028                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
1029                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
1030                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1031                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1032                                         infoframe->len, hdr_sum);
1033                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1034                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1035                 break;
1036
1037         default:
1038                 break;
1039         }
1040 }
1041
1042 static int hdmi_check_timing(void *ctx, void *timing)
1043 {
1044         struct hdmi_context *hdata = ctx;
1045         struct fb_videomode *check_timing = timing;
1046
1047         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1048                         check_timing->yres, check_timing->refresh,
1049                         check_timing->vmode);
1050
1051         if (hdata->is_v13)
1052                 return hdmi_v13_check_timing(check_timing);
1053         else
1054                 return hdmi_v14_check_timing(check_timing);
1055 }
1056
1057 static void hdmi_set_acr(u32 freq, u8 *acr)
1058 {
1059         u32 n, cts;
1060
1061         switch (freq) {
1062         case 32000:
1063                 n = 4096;
1064                 cts = 27000;
1065                 break;
1066         case 44100:
1067                 n = 6272;
1068                 cts = 30000;
1069                 break;
1070         case 88200:
1071                 n = 12544;
1072                 cts = 30000;
1073                 break;
1074         case 176400:
1075                 n = 25088;
1076                 cts = 30000;
1077                 break;
1078         case 48000:
1079                 n = 6144;
1080                 cts = 27000;
1081                 break;
1082         case 96000:
1083                 n = 12288;
1084                 cts = 27000;
1085                 break;
1086         case 192000:
1087                 n = 24576;
1088                 cts = 27000;
1089                 break;
1090         default:
1091                 n = 0;
1092                 cts = 0;
1093                 break;
1094         }
1095
1096         acr[1] = cts >> 16;
1097         acr[2] = cts >> 8 & 0xff;
1098         acr[3] = cts & 0xff;
1099
1100         acr[4] = n >> 16;
1101         acr[5] = n >> 8 & 0xff;
1102         acr[6] = n & 0xff;
1103 }
1104
1105 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1106 {
1107         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1108         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1109         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1110         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1111         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1112         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1113         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1114         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1115         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1116
1117         if (hdata->is_v13)
1118                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1119         else
1120                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1121 }
1122
1123 static void hdmi_audio_init(struct hdmi_context *hdata)
1124 {
1125         u32 sample_rate, bits_per_sample, frame_size_code;
1126         u32 data_num, bit_ch, sample_frq;
1127         u32 val;
1128         u8 acr[7];
1129
1130         sample_rate = 44100;
1131         bits_per_sample = 16;
1132         frame_size_code = 0;
1133
1134         switch (bits_per_sample) {
1135         case 20:
1136                 data_num = 2;
1137                 bit_ch  = 1;
1138                 break;
1139         case 24:
1140                 data_num = 3;
1141                 bit_ch  = 1;
1142                 break;
1143         default:
1144                 data_num = 1;
1145                 bit_ch  = 0;
1146                 break;
1147         }
1148
1149         hdmi_set_acr(sample_rate, acr);
1150         hdmi_reg_acr(hdata, acr);
1151
1152         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1153                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1154                                 | HDMI_I2S_MUX_ENABLE);
1155
1156         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1157                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1158
1159         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1160
1161         sample_frq = (sample_rate == 44100) ? 0 :
1162                         (sample_rate == 48000) ? 2 :
1163                         (sample_rate == 32000) ? 3 :
1164                         (sample_rate == 96000) ? 0xa : 0x0;
1165
1166         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1167         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1168
1169         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1170         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1171
1172         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1173         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1174                         | HDMI_I2S_SEL_LRCK(6));
1175         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1176                         | HDMI_I2S_SEL_SDATA2(4));
1177         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1178                         | HDMI_I2S_SEL_SDATA2(2));
1179         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1180
1181         /* I2S_CON_1 & 2 */
1182         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1183                         | HDMI_I2S_L_CH_LOW_POL);
1184         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1185                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1186                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1187                         | HDMI_I2S_BASIC_FORMAT);
1188
1189         /* Configure register related to CUV information */
1190         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1191                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1192                         | HDMI_I2S_COPYRIGHT
1193                         | HDMI_I2S_LINEAR_PCM
1194                         | HDMI_I2S_CONSUMER_FORMAT);
1195         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1196         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1197         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1198                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1199         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1200                         HDMI_I2S_ORG_SMP_FREQ_44_1
1201                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1202                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1203
1204         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1205 }
1206
1207 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1208 {
1209         if (!hdata->has_hdmi_audio)
1210                 return;
1211
1212         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1213         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1214                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1215 }
1216
1217 static void hdmi_conf_reset(struct hdmi_context *hdata)
1218 {
1219         u32 reg;
1220
1221         /* disable hpd handle for drm */
1222         hdata->hpd_handle = false;
1223
1224         if (hdata->is_v13)
1225                 reg = HDMI_V13_CORE_RSTOUT;
1226         else
1227                 reg = HDMI_CORE_RSTOUT;
1228
1229         /* resetting HDMI core */
1230         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1231         mdelay(10);
1232         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1233         mdelay(10);
1234
1235         /* enable hpd handle for drm */
1236         hdata->hpd_handle = true;
1237 }
1238
1239 static void hdmi_enable_video(struct hdmi_context *hdata)
1240 {
1241         if (hdata->is_v13)
1242                 return;
1243
1244         hdata->video_enabled = true;
1245         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1246 }
1247
1248 static void hdmi_disable_video(struct hdmi_context *hdata)
1249 {
1250         if (hdata->is_v13)
1251                 return;
1252
1253         /* Set the blue screen color to black */
1254         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_0, 0);
1255         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_1, 0);
1256         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_0, 0);
1257         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_1, 0);
1258         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_0, 0);
1259         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_1, 0);
1260
1261         /* Enable the "blue screen", which effectively disconnects the mixer */
1262         hdata->video_enabled = false;
1263         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
1264 }
1265
1266 static void hdmi_conf_init(struct hdmi_context *hdata)
1267 {
1268         struct hdmi_infoframe infoframe;
1269         /* disable hpd handle for drm */
1270         hdata->hpd_handle = false;
1271
1272         /* enable HPD interrupts */
1273         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1274                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1275         mdelay(10);
1276         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1277                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1278
1279         /* choose HDMI mode */
1280         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1281                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1282
1283         if (hdata->video_enabled)
1284                 hdmi_enable_video(hdata);
1285         else
1286                 hdmi_disable_video(hdata);
1287
1288         if (!hdata->has_hdmi_sink) {
1289                 /* choose DVI mode */
1290                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1291                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1292                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1293                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1294         }
1295
1296         if (hdata->is_v13) {
1297                 /* choose bluescreen (fecal) color */
1298                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1299                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1300                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1301
1302                 /* enable AVI packet every vsync, fixes purple line problem */
1303                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1304                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1305                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1306                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1307
1308                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1309                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1310                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1311         } else {
1312                 /* enable AVI packet every vsync, fixes purple line problem */
1313                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1314
1315                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1316                 infoframe.ver = HDMI_AVI_VERSION;
1317                 infoframe.len = HDMI_AVI_LENGTH;
1318                 hdmi_reg_infoframe(hdata, &infoframe);
1319
1320                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1321                 infoframe.ver = HDMI_AUI_VERSION;
1322                 infoframe.len = HDMI_AUI_LENGTH;
1323                 hdmi_reg_infoframe(hdata, &infoframe);
1324
1325         }
1326
1327         /* enable hpd handle for drm */
1328         hdata->hpd_handle = true;
1329 }
1330
1331 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1332 {
1333         const struct hdmi_v13_preset_conf *conf =
1334                 hdmi_v13_confs[hdata->cur_conf].conf;
1335         const struct hdmi_v13_core_regs *core = &conf->core;
1336         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1337         int tries;
1338
1339         /* setting core registers */
1340         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1341         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1342         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1343         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1344         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1345         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1346         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1347         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1348         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1349         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1350         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1351         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1352         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1353         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1354         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1355         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1356         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1357         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1358         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1359         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1360         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1361         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1362         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1363         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1364         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1365         /* Timing generator registers */
1366         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1367         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1368         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1369         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1370         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1371         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1372         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1373         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1374         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1375         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1376         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1377         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1378         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1379         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1380         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1381         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1382         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1383         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1384         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1385         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1386         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1387         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1388         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1389         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1390         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1391         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1392         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1393         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1394
1395         /* waiting for HDMIPHY's PLL to get to steady state */
1396         for (tries = 100; tries; --tries) {
1397                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1398                 if (val & HDMI_PHY_STATUS_READY)
1399                         break;
1400                 mdelay(1);
1401         }
1402         /* steady state not achieved */
1403         if (tries == 0) {
1404                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1405                 hdmi_regs_dump(hdata, "timing apply");
1406         }
1407
1408         clk_disable(hdata->res.sclk_hdmi);
1409         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1410         clk_enable(hdata->res.sclk_hdmi);
1411
1412         /* enable HDMI and timing generator */
1413         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1414         if (core->int_pro_mode[0])
1415                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1416                                 HDMI_FIELD_EN);
1417         else
1418                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1419 }
1420
1421 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1422 {
1423         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1424         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1425         int tries;
1426
1427         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1428         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1429         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1430         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1431         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1432         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1433         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1434         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1435         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1436         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1437         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1438         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1439         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1440         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1441         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1442         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1443         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1444         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1445         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1446         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1447         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1448         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1449                         core->v_sync_line_bef_2[0]);
1450         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1451                         core->v_sync_line_bef_2[1]);
1452         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1453                         core->v_sync_line_bef_1[0]);
1454         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1455                         core->v_sync_line_bef_1[1]);
1456         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1457                         core->v_sync_line_aft_2[0]);
1458         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1459                         core->v_sync_line_aft_2[1]);
1460         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1461                         core->v_sync_line_aft_1[0]);
1462         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1463                         core->v_sync_line_aft_1[1]);
1464         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1465                         core->v_sync_line_aft_pxl_2[0]);
1466         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1467                         core->v_sync_line_aft_pxl_2[1]);
1468         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1469                         core->v_sync_line_aft_pxl_1[0]);
1470         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1471                         core->v_sync_line_aft_pxl_1[1]);
1472         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1473         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1474         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1475         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1476         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1477         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1478         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1479         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1480         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1481                         core->v_sync_line_aft_3[0]);
1482         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1483                         core->v_sync_line_aft_3[1]);
1484         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1485                         core->v_sync_line_aft_4[0]);
1486         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1487                         core->v_sync_line_aft_4[1]);
1488         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1489                         core->v_sync_line_aft_5[0]);
1490         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1491                         core->v_sync_line_aft_5[1]);
1492         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1493                         core->v_sync_line_aft_6[0]);
1494         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1495                         core->v_sync_line_aft_6[1]);
1496         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1497                         core->v_sync_line_aft_pxl_3[0]);
1498         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1499                         core->v_sync_line_aft_pxl_3[1]);
1500         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1501                         core->v_sync_line_aft_pxl_4[0]);
1502         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1503                         core->v_sync_line_aft_pxl_4[1]);
1504         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1505                         core->v_sync_line_aft_pxl_5[0]);
1506         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1507                         core->v_sync_line_aft_pxl_5[1]);
1508         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1509                         core->v_sync_line_aft_pxl_6[0]);
1510         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1511                         core->v_sync_line_aft_pxl_6[1]);
1512         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1513         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1514         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1515         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1516         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1517         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1518         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1519         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1520         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1521         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1522         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1523         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1524
1525         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1526         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1527         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1528         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1529         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1530         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1531         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1532         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1533         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1534         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1535         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1536         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1537         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1538         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1539         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1540         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1541         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1542         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1543         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1544         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1545         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1546         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1547         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1548         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1549         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1550         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1551         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1552         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1553         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1554         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1555         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1556         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1557         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1558
1559         /* waiting for HDMIPHY's PLL to get to steady state */
1560         for (tries = 100; tries; --tries) {
1561                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1562                 if (val & HDMI_PHY_STATUS_READY)
1563                         break;
1564                 mdelay(1);
1565         }
1566         /* steady state not achieved */
1567         if (tries == 0) {
1568                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1569                 hdmi_regs_dump(hdata, "timing apply");
1570         }
1571
1572         clk_disable(hdata->res.sclk_hdmi);
1573         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1574         clk_enable(hdata->res.sclk_hdmi);
1575
1576         /* enable HDMI and timing generator */
1577         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1578         if (core->int_pro_mode[0])
1579                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1580                                 HDMI_FIELD_EN);
1581         else
1582                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1583 }
1584
1585 static void hdmi_timing_apply(struct hdmi_context *hdata)
1586 {
1587         if (hdata->is_v13)
1588                 hdmi_v13_timing_apply(hdata);
1589         else
1590                 hdmi_v14_timing_apply(hdata);
1591 }
1592
1593 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1594 {
1595         u8 buffer[2];
1596         u32 reg;
1597
1598         clk_disable(hdata->res.sclk_hdmi);
1599         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1600         clk_enable(hdata->res.sclk_hdmi);
1601
1602         /* operation mode */
1603         buffer[0] = 0x1f;
1604         buffer[1] = 0x00;
1605
1606         if (hdata->hdmiphy_port)
1607                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1608
1609         if (hdata->is_v13)
1610                 reg = HDMI_V13_PHY_RSTOUT;
1611         else
1612                 reg = HDMI_PHY_RSTOUT;
1613
1614         /* reset hdmiphy */
1615         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1616         mdelay(10);
1617         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1618         mdelay(10);
1619 }
1620
1621 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1622 {
1623         const u8 *hdmiphy_data;
1624         u8 buffer[32];
1625         u8 operation[2];
1626         u8 read_buffer[32] = {0, };
1627         int ret;
1628         int i;
1629
1630         DRM_DEBUG_KMS("\n");
1631
1632         if (!hdata->hdmiphy_port) {
1633                 DRM_ERROR("hdmiphy is not attached\n");
1634                 return;
1635         }
1636
1637         /* pixel clock */
1638         if (hdata->is_v13) {
1639                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1640         } else {
1641                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1642                 hdmiphy_data = phy_configs[i].conf;
1643         }
1644
1645         memcpy(buffer, hdmiphy_data, 32);
1646         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1647         if (ret != 32) {
1648                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1649                 return;
1650         }
1651
1652         mdelay(10);
1653
1654         /* operation mode */
1655         operation[0] = 0x1f;
1656         operation[1] = 0x80;
1657
1658         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1659         if (ret != 2) {
1660                 DRM_ERROR("failed to enable hdmiphy\n");
1661                 return;
1662         }
1663
1664         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1665         if (ret < 0) {
1666                 DRM_ERROR("failed to read hdmiphy config\n");
1667                 return;
1668         }
1669
1670         for (i = 0; i < ret; i++)
1671                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1672                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1673 }
1674
1675 static void hdmi_conf_apply(struct hdmi_context *hdata)
1676 {
1677         DRM_DEBUG_KMS("\n");
1678
1679         hdmiphy_conf_reset(hdata);
1680         hdmiphy_conf_apply(hdata);
1681
1682         hdmi_conf_reset(hdata);
1683         hdmi_conf_init(hdata);
1684         if (!hdata->is_soc_exynos5)
1685                 hdmi_audio_init(hdata);
1686
1687         /* setting core registers */
1688         hdmi_timing_apply(hdata);
1689         if (!hdata->is_soc_exynos5)
1690                 hdmi_audio_control(hdata, true);
1691
1692         hdmi_regs_dump(hdata, "start");
1693 }
1694
1695 static void hdmi_mode_copy(struct drm_display_mode *dst,
1696         struct drm_display_mode *src)
1697 {
1698         struct drm_mode_object base;
1699
1700         DRM_DEBUG_KMS("[MODE:%d:%s]\n", DRM_BASE_ID(src), src->name);
1701
1702         /* following information should be preserved,
1703          * required for releasing the drm_display_mode node,
1704          * duplicated to recieve adjustment info. */
1705
1706         base.id = dst->base.id;
1707         base.type = dst->base.type;
1708
1709         memcpy(dst, src, sizeof(struct drm_display_mode));
1710
1711         dst->base.id = base.id;
1712         dst->base.type = base.type;
1713 }
1714
1715 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1716                                 struct drm_display_mode *mode,
1717                                 struct drm_display_mode *adjusted_mode)
1718 {
1719         struct drm_display_mode *m;
1720         struct hdmi_context *hdata = ctx;
1721         int index;
1722
1723         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] [MODE:%d:%s]\n",
1724                         DRM_BASE_ID(connector),
1725                         drm_get_connector_name(connector),
1726                         DRM_BASE_ID(mode), mode->name);
1727
1728         drm_mode_set_crtcinfo(adjusted_mode, 0);
1729
1730         if (hdata->is_v13)
1731                 index = hdmi_v13_conf_index(adjusted_mode);
1732         else
1733                 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1734
1735         /* just return if user desired mode exists. */
1736         if (index >= 0)
1737                 return;
1738
1739         /*
1740          * otherwise, find the most suitable mode among modes and change it
1741          * to adjusted_mode.
1742          */
1743         list_for_each_entry(m, &connector->modes, head) {
1744                 if (hdata->is_v13)
1745                         index = hdmi_v13_conf_index(m);
1746                 else
1747                         index = find_hdmiphy_conf(m->clock * 1000);
1748
1749                 if (index >= 0) {
1750                         DRM_INFO("desired mode doesn't exist so\n");
1751                         DRM_INFO("use the most suitable mode among modes.\n");
1752                         hdmi_mode_copy(adjusted_mode, m);
1753                         break;
1754                 }
1755         }
1756 }
1757
1758 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1759 {
1760         int i;
1761         BUG_ON(num_bytes > 4);
1762         for (i = 0; i < num_bytes; i++)
1763                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1764 }
1765
1766 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1767                         struct drm_display_mode *m)
1768 {
1769         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1770         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1771
1772         DRM_DEBUG_KMS("[MODE:%d:%s]\n", DRM_BASE_ID(m), m->name);
1773
1774         hdata->mode_conf.vic = drm_match_cea_mode(m);
1775
1776         hdata->mode_conf.pixel_clock = m->clock * 1000;
1777         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1778         hdmi_set_reg(core->v_line, 2, m->vtotal);
1779         hdmi_set_reg(core->h_line, 2, m->htotal);
1780         hdmi_set_reg(core->hsync_pol, 1,
1781                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1782         hdmi_set_reg(core->vsync_pol, 1,
1783                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1784         hdmi_set_reg(core->int_pro_mode, 1,
1785                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1786
1787         /*
1788          * Quirk requirement for exynos 5 HDMI IP design,
1789          * 2 pixels less than the actual calculation for hsync_start
1790          * and end.
1791          */
1792
1793         /* Following values & calculations differ for different type of modes */
1794         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1795                 /* Interlaced Mode */
1796                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1797                         (m->vsync_end - m->vdisplay) / 2);
1798                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1799                         (m->vsync_start - m->vdisplay) / 2);
1800                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1801                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1802                 hdmi_set_reg(core->v_blank_f0, 2,
1803                         (m->vtotal + ((m->vsync_end - m->vsync_start) * 4) + 5) / 2);
1804                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1805                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1806                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1807                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1808                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1809                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1810                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1811                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1812                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1813                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1814                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1815                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1816         } else {
1817                 /* Progressive Mode */
1818                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1819                         m->vsync_end - m->vdisplay);
1820                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1821                         m->vsync_start - m->vdisplay);
1822                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1823                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1824                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1825                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1826                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1827                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1828                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1829                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1830                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1831                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1832                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1833                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1834                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1835         }
1836
1837         /* Following values & calculations are same irrespective of mode type */
1838         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1839         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1840         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1841         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1842         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1843         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1844         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1845         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1846         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1847         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1848         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1849         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1850         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1851         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1852         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1853         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1854         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1855         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1856         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1857         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1858
1859         /* Timing generator registers */
1860         hdmi_set_reg(tg->cmd, 1, 0x0);
1861         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1862         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1863         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1864         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1865         hdmi_set_reg(tg->vsync, 2, 0x1);
1866         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1867         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1868         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1869         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1870         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1871         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1872         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1873
1874         /* Workaround 4 implementation for 1440x900 resolution support */
1875         if (hdata->is_soc_exynos5) {
1876                 if (m->hdisplay == 1440 && m->vdisplay == 900 && m->clock == 106500) {
1877                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0xe0);
1878                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0xe0);
1879                 }
1880         }
1881 }
1882
1883 static void hdmi_mode_set(void *ctx, struct drm_display_mode *mode)
1884 {
1885         struct hdmi_context *hdata = ctx;
1886
1887         DRM_DEBUG_KMS("[MODE:%d:%s]\n", DRM_BASE_ID(mode), mode->name);
1888
1889         if (hdata->is_v13)
1890                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1891         else
1892                 hdmi_v14_mode_set(hdata, mode);
1893 }
1894
1895 static int hdmiphy_update_bits(struct i2c_client *client, u8 *reg_cache,
1896                                u8 reg, u8 mask, u8 val)
1897 {
1898         int ret;
1899         u8 buffer[2];
1900
1901         buffer[0] = reg;
1902         buffer[1] = (reg_cache[reg] & ~mask) | (val & mask);
1903         reg_cache[reg] = buffer[1];
1904
1905         ret = i2c_master_send(client, buffer, 2);
1906         if (ret != 2)
1907                 return -EIO;
1908
1909         return 0;
1910 }
1911
1912 static int hdmiphy_s_power(struct i2c_client *client, bool on)
1913 {
1914         u8 reg_cache[32] = { 0 };
1915         u8 buffer[2];
1916         int ret;
1917
1918         DRM_DEBUG_KMS("%s\n", on ? "on" : "off");
1919
1920         /* Cache all 32 registers to make the code below faster */
1921         buffer[0] = 0x0;
1922         ret = i2c_master_send(client, buffer, 1);
1923         if (ret != 1) {
1924                 ret = -EIO;
1925                 goto exit;
1926         }
1927         ret = i2c_master_recv(client, reg_cache, 32);
1928         if (ret != 32) {
1929                 ret = -EIO;
1930                 goto exit;
1931         }
1932
1933         /* Go to/from configuration from/to operation mode */
1934         ret = hdmiphy_update_bits(client, reg_cache, 0x1f, 0xff,
1935                                   on ? 0x80 : 0x00);
1936         if (ret)
1937                 goto exit;
1938
1939         /*
1940          * Turn off undocumented "oscpad" if !on; it turns on again in
1941          * hdmiphy_conf_apply()
1942          */
1943         if (!on)
1944                 ret = hdmiphy_update_bits(client, reg_cache, 0x0b, 0xc0, 0x00);
1945                 if (ret)
1946                         goto exit;
1947
1948         /* Disable powerdown if on; enable if !on */
1949         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x80,
1950                                   on ? 0 : ~0);
1951         if (ret)
1952                 goto exit;
1953         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x77,
1954                                   on ? 0 : ~0);
1955         if (ret)
1956                 goto exit;
1957
1958         /*
1959          * Turn off bit 3 of reg 4 if !on; it turns on again in
1960          * hdmiphy_conf_apply().  It's unclear what this bit does.
1961          */
1962         if (!on)
1963                 ret = hdmiphy_update_bits(client, reg_cache, 0x04, BIT(3), 0);
1964                 if (ret)
1965                         goto exit;
1966
1967 exit:
1968         /* Don't expect any errors so just do a single warn */
1969         WARN_ON(ret);
1970
1971         return ret;
1972 }
1973
1974 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1975 {
1976         struct hdmi_resources *res = &hdata->res;
1977
1978         hdata->is_hdmi_powered_on = true;
1979         hdmi_cfg_hpd(hdata, false);
1980
1981         /* irq change by TV power status */
1982         if (hdata->curr_irq == hdata->internal_irq)
1983                 return;
1984
1985         disable_irq(hdata->curr_irq);
1986
1987         hdata->curr_irq = hdata->internal_irq;
1988
1989         enable_irq(hdata->curr_irq);
1990
1991         /* turn HDMI power on */
1992         regulator_bulk_enable(res->regul_count, res->regul_bulk);
1993
1994         /* power-on hdmi clocks */
1995         clk_enable(res->hdmiphy);
1996
1997         hdmiphy_s_power(hdata->hdmiphy_port, 1);
1998         hdmiphy_conf_reset(hdata);
1999         hdmi_conf_reset(hdata);
2000         hdmi_conf_init(hdata);
2001         if (!hdata->is_soc_exynos5)
2002                 hdmi_audio_init(hdata);
2003         hdmi_conf_apply(hdata);
2004 }
2005
2006 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
2007 {
2008         struct hdmi_resources *res = &hdata->res;
2009
2010         hdmi_cfg_hpd(hdata, true);
2011
2012         if (hdata->curr_irq == hdata->external_irq)
2013                 return;
2014
2015         disable_irq(hdata->curr_irq);
2016         hdata->curr_irq = hdata->external_irq;
2017
2018         enable_irq(hdata->curr_irq);
2019         hdata->is_hdmi_powered_on = false;
2020
2021         hdmiphy_s_power(hdata->hdmiphy_port, 0);
2022         hdmiphy_conf_reset(hdata);
2023
2024         /* power-off hdmi clocks */
2025         clk_disable(res->hdmiphy);
2026
2027         /* turn HDMI power off */
2028         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2029 }
2030
2031 static int hdmi_dpms(void *ctx, int mode)
2032 {
2033         struct hdmi_context *hdata = ctx;
2034
2035         DRM_DEBUG_KMS("[DPMS:%s]\n", drm_get_dpms_name(mode));
2036
2037         switch (mode) {
2038         case DRM_MODE_DPMS_ON:
2039                 if (!hdata->is_hdmi_powered_on)
2040                         hdmi_resource_poweron(hdata);
2041                 hdmi_enable_video(hdata);
2042                 break;
2043         case DRM_MODE_DPMS_STANDBY:
2044                 hdmi_disable_video(hdata);
2045                 break;
2046         case DRM_MODE_DPMS_OFF:
2047         case DRM_MODE_DPMS_SUSPEND:
2048                 if (hdata->is_hdmi_powered_on)
2049                         hdmi_resource_poweroff(hdata);
2050                 break;
2051         default:
2052                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2053                 break;
2054         }
2055
2056         return 0;
2057 }
2058
2059 static int hdmi_subdrv_probe(void *ctx, struct drm_device *drm_dev)
2060 {
2061         struct hdmi_context *hdata = ctx;
2062
2063         DRM_DEBUG_KMS("[DEV:%s]\n", drm_dev->devname);
2064
2065         hdata->drm_dev = drm_dev;
2066
2067         return 0;
2068 }
2069
2070 static struct exynos_panel_ops hdmi_ops = {
2071         /* display */
2072         .subdrv_probe   = hdmi_subdrv_probe,
2073         .is_connected   = hdmi_is_connected,
2074         .get_edid       = hdmi_get_edid,
2075         .check_timing   = hdmi_check_timing,
2076         .dpms           = hdmi_dpms,
2077
2078         /* manager */
2079         .mode_fixup     = hdmi_mode_fixup,
2080         .mode_set       = hdmi_mode_set,
2081 };
2082
2083 /*
2084  * Handle hotplug events outside the interrupt handler proper.
2085  */
2086 static void hdmi_hotplug_func(struct work_struct *work)
2087 {
2088         struct hdmi_context *hdata =
2089                 container_of(work, struct hdmi_context, hotplug_work);
2090
2091         drm_helper_hpd_irq_event(hdata->drm_dev);
2092 }
2093
2094 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
2095 {
2096         struct hdmi_context *hdata = arg;
2097         u32 intc_flag;
2098         if (hdata->is_hdmi_powered_on) {
2099                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
2100                 /* clearing flags for HPD plug/unplug */
2101                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
2102                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
2103                                 hdata->hpd_handle);
2104                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2105                                 HDMI_INTC_FLAG_HPD_UNPLUG);
2106                 }
2107                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
2108                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
2109                                 hdata->hpd_handle);
2110                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2111                                 HDMI_INTC_FLAG_HPD_PLUG);
2112                 }
2113         }
2114
2115         if (hdata->drm_dev && hdata->hpd_handle)
2116                 queue_work(hdata->wq, &hdata->hotplug_work);
2117
2118         return IRQ_HANDLED;
2119 }
2120
2121 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2122 {
2123         struct device *dev = hdata->dev;
2124         struct hdmi_resources *res = &hdata->res;
2125 #ifndef CONFIG_ARCH_EXYNOS5
2126         static char *supply[] = {
2127                 "hdmi-en",
2128                 "vdd",
2129                 "vdd_osc",
2130                 "vdd_pll",
2131         };
2132         int i, ret;
2133 #endif
2134
2135         DRM_DEBUG_KMS("HDMI resource init\n");
2136
2137         memset(res, 0, sizeof *res);
2138
2139         /* get clocks, power */
2140         res->hdmi = clk_get(dev, "hdmi");
2141         if (IS_ERR_OR_NULL(res->hdmi)) {
2142                 DRM_ERROR("failed to get clock 'hdmi'\n");
2143                 goto fail;
2144         }
2145         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
2146         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
2147                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2148                 goto fail;
2149         }
2150         res->sclk_pixel = clk_get(dev, "sclk_pixel");
2151         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
2152                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2153                 goto fail;
2154         }
2155         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
2156         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
2157                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2158                 goto fail;
2159         }
2160         res->hdmiphy = clk_get(dev, "hdmiphy");
2161         if (IS_ERR_OR_NULL(res->hdmiphy)) {
2162                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2163                 goto fail;
2164         }
2165
2166         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2167
2168 #ifndef CONFIG_ARCH_EXYNOS5
2169         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2170                 sizeof res->regul_bulk[0], GFP_KERNEL);
2171         if (!res->regul_bulk) {
2172                 DRM_ERROR("failed to get memory for regulators\n");
2173                 goto fail;
2174         }
2175         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2176                 res->regul_bulk[i].supply = supply[i];
2177                 res->regul_bulk[i].consumer = NULL;
2178         }
2179         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2180         if (ret) {
2181                 DRM_ERROR("failed to get regulators\n");
2182                 goto fail;
2183         }
2184         res->regul_count = ARRAY_SIZE(supply);
2185 #endif
2186         /* TODO:
2187          * These clocks also should be added in
2188          * runtime resume and runtime suspend
2189          */
2190         clk_enable(res->hdmi);
2191         clk_enable(res->sclk_hdmi);
2192
2193         return 0;
2194 fail:
2195         DRM_ERROR("HDMI resource init - failed\n");
2196         return -ENODEV;
2197 }
2198
2199 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2200 {
2201         struct hdmi_resources *res = &hdata->res;
2202
2203         regulator_bulk_free(res->regul_count, res->regul_bulk);
2204         /* kfree is NULL-safe */
2205         kfree(res->regul_bulk);
2206         if (!IS_ERR_OR_NULL(res->hdmiphy))
2207                 clk_put(res->hdmiphy);
2208         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
2209                 clk_put(res->sclk_hdmiphy);
2210         if (!IS_ERR_OR_NULL(res->sclk_pixel))
2211                 clk_put(res->sclk_pixel);
2212         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
2213                 clk_put(res->sclk_hdmi);
2214         if (!IS_ERR_OR_NULL(res->hdmi))
2215                 clk_put(res->hdmi);
2216         memset(res, 0, sizeof *res);
2217
2218         return 0;
2219 }
2220
2221 struct platform_device *hdmi_audio_device;
2222
2223 int hdmi_register_audio_device(struct platform_device *pdev)
2224 {
2225         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2226         struct platform_device *audio_dev;
2227         int ret;
2228
2229         DRM_DEBUG_KMS("[PDEV:%s]\n", pdev->name);
2230
2231         audio_dev = platform_device_alloc("exynos-hdmi-audio", -1);
2232         if (!audio_dev) {
2233                 DRM_ERROR("hdmi audio device allocation failed.\n");
2234                 ret = -ENOMEM;
2235                 goto err;
2236         }
2237
2238         ret = platform_device_add_resources(audio_dev, pdev->resource,
2239                         pdev->num_resources);
2240         if (ret) {
2241                 ret = -ENOMEM;
2242                 goto err_device;
2243         }
2244
2245         audio_dev->dev.of_node = of_get_next_child(pdev->dev.of_node, NULL);
2246         audio_dev->dev.platform_data = (void *)hdata->hpd_gpio;
2247
2248         ret = platform_device_add(audio_dev);
2249         if (ret) {
2250                 DRM_ERROR("hdmi audio device add failed.\n");
2251                 goto err_device;
2252         }
2253
2254         hdmi_audio_device = audio_dev;
2255         return 0;
2256
2257 err_device:
2258         platform_device_put(audio_dev);
2259
2260 err:
2261         return ret;
2262 }
2263
2264 void hdmi_unregister_audio_device(void)
2265 {
2266         DRM_DEBUG_KMS("\n");
2267         platform_device_unregister(hdmi_audio_device);
2268 }
2269
2270 static int __devinit hdmi_probe(struct platform_device *pdev)
2271 {
2272         struct device *dev = &pdev->dev;
2273         struct hdmi_context *hdata;
2274         struct exynos_drm_hdmi_pdata *pdata;
2275         struct resource *res;
2276         struct device_node *ddc_node, *phy_node;
2277         int ret;
2278         enum of_gpio_flags flags;
2279
2280         DRM_DEBUG_KMS("[PDEV:%s]\n", pdev->name);
2281
2282         pdata = pdev->dev.platform_data;
2283         if (!pdata) {
2284                 DRM_ERROR("no platform data specified\n");
2285                 return -EINVAL;
2286         }
2287
2288         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2289         if (!hdata) {
2290                 DRM_ERROR("out of memory\n");
2291                 return -ENOMEM;
2292         }
2293
2294         platform_set_drvdata(pdev, hdata);
2295
2296         hdata->is_v13 = pdata->is_v13;
2297         hdata->default_win = pdata->default_win;
2298         hdata->default_timing = &pdata->timing;
2299         hdata->default_bpp = pdata->bpp;
2300         hdata->dev = dev;
2301         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2302                 "samsung,exynos5-hdmi");
2303
2304         ret = hdmi_resources_init(hdata);
2305         if (ret) {
2306                 ret = -EINVAL;
2307                 goto err_data;
2308         }
2309
2310         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2311         if (!res) {
2312                 DRM_ERROR("failed to find registers\n");
2313                 ret = -ENOENT;
2314                 goto err_resource;
2315         }
2316
2317         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2318                                            dev_name(dev));
2319         if (!hdata->regs_res) {
2320                 DRM_ERROR("failed to claim register region\n");
2321                 ret = -ENOENT;
2322                 goto err_resource;
2323         }
2324
2325         hdata->regs = ioremap(res->start, resource_size(res));
2326         if (!hdata->regs) {
2327                 DRM_ERROR("failed to map registers\n");
2328                 ret = -ENXIO;
2329                 goto err_req_region;
2330         }
2331
2332         /* DDC i2c driver */
2333         ddc_node = of_find_node_by_name(NULL, "exynos_ddc");
2334         if (!ddc_node) {
2335                 DRM_ERROR("Failed to find ddc node in device tree\n");
2336                 ret = -ENODEV;
2337                 goto err_iomap;
2338         }
2339         hdata->ddc_port = of_find_i2c_device_by_node(ddc_node);
2340         if (!hdata->ddc_port) {
2341                 DRM_ERROR("Failed to get ddc i2c client by node\n");
2342                 ret = -ENODEV;
2343                 goto err_iomap;
2344         }
2345
2346         /* hdmiphy i2c driver */
2347         phy_node = of_find_node_by_name(NULL, "exynos_hdmiphy");
2348         if (!phy_node) {
2349                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2350                 ret = -ENODEV;
2351                 goto err_ddc;
2352         }
2353         hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2354         if (!hdata->hdmiphy_port) {
2355                 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2356                 ret = -ENODEV;
2357                 goto err_ddc;
2358         }
2359
2360         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2361         if (res == NULL) {
2362                 DRM_ERROR("get interrupt resource failed.\n");
2363                 ret = -ENXIO;
2364                 goto err_hdmiphy;
2365         }
2366
2367         hdata->internal_irq = res->start;
2368
2369         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2370                                 "hpd-gpio", 0, &flags);
2371
2372         if (!gpio_is_valid(hdata->hpd_gpio)) {
2373                 DRM_ERROR("failed to get hpd gpio.");
2374                 ret = -EINVAL;
2375                 goto err_hdmiphy;
2376         }
2377
2378         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2379
2380         /* create workqueue and hotplug work */
2381         hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2382                         WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2383         if (hdata->wq == NULL) {
2384                 DRM_ERROR("Failed to create workqueue.\n");
2385                 ret = -ENOMEM;
2386                 goto err_hdmiphy;
2387         }
2388         INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2389
2390         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2391                         IRQF_SHARED, "int_hdmi", hdata);
2392         if (ret) {
2393                 DRM_ERROR("request int interrupt failed.\n");
2394                 goto err_workqueue;
2395         }
2396         disable_irq(hdata->internal_irq);
2397
2398         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2399                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2400                 hdata);
2401         if (ret) {
2402                 DRM_ERROR("request ext interrupt failed.\n");
2403                 goto err_int_irq;
2404         }
2405         disable_irq(hdata->external_irq);
2406
2407         if (of_device_is_compatible(dev->of_node,
2408                 "samsung,exynos5-hdmi")) {
2409                 ret = hdmi_register_audio_device(pdev);
2410                 if (ret) {
2411                         DRM_ERROR("hdmi-audio device registering failed.\n");
2412                         goto err_ext_irq;
2413                 }
2414         }
2415
2416         hdmi_resource_poweron(hdata);
2417
2418         if (!hdmi_is_connected(hdata)) {
2419                 hdmi_resource_poweroff(hdata);
2420                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2421         }
2422
2423         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_MIXER, &hdmi_ops,
2424                         hdata);
2425
2426         return 0;
2427
2428 err_ext_irq:
2429         free_irq(hdata->external_irq, hdata);
2430 err_int_irq:
2431         free_irq(hdata->internal_irq, hdata);
2432  err_workqueue:
2433         destroy_workqueue(hdata->wq);
2434 err_hdmiphy:
2435         put_device(&hdata->hdmiphy_port->dev);
2436 err_ddc:
2437         put_device(&hdata->ddc_port->dev);
2438 err_iomap:
2439         iounmap(hdata->regs);
2440 err_req_region:
2441         release_mem_region(hdata->regs_res->start,
2442                         resource_size(hdata->regs_res));
2443 err_resource:
2444         hdmi_resources_cleanup(hdata);
2445 err_data:
2446         kfree(hdata);
2447         return ret;
2448 }
2449
2450 static int __devexit hdmi_remove(struct platform_device *pdev)
2451 {
2452         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2453         struct hdmi_resources *res = &hdata->res;
2454
2455         DRM_DEBUG_KMS("[PDEV:%s]\n", pdev->name);
2456
2457         hdmi_resource_poweroff(hdata);
2458
2459         hdmi_unregister_audio_device();
2460
2461         disable_irq(hdata->curr_irq);
2462         free_irq(hdata->internal_irq, hdata);
2463         free_irq(hdata->external_irq, hdata);
2464
2465         cancel_work_sync(&hdata->hotplug_work);
2466         destroy_workqueue(hdata->wq);
2467
2468         clk_disable(res->hdmi);
2469         clk_disable(res->sclk_hdmi);
2470         hdmi_resources_cleanup(hdata);
2471
2472         iounmap(hdata->regs);
2473
2474         release_mem_region(hdata->regs_res->start,
2475                         resource_size(hdata->regs_res));
2476
2477         put_device(&hdata->hdmiphy_port->dev);
2478         put_device(&hdata->ddc_port->dev);
2479
2480         kfree(hdata);
2481
2482         return 0;
2483 }
2484
2485 struct platform_driver hdmi_driver = {
2486         .probe          = hdmi_probe,
2487         .remove         = __devexit_p(hdmi_remove),
2488         .driver         = {
2489 #ifdef CONFIG_ARCH_EXYNOS5
2490                 .name   = "exynos5-hdmi",
2491 #else
2492                 .name   = "exynos4-hdmi",
2493 #endif
2494                 .owner  = THIS_MODULE,
2495         },
2496 };