2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
8 * Based on drivers/media/video/s5p-tv/mixer_reg.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
19 #include "regs-mixer.h"
22 #include <linux/kernel.h>
23 #include <linux/spinlock.h>
24 #include <linux/wait.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/clk.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/of_device.h>
35 #include <linux/component.h>
37 #include <drm/exynos_drm.h>
39 #include "exynos_drm_drv.h"
40 #include "exynos_drm_crtc.h"
41 #include "exynos_drm_fb.h"
42 #include "exynos_drm_plane.h"
43 #include "exynos_drm_iommu.h"
45 #define MIXER_WIN_NR 3
46 #define VP_DEFAULT_WIN 2
48 /* The pixelformats that are natively supported by the mixer. */
49 #define MXR_FORMAT_RGB565 4
50 #define MXR_FORMAT_ARGB1555 5
51 #define MXR_FORMAT_ARGB4444 6
52 #define MXR_FORMAT_ARGB8888 7
54 struct mixer_resources {
56 void __iomem *mixer_regs;
57 void __iomem *vp_regs;
62 struct clk *sclk_mixer;
63 struct clk *sclk_hdmi;
64 struct clk *mout_mixer;
67 enum mixer_version_id {
73 enum mixer_flag_bits {
78 static const uint32_t mixer_formats[] = {
88 static const uint32_t vp_formats[] = {
93 struct mixer_context {
94 struct platform_device *pdev;
96 struct drm_device *drm_dev;
97 struct exynos_drm_crtc *crtc;
98 struct exynos_drm_plane planes[MIXER_WIN_NR];
105 struct mixer_resources mixer_res;
106 enum mixer_version_id mxr_ver;
109 struct mixer_drv_data {
110 enum mixer_version_id version;
115 static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
118 .type = DRM_PLANE_TYPE_PRIMARY,
119 .pixel_formats = mixer_formats,
120 .num_pixel_formats = ARRAY_SIZE(mixer_formats),
121 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
122 EXYNOS_DRM_PLANE_CAP_ZPOS,
125 .type = DRM_PLANE_TYPE_CURSOR,
126 .pixel_formats = mixer_formats,
127 .num_pixel_formats = ARRAY_SIZE(mixer_formats),
128 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
129 EXYNOS_DRM_PLANE_CAP_ZPOS,
132 .type = DRM_PLANE_TYPE_OVERLAY,
133 .pixel_formats = vp_formats,
134 .num_pixel_formats = ARRAY_SIZE(vp_formats),
135 .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
136 EXYNOS_DRM_PLANE_CAP_ZPOS,
140 static const u8 filter_y_horiz_tap8[] = {
141 0, -1, -1, -1, -1, -1, -1, -1,
142 -1, -1, -1, -1, -1, 0, 0, 0,
143 0, 2, 4, 5, 6, 6, 6, 6,
144 6, 5, 5, 4, 3, 2, 1, 1,
145 0, -6, -12, -16, -18, -20, -21, -20,
146 -20, -18, -16, -13, -10, -8, -5, -2,
147 127, 126, 125, 121, 114, 107, 99, 89,
148 79, 68, 57, 46, 35, 25, 16, 8,
151 static const u8 filter_y_vert_tap4[] = {
152 0, -3, -6, -8, -8, -8, -8, -7,
153 -6, -5, -4, -3, -2, -1, -1, 0,
154 127, 126, 124, 118, 111, 102, 92, 81,
155 70, 59, 48, 37, 27, 19, 11, 5,
156 0, 5, 11, 19, 27, 37, 48, 59,
157 70, 81, 92, 102, 111, 118, 124, 126,
158 0, 0, -1, -1, -2, -3, -4, -5,
159 -6, -7, -8, -8, -8, -8, -6, -3,
162 static const u8 filter_cr_horiz_tap4[] = {
163 0, -3, -6, -8, -8, -8, -8, -7,
164 -6, -5, -4, -3, -2, -1, -1, 0,
165 127, 126, 124, 118, 111, 102, 92, 81,
166 70, 59, 48, 37, 27, 19, 11, 5,
169 static inline bool is_alpha_format(unsigned int pixel_format)
171 switch (pixel_format) {
172 case DRM_FORMAT_ARGB8888:
173 case DRM_FORMAT_ARGB1555:
174 case DRM_FORMAT_ARGB4444:
181 static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
183 return readl(res->vp_regs + reg_id);
186 static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
189 writel(val, res->vp_regs + reg_id);
192 static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
195 u32 old = vp_reg_read(res, reg_id);
197 val = (val & mask) | (old & ~mask);
198 writel(val, res->vp_regs + reg_id);
201 static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
203 return readl(res->mixer_regs + reg_id);
206 static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
209 writel(val, res->mixer_regs + reg_id);
212 static inline void mixer_reg_writemask(struct mixer_resources *res,
213 u32 reg_id, u32 val, u32 mask)
215 u32 old = mixer_reg_read(res, reg_id);
217 val = (val & mask) | (old & ~mask);
218 writel(val, res->mixer_regs + reg_id);
221 static void mixer_regs_dump(struct mixer_context *ctx)
223 #define DUMPREG(reg_id) \
225 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
226 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
232 DUMPREG(MXR_INT_STATUS);
234 DUMPREG(MXR_LAYER_CFG);
235 DUMPREG(MXR_VIDEO_CFG);
237 DUMPREG(MXR_GRAPHIC0_CFG);
238 DUMPREG(MXR_GRAPHIC0_BASE);
239 DUMPREG(MXR_GRAPHIC0_SPAN);
240 DUMPREG(MXR_GRAPHIC0_WH);
241 DUMPREG(MXR_GRAPHIC0_SXY);
242 DUMPREG(MXR_GRAPHIC0_DXY);
244 DUMPREG(MXR_GRAPHIC1_CFG);
245 DUMPREG(MXR_GRAPHIC1_BASE);
246 DUMPREG(MXR_GRAPHIC1_SPAN);
247 DUMPREG(MXR_GRAPHIC1_WH);
248 DUMPREG(MXR_GRAPHIC1_SXY);
249 DUMPREG(MXR_GRAPHIC1_DXY);
253 static void vp_regs_dump(struct mixer_context *ctx)
255 #define DUMPREG(reg_id) \
257 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
258 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
263 DUMPREG(VP_SHADOW_UPDATE);
264 DUMPREG(VP_FIELD_ID);
266 DUMPREG(VP_IMG_SIZE_Y);
267 DUMPREG(VP_IMG_SIZE_C);
268 DUMPREG(VP_PER_RATE_CTRL);
269 DUMPREG(VP_TOP_Y_PTR);
270 DUMPREG(VP_BOT_Y_PTR);
271 DUMPREG(VP_TOP_C_PTR);
272 DUMPREG(VP_BOT_C_PTR);
273 DUMPREG(VP_ENDIAN_MODE);
274 DUMPREG(VP_SRC_H_POSITION);
275 DUMPREG(VP_SRC_V_POSITION);
276 DUMPREG(VP_SRC_WIDTH);
277 DUMPREG(VP_SRC_HEIGHT);
278 DUMPREG(VP_DST_H_POSITION);
279 DUMPREG(VP_DST_V_POSITION);
280 DUMPREG(VP_DST_WIDTH);
281 DUMPREG(VP_DST_HEIGHT);
288 static inline void vp_filter_set(struct mixer_resources *res,
289 int reg_id, const u8 *data, unsigned int size)
291 /* assure 4-byte align */
293 for (; size; size -= 4, reg_id += 4, data += 4) {
294 u32 val = (data[0] << 24) | (data[1] << 16) |
295 (data[2] << 8) | data[3];
296 vp_reg_write(res, reg_id, val);
300 static void vp_default_filter(struct mixer_resources *res)
302 vp_filter_set(res, VP_POLY8_Y0_LL,
303 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
304 vp_filter_set(res, VP_POLY4_Y0_LL,
305 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
306 vp_filter_set(res, VP_POLY4_C0_LL,
307 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
310 static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
313 struct mixer_resources *res = &ctx->mixer_res;
316 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
318 /* blending based on pixel alpha */
319 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
320 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
322 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
323 val, MXR_GRP_CFG_MISC_MASK);
326 static void mixer_cfg_vp_blend(struct mixer_context *ctx)
328 struct mixer_resources *res = &ctx->mixer_res;
332 * No blending at the moment since the NV12/NV21 pixelformats don't
333 * have an alpha channel. However the mixer supports a global alpha
334 * value for a layer. Once this functionality is exposed, we can
335 * support blending of the video layer through this.
338 mixer_reg_write(res, MXR_VIDEO_CFG, val);
341 static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
343 struct mixer_resources *res = &ctx->mixer_res;
345 /* block update on vsync */
346 mixer_reg_writemask(res, MXR_STATUS, enable ?
347 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
350 vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
351 VP_SHADOW_UPDATE_ENABLE : 0);
354 static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
356 struct mixer_resources *res = &ctx->mixer_res;
359 /* choosing between interlace and progressive mode */
360 val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
361 MXR_CFG_SCAN_PROGRESSIVE);
363 if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
364 /* choosing between proper HD and SD mode */
366 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
367 else if (height <= 576)
368 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
369 else if (height <= 720)
370 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
371 else if (height <= 1080)
372 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
374 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
377 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
380 static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
382 struct mixer_resources *res = &ctx->mixer_res;
386 val = MXR_CFG_RGB601_0_255;
387 } else if (height == 576) {
388 val = MXR_CFG_RGB601_0_255;
389 } else if (height == 720) {
390 val = MXR_CFG_RGB709_16_235;
391 mixer_reg_write(res, MXR_CM_COEFF_Y,
392 (1 << 30) | (94 << 20) | (314 << 10) |
394 mixer_reg_write(res, MXR_CM_COEFF_CB,
395 (972 << 20) | (851 << 10) | (225 << 0));
396 mixer_reg_write(res, MXR_CM_COEFF_CR,
397 (225 << 20) | (820 << 10) | (1004 << 0));
398 } else if (height == 1080) {
399 val = MXR_CFG_RGB709_16_235;
400 mixer_reg_write(res, MXR_CM_COEFF_Y,
401 (1 << 30) | (94 << 20) | (314 << 10) |
403 mixer_reg_write(res, MXR_CM_COEFF_CB,
404 (972 << 20) | (851 << 10) | (225 << 0));
405 mixer_reg_write(res, MXR_CM_COEFF_CR,
406 (225 << 20) | (820 << 10) | (1004 << 0));
408 val = MXR_CFG_RGB709_16_235;
409 mixer_reg_write(res, MXR_CM_COEFF_Y,
410 (1 << 30) | (94 << 20) | (314 << 10) |
412 mixer_reg_write(res, MXR_CM_COEFF_CB,
413 (972 << 20) | (851 << 10) | (225 << 0));
414 mixer_reg_write(res, MXR_CM_COEFF_CR,
415 (225 << 20) | (820 << 10) | (1004 << 0));
418 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
421 static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
422 unsigned int priority, bool enable)
424 struct mixer_resources *res = &ctx->mixer_res;
425 u32 val = enable ? ~0 : 0;
429 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
430 mixer_reg_writemask(res, MXR_LAYER_CFG,
431 MXR_LAYER_CFG_GRP0_VAL(priority),
432 MXR_LAYER_CFG_GRP0_MASK);
435 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
436 mixer_reg_writemask(res, MXR_LAYER_CFG,
437 MXR_LAYER_CFG_GRP1_VAL(priority),
438 MXR_LAYER_CFG_GRP1_MASK);
441 if (ctx->vp_enabled) {
442 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
443 mixer_reg_writemask(res, MXR_CFG, val,
445 mixer_reg_writemask(res, MXR_LAYER_CFG,
446 MXR_LAYER_CFG_VP_VAL(priority),
447 MXR_LAYER_CFG_VP_MASK);
453 static void mixer_run(struct mixer_context *ctx)
455 struct mixer_resources *res = &ctx->mixer_res;
457 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
460 static void mixer_stop(struct mixer_context *ctx)
462 struct mixer_resources *res = &ctx->mixer_res;
465 mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
467 while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
469 usleep_range(10000, 12000);
472 static void vp_video_buffer(struct mixer_context *ctx,
473 struct exynos_drm_plane *plane)
475 struct exynos_drm_plane_state *state =
476 to_exynos_plane_state(plane->base.state);
477 struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
478 struct mixer_resources *res = &ctx->mixer_res;
479 struct drm_framebuffer *fb = state->base.fb;
481 dma_addr_t luma_addr[2], chroma_addr[2];
482 bool tiled_mode = false;
483 bool crcb_mode = false;
486 switch (fb->pixel_format) {
487 case DRM_FORMAT_NV12:
490 case DRM_FORMAT_NV21:
494 DRM_ERROR("pixel format for vp is wrong [%d].\n",
499 luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
500 chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
502 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
503 ctx->interlace = true;
505 luma_addr[1] = luma_addr[0] + 0x40;
506 chroma_addr[1] = chroma_addr[0] + 0x40;
508 luma_addr[1] = luma_addr[0] + fb->pitches[0];
509 chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
512 ctx->interlace = false;
517 spin_lock_irqsave(&res->reg_slock, flags);
519 /* interlace or progressive scan mode */
520 val = (ctx->interlace ? ~0 : 0);
521 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
524 val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
525 val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
526 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
528 /* setting size of input image */
529 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
530 VP_IMG_VSIZE(fb->height));
531 /* chroma height has to reduced by 2 to avoid chroma distorions */
532 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
533 VP_IMG_VSIZE(fb->height / 2));
535 vp_reg_write(res, VP_SRC_WIDTH, state->src.w);
536 vp_reg_write(res, VP_SRC_HEIGHT, state->src.h);
537 vp_reg_write(res, VP_SRC_H_POSITION,
538 VP_SRC_H_POSITION_VAL(state->src.x));
539 vp_reg_write(res, VP_SRC_V_POSITION, state->src.y);
541 vp_reg_write(res, VP_DST_WIDTH, state->crtc.w);
542 vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x);
543 if (ctx->interlace) {
544 vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2);
545 vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2);
547 vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h);
548 vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y);
551 vp_reg_write(res, VP_H_RATIO, state->h_ratio);
552 vp_reg_write(res, VP_V_RATIO, state->v_ratio);
554 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
556 /* set buffer address to vp */
557 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
558 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
559 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
560 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
562 mixer_cfg_scan(ctx, mode->vdisplay);
563 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
564 mixer_cfg_layer(ctx, plane->index, state->zpos + 1, true);
565 mixer_cfg_vp_blend(ctx);
568 spin_unlock_irqrestore(&res->reg_slock, flags);
570 mixer_regs_dump(ctx);
574 static void mixer_layer_update(struct mixer_context *ctx)
576 struct mixer_resources *res = &ctx->mixer_res;
578 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
581 static void mixer_graph_buffer(struct mixer_context *ctx,
582 struct exynos_drm_plane *plane)
584 struct exynos_drm_plane_state *state =
585 to_exynos_plane_state(plane->base.state);
586 struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
587 struct mixer_resources *res = &ctx->mixer_res;
588 struct drm_framebuffer *fb = state->base.fb;
590 unsigned int win = plane->index;
591 unsigned int x_ratio = 0, y_ratio = 0;
592 unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
597 switch (fb->pixel_format) {
598 case DRM_FORMAT_XRGB4444:
599 case DRM_FORMAT_ARGB4444:
600 fmt = MXR_FORMAT_ARGB4444;
603 case DRM_FORMAT_XRGB1555:
604 case DRM_FORMAT_ARGB1555:
605 fmt = MXR_FORMAT_ARGB1555;
608 case DRM_FORMAT_RGB565:
609 fmt = MXR_FORMAT_RGB565;
612 case DRM_FORMAT_XRGB8888:
613 case DRM_FORMAT_ARGB8888:
614 fmt = MXR_FORMAT_ARGB8888;
618 DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
622 /* ratio is already checked by common plane code */
623 x_ratio = state->h_ratio == (1 << 15);
624 y_ratio = state->v_ratio == (1 << 15);
626 dst_x_offset = state->crtc.x;
627 dst_y_offset = state->crtc.y;
629 /* converting dma address base and source offset */
630 dma_addr = exynos_drm_fb_dma_addr(fb, 0)
631 + (state->src.x * fb->bits_per_pixel >> 3)
632 + (state->src.y * fb->pitches[0]);
636 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
637 ctx->interlace = true;
639 ctx->interlace = false;
641 spin_lock_irqsave(&res->reg_slock, flags);
644 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
645 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
648 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
649 fb->pitches[0] / (fb->bits_per_pixel >> 3));
651 /* setup display size */
652 if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
653 win == DEFAULT_WIN) {
654 val = MXR_MXR_RES_HEIGHT(mode->vdisplay);
655 val |= MXR_MXR_RES_WIDTH(mode->hdisplay);
656 mixer_reg_write(res, MXR_RESOLUTION, val);
659 val = MXR_GRP_WH_WIDTH(state->src.w);
660 val |= MXR_GRP_WH_HEIGHT(state->src.h);
661 val |= MXR_GRP_WH_H_SCALE(x_ratio);
662 val |= MXR_GRP_WH_V_SCALE(y_ratio);
663 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
665 /* setup offsets in source image */
666 val = MXR_GRP_SXY_SX(src_x_offset);
667 val |= MXR_GRP_SXY_SY(src_y_offset);
668 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);
670 /* setup offsets in display image */
671 val = MXR_GRP_DXY_DX(dst_x_offset);
672 val |= MXR_GRP_DXY_DY(dst_y_offset);
673 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
675 /* set buffer address to mixer */
676 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
678 mixer_cfg_scan(ctx, mode->vdisplay);
679 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
680 mixer_cfg_layer(ctx, win, state->zpos + 1, true);
681 mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->pixel_format));
683 /* layer update mandatory for mixer 16.0.33.0 */
684 if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
685 ctx->mxr_ver == MXR_VER_128_0_0_184)
686 mixer_layer_update(ctx);
690 spin_unlock_irqrestore(&res->reg_slock, flags);
692 mixer_regs_dump(ctx);
695 static void vp_win_reset(struct mixer_context *ctx)
697 struct mixer_resources *res = &ctx->mixer_res;
700 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
701 for (tries = 100; tries; --tries) {
702 /* waiting until VP_SRESET_PROCESSING is 0 */
703 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
707 WARN(tries == 0, "failed to reset Video Processor\n");
710 static void mixer_win_reset(struct mixer_context *ctx)
712 struct mixer_resources *res = &ctx->mixer_res;
715 spin_lock_irqsave(&res->reg_slock, flags);
717 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
719 /* set output in RGB888 mode */
720 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
722 /* 16 beat burst in DMA */
723 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
724 MXR_STATUS_BURST_MASK);
726 /* reset default layer priority */
727 mixer_reg_write(res, MXR_LAYER_CFG, 0);
729 /* setting background color */
730 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
731 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
732 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
734 if (ctx->vp_enabled) {
735 /* configuration of Video Processor Registers */
737 vp_default_filter(res);
740 /* disable all layers */
741 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
742 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
744 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
746 spin_unlock_irqrestore(&res->reg_slock, flags);
749 static irqreturn_t mixer_irq_handler(int irq, void *arg)
751 struct mixer_context *ctx = arg;
752 struct mixer_resources *res = &ctx->mixer_res;
753 u32 val, base, shadow;
756 spin_lock(&res->reg_slock);
758 /* read interrupt status for handling and clearing flags for VSYNC */
759 val = mixer_reg_read(res, MXR_INT_STATUS);
762 if (val & MXR_INT_STATUS_VSYNC) {
763 /* vsync interrupt use different bit for read and clear */
764 val |= MXR_INT_CLEAR_VSYNC;
765 val &= ~MXR_INT_STATUS_VSYNC;
767 /* interlace scan need to check shadow register */
768 if (ctx->interlace) {
769 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
770 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
774 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
775 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
780 drm_crtc_handle_vblank(&ctx->crtc->base);
781 for (win = 0 ; win < MIXER_WIN_NR ; win++) {
782 struct exynos_drm_plane *plane = &ctx->planes[win];
784 if (!plane->pending_fb)
787 exynos_drm_crtc_finish_update(ctx->crtc, plane);
792 /* clear interrupts */
793 mixer_reg_write(res, MXR_INT_STATUS, val);
795 spin_unlock(&res->reg_slock);
800 static int mixer_resources_init(struct mixer_context *mixer_ctx)
802 struct device *dev = &mixer_ctx->pdev->dev;
803 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
804 struct resource *res;
807 spin_lock_init(&mixer_res->reg_slock);
809 mixer_res->mixer = devm_clk_get(dev, "mixer");
810 if (IS_ERR(mixer_res->mixer)) {
811 dev_err(dev, "failed to get clock 'mixer'\n");
815 mixer_res->hdmi = devm_clk_get(dev, "hdmi");
816 if (IS_ERR(mixer_res->hdmi)) {
817 dev_err(dev, "failed to get clock 'hdmi'\n");
818 return PTR_ERR(mixer_res->hdmi);
821 mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
822 if (IS_ERR(mixer_res->sclk_hdmi)) {
823 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
826 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);
828 dev_err(dev, "get memory resource failed.\n");
832 mixer_res->mixer_regs = devm_ioremap(dev, res->start,
834 if (mixer_res->mixer_regs == NULL) {
835 dev_err(dev, "register mapping failed.\n");
839 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);
841 dev_err(dev, "get interrupt resource failed.\n");
845 ret = devm_request_irq(dev, res->start, mixer_irq_handler,
846 0, "drm_mixer", mixer_ctx);
848 dev_err(dev, "request interrupt failed.\n");
851 mixer_res->irq = res->start;
856 static int vp_resources_init(struct mixer_context *mixer_ctx)
858 struct device *dev = &mixer_ctx->pdev->dev;
859 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
860 struct resource *res;
862 mixer_res->vp = devm_clk_get(dev, "vp");
863 if (IS_ERR(mixer_res->vp)) {
864 dev_err(dev, "failed to get clock 'vp'\n");
868 if (mixer_ctx->has_sclk) {
869 mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
870 if (IS_ERR(mixer_res->sclk_mixer)) {
871 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
874 mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer");
875 if (IS_ERR(mixer_res->mout_mixer)) {
876 dev_err(dev, "failed to get clock 'mout_mixer'\n");
880 if (mixer_res->sclk_hdmi && mixer_res->mout_mixer)
881 clk_set_parent(mixer_res->mout_mixer,
882 mixer_res->sclk_hdmi);
885 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
887 dev_err(dev, "get memory resource failed.\n");
891 mixer_res->vp_regs = devm_ioremap(dev, res->start,
893 if (mixer_res->vp_regs == NULL) {
894 dev_err(dev, "register mapping failed.\n");
901 static int mixer_initialize(struct mixer_context *mixer_ctx,
902 struct drm_device *drm_dev)
905 struct exynos_drm_private *priv;
906 priv = drm_dev->dev_private;
908 mixer_ctx->drm_dev = drm_dev;
909 mixer_ctx->pipe = priv->pipe++;
911 /* acquire resources: regs, irqs, clocks */
912 ret = mixer_resources_init(mixer_ctx);
914 DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
918 if (mixer_ctx->vp_enabled) {
919 /* acquire vp resources: regs, irqs, clocks */
920 ret = vp_resources_init(mixer_ctx);
922 DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
927 ret = drm_iommu_attach_device(drm_dev, mixer_ctx->dev);
934 static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
936 drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
939 static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
941 struct mixer_context *mixer_ctx = crtc->ctx;
942 struct mixer_resources *res = &mixer_ctx->mixer_res;
944 __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
945 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
948 /* enable vsync interrupt */
949 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
950 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
955 static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
957 struct mixer_context *mixer_ctx = crtc->ctx;
958 struct mixer_resources *res = &mixer_ctx->mixer_res;
960 __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
962 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
965 /* disable vsync interrupt */
966 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
967 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
970 static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
972 struct mixer_context *mixer_ctx = crtc->ctx;
974 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
977 mixer_vsync_set_update(mixer_ctx, false);
980 static void mixer_update_plane(struct exynos_drm_crtc *crtc,
981 struct exynos_drm_plane *plane)
983 struct mixer_context *mixer_ctx = crtc->ctx;
985 DRM_DEBUG_KMS("win: %d\n", plane->index);
987 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
990 if (plane->index == VP_DEFAULT_WIN)
991 vp_video_buffer(mixer_ctx, plane);
993 mixer_graph_buffer(mixer_ctx, plane);
996 static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
997 struct exynos_drm_plane *plane)
999 struct mixer_context *mixer_ctx = crtc->ctx;
1000 struct mixer_resources *res = &mixer_ctx->mixer_res;
1001 unsigned long flags;
1003 DRM_DEBUG_KMS("win: %d\n", plane->index);
1005 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1008 spin_lock_irqsave(&res->reg_slock, flags);
1009 mixer_cfg_layer(mixer_ctx, plane->index, 0, false);
1010 spin_unlock_irqrestore(&res->reg_slock, flags);
1013 static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
1015 struct mixer_context *mixer_ctx = crtc->ctx;
1017 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1020 mixer_vsync_set_update(mixer_ctx, true);
1023 static void mixer_enable(struct exynos_drm_crtc *crtc)
1025 struct mixer_context *ctx = crtc->ctx;
1026 struct mixer_resources *res = &ctx->mixer_res;
1028 if (test_bit(MXR_BIT_POWERED, &ctx->flags))
1031 pm_runtime_get_sync(ctx->dev);
1033 exynos_drm_pipe_clk_enable(crtc, true);
1035 mixer_vsync_set_update(ctx, false);
1037 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1039 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
1040 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
1041 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
1043 mixer_win_reset(ctx);
1045 mixer_vsync_set_update(ctx, true);
1047 set_bit(MXR_BIT_POWERED, &ctx->flags);
1050 static void mixer_disable(struct exynos_drm_crtc *crtc)
1052 struct mixer_context *ctx = crtc->ctx;
1055 if (!test_bit(MXR_BIT_POWERED, &ctx->flags))
1059 mixer_regs_dump(ctx);
1061 for (i = 0; i < MIXER_WIN_NR; i++)
1062 mixer_disable_plane(crtc, &ctx->planes[i]);
1064 exynos_drm_pipe_clk_enable(crtc, false);
1066 pm_runtime_put(ctx->dev);
1068 clear_bit(MXR_BIT_POWERED, &ctx->flags);
1071 /* Only valid for Mixer version 16.0.33.0 */
1072 static int mixer_atomic_check(struct exynos_drm_crtc *crtc,
1073 struct drm_crtc_state *state)
1075 struct drm_display_mode *mode = &state->adjusted_mode;
1081 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
1082 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1083 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1085 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
1086 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
1087 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
1093 static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1094 .enable = mixer_enable,
1095 .disable = mixer_disable,
1096 .enable_vblank = mixer_enable_vblank,
1097 .disable_vblank = mixer_disable_vblank,
1098 .atomic_begin = mixer_atomic_begin,
1099 .update_plane = mixer_update_plane,
1100 .disable_plane = mixer_disable_plane,
1101 .atomic_flush = mixer_atomic_flush,
1102 .atomic_check = mixer_atomic_check,
1105 static struct mixer_drv_data exynos5420_mxr_drv_data = {
1106 .version = MXR_VER_128_0_0_184,
1110 static struct mixer_drv_data exynos5250_mxr_drv_data = {
1111 .version = MXR_VER_16_0_33_0,
1115 static struct mixer_drv_data exynos4212_mxr_drv_data = {
1116 .version = MXR_VER_0_0_0_16,
1120 static struct mixer_drv_data exynos4210_mxr_drv_data = {
1121 .version = MXR_VER_0_0_0_16,
1126 static struct of_device_id mixer_match_types[] = {
1128 .compatible = "samsung,exynos4210-mixer",
1129 .data = &exynos4210_mxr_drv_data,
1131 .compatible = "samsung,exynos4212-mixer",
1132 .data = &exynos4212_mxr_drv_data,
1134 .compatible = "samsung,exynos5-mixer",
1135 .data = &exynos5250_mxr_drv_data,
1137 .compatible = "samsung,exynos5250-mixer",
1138 .data = &exynos5250_mxr_drv_data,
1140 .compatible = "samsung,exynos5420-mixer",
1141 .data = &exynos5420_mxr_drv_data,
1146 MODULE_DEVICE_TABLE(of, mixer_match_types);
1148 static int mixer_bind(struct device *dev, struct device *manager, void *data)
1150 struct mixer_context *ctx = dev_get_drvdata(dev);
1151 struct drm_device *drm_dev = data;
1152 struct exynos_drm_plane *exynos_plane;
1156 ret = mixer_initialize(ctx, drm_dev);
1160 for (i = 0; i < MIXER_WIN_NR; i++) {
1161 if (i == VP_DEFAULT_WIN && !ctx->vp_enabled)
1164 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1165 1 << ctx->pipe, &plane_configs[i]);
1170 exynos_plane = &ctx->planes[DEFAULT_WIN];
1171 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1172 ctx->pipe, EXYNOS_DISPLAY_TYPE_HDMI,
1173 &mixer_crtc_ops, ctx);
1174 if (IS_ERR(ctx->crtc)) {
1175 mixer_ctx_remove(ctx);
1176 ret = PTR_ERR(ctx->crtc);
1183 devm_kfree(dev, ctx);
1187 static void mixer_unbind(struct device *dev, struct device *master, void *data)
1189 struct mixer_context *ctx = dev_get_drvdata(dev);
1191 mixer_ctx_remove(ctx);
1194 static const struct component_ops mixer_component_ops = {
1196 .unbind = mixer_unbind,
1199 static int mixer_probe(struct platform_device *pdev)
1201 struct device *dev = &pdev->dev;
1202 const struct mixer_drv_data *drv;
1203 struct mixer_context *ctx;
1206 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
1208 DRM_ERROR("failed to alloc mixer context.\n");
1212 drv = of_device_get_match_data(dev);
1216 ctx->vp_enabled = drv->is_vp_enabled;
1217 ctx->has_sclk = drv->has_sclk;
1218 ctx->mxr_ver = drv->version;
1220 platform_set_drvdata(pdev, ctx);
1222 ret = component_add(&pdev->dev, &mixer_component_ops);
1224 pm_runtime_enable(dev);
1229 static int mixer_remove(struct platform_device *pdev)
1231 pm_runtime_disable(&pdev->dev);
1233 component_del(&pdev->dev, &mixer_component_ops);
1238 static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1240 struct mixer_context *ctx = dev_get_drvdata(dev);
1241 struct mixer_resources *res = &ctx->mixer_res;
1243 clk_disable_unprepare(res->hdmi);
1244 clk_disable_unprepare(res->mixer);
1245 if (ctx->vp_enabled) {
1246 clk_disable_unprepare(res->vp);
1248 clk_disable_unprepare(res->sclk_mixer);
1254 static int __maybe_unused exynos_mixer_resume(struct device *dev)
1256 struct mixer_context *ctx = dev_get_drvdata(dev);
1257 struct mixer_resources *res = &ctx->mixer_res;
1260 ret = clk_prepare_enable(res->mixer);
1262 DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret);
1265 ret = clk_prepare_enable(res->hdmi);
1267 DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
1270 if (ctx->vp_enabled) {
1271 ret = clk_prepare_enable(res->vp);
1273 DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
1277 if (ctx->has_sclk) {
1278 ret = clk_prepare_enable(res->sclk_mixer);
1280 DRM_ERROR("Failed to prepare_enable the " \
1281 "sclk_mixer clk [%d]\n",
1291 static const struct dev_pm_ops exynos_mixer_pm_ops = {
1292 SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL)
1295 struct platform_driver mixer_driver = {
1297 .name = "exynos-mixer",
1298 .owner = THIS_MODULE,
1299 .pm = &exynos_mixer_pm_ops,
1300 .of_match_table = mixer_match_types,
1302 .probe = mixer_probe,
1303 .remove = mixer_remove,