drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static char get_active_flag(struct drm_i915_gem_object *obj)
  93 {
  94         return i915_gem_object_is_active(obj) ? '*' : ' ';
  95 }
  96
  97 static char get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         return obj->pin_display ? 'p' : ' ';
 100 }
 101
 102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
 103 {
 104         switch (i915_gem_object_get_tiling(obj)) {
 105         default:
 106         case I915_TILING_NONE: return ' ';
 107         case I915_TILING_X: return 'X';
 108         case I915_TILING_Y: return 'Y';
 109         }
 110 }
 111
 112 static char get_global_flag(struct drm_i915_gem_object *obj)
 113 {
 114         return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
 115 }
 116
 117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->mapping ? 'M' : ' ';
 120 }
 121
 122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 123 {
 124         u64 size = 0;
 125         struct i915_vma *vma;
 126
 127         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 128                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 129                         size += vma->node.size;
 130         }
 131
 132         return size;
 133 }
 134
 135 static void
 136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 137 {
 138         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 139         struct intel_engine_cs *engine;
 140         struct i915_vma *vma;
 141         unsigned int frontbuffer_bits;
 142         int pin_count = 0;
 143         enum intel_engine_id id;
 144
 145         lockdep_assert_held(&obj->base.dev->struct_mutex);
 146
 147         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 148                    &obj->base,
 149                    get_active_flag(obj),
 150                    get_pin_flag(obj),
 151                    get_tiling_flag(obj),
 152                    get_global_flag(obj),
 153                    get_pin_mapped_flag(obj),
 154                    obj->base.size / 1024,
 155                    obj->base.read_domains,
 156                    obj->base.write_domain);
 157         for_each_engine_id(engine, dev_priv, id)
 158                 seq_printf(m, "%x ",
 159                            i915_gem_active_get_seqno(&obj->last_read[id],
 160                                                      &obj->base.dev->struct_mutex));
 161         seq_printf(m, "] %x %x%s%s%s",
 162                    i915_gem_active_get_seqno(&obj->last_write,
 163                                              &obj->base.dev->struct_mutex),
 164                    i915_gem_active_get_seqno(&obj->last_fence,
 165                                              &obj->base.dev->struct_mutex),
 166                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 167                    obj->dirty ? " dirty" : "",
 168                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 169         if (obj->base.name)
 170                 seq_printf(m, " (name: %d)", obj->base.name);
 171         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 172                 if (i915_vma_is_pinned(vma))
 173                         pin_count++;
 174         }
 175         seq_printf(m, " (pinned x %d)", pin_count);
 176         if (obj->pin_display)
 177                 seq_printf(m, " (display)");
 178         if (obj->fence_reg != I915_FENCE_REG_NONE)
 179                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 180         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 181                 if (!drm_mm_node_allocated(&vma->node))
 182                         continue;
 183
 184                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 185                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 186                            vma->node.start, vma->node.size);
 187                 if (i915_vma_is_ggtt(vma))
 188                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 189                 seq_puts(m, ")");
 190         }
 191         if (obj->stolen)
 192                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 193         if (obj->pin_display || obj->fault_mappable) {
 194                 char s[3], *t = s;
 195                 if (obj->pin_display)
 196                         *t++ = 'p';
 197                 if (obj->fault_mappable)
 198                         *t++ = 'f';
 199                 *t = '\0';
 200                 seq_printf(m, " (%s mappable)", s);
 201         }
 202
 203         engine = i915_gem_active_get_engine(&obj->last_write,
 204                                             &obj->base.dev->struct_mutex);
 205         if (engine)
 206                 seq_printf(m, " (%s)", engine->name);
 207
 208         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 209         if (frontbuffer_bits)
 210                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 211 }
 212
 213 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 214 {
 215         struct drm_info_node *node = m->private;
 216         uintptr_t list = (uintptr_t) node->info_ent->data;
 217         struct list_head *head;
 218         struct drm_device *dev = node->minor->dev;
 219         struct drm_i915_private *dev_priv = to_i915(dev);
 220         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 221         struct i915_vma *vma;
 222         u64 total_obj_size, total_gtt_size;
 223         int count, ret;
 224
 225         ret = mutex_lock_interruptible(&dev->struct_mutex);
 226         if (ret)
 227                 return ret;
 228
 229         /* FIXME: the user of this interface might want more than just GGTT */
 230         switch (list) {
 231         case ACTIVE_LIST:
 232                 seq_puts(m, "Active:\n");
 233                 head = &ggtt->base.active_list;
 234                 break;
 235         case INACTIVE_LIST:
 236                 seq_puts(m, "Inactive:\n");
 237                 head = &ggtt->base.inactive_list;
 238                 break;
 239         default:
 240                 mutex_unlock(&dev->struct_mutex);
 241                 return -EINVAL;
 242         }
 243
 244         total_obj_size = total_gtt_size = count = 0;
 245         list_for_each_entry(vma, head, vm_link) {
 246                 seq_printf(m, "   ");
 247                 describe_obj(m, vma->obj);
 248                 seq_printf(m, "\n");
 249                 total_obj_size += vma->obj->base.size;
 250                 total_gtt_size += vma->node.size;
 251                 count++;
 252         }
 253         mutex_unlock(&dev->struct_mutex);
 254
 255         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 256                    count, total_obj_size, total_gtt_size);
 257         return 0;
 258 }
 259
 260 static int obj_rank_by_stolen(void *priv,
 261                               struct list_head *A, struct list_head *B)
 262 {
 263         struct drm_i915_gem_object *a =
 264                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 265         struct drm_i915_gem_object *b =
 266                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 267
 268         if (a->stolen->start < b->stolen->start)
 269                 return -1;
 270         if (a->stolen->start > b->stolen->start)
 271                 return 1;
 272         return 0;
 273 }
 274
 275 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 276 {
 277         struct drm_info_node *node = m->private;
 278         struct drm_device *dev = node->minor->dev;
 279         struct drm_i915_private *dev_priv = to_i915(dev);
 280         struct drm_i915_gem_object *obj;
 281         u64 total_obj_size, total_gtt_size;
 282         LIST_HEAD(stolen);
 283         int count, ret;
 284
 285         ret = mutex_lock_interruptible(&dev->struct_mutex);
 286         if (ret)
 287                 return ret;
 288
 289         total_obj_size = total_gtt_size = count = 0;
 290         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 291                 if (obj->stolen == NULL)
 292                         continue;
 293
 294                 list_add(&obj->obj_exec_link, &stolen);
 295
 296                 total_obj_size += obj->base.size;
 297                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 298                 count++;
 299         }
 300         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 301                 if (obj->stolen == NULL)
 302                         continue;
 303
 304                 list_add(&obj->obj_exec_link, &stolen);
 305
 306                 total_obj_size += obj->base.size;
 307                 count++;
 308         }
 309         list_sort(NULL, &stolen, obj_rank_by_stolen);
 310         seq_puts(m, "Stolen:\n");
 311         while (!list_empty(&stolen)) {
 312                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 313                 seq_puts(m, "   ");
 314                 describe_obj(m, obj);
 315                 seq_putc(m, '\n');
 316                 list_del_init(&obj->obj_exec_link);
 317         }
 318         mutex_unlock(&dev->struct_mutex);
 319
 320         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 321                    count, total_obj_size, total_gtt_size);
 322         return 0;
 323 }
 324
 325 #define count_objects(list, member) do { \
 326         list_for_each_entry(obj, list, member) { \
 327                 size += i915_gem_obj_total_ggtt_size(obj); \
 328                 ++count; \
 329                 if (obj->map_and_fenceable) { \
 330                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 331                         ++mappable_count; \
 332                 } \
 333         } \
 334 } while (0)
 335
 336 struct file_stats {
 337         struct drm_i915_file_private *file_priv;
 338         unsigned long count;
 339         u64 total, unbound;
 340         u64 global, shared;
 341         u64 active, inactive;
 342 };
 343
 344 static int per_file_stats(int id, void *ptr, void *data)
 345 {
 346         struct drm_i915_gem_object *obj = ptr;
 347         struct file_stats *stats = data;
 348         struct i915_vma *vma;
 349
 350         stats->count++;
 351         stats->total += obj->base.size;
 352         if (!obj->bind_count)
 353                 stats->unbound += obj->base.size;
 354         if (obj->base.name || obj->base.dma_buf)
 355                 stats->shared += obj->base.size;
 356
 357         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 358                 if (!drm_mm_node_allocated(&vma->node))
 359                         continue;
 360
 361                 if (i915_vma_is_ggtt(vma)) {
 362                         stats->global += vma->node.size;
 363                 } else {
 364                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 365
 366                         if (ppgtt->base.file != stats->file_priv)
 367                                 continue;
 368                 }
 369
 370                 if (i915_vma_is_active(vma))
 371                         stats->active += vma->node.size;
 372                 else
 373                         stats->inactive += vma->node.size;
 374         }
 375
 376         return 0;
 377 }
 378
 379 #define print_file_stats(m, name, stats) do { \
 380         if (stats.count) \
 381                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 382                            name, \
 383                            stats.count, \
 384                            stats.total, \
 385                            stats.active, \
 386                            stats.inactive, \
 387                            stats.global, \
 388                            stats.shared, \
 389                            stats.unbound); \
 390 } while (0)
 391
 392 static void print_batch_pool_stats(struct seq_file *m,
 393                                    struct drm_i915_private *dev_priv)
 394 {
 395         struct drm_i915_gem_object *obj;
 396         struct file_stats stats;
 397         struct intel_engine_cs *engine;
 398         int j;
 399
 400         memset(&stats, 0, sizeof(stats));
 401
 402         for_each_engine(engine, dev_priv) {
 403                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 404                         list_for_each_entry(obj,
 405                                             &engine->batch_pool.cache_list[j],
 406                                             batch_pool_link)
 407                                 per_file_stats(0, obj, &stats);
 408                 }
 409         }
 410
 411         print_file_stats(m, "[k]batch pool", stats);
 412 }
 413
 414 static int per_file_ctx_stats(int id, void *ptr, void *data)
 415 {
 416         struct i915_gem_context *ctx = ptr;
 417         int n;
 418
 419         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 420                 if (ctx->engine[n].state)
 421                         per_file_stats(0, ctx->engine[n].state, data);
 422                 if (ctx->engine[n].ring)
 423                         per_file_stats(0, ctx->engine[n].ring->obj, data);
 424         }
 425
 426         return 0;
 427 }
 428
 429 static void print_context_stats(struct seq_file *m,
 430                                 struct drm_i915_private *dev_priv)
 431 {
 432         struct file_stats stats;
 433         struct drm_file *file;
 434
 435         memset(&stats, 0, sizeof(stats));
 436
 437         mutex_lock(&dev_priv->drm.struct_mutex);
 438         if (dev_priv->kernel_context)
 439                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 440
 441         list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
 442                 struct drm_i915_file_private *fpriv = file->driver_priv;
 443                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 444         }
 445         mutex_unlock(&dev_priv->drm.struct_mutex);
 446
 447         print_file_stats(m, "[k]contexts", stats);
 448 }
 449
 450 #define count_vmas(list, member) do { \
 451         list_for_each_entry(vma, list, member) { \
 452                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 453                 ++count; \
 454                 if (vma->obj->map_and_fenceable) { \
 455                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 456                         ++mappable_count; \
 457                 } \
 458         } \
 459 } while (0)
 460
 461 static int i915_gem_object_info(struct seq_file *m, void* data)
 462 {
 463         struct drm_info_node *node = m->private;
 464         struct drm_device *dev = node->minor->dev;
 465         struct drm_i915_private *dev_priv = to_i915(dev);
 466         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 467         u32 count, mappable_count, purgeable_count;
 468         u64 size, mappable_size, purgeable_size;
 469         unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
 470         u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
 471         struct drm_i915_gem_object *obj;
 472         struct drm_file *file;
 473         struct i915_vma *vma;
 474         int ret;
 475
 476         ret = mutex_lock_interruptible(&dev->struct_mutex);
 477         if (ret)
 478                 return ret;
 479
 480         seq_printf(m, "%u objects, %zu bytes\n",
 481                    dev_priv->mm.object_count,
 482                    dev_priv->mm.object_memory);
 483
 484         size = count = mappable_size = mappable_count = 0;
 485         count_objects(&dev_priv->mm.bound_list, global_list);
 486         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 487                    count, mappable_count, size, mappable_size);
 488
 489         size = count = mappable_size = mappable_count = 0;
 490         count_vmas(&ggtt->base.active_list, vm_link);
 491         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 492                    count, mappable_count, size, mappable_size);
 493
 494         size = count = mappable_size = mappable_count = 0;
 495         count_vmas(&ggtt->base.inactive_list, vm_link);
 496         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 497                    count, mappable_count, size, mappable_size);
 498
 499         size = count = purgeable_size = purgeable_count = 0;
 500         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 501                 size += obj->base.size, ++count;
 502                 if (obj->madv == I915_MADV_DONTNEED)
 503                         purgeable_size += obj->base.size, ++purgeable_count;
 504                 if (obj->mapping) {
 505                         pin_mapped_count++;
 506                         pin_mapped_size += obj->base.size;
 507                         if (obj->pages_pin_count == 0) {
 508                                 pin_mapped_purgeable_count++;
 509                                 pin_mapped_purgeable_size += obj->base.size;
 510                         }
 511                 }
 512         }
 513         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 514
 515         size = count = mappable_size = mappable_count = 0;
 516         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 517                 if (obj->fault_mappable) {
 518                         size += i915_gem_obj_ggtt_size(obj);
 519                         ++count;
 520                 }
 521                 if (obj->pin_display) {
 522                         mappable_size += i915_gem_obj_ggtt_size(obj);
 523                         ++mappable_count;
 524                 }
 525                 if (obj->madv == I915_MADV_DONTNEED) {
 526                         purgeable_size += obj->base.size;
 527                         ++purgeable_count;
 528                 }
 529                 if (obj->mapping) {
 530                         pin_mapped_count++;
 531                         pin_mapped_size += obj->base.size;
 532                         if (obj->pages_pin_count == 0) {
 533                                 pin_mapped_purgeable_count++;
 534                                 pin_mapped_purgeable_size += obj->base.size;
 535                         }
 536                 }
 537         }
 538         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 539                    purgeable_count, purgeable_size);
 540         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 541                    mappable_count, mappable_size);
 542         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 543                    count, size);
 544         seq_printf(m,
 545                    "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
 546                    pin_mapped_count, pin_mapped_purgeable_count,
 547                    pin_mapped_size, pin_mapped_purgeable_size);
 548
 549         seq_printf(m, "%llu [%llu] gtt total\n",
 550                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 551
 552         seq_putc(m, '\n');
 553         print_batch_pool_stats(m, dev_priv);
 554         mutex_unlock(&dev->struct_mutex);
 555
 556         mutex_lock(&dev->filelist_mutex);
 557         print_context_stats(m, dev_priv);
 558         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 559                 struct file_stats stats;
 560                 struct task_struct *task;
 561
 562                 memset(&stats, 0, sizeof(stats));
 563                 stats.file_priv = file->driver_priv;
 564                 spin_lock(&file->table_lock);
 565                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 566                 spin_unlock(&file->table_lock);
 567                 /*
 568                  * Although we have a valid reference on file->pid, that does
 569                  * not guarantee that the task_struct who called get_pid() is
 570                  * still alive (e.g. get_pid(current) => fork() => exit()).
 571                  * Therefore, we need to protect this ->comm access using RCU.
 572                  */
 573                 rcu_read_lock();
 574                 task = pid_task(file->pid, PIDTYPE_PID);
 575                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 576                 rcu_read_unlock();
 577         }
 578         mutex_unlock(&dev->filelist_mutex);
 579
 580         return 0;
 581 }
 582
 583 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 584 {
 585         struct drm_info_node *node = m->private;
 586         struct drm_device *dev = node->minor->dev;
 587         uintptr_t list = (uintptr_t) node->info_ent->data;
 588         struct drm_i915_private *dev_priv = to_i915(dev);
 589         struct drm_i915_gem_object *obj;
 590         u64 total_obj_size, total_gtt_size;
 591         int count, ret;
 592
 593         ret = mutex_lock_interruptible(&dev->struct_mutex);
 594         if (ret)
 595                 return ret;
 596
 597         total_obj_size = total_gtt_size = count = 0;
 598         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 599                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 600                         continue;
 601
 602                 seq_puts(m, "   ");
 603                 describe_obj(m, obj);
 604                 seq_putc(m, '\n');
 605                 total_obj_size += obj->base.size;
 606                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 607                 count++;
 608         }
 609
 610         mutex_unlock(&dev->struct_mutex);
 611
 612         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 613                    count, total_obj_size, total_gtt_size);
 614
 615         return 0;
 616 }
 617
 618 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 619 {
 620         struct drm_info_node *node = m->private;
 621         struct drm_device *dev = node->minor->dev;
 622         struct drm_i915_private *dev_priv = to_i915(dev);
 623         struct intel_crtc *crtc;
 624         int ret;
 625
 626         ret = mutex_lock_interruptible(&dev->struct_mutex);
 627         if (ret)
 628                 return ret;
 629
 630         for_each_intel_crtc(dev, crtc) {
 631                 const char pipe = pipe_name(crtc->pipe);
 632                 const char plane = plane_name(crtc->plane);
 633                 struct intel_flip_work *work;
 634
 635                 spin_lock_irq(&dev->event_lock);
 636                 work = crtc->flip_work;
 637                 if (work == NULL) {
 638                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 639                                    pipe, plane);
 640                 } else {
 641                         u32 pending;
 642                         u32 addr;
 643
 644                         pending = atomic_read(&work->pending);
 645                         if (pending) {
 646                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 647                                            pipe, plane);
 648                         } else {
 649                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 650                                            pipe, plane);
 651                         }
 652                         if (work->flip_queued_req) {
 653                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 654
 655                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 656                                            engine->name,
 657                                            i915_gem_request_get_seqno(work->flip_queued_req),
 658                                            dev_priv->next_seqno,
 659                                            intel_engine_get_seqno(engine),
 660                                            i915_gem_request_completed(work->flip_queued_req));
 661                         } else
 662                                 seq_printf(m, "Flip not associated with any ring\n");
 663                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 664                                    work->flip_queued_vblank,
 665                                    work->flip_ready_vblank,
 666                                    intel_crtc_get_vblank_counter(crtc));
 667                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 668
 669                         if (INTEL_INFO(dev)->gen >= 4)
 670                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 671                         else
 672                                 addr = I915_READ(DSPADDR(crtc->plane));
 673                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 674
 675                         if (work->pending_flip_obj) {
 676                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 677                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 678                         }
 679                 }
 680                 spin_unlock_irq(&dev->event_lock);
 681         }
 682
 683         mutex_unlock(&dev->struct_mutex);
 684
 685         return 0;
 686 }
 687
 688 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 689 {
 690         struct drm_info_node *node = m->private;
 691         struct drm_device *dev = node->minor->dev;
 692         struct drm_i915_private *dev_priv = to_i915(dev);
 693         struct drm_i915_gem_object *obj;
 694         struct intel_engine_cs *engine;
 695         int total = 0;
 696         int ret, j;
 697
 698         ret = mutex_lock_interruptible(&dev->struct_mutex);
 699         if (ret)
 700                 return ret;
 701
 702         for_each_engine(engine, dev_priv) {
 703                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 704                         int count;
 705
 706                         count = 0;
 707                         list_for_each_entry(obj,
 708                                             &engine->batch_pool.cache_list[j],
 709                                             batch_pool_link)
 710                                 count++;
 711                         seq_printf(m, "%s cache[%d]: %d objects\n",
 712                                    engine->name, j, count);
 713
 714                         list_for_each_entry(obj,
 715                                             &engine->batch_pool.cache_list[j],
 716                                             batch_pool_link) {
 717                                 seq_puts(m, "   ");
 718                                 describe_obj(m, obj);
 719                                 seq_putc(m, '\n');
 720                         }
 721
 722                         total += count;
 723                 }
 724         }
 725
 726         seq_printf(m, "total: %d\n", total);
 727
 728         mutex_unlock(&dev->struct_mutex);
 729
 730         return 0;
 731 }
 732
 733 static int i915_gem_request_info(struct seq_file *m, void *data)
 734 {
 735         struct drm_info_node *node = m->private;
 736         struct drm_device *dev = node->minor->dev;
 737         struct drm_i915_private *dev_priv = to_i915(dev);
 738         struct intel_engine_cs *engine;
 739         struct drm_i915_gem_request *req;
 740         int ret, any;
 741
 742         ret = mutex_lock_interruptible(&dev->struct_mutex);
 743         if (ret)
 744                 return ret;
 745
 746         any = 0;
 747         for_each_engine(engine, dev_priv) {
 748                 int count;
 749
 750                 count = 0;
 751                 list_for_each_entry(req, &engine->request_list, link)
 752                         count++;
 753                 if (count == 0)
 754                         continue;
 755
 756                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 757                 list_for_each_entry(req, &engine->request_list, link) {
 758                         struct task_struct *task;
 759
 760                         rcu_read_lock();
 761                         task = NULL;
 762                         if (req->pid)
 763                                 task = pid_task(req->pid, PIDTYPE_PID);
 764                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 765                                    req->fence.seqno,
 766                                    (int) (jiffies - req->emitted_jiffies),
 767                                    task ? task->comm : "<unknown>",
 768                                    task ? task->pid : -1);
 769                         rcu_read_unlock();
 770                 }
 771
 772                 any++;
 773         }
 774         mutex_unlock(&dev->struct_mutex);
 775
 776         if (any == 0)
 777                 seq_puts(m, "No requests\n");
 778
 779         return 0;
 780 }
 781
 782 static void i915_ring_seqno_info(struct seq_file *m,
 783                                  struct intel_engine_cs *engine)
 784 {
 785         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 786         struct rb_node *rb;
 787
 788         seq_printf(m, "Current sequence (%s): %x\n",
 789                    engine->name, intel_engine_get_seqno(engine));
 790
 791         spin_lock(&b->lock);
 792         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 793                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 794
 795                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 796                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 797         }
 798         spin_unlock(&b->lock);
 799 }
 800
 801 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 802 {
 803         struct drm_info_node *node = m->private;
 804         struct drm_device *dev = node->minor->dev;
 805         struct drm_i915_private *dev_priv = to_i915(dev);
 806         struct intel_engine_cs *engine;
 807         int ret;
 808
 809         ret = mutex_lock_interruptible(&dev->struct_mutex);
 810         if (ret)
 811                 return ret;
 812         intel_runtime_pm_get(dev_priv);
 813
 814         for_each_engine(engine, dev_priv)
 815                 i915_ring_seqno_info(m, engine);
 816
 817         intel_runtime_pm_put(dev_priv);
 818         mutex_unlock(&dev->struct_mutex);
 819
 820         return 0;
 821 }
 822
 823
 824 static int i915_interrupt_info(struct seq_file *m, void *data)
 825 {
 826         struct drm_info_node *node = m->private;
 827         struct drm_device *dev = node->minor->dev;
 828         struct drm_i915_private *dev_priv = to_i915(dev);
 829         struct intel_engine_cs *engine;
 830         int ret, i, pipe;
 831
 832         ret = mutex_lock_interruptible(&dev->struct_mutex);
 833         if (ret)
 834                 return ret;
 835         intel_runtime_pm_get(dev_priv);
 836
 837         if (IS_CHERRYVIEW(dev)) {
 838                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 839                            I915_READ(GEN8_MASTER_IRQ));
 840
 841                 seq_printf(m, "Display IER:\t%08x\n",
 842                            I915_READ(VLV_IER));
 843                 seq_printf(m, "Display IIR:\t%08x\n",
 844                            I915_READ(VLV_IIR));
 845                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 846                            I915_READ(VLV_IIR_RW));
 847                 seq_printf(m, "Display IMR:\t%08x\n",
 848                            I915_READ(VLV_IMR));
 849                 for_each_pipe(dev_priv, pipe)
 850                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 851                                    pipe_name(pipe),
 852                                    I915_READ(PIPESTAT(pipe)));
 853
 854                 seq_printf(m, "Port hotplug:\t%08x\n",
 855                            I915_READ(PORT_HOTPLUG_EN));
 856                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 857                            I915_READ(VLV_DPFLIPSTAT));
 858                 seq_printf(m, "DPINVGTT:\t%08x\n",
 859                            I915_READ(DPINVGTT));
 860
 861                 for (i = 0; i < 4; i++) {
 862                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 863                                    i, I915_READ(GEN8_GT_IMR(i)));
 864                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 865                                    i, I915_READ(GEN8_GT_IIR(i)));
 866                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 867                                    i, I915_READ(GEN8_GT_IER(i)));
 868                 }
 869
 870                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 871                            I915_READ(GEN8_PCU_IMR));
 872                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 873                            I915_READ(GEN8_PCU_IIR));
 874                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 875                            I915_READ(GEN8_PCU_IER));
 876         } else if (INTEL_INFO(dev)->gen >= 8) {
 877                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 878                            I915_READ(GEN8_MASTER_IRQ));
 879
 880                 for (i = 0; i < 4; i++) {
 881                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 882                                    i, I915_READ(GEN8_GT_IMR(i)));
 883                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 884                                    i, I915_READ(GEN8_GT_IIR(i)));
 885                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 886                                    i, I915_READ(GEN8_GT_IER(i)));
 887                 }
 888
 889                 for_each_pipe(dev_priv, pipe) {
 890                         enum intel_display_power_domain power_domain;
 891
 892                         power_domain = POWER_DOMAIN_PIPE(pipe);
 893                         if (!intel_display_power_get_if_enabled(dev_priv,
 894                                                                 power_domain)) {
 895                                 seq_printf(m, "Pipe %c power disabled\n",
 896                                            pipe_name(pipe));
 897                                 continue;
 898                         }
 899                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 900                                    pipe_name(pipe),
 901                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 902                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 903                                    pipe_name(pipe),
 904                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 905                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 906                                    pipe_name(pipe),
 907                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 908
 909                         intel_display_power_put(dev_priv, power_domain);
 910                 }
 911
 912                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 913                            I915_READ(GEN8_DE_PORT_IMR));
 914                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 915                            I915_READ(GEN8_DE_PORT_IIR));
 916                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 917                            I915_READ(GEN8_DE_PORT_IER));
 918
 919                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 920                            I915_READ(GEN8_DE_MISC_IMR));
 921                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 922                            I915_READ(GEN8_DE_MISC_IIR));
 923                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 924                            I915_READ(GEN8_DE_MISC_IER));
 925
 926                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 927                            I915_READ(GEN8_PCU_IMR));
 928                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 929                            I915_READ(GEN8_PCU_IIR));
 930                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 931                            I915_READ(GEN8_PCU_IER));
 932         } else if (IS_VALLEYVIEW(dev)) {
 933                 seq_printf(m, "Display IER:\t%08x\n",
 934                            I915_READ(VLV_IER));
 935                 seq_printf(m, "Display IIR:\t%08x\n",
 936                            I915_READ(VLV_IIR));
 937                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 938                            I915_READ(VLV_IIR_RW));
 939                 seq_printf(m, "Display IMR:\t%08x\n",
 940                            I915_READ(VLV_IMR));
 941                 for_each_pipe(dev_priv, pipe)
 942                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 943                                    pipe_name(pipe),
 944                                    I915_READ(PIPESTAT(pipe)));
 945
 946                 seq_printf(m, "Master IER:\t%08x\n",
 947                            I915_READ(VLV_MASTER_IER));
 948
 949                 seq_printf(m, "Render IER:\t%08x\n",
 950                            I915_READ(GTIER));
 951                 seq_printf(m, "Render IIR:\t%08x\n",
 952                            I915_READ(GTIIR));
 953                 seq_printf(m, "Render IMR:\t%08x\n",
 954                            I915_READ(GTIMR));
 955
 956                 seq_printf(m, "PM IER:\t\t%08x\n",
 957                            I915_READ(GEN6_PMIER));
 958                 seq_printf(m, "PM IIR:\t\t%08x\n",
 959                            I915_READ(GEN6_PMIIR));
 960                 seq_printf(m, "PM IMR:\t\t%08x\n",
 961                            I915_READ(GEN6_PMIMR));
 962
 963                 seq_printf(m, "Port hotplug:\t%08x\n",
 964                            I915_READ(PORT_HOTPLUG_EN));
 965                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 966                            I915_READ(VLV_DPFLIPSTAT));
 967                 seq_printf(m, "DPINVGTT:\t%08x\n",
 968                            I915_READ(DPINVGTT));
 969
 970         } else if (!HAS_PCH_SPLIT(dev)) {
 971                 seq_printf(m, "Interrupt enable:    %08x\n",
 972                            I915_READ(IER));
 973                 seq_printf(m, "Interrupt identity:  %08x\n",
 974                            I915_READ(IIR));
 975                 seq_printf(m, "Interrupt mask:      %08x\n",
 976                            I915_READ(IMR));
 977                 for_each_pipe(dev_priv, pipe)
 978                         seq_printf(m, "Pipe %c stat:         %08x\n",
 979                                    pipe_name(pipe),
 980                                    I915_READ(PIPESTAT(pipe)));
 981         } else {
 982                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 983                            I915_READ(DEIER));
 984                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 985                            I915_READ(DEIIR));
 986                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 987                            I915_READ(DEIMR));
 988                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 989                            I915_READ(SDEIER));
 990                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 991                            I915_READ(SDEIIR));
 992                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 993                            I915_READ(SDEIMR));
 994                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 995                            I915_READ(GTIER));
 996                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 997                            I915_READ(GTIIR));
 998                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 999                            I915_READ(GTIMR));
1000         }
1001         for_each_engine(engine, dev_priv) {
1002                 if (INTEL_INFO(dev)->gen >= 6) {
1003                         seq_printf(m,
1004                                    "Graphics Interrupt mask (%s):       %08x\n",
1005                                    engine->name, I915_READ_IMR(engine));
1006                 }
1007                 i915_ring_seqno_info(m, engine);
1008         }
1009         intel_runtime_pm_put(dev_priv);
1010         mutex_unlock(&dev->struct_mutex);
1011
1012         return 0;
1013 }
1014
1015 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1016 {
1017         struct drm_info_node *node = m->private;
1018         struct drm_device *dev = node->minor->dev;
1019         struct drm_i915_private *dev_priv = to_i915(dev);
1020         int i, ret;
1021
1022         ret = mutex_lock_interruptible(&dev->struct_mutex);
1023         if (ret)
1024                 return ret;
1025
1026         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1027         for (i = 0; i < dev_priv->num_fence_regs; i++) {
1028                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1029
1030                 seq_printf(m, "Fence %d, pin count = %d, object = ",
1031                            i, dev_priv->fence_regs[i].pin_count);
1032                 if (obj == NULL)
1033                         seq_puts(m, "unused");
1034                 else
1035                         describe_obj(m, obj);
1036                 seq_putc(m, '\n');
1037         }
1038
1039         mutex_unlock(&dev->struct_mutex);
1040         return 0;
1041 }
1042
1043 static int i915_hws_info(struct seq_file *m, void *data)
1044 {
1045         struct drm_info_node *node = m->private;
1046         struct drm_device *dev = node->minor->dev;
1047         struct drm_i915_private *dev_priv = to_i915(dev);
1048         struct intel_engine_cs *engine;
1049         const u32 *hws;
1050         int i;
1051
1052         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1053         hws = engine->status_page.page_addr;
1054         if (hws == NULL)
1055                 return 0;
1056
1057         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1058                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1059                            i * 4,
1060                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1061         }
1062         return 0;
1063 }
1064
1065 static ssize_t
1066 i915_error_state_write(struct file *filp,
1067                        const char __user *ubuf,
1068                        size_t cnt,
1069                        loff_t *ppos)
1070 {
1071         struct i915_error_state_file_priv *error_priv = filp->private_data;
1072         struct drm_device *dev = error_priv->dev;
1073         int ret;
1074
1075         DRM_DEBUG_DRIVER("Resetting error state\n");
1076
1077         ret = mutex_lock_interruptible(&dev->struct_mutex);
1078         if (ret)
1079                 return ret;
1080
1081         i915_destroy_error_state(dev);
1082         mutex_unlock(&dev->struct_mutex);
1083
1084         return cnt;
1085 }
1086
1087 static int i915_error_state_open(struct inode *inode, struct file *file)
1088 {
1089         struct drm_device *dev = inode->i_private;
1090         struct i915_error_state_file_priv *error_priv;
1091
1092         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1093         if (!error_priv)
1094                 return -ENOMEM;
1095
1096         error_priv->dev = dev;
1097
1098         i915_error_state_get(dev, error_priv);
1099
1100         file->private_data = error_priv;
1101
1102         return 0;
1103 }
1104
1105 static int i915_error_state_release(struct inode *inode, struct file *file)
1106 {
1107         struct i915_error_state_file_priv *error_priv = file->private_data;
1108
1109         i915_error_state_put(error_priv);
1110         kfree(error_priv);
1111
1112         return 0;
1113 }
1114
1115 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1116                                      size_t count, loff_t *pos)
1117 {
1118         struct i915_error_state_file_priv *error_priv = file->private_data;
1119         struct drm_i915_error_state_buf error_str;
1120         loff_t tmp_pos = 0;
1121         ssize_t ret_count = 0;
1122         int ret;
1123
1124         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1125         if (ret)
1126                 return ret;
1127
1128         ret = i915_error_state_to_str(&error_str, error_priv);
1129         if (ret)
1130                 goto out;
1131
1132         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1133                                             error_str.buf,
1134                                             error_str.bytes);
1135
1136         if (ret_count < 0)
1137                 ret = ret_count;
1138         else
1139                 *pos = error_str.start + ret_count;
1140 out:
1141         i915_error_state_buf_release(&error_str);
1142         return ret ?: ret_count;
1143 }
1144
1145 static const struct file_operations i915_error_state_fops = {
1146         .owner = THIS_MODULE,
1147         .open = i915_error_state_open,
1148         .read = i915_error_state_read,
1149         .write = i915_error_state_write,
1150         .llseek = default_llseek,
1151         .release = i915_error_state_release,
1152 };
1153
1154 static int
1155 i915_next_seqno_get(void *data, u64 *val)
1156 {
1157         struct drm_device *dev = data;
1158         struct drm_i915_private *dev_priv = to_i915(dev);
1159         int ret;
1160
1161         ret = mutex_lock_interruptible(&dev->struct_mutex);
1162         if (ret)
1163                 return ret;
1164
1165         *val = dev_priv->next_seqno;
1166         mutex_unlock(&dev->struct_mutex);
1167
1168         return 0;
1169 }
1170
1171 static int
1172 i915_next_seqno_set(void *data, u64 val)
1173 {
1174         struct drm_device *dev = data;
1175         int ret;
1176
1177         ret = mutex_lock_interruptible(&dev->struct_mutex);
1178         if (ret)
1179                 return ret;
1180
1181         ret = i915_gem_set_seqno(dev, val);
1182         mutex_unlock(&dev->struct_mutex);
1183
1184         return ret;
1185 }
1186
1187 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1188                         i915_next_seqno_get, i915_next_seqno_set,
1189                         "0x%llx\n");
1190
1191 static int i915_frequency_info(struct seq_file *m, void *unused)
1192 {
1193         struct drm_info_node *node = m->private;
1194         struct drm_device *dev = node->minor->dev;
1195         struct drm_i915_private *dev_priv = to_i915(dev);
1196         int ret = 0;
1197
1198         intel_runtime_pm_get(dev_priv);
1199
1200         if (IS_GEN5(dev)) {
1201                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1202                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1203
1204                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1205                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1206                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1207                            MEMSTAT_VID_SHIFT);
1208                 seq_printf(m, "Current P-state: %d\n",
1209                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1210         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1211                 u32 freq_sts;
1212
1213                 mutex_lock(&dev_priv->rps.hw_lock);
1214                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1215                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1216                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1217
1218                 seq_printf(m, "actual GPU freq: %d MHz\n",
1219                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1220
1221                 seq_printf(m, "current GPU freq: %d MHz\n",
1222                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1223
1224                 seq_printf(m, "max GPU freq: %d MHz\n",
1225                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1226
1227                 seq_printf(m, "min GPU freq: %d MHz\n",
1228                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1229
1230                 seq_printf(m, "idle GPU freq: %d MHz\n",
1231                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1232
1233                 seq_printf(m,
1234                            "efficient (RPe) frequency: %d MHz\n",
1235                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1236                 mutex_unlock(&dev_priv->rps.hw_lock);
1237         } else if (INTEL_INFO(dev)->gen >= 6) {
1238                 u32 rp_state_limits;
1239                 u32 gt_perf_status;
1240                 u32 rp_state_cap;
1241                 u32 rpmodectl, rpinclimit, rpdeclimit;
1242                 u32 rpstat, cagf, reqf;
1243                 u32 rpupei, rpcurup, rpprevup;
1244                 u32 rpdownei, rpcurdown, rpprevdown;
1245                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1246                 int max_freq;
1247
1248                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1249                 if (IS_BROXTON(dev)) {
1250                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1251                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1252                 } else {
1253                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1254                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1255                 }
1256
1257                 /* RPSTAT1 is in the GT power well */
1258                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1259                 if (ret)
1260                         goto out;
1261
1262                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1263
1264                 reqf = I915_READ(GEN6_RPNSWREQ);
1265                 if (IS_GEN9(dev))
1266                         reqf >>= 23;
1267                 else {
1268                         reqf &= ~GEN6_TURBO_DISABLE;
1269                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1270                                 reqf >>= 24;
1271                         else
1272                                 reqf >>= 25;
1273                 }
1274                 reqf = intel_gpu_freq(dev_priv, reqf);
1275
1276                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1277                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1278                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1279
1280                 rpstat = I915_READ(GEN6_RPSTAT1);
1281                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1282                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1283                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1284                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1285                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1286                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1287                 if (IS_GEN9(dev))
1288                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1289                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1290                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1291                 else
1292                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1293                 cagf = intel_gpu_freq(dev_priv, cagf);
1294
1295                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1296                 mutex_unlock(&dev->struct_mutex);
1297
1298                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1299                         pm_ier = I915_READ(GEN6_PMIER);
1300                         pm_imr = I915_READ(GEN6_PMIMR);
1301                         pm_isr = I915_READ(GEN6_PMISR);
1302                         pm_iir = I915_READ(GEN6_PMIIR);
1303                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1304                 } else {
1305                         pm_ier = I915_READ(GEN8_GT_IER(2));
1306                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1307                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1308                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1309                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1310                 }
1311                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1312                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1313                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1314                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1315                 seq_printf(m, "Render p-state ratio: %d\n",
1316                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1317                 seq_printf(m, "Render p-state VID: %d\n",
1318                            gt_perf_status & 0xff);
1319                 seq_printf(m, "Render p-state limit: %d\n",
1320                            rp_state_limits & 0xff);
1321                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1322                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1323                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1324                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1325                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1326                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1327                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1328                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1329                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1330                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1331                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1332                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1333                 seq_printf(m, "Up threshold: %d%%\n",
1334                            dev_priv->rps.up_threshold);
1335
1336                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1337                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1338                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1339                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1340                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1341                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1342                 seq_printf(m, "Down threshold: %d%%\n",
1343                            dev_priv->rps.down_threshold);
1344
1345                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1346                             rp_state_cap >> 16) & 0xff;
1347                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1348                              GEN9_FREQ_SCALER : 1);
1349                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1350                            intel_gpu_freq(dev_priv, max_freq));
1351
1352                 max_freq = (rp_state_cap & 0xff00) >> 8;
1353                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1354                              GEN9_FREQ_SCALER : 1);
1355                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1356                            intel_gpu_freq(dev_priv, max_freq));
1357
1358                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1359                             rp_state_cap >> 0) & 0xff;
1360                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1361                              GEN9_FREQ_SCALER : 1);
1362                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1363                            intel_gpu_freq(dev_priv, max_freq));
1364                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1365                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1366
1367                 seq_printf(m, "Current freq: %d MHz\n",
1368                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1369                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1370                 seq_printf(m, "Idle freq: %d MHz\n",
1371                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1372                 seq_printf(m, "Min freq: %d MHz\n",
1373                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1374                 seq_printf(m, "Boost freq: %d MHz\n",
1375                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1376                 seq_printf(m, "Max freq: %d MHz\n",
1377                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1378                 seq_printf(m,
1379                            "efficient (RPe) frequency: %d MHz\n",
1380                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1381         } else {
1382                 seq_puts(m, "no P-state info available\n");
1383         }
1384
1385         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1386         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1387         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1388
1389 out:
1390         intel_runtime_pm_put(dev_priv);
1391         return ret;
1392 }
1393
1394 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1395 {
1396         struct drm_info_node *node = m->private;
1397         struct drm_device *dev = node->minor->dev;
1398         struct drm_i915_private *dev_priv = to_i915(dev);
1399         struct intel_engine_cs *engine;
1400         u64 acthd[I915_NUM_ENGINES];
1401         u32 seqno[I915_NUM_ENGINES];
1402         u32 instdone[I915_NUM_INSTDONE_REG];
1403         enum intel_engine_id id;
1404         int j;
1405
1406         if (!i915.enable_hangcheck) {
1407                 seq_printf(m, "Hangcheck disabled\n");
1408                 return 0;
1409         }
1410
1411         intel_runtime_pm_get(dev_priv);
1412
1413         for_each_engine_id(engine, dev_priv, id) {
1414                 acthd[id] = intel_engine_get_active_head(engine);
1415                 seqno[id] = intel_engine_get_seqno(engine);
1416         }
1417
1418         i915_get_extra_instdone(dev_priv, instdone);
1419
1420         intel_runtime_pm_put(dev_priv);
1421
1422         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1423                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1424                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1425                                             jiffies));
1426         } else
1427                 seq_printf(m, "Hangcheck inactive\n");
1428
1429         for_each_engine_id(engine, dev_priv, id) {
1430                 seq_printf(m, "%s:\n", engine->name);
1431                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1432                            engine->hangcheck.seqno,
1433                            seqno[id],
1434                            engine->last_submitted_seqno);
1435                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1436                            yesno(intel_engine_has_waiter(engine)),
1437                            yesno(test_bit(engine->id,
1438                                           &dev_priv->gpu_error.missed_irq_rings)));
1439                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1440                            (long long)engine->hangcheck.acthd,
1441                            (long long)acthd[id]);
1442                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1443                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1444
1445                 if (engine->id == RCS) {
1446                         seq_puts(m, "\tinstdone read =");
1447
1448                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1449                                 seq_printf(m, " 0x%08x", instdone[j]);
1450
1451                         seq_puts(m, "\n\tinstdone accu =");
1452
1453                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1454                                 seq_printf(m, " 0x%08x",
1455                                            engine->hangcheck.instdone[j]);
1456
1457                         seq_puts(m, "\n");
1458                 }
1459         }
1460
1461         return 0;
1462 }
1463
1464 static int ironlake_drpc_info(struct seq_file *m)
1465 {
1466         struct drm_info_node *node = m->private;
1467         struct drm_device *dev = node->minor->dev;
1468         struct drm_i915_private *dev_priv = to_i915(dev);
1469         u32 rgvmodectl, rstdbyctl;
1470         u16 crstandvid;
1471         int ret;
1472
1473         ret = mutex_lock_interruptible(&dev->struct_mutex);
1474         if (ret)
1475                 return ret;
1476         intel_runtime_pm_get(dev_priv);
1477
1478         rgvmodectl = I915_READ(MEMMODECTL);
1479         rstdbyctl = I915_READ(RSTDBYCTL);
1480         crstandvid = I915_READ16(CRSTANDVID);
1481
1482         intel_runtime_pm_put(dev_priv);
1483         mutex_unlock(&dev->struct_mutex);
1484
1485         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1486         seq_printf(m, "Boost freq: %d\n",
1487                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1488                    MEMMODE_BOOST_FREQ_SHIFT);
1489         seq_printf(m, "HW control enabled: %s\n",
1490                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1491         seq_printf(m, "SW control enabled: %s\n",
1492                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1493         seq_printf(m, "Gated voltage change: %s\n",
1494                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1495         seq_printf(m, "Starting frequency: P%d\n",
1496                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1497         seq_printf(m, "Max P-state: P%d\n",
1498                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1499         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1500         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1501         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1502         seq_printf(m, "Render standby enabled: %s\n",
1503                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1504         seq_puts(m, "Current RS state: ");
1505         switch (rstdbyctl & RSX_STATUS_MASK) {
1506         case RSX_STATUS_ON:
1507                 seq_puts(m, "on\n");
1508                 break;
1509         case RSX_STATUS_RC1:
1510                 seq_puts(m, "RC1\n");
1511                 break;
1512         case RSX_STATUS_RC1E:
1513                 seq_puts(m, "RC1E\n");
1514                 break;
1515         case RSX_STATUS_RS1:
1516                 seq_puts(m, "RS1\n");
1517                 break;
1518         case RSX_STATUS_RS2:
1519                 seq_puts(m, "RS2 (RC6)\n");
1520                 break;
1521         case RSX_STATUS_RS3:
1522                 seq_puts(m, "RC3 (RC6+)\n");
1523                 break;
1524         default:
1525                 seq_puts(m, "unknown\n");
1526                 break;
1527         }
1528
1529         return 0;
1530 }
1531
1532 static int i915_forcewake_domains(struct seq_file *m, void *data)
1533 {
1534         struct drm_info_node *node = m->private;
1535         struct drm_device *dev = node->minor->dev;
1536         struct drm_i915_private *dev_priv = to_i915(dev);
1537         struct intel_uncore_forcewake_domain *fw_domain;
1538
1539         spin_lock_irq(&dev_priv->uncore.lock);
1540         for_each_fw_domain(fw_domain, dev_priv) {
1541                 seq_printf(m, "%s.wake_count = %u\n",
1542                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1543                            fw_domain->wake_count);
1544         }
1545         spin_unlock_irq(&dev_priv->uncore.lock);
1546
1547         return 0;
1548 }
1549
1550 static int vlv_drpc_info(struct seq_file *m)
1551 {
1552         struct drm_info_node *node = m->private;
1553         struct drm_device *dev = node->minor->dev;
1554         struct drm_i915_private *dev_priv = to_i915(dev);
1555         u32 rpmodectl1, rcctl1, pw_status;
1556
1557         intel_runtime_pm_get(dev_priv);
1558
1559         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1560         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1561         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1562
1563         intel_runtime_pm_put(dev_priv);
1564
1565         seq_printf(m, "Video Turbo Mode: %s\n",
1566                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1567         seq_printf(m, "Turbo enabled: %s\n",
1568                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1569         seq_printf(m, "HW control enabled: %s\n",
1570                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1571         seq_printf(m, "SW control enabled: %s\n",
1572                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1573                           GEN6_RP_MEDIA_SW_MODE));
1574         seq_printf(m, "RC6 Enabled: %s\n",
1575                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1576                                         GEN6_RC_CTL_EI_MODE(1))));
1577         seq_printf(m, "Render Power Well: %s\n",
1578                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1579         seq_printf(m, "Media Power Well: %s\n",
1580                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1581
1582         seq_printf(m, "Render RC6 residency since boot: %u\n",
1583                    I915_READ(VLV_GT_RENDER_RC6));
1584         seq_printf(m, "Media RC6 residency since boot: %u\n",
1585                    I915_READ(VLV_GT_MEDIA_RC6));
1586
1587         return i915_forcewake_domains(m, NULL);
1588 }
1589
1590 static int gen6_drpc_info(struct seq_file *m)
1591 {
1592         struct drm_info_node *node = m->private;
1593         struct drm_device *dev = node->minor->dev;
1594         struct drm_i915_private *dev_priv = to_i915(dev);
1595         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1596         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1597         unsigned forcewake_count;
1598         int count = 0, ret;
1599
1600         ret = mutex_lock_interruptible(&dev->struct_mutex);
1601         if (ret)
1602                 return ret;
1603         intel_runtime_pm_get(dev_priv);
1604
1605         spin_lock_irq(&dev_priv->uncore.lock);
1606         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1607         spin_unlock_irq(&dev_priv->uncore.lock);
1608
1609         if (forcewake_count) {
1610                 seq_puts(m, "RC information inaccurate because somebody "
1611                             "holds a forcewake reference \n");
1612         } else {
1613                 /* NB: we cannot use forcewake, else we read the wrong values */
1614                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1615                         udelay(10);
1616                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1617         }
1618
1619         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1620         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1621
1622         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1623         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1624         if (INTEL_INFO(dev)->gen >= 9) {
1625                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1626                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1627         }
1628         mutex_unlock(&dev->struct_mutex);
1629         mutex_lock(&dev_priv->rps.hw_lock);
1630         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1631         mutex_unlock(&dev_priv->rps.hw_lock);
1632
1633         intel_runtime_pm_put(dev_priv);
1634
1635         seq_printf(m, "Video Turbo Mode: %s\n",
1636                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1637         seq_printf(m, "HW control enabled: %s\n",
1638                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1639         seq_printf(m, "SW control enabled: %s\n",
1640                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1641                           GEN6_RP_MEDIA_SW_MODE));
1642         seq_printf(m, "RC1e Enabled: %s\n",
1643                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1644         seq_printf(m, "RC6 Enabled: %s\n",
1645                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1646         if (INTEL_INFO(dev)->gen >= 9) {
1647                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1648                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1649                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1650                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1651         }
1652         seq_printf(m, "Deep RC6 Enabled: %s\n",
1653                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1654         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1655                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1656         seq_puts(m, "Current RC state: ");
1657         switch (gt_core_status & GEN6_RCn_MASK) {
1658         case GEN6_RC0:
1659                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1660                         seq_puts(m, "Core Power Down\n");
1661                 else
1662                         seq_puts(m, "on\n");
1663                 break;
1664         case GEN6_RC3:
1665                 seq_puts(m, "RC3\n");
1666                 break;
1667         case GEN6_RC6:
1668                 seq_puts(m, "RC6\n");
1669                 break;
1670         case GEN6_RC7:
1671                 seq_puts(m, "RC7\n");
1672                 break;
1673         default:
1674                 seq_puts(m, "Unknown\n");
1675                 break;
1676         }
1677
1678         seq_printf(m, "Core Power Down: %s\n",
1679                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1680         if (INTEL_INFO(dev)->gen >= 9) {
1681                 seq_printf(m, "Render Power Well: %s\n",
1682                         (gen9_powergate_status &
1683                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1684                 seq_printf(m, "Media Power Well: %s\n",
1685                         (gen9_powergate_status &
1686                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1687         }
1688
1689         /* Not exactly sure what this is */
1690         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1691                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1692         seq_printf(m, "RC6 residency since boot: %u\n",
1693                    I915_READ(GEN6_GT_GFX_RC6));
1694         seq_printf(m, "RC6+ residency since boot: %u\n",
1695                    I915_READ(GEN6_GT_GFX_RC6p));
1696         seq_printf(m, "RC6++ residency since boot: %u\n",
1697                    I915_READ(GEN6_GT_GFX_RC6pp));
1698
1699         seq_printf(m, "RC6   voltage: %dmV\n",
1700                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1701         seq_printf(m, "RC6+  voltage: %dmV\n",
1702                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1703         seq_printf(m, "RC6++ voltage: %dmV\n",
1704                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1705         return i915_forcewake_domains(m, NULL);
1706 }
1707
1708 static int i915_drpc_info(struct seq_file *m, void *unused)
1709 {
1710         struct drm_info_node *node = m->private;
1711         struct drm_device *dev = node->minor->dev;
1712
1713         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1714                 return vlv_drpc_info(m);
1715         else if (INTEL_INFO(dev)->gen >= 6)
1716                 return gen6_drpc_info(m);
1717         else
1718                 return ironlake_drpc_info(m);
1719 }
1720
1721 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1722 {
1723         struct drm_info_node *node = m->private;
1724         struct drm_device *dev = node->minor->dev;
1725         struct drm_i915_private *dev_priv = to_i915(dev);
1726
1727         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1728                    dev_priv->fb_tracking.busy_bits);
1729
1730         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1731                    dev_priv->fb_tracking.flip_bits);
1732
1733         return 0;
1734 }
1735
1736 static int i915_fbc_status(struct seq_file *m, void *unused)
1737 {
1738         struct drm_info_node *node = m->private;
1739         struct drm_device *dev = node->minor->dev;
1740         struct drm_i915_private *dev_priv = to_i915(dev);
1741
1742         if (!HAS_FBC(dev)) {
1743                 seq_puts(m, "FBC unsupported on this chipset\n");
1744                 return 0;
1745         }
1746
1747         intel_runtime_pm_get(dev_priv);
1748         mutex_lock(&dev_priv->fbc.lock);
1749
1750         if (intel_fbc_is_active(dev_priv))
1751                 seq_puts(m, "FBC enabled\n");
1752         else
1753                 seq_printf(m, "FBC disabled: %s\n",
1754                            dev_priv->fbc.no_fbc_reason);
1755
1756         if (INTEL_INFO(dev_priv)->gen >= 7)
1757                 seq_printf(m, "Compressing: %s\n",
1758                            yesno(I915_READ(FBC_STATUS2) &
1759                                  FBC_COMPRESSION_MASK));
1760
1761         mutex_unlock(&dev_priv->fbc.lock);
1762         intel_runtime_pm_put(dev_priv);
1763
1764         return 0;
1765 }
1766
1767 static int i915_fbc_fc_get(void *data, u64 *val)
1768 {
1769         struct drm_device *dev = data;
1770         struct drm_i915_private *dev_priv = to_i915(dev);
1771
1772         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1773                 return -ENODEV;
1774
1775         *val = dev_priv->fbc.false_color;
1776
1777         return 0;
1778 }
1779
1780 static int i915_fbc_fc_set(void *data, u64 val)
1781 {
1782         struct drm_device *dev = data;
1783         struct drm_i915_private *dev_priv = to_i915(dev);
1784         u32 reg;
1785
1786         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1787                 return -ENODEV;
1788
1789         mutex_lock(&dev_priv->fbc.lock);
1790
1791         reg = I915_READ(ILK_DPFC_CONTROL);
1792         dev_priv->fbc.false_color = val;
1793
1794         I915_WRITE(ILK_DPFC_CONTROL, val ?
1795                    (reg | FBC_CTL_FALSE_COLOR) :
1796                    (reg & ~FBC_CTL_FALSE_COLOR));
1797
1798         mutex_unlock(&dev_priv->fbc.lock);
1799         return 0;
1800 }
1801
1802 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1803                         i915_fbc_fc_get, i915_fbc_fc_set,
1804                         "%llu\n");
1805
1806 static int i915_ips_status(struct seq_file *m, void *unused)
1807 {
1808         struct drm_info_node *node = m->private;
1809         struct drm_device *dev = node->minor->dev;
1810         struct drm_i915_private *dev_priv = to_i915(dev);
1811
1812         if (!HAS_IPS(dev)) {
1813                 seq_puts(m, "not supported\n");
1814                 return 0;
1815         }
1816
1817         intel_runtime_pm_get(dev_priv);
1818
1819         seq_printf(m, "Enabled by kernel parameter: %s\n",
1820                    yesno(i915.enable_ips));
1821
1822         if (INTEL_INFO(dev)->gen >= 8) {
1823                 seq_puts(m, "Currently: unknown\n");
1824         } else {
1825                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1826                         seq_puts(m, "Currently: enabled\n");
1827                 else
1828                         seq_puts(m, "Currently: disabled\n");
1829         }
1830
1831         intel_runtime_pm_put(dev_priv);
1832
1833         return 0;
1834 }
1835
1836 static int i915_sr_status(struct seq_file *m, void *unused)
1837 {
1838         struct drm_info_node *node = m->private;
1839         struct drm_device *dev = node->minor->dev;
1840         struct drm_i915_private *dev_priv = to_i915(dev);
1841         bool sr_enabled = false;
1842
1843         intel_runtime_pm_get(dev_priv);
1844
1845         if (HAS_PCH_SPLIT(dev))
1846                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1847         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1848                  IS_I945G(dev) || IS_I945GM(dev))
1849                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1850         else if (IS_I915GM(dev))
1851                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1852         else if (IS_PINEVIEW(dev))
1853                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1854         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1855                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1856
1857         intel_runtime_pm_put(dev_priv);
1858
1859         seq_printf(m, "self-refresh: %s\n",
1860                    sr_enabled ? "enabled" : "disabled");
1861
1862         return 0;
1863 }
1864
1865 static int i915_emon_status(struct seq_file *m, void *unused)
1866 {
1867         struct drm_info_node *node = m->private;
1868         struct drm_device *dev = node->minor->dev;
1869         struct drm_i915_private *dev_priv = to_i915(dev);
1870         unsigned long temp, chipset, gfx;
1871         int ret;
1872
1873         if (!IS_GEN5(dev))
1874                 return -ENODEV;
1875
1876         ret = mutex_lock_interruptible(&dev->struct_mutex);
1877         if (ret)
1878                 return ret;
1879
1880         temp = i915_mch_val(dev_priv);
1881         chipset = i915_chipset_val(dev_priv);
1882         gfx = i915_gfx_val(dev_priv);
1883         mutex_unlock(&dev->struct_mutex);
1884
1885         seq_printf(m, "GMCH temp: %ld\n", temp);
1886         seq_printf(m, "Chipset power: %ld\n", chipset);
1887         seq_printf(m, "GFX power: %ld\n", gfx);
1888         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1889
1890         return 0;
1891 }
1892
1893 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1894 {
1895         struct drm_info_node *node = m->private;
1896         struct drm_device *dev = node->minor->dev;
1897         struct drm_i915_private *dev_priv = to_i915(dev);
1898         int ret = 0;
1899         int gpu_freq, ia_freq;
1900         unsigned int max_gpu_freq, min_gpu_freq;
1901
1902         if (!HAS_CORE_RING_FREQ(dev)) {
1903                 seq_puts(m, "unsupported on this chipset\n");
1904                 return 0;
1905         }
1906
1907         intel_runtime_pm_get(dev_priv);
1908
1909         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1910         if (ret)
1911                 goto out;
1912
1913         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1914                 /* Convert GT frequency to 50 HZ units */
1915                 min_gpu_freq =
1916                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1917                 max_gpu_freq =
1918                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1919         } else {
1920                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1921                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1922         }
1923
1924         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1925
1926         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1927                 ia_freq = gpu_freq;
1928                 sandybridge_pcode_read(dev_priv,
1929                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1930                                        &ia_freq);
1931                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1932                            intel_gpu_freq(dev_priv, (gpu_freq *
1933                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1934                                  GEN9_FREQ_SCALER : 1))),
1935                            ((ia_freq >> 0) & 0xff) * 100,
1936                            ((ia_freq >> 8) & 0xff) * 100);
1937         }
1938
1939         mutex_unlock(&dev_priv->rps.hw_lock);
1940
1941 out:
1942         intel_runtime_pm_put(dev_priv);
1943         return ret;
1944 }
1945
1946 static int i915_opregion(struct seq_file *m, void *unused)
1947 {
1948         struct drm_info_node *node = m->private;
1949         struct drm_device *dev = node->minor->dev;
1950         struct drm_i915_private *dev_priv = to_i915(dev);
1951         struct intel_opregion *opregion = &dev_priv->opregion;
1952         int ret;
1953
1954         ret = mutex_lock_interruptible(&dev->struct_mutex);
1955         if (ret)
1956                 goto out;
1957
1958         if (opregion->header)
1959                 seq_write(m, opregion->header, OPREGION_SIZE);
1960
1961         mutex_unlock(&dev->struct_mutex);
1962
1963 out:
1964         return 0;
1965 }
1966
1967 static int i915_vbt(struct seq_file *m, void *unused)
1968 {
1969         struct drm_info_node *node = m->private;
1970         struct drm_device *dev = node->minor->dev;
1971         struct drm_i915_private *dev_priv = to_i915(dev);
1972         struct intel_opregion *opregion = &dev_priv->opregion;
1973
1974         if (opregion->vbt)
1975                 seq_write(m, opregion->vbt, opregion->vbt_size);
1976
1977         return 0;
1978 }
1979
1980 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1981 {
1982         struct drm_info_node *node = m->private;
1983         struct drm_device *dev = node->minor->dev;
1984         struct intel_framebuffer *fbdev_fb = NULL;
1985         struct drm_framebuffer *drm_fb;
1986         int ret;
1987
1988         ret = mutex_lock_interruptible(&dev->struct_mutex);
1989         if (ret)
1990                 return ret;
1991
1992 #ifdef CONFIG_DRM_FBDEV_EMULATION
1993         if (to_i915(dev)->fbdev) {
1994                 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1995
1996                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1997                            fbdev_fb->base.width,
1998                            fbdev_fb->base.height,
1999                            fbdev_fb->base.depth,
2000                            fbdev_fb->base.bits_per_pixel,
2001                            fbdev_fb->base.modifier[0],
2002                            drm_framebuffer_read_refcount(&fbdev_fb->base));
2003                 describe_obj(m, fbdev_fb->obj);
2004                 seq_putc(m, '\n');
2005         }
2006 #endif
2007
2008         mutex_lock(&dev->mode_config.fb_lock);
2009         drm_for_each_fb(drm_fb, dev) {
2010                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2011                 if (fb == fbdev_fb)
2012                         continue;
2013
2014                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2015                            fb->base.width,
2016                            fb->base.height,
2017                            fb->base.depth,
2018                            fb->base.bits_per_pixel,
2019                            fb->base.modifier[0],
2020                            drm_framebuffer_read_refcount(&fb->base));
2021                 describe_obj(m, fb->obj);
2022                 seq_putc(m, '\n');
2023         }
2024         mutex_unlock(&dev->mode_config.fb_lock);
2025         mutex_unlock(&dev->struct_mutex);
2026
2027         return 0;
2028 }
2029
2030 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
2031 {
2032         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2033                    ring->space, ring->head, ring->tail,
2034                    ring->last_retired_head);
2035 }
2036
2037 static int i915_context_status(struct seq_file *m, void *unused)
2038 {
2039         struct drm_info_node *node = m->private;
2040         struct drm_device *dev = node->minor->dev;
2041         struct drm_i915_private *dev_priv = to_i915(dev);
2042         struct intel_engine_cs *engine;
2043         struct i915_gem_context *ctx;
2044         int ret;
2045
2046         ret = mutex_lock_interruptible(&dev->struct_mutex);
2047         if (ret)
2048                 return ret;
2049
2050         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2051                 seq_printf(m, "HW context %u ", ctx->hw_id);
2052                 if (IS_ERR(ctx->file_priv)) {
2053                         seq_puts(m, "(deleted) ");
2054                 } else if (ctx->file_priv) {
2055                         struct pid *pid = ctx->file_priv->file->pid;
2056                         struct task_struct *task;
2057
2058                         task = get_pid_task(pid, PIDTYPE_PID);
2059                         if (task) {
2060                                 seq_printf(m, "(%s [%d]) ",
2061                                            task->comm, task->pid);
2062                                 put_task_struct(task);
2063                         }
2064                 } else {
2065                         seq_puts(m, "(kernel) ");
2066                 }
2067
2068                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2069                 seq_putc(m, '\n');
2070
2071                 for_each_engine(engine, dev_priv) {
2072                         struct intel_context *ce = &ctx->engine[engine->id];
2073
2074                         seq_printf(m, "%s: ", engine->name);
2075                         seq_putc(m, ce->initialised ? 'I' : 'i');
2076                         if (ce->state)
2077                                 describe_obj(m, ce->state);
2078                         if (ce->ring)
2079                                 describe_ctx_ring(m, ce->ring);
2080                         seq_putc(m, '\n');
2081                 }
2082
2083                 seq_putc(m, '\n');
2084         }
2085
2086         mutex_unlock(&dev->struct_mutex);
2087
2088         return 0;
2089 }
2090
2091 static void i915_dump_lrc_obj(struct seq_file *m,
2092                               struct i915_gem_context *ctx,
2093                               struct intel_engine_cs *engine)
2094 {
2095         struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2096         struct page *page;
2097         uint32_t *reg_state;
2098         int j;
2099         unsigned long ggtt_offset = 0;
2100
2101         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2102
2103         if (ctx_obj == NULL) {
2104                 seq_puts(m, "\tNot allocated\n");
2105                 return;
2106         }
2107
2108         if (!i915_gem_obj_ggtt_bound(ctx_obj))
2109                 seq_puts(m, "\tNot bound in GGTT\n");
2110         else
2111                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2112
2113         if (i915_gem_object_get_pages(ctx_obj)) {
2114                 seq_puts(m, "\tFailed to get pages for context object\n");
2115                 return;
2116         }
2117
2118         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2119         if (!WARN_ON(page == NULL)) {
2120                 reg_state = kmap_atomic(page);
2121
2122                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2123                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2124                                    ggtt_offset + 4096 + (j * 4),
2125                                    reg_state[j], reg_state[j + 1],
2126                                    reg_state[j + 2], reg_state[j + 3]);
2127                 }
2128                 kunmap_atomic(reg_state);
2129         }
2130
2131         seq_putc(m, '\n');
2132 }
2133
2134 static int i915_dump_lrc(struct seq_file *m, void *unused)
2135 {
2136         struct drm_info_node *node = (struct drm_info_node *) m->private;
2137         struct drm_device *dev = node->minor->dev;
2138         struct drm_i915_private *dev_priv = to_i915(dev);
2139         struct intel_engine_cs *engine;
2140         struct i915_gem_context *ctx;
2141         int ret;
2142
2143         if (!i915.enable_execlists) {
2144                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2145                 return 0;
2146         }
2147
2148         ret = mutex_lock_interruptible(&dev->struct_mutex);
2149         if (ret)
2150                 return ret;
2151
2152         list_for_each_entry(ctx, &dev_priv->context_list, link)
2153                 for_each_engine(engine, dev_priv)
2154                         i915_dump_lrc_obj(m, ctx, engine);
2155
2156         mutex_unlock(&dev->struct_mutex);
2157
2158         return 0;
2159 }
2160
2161 static int i915_execlists(struct seq_file *m, void *data)
2162 {
2163         struct drm_info_node *node = (struct drm_info_node *)m->private;
2164         struct drm_device *dev = node->minor->dev;
2165         struct drm_i915_private *dev_priv = to_i915(dev);
2166         struct intel_engine_cs *engine;
2167         u32 status_pointer;
2168         u8 read_pointer;
2169         u8 write_pointer;
2170         u32 status;
2171         u32 ctx_id;
2172         struct list_head *cursor;
2173         int i, ret;
2174
2175         if (!i915.enable_execlists) {
2176                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2177                 return 0;
2178         }
2179
2180         ret = mutex_lock_interruptible(&dev->struct_mutex);
2181         if (ret)
2182                 return ret;
2183
2184         intel_runtime_pm_get(dev_priv);
2185
2186         for_each_engine(engine, dev_priv) {
2187                 struct drm_i915_gem_request *head_req = NULL;
2188                 int count = 0;
2189
2190                 seq_printf(m, "%s\n", engine->name);
2191
2192                 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2193                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2194                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2195                            status, ctx_id);
2196
2197                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2198                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2199
2200                 read_pointer = engine->next_context_status_buffer;
2201                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2202                 if (read_pointer > write_pointer)
2203                         write_pointer += GEN8_CSB_ENTRIES;
2204                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2205                            read_pointer, write_pointer);
2206
2207                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2208                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2209                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2210
2211                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2212                                    i, status, ctx_id);
2213                 }
2214
2215                 spin_lock_bh(&engine->execlist_lock);
2216                 list_for_each(cursor, &engine->execlist_queue)
2217                         count++;
2218                 head_req = list_first_entry_or_null(&engine->execlist_queue,
2219                                                     struct drm_i915_gem_request,
2220                                                     execlist_link);
2221                 spin_unlock_bh(&engine->execlist_lock);
2222
2223                 seq_printf(m, "\t%d requests in queue\n", count);
2224                 if (head_req) {
2225                         seq_printf(m, "\tHead request context: %u\n",
2226                                    head_req->ctx->hw_id);
2227                         seq_printf(m, "\tHead request tail: %u\n",
2228                                    head_req->tail);
2229                 }
2230
2231                 seq_putc(m, '\n');
2232         }
2233
2234         intel_runtime_pm_put(dev_priv);
2235         mutex_unlock(&dev->struct_mutex);
2236
2237         return 0;
2238 }
2239
2240 static const char *swizzle_string(unsigned swizzle)
2241 {
2242         switch (swizzle) {
2243         case I915_BIT_6_SWIZZLE_NONE:
2244                 return "none";
2245         case I915_BIT_6_SWIZZLE_9:
2246                 return "bit9";
2247         case I915_BIT_6_SWIZZLE_9_10:
2248                 return "bit9/bit10";
2249         case I915_BIT_6_SWIZZLE_9_11:
2250                 return "bit9/bit11";
2251         case I915_BIT_6_SWIZZLE_9_10_11:
2252                 return "bit9/bit10/bit11";
2253         case I915_BIT_6_SWIZZLE_9_17:
2254                 return "bit9/bit17";
2255         case I915_BIT_6_SWIZZLE_9_10_17:
2256                 return "bit9/bit10/bit17";
2257         case I915_BIT_6_SWIZZLE_UNKNOWN:
2258                 return "unknown";
2259         }
2260
2261         return "bug";
2262 }
2263
2264 static int i915_swizzle_info(struct seq_file *m, void *data)
2265 {
2266         struct drm_info_node *node = m->private;
2267         struct drm_device *dev = node->minor->dev;
2268         struct drm_i915_private *dev_priv = to_i915(dev);
2269         int ret;
2270
2271         ret = mutex_lock_interruptible(&dev->struct_mutex);
2272         if (ret)
2273                 return ret;
2274         intel_runtime_pm_get(dev_priv);
2275
2276         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2277                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2278         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2279                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2280
2281         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2282                 seq_printf(m, "DDC = 0x%08x\n",
2283                            I915_READ(DCC));
2284                 seq_printf(m, "DDC2 = 0x%08x\n",
2285                            I915_READ(DCC2));
2286                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2287                            I915_READ16(C0DRB3));
2288                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2289                            I915_READ16(C1DRB3));
2290         } else if (INTEL_INFO(dev)->gen >= 6) {
2291                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2292                            I915_READ(MAD_DIMM_C0));
2293                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2294                            I915_READ(MAD_DIMM_C1));
2295                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2296                            I915_READ(MAD_DIMM_C2));
2297                 seq_printf(m, "TILECTL = 0x%08x\n",
2298                            I915_READ(TILECTL));
2299                 if (INTEL_INFO(dev)->gen >= 8)
2300                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2301                                    I915_READ(GAMTARBMODE));
2302                 else
2303                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2304                                    I915_READ(ARB_MODE));
2305                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2306                            I915_READ(DISP_ARB_CTL));
2307         }
2308
2309         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2310                 seq_puts(m, "L-shaped memory detected\n");
2311
2312         intel_runtime_pm_put(dev_priv);
2313         mutex_unlock(&dev->struct_mutex);
2314
2315         return 0;
2316 }
2317
2318 static int per_file_ctx(int id, void *ptr, void *data)
2319 {
2320         struct i915_gem_context *ctx = ptr;
2321         struct seq_file *m = data;
2322         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2323
2324         if (!ppgtt) {
2325                 seq_printf(m, "  no ppgtt for context %d\n",
2326                            ctx->user_handle);
2327                 return 0;
2328         }
2329
2330         if (i915_gem_context_is_default(ctx))
2331                 seq_puts(m, "  default context:\n");
2332         else
2333                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2334         ppgtt->debug_dump(ppgtt, m);
2335
2336         return 0;
2337 }
2338
2339 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2340 {
2341         struct drm_i915_private *dev_priv = to_i915(dev);
2342         struct intel_engine_cs *engine;
2343         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2344         int i;
2345
2346         if (!ppgtt)
2347                 return;
2348
2349         for_each_engine(engine, dev_priv) {
2350                 seq_printf(m, "%s\n", engine->name);
2351                 for (i = 0; i < 4; i++) {
2352                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2353                         pdp <<= 32;
2354                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2355                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2356                 }
2357         }
2358 }
2359
2360 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2361 {
2362         struct drm_i915_private *dev_priv = to_i915(dev);
2363         struct intel_engine_cs *engine;
2364
2365         if (IS_GEN6(dev_priv))
2366                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2367
2368         for_each_engine(engine, dev_priv) {
2369                 seq_printf(m, "%s\n", engine->name);
2370                 if (IS_GEN7(dev_priv))
2371                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2372                                    I915_READ(RING_MODE_GEN7(engine)));
2373                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2374                            I915_READ(RING_PP_DIR_BASE(engine)));
2375                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2376                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2377                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2378                            I915_READ(RING_PP_DIR_DCLV(engine)));
2379         }
2380         if (dev_priv->mm.aliasing_ppgtt) {
2381                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2382
2383                 seq_puts(m, "aliasing PPGTT:\n");
2384                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2385
2386                 ppgtt->debug_dump(ppgtt, m);
2387         }
2388
2389         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2390 }
2391
2392 static int i915_ppgtt_info(struct seq_file *m, void *data)
2393 {
2394         struct drm_info_node *node = m->private;
2395         struct drm_device *dev = node->minor->dev;
2396         struct drm_i915_private *dev_priv = to_i915(dev);
2397         struct drm_file *file;
2398
2399         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2400         if (ret)
2401                 return ret;
2402         intel_runtime_pm_get(dev_priv);
2403
2404         if (INTEL_INFO(dev)->gen >= 8)
2405                 gen8_ppgtt_info(m, dev);
2406         else if (INTEL_INFO(dev)->gen >= 6)
2407                 gen6_ppgtt_info(m, dev);
2408
2409         mutex_lock(&dev->filelist_mutex);
2410         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2411                 struct drm_i915_file_private *file_priv = file->driver_priv;
2412                 struct task_struct *task;
2413
2414                 task = get_pid_task(file->pid, PIDTYPE_PID);
2415                 if (!task) {
2416                         ret = -ESRCH;
2417                         goto out_unlock;
2418                 }
2419                 seq_printf(m, "\nproc: %s\n", task->comm);
2420                 put_task_struct(task);
2421                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2422                              (void *)(unsigned long)m);
2423         }
2424 out_unlock:
2425         mutex_unlock(&dev->filelist_mutex);
2426
2427         intel_runtime_pm_put(dev_priv);
2428         mutex_unlock(&dev->struct_mutex);
2429
2430         return ret;
2431 }
2432
2433 static int count_irq_waiters(struct drm_i915_private *i915)
2434 {
2435         struct intel_engine_cs *engine;
2436         int count = 0;
2437
2438         for_each_engine(engine, i915)
2439                 count += intel_engine_has_waiter(engine);
2440
2441         return count;
2442 }
2443
2444 static int i915_rps_boost_info(struct seq_file *m, void *data)
2445 {
2446         struct drm_info_node *node = m->private;
2447         struct drm_device *dev = node->minor->dev;
2448         struct drm_i915_private *dev_priv = to_i915(dev);
2449         struct drm_file *file;
2450
2451         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2452         seq_printf(m, "GPU busy? %s [%x]\n",
2453                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2454         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2455         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2456                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2457                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2458                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2459                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2460                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2461
2462         mutex_lock(&dev->filelist_mutex);
2463         spin_lock(&dev_priv->rps.client_lock);
2464         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2465                 struct drm_i915_file_private *file_priv = file->driver_priv;
2466                 struct task_struct *task;
2467
2468                 rcu_read_lock();
2469                 task = pid_task(file->pid, PIDTYPE_PID);
2470                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2471                            task ? task->comm : "<unknown>",
2472                            task ? task->pid : -1,
2473                            file_priv->rps.boosts,
2474                            list_empty(&file_priv->rps.link) ? "" : ", active");
2475                 rcu_read_unlock();
2476         }
2477         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2478         spin_unlock(&dev_priv->rps.client_lock);
2479         mutex_unlock(&dev->filelist_mutex);
2480
2481         return 0;
2482 }
2483
2484 static int i915_llc(struct seq_file *m, void *data)
2485 {
2486         struct drm_info_node *node = m->private;
2487         struct drm_device *dev = node->minor->dev;
2488         struct drm_i915_private *dev_priv = to_i915(dev);
2489         const bool edram = INTEL_GEN(dev_priv) > 8;
2490
2491         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2492         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2493                    intel_uncore_edram_size(dev_priv)/1024/1024);
2494
2495         return 0;
2496 }
2497
2498 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2499 {
2500         struct drm_info_node *node = m->private;
2501         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2502         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2503         u32 tmp, i;
2504
2505         if (!HAS_GUC_UCODE(dev_priv))
2506                 return 0;
2507
2508         seq_printf(m, "GuC firmware status:\n");
2509         seq_printf(m, "\tpath: %s\n",
2510                 guc_fw->guc_fw_path);
2511         seq_printf(m, "\tfetch: %s\n",
2512                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2513         seq_printf(m, "\tload: %s\n",
2514                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2515         seq_printf(m, "\tversion wanted: %d.%d\n",
2516                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2517         seq_printf(m, "\tversion found: %d.%d\n",
2518                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2519         seq_printf(m, "\theader: offset is %d; size = %d\n",
2520                 guc_fw->header_offset, guc_fw->header_size);
2521         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2522                 guc_fw->ucode_offset, guc_fw->ucode_size);
2523         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2524                 guc_fw->rsa_offset, guc_fw->rsa_size);
2525
2526         tmp = I915_READ(GUC_STATUS);
2527
2528         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2529         seq_printf(m, "\tBootrom status = 0x%x\n",
2530                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2531         seq_printf(m, "\tuKernel status = 0x%x\n",
2532                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2533         seq_printf(m, "\tMIA Core status = 0x%x\n",
2534                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2535         seq_puts(m, "\nScratch registers:\n");
2536         for (i = 0; i < 16; i++)
2537                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2538
2539         return 0;
2540 }
2541
2542 static void i915_guc_client_info(struct seq_file *m,
2543                                  struct drm_i915_private *dev_priv,
2544                                  struct i915_guc_client *client)
2545 {
2546         struct intel_engine_cs *engine;
2547         enum intel_engine_id id;
2548         uint64_t tot = 0;
2549
2550         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2551                 client->priority, client->ctx_index, client->proc_desc_offset);
2552         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2553                 client->doorbell_id, client->doorbell_offset, client->cookie);
2554         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2555                 client->wq_size, client->wq_offset, client->wq_tail);
2556
2557         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2558         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2559         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2560
2561         for_each_engine_id(engine, dev_priv, id) {
2562                 u64 submissions = client->submissions[id];
2563                 tot += submissions;
2564                 seq_printf(m, "\tSubmissions: %llu %s\n",
2565                                 submissions, engine->name);
2566         }
2567         seq_printf(m, "\tTotal: %llu\n", tot);
2568 }
2569
2570 static int i915_guc_info(struct seq_file *m, void *data)
2571 {
2572         struct drm_info_node *node = m->private;
2573         struct drm_device *dev = node->minor->dev;
2574         struct drm_i915_private *dev_priv = to_i915(dev);
2575         struct intel_guc guc;
2576         struct i915_guc_client client = {};
2577         struct intel_engine_cs *engine;
2578         enum intel_engine_id id;
2579         u64 total = 0;
2580
2581         if (!HAS_GUC_SCHED(dev_priv))
2582                 return 0;
2583
2584         if (mutex_lock_interruptible(&dev->struct_mutex))
2585                 return 0;
2586
2587         /* Take a local copy of the GuC data, so we can dump it at leisure */
2588         guc = dev_priv->guc;
2589         if (guc.execbuf_client)
2590                 client = *guc.execbuf_client;
2591
2592         mutex_unlock(&dev->struct_mutex);
2593
2594         seq_printf(m, "Doorbell map:\n");
2595         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2596         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2597
2598         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2599         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2600         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2601         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2602         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2603
2604         seq_printf(m, "\nGuC submissions:\n");
2605         for_each_engine_id(engine, dev_priv, id) {
2606                 u64 submissions = guc.submissions[id];
2607                 total += submissions;
2608                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2609                         engine->name, submissions, guc.last_seqno[id]);
2610         }
2611         seq_printf(m, "\t%s: %llu\n", "Total", total);
2612
2613         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2614         i915_guc_client_info(m, dev_priv, &client);
2615
2616         /* Add more as required ... */
2617
2618         return 0;
2619 }
2620
2621 static int i915_guc_log_dump(struct seq_file *m, void *data)
2622 {
2623         struct drm_info_node *node = m->private;
2624         struct drm_device *dev = node->minor->dev;
2625         struct drm_i915_private *dev_priv = to_i915(dev);
2626         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2627         u32 *log;
2628         int i = 0, pg;
2629
2630         if (!log_obj)
2631                 return 0;
2632
2633         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2634                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2635
2636                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2637                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2638                                    *(log + i), *(log + i + 1),
2639                                    *(log + i + 2), *(log + i + 3));
2640
2641                 kunmap_atomic(log);
2642         }
2643
2644         seq_putc(m, '\n');
2645
2646         return 0;
2647 }
2648
2649 static int i915_edp_psr_status(struct seq_file *m, void *data)
2650 {
2651         struct drm_info_node *node = m->private;
2652         struct drm_device *dev = node->minor->dev;
2653         struct drm_i915_private *dev_priv = to_i915(dev);
2654         u32 psrperf = 0;
2655         u32 stat[3];
2656         enum pipe pipe;
2657         bool enabled = false;
2658
2659         if (!HAS_PSR(dev)) {
2660                 seq_puts(m, "PSR not supported\n");
2661                 return 0;
2662         }
2663
2664         intel_runtime_pm_get(dev_priv);
2665
2666         mutex_lock(&dev_priv->psr.lock);
2667         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2668         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2669         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2670         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2671         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2672                    dev_priv->psr.busy_frontbuffer_bits);
2673         seq_printf(m, "Re-enable work scheduled: %s\n",
2674                    yesno(work_busy(&dev_priv->psr.work.work)));
2675
2676         if (HAS_DDI(dev))
2677                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2678         else {
2679                 for_each_pipe(dev_priv, pipe) {
2680                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2681                                 VLV_EDP_PSR_CURR_STATE_MASK;
2682                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2683                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2684                                 enabled = true;
2685                 }
2686         }
2687
2688         seq_printf(m, "Main link in standby mode: %s\n",
2689                    yesno(dev_priv->psr.link_standby));
2690
2691         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2692
2693         if (!HAS_DDI(dev))
2694                 for_each_pipe(dev_priv, pipe) {
2695                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2696                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2697                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2698                 }
2699         seq_puts(m, "\n");
2700
2701         /*
2702          * VLV/CHV PSR has no kind of performance counter
2703          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2704          */
2705         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2706                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2707                         EDP_PSR_PERF_CNT_MASK;
2708
2709                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2710         }
2711         mutex_unlock(&dev_priv->psr.lock);
2712
2713         intel_runtime_pm_put(dev_priv);
2714         return 0;
2715 }
2716
2717 static int i915_sink_crc(struct seq_file *m, void *data)
2718 {
2719         struct drm_info_node *node = m->private;
2720         struct drm_device *dev = node->minor->dev;
2721         struct intel_connector *connector;
2722         struct intel_dp *intel_dp = NULL;
2723         int ret;
2724         u8 crc[6];
2725
2726         drm_modeset_lock_all(dev);
2727         for_each_intel_connector(dev, connector) {
2728                 struct drm_crtc *crtc;
2729
2730                 if (!connector->base.state->best_encoder)
2731                         continue;
2732
2733                 crtc = connector->base.state->crtc;
2734                 if (!crtc->state->active)
2735                         continue;
2736
2737                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2738                         continue;
2739
2740                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2741
2742                 ret = intel_dp_sink_crc(intel_dp, crc);
2743                 if (ret)
2744                         goto out;
2745
2746                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2747                            crc[0], crc[1], crc[2],
2748                            crc[3], crc[4], crc[5]);
2749                 goto out;
2750         }
2751         ret = -ENODEV;
2752 out:
2753         drm_modeset_unlock_all(dev);
2754         return ret;
2755 }
2756
2757 static int i915_energy_uJ(struct seq_file *m, void *data)
2758 {
2759         struct drm_info_node *node = m->private;
2760         struct drm_device *dev = node->minor->dev;
2761         struct drm_i915_private *dev_priv = to_i915(dev);
2762         u64 power;
2763         u32 units;
2764
2765         if (INTEL_INFO(dev)->gen < 6)
2766                 return -ENODEV;
2767
2768         intel_runtime_pm_get(dev_priv);
2769
2770         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2771         power = (power & 0x1f00) >> 8;
2772         units = 1000000 / (1 << power); /* convert to uJ */
2773         power = I915_READ(MCH_SECP_NRG_STTS);
2774         power *= units;
2775
2776         intel_runtime_pm_put(dev_priv);
2777
2778         seq_printf(m, "%llu", (long long unsigned)power);
2779
2780         return 0;
2781 }
2782
2783 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2784 {
2785         struct drm_info_node *node = m->private;
2786         struct drm_device *dev = node->minor->dev;
2787         struct drm_i915_private *dev_priv = to_i915(dev);
2788
2789         if (!HAS_RUNTIME_PM(dev_priv))
2790                 seq_puts(m, "Runtime power management not supported\n");
2791
2792         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2793         seq_printf(m, "IRQs disabled: %s\n",
2794                    yesno(!intel_irqs_enabled(dev_priv)));
2795 #ifdef CONFIG_PM
2796         seq_printf(m, "Usage count: %d\n",
2797                    atomic_read(&dev->dev->power.usage_count));
2798 #else
2799         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2800 #endif
2801         seq_printf(m, "PCI device power state: %s [%d]\n",
2802                    pci_power_name(dev_priv->drm.pdev->current_state),
2803                    dev_priv->drm.pdev->current_state);
2804
2805         return 0;
2806 }
2807
2808 static int i915_power_domain_info(struct seq_file *m, void *unused)
2809 {
2810         struct drm_info_node *node = m->private;
2811         struct drm_device *dev = node->minor->dev;
2812         struct drm_i915_private *dev_priv = to_i915(dev);
2813         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2814         int i;
2815
2816         mutex_lock(&power_domains->lock);
2817
2818         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2819         for (i = 0; i < power_domains->power_well_count; i++) {
2820                 struct i915_power_well *power_well;
2821                 enum intel_display_power_domain power_domain;
2822
2823                 power_well = &power_domains->power_wells[i];
2824                 seq_printf(m, "%-25s %d\n", power_well->name,
2825                            power_well->count);
2826
2827                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2828                      power_domain++) {
2829                         if (!(BIT(power_domain) & power_well->domains))
2830                                 continue;
2831
2832                         seq_printf(m, "  %-23s %d\n",
2833                                  intel_display_power_domain_str(power_domain),
2834                                  power_domains->domain_use_count[power_domain]);
2835                 }
2836         }
2837
2838         mutex_unlock(&power_domains->lock);
2839
2840         return 0;
2841 }
2842
2843 static int i915_dmc_info(struct seq_file *m, void *unused)
2844 {
2845         struct drm_info_node *node = m->private;
2846         struct drm_device *dev = node->minor->dev;
2847         struct drm_i915_private *dev_priv = to_i915(dev);
2848         struct intel_csr *csr;
2849
2850         if (!HAS_CSR(dev)) {
2851                 seq_puts(m, "not supported\n");
2852                 return 0;
2853         }
2854
2855         csr = &dev_priv->csr;
2856
2857         intel_runtime_pm_get(dev_priv);
2858
2859         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2860         seq_printf(m, "path: %s\n", csr->fw_path);
2861
2862         if (!csr->dmc_payload)
2863                 goto out;
2864
2865         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2866                    CSR_VERSION_MINOR(csr->version));
2867
2868         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2869                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2870                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2871                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2872                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2873         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2874                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2875                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2876         }
2877
2878 out:
2879         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2880         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2881         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2882
2883         intel_runtime_pm_put(dev_priv);
2884
2885         return 0;
2886 }
2887
2888 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2889                                  struct drm_display_mode *mode)
2890 {
2891         int i;
2892
2893         for (i = 0; i < tabs; i++)
2894                 seq_putc(m, '\t');
2895
2896         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2897                    mode->base.id, mode->name,
2898                    mode->vrefresh, mode->clock,
2899                    mode->hdisplay, mode->hsync_start,
2900                    mode->hsync_end, mode->htotal,
2901                    mode->vdisplay, mode->vsync_start,
2902                    mode->vsync_end, mode->vtotal,
2903                    mode->type, mode->flags);
2904 }
2905
2906 static void intel_encoder_info(struct seq_file *m,
2907                                struct intel_crtc *intel_crtc,
2908                                struct intel_encoder *intel_encoder)
2909 {
2910         struct drm_info_node *node = m->private;
2911         struct drm_device *dev = node->minor->dev;
2912         struct drm_crtc *crtc = &intel_crtc->base;
2913         struct intel_connector *intel_connector;
2914         struct drm_encoder *encoder;
2915
2916         encoder = &intel_encoder->base;
2917         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2918                    encoder->base.id, encoder->name);
2919         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2920                 struct drm_connector *connector = &intel_connector->base;
2921                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2922                            connector->base.id,
2923                            connector->name,
2924                            drm_get_connector_status_name(connector->status));
2925                 if (connector->status == connector_status_connected) {
2926                         struct drm_display_mode *mode = &crtc->mode;
2927                         seq_printf(m, ", mode:\n");
2928                         intel_seq_print_mode(m, 2, mode);
2929                 } else {
2930                         seq_putc(m, '\n');
2931                 }
2932         }
2933 }
2934
2935 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2936 {
2937         struct drm_info_node *node = m->private;
2938         struct drm_device *dev = node->minor->dev;
2939         struct drm_crtc *crtc = &intel_crtc->base;
2940         struct intel_encoder *intel_encoder;
2941         struct drm_plane_state *plane_state = crtc->primary->state;
2942         struct drm_framebuffer *fb = plane_state->fb;
2943
2944         if (fb)
2945                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2946                            fb->base.id, plane_state->src_x >> 16,
2947                            plane_state->src_y >> 16, fb->width, fb->height);
2948         else
2949                 seq_puts(m, "\tprimary plane disabled\n");
2950         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2951                 intel_encoder_info(m, intel_crtc, intel_encoder);
2952 }
2953
2954 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2955 {
2956         struct drm_display_mode *mode = panel->fixed_mode;
2957
2958         seq_printf(m, "\tfixed mode:\n");
2959         intel_seq_print_mode(m, 2, mode);
2960 }
2961
2962 static void intel_dp_info(struct seq_file *m,
2963                           struct intel_connector *intel_connector)
2964 {
2965         struct intel_encoder *intel_encoder = intel_connector->encoder;
2966         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2967
2968         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2969         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2970         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2971                 intel_panel_info(m, &intel_connector->panel);
2972 }
2973
2974 static void intel_hdmi_info(struct seq_file *m,
2975                             struct intel_connector *intel_connector)
2976 {
2977         struct intel_encoder *intel_encoder = intel_connector->encoder;
2978         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2979
2980         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2981 }
2982
2983 static void intel_lvds_info(struct seq_file *m,
2984                             struct intel_connector *intel_connector)
2985 {
2986         intel_panel_info(m, &intel_connector->panel);
2987 }
2988
2989 static void intel_connector_info(struct seq_file *m,
2990                                  struct drm_connector *connector)
2991 {
2992         struct intel_connector *intel_connector = to_intel_connector(connector);
2993         struct intel_encoder *intel_encoder = intel_connector->encoder;
2994         struct drm_display_mode *mode;
2995
2996         seq_printf(m, "connector %d: type %s, status: %s\n",
2997                    connector->base.id, connector->name,
2998                    drm_get_connector_status_name(connector->status));
2999         if (connector->status == connector_status_connected) {
3000                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3001                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3002                            connector->display_info.width_mm,
3003                            connector->display_info.height_mm);
3004                 seq_printf(m, "\tsubpixel order: %s\n",
3005                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3006                 seq_printf(m, "\tCEA rev: %d\n",
3007                            connector->display_info.cea_rev);
3008         }
3009
3010         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3011                 return;
3012
3013         switch (connector->connector_type) {
3014         case DRM_MODE_CONNECTOR_DisplayPort:
3015         case DRM_MODE_CONNECTOR_eDP:
3016                 intel_dp_info(m, intel_connector);
3017                 break;
3018         case DRM_MODE_CONNECTOR_LVDS:
3019                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3020                         intel_lvds_info(m, intel_connector);
3021                 break;
3022         case DRM_MODE_CONNECTOR_HDMIA:
3023                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3024                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3025                         intel_hdmi_info(m, intel_connector);
3026                 break;
3027         default:
3028                 break;
3029         }
3030
3031         seq_printf(m, "\tmodes:\n");
3032         list_for_each_entry(mode, &connector->modes, head)
3033                 intel_seq_print_mode(m, 2, mode);
3034 }
3035
3036 static bool cursor_active(struct drm_device *dev, int pipe)
3037 {
3038         struct drm_i915_private *dev_priv = to_i915(dev);
3039         u32 state;
3040
3041         if (IS_845G(dev) || IS_I865G(dev))
3042                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3043         else
3044                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3045
3046         return state;
3047 }
3048
3049 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3050 {
3051         struct drm_i915_private *dev_priv = to_i915(dev);
3052         u32 pos;
3053
3054         pos = I915_READ(CURPOS(pipe));
3055
3056         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3057         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3058                 *x = -*x;
3059
3060         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3061         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3062                 *y = -*y;
3063
3064         return cursor_active(dev, pipe);
3065 }
3066
3067 static const char *plane_type(enum drm_plane_type type)
3068 {
3069         switch (type) {
3070         case DRM_PLANE_TYPE_OVERLAY:
3071                 return "OVL";
3072         case DRM_PLANE_TYPE_PRIMARY:
3073                 return "PRI";
3074         case DRM_PLANE_TYPE_CURSOR:
3075                 return "CUR";
3076         /*
3077          * Deliberately omitting default: to generate compiler warnings
3078          * when a new drm_plane_type gets added.
3079          */
3080         }
3081
3082         return "unknown";
3083 }
3084
3085 static const char *plane_rotation(unsigned int rotation)
3086 {
3087         static char buf[48];
3088         /*
3089          * According to doc only one DRM_ROTATE_ is allowed but this
3090          * will print them all to visualize if the values are misused
3091          */
3092         snprintf(buf, sizeof(buf),
3093                  "%s%s%s%s%s%s(0x%08x)",
3094                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3095                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3096                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3097                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3098                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3099                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3100                  rotation);
3101
3102         return buf;
3103 }
3104
3105 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3106 {
3107         struct drm_info_node *node = m->private;
3108         struct drm_device *dev = node->minor->dev;
3109         struct intel_plane *intel_plane;
3110
3111         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3112                 struct drm_plane_state *state;
3113                 struct drm_plane *plane = &intel_plane->base;
3114
3115                 if (!plane->state) {
3116                         seq_puts(m, "plane->state is NULL!\n");
3117                         continue;
3118                 }
3119
3120                 state = plane->state;
3121
3122                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3123                            plane->base.id,
3124                            plane_type(intel_plane->base.type),
3125                            state->crtc_x, state->crtc_y,
3126                            state->crtc_w, state->crtc_h,
3127                            (state->src_x >> 16),
3128                            ((state->src_x & 0xffff) * 15625) >> 10,
3129                            (state->src_y >> 16),
3130                            ((state->src_y & 0xffff) * 15625) >> 10,
3131                            (state->src_w >> 16),
3132                            ((state->src_w & 0xffff) * 15625) >> 10,
3133                            (state->src_h >> 16),
3134                            ((state->src_h & 0xffff) * 15625) >> 10,
3135                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3136                            plane_rotation(state->rotation));
3137         }
3138 }
3139
3140 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3141 {
3142         struct intel_crtc_state *pipe_config;
3143         int num_scalers = intel_crtc->num_scalers;
3144         int i;
3145
3146         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3147
3148         /* Not all platformas have a scaler */
3149         if (num_scalers) {
3150                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3151                            num_scalers,
3152                            pipe_config->scaler_state.scaler_users,
3153                            pipe_config->scaler_state.scaler_id);
3154
3155                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3156                         struct intel_scaler *sc =
3157                                         &pipe_config->scaler_state.scalers[i];
3158
3159                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3160                                    i, yesno(sc->in_use), sc->mode);
3161                 }
3162                 seq_puts(m, "\n");
3163         } else {
3164                 seq_puts(m, "\tNo scalers available on this platform\n");
3165         }
3166 }
3167
3168 static int i915_display_info(struct seq_file *m, void *unused)
3169 {
3170         struct drm_info_node *node = m->private;
3171         struct drm_device *dev = node->minor->dev;
3172         struct drm_i915_private *dev_priv = to_i915(dev);
3173         struct intel_crtc *crtc;
3174         struct drm_connector *connector;
3175
3176         intel_runtime_pm_get(dev_priv);
3177         drm_modeset_lock_all(dev);
3178         seq_printf(m, "CRTC info\n");
3179         seq_printf(m, "---------\n");
3180         for_each_intel_crtc(dev, crtc) {
3181                 bool active;
3182                 struct intel_crtc_state *pipe_config;
3183                 int x, y;
3184
3185                 pipe_config = to_intel_crtc_state(crtc->base.state);
3186
3187                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3188                            crtc->base.base.id, pipe_name(crtc->pipe),
3189                            yesno(pipe_config->base.active),
3190                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3191                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3192
3193                 if (pipe_config->base.active) {
3194                         intel_crtc_info(m, crtc);
3195
3196                         active = cursor_position(dev, crtc->pipe, &x, &y);
3197                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3198                                    yesno(crtc->cursor_base),
3199                                    x, y, crtc->base.cursor->state->crtc_w,
3200                                    crtc->base.cursor->state->crtc_h,
3201                                    crtc->cursor_addr, yesno(active));
3202                         intel_scaler_info(m, crtc);
3203                         intel_plane_info(m, crtc);
3204                 }
3205
3206                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3207                            yesno(!crtc->cpu_fifo_underrun_disabled),
3208                            yesno(!crtc->pch_fifo_underrun_disabled));
3209         }
3210
3211         seq_printf(m, "\n");
3212         seq_printf(m, "Connector info\n");
3213         seq_printf(m, "--------------\n");
3214         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3215                 intel_connector_info(m, connector);
3216         }
3217         drm_modeset_unlock_all(dev);
3218         intel_runtime_pm_put(dev_priv);
3219
3220         return 0;
3221 }
3222
3223 static int i915_semaphore_status(struct seq_file *m, void *unused)
3224 {
3225         struct drm_info_node *node = (struct drm_info_node *) m->private;
3226         struct drm_device *dev = node->minor->dev;
3227         struct drm_i915_private *dev_priv = to_i915(dev);
3228         struct intel_engine_cs *engine;
3229         int num_rings = INTEL_INFO(dev)->num_rings;
3230         enum intel_engine_id id;
3231         int j, ret;
3232
3233         if (!i915.semaphores) {
3234                 seq_puts(m, "Semaphores are disabled\n");
3235                 return 0;
3236         }
3237
3238         ret = mutex_lock_interruptible(&dev->struct_mutex);
3239         if (ret)
3240                 return ret;
3241         intel_runtime_pm_get(dev_priv);
3242
3243         if (IS_BROADWELL(dev)) {
3244                 struct page *page;
3245                 uint64_t *seqno;
3246
3247                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3248
3249                 seqno = (uint64_t *)kmap_atomic(page);
3250                 for_each_engine_id(engine, dev_priv, id) {
3251                         uint64_t offset;
3252
3253                         seq_printf(m, "%s\n", engine->name);
3254
3255                         seq_puts(m, "  Last signal:");
3256                         for (j = 0; j < num_rings; j++) {
3257                                 offset = id * I915_NUM_ENGINES + j;
3258                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3259                                            seqno[offset], offset * 8);
3260                         }
3261                         seq_putc(m, '\n');
3262
3263                         seq_puts(m, "  Last wait:  ");
3264                         for (j = 0; j < num_rings; j++) {
3265                                 offset = id + (j * I915_NUM_ENGINES);
3266                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3267                                            seqno[offset], offset * 8);
3268                         }
3269                         seq_putc(m, '\n');
3270
3271                 }
3272                 kunmap_atomic(seqno);
3273         } else {
3274                 seq_puts(m, "  Last signal:");
3275                 for_each_engine(engine, dev_priv)
3276                         for (j = 0; j < num_rings; j++)
3277                                 seq_printf(m, "0x%08x\n",
3278                                            I915_READ(engine->semaphore.mbox.signal[j]));
3279                 seq_putc(m, '\n');
3280         }
3281
3282         seq_puts(m, "\nSync seqno:\n");
3283         for_each_engine(engine, dev_priv) {
3284                 for (j = 0; j < num_rings; j++)
3285                         seq_printf(m, "  0x%08x ",
3286                                    engine->semaphore.sync_seqno[j]);
3287                 seq_putc(m, '\n');
3288         }
3289         seq_putc(m, '\n');
3290
3291         intel_runtime_pm_put(dev_priv);
3292         mutex_unlock(&dev->struct_mutex);
3293         return 0;
3294 }
3295
3296 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3297 {
3298         struct drm_info_node *node = (struct drm_info_node *) m->private;
3299         struct drm_device *dev = node->minor->dev;
3300         struct drm_i915_private *dev_priv = to_i915(dev);
3301         int i;
3302
3303         drm_modeset_lock_all(dev);
3304         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3305                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3306
3307                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3308                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3309                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3310                 seq_printf(m, " tracked hardware state:\n");
3311                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3312                 seq_printf(m, " dpll_md: 0x%08x\n",
3313                            pll->config.hw_state.dpll_md);
3314                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3315                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3316                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3317         }
3318         drm_modeset_unlock_all(dev);
3319
3320         return 0;
3321 }
3322
3323 static int i915_wa_registers(struct seq_file *m, void *unused)
3324 {
3325         int i;
3326         int ret;
3327         struct intel_engine_cs *engine;
3328         struct drm_info_node *node = (struct drm_info_node *) m->private;
3329         struct drm_device *dev = node->minor->dev;
3330         struct drm_i915_private *dev_priv = to_i915(dev);
3331         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3332         enum intel_engine_id id;
3333
3334         ret = mutex_lock_interruptible(&dev->struct_mutex);
3335         if (ret)
3336                 return ret;
3337
3338         intel_runtime_pm_get(dev_priv);
3339
3340         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3341         for_each_engine_id(engine, dev_priv, id)
3342                 seq_printf(m, "HW whitelist count for %s: %d\n",
3343                            engine->name, workarounds->hw_whitelist_count[id]);
3344         for (i = 0; i < workarounds->count; ++i) {
3345                 i915_reg_t addr;
3346                 u32 mask, value, read;
3347                 bool ok;
3348
3349                 addr = workarounds->reg[i].addr;
3350                 mask = workarounds->reg[i].mask;
3351                 value = workarounds->reg[i].value;
3352                 read = I915_READ(addr);
3353                 ok = (value & mask) == (read & mask);
3354                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3355                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3356         }
3357
3358         intel_runtime_pm_put(dev_priv);
3359         mutex_unlock(&dev->struct_mutex);
3360
3361         return 0;
3362 }
3363
3364 static int i915_ddb_info(struct seq_file *m, void *unused)
3365 {
3366         struct drm_info_node *node = m->private;
3367         struct drm_device *dev = node->minor->dev;
3368         struct drm_i915_private *dev_priv = to_i915(dev);
3369         struct skl_ddb_allocation *ddb;
3370         struct skl_ddb_entry *entry;
3371         enum pipe pipe;
3372         int plane;
3373
3374         if (INTEL_INFO(dev)->gen < 9)
3375                 return 0;
3376
3377         drm_modeset_lock_all(dev);
3378
3379         ddb = &dev_priv->wm.skl_hw.ddb;
3380
3381         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3382
3383         for_each_pipe(dev_priv, pipe) {
3384                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3385
3386                 for_each_plane(dev_priv, pipe, plane) {
3387                         entry = &ddb->plane[pipe][plane];
3388                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3389                                    entry->start, entry->end,
3390                                    skl_ddb_entry_size(entry));
3391                 }
3392
3393                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3394                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3395                            entry->end, skl_ddb_entry_size(entry));
3396         }
3397
3398         drm_modeset_unlock_all(dev);
3399
3400         return 0;
3401 }
3402
3403 static void drrs_status_per_crtc(struct seq_file *m,
3404                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3405 {
3406         struct drm_i915_private *dev_priv = to_i915(dev);
3407         struct i915_drrs *drrs = &dev_priv->drrs;
3408         int vrefresh = 0;
3409         struct drm_connector *connector;
3410
3411         drm_for_each_connector(connector, dev) {
3412                 if (connector->state->crtc != &intel_crtc->base)
3413                         continue;
3414
3415                 seq_printf(m, "%s:\n", connector->name);
3416         }
3417
3418         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3419                 seq_puts(m, "\tVBT: DRRS_type: Static");
3420         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3421                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3422         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3423                 seq_puts(m, "\tVBT: DRRS_type: None");
3424         else
3425                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3426
3427         seq_puts(m, "\n\n");
3428
3429         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3430                 struct intel_panel *panel;
3431
3432                 mutex_lock(&drrs->mutex);
3433                 /* DRRS Supported */
3434                 seq_puts(m, "\tDRRS Supported: Yes\n");
3435
3436                 /* disable_drrs() will make drrs->dp NULL */
3437                 if (!drrs->dp) {
3438                         seq_puts(m, "Idleness DRRS: Disabled");
3439                         mutex_unlock(&drrs->mutex);
3440                         return;
3441                 }
3442
3443                 panel = &drrs->dp->attached_connector->panel;
3444                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3445                                         drrs->busy_frontbuffer_bits);
3446
3447                 seq_puts(m, "\n\t\t");
3448                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3449                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3450                         vrefresh = panel->fixed_mode->vrefresh;
3451                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3452                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3453                         vrefresh = panel->downclock_mode->vrefresh;
3454                 } else {
3455                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3456                                                 drrs->refresh_rate_type);
3457                         mutex_unlock(&drrs->mutex);
3458                         return;
3459                 }
3460                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3461
3462                 seq_puts(m, "\n\t\t");
3463                 mutex_unlock(&drrs->mutex);
3464         } else {
3465                 /* DRRS not supported. Print the VBT parameter*/
3466                 seq_puts(m, "\tDRRS Supported : No");
3467         }
3468         seq_puts(m, "\n");
3469 }
3470
3471 static int i915_drrs_status(struct seq_file *m, void *unused)
3472 {
3473         struct drm_info_node *node = m->private;
3474         struct drm_device *dev = node->minor->dev;
3475         struct intel_crtc *intel_crtc;
3476         int active_crtc_cnt = 0;
3477
3478         drm_modeset_lock_all(dev);
3479         for_each_intel_crtc(dev, intel_crtc) {
3480                 if (intel_crtc->base.state->active) {
3481                         active_crtc_cnt++;
3482                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3483
3484                         drrs_status_per_crtc(m, dev, intel_crtc);
3485                 }
3486         }
3487         drm_modeset_unlock_all(dev);
3488
3489         if (!active_crtc_cnt)
3490                 seq_puts(m, "No active crtc found\n");
3491
3492         return 0;
3493 }
3494
3495 struct pipe_crc_info {
3496         const char *name;
3497         struct drm_device *dev;
3498         enum pipe pipe;
3499 };
3500
3501 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3502 {
3503         struct drm_info_node *node = (struct drm_info_node *) m->private;
3504         struct drm_device *dev = node->minor->dev;
3505         struct intel_encoder *intel_encoder;
3506         struct intel_digital_port *intel_dig_port;
3507         struct drm_connector *connector;
3508
3509         drm_modeset_lock_all(dev);
3510         drm_for_each_connector(connector, dev) {
3511                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3512                         continue;
3513
3514                 intel_encoder = intel_attached_encoder(connector);
3515                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3516                         continue;
3517
3518                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3519                 if (!intel_dig_port->dp.can_mst)
3520                         continue;
3521
3522                 seq_printf(m, "MST Source Port %c\n",
3523                            port_name(intel_dig_port->port));
3524                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3525         }
3526         drm_modeset_unlock_all(dev);
3527         return 0;
3528 }
3529
3530 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3531 {
3532         struct pipe_crc_info *info = inode->i_private;
3533         struct drm_i915_private *dev_priv = to_i915(info->dev);
3534         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3535
3536         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3537                 return -ENODEV;
3538
3539         spin_lock_irq(&pipe_crc->lock);
3540
3541         if (pipe_crc->opened) {
3542                 spin_unlock_irq(&pipe_crc->lock);
3543                 return -EBUSY; /* already open */
3544         }
3545
3546         pipe_crc->opened = true;
3547         filep->private_data = inode->i_private;
3548
3549         spin_unlock_irq(&pipe_crc->lock);
3550
3551         return 0;
3552 }
3553
3554 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3555 {
3556         struct pipe_crc_info *info = inode->i_private;
3557         struct drm_i915_private *dev_priv = to_i915(info->dev);
3558         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3559
3560         spin_lock_irq(&pipe_crc->lock);
3561         pipe_crc->opened = false;
3562         spin_unlock_irq(&pipe_crc->lock);
3563
3564         return 0;
3565 }
3566
3567 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3568 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3569 /* account for \'0' */
3570 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3571
3572 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3573 {
3574         assert_spin_locked(&pipe_crc->lock);
3575         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3576                         INTEL_PIPE_CRC_ENTRIES_NR);
3577 }
3578
3579 static ssize_t
3580 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3581                    loff_t *pos)
3582 {
3583         struct pipe_crc_info *info = filep->private_data;
3584         struct drm_device *dev = info->dev;
3585         struct drm_i915_private *dev_priv = to_i915(dev);
3586         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3587         char buf[PIPE_CRC_BUFFER_LEN];
3588         int n_entries;
3589         ssize_t bytes_read;
3590
3591         /*
3592          * Don't allow user space to provide buffers not big enough to hold
3593          * a line of data.
3594          */
3595         if (count < PIPE_CRC_LINE_LEN)
3596                 return -EINVAL;
3597
3598         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3599                 return 0;
3600
3601         /* nothing to read */
3602         spin_lock_irq(&pipe_crc->lock);
3603         while (pipe_crc_data_count(pipe_crc) == 0) {
3604                 int ret;
3605
3606                 if (filep->f_flags & O_NONBLOCK) {
3607                         spin_unlock_irq(&pipe_crc->lock);
3608                         return -EAGAIN;
3609                 }
3610
3611                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3612                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3613                 if (ret) {
3614                         spin_unlock_irq(&pipe_crc->lock);
3615                         return ret;
3616                 }
3617         }
3618
3619         /* We now have one or more entries to read */
3620         n_entries = count / PIPE_CRC_LINE_LEN;
3621
3622         bytes_read = 0;
3623         while (n_entries > 0) {
3624                 struct intel_pipe_crc_entry *entry =
3625                         &pipe_crc->entries[pipe_crc->tail];
3626
3627                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3628                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3629                         break;
3630
3631                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3632                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3633
3634                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3635                                        "%8u %8x %8x %8x %8x %8x\n",
3636                                        entry->frame, entry->crc[0],
3637                                        entry->crc[1], entry->crc[2],
3638                                        entry->crc[3], entry->crc[4]);
3639
3640                 spin_unlock_irq(&pipe_crc->lock);
3641
3642                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3643                         return -EFAULT;
3644
3645                 user_buf += PIPE_CRC_LINE_LEN;
3646                 n_entries--;
3647
3648                 spin_lock_irq(&pipe_crc->lock);
3649         }
3650
3651         spin_unlock_irq(&pipe_crc->lock);
3652
3653         return bytes_read;
3654 }
3655
3656 static const struct file_operations i915_pipe_crc_fops = {
3657         .owner = THIS_MODULE,
3658         .open = i915_pipe_crc_open,
3659         .read = i915_pipe_crc_read,
3660         .release = i915_pipe_crc_release,
3661 };
3662
3663 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3664         {
3665                 .name = "i915_pipe_A_crc",
3666                 .pipe = PIPE_A,
3667         },
3668         {
3669                 .name = "i915_pipe_B_crc",
3670                 .pipe = PIPE_B,
3671         },
3672         {
3673                 .name = "i915_pipe_C_crc",
3674                 .pipe = PIPE_C,
3675         },
3676 };
3677
3678 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3679                                 enum pipe pipe)
3680 {
3681         struct drm_device *dev = minor->dev;
3682         struct dentry *ent;
3683         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3684
3685         info->dev = dev;
3686         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3687                                   &i915_pipe_crc_fops);
3688         if (!ent)
3689                 return -ENOMEM;
3690
3691         return drm_add_fake_info_node(minor, ent, info);
3692 }
3693
3694 static const char * const pipe_crc_sources[] = {
3695         "none",
3696         "plane1",
3697         "plane2",
3698         "pf",
3699         "pipe",
3700         "TV",
3701         "DP-B",
3702         "DP-C",
3703         "DP-D",
3704         "auto",
3705 };
3706
3707 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3708 {
3709         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3710         return pipe_crc_sources[source];
3711 }
3712
3713 static int display_crc_ctl_show(struct seq_file *m, void *data)
3714 {
3715         struct drm_device *dev = m->private;
3716         struct drm_i915_private *dev_priv = to_i915(dev);
3717         int i;
3718
3719         for (i = 0; i < I915_MAX_PIPES; i++)
3720                 seq_printf(m, "%c %s\n", pipe_name(i),
3721                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3722
3723         return 0;
3724 }
3725
3726 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3727 {
3728         struct drm_device *dev = inode->i_private;
3729
3730         return single_open(file, display_crc_ctl_show, dev);
3731 }
3732
3733 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3734                                  uint32_t *val)
3735 {
3736         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3737                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3738
3739         switch (*source) {
3740         case INTEL_PIPE_CRC_SOURCE_PIPE:
3741                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3742                 break;
3743         case INTEL_PIPE_CRC_SOURCE_NONE:
3744                 *val = 0;
3745                 break;
3746         default:
3747                 return -EINVAL;
3748         }
3749
3750         return 0;
3751 }
3752
3753 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3754                                      enum intel_pipe_crc_source *source)
3755 {
3756         struct intel_encoder *encoder;
3757         struct intel_crtc *crtc;
3758         struct intel_digital_port *dig_port;
3759         int ret = 0;
3760
3761         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3762
3763         drm_modeset_lock_all(dev);
3764         for_each_intel_encoder(dev, encoder) {
3765                 if (!encoder->base.crtc)
3766                         continue;
3767
3768                 crtc = to_intel_crtc(encoder->base.crtc);
3769
3770                 if (crtc->pipe != pipe)
3771                         continue;
3772
3773                 switch (encoder->type) {
3774                 case INTEL_OUTPUT_TVOUT:
3775                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3776                         break;
3777                 case INTEL_OUTPUT_DP:
3778                 case INTEL_OUTPUT_EDP:
3779                         dig_port = enc_to_dig_port(&encoder->base);
3780                         switch (dig_port->port) {
3781                         case PORT_B:
3782                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3783                                 break;
3784                         case PORT_C:
3785                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3786                                 break;
3787                         case PORT_D:
3788                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3789                                 break;
3790                         default:
3791                                 WARN(1, "nonexisting DP port %c\n",
3792                                      port_name(dig_port->port));
3793                                 break;
3794                         }
3795                         break;
3796                 default:
3797                         break;
3798                 }
3799         }
3800         drm_modeset_unlock_all(dev);
3801
3802         return ret;
3803 }
3804
3805 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3806                                 enum pipe pipe,
3807                                 enum intel_pipe_crc_source *source,
3808                                 uint32_t *val)
3809 {
3810         struct drm_i915_private *dev_priv = to_i915(dev);
3811         bool need_stable_symbols = false;
3812
3813         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3814                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3815                 if (ret)
3816                         return ret;
3817         }
3818
3819         switch (*source) {
3820         case INTEL_PIPE_CRC_SOURCE_PIPE:
3821                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3822                 break;
3823         case INTEL_PIPE_CRC_SOURCE_DP_B:
3824                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3825                 need_stable_symbols = true;
3826                 break;
3827         case INTEL_PIPE_CRC_SOURCE_DP_C:
3828                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3829                 need_stable_symbols = true;
3830                 break;
3831         case INTEL_PIPE_CRC_SOURCE_DP_D:
3832                 if (!IS_CHERRYVIEW(dev))
3833                         return -EINVAL;
3834                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3835                 need_stable_symbols = true;
3836                 break;
3837         case INTEL_PIPE_CRC_SOURCE_NONE:
3838                 *val = 0;
3839                 break;
3840         default:
3841                 return -EINVAL;
3842         }
3843
3844         /*
3845          * When the pipe CRC tap point is after the transcoders we need
3846          * to tweak symbol-level features to produce a deterministic series of
3847          * symbols for a given frame. We need to reset those features only once
3848          * a frame (instead of every nth symbol):
3849          *   - DC-balance: used to ensure a better clock recovery from the data
3850          *     link (SDVO)
3851          *   - DisplayPort scrambling: used for EMI reduction
3852          */
3853         if (need_stable_symbols) {
3854                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3855
3856                 tmp |= DC_BALANCE_RESET_VLV;
3857                 switch (pipe) {
3858                 case PIPE_A:
3859                         tmp |= PIPE_A_SCRAMBLE_RESET;
3860                         break;
3861                 case PIPE_B:
3862                         tmp |= PIPE_B_SCRAMBLE_RESET;
3863                         break;
3864                 case PIPE_C:
3865                         tmp |= PIPE_C_SCRAMBLE_RESET;
3866                         break;
3867                 default:
3868                         return -EINVAL;
3869                 }
3870                 I915_WRITE(PORT_DFT2_G4X, tmp);
3871         }
3872
3873         return 0;
3874 }
3875
3876 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3877                                  enum pipe pipe,
3878                                  enum intel_pipe_crc_source *source,
3879                                  uint32_t *val)
3880 {
3881         struct drm_i915_private *dev_priv = to_i915(dev);
3882         bool need_stable_symbols = false;
3883
3884         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3885                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3886                 if (ret)
3887                         return ret;
3888         }
3889
3890         switch (*source) {
3891         case INTEL_PIPE_CRC_SOURCE_PIPE:
3892                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3893                 break;
3894         case INTEL_PIPE_CRC_SOURCE_TV:
3895                 if (!SUPPORTS_TV(dev))
3896                         return -EINVAL;
3897                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3898                 break;
3899         case INTEL_PIPE_CRC_SOURCE_DP_B:
3900                 if (!IS_G4X(dev))
3901                         return -EINVAL;
3902                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3903                 need_stable_symbols = true;
3904                 break;
3905         case INTEL_PIPE_CRC_SOURCE_DP_C:
3906                 if (!IS_G4X(dev))
3907                         return -EINVAL;
3908                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3909                 need_stable_symbols = true;
3910                 break;
3911         case INTEL_PIPE_CRC_SOURCE_DP_D:
3912                 if (!IS_G4X(dev))
3913                         return -EINVAL;
3914                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3915                 need_stable_symbols = true;
3916                 break;
3917         case INTEL_PIPE_CRC_SOURCE_NONE:
3918                 *val = 0;
3919                 break;
3920         default:
3921                 return -EINVAL;
3922         }
3923
3924         /*
3925          * When the pipe CRC tap point is after the transcoders we need
3926          * to tweak symbol-level features to produce a deterministic series of
3927          * symbols for a given frame. We need to reset those features only once
3928          * a frame (instead of every nth symbol):
3929          *   - DC-balance: used to ensure a better clock recovery from the data
3930          *     link (SDVO)
3931          *   - DisplayPort scrambling: used for EMI reduction
3932          */
3933         if (need_stable_symbols) {
3934                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3935
3936                 WARN_ON(!IS_G4X(dev));
3937
3938                 I915_WRITE(PORT_DFT_I9XX,
3939                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3940
3941                 if (pipe == PIPE_A)
3942                         tmp |= PIPE_A_SCRAMBLE_RESET;
3943                 else
3944                         tmp |= PIPE_B_SCRAMBLE_RESET;
3945
3946                 I915_WRITE(PORT_DFT2_G4X, tmp);
3947         }
3948
3949         return 0;
3950 }
3951
3952 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3953                                          enum pipe pipe)
3954 {
3955         struct drm_i915_private *dev_priv = to_i915(dev);
3956         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3957
3958         switch (pipe) {
3959         case PIPE_A:
3960                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3961                 break;
3962         case PIPE_B:
3963                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3964                 break;
3965         case PIPE_C:
3966                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3967                 break;
3968         default:
3969                 return;
3970         }
3971         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3972                 tmp &= ~DC_BALANCE_RESET_VLV;
3973         I915_WRITE(PORT_DFT2_G4X, tmp);
3974
3975 }
3976
3977 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3978                                          enum pipe pipe)
3979 {
3980         struct drm_i915_private *dev_priv = to_i915(dev);
3981         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3982
3983         if (pipe == PIPE_A)
3984                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3985         else
3986                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3987         I915_WRITE(PORT_DFT2_G4X, tmp);
3988
3989         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3990                 I915_WRITE(PORT_DFT_I9XX,
3991                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3992         }
3993 }
3994
3995 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3996                                 uint32_t *val)
3997 {
3998         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3999                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4000
4001         switch (*source) {
4002         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4003                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4004                 break;
4005         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4006                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4007                 break;
4008         case INTEL_PIPE_CRC_SOURCE_PIPE:
4009                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4010                 break;
4011         case INTEL_PIPE_CRC_SOURCE_NONE:
4012                 *val = 0;
4013                 break;
4014         default:
4015                 return -EINVAL;
4016         }
4017
4018         return 0;
4019 }
4020
4021 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4022 {
4023         struct drm_i915_private *dev_priv = to_i915(dev);
4024         struct intel_crtc *crtc =
4025                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4026         struct intel_crtc_state *pipe_config;
4027         struct drm_atomic_state *state;
4028         int ret = 0;
4029
4030         drm_modeset_lock_all(dev);
4031         state = drm_atomic_state_alloc(dev);
4032         if (!state) {
4033                 ret = -ENOMEM;
4034                 goto out;
4035         }
4036
4037         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4038         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4039         if (IS_ERR(pipe_config)) {
4040                 ret = PTR_ERR(pipe_config);
4041                 goto out;
4042         }
4043
4044         pipe_config->pch_pfit.force_thru = enable;
4045         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4046             pipe_config->pch_pfit.enabled != enable)
4047                 pipe_config->base.connectors_changed = true;
4048
4049         ret = drm_atomic_commit(state);
4050 out:
4051         drm_modeset_unlock_all(dev);
4052         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4053         if (ret)
4054                 drm_atomic_state_free(state);
4055 }
4056
4057 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4058                                 enum pipe pipe,
4059                                 enum intel_pipe_crc_source *source,
4060                                 uint32_t *val)
4061 {
4062         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4063                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4064
4065         switch (*source) {
4066         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4067                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4068                 break;
4069         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4070                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4071                 break;
4072         case INTEL_PIPE_CRC_SOURCE_PF:
4073                 if (IS_HASWELL(dev) && pipe == PIPE_A)
4074                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
4075
4076                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4077                 break;
4078         case INTEL_PIPE_CRC_SOURCE_NONE:
4079                 *val = 0;
4080                 break;
4081         default:
4082                 return -EINVAL;
4083         }
4084
4085         return 0;
4086 }
4087
4088 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4089                                enum intel_pipe_crc_source source)
4090 {
4091         struct drm_i915_private *dev_priv = to_i915(dev);
4092         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4093         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4094                                                                         pipe));
4095         enum intel_display_power_domain power_domain;
4096         u32 val = 0; /* shut up gcc */
4097         int ret;
4098
4099         if (pipe_crc->source == source)
4100                 return 0;
4101
4102         /* forbid changing the source without going back to 'none' */
4103         if (pipe_crc->source && source)
4104                 return -EINVAL;
4105
4106         power_domain = POWER_DOMAIN_PIPE(pipe);
4107         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4108                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4109                 return -EIO;
4110         }
4111
4112         if (IS_GEN2(dev))
4113                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4114         else if (INTEL_INFO(dev)->gen < 5)
4115                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4116         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4117                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4118         else if (IS_GEN5(dev) || IS_GEN6(dev))
4119                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4120         else
4121                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4122
4123         if (ret != 0)
4124                 goto out;
4125
4126         /* none -> real source transition */
4127         if (source) {
4128                 struct intel_pipe_crc_entry *entries;
4129
4130                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4131                                  pipe_name(pipe), pipe_crc_source_name(source));
4132
4133                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4134                                   sizeof(pipe_crc->entries[0]),
4135                                   GFP_KERNEL);
4136                 if (!entries) {
4137                         ret = -ENOMEM;
4138                         goto out;
4139                 }
4140
4141                 /*
4142                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4143                  * enabled and disabled dynamically based on package C states,
4144                  * user space can't make reliable use of the CRCs, so let's just
4145                  * completely disable it.
4146                  */
4147                 hsw_disable_ips(crtc);
4148
4149                 spin_lock_irq(&pipe_crc->lock);
4150                 kfree(pipe_crc->entries);
4151                 pipe_crc->entries = entries;
4152                 pipe_crc->head = 0;
4153                 pipe_crc->tail = 0;
4154                 spin_unlock_irq(&pipe_crc->lock);
4155         }
4156
4157         pipe_crc->source = source;
4158
4159         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4160         POSTING_READ(PIPE_CRC_CTL(pipe));
4161
4162         /* real source -> none transition */
4163         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4164                 struct intel_pipe_crc_entry *entries;
4165                 struct intel_crtc *crtc =
4166                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4167
4168                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4169                                  pipe_name(pipe));
4170
4171                 drm_modeset_lock(&crtc->base.mutex, NULL);
4172                 if (crtc->base.state->active)
4173                         intel_wait_for_vblank(dev, pipe);
4174                 drm_modeset_unlock(&crtc->base.mutex);
4175
4176                 spin_lock_irq(&pipe_crc->lock);
4177                 entries = pipe_crc->entries;
4178                 pipe_crc->entries = NULL;
4179                 pipe_crc->head = 0;
4180                 pipe_crc->tail = 0;
4181                 spin_unlock_irq(&pipe_crc->lock);
4182
4183                 kfree(entries);
4184
4185                 if (IS_G4X(dev))
4186                         g4x_undo_pipe_scramble_reset(dev, pipe);
4187                 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4188                         vlv_undo_pipe_scramble_reset(dev, pipe);
4189                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4190                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4191
4192                 hsw_enable_ips(crtc);
4193         }
4194
4195         ret = 0;
4196
4197 out:
4198         intel_display_power_put(dev_priv, power_domain);
4199
4200         return ret;
4201 }
4202
4203 /*
4204  * Parse pipe CRC command strings:
4205  *   command: wsp* object wsp+ name wsp+ source wsp*
4206  *   object: 'pipe'
4207  *   name: (A | B | C)
4208  *   source: (none | plane1 | plane2 | pf)
4209  *   wsp: (#0x20 | #0x9 | #0xA)+
4210  *
4211  * eg.:
4212  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4213  *  "pipe A none"    ->  Stop CRC
4214  */
4215 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4216 {
4217         int n_words = 0;
4218
4219         while (*buf) {
4220                 char *end;
4221
4222                 /* skip leading white space */
4223                 buf = skip_spaces(buf);
4224                 if (!*buf)
4225                         break;  /* end of buffer */
4226
4227                 /* find end of word */
4228                 for (end = buf; *end && !isspace(*end); end++)
4229                         ;
4230
4231                 if (n_words == max_words) {
4232                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4233                                          max_words);
4234                         return -EINVAL; /* ran out of words[] before bytes */
4235                 }
4236
4237                 if (*end)
4238                         *end++ = '\0';
4239                 words[n_words++] = buf;
4240                 buf = end;
4241         }
4242
4243         return n_words;
4244 }
4245
4246 enum intel_pipe_crc_object {
4247         PIPE_CRC_OBJECT_PIPE,
4248 };
4249
4250 static const char * const pipe_crc_objects[] = {
4251         "pipe",
4252 };
4253
4254 static int
4255 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4256 {
4257         int i;
4258
4259         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4260                 if (!strcmp(buf, pipe_crc_objects[i])) {
4261                         *o = i;
4262                         return 0;
4263                     }
4264
4265         return -EINVAL;
4266 }
4267
4268 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4269 {
4270         const char name = buf[0];
4271
4272         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4273                 return -EINVAL;
4274
4275         *pipe = name - 'A';
4276
4277         return 0;
4278 }
4279
4280 static int
4281 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4282 {
4283         int i;
4284
4285         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4286                 if (!strcmp(buf, pipe_crc_sources[i])) {
4287                         *s = i;
4288                         return 0;
4289                     }
4290
4291         return -EINVAL;
4292 }
4293
4294 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4295 {
4296 #define N_WORDS 3
4297         int n_words;
4298         char *words[N_WORDS];
4299         enum pipe pipe;
4300         enum intel_pipe_crc_object object;
4301         enum intel_pipe_crc_source source;
4302
4303         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4304         if (n_words != N_WORDS) {
4305                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4306                                  N_WORDS);
4307                 return -EINVAL;
4308         }
4309
4310         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4311                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4312                 return -EINVAL;
4313         }
4314
4315         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4316                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4317                 return -EINVAL;
4318         }
4319
4320         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4321                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4322                 return -EINVAL;
4323         }
4324
4325         return pipe_crc_set_source(dev, pipe, source);
4326 }
4327
4328 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4329                                      size_t len, loff_t *offp)
4330 {
4331         struct seq_file *m = file->private_data;
4332         struct drm_device *dev = m->private;
4333         char *tmpbuf;
4334         int ret;
4335
4336         if (len == 0)
4337                 return 0;
4338
4339         if (len > PAGE_SIZE - 1) {
4340                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4341                                  PAGE_SIZE);
4342                 return -E2BIG;
4343         }
4344
4345         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4346         if (!tmpbuf)
4347                 return -ENOMEM;
4348
4349         if (copy_from_user(tmpbuf, ubuf, len)) {
4350                 ret = -EFAULT;
4351                 goto out;
4352         }
4353         tmpbuf[len] = '\0';
4354
4355         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4356
4357 out:
4358         kfree(tmpbuf);
4359         if (ret < 0)
4360                 return ret;
4361
4362         *offp += len;
4363         return len;
4364 }
4365
4366 static const struct file_operations i915_display_crc_ctl_fops = {
4367         .owner = THIS_MODULE,
4368         .open = display_crc_ctl_open,
4369         .read = seq_read,
4370         .llseek = seq_lseek,
4371         .release = single_release,
4372         .write = display_crc_ctl_write
4373 };
4374
4375 static ssize_t i915_displayport_test_active_write(struct file *file,
4376                                             const char __user *ubuf,
4377                                             size_t len, loff_t *offp)
4378 {
4379         char *input_buffer;
4380         int status = 0;
4381         struct drm_device *dev;
4382         struct drm_connector *connector;
4383         struct list_head *connector_list;
4384         struct intel_dp *intel_dp;
4385         int val = 0;
4386
4387         dev = ((struct seq_file *)file->private_data)->private;
4388
4389         connector_list = &dev->mode_config.connector_list;
4390
4391         if (len == 0)
4392                 return 0;
4393
4394         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4395         if (!input_buffer)
4396                 return -ENOMEM;
4397
4398         if (copy_from_user(input_buffer, ubuf, len)) {
4399                 status = -EFAULT;
4400                 goto out;
4401         }
4402
4403         input_buffer[len] = '\0';
4404         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4405
4406         list_for_each_entry(connector, connector_list, head) {
4407
4408                 if (connector->connector_type !=
4409                     DRM_MODE_CONNECTOR_DisplayPort)
4410                         continue;
4411
4412                 if (connector->status == connector_status_connected &&
4413                     connector->encoder != NULL) {
4414                         intel_dp = enc_to_intel_dp(connector->encoder);
4415                         status = kstrtoint(input_buffer, 10, &val);
4416                         if (status < 0)
4417                                 goto out;
4418                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4419                         /* To prevent erroneous activation of the compliance
4420                          * testing code, only accept an actual value of 1 here
4421                          */
4422                         if (val == 1)
4423                                 intel_dp->compliance_test_active = 1;
4424                         else
4425                                 intel_dp->compliance_test_active = 0;
4426                 }
4427         }
4428 out:
4429         kfree(input_buffer);
4430         if (status < 0)
4431                 return status;
4432
4433         *offp += len;
4434         return len;
4435 }
4436
4437 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4438 {
4439         struct drm_device *dev = m->private;
4440         struct drm_connector *connector;
4441         struct list_head *connector_list = &dev->mode_config.connector_list;
4442         struct intel_dp *intel_dp;
4443
4444         list_for_each_entry(connector, connector_list, head) {
4445
4446                 if (connector->connector_type !=
4447                     DRM_MODE_CONNECTOR_DisplayPort)
4448                         continue;
4449
4450                 if (connector->status == connector_status_connected &&
4451                     connector->encoder != NULL) {
4452                         intel_dp = enc_to_intel_dp(connector->encoder);
4453                         if (intel_dp->compliance_test_active)
4454                                 seq_puts(m, "1");
4455                         else
4456                                 seq_puts(m, "0");
4457                 } else
4458                         seq_puts(m, "0");
4459         }
4460
4461         return 0;
4462 }
4463
4464 static int i915_displayport_test_active_open(struct inode *inode,
4465                                        struct file *file)
4466 {
4467         struct drm_device *dev = inode->i_private;
4468
4469         return single_open(file, i915_displayport_test_active_show, dev);
4470 }
4471
4472 static const struct file_operations i915_displayport_test_active_fops = {
4473         .owner = THIS_MODULE,
4474         .open = i915_displayport_test_active_open,
4475         .read = seq_read,
4476         .llseek = seq_lseek,
4477         .release = single_release,
4478         .write = i915_displayport_test_active_write
4479 };
4480
4481 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4482 {
4483         struct drm_device *dev = m->private;
4484         struct drm_connector *connector;
4485         struct list_head *connector_list = &dev->mode_config.connector_list;
4486         struct intel_dp *intel_dp;
4487
4488         list_for_each_entry(connector, connector_list, head) {
4489
4490                 if (connector->connector_type !=
4491                     DRM_MODE_CONNECTOR_DisplayPort)
4492                         continue;
4493
4494                 if (connector->status == connector_status_connected &&
4495                     connector->encoder != NULL) {
4496                         intel_dp = enc_to_intel_dp(connector->encoder);
4497                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4498                 } else
4499                         seq_puts(m, "0");
4500         }
4501
4502         return 0;
4503 }
4504 static int i915_displayport_test_data_open(struct inode *inode,
4505                                        struct file *file)
4506 {
4507         struct drm_device *dev = inode->i_private;
4508
4509         return single_open(file, i915_displayport_test_data_show, dev);
4510 }
4511
4512 static const struct file_operations i915_displayport_test_data_fops = {
4513         .owner = THIS_MODULE,
4514         .open = i915_displayport_test_data_open,
4515         .read = seq_read,
4516         .llseek = seq_lseek,
4517         .release = single_release
4518 };
4519
4520 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4521 {
4522         struct drm_device *dev = m->private;
4523         struct drm_connector *connector;
4524         struct list_head *connector_list = &dev->mode_config.connector_list;
4525         struct intel_dp *intel_dp;
4526
4527         list_for_each_entry(connector, connector_list, head) {
4528
4529                 if (connector->connector_type !=
4530                     DRM_MODE_CONNECTOR_DisplayPort)
4531                         continue;
4532
4533                 if (connector->status == connector_status_connected &&
4534                     connector->encoder != NULL) {
4535                         intel_dp = enc_to_intel_dp(connector->encoder);
4536                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4537                 } else
4538                         seq_puts(m, "0");
4539         }
4540
4541         return 0;
4542 }
4543
4544 static int i915_displayport_test_type_open(struct inode *inode,
4545                                        struct file *file)
4546 {
4547         struct drm_device *dev = inode->i_private;
4548
4549         return single_open(file, i915_displayport_test_type_show, dev);
4550 }
4551
4552 static const struct file_operations i915_displayport_test_type_fops = {
4553         .owner = THIS_MODULE,
4554         .open = i915_displayport_test_type_open,
4555         .read = seq_read,
4556         .llseek = seq_lseek,
4557         .release = single_release
4558 };
4559
4560 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4561 {
4562         struct drm_device *dev = m->private;
4563         int level;
4564         int num_levels;
4565
4566         if (IS_CHERRYVIEW(dev))
4567                 num_levels = 3;
4568         else if (IS_VALLEYVIEW(dev))
4569                 num_levels = 1;
4570         else
4571                 num_levels = ilk_wm_max_level(dev) + 1;
4572
4573         drm_modeset_lock_all(dev);
4574
4575         for (level = 0; level < num_levels; level++) {
4576                 unsigned int latency = wm[level];
4577
4578                 /*
4579                  * - WM1+ latency values in 0.5us units
4580                  * - latencies are in us on gen9/vlv/chv
4581                  */
4582                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4583                     IS_CHERRYVIEW(dev))
4584                         latency *= 10;
4585                 else if (level > 0)
4586                         latency *= 5;
4587
4588                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4589                            level, wm[level], latency / 10, latency % 10);
4590         }
4591
4592         drm_modeset_unlock_all(dev);
4593 }
4594
4595 static int pri_wm_latency_show(struct seq_file *m, void *data)
4596 {
4597         struct drm_device *dev = m->private;
4598         struct drm_i915_private *dev_priv = to_i915(dev);
4599         const uint16_t *latencies;
4600
4601         if (INTEL_INFO(dev)->gen >= 9)
4602                 latencies = dev_priv->wm.skl_latency;
4603         else
4604                 latencies = to_i915(dev)->wm.pri_latency;
4605
4606         wm_latency_show(m, latencies);
4607
4608         return 0;
4609 }
4610
4611 static int spr_wm_latency_show(struct seq_file *m, void *data)
4612 {
4613         struct drm_device *dev = m->private;
4614         struct drm_i915_private *dev_priv = to_i915(dev);
4615         const uint16_t *latencies;
4616
4617         if (INTEL_INFO(dev)->gen >= 9)
4618                 latencies = dev_priv->wm.skl_latency;
4619         else
4620                 latencies = to_i915(dev)->wm.spr_latency;
4621
4622         wm_latency_show(m, latencies);
4623
4624         return 0;
4625 }
4626
4627 static int cur_wm_latency_show(struct seq_file *m, void *data)
4628 {
4629         struct drm_device *dev = m->private;
4630         struct drm_i915_private *dev_priv = to_i915(dev);
4631         const uint16_t *latencies;
4632
4633         if (INTEL_INFO(dev)->gen >= 9)
4634                 latencies = dev_priv->wm.skl_latency;
4635         else
4636                 latencies = to_i915(dev)->wm.cur_latency;
4637
4638         wm_latency_show(m, latencies);
4639
4640         return 0;
4641 }
4642
4643 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4644 {
4645         struct drm_device *dev = inode->i_private;
4646
4647         if (INTEL_INFO(dev)->gen < 5)
4648                 return -ENODEV;
4649
4650         return single_open(file, pri_wm_latency_show, dev);
4651 }
4652
4653 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4654 {
4655         struct drm_device *dev = inode->i_private;
4656
4657         if (HAS_GMCH_DISPLAY(dev))
4658                 return -ENODEV;
4659
4660         return single_open(file, spr_wm_latency_show, dev);
4661 }
4662
4663 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4664 {
4665         struct drm_device *dev = inode->i_private;
4666
4667         if (HAS_GMCH_DISPLAY(dev))
4668                 return -ENODEV;
4669
4670         return single_open(file, cur_wm_latency_show, dev);
4671 }
4672
4673 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4674                                 size_t len, loff_t *offp, uint16_t wm[8])
4675 {
4676         struct seq_file *m = file->private_data;
4677         struct drm_device *dev = m->private;
4678         uint16_t new[8] = { 0 };
4679         int num_levels;
4680         int level;
4681         int ret;
4682         char tmp[32];
4683
4684         if (IS_CHERRYVIEW(dev))
4685                 num_levels = 3;
4686         else if (IS_VALLEYVIEW(dev))
4687                 num_levels = 1;
4688         else
4689                 num_levels = ilk_wm_max_level(dev) + 1;
4690
4691         if (len >= sizeof(tmp))
4692                 return -EINVAL;
4693
4694         if (copy_from_user(tmp, ubuf, len))
4695                 return -EFAULT;
4696
4697         tmp[len] = '\0';
4698
4699         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4700                      &new[0], &new[1], &new[2], &new[3],
4701                      &new[4], &new[5], &new[6], &new[7]);
4702         if (ret != num_levels)
4703                 return -EINVAL;
4704
4705         drm_modeset_lock_all(dev);
4706
4707         for (level = 0; level < num_levels; level++)
4708                 wm[level] = new[level];
4709
4710         drm_modeset_unlock_all(dev);
4711
4712         return len;
4713 }
4714
4715
4716 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4717                                     size_t len, loff_t *offp)
4718 {
4719         struct seq_file *m = file->private_data;
4720         struct drm_device *dev = m->private;
4721         struct drm_i915_private *dev_priv = to_i915(dev);
4722         uint16_t *latencies;
4723
4724         if (INTEL_INFO(dev)->gen >= 9)
4725                 latencies = dev_priv->wm.skl_latency;
4726         else
4727                 latencies = to_i915(dev)->wm.pri_latency;
4728
4729         return wm_latency_write(file, ubuf, len, offp, latencies);
4730 }
4731
4732 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4733                                     size_t len, loff_t *offp)
4734 {
4735         struct seq_file *m = file->private_data;
4736         struct drm_device *dev = m->private;
4737         struct drm_i915_private *dev_priv = to_i915(dev);
4738         uint16_t *latencies;
4739
4740         if (INTEL_INFO(dev)->gen >= 9)
4741                 latencies = dev_priv->wm.skl_latency;
4742         else
4743                 latencies = to_i915(dev)->wm.spr_latency;
4744
4745         return wm_latency_write(file, ubuf, len, offp, latencies);
4746 }
4747
4748 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4749                                     size_t len, loff_t *offp)
4750 {
4751         struct seq_file *m = file->private_data;
4752         struct drm_device *dev = m->private;
4753         struct drm_i915_private *dev_priv = to_i915(dev);
4754         uint16_t *latencies;
4755
4756         if (INTEL_INFO(dev)->gen >= 9)
4757                 latencies = dev_priv->wm.skl_latency;
4758         else
4759                 latencies = to_i915(dev)->wm.cur_latency;
4760
4761         return wm_latency_write(file, ubuf, len, offp, latencies);
4762 }
4763
4764 static const struct file_operations i915_pri_wm_latency_fops = {
4765         .owner = THIS_MODULE,
4766         .open = pri_wm_latency_open,
4767         .read = seq_read,
4768         .llseek = seq_lseek,
4769         .release = single_release,
4770         .write = pri_wm_latency_write
4771 };
4772
4773 static const struct file_operations i915_spr_wm_latency_fops = {
4774         .owner = THIS_MODULE,
4775         .open = spr_wm_latency_open,
4776         .read = seq_read,
4777         .llseek = seq_lseek,
4778         .release = single_release,
4779         .write = spr_wm_latency_write
4780 };
4781
4782 static const struct file_operations i915_cur_wm_latency_fops = {
4783         .owner = THIS_MODULE,
4784         .open = cur_wm_latency_open,
4785         .read = seq_read,
4786         .llseek = seq_lseek,
4787         .release = single_release,
4788         .write = cur_wm_latency_write
4789 };
4790
4791 static int
4792 i915_wedged_get(void *data, u64 *val)
4793 {
4794         struct drm_device *dev = data;
4795         struct drm_i915_private *dev_priv = to_i915(dev);
4796
4797         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4798
4799         return 0;
4800 }
4801
4802 static int
4803 i915_wedged_set(void *data, u64 val)
4804 {
4805         struct drm_device *dev = data;
4806         struct drm_i915_private *dev_priv = to_i915(dev);
4807
4808         /*
4809          * There is no safeguard against this debugfs entry colliding
4810          * with the hangcheck calling same i915_handle_error() in
4811          * parallel, causing an explosion. For now we assume that the
4812          * test harness is responsible enough not to inject gpu hangs
4813          * while it is writing to 'i915_wedged'
4814          */
4815
4816         if (i915_reset_in_progress(&dev_priv->gpu_error))
4817                 return -EAGAIN;
4818
4819         intel_runtime_pm_get(dev_priv);
4820
4821         i915_handle_error(dev_priv, val,
4822                           "Manually setting wedged to %llu", val);
4823
4824         intel_runtime_pm_put(dev_priv);
4825
4826         return 0;
4827 }
4828
4829 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4830                         i915_wedged_get, i915_wedged_set,
4831                         "%llu\n");
4832
4833 static int
4834 i915_ring_missed_irq_get(void *data, u64 *val)
4835 {
4836         struct drm_device *dev = data;
4837         struct drm_i915_private *dev_priv = to_i915(dev);
4838
4839         *val = dev_priv->gpu_error.missed_irq_rings;
4840         return 0;
4841 }
4842
4843 static int
4844 i915_ring_missed_irq_set(void *data, u64 val)
4845 {
4846         struct drm_device *dev = data;
4847         struct drm_i915_private *dev_priv = to_i915(dev);
4848         int ret;
4849
4850         /* Lock against concurrent debugfs callers */
4851         ret = mutex_lock_interruptible(&dev->struct_mutex);
4852         if (ret)
4853                 return ret;
4854         dev_priv->gpu_error.missed_irq_rings = val;
4855         mutex_unlock(&dev->struct_mutex);
4856
4857         return 0;
4858 }
4859
4860 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4861                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4862                         "0x%08llx\n");
4863
4864 static int
4865 i915_ring_test_irq_get(void *data, u64 *val)
4866 {
4867         struct drm_device *dev = data;
4868         struct drm_i915_private *dev_priv = to_i915(dev);
4869
4870         *val = dev_priv->gpu_error.test_irq_rings;
4871
4872         return 0;
4873 }
4874
4875 static int
4876 i915_ring_test_irq_set(void *data, u64 val)
4877 {
4878         struct drm_device *dev = data;
4879         struct drm_i915_private *dev_priv = to_i915(dev);
4880
4881         val &= INTEL_INFO(dev_priv)->ring_mask;
4882         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4883         dev_priv->gpu_error.test_irq_rings = val;
4884
4885         return 0;
4886 }
4887
4888 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4889                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4890                         "0x%08llx\n");
4891
4892 #define DROP_UNBOUND 0x1
4893 #define DROP_BOUND 0x2
4894 #define DROP_RETIRE 0x4
4895 #define DROP_ACTIVE 0x8
4896 #define DROP_ALL (DROP_UNBOUND | \
4897                   DROP_BOUND | \
4898                   DROP_RETIRE | \
4899                   DROP_ACTIVE)
4900 static int
4901 i915_drop_caches_get(void *data, u64 *val)
4902 {
4903         *val = DROP_ALL;
4904
4905         return 0;
4906 }
4907
4908 static int
4909 i915_drop_caches_set(void *data, u64 val)
4910 {
4911         struct drm_device *dev = data;
4912         struct drm_i915_private *dev_priv = to_i915(dev);
4913         int ret;
4914
4915         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4916
4917         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4918          * on ioctls on -EAGAIN. */
4919         ret = mutex_lock_interruptible(&dev->struct_mutex);
4920         if (ret)
4921                 return ret;
4922
4923         if (val & DROP_ACTIVE) {
4924                 ret = i915_gem_wait_for_idle(dev_priv, true);
4925                 if (ret)
4926                         goto unlock;
4927         }
4928
4929         if (val & (DROP_RETIRE | DROP_ACTIVE))
4930                 i915_gem_retire_requests(dev_priv);
4931
4932         if (val & DROP_BOUND)
4933                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4934
4935         if (val & DROP_UNBOUND)
4936                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4937
4938 unlock:
4939         mutex_unlock(&dev->struct_mutex);
4940
4941         return ret;
4942 }
4943
4944 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4945                         i915_drop_caches_get, i915_drop_caches_set,
4946                         "0x%08llx\n");
4947
4948 static int
4949 i915_max_freq_get(void *data, u64 *val)
4950 {
4951         struct drm_device *dev = data;
4952         struct drm_i915_private *dev_priv = to_i915(dev);
4953
4954         if (INTEL_INFO(dev)->gen < 6)
4955                 return -ENODEV;
4956
4957         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4958         return 0;
4959 }
4960
4961 static int
4962 i915_max_freq_set(void *data, u64 val)
4963 {
4964         struct drm_device *dev = data;
4965         struct drm_i915_private *dev_priv = to_i915(dev);
4966         u32 hw_max, hw_min;
4967         int ret;
4968
4969         if (INTEL_INFO(dev)->gen < 6)
4970                 return -ENODEV;
4971
4972         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4973
4974         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4975         if (ret)
4976                 return ret;
4977
4978         /*
4979          * Turbo will still be enabled, but won't go above the set value.
4980          */
4981         val = intel_freq_opcode(dev_priv, val);
4982
4983         hw_max = dev_priv->rps.max_freq;
4984         hw_min = dev_priv->rps.min_freq;
4985
4986         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4987                 mutex_unlock(&dev_priv->rps.hw_lock);
4988                 return -EINVAL;
4989         }
4990
4991         dev_priv->rps.max_freq_softlimit = val;
4992
4993         intel_set_rps(dev_priv, val);
4994
4995         mutex_unlock(&dev_priv->rps.hw_lock);
4996
4997         return 0;
4998 }
4999
5000 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5001                         i915_max_freq_get, i915_max_freq_set,
5002                         "%llu\n");
5003
5004 static int
5005 i915_min_freq_get(void *data, u64 *val)
5006 {
5007         struct drm_device *dev = data;
5008         struct drm_i915_private *dev_priv = to_i915(dev);
5009
5010         if (INTEL_GEN(dev_priv) < 6)
5011                 return -ENODEV;
5012
5013         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5014         return 0;
5015 }
5016
5017 static int
5018 i915_min_freq_set(void *data, u64 val)
5019 {
5020         struct drm_device *dev = data;
5021         struct drm_i915_private *dev_priv = to_i915(dev);
5022         u32 hw_max, hw_min;
5023         int ret;
5024
5025         if (INTEL_GEN(dev_priv) < 6)
5026                 return -ENODEV;
5027
5028         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5029
5030         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5031         if (ret)
5032                 return ret;
5033
5034         /*
5035          * Turbo will still be enabled, but won't go below the set value.
5036          */
5037         val = intel_freq_opcode(dev_priv, val);
5038
5039         hw_max = dev_priv->rps.max_freq;
5040         hw_min = dev_priv->rps.min_freq;
5041
5042         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5043                 mutex_unlock(&dev_priv->rps.hw_lock);
5044                 return -EINVAL;
5045         }
5046
5047         dev_priv->rps.min_freq_softlimit = val;
5048
5049         intel_set_rps(dev_priv, val);
5050
5051         mutex_unlock(&dev_priv->rps.hw_lock);
5052
5053         return 0;
5054 }
5055
5056 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5057                         i915_min_freq_get, i915_min_freq_set,
5058                         "%llu\n");
5059
5060 static int
5061 i915_cache_sharing_get(void *data, u64 *val)
5062 {
5063         struct drm_device *dev = data;
5064         struct drm_i915_private *dev_priv = to_i915(dev);
5065         u32 snpcr;
5066         int ret;
5067
5068         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5069                 return -ENODEV;
5070
5071         ret = mutex_lock_interruptible(&dev->struct_mutex);
5072         if (ret)
5073                 return ret;
5074         intel_runtime_pm_get(dev_priv);
5075
5076         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5077
5078         intel_runtime_pm_put(dev_priv);
5079         mutex_unlock(&dev_priv->drm.struct_mutex);
5080
5081         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5082
5083         return 0;
5084 }
5085
5086 static int
5087 i915_cache_sharing_set(void *data, u64 val)
5088 {
5089         struct drm_device *dev = data;
5090         struct drm_i915_private *dev_priv = to_i915(dev);
5091         u32 snpcr;
5092
5093         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5094                 return -ENODEV;
5095
5096         if (val > 3)
5097                 return -EINVAL;
5098
5099         intel_runtime_pm_get(dev_priv);
5100         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5101
5102         /* Update the cache sharing policy here as well */
5103         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5104         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5105         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5106         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5107
5108         intel_runtime_pm_put(dev_priv);
5109         return 0;
5110 }
5111
5112 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5113                         i915_cache_sharing_get, i915_cache_sharing_set,
5114                         "%llu\n");
5115
5116 struct sseu_dev_status {
5117         unsigned int slice_total;
5118         unsigned int subslice_total;
5119         unsigned int subslice_per_slice;
5120         unsigned int eu_total;
5121         unsigned int eu_per_subslice;
5122 };
5123
5124 static void cherryview_sseu_device_status(struct drm_device *dev,
5125                                           struct sseu_dev_status *stat)
5126 {
5127         struct drm_i915_private *dev_priv = to_i915(dev);
5128         int ss_max = 2;
5129         int ss;
5130         u32 sig1[ss_max], sig2[ss_max];
5131
5132         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5133         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5134         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5135         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5136
5137         for (ss = 0; ss < ss_max; ss++) {
5138                 unsigned int eu_cnt;
5139
5140                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5141                         /* skip disabled subslice */
5142                         continue;
5143
5144                 stat->slice_total = 1;
5145                 stat->subslice_per_slice++;
5146                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5147                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5148                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5149                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5150                 stat->eu_total += eu_cnt;
5151                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5152         }
5153         stat->subslice_total = stat->subslice_per_slice;
5154 }
5155
5156 static void gen9_sseu_device_status(struct drm_device *dev,
5157                                     struct sseu_dev_status *stat)
5158 {
5159         struct drm_i915_private *dev_priv = to_i915(dev);
5160         int s_max = 3, ss_max = 4;
5161         int s, ss;
5162         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5163
5164         /* BXT has a single slice and at most 3 subslices. */
5165         if (IS_BROXTON(dev)) {
5166                 s_max = 1;
5167                 ss_max = 3;
5168         }
5169
5170         for (s = 0; s < s_max; s++) {
5171                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5172                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5173                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5174         }
5175
5176         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5177                      GEN9_PGCTL_SSA_EU19_ACK |
5178                      GEN9_PGCTL_SSA_EU210_ACK |
5179                      GEN9_PGCTL_SSA_EU311_ACK;
5180         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5181                      GEN9_PGCTL_SSB_EU19_ACK |
5182                      GEN9_PGCTL_SSB_EU210_ACK |
5183                      GEN9_PGCTL_SSB_EU311_ACK;
5184
5185         for (s = 0; s < s_max; s++) {
5186                 unsigned int ss_cnt = 0;
5187
5188                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5189                         /* skip disabled slice */
5190                         continue;
5191
5192                 stat->slice_total++;
5193
5194                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5195                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5196
5197                 for (ss = 0; ss < ss_max; ss++) {
5198                         unsigned int eu_cnt;
5199
5200                         if (IS_BROXTON(dev) &&
5201                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5202                                 /* skip disabled subslice */
5203                                 continue;
5204
5205                         if (IS_BROXTON(dev))
5206                                 ss_cnt++;
5207
5208                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5209                                                eu_mask[ss%2]);
5210                         stat->eu_total += eu_cnt;
5211                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5212                                                     eu_cnt);
5213                 }
5214
5215                 stat->subslice_total += ss_cnt;
5216                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5217                                                ss_cnt);
5218         }
5219 }
5220
5221 static void broadwell_sseu_device_status(struct drm_device *dev,
5222                                          struct sseu_dev_status *stat)
5223 {
5224         struct drm_i915_private *dev_priv = to_i915(dev);
5225         int s;
5226         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5227
5228         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5229
5230         if (stat->slice_total) {
5231                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5232                 stat->subslice_total = stat->slice_total *
5233                                        stat->subslice_per_slice;
5234                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5235                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5236
5237                 /* subtract fused off EU(s) from enabled slice(s) */
5238                 for (s = 0; s < stat->slice_total; s++) {
5239                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5240
5241                         stat->eu_total -= hweight8(subslice_7eu);
5242                 }
5243         }
5244 }
5245
5246 static int i915_sseu_status(struct seq_file *m, void *unused)
5247 {
5248         struct drm_info_node *node = (struct drm_info_node *) m->private;
5249         struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5250         struct drm_device *dev = &dev_priv->drm;
5251         struct sseu_dev_status stat;
5252
5253         if (INTEL_INFO(dev)->gen < 8)
5254                 return -ENODEV;
5255
5256         seq_puts(m, "SSEU Device Info\n");
5257         seq_printf(m, "  Available Slice Total: %u\n",
5258                    INTEL_INFO(dev)->slice_total);
5259         seq_printf(m, "  Available Subslice Total: %u\n",
5260                    INTEL_INFO(dev)->subslice_total);
5261         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5262                    INTEL_INFO(dev)->subslice_per_slice);
5263         seq_printf(m, "  Available EU Total: %u\n",
5264                    INTEL_INFO(dev)->eu_total);
5265         seq_printf(m, "  Available EU Per Subslice: %u\n",
5266                    INTEL_INFO(dev)->eu_per_subslice);
5267         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5268         if (HAS_POOLED_EU(dev))
5269                 seq_printf(m, "  Min EU in pool: %u\n",
5270                            INTEL_INFO(dev)->min_eu_in_pool);
5271         seq_printf(m, "  Has Slice Power Gating: %s\n",
5272                    yesno(INTEL_INFO(dev)->has_slice_pg));
5273         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5274                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5275         seq_printf(m, "  Has EU Power Gating: %s\n",
5276                    yesno(INTEL_INFO(dev)->has_eu_pg));
5277
5278         seq_puts(m, "SSEU Device Status\n");
5279         memset(&stat, 0, sizeof(stat));
5280
5281         intel_runtime_pm_get(dev_priv);
5282
5283         if (IS_CHERRYVIEW(dev)) {
5284                 cherryview_sseu_device_status(dev, &stat);
5285         } else if (IS_BROADWELL(dev)) {
5286                 broadwell_sseu_device_status(dev, &stat);
5287         } else if (INTEL_INFO(dev)->gen >= 9) {
5288                 gen9_sseu_device_status(dev, &stat);
5289         }
5290
5291         intel_runtime_pm_put(dev_priv);
5292
5293         seq_printf(m, "  Enabled Slice Total: %u\n",
5294                    stat.slice_total);
5295         seq_printf(m, "  Enabled Subslice Total: %u\n",
5296                    stat.subslice_total);
5297         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5298                    stat.subslice_per_slice);
5299         seq_printf(m, "  Enabled EU Total: %u\n",
5300                    stat.eu_total);
5301         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5302                    stat.eu_per_subslice);
5303
5304         return 0;
5305 }
5306
5307 static int i915_forcewake_open(struct inode *inode, struct file *file)
5308 {
5309         struct drm_device *dev = inode->i_private;
5310         struct drm_i915_private *dev_priv = to_i915(dev);
5311
5312         if (INTEL_INFO(dev)->gen < 6)
5313                 return 0;
5314
5315         intel_runtime_pm_get(dev_priv);
5316         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5317
5318         return 0;
5319 }
5320
5321 static int i915_forcewake_release(struct inode *inode, struct file *file)
5322 {
5323         struct drm_device *dev = inode->i_private;
5324         struct drm_i915_private *dev_priv = to_i915(dev);
5325
5326         if (INTEL_INFO(dev)->gen < 6)
5327                 return 0;
5328
5329         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5330         intel_runtime_pm_put(dev_priv);
5331
5332         return 0;
5333 }
5334
5335 static const struct file_operations i915_forcewake_fops = {
5336         .owner = THIS_MODULE,
5337         .open = i915_forcewake_open,
5338         .release = i915_forcewake_release,
5339 };
5340
5341 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5342 {
5343         struct drm_device *dev = minor->dev;
5344         struct dentry *ent;
5345
5346         ent = debugfs_create_file("i915_forcewake_user",
5347                                   S_IRUSR,
5348                                   root, dev,
5349                                   &i915_forcewake_fops);
5350         if (!ent)
5351                 return -ENOMEM;
5352
5353         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5354 }
5355
5356 static int i915_debugfs_create(struct dentry *root,
5357                                struct drm_minor *minor,
5358                                const char *name,
5359                                const struct file_operations *fops)
5360 {
5361         struct drm_device *dev = minor->dev;
5362         struct dentry *ent;
5363
5364         ent = debugfs_create_file(name,
5365                                   S_IRUGO | S_IWUSR,
5366                                   root, dev,
5367                                   fops);
5368         if (!ent)
5369                 return -ENOMEM;
5370
5371         return drm_add_fake_info_node(minor, ent, fops);
5372 }
5373
5374 static const struct drm_info_list i915_debugfs_list[] = {
5375         {"i915_capabilities", i915_capabilities, 0},
5376         {"i915_gem_objects", i915_gem_object_info, 0},
5377         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5378         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5379         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5380         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5381         {"i915_gem_stolen", i915_gem_stolen_list_info },
5382         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5383         {"i915_gem_request", i915_gem_request_info, 0},
5384         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5385         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5386         {"i915_gem_interrupt", i915_interrupt_info, 0},
5387         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5388         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5389         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5390         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5391         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5392         {"i915_guc_info", i915_guc_info, 0},
5393         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5394         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5395         {"i915_frequency_info", i915_frequency_info, 0},
5396         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5397         {"i915_drpc_info", i915_drpc_info, 0},
5398         {"i915_emon_status", i915_emon_status, 0},
5399         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5400         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5401         {"i915_fbc_status", i915_fbc_status, 0},
5402         {"i915_ips_status", i915_ips_status, 0},
5403         {"i915_sr_status", i915_sr_status, 0},
5404         {"i915_opregion", i915_opregion, 0},
5405         {"i915_vbt", i915_vbt, 0},
5406         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5407         {"i915_context_status", i915_context_status, 0},
5408         {"i915_dump_lrc", i915_dump_lrc, 0},
5409         {"i915_execlists", i915_execlists, 0},
5410         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5411         {"i915_swizzle_info", i915_swizzle_info, 0},
5412         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5413         {"i915_llc", i915_llc, 0},
5414         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5415         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5416         {"i915_energy_uJ", i915_energy_uJ, 0},
5417         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5418         {"i915_power_domain_info", i915_power_domain_info, 0},
5419         {"i915_dmc_info", i915_dmc_info, 0},
5420         {"i915_display_info", i915_display_info, 0},
5421         {"i915_semaphore_status", i915_semaphore_status, 0},
5422         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5423         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5424         {"i915_wa_registers", i915_wa_registers, 0},
5425         {"i915_ddb_info", i915_ddb_info, 0},
5426         {"i915_sseu_status", i915_sseu_status, 0},
5427         {"i915_drrs_status", i915_drrs_status, 0},
5428         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5429 };
5430 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5431
5432 static const struct i915_debugfs_files {
5433         const char *name;
5434         const struct file_operations *fops;
5435 } i915_debugfs_files[] = {
5436         {"i915_wedged", &i915_wedged_fops},
5437         {"i915_max_freq", &i915_max_freq_fops},
5438         {"i915_min_freq", &i915_min_freq_fops},
5439         {"i915_cache_sharing", &i915_cache_sharing_fops},
5440         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5441         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5442         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5443         {"i915_error_state", &i915_error_state_fops},
5444         {"i915_next_seqno", &i915_next_seqno_fops},
5445         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5446         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5447         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5448         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5449         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5450         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5451         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5452         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5453 };
5454
5455 void intel_display_crc_init(struct drm_device *dev)
5456 {
5457         struct drm_i915_private *dev_priv = to_i915(dev);
5458         enum pipe pipe;
5459
5460         for_each_pipe(dev_priv, pipe) {
5461                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5462
5463                 pipe_crc->opened = false;
5464                 spin_lock_init(&pipe_crc->lock);
5465                 init_waitqueue_head(&pipe_crc->wq);
5466         }
5467 }
5468
5469 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5470 {
5471         struct drm_minor *minor = dev_priv->drm.primary;
5472         int ret, i;
5473
5474         ret = i915_forcewake_create(minor->debugfs_root, minor);
5475         if (ret)
5476                 return ret;
5477
5478         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5479                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5480                 if (ret)
5481                         return ret;
5482         }
5483
5484         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5485                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5486                                           i915_debugfs_files[i].name,
5487                                           i915_debugfs_files[i].fops);
5488                 if (ret)
5489                         return ret;
5490         }
5491
5492         return drm_debugfs_create_files(i915_debugfs_list,
5493                                         I915_DEBUGFS_ENTRIES,
5494                                         minor->debugfs_root, minor);
5495 }
5496
5497 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5498 {
5499         struct drm_minor *minor = dev_priv->drm.primary;
5500         int i;
5501
5502         drm_debugfs_remove_files(i915_debugfs_list,
5503                                  I915_DEBUGFS_ENTRIES, minor);
5504
5505         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5506                                  1, minor);
5507
5508         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5509                 struct drm_info_list *info_list =
5510                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5511
5512                 drm_debugfs_remove_files(info_list, 1, minor);
5513         }
5514
5515         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5516                 struct drm_info_list *info_list =
5517                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5518
5519                 drm_debugfs_remove_files(info_list, 1, minor);
5520         }
5521 }
5522
5523 struct dpcd_block {
5524         /* DPCD dump start address. */
5525         unsigned int offset;
5526         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5527         unsigned int end;
5528         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5529         size_t size;
5530         /* Only valid for eDP. */
5531         bool edp;
5532 };
5533
5534 static const struct dpcd_block i915_dpcd_debug[] = {
5535         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5536         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5537         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5538         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5539         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5540         { .offset = DP_SET_POWER },
5541         { .offset = DP_EDP_DPCD_REV },
5542         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5543         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5544         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5545 };
5546
5547 static int i915_dpcd_show(struct seq_file *m, void *data)
5548 {
5549         struct drm_connector *connector = m->private;
5550         struct intel_dp *intel_dp =
5551                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5552         uint8_t buf[16];
5553         ssize_t err;
5554         int i;
5555
5556         if (connector->status != connector_status_connected)
5557                 return -ENODEV;
5558
5559         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5560                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5561                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5562
5563                 if (b->edp &&
5564                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5565                         continue;
5566
5567                 /* low tech for now */
5568                 if (WARN_ON(size > sizeof(buf)))
5569                         continue;
5570
5571                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5572                 if (err <= 0) {
5573                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5574                                   size, b->offset, err);
5575                         continue;
5576                 }
5577
5578                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5579         }
5580
5581         return 0;
5582 }
5583
5584 static int i915_dpcd_open(struct inode *inode, struct file *file)
5585 {
5586         return single_open(file, i915_dpcd_show, inode->i_private);
5587 }
5588
5589 static const struct file_operations i915_dpcd_fops = {
5590         .owner = THIS_MODULE,
5591         .open = i915_dpcd_open,
5592         .read = seq_read,
5593         .llseek = seq_lseek,
5594         .release = single_release,
5595 };
5596
5597 /**
5598  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5599  * @connector: pointer to a registered drm_connector
5600  *
5601  * Cleanup will be done by drm_connector_unregister() through a call to
5602  * drm_debugfs_connector_remove().
5603  *
5604  * Returns 0 on success, negative error codes on error.
5605  */
5606 int i915_debugfs_connector_add(struct drm_connector *connector)
5607 {
5608         struct dentry *root = connector->debugfs_entry;
5609
5610         /* The connector must have been registered beforehands. */
5611         if (!root)
5612                 return -ENODEV;
5613
5614         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5615             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5616                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5617                                     &i915_dpcd_fops);
5618
5619         return 0;
5620 }