drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/apple-gmux.h>
  39 #include <linux/console.h>
  40 #include <linux/module.h>
  41 #include <linux/pm_runtime.h>
  42 #include <linux/vgaarb.h>
  43 #include <linux/vga_switcheroo.h>
  44 #include <drm/drm_crtc_helper.h>
  45
  46 static struct drm_driver driver;
  47
  48 #define GEN_DEFAULT_PIPEOFFSETS \
  49         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  50                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  51         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  52                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  53         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  54
  55 #define GEN_CHV_PIPEOFFSETS \
  56         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  57                           CHV_PIPE_C_OFFSET }, \
  58         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  59                            CHV_TRANSCODER_C_OFFSET, }, \
  60         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  61                              CHV_PALETTE_C_OFFSET }
  62
  63 #define CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  65
  66 #define IVB_CURSOR_OFFSETS \
  67         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  68
  69 #define BDW_COLORS \
  70         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  71 #define CHV_COLORS \
  72         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  73
  74 static const struct intel_device_info intel_i830_info = {
  75         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_845g_info = {
  83         .gen = 2, .num_pipes = 1,
  84         .has_overlay = 1, .overlay_needs_physical = 1,
  85         .ring_mask = RENDER_RING,
  86         GEN_DEFAULT_PIPEOFFSETS,
  87         CURSOR_OFFSETS,
  88 };
  89
  90 static const struct intel_device_info intel_i85x_info = {
  91         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  92         .cursor_needs_physical = 1,
  93         .has_overlay = 1, .overlay_needs_physical = 1,
  94         .has_fbc = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i865g_info = {
 101         .gen = 2, .num_pipes = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107
 108 static const struct intel_device_info intel_i915g_info = {
 109         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .ring_mask = RENDER_RING,
 112         GEN_DEFAULT_PIPEOFFSETS,
 113         CURSOR_OFFSETS,
 114 };
 115 static const struct intel_device_info intel_i915gm_info = {
 116         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 117         .cursor_needs_physical = 1,
 118         .has_overlay = 1, .overlay_needs_physical = 1,
 119         .supports_tv = 1,
 120         .has_fbc = 1,
 121         .ring_mask = RENDER_RING,
 122         GEN_DEFAULT_PIPEOFFSETS,
 123         CURSOR_OFFSETS,
 124 };
 125 static const struct intel_device_info intel_i945g_info = {
 126         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .ring_mask = RENDER_RING,
 129         GEN_DEFAULT_PIPEOFFSETS,
 130         CURSOR_OFFSETS,
 131 };
 132 static const struct intel_device_info intel_i945gm_info = {
 133         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 134         .has_hotplug = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136         .supports_tv = 1,
 137         .has_fbc = 1,
 138         .ring_mask = RENDER_RING,
 139         GEN_DEFAULT_PIPEOFFSETS,
 140         CURSOR_OFFSETS,
 141 };
 142
 143 static const struct intel_device_info intel_i965g_info = {
 144         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 145         .has_hotplug = 1,
 146         .has_overlay = 1,
 147         .ring_mask = RENDER_RING,
 148         GEN_DEFAULT_PIPEOFFSETS,
 149         CURSOR_OFFSETS,
 150 };
 151
 152 static const struct intel_device_info intel_i965gm_info = {
 153         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 154         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 155         .has_overlay = 1,
 156         .supports_tv = 1,
 157         .ring_mask = RENDER_RING,
 158         GEN_DEFAULT_PIPEOFFSETS,
 159         CURSOR_OFFSETS,
 160 };
 161
 162 static const struct intel_device_info intel_g33_info = {
 163         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 164         .need_gfx_hws = 1, .has_hotplug = 1,
 165         .has_overlay = 1,
 166         .ring_mask = RENDER_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_g45_info = {
 172         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 173         .has_pipe_cxsr = 1, .has_hotplug = 1,
 174         .ring_mask = RENDER_RING | BSD_RING,
 175         GEN_DEFAULT_PIPEOFFSETS,
 176         CURSOR_OFFSETS,
 177 };
 178
 179 static const struct intel_device_info intel_gm45_info = {
 180         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 181         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 182         .has_pipe_cxsr = 1, .has_hotplug = 1,
 183         .supports_tv = 1,
 184         .ring_mask = RENDER_RING | BSD_RING,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_pineview_info = {
 190         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .has_overlay = 1,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_d_info = {
 198         .gen = 5, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .ring_mask = RENDER_RING | BSD_RING,
 201         GEN_DEFAULT_PIPEOFFSETS,
 202         CURSOR_OFFSETS,
 203 };
 204
 205 static const struct intel_device_info intel_ironlake_m_info = {
 206         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 207         .need_gfx_hws = 1, .has_hotplug = 1,
 208         .has_fbc = 1,
 209         .ring_mask = RENDER_RING | BSD_RING,
 210         GEN_DEFAULT_PIPEOFFSETS,
 211         CURSOR_OFFSETS,
 212 };
 213
 214 static const struct intel_device_info intel_sandybridge_d_info = {
 215         .gen = 6, .num_pipes = 2,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_fbc = 1,
 218         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 219         .has_llc = 1,
 220         GEN_DEFAULT_PIPEOFFSETS,
 221         CURSOR_OFFSETS,
 222 };
 223
 224 static const struct intel_device_info intel_sandybridge_m_info = {
 225         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 226         .need_gfx_hws = 1, .has_hotplug = 1,
 227         .has_fbc = 1,
 228         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 229         .has_llc = 1,
 230         GEN_DEFAULT_PIPEOFFSETS,
 231         CURSOR_OFFSETS,
 232 };
 233
 234 #define GEN7_FEATURES  \
 235         .gen = 7, .num_pipes = 3, \
 236         .need_gfx_hws = 1, .has_hotplug = 1, \
 237         .has_fbc = 1, \
 238         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 239         .has_llc = 1, \
 240         GEN_DEFAULT_PIPEOFFSETS, \
 241         IVB_CURSOR_OFFSETS
 242
 243 static const struct intel_device_info intel_ivybridge_d_info = {
 244         GEN7_FEATURES,
 245         .is_ivybridge = 1,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_m_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .is_mobile = 1,
 252 };
 253
 254 static const struct intel_device_info intel_ivybridge_q_info = {
 255         GEN7_FEATURES,
 256         .is_ivybridge = 1,
 257         .num_pipes = 0, /* legal, last one wins */
 258 };
 259
 260 #define VLV_FEATURES  \
 261         .gen = 7, .num_pipes = 2, \
 262         .need_gfx_hws = 1, .has_hotplug = 1, \
 263         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 264         .display_mmio_offset = VLV_DISPLAY_BASE, \
 265         GEN_DEFAULT_PIPEOFFSETS, \
 266         CURSOR_OFFSETS
 267
 268 static const struct intel_device_info intel_valleyview_m_info = {
 269         VLV_FEATURES,
 270         .is_valleyview = 1,
 271         .is_mobile = 1,
 272 };
 273
 274 static const struct intel_device_info intel_valleyview_d_info = {
 275         VLV_FEATURES,
 276         .is_valleyview = 1,
 277 };
 278
 279 #define HSW_FEATURES  \
 280         GEN7_FEATURES, \
 281         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 282         .has_ddi = 1, \
 283         .has_fpga_dbg = 1
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         HSW_FEATURES,
 287         .is_haswell = 1,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_m_info = {
 291         HSW_FEATURES,
 292         .is_haswell = 1,
 293         .is_mobile = 1,
 294 };
 295
 296 #define BDW_FEATURES \
 297         HSW_FEATURES, \
 298         BDW_COLORS
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         BDW_FEATURES,
 302         .gen = 8,
 303 };
 304
 305 static const struct intel_device_info intel_broadwell_m_info = {
 306         BDW_FEATURES,
 307         .gen = 8, .is_mobile = 1,
 308 };
 309
 310 static const struct intel_device_info intel_broadwell_gt3d_info = {
 311         BDW_FEATURES,
 312         .gen = 8,
 313         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 314 };
 315
 316 static const struct intel_device_info intel_broadwell_gt3m_info = {
 317         BDW_FEATURES,
 318         .gen = 8, .is_mobile = 1,
 319         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 320 };
 321
 322 static const struct intel_device_info intel_cherryview_info = {
 323         .gen = 8, .num_pipes = 3,
 324         .need_gfx_hws = 1, .has_hotplug = 1,
 325         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 326         .is_cherryview = 1,
 327         .display_mmio_offset = VLV_DISPLAY_BASE,
 328         GEN_CHV_PIPEOFFSETS,
 329         CURSOR_OFFSETS,
 330         CHV_COLORS,
 331 };
 332
 333 static const struct intel_device_info intel_skylake_info = {
 334         BDW_FEATURES,
 335         .is_skylake = 1,
 336         .gen = 9,
 337 };
 338
 339 static const struct intel_device_info intel_skylake_gt3_info = {
 340         BDW_FEATURES,
 341         .is_skylake = 1,
 342         .gen = 9,
 343         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 344 };
 345
 346 static const struct intel_device_info intel_broxton_info = {
 347         .is_preliminary = 1,
 348         .is_broxton = 1,
 349         .gen = 9,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .num_pipes = 3,
 353         .has_ddi = 1,
 354         .has_fpga_dbg = 1,
 355         .has_fbc = 1,
 356         GEN_DEFAULT_PIPEOFFSETS,
 357         IVB_CURSOR_OFFSETS,
 358         BDW_COLORS,
 359 };
 360
 361 static const struct intel_device_info intel_kabylake_info = {
 362         BDW_FEATURES,
 363         .is_kabylake = 1,
 364         .gen = 9,
 365 };
 366
 367 static const struct intel_device_info intel_kabylake_gt3_info = {
 368         BDW_FEATURES,
 369         .is_kabylake = 1,
 370         .gen = 9,
 371         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 372 };
 373
 374 /*
 375  * Make sure any device matches here are from most specific to most
 376  * general.  For example, since the Quanta match is based on the subsystem
 377  * and subvendor IDs, we need it to come before the more general IVB
 378  * PCI ID matches, otherwise we'll use the wrong info struct above.
 379  */
 380 static const struct pci_device_id pciidlist[] = {
 381         INTEL_I830_IDS(&intel_i830_info),
 382         INTEL_I845G_IDS(&intel_845g_info),
 383         INTEL_I85X_IDS(&intel_i85x_info),
 384         INTEL_I865G_IDS(&intel_i865g_info),
 385         INTEL_I915G_IDS(&intel_i915g_info),
 386         INTEL_I915GM_IDS(&intel_i915gm_info),
 387         INTEL_I945G_IDS(&intel_i945g_info),
 388         INTEL_I945GM_IDS(&intel_i945gm_info),
 389         INTEL_I965G_IDS(&intel_i965g_info),
 390         INTEL_G33_IDS(&intel_g33_info),
 391         INTEL_I965GM_IDS(&intel_i965gm_info),
 392         INTEL_GM45_IDS(&intel_gm45_info),
 393         INTEL_G45_IDS(&intel_g45_info),
 394         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 395         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 396         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 397         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 398         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 399         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 400         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 401         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 402         INTEL_HSW_D_IDS(&intel_haswell_d_info),
 403         INTEL_HSW_M_IDS(&intel_haswell_m_info),
 404         INTEL_VLV_M_IDS(&intel_valleyview_m_info),
 405         INTEL_VLV_D_IDS(&intel_valleyview_d_info),
 406         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
 407         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
 408         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
 409         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
 410         INTEL_CHV_IDS(&intel_cherryview_info),
 411         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 412         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 413         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 414         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 415         INTEL_BXT_IDS(&intel_broxton_info),
 416         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 417         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 418         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 419         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 420         {0, 0, 0}
 421 };
 422
 423 MODULE_DEVICE_TABLE(pci, pciidlist);
 424
 425 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 426 {
 427         enum intel_pch ret = PCH_NOP;
 428
 429         /*
 430          * In a virtualized passthrough environment we can be in a
 431          * setup where the ISA bridge is not able to be passed through.
 432          * In this case, a south bridge can be emulated and we have to
 433          * make an educated guess as to which PCH is really there.
 434          */
 435
 436         if (IS_GEN5(dev)) {
 437                 ret = PCH_IBX;
 438                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 439         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 440                 ret = PCH_CPT;
 441                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 442         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 443                 ret = PCH_LPT;
 444                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 445         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 446                 ret = PCH_SPT;
 447                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 448         }
 449
 450         return ret;
 451 }
 452
 453 void intel_detect_pch(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         struct pci_dev *pch = NULL;
 457
 458         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 459          * (which really amounts to a PCH but no South Display).
 460          */
 461         if (INTEL_INFO(dev)->num_pipes == 0) {
 462                 dev_priv->pch_type = PCH_NOP;
 463                 return;
 464         }
 465
 466         /*
 467          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 468          * make graphics device passthrough work easy for VMM, that only
 469          * need to expose ISA bridge to let driver know the real hardware
 470          * underneath. This is a requirement from virtualization team.
 471          *
 472          * In some virtualized environments (e.g. XEN), there is irrelevant
 473          * ISA bridge in the system. To work reliably, we should scan trhough
 474          * all the ISA bridge devices and check for the first match, instead
 475          * of only checking the first one.
 476          */
 477         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 478                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 479                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 480                         dev_priv->pch_id = id;
 481
 482                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 483                                 dev_priv->pch_type = PCH_IBX;
 484                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 485                                 WARN_ON(!IS_GEN5(dev));
 486                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 487                                 dev_priv->pch_type = PCH_CPT;
 488                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 489                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 490                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 491                                 /* PantherPoint is CPT compatible */
 492                                 dev_priv->pch_type = PCH_CPT;
 493                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 494                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 495                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 496                                 dev_priv->pch_type = PCH_LPT;
 497                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 498                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 499                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 500                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 501                                 dev_priv->pch_type = PCH_LPT;
 502                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 503                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 504                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 505                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 506                                 dev_priv->pch_type = PCH_SPT;
 507                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 508                                 WARN_ON(!IS_SKYLAKE(dev) &&
 509                                         !IS_KABYLAKE(dev));
 510                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 511                                 dev_priv->pch_type = PCH_SPT;
 512                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 513                                 WARN_ON(!IS_SKYLAKE(dev) &&
 514                                         !IS_KABYLAKE(dev));
 515                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 516                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 517                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 518                                     pch->subsystem_vendor == 0x1af4 &&
 519                                     pch->subsystem_device == 0x1100)) {
 520                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 521                         } else
 522                                 continue;
 523
 524                         break;
 525                 }
 526         }
 527         if (!pch)
 528                 DRM_DEBUG_KMS("No PCH found.\n");
 529
 530         pci_dev_put(pch);
 531 }
 532
 533 bool i915_semaphore_is_enabled(struct drm_device *dev)
 534 {
 535         if (INTEL_INFO(dev)->gen < 6)
 536                 return false;
 537
 538         if (i915.semaphores >= 0)
 539                 return i915.semaphores;
 540
 541         /* TODO: make semaphores and Execlists play nicely together */
 542         if (i915.enable_execlists)
 543                 return false;
 544
 545         /* Until we get further testing... */
 546         if (IS_GEN8(dev))
 547                 return false;
 548
 549 #ifdef CONFIG_INTEL_IOMMU
 550         /* Enable semaphores on SNB when IO remapping is off */
 551         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 552                 return false;
 553 #endif
 554
 555         return true;
 556 }
 557
 558 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 559 {
 560         struct drm_device *dev = dev_priv->dev;
 561         struct intel_encoder *encoder;
 562
 563         drm_modeset_lock_all(dev);
 564         for_each_intel_encoder(dev, encoder)
 565                 if (encoder->suspend)
 566                         encoder->suspend(encoder);
 567         drm_modeset_unlock_all(dev);
 568 }
 569
 570 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 571                               bool rpm_resume);
 572 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
 573
 574 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
 575 {
 576 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 577         if (acpi_target_system_state() < ACPI_STATE_S3)
 578                 return true;
 579 #endif
 580         return false;
 581 }
 582
 583 static int i915_drm_suspend(struct drm_device *dev)
 584 {
 585         struct drm_i915_private *dev_priv = dev->dev_private;
 586         pci_power_t opregion_target_state;
 587         int error;
 588
 589         /* ignore lid events during suspend */
 590         mutex_lock(&dev_priv->modeset_restore_lock);
 591         dev_priv->modeset_restore = MODESET_SUSPENDED;
 592         mutex_unlock(&dev_priv->modeset_restore_lock);
 593
 594         disable_rpm_wakeref_asserts(dev_priv);
 595
 596         /* We do a lot of poking in a lot of registers, make sure they work
 597          * properly. */
 598         intel_display_set_init_power(dev_priv, true);
 599
 600         drm_kms_helper_poll_disable(dev);
 601
 602         pci_save_state(dev->pdev);
 603
 604         error = i915_gem_suspend(dev);
 605         if (error) {
 606                 dev_err(&dev->pdev->dev,
 607                         "GEM idle failed, resume might fail\n");
 608                 goto out;
 609         }
 610
 611         intel_guc_suspend(dev);
 612
 613         intel_suspend_gt_powersave(dev);
 614
 615         intel_display_suspend(dev);
 616
 617         intel_dp_mst_suspend(dev);
 618
 619         intel_runtime_pm_disable_interrupts(dev_priv);
 620         intel_hpd_cancel_work(dev_priv);
 621
 622         intel_suspend_encoders(dev_priv);
 623
 624         intel_suspend_hw(dev);
 625
 626         i915_gem_suspend_gtt_mappings(dev);
 627
 628         i915_save_state(dev);
 629
 630         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
 631         intel_opregion_notify_adapter(dev, opregion_target_state);
 632
 633         intel_uncore_forcewake_reset(dev, false);
 634         intel_opregion_fini(dev);
 635
 636         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 637
 638         dev_priv->suspend_count++;
 639
 640         intel_display_set_init_power(dev_priv, false);
 641
 642         intel_csr_ucode_suspend(dev_priv);
 643
 644 out:
 645         enable_rpm_wakeref_asserts(dev_priv);
 646
 647         return error;
 648 }
 649
 650 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 651 {
 652         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 653         bool fw_csr;
 654         int ret;
 655
 656         disable_rpm_wakeref_asserts(dev_priv);
 657
 658         fw_csr = !IS_BROXTON(dev_priv) &&
 659                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
 660         /*
 661          * In case of firmware assisted context save/restore don't manually
 662          * deinit the power domains. This also means the CSR/DMC firmware will
 663          * stay active, it will power down any HW resources as required and
 664          * also enable deeper system power states that would be blocked if the
 665          * firmware was inactive.
 666          */
 667         if (!fw_csr)
 668                 intel_power_domains_suspend(dev_priv);
 669
 670         ret = 0;
 671         if (IS_BROXTON(dev_priv))
 672                 bxt_enable_dc9(dev_priv);
 673         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 674                 hsw_enable_pc8(dev_priv);
 675         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 676                 ret = vlv_suspend_complete(dev_priv);
 677
 678         if (ret) {
 679                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 680                 if (!fw_csr)
 681                         intel_power_domains_init_hw(dev_priv, true);
 682
 683                 goto out;
 684         }
 685
 686         pci_disable_device(drm_dev->pdev);
 687         /*
 688          * During hibernation on some platforms the BIOS may try to access
 689          * the device even though it's already in D3 and hang the machine. So
 690          * leave the device in D0 on those platforms and hope the BIOS will
 691          * power down the device properly. The issue was seen on multiple old
 692          * GENs with different BIOS vendors, so having an explicit blacklist
 693          * is inpractical; apply the workaround on everything pre GEN6. The
 694          * platforms where the issue was seen:
 695          * Lenovo Thinkpad X301, X61s, X60, T60, X41
 696          * Fujitsu FSC S7110
 697          * Acer Aspire 1830T
 698          */
 699         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 700                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 701
 702         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
 703
 704 out:
 705         enable_rpm_wakeref_asserts(dev_priv);
 706
 707         return ret;
 708 }
 709
 710 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 711 {
 712         int error;
 713
 714         if (!dev || !dev->dev_private) {
 715                 DRM_ERROR("dev: %p\n", dev);
 716                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 717                 return -ENODEV;
 718         }
 719
 720         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 721                          state.event != PM_EVENT_FREEZE))
 722                 return -EINVAL;
 723
 724         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 725                 return 0;
 726
 727         error = i915_drm_suspend(dev);
 728         if (error)
 729                 return error;
 730
 731         return i915_drm_suspend_late(dev, false);
 732 }
 733
 734 static int i915_drm_resume(struct drm_device *dev)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737
 738         disable_rpm_wakeref_asserts(dev_priv);
 739
 740         intel_csr_ucode_resume(dev_priv);
 741
 742         mutex_lock(&dev->struct_mutex);
 743         i915_gem_restore_gtt_mappings(dev);
 744         mutex_unlock(&dev->struct_mutex);
 745
 746         i915_restore_state(dev);
 747         intel_opregion_setup(dev);
 748
 749         intel_init_pch_refclk(dev);
 750         drm_mode_config_reset(dev);
 751
 752         /*
 753          * Interrupts have to be enabled before any batches are run. If not the
 754          * GPU will hang. i915_gem_init_hw() will initiate batches to
 755          * update/restore the context.
 756          *
 757          * Modeset enabling in intel_modeset_init_hw() also needs working
 758          * interrupts.
 759          */
 760         intel_runtime_pm_enable_interrupts(dev_priv);
 761
 762         mutex_lock(&dev->struct_mutex);
 763         if (i915_gem_init_hw(dev)) {
 764                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 765                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 766         }
 767         mutex_unlock(&dev->struct_mutex);
 768
 769         intel_guc_resume(dev);
 770
 771         intel_modeset_init_hw(dev);
 772
 773         spin_lock_irq(&dev_priv->irq_lock);
 774         if (dev_priv->display.hpd_irq_setup)
 775                 dev_priv->display.hpd_irq_setup(dev);
 776         spin_unlock_irq(&dev_priv->irq_lock);
 777
 778         intel_dp_mst_resume(dev);
 779
 780         intel_display_resume(dev);
 781
 782         /*
 783          * ... but also need to make sure that hotplug processing
 784          * doesn't cause havoc. Like in the driver load code we don't
 785          * bother with the tiny race here where we might loose hotplug
 786          * notifications.
 787          * */
 788         intel_hpd_init(dev_priv);
 789         /* Config may have changed between suspend and resume */
 790         drm_helper_hpd_irq_event(dev);
 791
 792         intel_opregion_init(dev);
 793
 794         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 795
 796         mutex_lock(&dev_priv->modeset_restore_lock);
 797         dev_priv->modeset_restore = MODESET_DONE;
 798         mutex_unlock(&dev_priv->modeset_restore_lock);
 799
 800         intel_opregion_notify_adapter(dev, PCI_D0);
 801
 802         drm_kms_helper_poll_enable(dev);
 803
 804         enable_rpm_wakeref_asserts(dev_priv);
 805
 806         return 0;
 807 }
 808
 809 static int i915_drm_resume_early(struct drm_device *dev)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         int ret;
 813
 814         /*
 815          * We have a resume ordering issue with the snd-hda driver also
 816          * requiring our device to be power up. Due to the lack of a
 817          * parent/child relationship we currently solve this with an early
 818          * resume hook.
 819          *
 820          * FIXME: This should be solved with a special hdmi sink device or
 821          * similar so that power domains can be employed.
 822          */
 823
 824         /*
 825          * Note that we need to set the power state explicitly, since we
 826          * powered off the device during freeze and the PCI core won't power
 827          * it back up for us during thaw. Powering off the device during
 828          * freeze is not a hard requirement though, and during the
 829          * suspend/resume phases the PCI core makes sure we get here with the
 830          * device powered on. So in case we change our freeze logic and keep
 831          * the device powered we can also remove the following set power state
 832          * call.
 833          */
 834         ret = pci_set_power_state(dev->pdev, PCI_D0);
 835         if (ret) {
 836                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
 837                 goto out;
 838         }
 839
 840         /*
 841          * Note that pci_enable_device() first enables any parent bridge
 842          * device and only then sets the power state for this device. The
 843          * bridge enabling is a nop though, since bridge devices are resumed
 844          * first. The order of enabling power and enabling the device is
 845          * imposed by the PCI core as described above, so here we preserve the
 846          * same order for the freeze/thaw phases.
 847          *
 848          * TODO: eventually we should remove pci_disable_device() /
 849          * pci_enable_enable_device() from suspend/resume. Due to how they
 850          * depend on the device enable refcount we can't anyway depend on them
 851          * disabling/enabling the device.
 852          */
 853         if (pci_enable_device(dev->pdev)) {
 854                 ret = -EIO;
 855                 goto out;
 856         }
 857
 858         pci_set_master(dev->pdev);
 859
 860         disable_rpm_wakeref_asserts(dev_priv);
 861
 862         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 863                 ret = vlv_resume_prepare(dev_priv, false);
 864         if (ret)
 865                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 866                           ret);
 867
 868         intel_uncore_early_sanitize(dev, true);
 869
 870         if (IS_BROXTON(dev)) {
 871                 if (!dev_priv->suspended_to_idle)
 872                         gen9_sanitize_dc_state(dev_priv);
 873                 bxt_disable_dc9(dev_priv);
 874         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 875                 hsw_disable_pc8(dev_priv);
 876         }
 877
 878         intel_uncore_sanitize(dev);
 879
 880         if (IS_BROXTON(dev_priv) ||
 881             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
 882                 intel_power_domains_init_hw(dev_priv, true);
 883
 884         enable_rpm_wakeref_asserts(dev_priv);
 885
 886 out:
 887         dev_priv->suspended_to_idle = false;
 888
 889         return ret;
 890 }
 891
 892 int i915_resume_switcheroo(struct drm_device *dev)
 893 {
 894         int ret;
 895
 896         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 897                 return 0;
 898
 899         ret = i915_drm_resume_early(dev);
 900         if (ret)
 901                 return ret;
 902
 903         return i915_drm_resume(dev);
 904 }
 905
 906 /**
 907  * i915_reset - reset chip after a hang
 908  * @dev: drm device to reset
 909  *
 910  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 911  * reset or otherwise an error code.
 912  *
 913  * Procedure is fairly simple:
 914  *   - reset the chip using the reset reg
 915  *   - re-init context state
 916  *   - re-init hardware status page
 917  *   - re-init ring buffer
 918  *   - re-init interrupt state
 919  *   - re-init display
 920  */
 921 int i915_reset(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         struct i915_gpu_error *error = &dev_priv->gpu_error;
 925         unsigned reset_counter;
 926         int ret;
 927
 928         intel_reset_gt_powersave(dev);
 929
 930         mutex_lock(&dev->struct_mutex);
 931
 932         /* Clear any previous failed attempts at recovery. Time to try again. */
 933         atomic_andnot(I915_WEDGED, &error->reset_counter);
 934
 935         /* Clear the reset-in-progress flag and increment the reset epoch. */
 936         reset_counter = atomic_inc_return(&error->reset_counter);
 937         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
 938                 ret = -EIO;
 939                 goto error;
 940         }
 941
 942         i915_gem_reset(dev);
 943
 944         ret = intel_gpu_reset(dev, ALL_ENGINES);
 945
 946         /* Also reset the gpu hangman. */
 947         if (error->stop_rings != 0) {
 948                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 949                 error->stop_rings = 0;
 950                 if (ret == -ENODEV) {
 951                         DRM_INFO("Reset not implemented, but ignoring "
 952                                  "error for simulated gpu hangs\n");
 953                         ret = 0;
 954                 }
 955         }
 956
 957         if (i915_stop_ring_allow_warn(dev_priv))
 958                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 959
 960         if (ret) {
 961                 if (ret != -ENODEV)
 962                         DRM_ERROR("Failed to reset chip: %i\n", ret);
 963                 else
 964                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
 965                 goto error;
 966         }
 967
 968         intel_overlay_reset(dev_priv);
 969
 970         /* Ok, now get things going again... */
 971
 972         /*
 973          * Everything depends on having the GTT running, so we need to start
 974          * there.  Fortunately we don't need to do this unless we reset the
 975          * chip at a PCI level.
 976          *
 977          * Next we need to restore the context, but we don't use those
 978          * yet either...
 979          *
 980          * Ring buffer needs to be re-initialized in the KMS case, or if X
 981          * was running at the time of the reset (i.e. we weren't VT
 982          * switched away).
 983          */
 984         ret = i915_gem_init_hw(dev);
 985         if (ret) {
 986                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 987                 goto error;
 988         }
 989
 990         mutex_unlock(&dev->struct_mutex);
 991
 992         /*
 993          * rps/rc6 re-init is necessary to restore state lost after the
 994          * reset and the re-install of gt irqs. Skip for ironlake per
 995          * previous concerns that it doesn't respond well to some forms
 996          * of re-init after reset.
 997          */
 998         if (INTEL_INFO(dev)->gen > 5)
 999                 intel_enable_gt_powersave(dev);
1000
1001         return 0;
1002
1003 error:
1004         atomic_or(I915_WEDGED, &error->reset_counter);
1005         mutex_unlock(&dev->struct_mutex);
1006         return ret;
1007 }
1008
1009 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1010 {
1011         struct intel_device_info *intel_info =
1012                 (struct intel_device_info *) ent->driver_data;
1013
1014         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
1015                 DRM_INFO("This hardware requires preliminary hardware support.\n"
1016                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1017                 return -ENODEV;
1018         }
1019
1020         /* Only bind to function 0 of the device. Early generations
1021          * used function 1 as a placeholder for multi-head. This causes
1022          * us confusion instead, especially on the systems where both
1023          * functions have the same PCI-ID!
1024          */
1025         if (PCI_FUNC(pdev->devfn))
1026                 return -ENODEV;
1027
1028         /*
1029          * apple-gmux is needed on dual GPU MacBook Pro
1030          * to probe the panel if we're the inactive GPU.
1031          */
1032         if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1033             apple_gmux_present() && pdev != vga_default_device() &&
1034             !vga_switcheroo_handler_flags())
1035                 return -EPROBE_DEFER;
1036
1037         return drm_get_pci_dev(pdev, ent, &driver);
1038 }
1039
1040 static void
1041 i915_pci_remove(struct pci_dev *pdev)
1042 {
1043         struct drm_device *dev = pci_get_drvdata(pdev);
1044
1045         drm_put_dev(dev);
1046 }
1047
1048 static int i915_pm_suspend(struct device *dev)
1049 {
1050         struct pci_dev *pdev = to_pci_dev(dev);
1051         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1052
1053         if (!drm_dev || !drm_dev->dev_private) {
1054                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1055                 return -ENODEV;
1056         }
1057
1058         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1059                 return 0;
1060
1061         return i915_drm_suspend(drm_dev);
1062 }
1063
1064 static int i915_pm_suspend_late(struct device *dev)
1065 {
1066         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1067
1068         /*
1069          * We have a suspend ordering issue with the snd-hda driver also
1070          * requiring our device to be power up. Due to the lack of a
1071          * parent/child relationship we currently solve this with an late
1072          * suspend hook.
1073          *
1074          * FIXME: This should be solved with a special hdmi sink device or
1075          * similar so that power domains can be employed.
1076          */
1077         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1078                 return 0;
1079
1080         return i915_drm_suspend_late(drm_dev, false);
1081 }
1082
1083 static int i915_pm_poweroff_late(struct device *dev)
1084 {
1085         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1086
1087         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1088                 return 0;
1089
1090         return i915_drm_suspend_late(drm_dev, true);
1091 }
1092
1093 static int i915_pm_resume_early(struct device *dev)
1094 {
1095         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1096
1097         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1098                 return 0;
1099
1100         return i915_drm_resume_early(drm_dev);
1101 }
1102
1103 static int i915_pm_resume(struct device *dev)
1104 {
1105         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1106
1107         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1108                 return 0;
1109
1110         return i915_drm_resume(drm_dev);
1111 }
1112
1113 /*
1114  * Save all Gunit registers that may be lost after a D3 and a subsequent
1115  * S0i[R123] transition. The list of registers needing a save/restore is
1116  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1117  * registers in the following way:
1118  * - Driver: saved/restored by the driver
1119  * - Punit : saved/restored by the Punit firmware
1120  * - No, w/o marking: no need to save/restore, since the register is R/O or
1121  *                    used internally by the HW in a way that doesn't depend
1122  *                    keeping the content across a suspend/resume.
1123  * - Debug : used for debugging
1124  *
1125  * We save/restore all registers marked with 'Driver', with the following
1126  * exceptions:
1127  * - Registers out of use, including also registers marked with 'Debug'.
1128  *   These have no effect on the driver's operation, so we don't save/restore
1129  *   them to reduce the overhead.
1130  * - Registers that are fully setup by an initialization function called from
1131  *   the resume path. For example many clock gating and RPS/RC6 registers.
1132  * - Registers that provide the right functionality with their reset defaults.
1133  *
1134  * TODO: Except for registers that based on the above 3 criteria can be safely
1135  * ignored, we save/restore all others, practically treating the HW context as
1136  * a black-box for the driver. Further investigation is needed to reduce the
1137  * saved/restored registers even further, by following the same 3 criteria.
1138  */
1139 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1140 {
1141         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1142         int i;
1143
1144         /* GAM 0x4000-0x4770 */
1145         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1146         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1147         s->arb_mode             = I915_READ(ARB_MODE);
1148         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1149         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1150
1151         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1152                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1153
1154         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1155         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1156
1157         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1158         s->ecochk               = I915_READ(GAM_ECOCHK);
1159         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1160         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1161
1162         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1163
1164         /* MBC 0x9024-0x91D0, 0x8500 */
1165         s->g3dctl               = I915_READ(VLV_G3DCTL);
1166         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1167         s->mbctl                = I915_READ(GEN6_MBCTL);
1168
1169         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1170         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1171         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1172         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1173         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1174         s->rstctl               = I915_READ(GEN6_RSTCTL);
1175         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1176
1177         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1178         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1179         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1180         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1181         s->ecobus               = I915_READ(ECOBUS);
1182         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1183         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1184         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1185         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1186         s->rcedata              = I915_READ(VLV_RCEDATA);
1187         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1188
1189         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1190         s->gt_imr               = I915_READ(GTIMR);
1191         s->gt_ier               = I915_READ(GTIER);
1192         s->pm_imr               = I915_READ(GEN6_PMIMR);
1193         s->pm_ier               = I915_READ(GEN6_PMIER);
1194
1195         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1196                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1197
1198         /* GT SA CZ domain, 0x100000-0x138124 */
1199         s->tilectl              = I915_READ(TILECTL);
1200         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1201         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1202         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1203         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1204
1205         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1206         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1207         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1208         s->pcbr                 = I915_READ(VLV_PCBR);
1209         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1210
1211         /*
1212          * Not saving any of:
1213          * DFT,         0x9800-0x9EC0
1214          * SARB,        0xB000-0xB1FC
1215          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1216          * PCI CFG
1217          */
1218 }
1219
1220 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1221 {
1222         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1223         u32 val;
1224         int i;
1225
1226         /* GAM 0x4000-0x4770 */
1227         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1228         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1229         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1230         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1231         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1232
1233         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1234                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1235
1236         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1237         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1238
1239         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1240         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1241         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1242         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1243
1244         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1245
1246         /* MBC 0x9024-0x91D0, 0x8500 */
1247         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1248         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1249         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1250
1251         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1252         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1253         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1254         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1255         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1256         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1257         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1258
1259         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1260         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1261         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1262         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1263         I915_WRITE(ECOBUS,              s->ecobus);
1264         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1265         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1266         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1267         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1268         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1269         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1270
1271         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1272         I915_WRITE(GTIMR,               s->gt_imr);
1273         I915_WRITE(GTIER,               s->gt_ier);
1274         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1275         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1276
1277         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1278                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1279
1280         /* GT SA CZ domain, 0x100000-0x138124 */
1281         I915_WRITE(TILECTL,                     s->tilectl);
1282         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1283         /*
1284          * Preserve the GT allow wake and GFX force clock bit, they are not
1285          * be restored, as they are used to control the s0ix suspend/resume
1286          * sequence by the caller.
1287          */
1288         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1289         val &= VLV_GTLC_ALLOWWAKEREQ;
1290         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1291         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1292
1293         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1294         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1295         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1296         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1297
1298         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1299
1300         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1301         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1302         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1303         I915_WRITE(VLV_PCBR,                    s->pcbr);
1304         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1305 }
1306
1307 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1308 {
1309         u32 val;
1310         int err;
1311
1312 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1313
1314         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1315         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1316         if (force_on)
1317                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1318         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1319
1320         if (!force_on)
1321                 return 0;
1322
1323         err = wait_for(COND, 20);
1324         if (err)
1325                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1326                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1327
1328         return err;
1329 #undef COND
1330 }
1331
1332 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1333 {
1334         u32 val;
1335         int err = 0;
1336
1337         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1338         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1339         if (allow)
1340                 val |= VLV_GTLC_ALLOWWAKEREQ;
1341         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1342         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1343
1344 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1345               allow)
1346         err = wait_for(COND, 1);
1347         if (err)
1348                 DRM_ERROR("timeout disabling GT waking\n");
1349         return err;
1350 #undef COND
1351 }
1352
1353 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1354                                  bool wait_for_on)
1355 {
1356         u32 mask;
1357         u32 val;
1358         int err;
1359
1360         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1361         val = wait_for_on ? mask : 0;
1362 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1363         if (COND)
1364                 return 0;
1365
1366         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1367                       onoff(wait_for_on),
1368                       I915_READ(VLV_GTLC_PW_STATUS));
1369
1370         /*
1371          * RC6 transitioning can be delayed up to 2 msec (see
1372          * valleyview_enable_rps), use 3 msec for safety.
1373          */
1374         err = wait_for(COND, 3);
1375         if (err)
1376                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1377                           onoff(wait_for_on));
1378
1379         return err;
1380 #undef COND
1381 }
1382
1383 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1384 {
1385         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1386                 return;
1387
1388         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1389         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1390 }
1391
1392 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1393 {
1394         u32 mask;
1395         int err;
1396
1397         /*
1398          * Bspec defines the following GT well on flags as debug only, so
1399          * don't treat them as hard failures.
1400          */
1401         (void)vlv_wait_for_gt_wells(dev_priv, false);
1402
1403         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1404         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1405
1406         vlv_check_no_gt_access(dev_priv);
1407
1408         err = vlv_force_gfx_clock(dev_priv, true);
1409         if (err)
1410                 goto err1;
1411
1412         err = vlv_allow_gt_wake(dev_priv, false);
1413         if (err)
1414                 goto err2;
1415
1416         if (!IS_CHERRYVIEW(dev_priv))
1417                 vlv_save_gunit_s0ix_state(dev_priv);
1418
1419         err = vlv_force_gfx_clock(dev_priv, false);
1420         if (err)
1421                 goto err2;
1422
1423         return 0;
1424
1425 err2:
1426         /* For safety always re-enable waking and disable gfx clock forcing */
1427         vlv_allow_gt_wake(dev_priv, true);
1428 err1:
1429         vlv_force_gfx_clock(dev_priv, false);
1430
1431         return err;
1432 }
1433
1434 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1435                                 bool rpm_resume)
1436 {
1437         struct drm_device *dev = dev_priv->dev;
1438         int err;
1439         int ret;
1440
1441         /*
1442          * If any of the steps fail just try to continue, that's the best we
1443          * can do at this point. Return the first error code (which will also
1444          * leave RPM permanently disabled).
1445          */
1446         ret = vlv_force_gfx_clock(dev_priv, true);
1447
1448         if (!IS_CHERRYVIEW(dev_priv))
1449                 vlv_restore_gunit_s0ix_state(dev_priv);
1450
1451         err = vlv_allow_gt_wake(dev_priv, true);
1452         if (!ret)
1453                 ret = err;
1454
1455         err = vlv_force_gfx_clock(dev_priv, false);
1456         if (!ret)
1457                 ret = err;
1458
1459         vlv_check_no_gt_access(dev_priv);
1460
1461         if (rpm_resume) {
1462                 intel_init_clock_gating(dev);
1463                 i915_gem_restore_fences(dev);
1464         }
1465
1466         return ret;
1467 }
1468
1469 static int intel_runtime_suspend(struct device *device)
1470 {
1471         struct pci_dev *pdev = to_pci_dev(device);
1472         struct drm_device *dev = pci_get_drvdata(pdev);
1473         struct drm_i915_private *dev_priv = dev->dev_private;
1474         int ret;
1475
1476         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1477                 return -ENODEV;
1478
1479         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1480                 return -ENODEV;
1481
1482         DRM_DEBUG_KMS("Suspending device\n");
1483
1484         /*
1485          * We could deadlock here in case another thread holding struct_mutex
1486          * calls RPM suspend concurrently, since the RPM suspend will wait
1487          * first for this RPM suspend to finish. In this case the concurrent
1488          * RPM resume will be followed by its RPM suspend counterpart. Still
1489          * for consistency return -EAGAIN, which will reschedule this suspend.
1490          */
1491         if (!mutex_trylock(&dev->struct_mutex)) {
1492                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1493                 /*
1494                  * Bump the expiration timestamp, otherwise the suspend won't
1495                  * be rescheduled.
1496                  */
1497                 pm_runtime_mark_last_busy(device);
1498
1499                 return -EAGAIN;
1500         }
1501
1502         disable_rpm_wakeref_asserts(dev_priv);
1503
1504         /*
1505          * We are safe here against re-faults, since the fault handler takes
1506          * an RPM reference.
1507          */
1508         i915_gem_release_all_mmaps(dev_priv);
1509         mutex_unlock(&dev->struct_mutex);
1510
1511         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1512
1513         intel_guc_suspend(dev);
1514
1515         intel_suspend_gt_powersave(dev);
1516         intel_runtime_pm_disable_interrupts(dev_priv);
1517
1518         ret = 0;
1519         if (IS_BROXTON(dev_priv)) {
1520                 bxt_display_core_uninit(dev_priv);
1521                 bxt_enable_dc9(dev_priv);
1522         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1523                 hsw_enable_pc8(dev_priv);
1524         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1525                 ret = vlv_suspend_complete(dev_priv);
1526         }
1527
1528         if (ret) {
1529                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1530                 intel_runtime_pm_enable_interrupts(dev_priv);
1531
1532                 enable_rpm_wakeref_asserts(dev_priv);
1533
1534                 return ret;
1535         }
1536
1537         intel_uncore_forcewake_reset(dev, false);
1538
1539         enable_rpm_wakeref_asserts(dev_priv);
1540         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1541
1542         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1543                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1544
1545         dev_priv->pm.suspended = true;
1546
1547         /*
1548          * FIXME: We really should find a document that references the arguments
1549          * used below!
1550          */
1551         if (IS_BROADWELL(dev)) {
1552                 /*
1553                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1554                  * being detected, and the call we do at intel_runtime_resume()
1555                  * won't be able to restore them. Since PCI_D3hot matches the
1556                  * actual specification and appears to be working, use it.
1557                  */
1558                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1559         } else {
1560                 /*
1561                  * current versions of firmware which depend on this opregion
1562                  * notification have repurposed the D1 definition to mean
1563                  * "runtime suspended" vs. what you would normally expect (D3)
1564                  * to distinguish it from notifications that might be sent via
1565                  * the suspend path.
1566                  */
1567                 intel_opregion_notify_adapter(dev, PCI_D1);
1568         }
1569
1570         assert_forcewakes_inactive(dev_priv);
1571
1572         DRM_DEBUG_KMS("Device suspended\n");
1573         return 0;
1574 }
1575
1576 static int intel_runtime_resume(struct device *device)
1577 {
1578         struct pci_dev *pdev = to_pci_dev(device);
1579         struct drm_device *dev = pci_get_drvdata(pdev);
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         int ret = 0;
1582
1583         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1584                 return -ENODEV;
1585
1586         DRM_DEBUG_KMS("Resuming device\n");
1587
1588         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1589         disable_rpm_wakeref_asserts(dev_priv);
1590
1591         intel_opregion_notify_adapter(dev, PCI_D0);
1592         dev_priv->pm.suspended = false;
1593         if (intel_uncore_unclaimed_mmio(dev_priv))
1594                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1595
1596         intel_guc_resume(dev);
1597
1598         if (IS_GEN6(dev_priv))
1599                 intel_init_pch_refclk(dev);
1600
1601         if (IS_BROXTON(dev)) {
1602                 bxt_disable_dc9(dev_priv);
1603                 bxt_display_core_init(dev_priv, true);
1604                 if (dev_priv->csr.dmc_payload &&
1605                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
1606                         gen9_enable_dc5(dev_priv);
1607         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1608                 hsw_disable_pc8(dev_priv);
1609         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1610                 ret = vlv_resume_prepare(dev_priv, true);
1611         }
1612
1613         /*
1614          * No point of rolling back things in case of an error, as the best
1615          * we can do is to hope that things will still work (and disable RPM).
1616          */
1617         i915_gem_init_swizzling(dev);
1618         gen6_update_ring_freq(dev);
1619
1620         intel_runtime_pm_enable_interrupts(dev_priv);
1621
1622         /*
1623          * On VLV/CHV display interrupts are part of the display
1624          * power well, so hpd is reinitialized from there. For
1625          * everyone else do it here.
1626          */
1627         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1628                 intel_hpd_init(dev_priv);
1629
1630         intel_enable_gt_powersave(dev);
1631
1632         enable_rpm_wakeref_asserts(dev_priv);
1633
1634         if (ret)
1635                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1636         else
1637                 DRM_DEBUG_KMS("Device resumed\n");
1638
1639         return ret;
1640 }
1641
1642 static const struct dev_pm_ops i915_pm_ops = {
1643         /*
1644          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1645          * PMSG_RESUME]
1646          */
1647         .suspend = i915_pm_suspend,
1648         .suspend_late = i915_pm_suspend_late,
1649         .resume_early = i915_pm_resume_early,
1650         .resume = i915_pm_resume,
1651
1652         /*
1653          * S4 event handlers
1654          * @freeze, @freeze_late    : called (1) before creating the
1655          *                            hibernation image [PMSG_FREEZE] and
1656          *                            (2) after rebooting, before restoring
1657          *                            the image [PMSG_QUIESCE]
1658          * @thaw, @thaw_early       : called (1) after creating the hibernation
1659          *                            image, before writing it [PMSG_THAW]
1660          *                            and (2) after failing to create or
1661          *                            restore the image [PMSG_RECOVER]
1662          * @poweroff, @poweroff_late: called after writing the hibernation
1663          *                            image, before rebooting [PMSG_HIBERNATE]
1664          * @restore, @restore_early : called after rebooting and restoring the
1665          *                            hibernation image [PMSG_RESTORE]
1666          */
1667         .freeze = i915_pm_suspend,
1668         .freeze_late = i915_pm_suspend_late,
1669         .thaw_early = i915_pm_resume_early,
1670         .thaw = i915_pm_resume,
1671         .poweroff = i915_pm_suspend,
1672         .poweroff_late = i915_pm_poweroff_late,
1673         .restore_early = i915_pm_resume_early,
1674         .restore = i915_pm_resume,
1675
1676         /* S0ix (via runtime suspend) event handlers */
1677         .runtime_suspend = intel_runtime_suspend,
1678         .runtime_resume = intel_runtime_resume,
1679 };
1680
1681 static const struct vm_operations_struct i915_gem_vm_ops = {
1682         .fault = i915_gem_fault,
1683         .open = drm_gem_vm_open,
1684         .close = drm_gem_vm_close,
1685 };
1686
1687 static const struct file_operations i915_driver_fops = {
1688         .owner = THIS_MODULE,
1689         .open = drm_open,
1690         .release = drm_release,
1691         .unlocked_ioctl = drm_ioctl,
1692         .mmap = drm_gem_mmap,
1693         .poll = drm_poll,
1694         .read = drm_read,
1695 #ifdef CONFIG_COMPAT
1696         .compat_ioctl = i915_compat_ioctl,
1697 #endif
1698         .llseek = noop_llseek,
1699 };
1700
1701 static struct drm_driver driver = {
1702         /* Don't use MTRRs here; the Xserver or userspace app should
1703          * deal with them for Intel hardware.
1704          */
1705         .driver_features =
1706             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1707             DRIVER_RENDER | DRIVER_MODESET,
1708         .load = i915_driver_load,
1709         .unload = i915_driver_unload,
1710         .open = i915_driver_open,
1711         .lastclose = i915_driver_lastclose,
1712         .preclose = i915_driver_preclose,
1713         .postclose = i915_driver_postclose,
1714         .set_busid = drm_pci_set_busid,
1715
1716 #if defined(CONFIG_DEBUG_FS)
1717         .debugfs_init = i915_debugfs_init,
1718         .debugfs_cleanup = i915_debugfs_cleanup,
1719 #endif
1720         .gem_free_object = i915_gem_free_object,
1721         .gem_vm_ops = &i915_gem_vm_ops,
1722
1723         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1724         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1725         .gem_prime_export = i915_gem_prime_export,
1726         .gem_prime_import = i915_gem_prime_import,
1727
1728         .dumb_create = i915_gem_dumb_create,
1729         .dumb_map_offset = i915_gem_mmap_gtt,
1730         .dumb_destroy = drm_gem_dumb_destroy,
1731         .ioctls = i915_ioctls,
1732         .fops = &i915_driver_fops,
1733         .name = DRIVER_NAME,
1734         .desc = DRIVER_DESC,
1735         .date = DRIVER_DATE,
1736         .major = DRIVER_MAJOR,
1737         .minor = DRIVER_MINOR,
1738         .patchlevel = DRIVER_PATCHLEVEL,
1739 };
1740
1741 static struct pci_driver i915_pci_driver = {
1742         .name = DRIVER_NAME,
1743         .id_table = pciidlist,
1744         .probe = i915_pci_probe,
1745         .remove = i915_pci_remove,
1746         .driver.pm = &i915_pm_ops,
1747 };
1748
1749 static int __init i915_init(void)
1750 {
1751         driver.num_ioctls = i915_max_ioctl;
1752
1753         /*
1754          * Enable KMS by default, unless explicitly overriden by
1755          * either the i915.modeset prarameter or by the
1756          * vga_text_mode_force boot option.
1757          */
1758
1759         if (i915.modeset == 0)
1760                 driver.driver_features &= ~DRIVER_MODESET;
1761
1762         if (vgacon_text_force() && i915.modeset == -1)
1763                 driver.driver_features &= ~DRIVER_MODESET;
1764
1765         if (!(driver.driver_features & DRIVER_MODESET)) {
1766                 /* Silently fail loading to not upset userspace. */
1767                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1768                 return 0;
1769         }
1770
1771         if (i915.nuclear_pageflip)
1772                 driver.driver_features |= DRIVER_ATOMIC;
1773
1774         return drm_pci_init(&driver, &i915_pci_driver);
1775 }
1776
1777 static void __exit i915_exit(void)
1778 {
1779         if (!(driver.driver_features & DRIVER_MODESET))
1780                 return; /* Never loaded a driver. */
1781
1782         drm_pci_exit(&driver, &i915_pci_driver);
1783 }
1784
1785 module_init(i915_init);
1786 module_exit(i915_exit);
1787
1788 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1789 MODULE_AUTHOR("Intel Corporation");
1790
1791 MODULE_DESCRIPTION(DRIVER_DESC);
1792 MODULE_LICENSE("GPL and additional rights");