drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void gen9_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77 }
  78
  79 static void bxt_init_clock_gating(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82
  83         gen9_init_clock_gating(dev);
  84
  85         /* WaDisableSDEUnitClockGating:bxt */
  86         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  87                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  88
  89         /*
  90          * FIXME:
  91          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  92          */
  93         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  94                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  95
  96         /*
  97          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  98          * to stay fully on.
  99          */
 100         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 101                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 102                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 103 }
 104
 105 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 106 {
 107         struct drm_i915_private *dev_priv = dev->dev_private;
 108         u32 tmp;
 109
 110         tmp = I915_READ(CLKCFG);
 111
 112         switch (tmp & CLKCFG_FSB_MASK) {
 113         case CLKCFG_FSB_533:
 114                 dev_priv->fsb_freq = 533; /* 133*4 */
 115                 break;
 116         case CLKCFG_FSB_800:
 117                 dev_priv->fsb_freq = 800; /* 200*4 */
 118                 break;
 119         case CLKCFG_FSB_667:
 120                 dev_priv->fsb_freq =  667; /* 167*4 */
 121                 break;
 122         case CLKCFG_FSB_400:
 123                 dev_priv->fsb_freq = 400; /* 100*4 */
 124                 break;
 125         }
 126
 127         switch (tmp & CLKCFG_MEM_MASK) {
 128         case CLKCFG_MEM_533:
 129                 dev_priv->mem_freq = 533;
 130                 break;
 131         case CLKCFG_MEM_667:
 132                 dev_priv->mem_freq = 667;
 133                 break;
 134         case CLKCFG_MEM_800:
 135                 dev_priv->mem_freq = 800;
 136                 break;
 137         }
 138
 139         /* detect pineview DDR3 setting */
 140         tmp = I915_READ(CSHRDDR3CTL);
 141         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 142 }
 143
 144 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         u16 ddrpll, csipll;
 148
 149         ddrpll = I915_READ16(DDRMPLL1);
 150         csipll = I915_READ16(CSIPLL0);
 151
 152         switch (ddrpll & 0xff) {
 153         case 0xc:
 154                 dev_priv->mem_freq = 800;
 155                 break;
 156         case 0x10:
 157                 dev_priv->mem_freq = 1066;
 158                 break;
 159         case 0x14:
 160                 dev_priv->mem_freq = 1333;
 161                 break;
 162         case 0x18:
 163                 dev_priv->mem_freq = 1600;
 164                 break;
 165         default:
 166                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 167                                  ddrpll & 0xff);
 168                 dev_priv->mem_freq = 0;
 169                 break;
 170         }
 171
 172         dev_priv->ips.r_t = dev_priv->mem_freq;
 173
 174         switch (csipll & 0x3ff) {
 175         case 0x00c:
 176                 dev_priv->fsb_freq = 3200;
 177                 break;
 178         case 0x00e:
 179                 dev_priv->fsb_freq = 3733;
 180                 break;
 181         case 0x010:
 182                 dev_priv->fsb_freq = 4266;
 183                 break;
 184         case 0x012:
 185                 dev_priv->fsb_freq = 4800;
 186                 break;
 187         case 0x014:
 188                 dev_priv->fsb_freq = 5333;
 189                 break;
 190         case 0x016:
 191                 dev_priv->fsb_freq = 5866;
 192                 break;
 193         case 0x018:
 194                 dev_priv->fsb_freq = 6400;
 195                 break;
 196         default:
 197                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 198                                  csipll & 0x3ff);
 199                 dev_priv->fsb_freq = 0;
 200                 break;
 201         }
 202
 203         if (dev_priv->fsb_freq == 3200) {
 204                 dev_priv->ips.c_m = 0;
 205         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 206                 dev_priv->ips.c_m = 1;
 207         } else {
 208                 dev_priv->ips.c_m = 2;
 209         }
 210 }
 211
 212 static const struct cxsr_latency cxsr_latency_table[] = {
 213         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 214         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 215         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 216         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 217         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 218
 219         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 220         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 221         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 222         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 223         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 224
 225         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 226         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 227         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 228         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 229         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 230
 231         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 232         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 233         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 234         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 235         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 236
 237         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 238         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 239         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 240         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 241         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 242
 243         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 244         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 245         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 246         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 247         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 248 };
 249
 250 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 251                                                          int is_ddr3,
 252                                                          int fsb,
 253                                                          int mem)
 254 {
 255         const struct cxsr_latency *latency;
 256         int i;
 257
 258         if (fsb == 0 || mem == 0)
 259                 return NULL;
 260
 261         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 262                 latency = &cxsr_latency_table[i];
 263                 if (is_desktop == latency->is_desktop &&
 264                     is_ddr3 == latency->is_ddr3 &&
 265                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 266                         return latency;
 267         }
 268
 269         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 270
 271         return NULL;
 272 }
 273
 274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 275 {
 276         u32 val;
 277
 278         mutex_lock(&dev_priv->rps.hw_lock);
 279
 280         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 281         if (enable)
 282                 val &= ~FORCE_DDR_HIGH_FREQ;
 283         else
 284                 val |= FORCE_DDR_HIGH_FREQ;
 285         val &= ~FORCE_DDR_LOW_FREQ;
 286         val |= FORCE_DDR_FREQ_REQ_ACK;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 288
 289         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 290                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 291                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 292
 293         mutex_unlock(&dev_priv->rps.hw_lock);
 294 }
 295
 296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 303         if (enable)
 304                 val |= DSP_MAXFIFO_PM5_ENABLE;
 305         else
 306                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 307         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 308
 309         mutex_unlock(&dev_priv->rps.hw_lock);
 310 }
 311
 312 #define FW_WM(value, plane) \
 313         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 314
 315 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         struct drm_device *dev = dev_priv->dev;
 318         u32 val;
 319
 320         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 321                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 322                 POSTING_READ(FW_BLC_SELF_VLV);
 323                 dev_priv->wm.vlv.cxsr = enable;
 324         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 325                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 326                 POSTING_READ(FW_BLC_SELF);
 327         } else if (IS_PINEVIEW(dev)) {
 328                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 329                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 330                 I915_WRITE(DSPFW3, val);
 331                 POSTING_READ(DSPFW3);
 332         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 333                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 334                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 335                 I915_WRITE(FW_BLC_SELF, val);
 336                 POSTING_READ(FW_BLC_SELF);
 337         } else if (IS_I915GM(dev)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 340                 I915_WRITE(INSTPM, val);
 341                 POSTING_READ(INSTPM);
 342         } else {
 343                 return;
 344         }
 345
 346         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 347                       enable ? "enabled" : "disabled");
 348 }
 349
 350
 351 /*
 352  * Latency for FIFO fetches is dependent on several factors:
 353  *   - memory configuration (speed, channels)
 354  *   - chipset
 355  *   - current MCH state
 356  * It can be fairly high in some situations, so here we assume a fairly
 357  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 358  * set this value too high, the FIFO will fetch frequently to stay full)
 359  * and power consumption (set it too low to save power and we might see
 360  * FIFO underruns and display "flicker").
 361  *
 362  * A value of 5us seems to be a good balance; safe for very low end
 363  * platforms but not overly aggressive on lower latency configs.
 364  */
 365 static const int pessimal_latency_ns = 5000;
 366
 367 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 368         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 369
 370 static int vlv_get_fifo_size(struct drm_device *dev,
 371                               enum pipe pipe, int plane)
 372 {
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         int sprite0_start, sprite1_start, size;
 375
 376         switch (pipe) {
 377                 uint32_t dsparb, dsparb2, dsparb3;
 378         case PIPE_A:
 379                 dsparb = I915_READ(DSPARB);
 380                 dsparb2 = I915_READ(DSPARB2);
 381                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 382                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 383                 break;
 384         case PIPE_B:
 385                 dsparb = I915_READ(DSPARB);
 386                 dsparb2 = I915_READ(DSPARB2);
 387                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 388                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 389                 break;
 390         case PIPE_C:
 391                 dsparb2 = I915_READ(DSPARB2);
 392                 dsparb3 = I915_READ(DSPARB3);
 393                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 394                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 395                 break;
 396         default:
 397                 return 0;
 398         }
 399
 400         switch (plane) {
 401         case 0:
 402                 size = sprite0_start;
 403                 break;
 404         case 1:
 405                 size = sprite1_start - sprite0_start;
 406                 break;
 407         case 2:
 408                 size = 512 - 1 - sprite1_start;
 409                 break;
 410         default:
 411                 return 0;
 412         }
 413
 414         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 415                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 416                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 417                       size);
 418
 419         return size;
 420 }
 421
 422 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 423 {
 424         struct drm_i915_private *dev_priv = dev->dev_private;
 425         uint32_t dsparb = I915_READ(DSPARB);
 426         int size;
 427
 428         size = dsparb & 0x7f;
 429         if (plane)
 430                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 431
 432         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 433                       plane ? "B" : "A", size);
 434
 435         return size;
 436 }
 437
 438 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 439 {
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         uint32_t dsparb = I915_READ(DSPARB);
 442         int size;
 443
 444         size = dsparb & 0x1ff;
 445         if (plane)
 446                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 447         size >>= 1; /* Convert to cachelines */
 448
 449         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 450                       plane ? "B" : "A", size);
 451
 452         return size;
 453 }
 454
 455 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 456 {
 457         struct drm_i915_private *dev_priv = dev->dev_private;
 458         uint32_t dsparb = I915_READ(DSPARB);
 459         int size;
 460
 461         size = dsparb & 0x7f;
 462         size >>= 2; /* Convert to cachelines */
 463
 464         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 465                       plane ? "B" : "A",
 466                       size);
 467
 468         return size;
 469 }
 470
 471 /* Pineview has different values for various configs */
 472 static const struct intel_watermark_params pineview_display_wm = {
 473         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 474         .max_wm = PINEVIEW_MAX_WM,
 475         .default_wm = PINEVIEW_DFT_WM,
 476         .guard_size = PINEVIEW_GUARD_WM,
 477         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 478 };
 479 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 480         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 481         .max_wm = PINEVIEW_MAX_WM,
 482         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 483         .guard_size = PINEVIEW_GUARD_WM,
 484         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 485 };
 486 static const struct intel_watermark_params pineview_cursor_wm = {
 487         .fifo_size = PINEVIEW_CURSOR_FIFO,
 488         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 489         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 490         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 491         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 492 };
 493 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 494         .fifo_size = PINEVIEW_CURSOR_FIFO,
 495         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 496         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 497         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 498         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 499 };
 500 static const struct intel_watermark_params g4x_wm_info = {
 501         .fifo_size = G4X_FIFO_SIZE,
 502         .max_wm = G4X_MAX_WM,
 503         .default_wm = G4X_MAX_WM,
 504         .guard_size = 2,
 505         .cacheline_size = G4X_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params g4x_cursor_wm_info = {
 508         .fifo_size = I965_CURSOR_FIFO,
 509         .max_wm = I965_CURSOR_MAX_WM,
 510         .default_wm = I965_CURSOR_DFT_WM,
 511         .guard_size = 2,
 512         .cacheline_size = G4X_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params i965_cursor_wm_info = {
 515         .fifo_size = I965_CURSOR_FIFO,
 516         .max_wm = I965_CURSOR_MAX_WM,
 517         .default_wm = I965_CURSOR_DFT_WM,
 518         .guard_size = 2,
 519         .cacheline_size = I915_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params i945_wm_info = {
 522         .fifo_size = I945_FIFO_SIZE,
 523         .max_wm = I915_MAX_WM,
 524         .default_wm = 1,
 525         .guard_size = 2,
 526         .cacheline_size = I915_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params i915_wm_info = {
 529         .fifo_size = I915_FIFO_SIZE,
 530         .max_wm = I915_MAX_WM,
 531         .default_wm = 1,
 532         .guard_size = 2,
 533         .cacheline_size = I915_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params i830_a_wm_info = {
 536         .fifo_size = I855GM_FIFO_SIZE,
 537         .max_wm = I915_MAX_WM,
 538         .default_wm = 1,
 539         .guard_size = 2,
 540         .cacheline_size = I830_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params i830_bc_wm_info = {
 543         .fifo_size = I855GM_FIFO_SIZE,
 544         .max_wm = I915_MAX_WM/2,
 545         .default_wm = 1,
 546         .guard_size = 2,
 547         .cacheline_size = I830_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params i845_wm_info = {
 550         .fifo_size = I830_FIFO_SIZE,
 551         .max_wm = I915_MAX_WM,
 552         .default_wm = 1,
 553         .guard_size = 2,
 554         .cacheline_size = I830_FIFO_LINE_SIZE,
 555 };
 556
 557 /**
 558  * intel_calculate_wm - calculate watermark level
 559  * @clock_in_khz: pixel clock
 560  * @wm: chip FIFO params
 561  * @cpp: bytes per pixel
 562  * @latency_ns: memory latency for the platform
 563  *
 564  * Calculate the watermark level (the level at which the display plane will
 565  * start fetching from memory again).  Each chip has a different display
 566  * FIFO size and allocation, so the caller needs to figure that out and pass
 567  * in the correct intel_watermark_params structure.
 568  *
 569  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 570  * on the pixel size.  When it reaches the watermark level, it'll start
 571  * fetching FIFO line sized based chunks from memory until the FIFO fills
 572  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 573  * will occur, and a display engine hang could result.
 574  */
 575 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 576                                         const struct intel_watermark_params *wm,
 577                                         int fifo_size, int cpp,
 578                                         unsigned long latency_ns)
 579 {
 580         long entries_required, wm_size;
 581
 582         /*
 583          * Note: we need to make sure we don't overflow for various clock &
 584          * latency values.
 585          * clocks go from a few thousand to several hundred thousand.
 586          * latency is usually a few thousand
 587          */
 588         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 589                 1000;
 590         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 591
 592         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 593
 594         wm_size = fifo_size - (entries_required + wm->guard_size);
 595
 596         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 597
 598         /* Don't promote wm_size to unsigned... */
 599         if (wm_size > (long)wm->max_wm)
 600                 wm_size = wm->max_wm;
 601         if (wm_size <= 0)
 602                 wm_size = wm->default_wm;
 603
 604         /*
 605          * Bspec seems to indicate that the value shouldn't be lower than
 606          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 607          * Lets go for 8 which is the burst size since certain platforms
 608          * already use a hardcoded 8 (which is what the spec says should be
 609          * done).
 610          */
 611         if (wm_size <= 8)
 612                 wm_size = 8;
 613
 614         return wm_size;
 615 }
 616
 617 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 618 {
 619         struct drm_crtc *crtc, *enabled = NULL;
 620
 621         for_each_crtc(dev, crtc) {
 622                 if (intel_crtc_active(crtc)) {
 623                         if (enabled)
 624                                 return NULL;
 625                         enabled = crtc;
 626                 }
 627         }
 628
 629         return enabled;
 630 }
 631
 632 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 633 {
 634         struct drm_device *dev = unused_crtc->dev;
 635         struct drm_i915_private *dev_priv = dev->dev_private;
 636         struct drm_crtc *crtc;
 637         const struct cxsr_latency *latency;
 638         u32 reg;
 639         unsigned long wm;
 640
 641         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 642                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 643         if (!latency) {
 644                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 645                 intel_set_memory_cxsr(dev_priv, false);
 646                 return;
 647         }
 648
 649         crtc = single_enabled_crtc(dev);
 650         if (crtc) {
 651                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 652                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 653                 int clock = adjusted_mode->crtc_clock;
 654
 655                 /* Display SR */
 656                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 657                                         pineview_display_wm.fifo_size,
 658                                         cpp, latency->display_sr);
 659                 reg = I915_READ(DSPFW1);
 660                 reg &= ~DSPFW_SR_MASK;
 661                 reg |= FW_WM(wm, SR);
 662                 I915_WRITE(DSPFW1, reg);
 663                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 664
 665                 /* cursor SR */
 666                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 667                                         pineview_display_wm.fifo_size,
 668                                         cpp, latency->cursor_sr);
 669                 reg = I915_READ(DSPFW3);
 670                 reg &= ~DSPFW_CURSOR_SR_MASK;
 671                 reg |= FW_WM(wm, CURSOR_SR);
 672                 I915_WRITE(DSPFW3, reg);
 673
 674                 /* Display HPLL off SR */
 675                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 676                                         pineview_display_hplloff_wm.fifo_size,
 677                                         cpp, latency->display_hpll_disable);
 678                 reg = I915_READ(DSPFW3);
 679                 reg &= ~DSPFW_HPLL_SR_MASK;
 680                 reg |= FW_WM(wm, HPLL_SR);
 681                 I915_WRITE(DSPFW3, reg);
 682
 683                 /* cursor HPLL off SR */
 684                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 685                                         pineview_display_hplloff_wm.fifo_size,
 686                                         cpp, latency->cursor_hpll_disable);
 687                 reg = I915_READ(DSPFW3);
 688                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 689                 reg |= FW_WM(wm, HPLL_CURSOR);
 690                 I915_WRITE(DSPFW3, reg);
 691                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 692
 693                 intel_set_memory_cxsr(dev_priv, true);
 694         } else {
 695                 intel_set_memory_cxsr(dev_priv, false);
 696         }
 697 }
 698
 699 static bool g4x_compute_wm0(struct drm_device *dev,
 700                             int plane,
 701                             const struct intel_watermark_params *display,
 702                             int display_latency_ns,
 703                             const struct intel_watermark_params *cursor,
 704                             int cursor_latency_ns,
 705                             int *plane_wm,
 706                             int *cursor_wm)
 707 {
 708         struct drm_crtc *crtc;
 709         const struct drm_display_mode *adjusted_mode;
 710         int htotal, hdisplay, clock, cpp;
 711         int line_time_us, line_count;
 712         int entries, tlb_miss;
 713
 714         crtc = intel_get_crtc_for_plane(dev, plane);
 715         if (!intel_crtc_active(crtc)) {
 716                 *cursor_wm = cursor->guard_size;
 717                 *plane_wm = display->guard_size;
 718                 return false;
 719         }
 720
 721         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 722         clock = adjusted_mode->crtc_clock;
 723         htotal = adjusted_mode->crtc_htotal;
 724         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 725         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 726
 727         /* Use the small buffer method to calculate plane watermark */
 728         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 729         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 730         if (tlb_miss > 0)
 731                 entries += tlb_miss;
 732         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 733         *plane_wm = entries + display->guard_size;
 734         if (*plane_wm > (int)display->max_wm)
 735                 *plane_wm = display->max_wm;
 736
 737         /* Use the large buffer method to calculate cursor watermark */
 738         line_time_us = max(htotal * 1000 / clock, 1);
 739         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 740         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 741         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 742         if (tlb_miss > 0)
 743                 entries += tlb_miss;
 744         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 745         *cursor_wm = entries + cursor->guard_size;
 746         if (*cursor_wm > (int)cursor->max_wm)
 747                 *cursor_wm = (int)cursor->max_wm;
 748
 749         return true;
 750 }
 751
 752 /*
 753  * Check the wm result.
 754  *
 755  * If any calculated watermark values is larger than the maximum value that
 756  * can be programmed into the associated watermark register, that watermark
 757  * must be disabled.
 758  */
 759 static bool g4x_check_srwm(struct drm_device *dev,
 760                            int display_wm, int cursor_wm,
 761                            const struct intel_watermark_params *display,
 762                            const struct intel_watermark_params *cursor)
 763 {
 764         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 765                       display_wm, cursor_wm);
 766
 767         if (display_wm > display->max_wm) {
 768                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 769                               display_wm, display->max_wm);
 770                 return false;
 771         }
 772
 773         if (cursor_wm > cursor->max_wm) {
 774                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 775                               cursor_wm, cursor->max_wm);
 776                 return false;
 777         }
 778
 779         if (!(display_wm || cursor_wm)) {
 780                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 781                 return false;
 782         }
 783
 784         return true;
 785 }
 786
 787 static bool g4x_compute_srwm(struct drm_device *dev,
 788                              int plane,
 789                              int latency_ns,
 790                              const struct intel_watermark_params *display,
 791                              const struct intel_watermark_params *cursor,
 792                              int *display_wm, int *cursor_wm)
 793 {
 794         struct drm_crtc *crtc;
 795         const struct drm_display_mode *adjusted_mode;
 796         int hdisplay, htotal, cpp, clock;
 797         unsigned long line_time_us;
 798         int line_count, line_size;
 799         int small, large;
 800         int entries;
 801
 802         if (!latency_ns) {
 803                 *display_wm = *cursor_wm = 0;
 804                 return false;
 805         }
 806
 807         crtc = intel_get_crtc_for_plane(dev, plane);
 808         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 809         clock = adjusted_mode->crtc_clock;
 810         htotal = adjusted_mode->crtc_htotal;
 811         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 812         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 813
 814         line_time_us = max(htotal * 1000 / clock, 1);
 815         line_count = (latency_ns / line_time_us + 1000) / 1000;
 816         line_size = hdisplay * cpp;
 817
 818         /* Use the minimum of the small and large buffer method for primary */
 819         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 820         large = line_count * line_size;
 821
 822         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 823         *display_wm = entries + display->guard_size;
 824
 825         /* calculate the self-refresh watermark for display cursor */
 826         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 827         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 828         *cursor_wm = entries + cursor->guard_size;
 829
 830         return g4x_check_srwm(dev,
 831                               *display_wm, *cursor_wm,
 832                               display, cursor);
 833 }
 834
 835 #define FW_WM_VLV(value, plane) \
 836         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 837
 838 static void vlv_write_wm_values(struct intel_crtc *crtc,
 839                                 const struct vlv_wm_values *wm)
 840 {
 841         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 842         enum pipe pipe = crtc->pipe;
 843
 844         I915_WRITE(VLV_DDL(pipe),
 845                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 846                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 847                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 848                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 849
 850         I915_WRITE(DSPFW1,
 851                    FW_WM(wm->sr.plane, SR) |
 852                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 853                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 854                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 855         I915_WRITE(DSPFW2,
 856                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 857                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 858                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 859         I915_WRITE(DSPFW3,
 860                    FW_WM(wm->sr.cursor, CURSOR_SR));
 861
 862         if (IS_CHERRYVIEW(dev_priv)) {
 863                 I915_WRITE(DSPFW7_CHV,
 864                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 865                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 866                 I915_WRITE(DSPFW8_CHV,
 867                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 868                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 869                 I915_WRITE(DSPFW9_CHV,
 870                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 871                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 872                 I915_WRITE(DSPHOWM,
 873                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 874                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 875                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 876                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 877                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 878                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 879                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 880                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 881                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 882                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 883         } else {
 884                 I915_WRITE(DSPFW7,
 885                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 886                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 887                 I915_WRITE(DSPHOWM,
 888                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 889                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 890                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 891                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 892                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 893                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 894                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 895         }
 896
 897         /* zero (unused) WM1 watermarks */
 898         I915_WRITE(DSPFW4, 0);
 899         I915_WRITE(DSPFW5, 0);
 900         I915_WRITE(DSPFW6, 0);
 901         I915_WRITE(DSPHOWM1, 0);
 902
 903         POSTING_READ(DSPFW1);
 904 }
 905
 906 #undef FW_WM_VLV
 907
 908 enum vlv_wm_level {
 909         VLV_WM_LEVEL_PM2,
 910         VLV_WM_LEVEL_PM5,
 911         VLV_WM_LEVEL_DDR_DVFS,
 912 };
 913
 914 /* latency must be in 0.1us units. */
 915 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 916                                    unsigned int pipe_htotal,
 917                                    unsigned int horiz_pixels,
 918                                    unsigned int cpp,
 919                                    unsigned int latency)
 920 {
 921         unsigned int ret;
 922
 923         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 924         ret = (ret + 1) * horiz_pixels * cpp;
 925         ret = DIV_ROUND_UP(ret, 64);
 926
 927         return ret;
 928 }
 929
 930 static void vlv_setup_wm_latency(struct drm_device *dev)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933
 934         /* all latencies in usec */
 935         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 936
 937         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 938
 939         if (IS_CHERRYVIEW(dev_priv)) {
 940                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 941                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 942
 943                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 944         }
 945 }
 946
 947 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 948                                      struct intel_crtc *crtc,
 949                                      const struct intel_plane_state *state,
 950                                      int level)
 951 {
 952         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 953         int clock, htotal, cpp, width, wm;
 954
 955         if (dev_priv->wm.pri_latency[level] == 0)
 956                 return USHRT_MAX;
 957
 958         if (!state->visible)
 959                 return 0;
 960
 961         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 962         clock = crtc->config->base.adjusted_mode.crtc_clock;
 963         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 964         width = crtc->config->pipe_src_w;
 965         if (WARN_ON(htotal == 0))
 966                 htotal = 1;
 967
 968         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 969                 /*
 970                  * FIXME the formula gives values that are
 971                  * too big for the cursor FIFO, and hence we
 972                  * would never be able to use cursors. For
 973                  * now just hardcode the watermark.
 974                  */
 975                 wm = 63;
 976         } else {
 977                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 978                                     dev_priv->wm.pri_latency[level] * 10);
 979         }
 980
 981         return min_t(int, wm, USHRT_MAX);
 982 }
 983
 984 static void vlv_compute_fifo(struct intel_crtc *crtc)
 985 {
 986         struct drm_device *dev = crtc->base.dev;
 987         struct vlv_wm_state *wm_state = &crtc->wm_state;
 988         struct intel_plane *plane;
 989         unsigned int total_rate = 0;
 990         const int fifo_size = 512 - 1;
 991         int fifo_extra, fifo_left = fifo_size;
 992
 993         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 994                 struct intel_plane_state *state =
 995                         to_intel_plane_state(plane->base.state);
 996
 997                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 998                         continue;
 999
1000                 if (state->visible) {
1001                         wm_state->num_active_planes++;
1002                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003                 }
1004         }
1005
1006         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1007                 struct intel_plane_state *state =
1008                         to_intel_plane_state(plane->base.state);
1009                 unsigned int rate;
1010
1011                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1012                         plane->wm.fifo_size = 63;
1013                         continue;
1014                 }
1015
1016                 if (!state->visible) {
1017                         plane->wm.fifo_size = 0;
1018                         continue;
1019                 }
1020
1021                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1022                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1023                 fifo_left -= plane->wm.fifo_size;
1024         }
1025
1026         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1027
1028         /* spread the remainder evenly */
1029         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1030                 int plane_extra;
1031
1032                 if (fifo_left == 0)
1033                         break;
1034
1035                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036                         continue;
1037
1038                 /* give it all to the first plane if none are active */
1039                 if (plane->wm.fifo_size == 0 &&
1040                     wm_state->num_active_planes)
1041                         continue;
1042
1043                 plane_extra = min(fifo_extra, fifo_left);
1044                 plane->wm.fifo_size += plane_extra;
1045                 fifo_left -= plane_extra;
1046         }
1047
1048         WARN_ON(fifo_left != 0);
1049 }
1050
1051 static void vlv_invert_wms(struct intel_crtc *crtc)
1052 {
1053         struct vlv_wm_state *wm_state = &crtc->wm_state;
1054         int level;
1055
1056         for (level = 0; level < wm_state->num_levels; level++) {
1057                 struct drm_device *dev = crtc->base.dev;
1058                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1059                 struct intel_plane *plane;
1060
1061                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1062                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1063
1064                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1065                         switch (plane->base.type) {
1066                                 int sprite;
1067                         case DRM_PLANE_TYPE_CURSOR:
1068                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1069                                         wm_state->wm[level].cursor;
1070                                 break;
1071                         case DRM_PLANE_TYPE_PRIMARY:
1072                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1073                                         wm_state->wm[level].primary;
1074                                 break;
1075                         case DRM_PLANE_TYPE_OVERLAY:
1076                                 sprite = plane->plane;
1077                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1078                                         wm_state->wm[level].sprite[sprite];
1079                                 break;
1080                         }
1081                 }
1082         }
1083 }
1084
1085 static void vlv_compute_wm(struct intel_crtc *crtc)
1086 {
1087         struct drm_device *dev = crtc->base.dev;
1088         struct vlv_wm_state *wm_state = &crtc->wm_state;
1089         struct intel_plane *plane;
1090         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1091         int level;
1092
1093         memset(wm_state, 0, sizeof(*wm_state));
1094
1095         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1096         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1097
1098         wm_state->num_active_planes = 0;
1099
1100         vlv_compute_fifo(crtc);
1101
1102         if (wm_state->num_active_planes != 1)
1103                 wm_state->cxsr = false;
1104
1105         if (wm_state->cxsr) {
1106                 for (level = 0; level < wm_state->num_levels; level++) {
1107                         wm_state->sr[level].plane = sr_fifo_size;
1108                         wm_state->sr[level].cursor = 63;
1109                 }
1110         }
1111
1112         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1113                 struct intel_plane_state *state =
1114                         to_intel_plane_state(plane->base.state);
1115
1116                 if (!state->visible)
1117                         continue;
1118
1119                 /* normal watermarks */
1120                 for (level = 0; level < wm_state->num_levels; level++) {
1121                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1122                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1123
1124                         /* hack */
1125                         if (WARN_ON(level == 0 && wm > max_wm))
1126                                 wm = max_wm;
1127
1128                         if (wm > plane->wm.fifo_size)
1129                                 break;
1130
1131                         switch (plane->base.type) {
1132                                 int sprite;
1133                         case DRM_PLANE_TYPE_CURSOR:
1134                                 wm_state->wm[level].cursor = wm;
1135                                 break;
1136                         case DRM_PLANE_TYPE_PRIMARY:
1137                                 wm_state->wm[level].primary = wm;
1138                                 break;
1139                         case DRM_PLANE_TYPE_OVERLAY:
1140                                 sprite = plane->plane;
1141                                 wm_state->wm[level].sprite[sprite] = wm;
1142                                 break;
1143                         }
1144                 }
1145
1146                 wm_state->num_levels = level;
1147
1148                 if (!wm_state->cxsr)
1149                         continue;
1150
1151                 /* maxfifo watermarks */
1152                 switch (plane->base.type) {
1153                         int sprite, level;
1154                 case DRM_PLANE_TYPE_CURSOR:
1155                         for (level = 0; level < wm_state->num_levels; level++)
1156                                 wm_state->sr[level].cursor =
1157                                         wm_state->wm[level].cursor;
1158                         break;
1159                 case DRM_PLANE_TYPE_PRIMARY:
1160                         for (level = 0; level < wm_state->num_levels; level++)
1161                                 wm_state->sr[level].plane =
1162                                         min(wm_state->sr[level].plane,
1163                                             wm_state->wm[level].primary);
1164                         break;
1165                 case DRM_PLANE_TYPE_OVERLAY:
1166                         sprite = plane->plane;
1167                         for (level = 0; level < wm_state->num_levels; level++)
1168                                 wm_state->sr[level].plane =
1169                                         min(wm_state->sr[level].plane,
1170                                             wm_state->wm[level].sprite[sprite]);
1171                         break;
1172                 }
1173         }
1174
1175         /* clear any (partially) filled invalid levels */
1176         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1177                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1178                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1179         }
1180
1181         vlv_invert_wms(crtc);
1182 }
1183
1184 #define VLV_FIFO(plane, value) \
1185         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1186
1187 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1188 {
1189         struct drm_device *dev = crtc->base.dev;
1190         struct drm_i915_private *dev_priv = to_i915(dev);
1191         struct intel_plane *plane;
1192         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1193
1194         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1195                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1196                         WARN_ON(plane->wm.fifo_size != 63);
1197                         continue;
1198                 }
1199
1200                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1201                         sprite0_start = plane->wm.fifo_size;
1202                 else if (plane->plane == 0)
1203                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1204                 else
1205                         fifo_size = sprite1_start + plane->wm.fifo_size;
1206         }
1207
1208         WARN_ON(fifo_size != 512 - 1);
1209
1210         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1211                       pipe_name(crtc->pipe), sprite0_start,
1212                       sprite1_start, fifo_size);
1213
1214         switch (crtc->pipe) {
1215                 uint32_t dsparb, dsparb2, dsparb3;
1216         case PIPE_A:
1217                 dsparb = I915_READ(DSPARB);
1218                 dsparb2 = I915_READ(DSPARB2);
1219
1220                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1221                             VLV_FIFO(SPRITEB, 0xff));
1222                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1223                            VLV_FIFO(SPRITEB, sprite1_start));
1224
1225                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1226                              VLV_FIFO(SPRITEB_HI, 0x1));
1227                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1228                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1229
1230                 I915_WRITE(DSPARB, dsparb);
1231                 I915_WRITE(DSPARB2, dsparb2);
1232                 break;
1233         case PIPE_B:
1234                 dsparb = I915_READ(DSPARB);
1235                 dsparb2 = I915_READ(DSPARB2);
1236
1237                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1238                             VLV_FIFO(SPRITED, 0xff));
1239                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1240                            VLV_FIFO(SPRITED, sprite1_start));
1241
1242                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1243                              VLV_FIFO(SPRITED_HI, 0xff));
1244                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1245                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1246
1247                 I915_WRITE(DSPARB, dsparb);
1248                 I915_WRITE(DSPARB2, dsparb2);
1249                 break;
1250         case PIPE_C:
1251                 dsparb3 = I915_READ(DSPARB3);
1252                 dsparb2 = I915_READ(DSPARB2);
1253
1254                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1255                              VLV_FIFO(SPRITEF, 0xff));
1256                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1257                             VLV_FIFO(SPRITEF, sprite1_start));
1258
1259                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1260                              VLV_FIFO(SPRITEF_HI, 0xff));
1261                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1262                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1263
1264                 I915_WRITE(DSPARB3, dsparb3);
1265                 I915_WRITE(DSPARB2, dsparb2);
1266                 break;
1267         default:
1268                 break;
1269         }
1270 }
1271
1272 #undef VLV_FIFO
1273
1274 static void vlv_merge_wm(struct drm_device *dev,
1275                          struct vlv_wm_values *wm)
1276 {
1277         struct intel_crtc *crtc;
1278         int num_active_crtcs = 0;
1279
1280         wm->level = to_i915(dev)->wm.max_level;
1281         wm->cxsr = true;
1282
1283         for_each_intel_crtc(dev, crtc) {
1284                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1285
1286                 if (!crtc->active)
1287                         continue;
1288
1289                 if (!wm_state->cxsr)
1290                         wm->cxsr = false;
1291
1292                 num_active_crtcs++;
1293                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1294         }
1295
1296         if (num_active_crtcs != 1)
1297                 wm->cxsr = false;
1298
1299         if (num_active_crtcs > 1)
1300                 wm->level = VLV_WM_LEVEL_PM2;
1301
1302         for_each_intel_crtc(dev, crtc) {
1303                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1304                 enum pipe pipe = crtc->pipe;
1305
1306                 if (!crtc->active)
1307                         continue;
1308
1309                 wm->pipe[pipe] = wm_state->wm[wm->level];
1310                 if (wm->cxsr)
1311                         wm->sr = wm_state->sr[wm->level];
1312
1313                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1314                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1315                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1316                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1317         }
1318 }
1319
1320 static void vlv_update_wm(struct drm_crtc *crtc)
1321 {
1322         struct drm_device *dev = crtc->dev;
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1325         enum pipe pipe = intel_crtc->pipe;
1326         struct vlv_wm_values wm = {};
1327
1328         vlv_compute_wm(intel_crtc);
1329         vlv_merge_wm(dev, &wm);
1330
1331         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1332                 /* FIXME should be part of crtc atomic commit */
1333                 vlv_pipe_set_fifo_size(intel_crtc);
1334                 return;
1335         }
1336
1337         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1338             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1339                 chv_set_memory_dvfs(dev_priv, false);
1340
1341         if (wm.level < VLV_WM_LEVEL_PM5 &&
1342             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1343                 chv_set_memory_pm5(dev_priv, false);
1344
1345         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1346                 intel_set_memory_cxsr(dev_priv, false);
1347
1348         /* FIXME should be part of crtc atomic commit */
1349         vlv_pipe_set_fifo_size(intel_crtc);
1350
1351         vlv_write_wm_values(intel_crtc, &wm);
1352
1353         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1354                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1355                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1356                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1357                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1358
1359         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1360                 intel_set_memory_cxsr(dev_priv, true);
1361
1362         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1363             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1364                 chv_set_memory_pm5(dev_priv, true);
1365
1366         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1367             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1368                 chv_set_memory_dvfs(dev_priv, true);
1369
1370         dev_priv->wm.vlv = wm;
1371 }
1372
1373 #define single_plane_enabled(mask) is_power_of_2(mask)
1374
1375 static void g4x_update_wm(struct drm_crtc *crtc)
1376 {
1377         struct drm_device *dev = crtc->dev;
1378         static const int sr_latency_ns = 12000;
1379         struct drm_i915_private *dev_priv = dev->dev_private;
1380         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1381         int plane_sr, cursor_sr;
1382         unsigned int enabled = 0;
1383         bool cxsr_enabled;
1384
1385         if (g4x_compute_wm0(dev, PIPE_A,
1386                             &g4x_wm_info, pessimal_latency_ns,
1387                             &g4x_cursor_wm_info, pessimal_latency_ns,
1388                             &planea_wm, &cursora_wm))
1389                 enabled |= 1 << PIPE_A;
1390
1391         if (g4x_compute_wm0(dev, PIPE_B,
1392                             &g4x_wm_info, pessimal_latency_ns,
1393                             &g4x_cursor_wm_info, pessimal_latency_ns,
1394                             &planeb_wm, &cursorb_wm))
1395                 enabled |= 1 << PIPE_B;
1396
1397         if (single_plane_enabled(enabled) &&
1398             g4x_compute_srwm(dev, ffs(enabled) - 1,
1399                              sr_latency_ns,
1400                              &g4x_wm_info,
1401                              &g4x_cursor_wm_info,
1402                              &plane_sr, &cursor_sr)) {
1403                 cxsr_enabled = true;
1404         } else {
1405                 cxsr_enabled = false;
1406                 intel_set_memory_cxsr(dev_priv, false);
1407                 plane_sr = cursor_sr = 0;
1408         }
1409
1410         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1411                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1412                       planea_wm, cursora_wm,
1413                       planeb_wm, cursorb_wm,
1414                       plane_sr, cursor_sr);
1415
1416         I915_WRITE(DSPFW1,
1417                    FW_WM(plane_sr, SR) |
1418                    FW_WM(cursorb_wm, CURSORB) |
1419                    FW_WM(planeb_wm, PLANEB) |
1420                    FW_WM(planea_wm, PLANEA));
1421         I915_WRITE(DSPFW2,
1422                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1423                    FW_WM(cursora_wm, CURSORA));
1424         /* HPLL off in SR has some issues on G4x... disable it */
1425         I915_WRITE(DSPFW3,
1426                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1427                    FW_WM(cursor_sr, CURSOR_SR));
1428
1429         if (cxsr_enabled)
1430                 intel_set_memory_cxsr(dev_priv, true);
1431 }
1432
1433 static void i965_update_wm(struct drm_crtc *unused_crtc)
1434 {
1435         struct drm_device *dev = unused_crtc->dev;
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         struct drm_crtc *crtc;
1438         int srwm = 1;
1439         int cursor_sr = 16;
1440         bool cxsr_enabled;
1441
1442         /* Calc sr entries for one plane configs */
1443         crtc = single_enabled_crtc(dev);
1444         if (crtc) {
1445                 /* self-refresh has much higher latency */
1446                 static const int sr_latency_ns = 12000;
1447                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1448                 int clock = adjusted_mode->crtc_clock;
1449                 int htotal = adjusted_mode->crtc_htotal;
1450                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1451                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1452                 unsigned long line_time_us;
1453                 int entries;
1454
1455                 line_time_us = max(htotal * 1000 / clock, 1);
1456
1457                 /* Use ns/us then divide to preserve precision */
1458                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459                         cpp * hdisplay;
1460                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1461                 srwm = I965_FIFO_SIZE - entries;
1462                 if (srwm < 0)
1463                         srwm = 1;
1464                 srwm &= 0x1ff;
1465                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1466                               entries, srwm);
1467
1468                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469                         cpp * crtc->cursor->state->crtc_w;
1470                 entries = DIV_ROUND_UP(entries,
1471                                           i965_cursor_wm_info.cacheline_size);
1472                 cursor_sr = i965_cursor_wm_info.fifo_size -
1473                         (entries + i965_cursor_wm_info.guard_size);
1474
1475                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1476                         cursor_sr = i965_cursor_wm_info.max_wm;
1477
1478                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1479                               "cursor %d\n", srwm, cursor_sr);
1480
1481                 cxsr_enabled = true;
1482         } else {
1483                 cxsr_enabled = false;
1484                 /* Turn off self refresh if both pipes are enabled */
1485                 intel_set_memory_cxsr(dev_priv, false);
1486         }
1487
1488         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1489                       srwm);
1490
1491         /* 965 has limitations... */
1492         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1493                    FW_WM(8, CURSORB) |
1494                    FW_WM(8, PLANEB) |
1495                    FW_WM(8, PLANEA));
1496         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1497                    FW_WM(8, PLANEC_OLD));
1498         /* update cursor SR watermark */
1499         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1500
1501         if (cxsr_enabled)
1502                 intel_set_memory_cxsr(dev_priv, true);
1503 }
1504
1505 #undef FW_WM
1506
1507 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1508 {
1509         struct drm_device *dev = unused_crtc->dev;
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         const struct intel_watermark_params *wm_info;
1512         uint32_t fwater_lo;
1513         uint32_t fwater_hi;
1514         int cwm, srwm = 1;
1515         int fifo_size;
1516         int planea_wm, planeb_wm;
1517         struct drm_crtc *crtc, *enabled = NULL;
1518
1519         if (IS_I945GM(dev))
1520                 wm_info = &i945_wm_info;
1521         else if (!IS_GEN2(dev))
1522                 wm_info = &i915_wm_info;
1523         else
1524                 wm_info = &i830_a_wm_info;
1525
1526         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1527         crtc = intel_get_crtc_for_plane(dev, 0);
1528         if (intel_crtc_active(crtc)) {
1529                 const struct drm_display_mode *adjusted_mode;
1530                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1531                 if (IS_GEN2(dev))
1532                         cpp = 4;
1533
1534                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1535                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1536                                                wm_info, fifo_size, cpp,
1537                                                pessimal_latency_ns);
1538                 enabled = crtc;
1539         } else {
1540                 planea_wm = fifo_size - wm_info->guard_size;
1541                 if (planea_wm > (long)wm_info->max_wm)
1542                         planea_wm = wm_info->max_wm;
1543         }
1544
1545         if (IS_GEN2(dev))
1546                 wm_info = &i830_bc_wm_info;
1547
1548         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1549         crtc = intel_get_crtc_for_plane(dev, 1);
1550         if (intel_crtc_active(crtc)) {
1551                 const struct drm_display_mode *adjusted_mode;
1552                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1553                 if (IS_GEN2(dev))
1554                         cpp = 4;
1555
1556                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1557                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1558                                                wm_info, fifo_size, cpp,
1559                                                pessimal_latency_ns);
1560                 if (enabled == NULL)
1561                         enabled = crtc;
1562                 else
1563                         enabled = NULL;
1564         } else {
1565                 planeb_wm = fifo_size - wm_info->guard_size;
1566                 if (planeb_wm > (long)wm_info->max_wm)
1567                         planeb_wm = wm_info->max_wm;
1568         }
1569
1570         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1571
1572         if (IS_I915GM(dev) && enabled) {
1573                 struct drm_i915_gem_object *obj;
1574
1575                 obj = intel_fb_obj(enabled->primary->state->fb);
1576
1577                 /* self-refresh seems busted with untiled */
1578                 if (obj->tiling_mode == I915_TILING_NONE)
1579                         enabled = NULL;
1580         }
1581
1582         /*
1583          * Overlay gets an aggressive default since video jitter is bad.
1584          */
1585         cwm = 2;
1586
1587         /* Play safe and disable self-refresh before adjusting watermarks. */
1588         intel_set_memory_cxsr(dev_priv, false);
1589
1590         /* Calc sr entries for one plane configs */
1591         if (HAS_FW_BLC(dev) && enabled) {
1592                 /* self-refresh has much higher latency */
1593                 static const int sr_latency_ns = 6000;
1594                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1595                 int clock = adjusted_mode->crtc_clock;
1596                 int htotal = adjusted_mode->crtc_htotal;
1597                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1598                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1599                 unsigned long line_time_us;
1600                 int entries;
1601
1602                 line_time_us = max(htotal * 1000 / clock, 1);
1603
1604                 /* Use ns/us then divide to preserve precision */
1605                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1606                         cpp * hdisplay;
1607                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1608                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1609                 srwm = wm_info->fifo_size - entries;
1610                 if (srwm < 0)
1611                         srwm = 1;
1612
1613                 if (IS_I945G(dev) || IS_I945GM(dev))
1614                         I915_WRITE(FW_BLC_SELF,
1615                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1616                 else if (IS_I915GM(dev))
1617                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1618         }
1619
1620         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1621                       planea_wm, planeb_wm, cwm, srwm);
1622
1623         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1624         fwater_hi = (cwm & 0x1f);
1625
1626         /* Set request length to 8 cachelines per fetch */
1627         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1628         fwater_hi = fwater_hi | (1 << 8);
1629
1630         I915_WRITE(FW_BLC, fwater_lo);
1631         I915_WRITE(FW_BLC2, fwater_hi);
1632
1633         if (enabled)
1634                 intel_set_memory_cxsr(dev_priv, true);
1635 }
1636
1637 static void i845_update_wm(struct drm_crtc *unused_crtc)
1638 {
1639         struct drm_device *dev = unused_crtc->dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         struct drm_crtc *crtc;
1642         const struct drm_display_mode *adjusted_mode;
1643         uint32_t fwater_lo;
1644         int planea_wm;
1645
1646         crtc = single_enabled_crtc(dev);
1647         if (crtc == NULL)
1648                 return;
1649
1650         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1651         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1652                                        &i845_wm_info,
1653                                        dev_priv->display.get_fifo_size(dev, 0),
1654                                        4, pessimal_latency_ns);
1655         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1656         fwater_lo |= (3<<8) | planea_wm;
1657
1658         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1659
1660         I915_WRITE(FW_BLC, fwater_lo);
1661 }
1662
1663 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1664 {
1665         uint32_t pixel_rate;
1666
1667         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1668
1669         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1670          * adjust the pixel_rate here. */
1671
1672         if (pipe_config->pch_pfit.enabled) {
1673                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1674                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1675
1676                 pipe_w = pipe_config->pipe_src_w;
1677                 pipe_h = pipe_config->pipe_src_h;
1678
1679                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1680                 pfit_h = pfit_size & 0xFFFF;
1681                 if (pipe_w < pfit_w)
1682                         pipe_w = pfit_w;
1683                 if (pipe_h < pfit_h)
1684                         pipe_h = pfit_h;
1685
1686                 if (WARN_ON(!pfit_w || !pfit_h))
1687                         return pixel_rate;
1688
1689                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1690                                      pfit_w * pfit_h);
1691         }
1692
1693         return pixel_rate;
1694 }
1695
1696 /* latency must be in 0.1us units. */
1697 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1698 {
1699         uint64_t ret;
1700
1701         if (WARN(latency == 0, "Latency value missing\n"))
1702                 return UINT_MAX;
1703
1704         ret = (uint64_t) pixel_rate * cpp * latency;
1705         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1706
1707         return ret;
1708 }
1709
1710 /* latency must be in 0.1us units. */
1711 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1712                                uint32_t horiz_pixels, uint8_t cpp,
1713                                uint32_t latency)
1714 {
1715         uint32_t ret;
1716
1717         if (WARN(latency == 0, "Latency value missing\n"))
1718                 return UINT_MAX;
1719         if (WARN_ON(!pipe_htotal))
1720                 return UINT_MAX;
1721
1722         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1723         ret = (ret + 1) * horiz_pixels * cpp;
1724         ret = DIV_ROUND_UP(ret, 64) + 2;
1725         return ret;
1726 }
1727
1728 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1729                            uint8_t cpp)
1730 {
1731         /*
1732          * Neither of these should be possible since this function shouldn't be
1733          * called if the CRTC is off or the plane is invisible.  But let's be
1734          * extra paranoid to avoid a potential divide-by-zero if we screw up
1735          * elsewhere in the driver.
1736          */
1737         if (WARN_ON(!cpp))
1738                 return 0;
1739         if (WARN_ON(!horiz_pixels))
1740                 return 0;
1741
1742         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1743 }
1744
1745 struct ilk_wm_maximums {
1746         uint16_t pri;
1747         uint16_t spr;
1748         uint16_t cur;
1749         uint16_t fbc;
1750 };
1751
1752 /*
1753  * For both WM_PIPE and WM_LP.
1754  * mem_value must be in 0.1us units.
1755  */
1756 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1757                                    const struct intel_plane_state *pstate,
1758                                    uint32_t mem_value,
1759                                    bool is_lp)
1760 {
1761         int cpp = pstate->base.fb ?
1762                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1763         uint32_t method1, method2;
1764
1765         if (!cstate->base.active || !pstate->visible)
1766                 return 0;
1767
1768         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1769
1770         if (!is_lp)
1771                 return method1;
1772
1773         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774                                  cstate->base.adjusted_mode.crtc_htotal,
1775                                  drm_rect_width(&pstate->dst),
1776                                  cpp, mem_value);
1777
1778         return min(method1, method2);
1779 }
1780
1781 /*
1782  * For both WM_PIPE and WM_LP.
1783  * mem_value must be in 0.1us units.
1784  */
1785 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1786                                    const struct intel_plane_state *pstate,
1787                                    uint32_t mem_value)
1788 {
1789         int cpp = pstate->base.fb ?
1790                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1791         uint32_t method1, method2;
1792
1793         if (!cstate->base.active || !pstate->visible)
1794                 return 0;
1795
1796         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1797         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798                                  cstate->base.adjusted_mode.crtc_htotal,
1799                                  drm_rect_width(&pstate->dst),
1800                                  cpp, mem_value);
1801         return min(method1, method2);
1802 }
1803
1804 /*
1805  * For both WM_PIPE and WM_LP.
1806  * mem_value must be in 0.1us units.
1807  */
1808 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1809                                    const struct intel_plane_state *pstate,
1810                                    uint32_t mem_value)
1811 {
1812         /*
1813          * We treat the cursor plane as always-on for the purposes of watermark
1814          * calculation.  Until we have two-stage watermark programming merged,
1815          * this is necessary to avoid flickering.
1816          */
1817         int cpp = 4;
1818         int width = pstate->visible ? pstate->base.crtc_w : 64;
1819
1820         if (!cstate->base.active)
1821                 return 0;
1822
1823         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1824                               cstate->base.adjusted_mode.crtc_htotal,
1825                               width, cpp, mem_value);
1826 }
1827
1828 /* Only for WM_LP. */
1829 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1830                                    const struct intel_plane_state *pstate,
1831                                    uint32_t pri_val)
1832 {
1833         int cpp = pstate->base.fb ?
1834                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1835
1836         if (!cstate->base.active || !pstate->visible)
1837                 return 0;
1838
1839         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1840 }
1841
1842 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1843 {
1844         if (INTEL_INFO(dev)->gen >= 8)
1845                 return 3072;
1846         else if (INTEL_INFO(dev)->gen >= 7)
1847                 return 768;
1848         else
1849                 return 512;
1850 }
1851
1852 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1853                                          int level, bool is_sprite)
1854 {
1855         if (INTEL_INFO(dev)->gen >= 8)
1856                 /* BDW primary/sprite plane watermarks */
1857                 return level == 0 ? 255 : 2047;
1858         else if (INTEL_INFO(dev)->gen >= 7)
1859                 /* IVB/HSW primary/sprite plane watermarks */
1860                 return level == 0 ? 127 : 1023;
1861         else if (!is_sprite)
1862                 /* ILK/SNB primary plane watermarks */
1863                 return level == 0 ? 127 : 511;
1864         else
1865                 /* ILK/SNB sprite plane watermarks */
1866                 return level == 0 ? 63 : 255;
1867 }
1868
1869 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1870                                           int level)
1871 {
1872         if (INTEL_INFO(dev)->gen >= 7)
1873                 return level == 0 ? 63 : 255;
1874         else
1875                 return level == 0 ? 31 : 63;
1876 }
1877
1878 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1879 {
1880         if (INTEL_INFO(dev)->gen >= 8)
1881                 return 31;
1882         else
1883                 return 15;
1884 }
1885
1886 /* Calculate the maximum primary/sprite plane watermark */
1887 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1888                                      int level,
1889                                      const struct intel_wm_config *config,
1890                                      enum intel_ddb_partitioning ddb_partitioning,
1891                                      bool is_sprite)
1892 {
1893         unsigned int fifo_size = ilk_display_fifo_size(dev);
1894
1895         /* if sprites aren't enabled, sprites get nothing */
1896         if (is_sprite && !config->sprites_enabled)
1897                 return 0;
1898
1899         /* HSW allows LP1+ watermarks even with multiple pipes */
1900         if (level == 0 || config->num_pipes_active > 1) {
1901                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1902
1903                 /*
1904                  * For some reason the non self refresh
1905                  * FIFO size is only half of the self
1906                  * refresh FIFO size on ILK/SNB.
1907                  */
1908                 if (INTEL_INFO(dev)->gen <= 6)
1909                         fifo_size /= 2;
1910         }
1911
1912         if (config->sprites_enabled) {
1913                 /* level 0 is always calculated with 1:1 split */
1914                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1915                         if (is_sprite)
1916                                 fifo_size *= 5;
1917                         fifo_size /= 6;
1918                 } else {
1919                         fifo_size /= 2;
1920                 }
1921         }
1922
1923         /* clamp to max that the registers can hold */
1924         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1925 }
1926
1927 /* Calculate the maximum cursor plane watermark */
1928 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1929                                       int level,
1930                                       const struct intel_wm_config *config)
1931 {
1932         /* HSW LP1+ watermarks w/ multiple pipes */
1933         if (level > 0 && config->num_pipes_active > 1)
1934                 return 64;
1935
1936         /* otherwise just report max that registers can hold */
1937         return ilk_cursor_wm_reg_max(dev, level);
1938 }
1939
1940 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1941                                     int level,
1942                                     const struct intel_wm_config *config,
1943                                     enum intel_ddb_partitioning ddb_partitioning,
1944                                     struct ilk_wm_maximums *max)
1945 {
1946         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1947         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1948         max->cur = ilk_cursor_wm_max(dev, level, config);
1949         max->fbc = ilk_fbc_wm_reg_max(dev);
1950 }
1951
1952 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1953                                         int level,
1954                                         struct ilk_wm_maximums *max)
1955 {
1956         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1957         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1958         max->cur = ilk_cursor_wm_reg_max(dev, level);
1959         max->fbc = ilk_fbc_wm_reg_max(dev);
1960 }
1961
1962 static bool ilk_validate_wm_level(int level,
1963                                   const struct ilk_wm_maximums *max,
1964                                   struct intel_wm_level *result)
1965 {
1966         bool ret;
1967
1968         /* already determined to be invalid? */
1969         if (!result->enable)
1970                 return false;
1971
1972         result->enable = result->pri_val <= max->pri &&
1973                          result->spr_val <= max->spr &&
1974                          result->cur_val <= max->cur;
1975
1976         ret = result->enable;
1977
1978         /*
1979          * HACK until we can pre-compute everything,
1980          * and thus fail gracefully if LP0 watermarks
1981          * are exceeded...
1982          */
1983         if (level == 0 && !result->enable) {
1984                 if (result->pri_val > max->pri)
1985                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1986                                       level, result->pri_val, max->pri);
1987                 if (result->spr_val > max->spr)
1988                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1989                                       level, result->spr_val, max->spr);
1990                 if (result->cur_val > max->cur)
1991                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1992                                       level, result->cur_val, max->cur);
1993
1994                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1995                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1996                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1997                 result->enable = true;
1998         }
1999
2000         return ret;
2001 }
2002
2003 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2004                                  const struct intel_crtc *intel_crtc,
2005                                  int level,
2006                                  struct intel_crtc_state *cstate,
2007                                  struct intel_plane_state *pristate,
2008                                  struct intel_plane_state *sprstate,
2009                                  struct intel_plane_state *curstate,
2010                                  struct intel_wm_level *result)
2011 {
2012         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2013         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2014         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2015
2016         /* WM1+ latency values stored in 0.5us units */
2017         if (level > 0) {
2018                 pri_latency *= 5;
2019                 spr_latency *= 5;
2020                 cur_latency *= 5;
2021         }
2022
2023         if (pristate) {
2024                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2025                                                      pri_latency, level);
2026                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2027         }
2028
2029         if (sprstate)
2030                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2031
2032         if (curstate)
2033                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2034
2035         result->enable = true;
2036 }
2037
2038 static uint32_t
2039 hsw_compute_linetime_wm(struct drm_device *dev,
2040                         struct intel_crtc_state *cstate)
2041 {
2042         struct drm_i915_private *dev_priv = dev->dev_private;
2043         const struct drm_display_mode *adjusted_mode =
2044                 &cstate->base.adjusted_mode;
2045         u32 linetime, ips_linetime;
2046
2047         if (!cstate->base.active)
2048                 return 0;
2049         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2050                 return 0;
2051         if (WARN_ON(dev_priv->cdclk_freq == 0))
2052                 return 0;
2053
2054         /* The WM are computed with base on how long it takes to fill a single
2055          * row at the given clock rate, multiplied by 8.
2056          * */
2057         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2058                                      adjusted_mode->crtc_clock);
2059         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2060                                          dev_priv->cdclk_freq);
2061
2062         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2063                PIPE_WM_LINETIME_TIME(linetime);
2064 }
2065
2066 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2067 {
2068         struct drm_i915_private *dev_priv = dev->dev_private;
2069
2070         if (IS_GEN9(dev)) {
2071                 uint32_t val;
2072                 int ret, i;
2073                 int level, max_level = ilk_wm_max_level(dev);
2074
2075                 /* read the first set of memory latencies[0:3] */
2076                 val = 0; /* data0 to be programmed to 0 for first set */
2077                 mutex_lock(&dev_priv->rps.hw_lock);
2078                 ret = sandybridge_pcode_read(dev_priv,
2079                                              GEN9_PCODE_READ_MEM_LATENCY,
2080                                              &val);
2081                 mutex_unlock(&dev_priv->rps.hw_lock);
2082
2083                 if (ret) {
2084                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2085                         return;
2086                 }
2087
2088                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2089                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2090                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2091                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2092                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2093                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2094                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2095
2096                 /* read the second set of memory latencies[4:7] */
2097                 val = 1; /* data0 to be programmed to 1 for second set */
2098                 mutex_lock(&dev_priv->rps.hw_lock);
2099                 ret = sandybridge_pcode_read(dev_priv,
2100                                              GEN9_PCODE_READ_MEM_LATENCY,
2101                                              &val);
2102                 mutex_unlock(&dev_priv->rps.hw_lock);
2103                 if (ret) {
2104                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2105                         return;
2106                 }
2107
2108                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2109                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2110                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2111                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2112                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2113                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2114                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2115
2116                 /*
2117                  * WaWmMemoryReadLatency:skl
2118                  *
2119                  * punit doesn't take into account the read latency so we need
2120                  * to add 2us to the various latency levels we retrieve from
2121                  * the punit.
2122                  *   - W0 is a bit special in that it's the only level that
2123                  *   can't be disabled if we want to have display working, so
2124                  *   we always add 2us there.
2125                  *   - For levels >=1, punit returns 0us latency when they are
2126                  *   disabled, so we respect that and don't add 2us then
2127                  *
2128                  * Additionally, if a level n (n > 1) has a 0us latency, all
2129                  * levels m (m >= n) need to be disabled. We make sure to
2130                  * sanitize the values out of the punit to satisfy this
2131                  * requirement.
2132                  */
2133                 wm[0] += 2;
2134                 for (level = 1; level <= max_level; level++)
2135                         if (wm[level] != 0)
2136                                 wm[level] += 2;
2137                         else {
2138                                 for (i = level + 1; i <= max_level; i++)
2139                                         wm[i] = 0;
2140
2141                                 break;
2142                         }
2143         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2144                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2145
2146                 wm[0] = (sskpd >> 56) & 0xFF;
2147                 if (wm[0] == 0)
2148                         wm[0] = sskpd & 0xF;
2149                 wm[1] = (sskpd >> 4) & 0xFF;
2150                 wm[2] = (sskpd >> 12) & 0xFF;
2151                 wm[3] = (sskpd >> 20) & 0x1FF;
2152                 wm[4] = (sskpd >> 32) & 0x1FF;
2153         } else if (INTEL_INFO(dev)->gen >= 6) {
2154                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2155
2156                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2157                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2158                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2159                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2160         } else if (INTEL_INFO(dev)->gen >= 5) {
2161                 uint32_t mltr = I915_READ(MLTR_ILK);
2162
2163                 /* ILK primary LP0 latency is 700 ns */
2164                 wm[0] = 7;
2165                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2166                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2167         }
2168 }
2169
2170 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2171 {
2172         /* ILK sprite LP0 latency is 1300 ns */
2173         if (INTEL_INFO(dev)->gen == 5)
2174                 wm[0] = 13;
2175 }
2176
2177 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2178 {
2179         /* ILK cursor LP0 latency is 1300 ns */
2180         if (INTEL_INFO(dev)->gen == 5)
2181                 wm[0] = 13;
2182
2183         /* WaDoubleCursorLP3Latency:ivb */
2184         if (IS_IVYBRIDGE(dev))
2185                 wm[3] *= 2;
2186 }
2187
2188 int ilk_wm_max_level(const struct drm_device *dev)
2189 {
2190         /* how many WM levels are we expecting */
2191         if (INTEL_INFO(dev)->gen >= 9)
2192                 return 7;
2193         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2194                 return 4;
2195         else if (INTEL_INFO(dev)->gen >= 6)
2196                 return 3;
2197         else
2198                 return 2;
2199 }
2200
2201 static void intel_print_wm_latency(struct drm_device *dev,
2202                                    const char *name,
2203                                    const uint16_t wm[8])
2204 {
2205         int level, max_level = ilk_wm_max_level(dev);
2206
2207         for (level = 0; level <= max_level; level++) {
2208                 unsigned int latency = wm[level];
2209
2210                 if (latency == 0) {
2211                         DRM_ERROR("%s WM%d latency not provided\n",
2212                                   name, level);
2213                         continue;
2214                 }
2215
2216                 /*
2217                  * - latencies are in us on gen9.
2218                  * - before then, WM1+ latency values are in 0.5us units
2219                  */
2220                 if (IS_GEN9(dev))
2221                         latency *= 10;
2222                 else if (level > 0)
2223                         latency *= 5;
2224
2225                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2226                               name, level, wm[level],
2227                               latency / 10, latency % 10);
2228         }
2229 }
2230
2231 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2232                                     uint16_t wm[5], uint16_t min)
2233 {
2234         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2235
2236         if (wm[0] >= min)
2237                 return false;
2238
2239         wm[0] = max(wm[0], min);
2240         for (level = 1; level <= max_level; level++)
2241                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2242
2243         return true;
2244 }
2245
2246 static void snb_wm_latency_quirk(struct drm_device *dev)
2247 {
2248         struct drm_i915_private *dev_priv = dev->dev_private;
2249         bool changed;
2250
2251         /*
2252          * The BIOS provided WM memory latency values are often
2253          * inadequate for high resolution displays. Adjust them.
2254          */
2255         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2256                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2257                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2258
2259         if (!changed)
2260                 return;
2261
2262         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2263         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2264         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2265         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2266 }
2267
2268 static void ilk_setup_wm_latency(struct drm_device *dev)
2269 {
2270         struct drm_i915_private *dev_priv = dev->dev_private;
2271
2272         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2273
2274         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2275                sizeof(dev_priv->wm.pri_latency));
2276         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2277                sizeof(dev_priv->wm.pri_latency));
2278
2279         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2280         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2281
2282         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2283         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2284         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2285
2286         if (IS_GEN6(dev))
2287                 snb_wm_latency_quirk(dev);
2288 }
2289
2290 static void skl_setup_wm_latency(struct drm_device *dev)
2291 {
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293
2294         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2295         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2296 }
2297
2298 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2299                                  struct intel_pipe_wm *pipe_wm)
2300 {
2301         /* LP0 watermark maximums depend on this pipe alone */
2302         const struct intel_wm_config config = {
2303                 .num_pipes_active = 1,
2304                 .sprites_enabled = pipe_wm->sprites_enabled,
2305                 .sprites_scaled = pipe_wm->sprites_scaled,
2306         };
2307         struct ilk_wm_maximums max;
2308
2309         /* LP0 watermarks always use 1/2 DDB partitioning */
2310         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2311
2312         /* At least LP0 must be valid */
2313         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2314                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2315                 return false;
2316         }
2317
2318         return true;
2319 }
2320
2321 /* Compute new watermarks for the pipe */
2322 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2323 {
2324         struct drm_atomic_state *state = cstate->base.state;
2325         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2326         struct intel_pipe_wm *pipe_wm;
2327         struct drm_device *dev = state->dev;
2328         const struct drm_i915_private *dev_priv = dev->dev_private;
2329         struct intel_plane *intel_plane;
2330         struct intel_plane_state *pristate = NULL;
2331         struct intel_plane_state *sprstate = NULL;
2332         struct intel_plane_state *curstate = NULL;
2333         int level, max_level = ilk_wm_max_level(dev), usable_level;
2334         struct ilk_wm_maximums max;
2335
2336         pipe_wm = &cstate->wm.optimal.ilk;
2337
2338         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2339                 struct intel_plane_state *ps;
2340
2341                 ps = intel_atomic_get_existing_plane_state(state,
2342                                                            intel_plane);
2343                 if (!ps)
2344                         continue;
2345
2346                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2347                         pristate = ps;
2348                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2349                         sprstate = ps;
2350                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2351                         curstate = ps;
2352         }
2353
2354         pipe_wm->pipe_enabled = cstate->base.active;
2355         if (sprstate) {
2356                 pipe_wm->sprites_enabled = sprstate->visible;
2357                 pipe_wm->sprites_scaled = sprstate->visible &&
2358                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2359                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2360         }
2361
2362         usable_level = max_level;
2363
2364         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2365         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2366                 usable_level = 1;
2367
2368         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2369         if (pipe_wm->sprites_scaled)
2370                 usable_level = 0;
2371
2372         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2373                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2374
2375         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2376         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2377
2378         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2379                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2380
2381         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2382                 return -EINVAL;
2383
2384         ilk_compute_wm_reg_maximums(dev, 1, &max);
2385
2386         for (level = 1; level <= max_level; level++) {
2387                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2388
2389                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2390                                      pristate, sprstate, curstate, wm);
2391
2392                 /*
2393                  * Disable any watermark level that exceeds the
2394                  * register maximums since such watermarks are
2395                  * always invalid.
2396                  */
2397                 if (level > usable_level)
2398                         continue;
2399
2400                 if (ilk_validate_wm_level(level, &max, wm))
2401                         pipe_wm->wm[level] = *wm;
2402                 else
2403                         usable_level = level;
2404         }
2405
2406         return 0;
2407 }
2408
2409 /*
2410  * Build a set of 'intermediate' watermark values that satisfy both the old
2411  * state and the new state.  These can be programmed to the hardware
2412  * immediately.
2413  */
2414 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2415                                        struct intel_crtc *intel_crtc,
2416                                        struct intel_crtc_state *newstate)
2417 {
2418         struct intel_pipe_wm *a = &newstate->wm.intermediate;
2419         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2420         int level, max_level = ilk_wm_max_level(dev);
2421
2422         /*
2423          * Start with the final, target watermarks, then combine with the
2424          * currently active watermarks to get values that are safe both before
2425          * and after the vblank.
2426          */
2427         *a = newstate->wm.optimal.ilk;
2428         a->pipe_enabled |= b->pipe_enabled;
2429         a->sprites_enabled |= b->sprites_enabled;
2430         a->sprites_scaled |= b->sprites_scaled;
2431
2432         for (level = 0; level <= max_level; level++) {
2433                 struct intel_wm_level *a_wm = &a->wm[level];
2434                 const struct intel_wm_level *b_wm = &b->wm[level];
2435
2436                 a_wm->enable &= b_wm->enable;
2437                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2438                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2439                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2440                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2441         }
2442
2443         /*
2444          * We need to make sure that these merged watermark values are
2445          * actually a valid configuration themselves.  If they're not,
2446          * there's no safe way to transition from the old state to
2447          * the new state, so we need to fail the atomic transaction.
2448          */
2449         if (!ilk_validate_pipe_wm(dev, a))
2450                 return -EINVAL;
2451
2452         /*
2453          * If our intermediate WM are identical to the final WM, then we can
2454          * omit the post-vblank programming; only update if it's different.
2455          */
2456         if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2457                 newstate->wm.need_postvbl_update = false;
2458
2459         return 0;
2460 }
2461
2462 /*
2463  * Merge the watermarks from all active pipes for a specific level.
2464  */
2465 static void ilk_merge_wm_level(struct drm_device *dev,
2466                                int level,
2467                                struct intel_wm_level *ret_wm)
2468 {
2469         const struct intel_crtc *intel_crtc;
2470
2471         ret_wm->enable = true;
2472
2473         for_each_intel_crtc(dev, intel_crtc) {
2474                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2475                 const struct intel_wm_level *wm = &active->wm[level];
2476
2477                 if (!active->pipe_enabled)
2478                         continue;
2479
2480                 /*
2481                  * The watermark values may have been used in the past,
2482                  * so we must maintain them in the registers for some
2483                  * time even if the level is now disabled.
2484                  */
2485                 if (!wm->enable)
2486                         ret_wm->enable = false;
2487
2488                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2489                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2490                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2491                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2492         }
2493 }
2494
2495 /*
2496  * Merge all low power watermarks for all active pipes.
2497  */
2498 static void ilk_wm_merge(struct drm_device *dev,
2499                          const struct intel_wm_config *config,
2500                          const struct ilk_wm_maximums *max,
2501                          struct intel_pipe_wm *merged)
2502 {
2503         struct drm_i915_private *dev_priv = dev->dev_private;
2504         int level, max_level = ilk_wm_max_level(dev);
2505         int last_enabled_level = max_level;
2506
2507         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2508         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2509             config->num_pipes_active > 1)
2510                 last_enabled_level = 0;
2511
2512         /* ILK: FBC WM must be disabled always */
2513         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2514
2515         /* merge each WM1+ level */
2516         for (level = 1; level <= max_level; level++) {
2517                 struct intel_wm_level *wm = &merged->wm[level];
2518
2519                 ilk_merge_wm_level(dev, level, wm);
2520
2521                 if (level > last_enabled_level)
2522                         wm->enable = false;
2523                 else if (!ilk_validate_wm_level(level, max, wm))
2524                         /* make sure all following levels get disabled */
2525                         last_enabled_level = level - 1;
2526
2527                 /*
2528                  * The spec says it is preferred to disable
2529                  * FBC WMs instead of disabling a WM level.
2530                  */
2531                 if (wm->fbc_val > max->fbc) {
2532                         if (wm->enable)
2533                                 merged->fbc_wm_enabled = false;
2534                         wm->fbc_val = 0;
2535                 }
2536         }
2537
2538         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2539         /*
2540          * FIXME this is racy. FBC might get enabled later.
2541          * What we should check here is whether FBC can be
2542          * enabled sometime later.
2543          */
2544         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2545             intel_fbc_is_active(dev_priv)) {
2546                 for (level = 2; level <= max_level; level++) {
2547                         struct intel_wm_level *wm = &merged->wm[level];
2548
2549                         wm->enable = false;
2550                 }
2551         }
2552 }
2553
2554 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2555 {
2556         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2557         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2558 }
2559
2560 /* The value we need to program into the WM_LPx latency field */
2561 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2562 {
2563         struct drm_i915_private *dev_priv = dev->dev_private;
2564
2565         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2566                 return 2 * level;
2567         else
2568                 return dev_priv->wm.pri_latency[level];
2569 }
2570
2571 static void ilk_compute_wm_results(struct drm_device *dev,
2572                                    const struct intel_pipe_wm *merged,
2573                                    enum intel_ddb_partitioning partitioning,
2574                                    struct ilk_wm_values *results)
2575 {
2576         struct intel_crtc *intel_crtc;
2577         int level, wm_lp;
2578
2579         results->enable_fbc_wm = merged->fbc_wm_enabled;
2580         results->partitioning = partitioning;
2581
2582         /* LP1+ register values */
2583         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2584                 const struct intel_wm_level *r;
2585
2586                 level = ilk_wm_lp_to_level(wm_lp, merged);
2587
2588                 r = &merged->wm[level];
2589
2590                 /*
2591                  * Maintain the watermark values even if the level is
2592                  * disabled. Doing otherwise could cause underruns.
2593                  */
2594                 results->wm_lp[wm_lp - 1] =
2595                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2596                         (r->pri_val << WM1_LP_SR_SHIFT) |
2597                         r->cur_val;
2598
2599                 if (r->enable)
2600                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2601
2602                 if (INTEL_INFO(dev)->gen >= 8)
2603                         results->wm_lp[wm_lp - 1] |=
2604                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2605                 else
2606                         results->wm_lp[wm_lp - 1] |=
2607                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2608
2609                 /*
2610                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2611                  * level is disabled. Doing otherwise could cause underruns.
2612                  */
2613                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2614                         WARN_ON(wm_lp != 1);
2615                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2616                 } else
2617                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2618         }
2619
2620         /* LP0 register values */
2621         for_each_intel_crtc(dev, intel_crtc) {
2622                 enum pipe pipe = intel_crtc->pipe;
2623                 const struct intel_wm_level *r =
2624                         &intel_crtc->wm.active.ilk.wm[0];
2625
2626                 if (WARN_ON(!r->enable))
2627                         continue;
2628
2629                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2630
2631                 results->wm_pipe[pipe] =
2632                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2633                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2634                         r->cur_val;
2635         }
2636 }
2637
2638 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2639  * case both are at the same level. Prefer r1 in case they're the same. */
2640 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2641                                                   struct intel_pipe_wm *r1,
2642                                                   struct intel_pipe_wm *r2)
2643 {
2644         int level, max_level = ilk_wm_max_level(dev);
2645         int level1 = 0, level2 = 0;
2646
2647         for (level = 1; level <= max_level; level++) {
2648                 if (r1->wm[level].enable)
2649                         level1 = level;
2650                 if (r2->wm[level].enable)
2651                         level2 = level;
2652         }
2653
2654         if (level1 == level2) {
2655                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2656                         return r2;
2657                 else
2658                         return r1;
2659         } else if (level1 > level2) {
2660                 return r1;
2661         } else {
2662                 return r2;
2663         }
2664 }
2665
2666 /* dirty bits used to track which watermarks need changes */
2667 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2668 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2669 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2670 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2671 #define WM_DIRTY_FBC (1 << 24)
2672 #define WM_DIRTY_DDB (1 << 25)
2673
2674 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2675                                          const struct ilk_wm_values *old,
2676                                          const struct ilk_wm_values *new)
2677 {
2678         unsigned int dirty = 0;
2679         enum pipe pipe;
2680         int wm_lp;
2681
2682         for_each_pipe(dev_priv, pipe) {
2683                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2684                         dirty |= WM_DIRTY_LINETIME(pipe);
2685                         /* Must disable LP1+ watermarks too */
2686                         dirty |= WM_DIRTY_LP_ALL;
2687                 }
2688
2689                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2690                         dirty |= WM_DIRTY_PIPE(pipe);
2691                         /* Must disable LP1+ watermarks too */
2692                         dirty |= WM_DIRTY_LP_ALL;
2693                 }
2694         }
2695
2696         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2697                 dirty |= WM_DIRTY_FBC;
2698                 /* Must disable LP1+ watermarks too */
2699                 dirty |= WM_DIRTY_LP_ALL;
2700         }
2701
2702         if (old->partitioning != new->partitioning) {
2703                 dirty |= WM_DIRTY_DDB;
2704                 /* Must disable LP1+ watermarks too */
2705                 dirty |= WM_DIRTY_LP_ALL;
2706         }
2707
2708         /* LP1+ watermarks already deemed dirty, no need to continue */
2709         if (dirty & WM_DIRTY_LP_ALL)
2710                 return dirty;
2711
2712         /* Find the lowest numbered LP1+ watermark in need of an update... */
2713         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2714                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2715                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2716                         break;
2717         }
2718
2719         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2720         for (; wm_lp <= 3; wm_lp++)
2721                 dirty |= WM_DIRTY_LP(wm_lp);
2722
2723         return dirty;
2724 }
2725
2726 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2727                                unsigned int dirty)
2728 {
2729         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2730         bool changed = false;
2731
2732         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2733                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2734                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2735                 changed = true;
2736         }
2737         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2738                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2739                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2740                 changed = true;
2741         }
2742         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2743                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2744                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2745                 changed = true;
2746         }
2747
2748         /*
2749          * Don't touch WM1S_LP_EN here.
2750          * Doing so could cause underruns.
2751          */
2752
2753         return changed;
2754 }
2755
2756 /*
2757  * The spec says we shouldn't write when we don't need, because every write
2758  * causes WMs to be re-evaluated, expending some power.
2759  */
2760 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2761                                 struct ilk_wm_values *results)
2762 {
2763         struct drm_device *dev = dev_priv->dev;
2764         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2765         unsigned int dirty;
2766         uint32_t val;
2767
2768         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2769         if (!dirty)
2770                 return;
2771
2772         _ilk_disable_lp_wm(dev_priv, dirty);
2773
2774         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2775                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2776         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2777                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2778         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2779                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2780
2781         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2782                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2783         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2784                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2785         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2786                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2787
2788         if (dirty & WM_DIRTY_DDB) {
2789                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2790                         val = I915_READ(WM_MISC);
2791                         if (results->partitioning == INTEL_DDB_PART_1_2)
2792                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2793                         else
2794                                 val |= WM_MISC_DATA_PARTITION_5_6;
2795                         I915_WRITE(WM_MISC, val);
2796                 } else {
2797                         val = I915_READ(DISP_ARB_CTL2);
2798                         if (results->partitioning == INTEL_DDB_PART_1_2)
2799                                 val &= ~DISP_DATA_PARTITION_5_6;
2800                         else
2801                                 val |= DISP_DATA_PARTITION_5_6;
2802                         I915_WRITE(DISP_ARB_CTL2, val);
2803                 }
2804         }
2805
2806         if (dirty & WM_DIRTY_FBC) {
2807                 val = I915_READ(DISP_ARB_CTL);
2808                 if (results->enable_fbc_wm)
2809                         val &= ~DISP_FBC_WM_DIS;
2810                 else
2811                         val |= DISP_FBC_WM_DIS;
2812                 I915_WRITE(DISP_ARB_CTL, val);
2813         }
2814
2815         if (dirty & WM_DIRTY_LP(1) &&
2816             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2817                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2818
2819         if (INTEL_INFO(dev)->gen >= 7) {
2820                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2821                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2822                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2823                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2824         }
2825
2826         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2827                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2828         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2829                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2830         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2831                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2832
2833         dev_priv->wm.hw = *results;
2834 }
2835
2836 bool ilk_disable_lp_wm(struct drm_device *dev)
2837 {
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839
2840         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2841 }
2842
2843 /*
2844  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2845  * different active planes.
2846  */
2847
2848 #define SKL_DDB_SIZE            896     /* in blocks */
2849 #define BXT_DDB_SIZE            512
2850
2851 /*
2852  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2853  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2854  * other universal planes are in indices 1..n.  Note that this may leave unused
2855  * indices between the top "sprite" plane and the cursor.
2856  */
2857 static int
2858 skl_wm_plane_id(const struct intel_plane *plane)
2859 {
2860         switch (plane->base.type) {
2861         case DRM_PLANE_TYPE_PRIMARY:
2862                 return 0;
2863         case DRM_PLANE_TYPE_CURSOR:
2864                 return PLANE_CURSOR;
2865         case DRM_PLANE_TYPE_OVERLAY:
2866                 return plane->plane + 1;
2867         default:
2868                 MISSING_CASE(plane->base.type);
2869                 return plane->plane;
2870         }
2871 }
2872
2873 static void
2874 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2875                                    const struct intel_crtc_state *cstate,
2876                                    const struct intel_wm_config *config,
2877                                    struct skl_ddb_entry *alloc /* out */)
2878 {
2879         struct drm_crtc *for_crtc = cstate->base.crtc;
2880         struct drm_crtc *crtc;
2881         unsigned int pipe_size, ddb_size;
2882         int nth_active_pipe;
2883
2884         if (!cstate->base.active) {
2885                 alloc->start = 0;
2886                 alloc->end = 0;
2887                 return;
2888         }
2889
2890         if (IS_BROXTON(dev))
2891                 ddb_size = BXT_DDB_SIZE;
2892         else
2893                 ddb_size = SKL_DDB_SIZE;
2894
2895         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2896
2897         nth_active_pipe = 0;
2898         for_each_crtc(dev, crtc) {
2899                 if (!to_intel_crtc(crtc)->active)
2900                         continue;
2901
2902                 if (crtc == for_crtc)
2903                         break;
2904
2905                 nth_active_pipe++;
2906         }
2907
2908         pipe_size = ddb_size / config->num_pipes_active;
2909         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2910         alloc->end = alloc->start + pipe_size;
2911 }
2912
2913 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2914 {
2915         if (config->num_pipes_active == 1)
2916                 return 32;
2917
2918         return 8;
2919 }
2920
2921 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2922 {
2923         entry->start = reg & 0x3ff;
2924         entry->end = (reg >> 16) & 0x3ff;
2925         if (entry->end)
2926                 entry->end += 1;
2927 }
2928
2929 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2930                           struct skl_ddb_allocation *ddb /* out */)
2931 {
2932         enum pipe pipe;
2933         int plane;
2934         u32 val;
2935
2936         memset(ddb, 0, sizeof(*ddb));
2937
2938         for_each_pipe(dev_priv, pipe) {
2939                 enum intel_display_power_domain power_domain;
2940
2941                 power_domain = POWER_DOMAIN_PIPE(pipe);
2942                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2943                         continue;
2944
2945                 for_each_plane(dev_priv, pipe, plane) {
2946                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2947                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2948                                                    val);
2949                 }
2950
2951                 val = I915_READ(CUR_BUF_CFG(pipe));
2952                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2953                                            val);
2954
2955                 intel_display_power_put(dev_priv, power_domain);
2956         }
2957 }
2958
2959 static unsigned int
2960 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2961                              const struct drm_plane_state *pstate,
2962                              int y)
2963 {
2964         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2965         struct drm_framebuffer *fb = pstate->fb;
2966         uint32_t width = 0, height = 0;
2967
2968         width = drm_rect_width(&intel_pstate->src) >> 16;
2969         height = drm_rect_height(&intel_pstate->src) >> 16;
2970
2971         if (intel_rotation_90_or_270(pstate->rotation))
2972                 swap(width, height);
2973
2974         /* for planar format */
2975         if (fb->pixel_format == DRM_FORMAT_NV12) {
2976                 if (y)  /* y-plane data rate */
2977                         return width * height *
2978                                 drm_format_plane_cpp(fb->pixel_format, 0);
2979                 else    /* uv-plane data rate */
2980                         return (width / 2) * (height / 2) *
2981                                 drm_format_plane_cpp(fb->pixel_format, 1);
2982         }
2983
2984         /* for packed formats */
2985         return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
2986 }
2987
2988 /*
2989  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2990  * a 8192x4096@32bpp framebuffer:
2991  *   3 * 4096 * 8192  * 4 < 2^32
2992  */
2993 static unsigned int
2994 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2995 {
2996         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2997         struct drm_device *dev = intel_crtc->base.dev;
2998         const struct intel_plane *intel_plane;
2999         unsigned int total_data_rate = 0;
3000
3001         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3002                 const struct drm_plane_state *pstate = intel_plane->base.state;
3003
3004                 if (pstate->fb == NULL)
3005                         continue;
3006
3007                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3008                         continue;
3009
3010                 /* packed/uv */
3011                 total_data_rate += skl_plane_relative_data_rate(cstate,
3012                                                                 pstate,
3013                                                                 0);
3014
3015                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
3016                         /* y-plane */
3017                         total_data_rate += skl_plane_relative_data_rate(cstate,
3018                                                                         pstate,
3019                                                                         1);
3020         }
3021
3022         return total_data_rate;
3023 }
3024
3025 static void
3026 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3027                       struct skl_ddb_allocation *ddb /* out */)
3028 {
3029         struct drm_crtc *crtc = cstate->base.crtc;
3030         struct drm_device *dev = crtc->dev;
3031         struct drm_i915_private *dev_priv = to_i915(dev);
3032         struct intel_wm_config *config = &dev_priv->wm.config;
3033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034         struct intel_plane *intel_plane;
3035         enum pipe pipe = intel_crtc->pipe;
3036         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3037         uint16_t alloc_size, start, cursor_blocks;
3038         uint16_t minimum[I915_MAX_PLANES];
3039         uint16_t y_minimum[I915_MAX_PLANES];
3040         unsigned int total_data_rate;
3041
3042         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3043         alloc_size = skl_ddb_entry_size(alloc);
3044         if (alloc_size == 0) {
3045                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3046                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3047                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3048                 return;
3049         }
3050
3051         cursor_blocks = skl_cursor_allocation(config);
3052         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3053         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3054
3055         alloc_size -= cursor_blocks;
3056         alloc->end -= cursor_blocks;
3057
3058         /* 1. Allocate the mininum required blocks for each active plane */
3059         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3060                 struct drm_plane *plane = &intel_plane->base;
3061                 struct drm_framebuffer *fb = plane->state->fb;
3062                 int id = skl_wm_plane_id(intel_plane);
3063
3064                 if (!to_intel_plane_state(plane->state)->visible)
3065                         continue;
3066
3067                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3068                         continue;
3069
3070                 minimum[id] = 8;
3071                 alloc_size -= minimum[id];
3072                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3073                 alloc_size -= y_minimum[id];
3074         }
3075
3076         /*
3077          * 2. Distribute the remaining space in proportion to the amount of
3078          * data each plane needs to fetch from memory.
3079          *
3080          * FIXME: we may not allocate every single block here.
3081          */
3082         total_data_rate = skl_get_total_relative_data_rate(cstate);
3083
3084         start = alloc->start;
3085         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3086                 struct drm_plane *plane = &intel_plane->base;
3087                 struct drm_plane_state *pstate = intel_plane->base.state;
3088                 unsigned int data_rate, y_data_rate;
3089                 uint16_t plane_blocks, y_plane_blocks = 0;
3090                 int id = skl_wm_plane_id(intel_plane);
3091
3092                 if (!to_intel_plane_state(pstate)->visible)
3093                         continue;
3094                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3095                         continue;
3096
3097                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3098
3099                 /*
3100                  * allocation for (packed formats) or (uv-plane part of planar format):
3101                  * promote the expression to 64 bits to avoid overflowing, the
3102                  * result is < available as data_rate / total_data_rate < 1
3103                  */
3104                 plane_blocks = minimum[id];
3105                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3106                                         total_data_rate);
3107
3108                 ddb->plane[pipe][id].start = start;
3109                 ddb->plane[pipe][id].end = start + plane_blocks;
3110
3111                 start += plane_blocks;
3112
3113                 /*
3114                  * allocation for y_plane part of planar format:
3115                  */
3116                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3117                         y_data_rate = skl_plane_relative_data_rate(cstate,
3118                                                                    pstate,
3119                                                                    1);
3120                         y_plane_blocks = y_minimum[id];
3121                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3122                                                 total_data_rate);
3123
3124                         ddb->y_plane[pipe][id].start = start;
3125                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3126
3127                         start += y_plane_blocks;
3128                 }
3129
3130         }
3131
3132 }
3133
3134 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3135 {
3136         /* TODO: Take into account the scalers once we support them */
3137         return config->base.adjusted_mode.crtc_clock;
3138 }
3139
3140 /*
3141  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3142  * for the read latency) and cpp should always be <= 8, so that
3143  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3144  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3145 */
3146 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3147 {
3148         uint32_t wm_intermediate_val, ret;
3149
3150         if (latency == 0)
3151                 return UINT_MAX;
3152
3153         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3154         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3155
3156         return ret;
3157 }
3158
3159 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3160                                uint32_t horiz_pixels, uint8_t cpp,
3161                                uint64_t tiling, uint32_t latency)
3162 {
3163         uint32_t ret;
3164         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3165         uint32_t wm_intermediate_val;
3166
3167         if (latency == 0)
3168                 return UINT_MAX;
3169
3170         plane_bytes_per_line = horiz_pixels * cpp;
3171
3172         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3173             tiling == I915_FORMAT_MOD_Yf_TILED) {
3174                 plane_bytes_per_line *= 4;
3175                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3176                 plane_blocks_per_line /= 4;
3177         } else {
3178                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3179         }
3180
3181         wm_intermediate_val = latency * pixel_rate;
3182         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3183                                 plane_blocks_per_line;
3184
3185         return ret;
3186 }
3187
3188 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3189                                        const struct intel_crtc *intel_crtc)
3190 {
3191         struct drm_device *dev = intel_crtc->base.dev;
3192         struct drm_i915_private *dev_priv = dev->dev_private;
3193         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3194
3195         /*
3196          * If ddb allocation of pipes changed, it may require recalculation of
3197          * watermarks
3198          */
3199         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3200                 return true;
3201
3202         return false;
3203 }
3204
3205 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3206                                  struct intel_crtc_state *cstate,
3207                                  struct intel_plane *intel_plane,
3208                                  uint16_t ddb_allocation,
3209                                  int level,
3210                                  uint16_t *out_blocks, /* out */
3211                                  uint8_t *out_lines /* out */)
3212 {
3213         struct drm_plane *plane = &intel_plane->base;
3214         struct drm_framebuffer *fb = plane->state->fb;
3215         struct intel_plane_state *intel_pstate =
3216                                         to_intel_plane_state(plane->state);
3217         uint32_t latency = dev_priv->wm.skl_latency[level];
3218         uint32_t method1, method2;
3219         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3220         uint32_t res_blocks, res_lines;
3221         uint32_t selected_result;
3222         uint8_t cpp;
3223         uint32_t width = 0, height = 0;
3224
3225         if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
3226                 return false;
3227
3228         width = drm_rect_width(&intel_pstate->src) >> 16;
3229         height = drm_rect_height(&intel_pstate->src) >> 16;
3230
3231         if (intel_rotation_90_or_270(plane->state->rotation))
3232                 swap(width, height);
3233
3234         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3235         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3236                                  cpp, latency);
3237         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3238                                  cstate->base.adjusted_mode.crtc_htotal,
3239                                  width,
3240                                  cpp,
3241                                  fb->modifier[0],
3242                                  latency);
3243
3244         plane_bytes_per_line = width * cpp;
3245         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3246
3247         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3248             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3249                 uint32_t min_scanlines = 4;
3250                 uint32_t y_tile_minimum;
3251                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3252                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3253                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3254                                 drm_format_plane_cpp(fb->pixel_format, 0);
3255
3256                         switch (cpp) {
3257                         case 1:
3258                                 min_scanlines = 16;
3259                                 break;
3260                         case 2:
3261                                 min_scanlines = 8;
3262                                 break;
3263                         case 8:
3264                                 WARN(1, "Unsupported pixel depth for rotation");
3265                         }
3266                 }
3267                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3268                 selected_result = max(method2, y_tile_minimum);
3269         } else {
3270                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3271                         selected_result = min(method1, method2);
3272                 else
3273                         selected_result = method1;
3274         }
3275
3276         res_blocks = selected_result + 1;
3277         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3278
3279         if (level >= 1 && level <= 7) {
3280                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3281                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3282                         res_lines += 4;
3283                 else
3284                         res_blocks++;
3285         }
3286
3287         if (res_blocks >= ddb_allocation || res_lines > 31)
3288                 return false;
3289
3290         *out_blocks = res_blocks;
3291         *out_lines = res_lines;
3292
3293         return true;
3294 }
3295
3296 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3297                                  struct skl_ddb_allocation *ddb,
3298                                  struct intel_crtc_state *cstate,
3299                                  int level,
3300                                  struct skl_wm_level *result)
3301 {
3302         struct drm_device *dev = dev_priv->dev;
3303         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3304         struct intel_plane *intel_plane;
3305         uint16_t ddb_blocks;
3306         enum pipe pipe = intel_crtc->pipe;
3307
3308         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3309                 int i = skl_wm_plane_id(intel_plane);
3310
3311                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3312
3313                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3314                                                 cstate,
3315                                                 intel_plane,
3316                                                 ddb_blocks,
3317                                                 level,
3318                                                 &result->plane_res_b[i],
3319                                                 &result->plane_res_l[i]);
3320         }
3321 }
3322
3323 static uint32_t
3324 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3325 {
3326         if (!cstate->base.active)
3327                 return 0;
3328
3329         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3330                 return 0;
3331
3332         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3333                             skl_pipe_pixel_rate(cstate));
3334 }
3335
3336 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3337                                       struct skl_wm_level *trans_wm /* out */)
3338 {
3339         struct drm_crtc *crtc = cstate->base.crtc;
3340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341         struct intel_plane *intel_plane;
3342
3343         if (!cstate->base.active)
3344                 return;
3345
3346         /* Until we know more, just disable transition WMs */
3347         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3348                 int i = skl_wm_plane_id(intel_plane);
3349
3350                 trans_wm->plane_en[i] = false;
3351         }
3352 }
3353
3354 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3355                                 struct skl_ddb_allocation *ddb,
3356                                 struct skl_pipe_wm *pipe_wm)
3357 {
3358         struct drm_device *dev = cstate->base.crtc->dev;
3359         const struct drm_i915_private *dev_priv = dev->dev_private;
3360         int level, max_level = ilk_wm_max_level(dev);
3361
3362         for (level = 0; level <= max_level; level++) {
3363                 skl_compute_wm_level(dev_priv, ddb, cstate,
3364                                      level, &pipe_wm->wm[level]);
3365         }
3366         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3367
3368         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3369 }
3370
3371 static void skl_compute_wm_results(struct drm_device *dev,
3372                                    struct skl_pipe_wm *p_wm,
3373                                    struct skl_wm_values *r,
3374                                    struct intel_crtc *intel_crtc)
3375 {
3376         int level, max_level = ilk_wm_max_level(dev);
3377         enum pipe pipe = intel_crtc->pipe;
3378         uint32_t temp;
3379         int i;
3380
3381         for (level = 0; level <= max_level; level++) {
3382                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3383                         temp = 0;
3384
3385                         temp |= p_wm->wm[level].plane_res_l[i] <<
3386                                         PLANE_WM_LINES_SHIFT;
3387                         temp |= p_wm->wm[level].plane_res_b[i];
3388                         if (p_wm->wm[level].plane_en[i])
3389                                 temp |= PLANE_WM_EN;
3390
3391                         r->plane[pipe][i][level] = temp;
3392                 }
3393
3394                 temp = 0;
3395
3396                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3397                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3398
3399                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3400                         temp |= PLANE_WM_EN;
3401
3402                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3403
3404         }
3405
3406         /* transition WMs */
3407         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3408                 temp = 0;
3409                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3410                 temp |= p_wm->trans_wm.plane_res_b[i];
3411                 if (p_wm->trans_wm.plane_en[i])
3412                         temp |= PLANE_WM_EN;
3413
3414                 r->plane_trans[pipe][i] = temp;
3415         }
3416
3417         temp = 0;
3418         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3419         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3420         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3421                 temp |= PLANE_WM_EN;
3422
3423         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3424
3425         r->wm_linetime[pipe] = p_wm->linetime;
3426 }
3427
3428 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3429                                 i915_reg_t reg,
3430                                 const struct skl_ddb_entry *entry)
3431 {
3432         if (entry->end)
3433                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3434         else
3435                 I915_WRITE(reg, 0);
3436 }
3437
3438 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3439                                 const struct skl_wm_values *new)
3440 {
3441         struct drm_device *dev = dev_priv->dev;
3442         struct intel_crtc *crtc;
3443
3444         for_each_intel_crtc(dev, crtc) {
3445                 int i, level, max_level = ilk_wm_max_level(dev);
3446                 enum pipe pipe = crtc->pipe;
3447
3448                 if (!new->dirty[pipe])
3449                         continue;
3450
3451                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3452
3453                 for (level = 0; level <= max_level; level++) {
3454                         for (i = 0; i < intel_num_planes(crtc); i++)
3455                                 I915_WRITE(PLANE_WM(pipe, i, level),
3456                                            new->plane[pipe][i][level]);
3457                         I915_WRITE(CUR_WM(pipe, level),
3458                                    new->plane[pipe][PLANE_CURSOR][level]);
3459                 }
3460                 for (i = 0; i < intel_num_planes(crtc); i++)
3461                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3462                                    new->plane_trans[pipe][i]);
3463                 I915_WRITE(CUR_WM_TRANS(pipe),
3464                            new->plane_trans[pipe][PLANE_CURSOR]);
3465
3466                 for (i = 0; i < intel_num_planes(crtc); i++) {
3467                         skl_ddb_entry_write(dev_priv,
3468                                             PLANE_BUF_CFG(pipe, i),
3469                                             &new->ddb.plane[pipe][i]);
3470                         skl_ddb_entry_write(dev_priv,
3471                                             PLANE_NV12_BUF_CFG(pipe, i),
3472                                             &new->ddb.y_plane[pipe][i]);
3473                 }
3474
3475                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3476                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3477         }
3478 }
3479
3480 /*
3481  * When setting up a new DDB allocation arrangement, we need to correctly
3482  * sequence the times at which the new allocations for the pipes are taken into
3483  * account or we'll have pipes fetching from space previously allocated to
3484  * another pipe.
3485  *
3486  * Roughly the sequence looks like:
3487  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3488  *     overlapping with a previous light-up pipe (another way to put it is:
3489  *     pipes with their new allocation strickly included into their old ones).
3490  *  2. re-allocate the other pipes that get their allocation reduced
3491  *  3. allocate the pipes having their allocation increased
3492  *
3493  * Steps 1. and 2. are here to take care of the following case:
3494  * - Initially DDB looks like this:
3495  *     |   B    |   C    |
3496  * - enable pipe A.
3497  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3498  *   allocation
3499  *     |  A  |  B  |  C  |
3500  *
3501  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3502  */
3503
3504 static void
3505 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3506 {
3507         int plane;
3508
3509         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3510
3511         for_each_plane(dev_priv, pipe, plane) {
3512                 I915_WRITE(PLANE_SURF(pipe, plane),
3513                            I915_READ(PLANE_SURF(pipe, plane)));
3514         }
3515         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3516 }
3517
3518 static bool
3519 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3520                             const struct skl_ddb_allocation *new,
3521                             enum pipe pipe)
3522 {
3523         uint16_t old_size, new_size;
3524
3525         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3526         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3527
3528         return old_size != new_size &&
3529                new->pipe[pipe].start >= old->pipe[pipe].start &&
3530                new->pipe[pipe].end <= old->pipe[pipe].end;
3531 }
3532
3533 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3534                                 struct skl_wm_values *new_values)
3535 {
3536         struct drm_device *dev = dev_priv->dev;
3537         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3538         bool reallocated[I915_MAX_PIPES] = {};
3539         struct intel_crtc *crtc;
3540         enum pipe pipe;
3541
3542         new_ddb = &new_values->ddb;
3543         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3544
3545         /*
3546          * First pass: flush the pipes with the new allocation contained into
3547          * the old space.
3548          *
3549          * We'll wait for the vblank on those pipes to ensure we can safely
3550          * re-allocate the freed space without this pipe fetching from it.
3551          */
3552         for_each_intel_crtc(dev, crtc) {
3553                 if (!crtc->active)
3554                         continue;
3555
3556                 pipe = crtc->pipe;
3557
3558                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3559                         continue;
3560
3561                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3562                 intel_wait_for_vblank(dev, pipe);
3563
3564                 reallocated[pipe] = true;
3565         }
3566
3567
3568         /*
3569          * Second pass: flush the pipes that are having their allocation
3570          * reduced, but overlapping with a previous allocation.
3571          *
3572          * Here as well we need to wait for the vblank to make sure the freed
3573          * space is not used anymore.
3574          */
3575         for_each_intel_crtc(dev, crtc) {
3576                 if (!crtc->active)
3577                         continue;
3578
3579                 pipe = crtc->pipe;
3580
3581                 if (reallocated[pipe])
3582                         continue;
3583
3584                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3585                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3586                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3587                         intel_wait_for_vblank(dev, pipe);
3588                         reallocated[pipe] = true;
3589                 }
3590         }
3591
3592         /*
3593          * Third pass: flush the pipes that got more space allocated.
3594          *
3595          * We don't need to actively wait for the update here, next vblank
3596          * will just get more DDB space with the correct WM values.
3597          */
3598         for_each_intel_crtc(dev, crtc) {
3599                 if (!crtc->active)
3600                         continue;
3601
3602                 pipe = crtc->pipe;
3603
3604                 /*
3605                  * At this point, only the pipes more space than before are
3606                  * left to re-allocate.
3607                  */
3608                 if (reallocated[pipe])
3609                         continue;
3610
3611                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3612         }
3613 }
3614
3615 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3616                                struct skl_ddb_allocation *ddb, /* out */
3617                                struct skl_pipe_wm *pipe_wm /* out */)
3618 {
3619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3621
3622         skl_allocate_pipe_ddb(cstate, ddb);
3623         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3624
3625         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3626                 return false;
3627
3628         intel_crtc->wm.active.skl = *pipe_wm;
3629
3630         return true;
3631 }
3632
3633 static void skl_update_other_pipe_wm(struct drm_device *dev,
3634                                      struct drm_crtc *crtc,
3635                                      struct skl_wm_values *r)
3636 {
3637         struct intel_crtc *intel_crtc;
3638         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3639
3640         /*
3641          * If the WM update hasn't changed the allocation for this_crtc (the
3642          * crtc we are currently computing the new WM values for), other
3643          * enabled crtcs will keep the same allocation and we don't need to
3644          * recompute anything for them.
3645          */
3646         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3647                 return;
3648
3649         /*
3650          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3651          * other active pipes need new DDB allocation and WM values.
3652          */
3653         for_each_intel_crtc(dev, intel_crtc) {
3654                 struct skl_pipe_wm pipe_wm = {};
3655                 bool wm_changed;
3656
3657                 if (this_crtc->pipe == intel_crtc->pipe)
3658                         continue;
3659
3660                 if (!intel_crtc->active)
3661                         continue;
3662
3663                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3664                                                 &r->ddb, &pipe_wm);
3665
3666                 /*
3667                  * If we end up re-computing the other pipe WM values, it's
3668                  * because it was really needed, so we expect the WM values to
3669                  * be different.
3670                  */
3671                 WARN_ON(!wm_changed);
3672
3673                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3674                 r->dirty[intel_crtc->pipe] = true;
3675         }
3676 }
3677
3678 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3679 {
3680         watermarks->wm_linetime[pipe] = 0;
3681         memset(watermarks->plane[pipe], 0,
3682                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3683         memset(watermarks->plane_trans[pipe],
3684                0, sizeof(uint32_t) * I915_MAX_PLANES);
3685         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3686
3687         /* Clear ddb entries for pipe */
3688         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3689         memset(&watermarks->ddb.plane[pipe], 0,
3690                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3691         memset(&watermarks->ddb.y_plane[pipe], 0,
3692                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3693         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3694                sizeof(struct skl_ddb_entry));
3695
3696 }
3697
3698 static void skl_update_wm(struct drm_crtc *crtc)
3699 {
3700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701         struct drm_device *dev = crtc->dev;
3702         struct drm_i915_private *dev_priv = dev->dev_private;
3703         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3704         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3705         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3706
3707
3708         /* Clear all dirty flags */
3709         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3710
3711         skl_clear_wm(results, intel_crtc->pipe);
3712
3713         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3714                 return;
3715
3716         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3717         results->dirty[intel_crtc->pipe] = true;
3718
3719         skl_update_other_pipe_wm(dev, crtc, results);
3720         skl_write_wm_values(dev_priv, results);
3721         skl_flush_wm_values(dev_priv, results);
3722
3723         /* store the new configuration */
3724         dev_priv->wm.skl_hw = *results;
3725 }
3726
3727 static void ilk_compute_wm_config(struct drm_device *dev,
3728                                   struct intel_wm_config *config)
3729 {
3730         struct intel_crtc *crtc;
3731
3732         /* Compute the currently _active_ config */
3733         for_each_intel_crtc(dev, crtc) {
3734                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3735
3736                 if (!wm->pipe_enabled)
3737                         continue;
3738
3739                 config->sprites_enabled |= wm->sprites_enabled;
3740                 config->sprites_scaled |= wm->sprites_scaled;
3741                 config->num_pipes_active++;
3742         }
3743 }
3744
3745 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3746 {
3747         struct drm_device *dev = dev_priv->dev;
3748         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3749         struct ilk_wm_maximums max;
3750         struct intel_wm_config config = {};
3751         struct ilk_wm_values results = {};
3752         enum intel_ddb_partitioning partitioning;
3753
3754         ilk_compute_wm_config(dev, &config);
3755
3756         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3757         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3758
3759         /* 5/6 split only in single pipe config on IVB+ */
3760         if (INTEL_INFO(dev)->gen >= 7 &&
3761             config.num_pipes_active == 1 && config.sprites_enabled) {
3762                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3763                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3764
3765                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3766         } else {
3767                 best_lp_wm = &lp_wm_1_2;
3768         }
3769
3770         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3771                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3772
3773         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3774
3775         ilk_write_wm_values(dev_priv, &results);
3776 }
3777
3778 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3779 {
3780         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3781         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3782
3783         mutex_lock(&dev_priv->wm.wm_mutex);
3784         intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3785         ilk_program_watermarks(dev_priv);
3786         mutex_unlock(&dev_priv->wm.wm_mutex);
3787 }
3788
3789 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3790 {
3791         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3792         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3793
3794         mutex_lock(&dev_priv->wm.wm_mutex);
3795         if (cstate->wm.need_postvbl_update) {
3796                 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3797                 ilk_program_watermarks(dev_priv);
3798         }
3799         mutex_unlock(&dev_priv->wm.wm_mutex);
3800 }
3801
3802 static void skl_pipe_wm_active_state(uint32_t val,
3803                                      struct skl_pipe_wm *active,
3804                                      bool is_transwm,
3805                                      bool is_cursor,
3806                                      int i,
3807                                      int level)
3808 {
3809         bool is_enabled = (val & PLANE_WM_EN) != 0;
3810
3811         if (!is_transwm) {
3812                 if (!is_cursor) {
3813                         active->wm[level].plane_en[i] = is_enabled;
3814                         active->wm[level].plane_res_b[i] =
3815                                         val & PLANE_WM_BLOCKS_MASK;
3816                         active->wm[level].plane_res_l[i] =
3817                                         (val >> PLANE_WM_LINES_SHIFT) &
3818                                                 PLANE_WM_LINES_MASK;
3819                 } else {
3820                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3821                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3822                                         val & PLANE_WM_BLOCKS_MASK;
3823                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3824                                         (val >> PLANE_WM_LINES_SHIFT) &
3825                                                 PLANE_WM_LINES_MASK;
3826                 }
3827         } else {
3828                 if (!is_cursor) {
3829                         active->trans_wm.plane_en[i] = is_enabled;
3830                         active->trans_wm.plane_res_b[i] =
3831                                         val & PLANE_WM_BLOCKS_MASK;
3832                         active->trans_wm.plane_res_l[i] =
3833                                         (val >> PLANE_WM_LINES_SHIFT) &
3834                                                 PLANE_WM_LINES_MASK;
3835                 } else {
3836                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3837                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3838                                         val & PLANE_WM_BLOCKS_MASK;
3839                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3840                                         (val >> PLANE_WM_LINES_SHIFT) &
3841                                                 PLANE_WM_LINES_MASK;
3842                 }
3843         }
3844 }
3845
3846 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3847 {
3848         struct drm_device *dev = crtc->dev;
3849         struct drm_i915_private *dev_priv = dev->dev_private;
3850         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3852         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3853         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3854         enum pipe pipe = intel_crtc->pipe;
3855         int level, i, max_level;
3856         uint32_t temp;
3857
3858         max_level = ilk_wm_max_level(dev);
3859
3860         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3861
3862         for (level = 0; level <= max_level; level++) {
3863                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3864                         hw->plane[pipe][i][level] =
3865                                         I915_READ(PLANE_WM(pipe, i, level));
3866                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3867         }
3868
3869         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3870                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3871         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3872
3873         if (!intel_crtc->active)
3874                 return;
3875
3876         hw->dirty[pipe] = true;
3877
3878         active->linetime = hw->wm_linetime[pipe];
3879
3880         for (level = 0; level <= max_level; level++) {
3881                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3882                         temp = hw->plane[pipe][i][level];
3883                         skl_pipe_wm_active_state(temp, active, false,
3884                                                 false, i, level);
3885                 }
3886                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3887                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3888         }
3889
3890         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3891                 temp = hw->plane_trans[pipe][i];
3892                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3893         }
3894
3895         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3896         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3897
3898         intel_crtc->wm.active.skl = *active;
3899 }
3900
3901 void skl_wm_get_hw_state(struct drm_device *dev)
3902 {
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3905         struct drm_crtc *crtc;
3906
3907         skl_ddb_get_hw_state(dev_priv, ddb);
3908         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3909                 skl_pipe_wm_get_hw_state(crtc);
3910 }
3911
3912 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3919         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3920         enum pipe pipe = intel_crtc->pipe;
3921         static const i915_reg_t wm0_pipe_reg[] = {
3922                 [PIPE_A] = WM0_PIPEA_ILK,
3923                 [PIPE_B] = WM0_PIPEB_ILK,
3924                 [PIPE_C] = WM0_PIPEC_IVB,
3925         };
3926
3927         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3928         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3929                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3930
3931         memset(active, 0, sizeof(*active));
3932
3933         active->pipe_enabled = intel_crtc->active;
3934
3935         if (active->pipe_enabled) {
3936                 u32 tmp = hw->wm_pipe[pipe];
3937
3938                 /*
3939                  * For active pipes LP0 watermark is marked as
3940                  * enabled, and LP1+ watermaks as disabled since
3941                  * we can't really reverse compute them in case
3942                  * multiple pipes are active.
3943                  */
3944                 active->wm[0].enable = true;
3945                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3946                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3947                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3948                 active->linetime = hw->wm_linetime[pipe];
3949         } else {
3950                 int level, max_level = ilk_wm_max_level(dev);
3951
3952                 /*
3953                  * For inactive pipes, all watermark levels
3954                  * should be marked as enabled but zeroed,
3955                  * which is what we'd compute them to.
3956                  */
3957                 for (level = 0; level <= max_level; level++)
3958                         active->wm[level].enable = true;
3959         }
3960
3961         intel_crtc->wm.active.ilk = *active;
3962 }
3963
3964 #define _FW_WM(value, plane) \
3965         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3966 #define _FW_WM_VLV(value, plane) \
3967         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3968
3969 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3970                                struct vlv_wm_values *wm)
3971 {
3972         enum pipe pipe;
3973         uint32_t tmp;
3974
3975         for_each_pipe(dev_priv, pipe) {
3976                 tmp = I915_READ(VLV_DDL(pipe));
3977
3978                 wm->ddl[pipe].primary =
3979                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3980                 wm->ddl[pipe].cursor =
3981                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3982                 wm->ddl[pipe].sprite[0] =
3983                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3984                 wm->ddl[pipe].sprite[1] =
3985                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3986         }
3987
3988         tmp = I915_READ(DSPFW1);
3989         wm->sr.plane = _FW_WM(tmp, SR);
3990         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3991         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3992         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3993
3994         tmp = I915_READ(DSPFW2);
3995         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3996         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3997         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3998
3999         tmp = I915_READ(DSPFW3);
4000         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4001
4002         if (IS_CHERRYVIEW(dev_priv)) {
4003                 tmp = I915_READ(DSPFW7_CHV);
4004                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4005                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4006
4007                 tmp = I915_READ(DSPFW8_CHV);
4008                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4009                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4010
4011                 tmp = I915_READ(DSPFW9_CHV);
4012                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4013                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4014
4015                 tmp = I915_READ(DSPHOWM);
4016                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4017                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4018                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4019                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4020                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4021                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4022                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4023                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4024                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4025                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4026         } else {
4027                 tmp = I915_READ(DSPFW7);
4028                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4029                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4030
4031                 tmp = I915_READ(DSPHOWM);
4032                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4033                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4034                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4035                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4036                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4037                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4038                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4039         }
4040 }
4041
4042 #undef _FW_WM
4043 #undef _FW_WM_VLV
4044
4045 void vlv_wm_get_hw_state(struct drm_device *dev)
4046 {
4047         struct drm_i915_private *dev_priv = to_i915(dev);
4048         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4049         struct intel_plane *plane;
4050         enum pipe pipe;
4051         u32 val;
4052
4053         vlv_read_wm_values(dev_priv, wm);
4054
4055         for_each_intel_plane(dev, plane) {
4056                 switch (plane->base.type) {
4057                         int sprite;
4058                 case DRM_PLANE_TYPE_CURSOR:
4059                         plane->wm.fifo_size = 63;
4060                         break;
4061                 case DRM_PLANE_TYPE_PRIMARY:
4062                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4063                         break;
4064                 case DRM_PLANE_TYPE_OVERLAY:
4065                         sprite = plane->plane;
4066                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4067                         break;
4068                 }
4069         }
4070
4071         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4072         wm->level = VLV_WM_LEVEL_PM2;
4073
4074         if (IS_CHERRYVIEW(dev_priv)) {
4075                 mutex_lock(&dev_priv->rps.hw_lock);
4076
4077                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4078                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4079                         wm->level = VLV_WM_LEVEL_PM5;
4080
4081                 /*
4082                  * If DDR DVFS is disabled in the BIOS, Punit
4083                  * will never ack the request. So if that happens
4084                  * assume we don't have to enable/disable DDR DVFS
4085                  * dynamically. To test that just set the REQ_ACK
4086                  * bit to poke the Punit, but don't change the
4087                  * HIGH/LOW bits so that we don't actually change
4088                  * the current state.
4089                  */
4090                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4091                 val |= FORCE_DDR_FREQ_REQ_ACK;
4092                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4093
4094                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4095                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4096                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4097                                       "assuming DDR DVFS is disabled\n");
4098                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4099                 } else {
4100                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4101                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4102                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4103                 }
4104
4105                 mutex_unlock(&dev_priv->rps.hw_lock);
4106         }
4107
4108         for_each_pipe(dev_priv, pipe)
4109                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4110                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4111                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4112
4113         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4114                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4115 }
4116
4117 void ilk_wm_get_hw_state(struct drm_device *dev)
4118 {
4119         struct drm_i915_private *dev_priv = dev->dev_private;
4120         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4121         struct drm_crtc *crtc;
4122
4123         for_each_crtc(dev, crtc)
4124                 ilk_pipe_wm_get_hw_state(crtc);
4125
4126         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4127         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4128         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4129
4130         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4131         if (INTEL_INFO(dev)->gen >= 7) {
4132                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4133                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4134         }
4135
4136         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4137                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4138                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4139         else if (IS_IVYBRIDGE(dev))
4140                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4141                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4142
4143         hw->enable_fbc_wm =
4144                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4145 }
4146
4147 /**
4148  * intel_update_watermarks - update FIFO watermark values based on current modes
4149  *
4150  * Calculate watermark values for the various WM regs based on current mode
4151  * and plane configuration.
4152  *
4153  * There are several cases to deal with here:
4154  *   - normal (i.e. non-self-refresh)
4155  *   - self-refresh (SR) mode
4156  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4157  *   - lines are small relative to FIFO size (buffer can hold more than 2
4158  *     lines), so need to account for TLB latency
4159  *
4160  *   The normal calculation is:
4161  *     watermark = dotclock * bytes per pixel * latency
4162  *   where latency is platform & configuration dependent (we assume pessimal
4163  *   values here).
4164  *
4165  *   The SR calculation is:
4166  *     watermark = (trunc(latency/line time)+1) * surface width *
4167  *       bytes per pixel
4168  *   where
4169  *     line time = htotal / dotclock
4170  *     surface width = hdisplay for normal plane and 64 for cursor
4171  *   and latency is assumed to be high, as above.
4172  *
4173  * The final value programmed to the register should always be rounded up,
4174  * and include an extra 2 entries to account for clock crossings.
4175  *
4176  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4177  * to set the non-SR watermarks to 8.
4178  */
4179 void intel_update_watermarks(struct drm_crtc *crtc)
4180 {
4181         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4182
4183         if (dev_priv->display.update_wm)
4184                 dev_priv->display.update_wm(crtc);
4185 }
4186
4187 /*
4188  * Lock protecting IPS related data structures
4189  */
4190 DEFINE_SPINLOCK(mchdev_lock);
4191
4192 /* Global for IPS driver to get at the current i915 device. Protected by
4193  * mchdev_lock. */
4194 static struct drm_i915_private *i915_mch_dev;
4195
4196 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4197 {
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199         u16 rgvswctl;
4200
4201         assert_spin_locked(&mchdev_lock);
4202
4203         rgvswctl = I915_READ16(MEMSWCTL);
4204         if (rgvswctl & MEMCTL_CMD_STS) {
4205                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4206                 return false; /* still busy with another command */
4207         }
4208
4209         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4210                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4211         I915_WRITE16(MEMSWCTL, rgvswctl);
4212         POSTING_READ16(MEMSWCTL);
4213
4214         rgvswctl |= MEMCTL_CMD_STS;
4215         I915_WRITE16(MEMSWCTL, rgvswctl);
4216
4217         return true;
4218 }
4219
4220 static void ironlake_enable_drps(struct drm_device *dev)
4221 {
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         u32 rgvmodectl;
4224         u8 fmax, fmin, fstart, vstart;
4225
4226         spin_lock_irq(&mchdev_lock);
4227
4228         rgvmodectl = I915_READ(MEMMODECTL);
4229
4230         /* Enable temp reporting */
4231         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4232         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4233
4234         /* 100ms RC evaluation intervals */
4235         I915_WRITE(RCUPEI, 100000);
4236         I915_WRITE(RCDNEI, 100000);
4237
4238         /* Set max/min thresholds to 90ms and 80ms respectively */
4239         I915_WRITE(RCBMAXAVG, 90000);
4240         I915_WRITE(RCBMINAVG, 80000);
4241
4242         I915_WRITE(MEMIHYST, 1);
4243
4244         /* Set up min, max, and cur for interrupt handling */
4245         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4246         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4247         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4248                 MEMMODE_FSTART_SHIFT;
4249
4250         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4251                 PXVFREQ_PX_SHIFT;
4252
4253         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4254         dev_priv->ips.fstart = fstart;
4255
4256         dev_priv->ips.max_delay = fstart;
4257         dev_priv->ips.min_delay = fmin;
4258         dev_priv->ips.cur_delay = fstart;
4259
4260         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4261                          fmax, fmin, fstart);
4262
4263         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4264
4265         /*
4266          * Interrupts will be enabled in ironlake_irq_postinstall
4267          */
4268
4269         I915_WRITE(VIDSTART, vstart);
4270         POSTING_READ(VIDSTART);
4271
4272         rgvmodectl |= MEMMODE_SWMODE_EN;
4273         I915_WRITE(MEMMODECTL, rgvmodectl);
4274
4275         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4276                 DRM_ERROR("stuck trying to change perf mode\n");
4277         mdelay(1);
4278
4279         ironlake_set_drps(dev, fstart);
4280
4281         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4282                 I915_READ(DDREC) + I915_READ(CSIEC);
4283         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4284         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4285         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4286
4287         spin_unlock_irq(&mchdev_lock);
4288 }
4289
4290 static void ironlake_disable_drps(struct drm_device *dev)
4291 {
4292         struct drm_i915_private *dev_priv = dev->dev_private;
4293         u16 rgvswctl;
4294
4295         spin_lock_irq(&mchdev_lock);
4296
4297         rgvswctl = I915_READ16(MEMSWCTL);
4298
4299         /* Ack interrupts, disable EFC interrupt */
4300         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4301         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4302         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4303         I915_WRITE(DEIIR, DE_PCU_EVENT);
4304         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4305
4306         /* Go back to the starting frequency */
4307         ironlake_set_drps(dev, dev_priv->ips.fstart);
4308         mdelay(1);
4309         rgvswctl |= MEMCTL_CMD_STS;
4310         I915_WRITE(MEMSWCTL, rgvswctl);
4311         mdelay(1);
4312
4313         spin_unlock_irq(&mchdev_lock);
4314 }
4315
4316 /* There's a funny hw issue where the hw returns all 0 when reading from
4317  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4318  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4319  * all limits and the gpu stuck at whatever frequency it is at atm).
4320  */
4321 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4322 {
4323         u32 limits;
4324
4325         /* Only set the down limit when we've reached the lowest level to avoid
4326          * getting more interrupts, otherwise leave this clear. This prevents a
4327          * race in the hw when coming out of rc6: There's a tiny window where
4328          * the hw runs at the minimal clock before selecting the desired
4329          * frequency, if the down threshold expires in that window we will not
4330          * receive a down interrupt. */
4331         if (IS_GEN9(dev_priv)) {
4332                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4333                 if (val <= dev_priv->rps.min_freq_softlimit)
4334                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4335         } else {
4336                 limits = dev_priv->rps.max_freq_softlimit << 24;
4337                 if (val <= dev_priv->rps.min_freq_softlimit)
4338                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4339         }
4340
4341         return limits;
4342 }
4343
4344 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4345 {
4346         int new_power;
4347         u32 threshold_up = 0, threshold_down = 0; /* in % */
4348         u32 ei_up = 0, ei_down = 0;
4349
4350         new_power = dev_priv->rps.power;
4351         switch (dev_priv->rps.power) {
4352         case LOW_POWER:
4353                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4354                         new_power = BETWEEN;
4355                 break;
4356
4357         case BETWEEN:
4358                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4359                         new_power = LOW_POWER;
4360                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4361                         new_power = HIGH_POWER;
4362                 break;
4363
4364         case HIGH_POWER:
4365                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4366                         new_power = BETWEEN;
4367                 break;
4368         }
4369         /* Max/min bins are special */
4370         if (val <= dev_priv->rps.min_freq_softlimit)
4371                 new_power = LOW_POWER;
4372         if (val >= dev_priv->rps.max_freq_softlimit)
4373                 new_power = HIGH_POWER;
4374         if (new_power == dev_priv->rps.power)
4375                 return;
4376
4377         /* Note the units here are not exactly 1us, but 1280ns. */
4378         switch (new_power) {
4379         case LOW_POWER:
4380                 /* Upclock if more than 95% busy over 16ms */
4381                 ei_up = 16000;
4382                 threshold_up = 95;
4383
4384                 /* Downclock if less than 85% busy over 32ms */
4385                 ei_down = 32000;
4386                 threshold_down = 85;
4387                 break;
4388
4389         case BETWEEN:
4390                 /* Upclock if more than 90% busy over 13ms */
4391                 ei_up = 13000;
4392                 threshold_up = 90;
4393
4394                 /* Downclock if less than 75% busy over 32ms */
4395                 ei_down = 32000;
4396                 threshold_down = 75;
4397                 break;
4398
4399         case HIGH_POWER:
4400                 /* Upclock if more than 85% busy over 10ms */
4401                 ei_up = 10000;
4402                 threshold_up = 85;
4403
4404                 /* Downclock if less than 60% busy over 32ms */
4405                 ei_down = 32000;
4406                 threshold_down = 60;
4407                 break;
4408         }
4409
4410         I915_WRITE(GEN6_RP_UP_EI,
4411                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4412         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4413                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4414
4415         I915_WRITE(GEN6_RP_DOWN_EI,
4416                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4417         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4418                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4419
4420          I915_WRITE(GEN6_RP_CONTROL,
4421                     GEN6_RP_MEDIA_TURBO |
4422                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4423                     GEN6_RP_MEDIA_IS_GFX |
4424                     GEN6_RP_ENABLE |
4425                     GEN6_RP_UP_BUSY_AVG |
4426                     GEN6_RP_DOWN_IDLE_AVG);
4427
4428         dev_priv->rps.power = new_power;
4429         dev_priv->rps.up_threshold = threshold_up;
4430         dev_priv->rps.down_threshold = threshold_down;
4431         dev_priv->rps.last_adj = 0;
4432 }
4433
4434 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4435 {
4436         u32 mask = 0;
4437
4438         if (val > dev_priv->rps.min_freq_softlimit)
4439                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4440         if (val < dev_priv->rps.max_freq_softlimit)
4441                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4442
4443         mask &= dev_priv->pm_rps_events;
4444
4445         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4446 }
4447
4448 /* gen6_set_rps is called to update the frequency request, but should also be
4449  * called when the range (min_delay and max_delay) is modified so that we can
4450  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4451 static void gen6_set_rps(struct drm_device *dev, u8 val)
4452 {
4453         struct drm_i915_private *dev_priv = dev->dev_private;
4454
4455         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4456         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4457                 return;
4458
4459         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4460         WARN_ON(val > dev_priv->rps.max_freq);
4461         WARN_ON(val < dev_priv->rps.min_freq);
4462
4463         /* min/max delay may still have been modified so be sure to
4464          * write the limits value.
4465          */
4466         if (val != dev_priv->rps.cur_freq) {
4467                 gen6_set_rps_thresholds(dev_priv, val);
4468
4469                 if (IS_GEN9(dev))
4470                         I915_WRITE(GEN6_RPNSWREQ,
4471                                    GEN9_FREQUENCY(val));
4472                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4473                         I915_WRITE(GEN6_RPNSWREQ,
4474                                    HSW_FREQUENCY(val));
4475                 else
4476                         I915_WRITE(GEN6_RPNSWREQ,
4477                                    GEN6_FREQUENCY(val) |
4478                                    GEN6_OFFSET(0) |
4479                                    GEN6_AGGRESSIVE_TURBO);
4480         }
4481
4482         /* Make sure we continue to get interrupts
4483          * until we hit the minimum or maximum frequencies.
4484          */
4485         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4486         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4487
4488         POSTING_READ(GEN6_RPNSWREQ);
4489
4490         dev_priv->rps.cur_freq = val;
4491         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4492 }
4493
4494 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4495 {
4496         struct drm_i915_private *dev_priv = dev->dev_private;
4497
4498         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4499         WARN_ON(val > dev_priv->rps.max_freq);
4500         WARN_ON(val < dev_priv->rps.min_freq);
4501
4502         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4503                       "Odd GPU freq value\n"))
4504                 val &= ~1;
4505
4506         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4507
4508         if (val != dev_priv->rps.cur_freq) {
4509                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4510                 if (!IS_CHERRYVIEW(dev_priv))
4511                         gen6_set_rps_thresholds(dev_priv, val);
4512         }
4513
4514         dev_priv->rps.cur_freq = val;
4515         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4516 }
4517
4518 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4519  *
4520  * * If Gfx is Idle, then
4521  * 1. Forcewake Media well.
4522  * 2. Request idle freq.
4523  * 3. Release Forcewake of Media well.
4524 */
4525 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4526 {
4527         u32 val = dev_priv->rps.idle_freq;
4528
4529         if (dev_priv->rps.cur_freq <= val)
4530                 return;
4531
4532         /* Wake up the media well, as that takes a lot less
4533          * power than the Render well. */
4534         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4535         valleyview_set_rps(dev_priv->dev, val);
4536         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4537 }
4538
4539 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4540 {
4541         mutex_lock(&dev_priv->rps.hw_lock);
4542         if (dev_priv->rps.enabled) {
4543                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4544                         gen6_rps_reset_ei(dev_priv);
4545                 I915_WRITE(GEN6_PMINTRMSK,
4546                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4547         }
4548         mutex_unlock(&dev_priv->rps.hw_lock);
4549 }
4550
4551 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4552 {
4553         struct drm_device *dev = dev_priv->dev;
4554
4555         mutex_lock(&dev_priv->rps.hw_lock);
4556         if (dev_priv->rps.enabled) {
4557                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4558                         vlv_set_rps_idle(dev_priv);
4559                 else
4560                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4561                 dev_priv->rps.last_adj = 0;
4562                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4563         }
4564         mutex_unlock(&dev_priv->rps.hw_lock);
4565
4566         spin_lock(&dev_priv->rps.client_lock);
4567         while (!list_empty(&dev_priv->rps.clients))
4568                 list_del_init(dev_priv->rps.clients.next);
4569         spin_unlock(&dev_priv->rps.client_lock);
4570 }
4571
4572 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4573                     struct intel_rps_client *rps,
4574                     unsigned long submitted)
4575 {
4576         /* This is intentionally racy! We peek at the state here, then
4577          * validate inside the RPS worker.
4578          */
4579         if (!(dev_priv->mm.busy &&
4580               dev_priv->rps.enabled &&
4581               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4582                 return;
4583
4584         /* Force a RPS boost (and don't count it against the client) if
4585          * the GPU is severely congested.
4586          */
4587         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4588                 rps = NULL;
4589
4590         spin_lock(&dev_priv->rps.client_lock);
4591         if (rps == NULL || list_empty(&rps->link)) {
4592                 spin_lock_irq(&dev_priv->irq_lock);
4593                 if (dev_priv->rps.interrupts_enabled) {
4594                         dev_priv->rps.client_boost = true;
4595                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4596                 }
4597                 spin_unlock_irq(&dev_priv->irq_lock);
4598
4599                 if (rps != NULL) {
4600                         list_add(&rps->link, &dev_priv->rps.clients);
4601                         rps->boosts++;
4602                 } else
4603                         dev_priv->rps.boosts++;
4604         }
4605         spin_unlock(&dev_priv->rps.client_lock);
4606 }
4607
4608 void intel_set_rps(struct drm_device *dev, u8 val)
4609 {
4610         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4611                 valleyview_set_rps(dev, val);
4612         else
4613                 gen6_set_rps(dev, val);
4614 }
4615
4616 static void gen9_disable_rc6(struct drm_device *dev)
4617 {
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619
4620         I915_WRITE(GEN6_RC_CONTROL, 0);
4621         I915_WRITE(GEN9_PG_ENABLE, 0);
4622 }
4623
4624 static void gen9_disable_rps(struct drm_device *dev)
4625 {
4626         struct drm_i915_private *dev_priv = dev->dev_private;
4627
4628         I915_WRITE(GEN6_RP_CONTROL, 0);
4629 }
4630
4631 static void gen6_disable_rps(struct drm_device *dev)
4632 {
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635         I915_WRITE(GEN6_RC_CONTROL, 0);
4636         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4637         I915_WRITE(GEN6_RP_CONTROL, 0);
4638 }
4639
4640 static void cherryview_disable_rps(struct drm_device *dev)
4641 {
4642         struct drm_i915_private *dev_priv = dev->dev_private;
4643
4644         I915_WRITE(GEN6_RC_CONTROL, 0);
4645 }
4646
4647 static void valleyview_disable_rps(struct drm_device *dev)
4648 {
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650
4651         /* we're doing forcewake before Disabling RC6,
4652          * This what the BIOS expects when going into suspend */
4653         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4654
4655         I915_WRITE(GEN6_RC_CONTROL, 0);
4656
4657         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4658 }
4659
4660 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4661 {
4662         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4663                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4664                         mode = GEN6_RC_CTL_RC6_ENABLE;
4665                 else
4666                         mode = 0;
4667         }
4668         if (HAS_RC6p(dev))
4669                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4670                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4671                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4672                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4673
4674         else
4675                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4676                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4677 }
4678
4679 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4680 {
4681         struct drm_i915_private *dev_priv = to_i915(dev);
4682         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4683         bool enable_rc6 = true;
4684         unsigned long rc6_ctx_base;
4685
4686         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4687                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4688                 enable_rc6 = false;
4689         }
4690
4691         /*
4692          * The exact context size is not known for BXT, so assume a page size
4693          * for this check.
4694          */
4695         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4696         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4697               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4698                                         ggtt->stolen_reserved_size))) {
4699                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4700                 enable_rc6 = false;
4701         }
4702
4703         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4704               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4705               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4706               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4707                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4708                 enable_rc6 = false;
4709         }
4710
4711         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4712                                             GEN6_RC_CTL_HW_ENABLE)) &&
4713             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4714              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4715                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4716                 enable_rc6 = false;
4717         }
4718
4719         return enable_rc6;
4720 }
4721
4722 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4723 {
4724         /* No RC6 before Ironlake and code is gone for ilk. */
4725         if (INTEL_INFO(dev)->gen < 6)
4726                 return 0;
4727
4728         if (!enable_rc6)
4729                 return 0;
4730
4731         if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4732                 DRM_INFO("RC6 disabled by BIOS\n");
4733                 return 0;
4734         }
4735
4736         /* Respect the kernel parameter if it is set */
4737         if (enable_rc6 >= 0) {
4738                 int mask;
4739
4740                 if (HAS_RC6p(dev))
4741                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4742                                INTEL_RC6pp_ENABLE;
4743                 else
4744                         mask = INTEL_RC6_ENABLE;
4745
4746                 if ((enable_rc6 & mask) != enable_rc6)
4747                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4748                                       enable_rc6 & mask, enable_rc6, mask);
4749
4750                 return enable_rc6 & mask;
4751         }
4752
4753         if (IS_IVYBRIDGE(dev))
4754                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4755
4756         return INTEL_RC6_ENABLE;
4757 }
4758
4759 int intel_enable_rc6(const struct drm_device *dev)
4760 {
4761         return i915.enable_rc6;
4762 }
4763
4764 static void gen6_init_rps_frequencies(struct drm_device *dev)
4765 {
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767         uint32_t rp_state_cap;
4768         u32 ddcc_status = 0;
4769         int ret;
4770
4771         /* All of these values are in units of 50MHz */
4772         dev_priv->rps.cur_freq          = 0;
4773         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4774         if (IS_BROXTON(dev)) {
4775                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4776                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4777                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4778                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4779         } else {
4780                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4781                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4782                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4783                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4784         }
4785
4786         /* hw_max = RP0 until we check for overclocking */
4787         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4788
4789         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4790         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4791             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4792                 ret = sandybridge_pcode_read(dev_priv,
4793                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4794                                         &ddcc_status);
4795                 if (0 == ret)
4796                         dev_priv->rps.efficient_freq =
4797                                 clamp_t(u8,
4798                                         ((ddcc_status >> 8) & 0xff),
4799                                         dev_priv->rps.min_freq,
4800                                         dev_priv->rps.max_freq);
4801         }
4802
4803         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4804                 /* Store the frequency values in 16.66 MHZ units, which is
4805                    the natural hardware unit for SKL */
4806                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4807                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4808                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4809                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4810                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4811         }
4812
4813         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4814
4815         /* Preserve min/max settings in case of re-init */
4816         if (dev_priv->rps.max_freq_softlimit == 0)
4817                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4818
4819         if (dev_priv->rps.min_freq_softlimit == 0) {
4820                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4821                         dev_priv->rps.min_freq_softlimit =
4822                                 max_t(int, dev_priv->rps.efficient_freq,
4823                                       intel_freq_opcode(dev_priv, 450));
4824                 else
4825                         dev_priv->rps.min_freq_softlimit =
4826                                 dev_priv->rps.min_freq;
4827         }
4828 }
4829
4830 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4831 static void gen9_enable_rps(struct drm_device *dev)
4832 {
4833         struct drm_i915_private *dev_priv = dev->dev_private;
4834
4835         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4836
4837         gen6_init_rps_frequencies(dev);
4838
4839         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4840         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4841                 /*
4842                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
4843                  * clear out the Control register just to avoid inconsitency
4844                  * with debugfs interface, which will show  Turbo as enabled
4845                  * only and that is not expected by the User after adding the
4846                  * WaGsvDisableTurbo. Apart from this there is no problem even
4847                  * if the Turbo is left enabled in the Control register, as the
4848                  * Up/Down interrupts would remain masked.
4849                  */
4850                 gen9_disable_rps(dev);
4851                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4852                 return;
4853         }
4854
4855         /* Program defaults and thresholds for RPS*/
4856         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4857                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4858
4859         /* 1 second timeout*/
4860         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4861                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4862
4863         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4864
4865         /* Leaning on the below call to gen6_set_rps to program/setup the
4866          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4867          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4868         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4869         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4870
4871         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4872 }
4873
4874 static void gen9_enable_rc6(struct drm_device *dev)
4875 {
4876         struct drm_i915_private *dev_priv = dev->dev_private;
4877         struct intel_engine_cs *engine;
4878         uint32_t rc6_mask = 0;
4879
4880         /* 1a: Software RC state - RC0 */
4881         I915_WRITE(GEN6_RC_STATE, 0);
4882
4883         /* 1b: Get forcewake during program sequence. Although the driver
4884          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4885         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4886
4887         /* 2a: Disable RC states. */
4888         I915_WRITE(GEN6_RC_CONTROL, 0);
4889
4890         /* 2b: Program RC6 thresholds.*/
4891
4892         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4893         if (IS_SKYLAKE(dev))
4894                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4895         else
4896                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4897         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4898         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4899         for_each_engine(engine, dev_priv)
4900                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4901
4902         if (HAS_GUC_UCODE(dev))
4903                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4904
4905         I915_WRITE(GEN6_RC_SLEEP, 0);
4906
4907         /* 2c: Program Coarse Power Gating Policies. */
4908         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4909         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4910
4911         /* 3a: Enable RC6 */
4912         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4913                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4914         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4915         /* WaRsUseTimeoutMode */
4916         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4917             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4918                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4919                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4920                            GEN7_RC_CTL_TO_MODE |
4921                            rc6_mask);
4922         } else {
4923                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4924                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4925                            GEN6_RC_CTL_EI_MODE(1) |
4926                            rc6_mask);
4927         }
4928
4929         /*
4930          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4931          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4932          */
4933         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4934                 I915_WRITE(GEN9_PG_ENABLE, 0);
4935         else
4936                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4937                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4938
4939         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4940
4941 }
4942
4943 static void gen8_enable_rps(struct drm_device *dev)
4944 {
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         struct intel_engine_cs *engine;
4947         uint32_t rc6_mask = 0;
4948
4949         /* 1a: Software RC state - RC0 */
4950         I915_WRITE(GEN6_RC_STATE, 0);
4951
4952         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4953          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4954         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4955
4956         /* 2a: Disable RC states. */
4957         I915_WRITE(GEN6_RC_CONTROL, 0);
4958
4959         /* Initialize rps frequencies */
4960         gen6_init_rps_frequencies(dev);
4961
4962         /* 2b: Program RC6 thresholds.*/
4963         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4964         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4965         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4966         for_each_engine(engine, dev_priv)
4967                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4968         I915_WRITE(GEN6_RC_SLEEP, 0);
4969         if (IS_BROADWELL(dev))
4970                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4971         else
4972                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4973
4974         /* 3: Enable RC6 */
4975         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4976                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4977         intel_print_rc6_info(dev, rc6_mask);
4978         if (IS_BROADWELL(dev))
4979                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4980                                 GEN7_RC_CTL_TO_MODE |
4981                                 rc6_mask);
4982         else
4983                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4984                                 GEN6_RC_CTL_EI_MODE(1) |
4985                                 rc6_mask);
4986
4987         /* 4 Program defaults and thresholds for RPS*/
4988         I915_WRITE(GEN6_RPNSWREQ,
4989                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4990         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4991                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4992         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4993         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4994
4995         /* Docs recommend 900MHz, and 300 MHz respectively */
4996         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4997                    dev_priv->rps.max_freq_softlimit << 24 |
4998                    dev_priv->rps.min_freq_softlimit << 16);
4999
5000         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5001         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5002         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5003         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5004
5005         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5006
5007         /* 5: Enable RPS */
5008         I915_WRITE(GEN6_RP_CONTROL,
5009                    GEN6_RP_MEDIA_TURBO |
5010                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5011                    GEN6_RP_MEDIA_IS_GFX |
5012                    GEN6_RP_ENABLE |
5013                    GEN6_RP_UP_BUSY_AVG |
5014                    GEN6_RP_DOWN_IDLE_AVG);
5015
5016         /* 6: Ring frequency + overclocking (our driver does this later */
5017
5018         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5019         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5020
5021         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5022 }
5023
5024 static void gen6_enable_rps(struct drm_device *dev)
5025 {
5026         struct drm_i915_private *dev_priv = dev->dev_private;
5027         struct intel_engine_cs *engine;
5028         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5029         u32 gtfifodbg;
5030         int rc6_mode;
5031         int ret;
5032
5033         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5034
5035         /* Here begins a magic sequence of register writes to enable
5036          * auto-downclocking.
5037          *
5038          * Perhaps there might be some value in exposing these to
5039          * userspace...
5040          */
5041         I915_WRITE(GEN6_RC_STATE, 0);
5042
5043         /* Clear the DBG now so we don't confuse earlier errors */
5044         gtfifodbg = I915_READ(GTFIFODBG);
5045         if (gtfifodbg) {
5046                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5047                 I915_WRITE(GTFIFODBG, gtfifodbg);
5048         }
5049
5050         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5051
5052         /* Initialize rps frequencies */
5053         gen6_init_rps_frequencies(dev);
5054
5055         /* disable the counters and set deterministic thresholds */
5056         I915_WRITE(GEN6_RC_CONTROL, 0);
5057
5058         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5059         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5060         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5061         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5062         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5063
5064         for_each_engine(engine, dev_priv)
5065                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5066
5067         I915_WRITE(GEN6_RC_SLEEP, 0);
5068         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5069         if (IS_IVYBRIDGE(dev))
5070                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5071         else
5072                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5073         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5074         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5075
5076         /* Check if we are enabling RC6 */
5077         rc6_mode = intel_enable_rc6(dev_priv->dev);
5078         if (rc6_mode & INTEL_RC6_ENABLE)
5079                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5080
5081         /* We don't use those on Haswell */
5082         if (!IS_HASWELL(dev)) {
5083                 if (rc6_mode & INTEL_RC6p_ENABLE)
5084                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5085
5086                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5087                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5088         }
5089
5090         intel_print_rc6_info(dev, rc6_mask);
5091
5092         I915_WRITE(GEN6_RC_CONTROL,
5093                    rc6_mask |
5094                    GEN6_RC_CTL_EI_MODE(1) |
5095                    GEN6_RC_CTL_HW_ENABLE);
5096
5097         /* Power down if completely idle for over 50ms */
5098         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5099         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5100
5101         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5102         if (ret)
5103                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5104
5105         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5106         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5107                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5108                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5109                                  (pcu_mbox & 0xff) * 50);
5110                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5111         }
5112
5113         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5114         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5115
5116         rc6vids = 0;
5117         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5118         if (IS_GEN6(dev) && ret) {
5119                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5120         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5121                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5122                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5123                 rc6vids &= 0xffff00;
5124                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5125                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5126                 if (ret)
5127                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5128         }
5129
5130         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5131 }
5132
5133 static void __gen6_update_ring_freq(struct drm_device *dev)
5134 {
5135         struct drm_i915_private *dev_priv = dev->dev_private;
5136         int min_freq = 15;
5137         unsigned int gpu_freq;
5138         unsigned int max_ia_freq, min_ring_freq;
5139         unsigned int max_gpu_freq, min_gpu_freq;
5140         int scaling_factor = 180;
5141         struct cpufreq_policy *policy;
5142
5143         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5144
5145         policy = cpufreq_cpu_get(0);
5146         if (policy) {
5147                 max_ia_freq = policy->cpuinfo.max_freq;
5148                 cpufreq_cpu_put(policy);
5149         } else {
5150                 /*
5151                  * Default to measured freq if none found, PCU will ensure we
5152                  * don't go over
5153                  */
5154                 max_ia_freq = tsc_khz;
5155         }
5156
5157         /* Convert from kHz to MHz */
5158         max_ia_freq /= 1000;
5159
5160         min_ring_freq = I915_READ(DCLK) & 0xf;
5161         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5162         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5163
5164         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5165                 /* Convert GT frequency to 50 HZ units */
5166                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5167                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5168         } else {
5169                 min_gpu_freq = dev_priv->rps.min_freq;
5170                 max_gpu_freq = dev_priv->rps.max_freq;
5171         }
5172
5173         /*
5174          * For each potential GPU frequency, load a ring frequency we'd like
5175          * to use for memory access.  We do this by specifying the IA frequency
5176          * the PCU should use as a reference to determine the ring frequency.
5177          */
5178         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5179                 int diff = max_gpu_freq - gpu_freq;
5180                 unsigned int ia_freq = 0, ring_freq = 0;
5181
5182                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5183                         /*
5184                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5185                          * No floor required for ring frequency on SKL.
5186                          */
5187                         ring_freq = gpu_freq;
5188                 } else if (INTEL_INFO(dev)->gen >= 8) {
5189                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5190                         ring_freq = max(min_ring_freq, gpu_freq);
5191                 } else if (IS_HASWELL(dev)) {
5192                         ring_freq = mult_frac(gpu_freq, 5, 4);
5193                         ring_freq = max(min_ring_freq, ring_freq);
5194                         /* leave ia_freq as the default, chosen by cpufreq */
5195                 } else {
5196                         /* On older processors, there is no separate ring
5197                          * clock domain, so in order to boost the bandwidth
5198                          * of the ring, we need to upclock the CPU (ia_freq).
5199                          *
5200                          * For GPU frequencies less than 750MHz,
5201                          * just use the lowest ring freq.
5202                          */
5203                         if (gpu_freq < min_freq)
5204                                 ia_freq = 800;
5205                         else
5206                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5207                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5208                 }
5209
5210                 sandybridge_pcode_write(dev_priv,
5211                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5212                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5213                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5214                                         gpu_freq);
5215         }
5216 }
5217
5218 void gen6_update_ring_freq(struct drm_device *dev)
5219 {
5220         struct drm_i915_private *dev_priv = dev->dev_private;
5221
5222         if (!HAS_CORE_RING_FREQ(dev))
5223                 return;
5224
5225         mutex_lock(&dev_priv->rps.hw_lock);
5226         __gen6_update_ring_freq(dev);
5227         mutex_unlock(&dev_priv->rps.hw_lock);
5228 }
5229
5230 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5231 {
5232         struct drm_device *dev = dev_priv->dev;
5233         u32 val, rp0;
5234
5235         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5236
5237         switch (INTEL_INFO(dev)->eu_total) {
5238         case 8:
5239                 /* (2 * 4) config */
5240                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5241                 break;
5242         case 12:
5243                 /* (2 * 6) config */
5244                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5245                 break;
5246         case 16:
5247                 /* (2 * 8) config */
5248         default:
5249                 /* Setting (2 * 8) Min RP0 for any other combination */
5250                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5251                 break;
5252         }
5253
5254         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5255
5256         return rp0;
5257 }
5258
5259 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5260 {
5261         u32 val, rpe;
5262
5263         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5264         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5265
5266         return rpe;
5267 }
5268
5269 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5270 {
5271         u32 val, rp1;
5272
5273         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5274         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5275
5276         return rp1;
5277 }
5278
5279 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5280 {
5281         u32 val, rp1;
5282
5283         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5284
5285         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5286
5287         return rp1;
5288 }
5289
5290 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5291 {
5292         u32 val, rp0;
5293
5294         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5295
5296         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5297         /* Clamp to max */
5298         rp0 = min_t(u32, rp0, 0xea);
5299
5300         return rp0;
5301 }
5302
5303 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5304 {
5305         u32 val, rpe;
5306
5307         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5308         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5309         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5310         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5311
5312         return rpe;
5313 }
5314
5315 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5316 {
5317         u32 val;
5318
5319         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5320         /*
5321          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5322          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5323          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5324          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5325          * to make sure it matches what Punit accepts.
5326          */
5327         return max_t(u32, val, 0xc0);
5328 }
5329
5330 /* Check that the pctx buffer wasn't move under us. */
5331 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5332 {
5333         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5334
5335         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5336                              dev_priv->vlv_pctx->stolen->start);
5337 }
5338
5339
5340 /* Check that the pcbr address is not empty. */
5341 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5342 {
5343         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5344
5345         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5346 }
5347
5348 static void cherryview_setup_pctx(struct drm_device *dev)
5349 {
5350         struct drm_i915_private *dev_priv = to_i915(dev);
5351         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5352         unsigned long pctx_paddr, paddr;
5353         u32 pcbr;
5354         int pctx_size = 32*1024;
5355
5356         pcbr = I915_READ(VLV_PCBR);
5357         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5358                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5359                 paddr = (dev_priv->mm.stolen_base +
5360                          (ggtt->stolen_size - pctx_size));
5361
5362                 pctx_paddr = (paddr & (~4095));
5363                 I915_WRITE(VLV_PCBR, pctx_paddr);
5364         }
5365
5366         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5367 }
5368
5369 static void valleyview_setup_pctx(struct drm_device *dev)
5370 {
5371         struct drm_i915_private *dev_priv = dev->dev_private;
5372         struct drm_i915_gem_object *pctx;
5373         unsigned long pctx_paddr;
5374         u32 pcbr;
5375         int pctx_size = 24*1024;
5376
5377         mutex_lock(&dev->struct_mutex);
5378
5379         pcbr = I915_READ(VLV_PCBR);
5380         if (pcbr) {
5381                 /* BIOS set it up already, grab the pre-alloc'd space */
5382                 int pcbr_offset;
5383
5384                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5385                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5386                                                                       pcbr_offset,
5387                                                                       I915_GTT_OFFSET_NONE,
5388                                                                       pctx_size);
5389                 goto out;
5390         }
5391
5392         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5393
5394         /*
5395          * From the Gunit register HAS:
5396          * The Gfx driver is expected to program this register and ensure
5397          * proper allocation within Gfx stolen memory.  For example, this
5398          * register should be programmed such than the PCBR range does not
5399          * overlap with other ranges, such as the frame buffer, protected
5400          * memory, or any other relevant ranges.
5401          */
5402         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5403         if (!pctx) {
5404                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5405                 goto out;
5406         }
5407
5408         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5409         I915_WRITE(VLV_PCBR, pctx_paddr);
5410
5411 out:
5412         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5413         dev_priv->vlv_pctx = pctx;
5414         mutex_unlock(&dev->struct_mutex);
5415 }
5416
5417 static void valleyview_cleanup_pctx(struct drm_device *dev)
5418 {
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420
5421         if (WARN_ON(!dev_priv->vlv_pctx))
5422                 return;
5423
5424         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5425         dev_priv->vlv_pctx = NULL;
5426 }
5427
5428 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5429 {
5430         dev_priv->rps.gpll_ref_freq =
5431                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5432                                   CCK_GPLL_CLOCK_CONTROL,
5433                                   dev_priv->czclk_freq);
5434
5435         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5436                          dev_priv->rps.gpll_ref_freq);
5437 }
5438
5439 static void valleyview_init_gt_powersave(struct drm_device *dev)
5440 {
5441         struct drm_i915_private *dev_priv = dev->dev_private;
5442         u32 val;
5443
5444         valleyview_setup_pctx(dev);
5445
5446         vlv_init_gpll_ref_freq(dev_priv);
5447
5448         mutex_lock(&dev_priv->rps.hw_lock);
5449
5450         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5451         switch ((val >> 6) & 3) {
5452         case 0:
5453         case 1:
5454                 dev_priv->mem_freq = 800;
5455                 break;
5456         case 2:
5457                 dev_priv->mem_freq = 1066;
5458                 break;
5459         case 3:
5460                 dev_priv->mem_freq = 1333;
5461                 break;
5462         }
5463         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5464
5465         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5466         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5467         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5468                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5469                          dev_priv->rps.max_freq);
5470
5471         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5472         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5473                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5474                          dev_priv->rps.efficient_freq);
5475
5476         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5477         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5478                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5479                          dev_priv->rps.rp1_freq);
5480
5481         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5482         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5483                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5484                          dev_priv->rps.min_freq);
5485
5486         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5487
5488         /* Preserve min/max settings in case of re-init */
5489         if (dev_priv->rps.max_freq_softlimit == 0)
5490                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5491
5492         if (dev_priv->rps.min_freq_softlimit == 0)
5493                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5494
5495         mutex_unlock(&dev_priv->rps.hw_lock);
5496 }
5497
5498 static void cherryview_init_gt_powersave(struct drm_device *dev)
5499 {
5500         struct drm_i915_private *dev_priv = dev->dev_private;
5501         u32 val;
5502
5503         cherryview_setup_pctx(dev);
5504
5505         vlv_init_gpll_ref_freq(dev_priv);
5506
5507         mutex_lock(&dev_priv->rps.hw_lock);
5508
5509         mutex_lock(&dev_priv->sb_lock);
5510         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5511         mutex_unlock(&dev_priv->sb_lock);
5512
5513         switch ((val >> 2) & 0x7) {
5514         case 3:
5515                 dev_priv->mem_freq = 2000;
5516                 break;
5517         default:
5518                 dev_priv->mem_freq = 1600;
5519                 break;
5520         }
5521         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5522
5523         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5524         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5525         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5526                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5527                          dev_priv->rps.max_freq);
5528
5529         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5530         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5531                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5532                          dev_priv->rps.efficient_freq);
5533
5534         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5535         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5536                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5537                          dev_priv->rps.rp1_freq);
5538
5539         /* PUnit validated range is only [RPe, RP0] */
5540         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5541         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5542                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5543                          dev_priv->rps.min_freq);
5544
5545         WARN_ONCE((dev_priv->rps.max_freq |
5546                    dev_priv->rps.efficient_freq |
5547                    dev_priv->rps.rp1_freq |
5548                    dev_priv->rps.min_freq) & 1,
5549                   "Odd GPU freq values\n");
5550
5551         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5552
5553         /* Preserve min/max settings in case of re-init */
5554         if (dev_priv->rps.max_freq_softlimit == 0)
5555                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5556
5557         if (dev_priv->rps.min_freq_softlimit == 0)
5558                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5559
5560         mutex_unlock(&dev_priv->rps.hw_lock);
5561 }
5562
5563 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5564 {
5565         valleyview_cleanup_pctx(dev);
5566 }
5567
5568 static void cherryview_enable_rps(struct drm_device *dev)
5569 {
5570         struct drm_i915_private *dev_priv = dev->dev_private;
5571         struct intel_engine_cs *engine;
5572         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5573
5574         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5575
5576         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5577                                              GT_FIFO_FREE_ENTRIES_CHV);
5578         if (gtfifodbg) {
5579                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5580                                  gtfifodbg);
5581                 I915_WRITE(GTFIFODBG, gtfifodbg);
5582         }
5583
5584         cherryview_check_pctx(dev_priv);
5585
5586         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5587          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5588         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5589
5590         /*  Disable RC states. */
5591         I915_WRITE(GEN6_RC_CONTROL, 0);
5592
5593         /* 2a: Program RC6 thresholds.*/
5594         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5595         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5596         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5597
5598         for_each_engine(engine, dev_priv)
5599                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5600         I915_WRITE(GEN6_RC_SLEEP, 0);
5601
5602         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5603         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5604
5605         /* allows RC6 residency counter to work */
5606         I915_WRITE(VLV_COUNTER_CONTROL,
5607                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5608                                       VLV_MEDIA_RC6_COUNT_EN |
5609                                       VLV_RENDER_RC6_COUNT_EN));
5610
5611         /* For now we assume BIOS is allocating and populating the PCBR  */
5612         pcbr = I915_READ(VLV_PCBR);
5613
5614         /* 3: Enable RC6 */
5615         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5616                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5617                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5618
5619         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5620
5621         /* 4 Program defaults and thresholds for RPS*/
5622         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5623         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5624         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5625         I915_WRITE(GEN6_RP_UP_EI, 66000);
5626         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5627
5628         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5629
5630         /* 5: Enable RPS */
5631         I915_WRITE(GEN6_RP_CONTROL,
5632                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5633                    GEN6_RP_MEDIA_IS_GFX |
5634                    GEN6_RP_ENABLE |
5635                    GEN6_RP_UP_BUSY_AVG |
5636                    GEN6_RP_DOWN_IDLE_AVG);
5637
5638         /* Setting Fixed Bias */
5639         val = VLV_OVERRIDE_EN |
5640                   VLV_SOC_TDP_EN |
5641                   CHV_BIAS_CPU_50_SOC_50;
5642         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5643
5644         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5645
5646         /* RPS code assumes GPLL is used */
5647         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5648
5649         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5650         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5651
5652         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5653         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5654                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5655                          dev_priv->rps.cur_freq);
5656
5657         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5658                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5659                          dev_priv->rps.idle_freq);
5660
5661         valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5662
5663         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5664 }
5665
5666 static void valleyview_enable_rps(struct drm_device *dev)
5667 {
5668         struct drm_i915_private *dev_priv = dev->dev_private;
5669         struct intel_engine_cs *engine;
5670         u32 gtfifodbg, val, rc6_mode = 0;
5671
5672         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5673
5674         valleyview_check_pctx(dev_priv);
5675
5676         gtfifodbg = I915_READ(GTFIFODBG);
5677         if (gtfifodbg) {
5678                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5679                                  gtfifodbg);
5680                 I915_WRITE(GTFIFODBG, gtfifodbg);
5681         }
5682
5683         /* If VLV, Forcewake all wells, else re-direct to regular path */
5684         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5685
5686         /*  Disable RC states. */
5687         I915_WRITE(GEN6_RC_CONTROL, 0);
5688
5689         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5690         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5691         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5692         I915_WRITE(GEN6_RP_UP_EI, 66000);
5693         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5694
5695         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5696
5697         I915_WRITE(GEN6_RP_CONTROL,
5698                    GEN6_RP_MEDIA_TURBO |
5699                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5700                    GEN6_RP_MEDIA_IS_GFX |
5701                    GEN6_RP_ENABLE |
5702                    GEN6_RP_UP_BUSY_AVG |
5703                    GEN6_RP_DOWN_IDLE_CONT);
5704
5705         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5706         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5707         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5708
5709         for_each_engine(engine, dev_priv)
5710                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5711
5712         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5713
5714         /* allows RC6 residency counter to work */
5715         I915_WRITE(VLV_COUNTER_CONTROL,
5716                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5717                                       VLV_RENDER_RC0_COUNT_EN |
5718                                       VLV_MEDIA_RC6_COUNT_EN |
5719                                       VLV_RENDER_RC6_COUNT_EN));
5720
5721         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5722                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5723
5724         intel_print_rc6_info(dev, rc6_mode);
5725
5726         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5727
5728         /* Setting Fixed Bias */
5729         val = VLV_OVERRIDE_EN |
5730                   VLV_SOC_TDP_EN |
5731                   VLV_BIAS_CPU_125_SOC_875;
5732         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5733
5734         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5735
5736         /* RPS code assumes GPLL is used */
5737         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5738
5739         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5740         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5741
5742         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5743         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5744                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5745                          dev_priv->rps.cur_freq);
5746
5747         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5748                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5749                          dev_priv->rps.idle_freq);
5750
5751         valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5752
5753         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5754 }
5755
5756 static unsigned long intel_pxfreq(u32 vidfreq)
5757 {
5758         unsigned long freq;
5759         int div = (vidfreq & 0x3f0000) >> 16;
5760         int post = (vidfreq & 0x3000) >> 12;
5761         int pre = (vidfreq & 0x7);
5762
5763         if (!pre)
5764                 return 0;
5765
5766         freq = ((div * 133333) / ((1<<post) * pre));
5767
5768         return freq;
5769 }
5770
5771 static const struct cparams {
5772         u16 i;
5773         u16 t;
5774         u16 m;
5775         u16 c;
5776 } cparams[] = {
5777         { 1, 1333, 301, 28664 },
5778         { 1, 1066, 294, 24460 },
5779         { 1, 800, 294, 25192 },
5780         { 0, 1333, 276, 27605 },
5781         { 0, 1066, 276, 27605 },
5782         { 0, 800, 231, 23784 },
5783 };
5784
5785 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5786 {
5787         u64 total_count, diff, ret;
5788         u32 count1, count2, count3, m = 0, c = 0;
5789         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5790         int i;
5791
5792         assert_spin_locked(&mchdev_lock);
5793
5794         diff1 = now - dev_priv->ips.last_time1;
5795
5796         /* Prevent division-by-zero if we are asking too fast.
5797          * Also, we don't get interesting results if we are polling
5798          * faster than once in 10ms, so just return the saved value
5799          * in such cases.
5800          */
5801         if (diff1 <= 10)
5802                 return dev_priv->ips.chipset_power;
5803
5804         count1 = I915_READ(DMIEC);
5805         count2 = I915_READ(DDREC);
5806         count3 = I915_READ(CSIEC);
5807
5808         total_count = count1 + count2 + count3;
5809
5810         /* FIXME: handle per-counter overflow */
5811         if (total_count < dev_priv->ips.last_count1) {
5812                 diff = ~0UL - dev_priv->ips.last_count1;
5813                 diff += total_count;
5814         } else {
5815                 diff = total_count - dev_priv->ips.last_count1;
5816         }
5817
5818         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5819                 if (cparams[i].i == dev_priv->ips.c_m &&
5820                     cparams[i].t == dev_priv->ips.r_t) {
5821                         m = cparams[i].m;
5822                         c = cparams[i].c;
5823                         break;
5824                 }
5825         }
5826
5827         diff = div_u64(diff, diff1);
5828         ret = ((m * diff) + c);
5829         ret = div_u64(ret, 10);
5830
5831         dev_priv->ips.last_count1 = total_count;
5832         dev_priv->ips.last_time1 = now;
5833
5834         dev_priv->ips.chipset_power = ret;
5835
5836         return ret;
5837 }
5838
5839 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5840 {
5841         struct drm_device *dev = dev_priv->dev;
5842         unsigned long val;
5843
5844         if (INTEL_INFO(dev)->gen != 5)
5845                 return 0;
5846
5847         spin_lock_irq(&mchdev_lock);
5848
5849         val = __i915_chipset_val(dev_priv);
5850
5851         spin_unlock_irq(&mchdev_lock);
5852
5853         return val;
5854 }
5855
5856 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5857 {
5858         unsigned long m, x, b;
5859         u32 tsfs;
5860
5861         tsfs = I915_READ(TSFS);
5862
5863         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5864         x = I915_READ8(TR1);
5865
5866         b = tsfs & TSFS_INTR_MASK;
5867
5868         return ((m * x) / 127) - b;
5869 }
5870
5871 static int _pxvid_to_vd(u8 pxvid)
5872 {
5873         if (pxvid == 0)
5874                 return 0;
5875
5876         if (pxvid >= 8 && pxvid < 31)
5877                 pxvid = 31;
5878
5879         return (pxvid + 2) * 125;
5880 }
5881
5882 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5883 {
5884         struct drm_device *dev = dev_priv->dev;
5885         const int vd = _pxvid_to_vd(pxvid);
5886         const int vm = vd - 1125;
5887
5888         if (INTEL_INFO(dev)->is_mobile)
5889                 return vm > 0 ? vm : 0;
5890
5891         return vd;
5892 }
5893
5894 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5895 {
5896         u64 now, diff, diffms;
5897         u32 count;
5898
5899         assert_spin_locked(&mchdev_lock);
5900
5901         now = ktime_get_raw_ns();
5902         diffms = now - dev_priv->ips.last_time2;
5903         do_div(diffms, NSEC_PER_MSEC);
5904
5905         /* Don't divide by 0 */
5906         if (!diffms)
5907                 return;
5908
5909         count = I915_READ(GFXEC);
5910
5911         if (count < dev_priv->ips.last_count2) {
5912                 diff = ~0UL - dev_priv->ips.last_count2;
5913                 diff += count;
5914         } else {
5915                 diff = count - dev_priv->ips.last_count2;
5916         }
5917
5918         dev_priv->ips.last_count2 = count;
5919         dev_priv->ips.last_time2 = now;
5920
5921         /* More magic constants... */
5922         diff = diff * 1181;
5923         diff = div_u64(diff, diffms * 10);
5924         dev_priv->ips.gfx_power = diff;
5925 }
5926
5927 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5928 {
5929         struct drm_device *dev = dev_priv->dev;
5930
5931         if (INTEL_INFO(dev)->gen != 5)
5932                 return;
5933
5934         spin_lock_irq(&mchdev_lock);
5935
5936         __i915_update_gfx_val(dev_priv);
5937
5938         spin_unlock_irq(&mchdev_lock);
5939 }
5940
5941 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5942 {
5943         unsigned long t, corr, state1, corr2, state2;
5944         u32 pxvid, ext_v;
5945
5946         assert_spin_locked(&mchdev_lock);
5947
5948         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5949         pxvid = (pxvid >> 24) & 0x7f;
5950         ext_v = pvid_to_extvid(dev_priv, pxvid);
5951
5952         state1 = ext_v;
5953
5954         t = i915_mch_val(dev_priv);
5955
5956         /* Revel in the empirically derived constants */
5957
5958         /* Correction factor in 1/100000 units */
5959         if (t > 80)
5960                 corr = ((t * 2349) + 135940);
5961         else if (t >= 50)
5962                 corr = ((t * 964) + 29317);
5963         else /* < 50 */
5964                 corr = ((t * 301) + 1004);
5965
5966         corr = corr * ((150142 * state1) / 10000 - 78642);
5967         corr /= 100000;
5968         corr2 = (corr * dev_priv->ips.corr);
5969
5970         state2 = (corr2 * state1) / 10000;
5971         state2 /= 100; /* convert to mW */
5972
5973         __i915_update_gfx_val(dev_priv);
5974
5975         return dev_priv->ips.gfx_power + state2;
5976 }
5977
5978 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5979 {
5980         struct drm_device *dev = dev_priv->dev;
5981         unsigned long val;
5982
5983         if (INTEL_INFO(dev)->gen != 5)
5984                 return 0;
5985
5986         spin_lock_irq(&mchdev_lock);
5987
5988         val = __i915_gfx_val(dev_priv);
5989
5990         spin_unlock_irq(&mchdev_lock);
5991
5992         return val;
5993 }
5994
5995 /**
5996  * i915_read_mch_val - return value for IPS use
5997  *
5998  * Calculate and return a value for the IPS driver to use when deciding whether
5999  * we have thermal and power headroom to increase CPU or GPU power budget.
6000  */
6001 unsigned long i915_read_mch_val(void)
6002 {
6003         struct drm_i915_private *dev_priv;
6004         unsigned long chipset_val, graphics_val, ret = 0;
6005
6006         spin_lock_irq(&mchdev_lock);
6007         if (!i915_mch_dev)
6008                 goto out_unlock;
6009         dev_priv = i915_mch_dev;
6010
6011         chipset_val = __i915_chipset_val(dev_priv);
6012         graphics_val = __i915_gfx_val(dev_priv);
6013
6014         ret = chipset_val + graphics_val;
6015
6016 out_unlock:
6017         spin_unlock_irq(&mchdev_lock);
6018
6019         return ret;
6020 }
6021 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6022
6023 /**
6024  * i915_gpu_raise - raise GPU frequency limit
6025  *
6026  * Raise the limit; IPS indicates we have thermal headroom.
6027  */
6028 bool i915_gpu_raise(void)
6029 {
6030         struct drm_i915_private *dev_priv;
6031         bool ret = true;
6032
6033         spin_lock_irq(&mchdev_lock);
6034         if (!i915_mch_dev) {
6035                 ret = false;
6036                 goto out_unlock;
6037         }
6038         dev_priv = i915_mch_dev;
6039
6040         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6041                 dev_priv->ips.max_delay--;
6042
6043 out_unlock:
6044         spin_unlock_irq(&mchdev_lock);
6045
6046         return ret;
6047 }
6048 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6049
6050 /**
6051  * i915_gpu_lower - lower GPU frequency limit
6052  *
6053  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6054  * frequency maximum.
6055  */
6056 bool i915_gpu_lower(void)
6057 {
6058         struct drm_i915_private *dev_priv;
6059         bool ret = true;
6060
6061         spin_lock_irq(&mchdev_lock);
6062         if (!i915_mch_dev) {
6063                 ret = false;
6064                 goto out_unlock;
6065         }
6066         dev_priv = i915_mch_dev;
6067
6068         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6069                 dev_priv->ips.max_delay++;
6070
6071 out_unlock:
6072         spin_unlock_irq(&mchdev_lock);
6073
6074         return ret;
6075 }
6076 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6077
6078 /**
6079  * i915_gpu_busy - indicate GPU business to IPS
6080  *
6081  * Tell the IPS driver whether or not the GPU is busy.
6082  */
6083 bool i915_gpu_busy(void)
6084 {
6085         struct drm_i915_private *dev_priv;
6086         struct intel_engine_cs *engine;
6087         bool ret = false;
6088
6089         spin_lock_irq(&mchdev_lock);
6090         if (!i915_mch_dev)
6091                 goto out_unlock;
6092         dev_priv = i915_mch_dev;
6093
6094         for_each_engine(engine, dev_priv)
6095                 ret |= !list_empty(&engine->request_list);
6096
6097 out_unlock:
6098         spin_unlock_irq(&mchdev_lock);
6099
6100         return ret;
6101 }
6102 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6103
6104 /**
6105  * i915_gpu_turbo_disable - disable graphics turbo
6106  *
6107  * Disable graphics turbo by resetting the max frequency and setting the
6108  * current frequency to the default.
6109  */
6110 bool i915_gpu_turbo_disable(void)
6111 {
6112         struct drm_i915_private *dev_priv;
6113         bool ret = true;
6114
6115         spin_lock_irq(&mchdev_lock);
6116         if (!i915_mch_dev) {
6117                 ret = false;
6118                 goto out_unlock;
6119         }
6120         dev_priv = i915_mch_dev;
6121
6122         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6123
6124         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6125                 ret = false;
6126
6127 out_unlock:
6128         spin_unlock_irq(&mchdev_lock);
6129
6130         return ret;
6131 }
6132 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6133
6134 /**
6135  * Tells the intel_ips driver that the i915 driver is now loaded, if
6136  * IPS got loaded first.
6137  *
6138  * This awkward dance is so that neither module has to depend on the
6139  * other in order for IPS to do the appropriate communication of
6140  * GPU turbo limits to i915.
6141  */
6142 static void
6143 ips_ping_for_i915_load(void)
6144 {
6145         void (*link)(void);
6146
6147         link = symbol_get(ips_link_to_i915_driver);
6148         if (link) {
6149                 link();
6150                 symbol_put(ips_link_to_i915_driver);
6151         }
6152 }
6153
6154 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6155 {
6156         /* We only register the i915 ips part with intel-ips once everything is
6157          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6158         spin_lock_irq(&mchdev_lock);
6159         i915_mch_dev = dev_priv;
6160         spin_unlock_irq(&mchdev_lock);
6161
6162         ips_ping_for_i915_load();
6163 }
6164
6165 void intel_gpu_ips_teardown(void)
6166 {
6167         spin_lock_irq(&mchdev_lock);
6168         i915_mch_dev = NULL;
6169         spin_unlock_irq(&mchdev_lock);
6170 }
6171
6172 static void intel_init_emon(struct drm_device *dev)
6173 {
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         u32 lcfuse;
6176         u8 pxw[16];
6177         int i;
6178
6179         /* Disable to program */
6180         I915_WRITE(ECR, 0);
6181         POSTING_READ(ECR);
6182
6183         /* Program energy weights for various events */
6184         I915_WRITE(SDEW, 0x15040d00);
6185         I915_WRITE(CSIEW0, 0x007f0000);
6186         I915_WRITE(CSIEW1, 0x1e220004);
6187         I915_WRITE(CSIEW2, 0x04000004);
6188
6189         for (i = 0; i < 5; i++)
6190                 I915_WRITE(PEW(i), 0);
6191         for (i = 0; i < 3; i++)
6192                 I915_WRITE(DEW(i), 0);
6193
6194         /* Program P-state weights to account for frequency power adjustment */
6195         for (i = 0; i < 16; i++) {
6196                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6197                 unsigned long freq = intel_pxfreq(pxvidfreq);
6198                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6199                         PXVFREQ_PX_SHIFT;
6200                 unsigned long val;
6201
6202                 val = vid * vid;
6203                 val *= (freq / 1000);
6204                 val *= 255;
6205                 val /= (127*127*900);
6206                 if (val > 0xff)
6207                         DRM_ERROR("bad pxval: %ld\n", val);
6208                 pxw[i] = val;
6209         }
6210         /* Render standby states get 0 weight */
6211         pxw[14] = 0;
6212         pxw[15] = 0;
6213
6214         for (i = 0; i < 4; i++) {
6215                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6216                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6217                 I915_WRITE(PXW(i), val);
6218         }
6219
6220         /* Adjust magic regs to magic values (more experimental results) */
6221         I915_WRITE(OGW0, 0);
6222         I915_WRITE(OGW1, 0);
6223         I915_WRITE(EG0, 0x00007f00);
6224         I915_WRITE(EG1, 0x0000000e);
6225         I915_WRITE(EG2, 0x000e0000);
6226         I915_WRITE(EG3, 0x68000300);
6227         I915_WRITE(EG4, 0x42000000);
6228         I915_WRITE(EG5, 0x00140031);
6229         I915_WRITE(EG6, 0);
6230         I915_WRITE(EG7, 0);
6231
6232         for (i = 0; i < 8; i++)
6233                 I915_WRITE(PXWL(i), 0);
6234
6235         /* Enable PMON + select events */
6236         I915_WRITE(ECR, 0x80000019);
6237
6238         lcfuse = I915_READ(LCFUSE02);
6239
6240         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6241 }
6242
6243 void intel_init_gt_powersave(struct drm_device *dev)
6244 {
6245         struct drm_i915_private *dev_priv = dev->dev_private;
6246
6247         /*
6248          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6249          * requirement.
6250          */
6251         if (!i915.enable_rc6) {
6252                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6253                 intel_runtime_pm_get(dev_priv);
6254         }
6255
6256         if (IS_CHERRYVIEW(dev))
6257                 cherryview_init_gt_powersave(dev);
6258         else if (IS_VALLEYVIEW(dev))
6259                 valleyview_init_gt_powersave(dev);
6260 }
6261
6262 void intel_cleanup_gt_powersave(struct drm_device *dev)
6263 {
6264         struct drm_i915_private *dev_priv = dev->dev_private;
6265
6266         if (IS_CHERRYVIEW(dev))
6267                 return;
6268         else if (IS_VALLEYVIEW(dev))
6269                 valleyview_cleanup_gt_powersave(dev);
6270
6271         if (!i915.enable_rc6)
6272                 intel_runtime_pm_put(dev_priv);
6273 }
6274
6275 static void gen6_suspend_rps(struct drm_device *dev)
6276 {
6277         struct drm_i915_private *dev_priv = dev->dev_private;
6278
6279         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6280
6281         gen6_disable_rps_interrupts(dev);
6282 }
6283
6284 /**
6285  * intel_suspend_gt_powersave - suspend PM work and helper threads
6286  * @dev: drm device
6287  *
6288  * We don't want to disable RC6 or other features here, we just want
6289  * to make sure any work we've queued has finished and won't bother
6290  * us while we're suspended.
6291  */
6292 void intel_suspend_gt_powersave(struct drm_device *dev)
6293 {
6294         struct drm_i915_private *dev_priv = dev->dev_private;
6295
6296         if (INTEL_INFO(dev)->gen < 6)
6297                 return;
6298
6299         gen6_suspend_rps(dev);
6300
6301         /* Force GPU to min freq during suspend */
6302         gen6_rps_idle(dev_priv);
6303 }
6304
6305 void intel_disable_gt_powersave(struct drm_device *dev)
6306 {
6307         struct drm_i915_private *dev_priv = dev->dev_private;
6308
6309         if (IS_IRONLAKE_M(dev)) {
6310                 ironlake_disable_drps(dev);
6311         } else if (INTEL_INFO(dev)->gen >= 6) {
6312                 intel_suspend_gt_powersave(dev);
6313
6314                 mutex_lock(&dev_priv->rps.hw_lock);
6315                 if (INTEL_INFO(dev)->gen >= 9) {
6316                         gen9_disable_rc6(dev);
6317                         gen9_disable_rps(dev);
6318                 } else if (IS_CHERRYVIEW(dev))
6319                         cherryview_disable_rps(dev);
6320                 else if (IS_VALLEYVIEW(dev))
6321                         valleyview_disable_rps(dev);
6322                 else
6323                         gen6_disable_rps(dev);
6324
6325                 dev_priv->rps.enabled = false;
6326                 mutex_unlock(&dev_priv->rps.hw_lock);
6327         }
6328 }
6329
6330 static void intel_gen6_powersave_work(struct work_struct *work)
6331 {
6332         struct drm_i915_private *dev_priv =
6333                 container_of(work, struct drm_i915_private,
6334                              rps.delayed_resume_work.work);
6335         struct drm_device *dev = dev_priv->dev;
6336
6337         mutex_lock(&dev_priv->rps.hw_lock);
6338
6339         gen6_reset_rps_interrupts(dev);
6340
6341         if (IS_CHERRYVIEW(dev)) {
6342                 cherryview_enable_rps(dev);
6343         } else if (IS_VALLEYVIEW(dev)) {
6344                 valleyview_enable_rps(dev);
6345         } else if (INTEL_INFO(dev)->gen >= 9) {
6346                 gen9_enable_rc6(dev);
6347                 gen9_enable_rps(dev);
6348                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6349                         __gen6_update_ring_freq(dev);
6350         } else if (IS_BROADWELL(dev)) {
6351                 gen8_enable_rps(dev);
6352                 __gen6_update_ring_freq(dev);
6353         } else {
6354                 gen6_enable_rps(dev);
6355                 __gen6_update_ring_freq(dev);
6356         }
6357
6358         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6359         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6360
6361         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6362         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6363
6364         dev_priv->rps.enabled = true;
6365
6366         gen6_enable_rps_interrupts(dev);
6367
6368         mutex_unlock(&dev_priv->rps.hw_lock);
6369
6370         intel_runtime_pm_put(dev_priv);
6371 }
6372
6373 void intel_enable_gt_powersave(struct drm_device *dev)
6374 {
6375         struct drm_i915_private *dev_priv = dev->dev_private;
6376
6377         /* Powersaving is controlled by the host when inside a VM */
6378         if (intel_vgpu_active(dev))
6379                 return;
6380
6381         if (IS_IRONLAKE_M(dev)) {
6382                 ironlake_enable_drps(dev);
6383                 mutex_lock(&dev->struct_mutex);
6384                 intel_init_emon(dev);
6385                 mutex_unlock(&dev->struct_mutex);
6386         } else if (INTEL_INFO(dev)->gen >= 6) {
6387                 /*
6388                  * PCU communication is slow and this doesn't need to be
6389                  * done at any specific time, so do this out of our fast path
6390                  * to make resume and init faster.
6391                  *
6392                  * We depend on the HW RC6 power context save/restore
6393                  * mechanism when entering D3 through runtime PM suspend. So
6394                  * disable RPM until RPS/RC6 is properly setup. We can only
6395                  * get here via the driver load/system resume/runtime resume
6396                  * paths, so the _noresume version is enough (and in case of
6397                  * runtime resume it's necessary).
6398                  */
6399                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6400                                            round_jiffies_up_relative(HZ)))
6401                         intel_runtime_pm_get_noresume(dev_priv);
6402         }
6403 }
6404
6405 void intel_reset_gt_powersave(struct drm_device *dev)
6406 {
6407         struct drm_i915_private *dev_priv = dev->dev_private;
6408
6409         if (INTEL_INFO(dev)->gen < 6)
6410                 return;
6411
6412         gen6_suspend_rps(dev);
6413         dev_priv->rps.enabled = false;
6414 }
6415
6416 static void ibx_init_clock_gating(struct drm_device *dev)
6417 {
6418         struct drm_i915_private *dev_priv = dev->dev_private;
6419
6420         /*
6421          * On Ibex Peak and Cougar Point, we need to disable clock
6422          * gating for the panel power sequencer or it will fail to
6423          * start up when no ports are active.
6424          */
6425         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6426 }
6427
6428 static void g4x_disable_trickle_feed(struct drm_device *dev)
6429 {
6430         struct drm_i915_private *dev_priv = dev->dev_private;
6431         enum pipe pipe;
6432
6433         for_each_pipe(dev_priv, pipe) {
6434                 I915_WRITE(DSPCNTR(pipe),
6435                            I915_READ(DSPCNTR(pipe)) |
6436                            DISPPLANE_TRICKLE_FEED_DISABLE);
6437
6438                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6439                 POSTING_READ(DSPSURF(pipe));
6440         }
6441 }
6442
6443 static void ilk_init_lp_watermarks(struct drm_device *dev)
6444 {
6445         struct drm_i915_private *dev_priv = dev->dev_private;
6446
6447         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6448         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6449         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6450
6451         /*
6452          * Don't touch WM1S_LP_EN here.
6453          * Doing so could cause underruns.
6454          */
6455 }
6456
6457 static void ironlake_init_clock_gating(struct drm_device *dev)
6458 {
6459         struct drm_i915_private *dev_priv = dev->dev_private;
6460         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6461
6462         /*
6463          * Required for FBC
6464          * WaFbcDisableDpfcClockGating:ilk
6465          */
6466         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6467                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6468                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6469
6470         I915_WRITE(PCH_3DCGDIS0,
6471                    MARIUNIT_CLOCK_GATE_DISABLE |
6472                    SVSMUNIT_CLOCK_GATE_DISABLE);
6473         I915_WRITE(PCH_3DCGDIS1,
6474                    VFMUNIT_CLOCK_GATE_DISABLE);
6475
6476         /*
6477          * According to the spec the following bits should be set in
6478          * order to enable memory self-refresh
6479          * The bit 22/21 of 0x42004
6480          * The bit 5 of 0x42020
6481          * The bit 15 of 0x45000
6482          */
6483         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6484                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6485                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6486         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6487         I915_WRITE(DISP_ARB_CTL,
6488                    (I915_READ(DISP_ARB_CTL) |
6489                     DISP_FBC_WM_DIS));
6490
6491         ilk_init_lp_watermarks(dev);
6492
6493         /*
6494          * Based on the document from hardware guys the following bits
6495          * should be set unconditionally in order to enable FBC.
6496          * The bit 22 of 0x42000
6497          * The bit 22 of 0x42004
6498          * The bit 7,8,9 of 0x42020.
6499          */
6500         if (IS_IRONLAKE_M(dev)) {
6501                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6502                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6503                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6504                            ILK_FBCQ_DIS);
6505                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6506                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6507                            ILK_DPARB_GATE);
6508         }
6509
6510         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6511
6512         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6513                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6514                    ILK_ELPIN_409_SELECT);
6515         I915_WRITE(_3D_CHICKEN2,
6516                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6517                    _3D_CHICKEN2_WM_READ_PIPELINED);
6518
6519         /* WaDisableRenderCachePipelinedFlush:ilk */
6520         I915_WRITE(CACHE_MODE_0,
6521                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6522
6523         /* WaDisable_RenderCache_OperationalFlush:ilk */
6524         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6525
6526         g4x_disable_trickle_feed(dev);
6527
6528         ibx_init_clock_gating(dev);
6529 }
6530
6531 static void cpt_init_clock_gating(struct drm_device *dev)
6532 {
6533         struct drm_i915_private *dev_priv = dev->dev_private;
6534         int pipe;
6535         uint32_t val;
6536
6537         /*
6538          * On Ibex Peak and Cougar Point, we need to disable clock
6539          * gating for the panel power sequencer or it will fail to
6540          * start up when no ports are active.
6541          */
6542         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6543                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6544                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6545         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6546                    DPLS_EDP_PPS_FIX_DIS);
6547         /* The below fixes the weird display corruption, a few pixels shifted
6548          * downward, on (only) LVDS of some HP laptops with IVY.
6549          */
6550         for_each_pipe(dev_priv, pipe) {
6551                 val = I915_READ(TRANS_CHICKEN2(pipe));
6552                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6553                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6554                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6555                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6556                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6557                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6558                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6559                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6560         }
6561         /* WADP0ClockGatingDisable */
6562         for_each_pipe(dev_priv, pipe) {
6563                 I915_WRITE(TRANS_CHICKEN1(pipe),
6564                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6565         }
6566 }
6567
6568 static void gen6_check_mch_setup(struct drm_device *dev)
6569 {
6570         struct drm_i915_private *dev_priv = dev->dev_private;
6571         uint32_t tmp;
6572
6573         tmp = I915_READ(MCH_SSKPD);
6574         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6575                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6576                               tmp);
6577 }
6578
6579 static void gen6_init_clock_gating(struct drm_device *dev)
6580 {
6581         struct drm_i915_private *dev_priv = dev->dev_private;
6582         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6583
6584         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6585
6586         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6587                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6588                    ILK_ELPIN_409_SELECT);
6589
6590         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6591         I915_WRITE(_3D_CHICKEN,
6592                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6593
6594         /* WaDisable_RenderCache_OperationalFlush:snb */
6595         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6596
6597         /*
6598          * BSpec recoomends 8x4 when MSAA is used,
6599          * however in practice 16x4 seems fastest.
6600          *
6601          * Note that PS/WM thread counts depend on the WIZ hashing
6602          * disable bit, which we don't touch here, but it's good
6603          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6604          */
6605         I915_WRITE(GEN6_GT_MODE,
6606                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6607
6608         ilk_init_lp_watermarks(dev);
6609
6610         I915_WRITE(CACHE_MODE_0,
6611                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6612
6613         I915_WRITE(GEN6_UCGCTL1,
6614                    I915_READ(GEN6_UCGCTL1) |
6615                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6616                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6617
6618         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6619          * gating disable must be set.  Failure to set it results in
6620          * flickering pixels due to Z write ordering failures after
6621          * some amount of runtime in the Mesa "fire" demo, and Unigine
6622          * Sanctuary and Tropics, and apparently anything else with
6623          * alpha test or pixel discard.
6624          *
6625          * According to the spec, bit 11 (RCCUNIT) must also be set,
6626          * but we didn't debug actual testcases to find it out.
6627          *
6628          * WaDisableRCCUnitClockGating:snb
6629          * WaDisableRCPBUnitClockGating:snb
6630          */
6631         I915_WRITE(GEN6_UCGCTL2,
6632                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6633                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6634
6635         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6636         I915_WRITE(_3D_CHICKEN3,
6637                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6638
6639         /*
6640          * Bspec says:
6641          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6642          * 3DSTATE_SF number of SF output attributes is more than 16."
6643          */
6644         I915_WRITE(_3D_CHICKEN3,
6645                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6646
6647         /*
6648          * According to the spec the following bits should be
6649          * set in order to enable memory self-refresh and fbc:
6650          * The bit21 and bit22 of 0x42000
6651          * The bit21 and bit22 of 0x42004
6652          * The bit5 and bit7 of 0x42020
6653          * The bit14 of 0x70180
6654          * The bit14 of 0x71180
6655          *
6656          * WaFbcAsynchFlipDisableFbcQueue:snb
6657          */
6658         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6659                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6660                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6661         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6662                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6663                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6664         I915_WRITE(ILK_DSPCLK_GATE_D,
6665                    I915_READ(ILK_DSPCLK_GATE_D) |
6666                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6667                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6668
6669         g4x_disable_trickle_feed(dev);
6670
6671         cpt_init_clock_gating(dev);
6672
6673         gen6_check_mch_setup(dev);
6674 }
6675
6676 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6677 {
6678         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6679
6680         /*
6681          * WaVSThreadDispatchOverride:ivb,vlv
6682          *
6683          * This actually overrides the dispatch
6684          * mode for all thread types.
6685          */
6686         reg &= ~GEN7_FF_SCHED_MASK;
6687         reg |= GEN7_FF_TS_SCHED_HW;
6688         reg |= GEN7_FF_VS_SCHED_HW;
6689         reg |= GEN7_FF_DS_SCHED_HW;
6690
6691         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6692 }
6693
6694 static void lpt_init_clock_gating(struct drm_device *dev)
6695 {
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697
6698         /*
6699          * TODO: this bit should only be enabled when really needed, then
6700          * disabled when not needed anymore in order to save power.
6701          */
6702         if (HAS_PCH_LPT_LP(dev))
6703                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6704                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6705                            PCH_LP_PARTITION_LEVEL_DISABLE);
6706
6707         /* WADPOClockGatingDisable:hsw */
6708         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6709                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6710                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6711 }
6712
6713 static void lpt_suspend_hw(struct drm_device *dev)
6714 {
6715         struct drm_i915_private *dev_priv = dev->dev_private;
6716
6717         if (HAS_PCH_LPT_LP(dev)) {
6718                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6719
6720                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6721                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6722         }
6723 }
6724
6725 static void kabylake_init_clock_gating(struct drm_device *dev)
6726 {
6727         struct drm_i915_private *dev_priv = dev->dev_private;
6728
6729         gen9_init_clock_gating(dev);
6730
6731         /* WaDisableSDEUnitClockGating:kbl */
6732         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6733                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6734                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6735
6736         /* WaDisableGamClockGating:kbl */
6737         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6738                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6739                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
6740 }
6741
6742 static void skylake_init_clock_gating(struct drm_device *dev)
6743 {
6744         gen9_init_clock_gating(dev);
6745 }
6746
6747 static void broadwell_init_clock_gating(struct drm_device *dev)
6748 {
6749         struct drm_i915_private *dev_priv = dev->dev_private;
6750         enum pipe pipe;
6751         uint32_t misccpctl;
6752
6753         ilk_init_lp_watermarks(dev);
6754
6755         /* WaSwitchSolVfFArbitrationPriority:bdw */
6756         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6757
6758         /* WaPsrDPAMaskVBlankInSRD:bdw */
6759         I915_WRITE(CHICKEN_PAR1_1,
6760                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6761
6762         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6763         for_each_pipe(dev_priv, pipe) {
6764                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6765                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6766                            BDW_DPRS_MASK_VBLANK_SRD);
6767         }
6768
6769         /* WaVSRefCountFullforceMissDisable:bdw */
6770         /* WaDSRefCountFullforceMissDisable:bdw */
6771         I915_WRITE(GEN7_FF_THREAD_MODE,
6772                    I915_READ(GEN7_FF_THREAD_MODE) &
6773                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6774
6775         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6776                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6777
6778         /* WaDisableSDEUnitClockGating:bdw */
6779         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6780                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6781
6782         /*
6783          * WaProgramL3SqcReg1Default:bdw
6784          * WaTempDisableDOPClkGating:bdw
6785          */
6786         misccpctl = I915_READ(GEN7_MISCCPCTL);
6787         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6788         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6789         /*
6790          * Wait at least 100 clocks before re-enabling clock gating. See
6791          * the definition of L3SQCREG1 in BSpec.
6792          */
6793         POSTING_READ(GEN8_L3SQCREG1);
6794         udelay(1);
6795         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6796
6797         /*
6798          * WaGttCachingOffByDefault:bdw
6799          * GTT cache may not work with big pages, so if those
6800          * are ever enabled GTT cache may need to be disabled.
6801          */
6802         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6803
6804         lpt_init_clock_gating(dev);
6805 }
6806
6807 static void haswell_init_clock_gating(struct drm_device *dev)
6808 {
6809         struct drm_i915_private *dev_priv = dev->dev_private;
6810
6811         ilk_init_lp_watermarks(dev);
6812
6813         /* L3 caching of data atomics doesn't work -- disable it. */
6814         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6815         I915_WRITE(HSW_ROW_CHICKEN3,
6816                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6817
6818         /* This is required by WaCatErrorRejectionIssue:hsw */
6819         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6820                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6821                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6822
6823         /* WaVSRefCountFullforceMissDisable:hsw */
6824         I915_WRITE(GEN7_FF_THREAD_MODE,
6825                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6826
6827         /* WaDisable_RenderCache_OperationalFlush:hsw */
6828         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6829
6830         /* enable HiZ Raw Stall Optimization */
6831         I915_WRITE(CACHE_MODE_0_GEN7,
6832                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6833
6834         /* WaDisable4x2SubspanOptimization:hsw */
6835         I915_WRITE(CACHE_MODE_1,
6836                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6837
6838         /*
6839          * BSpec recommends 8x4 when MSAA is used,
6840          * however in practice 16x4 seems fastest.
6841          *
6842          * Note that PS/WM thread counts depend on the WIZ hashing
6843          * disable bit, which we don't touch here, but it's good
6844          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6845          */
6846         I915_WRITE(GEN7_GT_MODE,
6847                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6848
6849         /* WaSampleCChickenBitEnable:hsw */
6850         I915_WRITE(HALF_SLICE_CHICKEN3,
6851                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6852
6853         /* WaSwitchSolVfFArbitrationPriority:hsw */
6854         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6855
6856         /* WaRsPkgCStateDisplayPMReq:hsw */
6857         I915_WRITE(CHICKEN_PAR1_1,
6858                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6859
6860         lpt_init_clock_gating(dev);
6861 }
6862
6863 static void ivybridge_init_clock_gating(struct drm_device *dev)
6864 {
6865         struct drm_i915_private *dev_priv = dev->dev_private;
6866         uint32_t snpcr;
6867
6868         ilk_init_lp_watermarks(dev);
6869
6870         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6871
6872         /* WaDisableEarlyCull:ivb */
6873         I915_WRITE(_3D_CHICKEN3,
6874                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6875
6876         /* WaDisableBackToBackFlipFix:ivb */
6877         I915_WRITE(IVB_CHICKEN3,
6878                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6879                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6880
6881         /* WaDisablePSDDualDispatchEnable:ivb */
6882         if (IS_IVB_GT1(dev))
6883                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6884                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6885
6886         /* WaDisable_RenderCache_OperationalFlush:ivb */
6887         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6888
6889         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6890         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6891                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6892
6893         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6894         I915_WRITE(GEN7_L3CNTLREG1,
6895                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6896         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6897                    GEN7_WA_L3_CHICKEN_MODE);
6898         if (IS_IVB_GT1(dev))
6899                 I915_WRITE(GEN7_ROW_CHICKEN2,
6900                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6901         else {
6902                 /* must write both registers */
6903                 I915_WRITE(GEN7_ROW_CHICKEN2,
6904                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6905                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6906                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6907         }
6908
6909         /* WaForceL3Serialization:ivb */
6910         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6911                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6912
6913         /*
6914          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6915          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6916          */
6917         I915_WRITE(GEN6_UCGCTL2,
6918                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6919
6920         /* This is required by WaCatErrorRejectionIssue:ivb */
6921         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6922                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6923                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6924
6925         g4x_disable_trickle_feed(dev);
6926
6927         gen7_setup_fixed_func_scheduler(dev_priv);
6928
6929         if (0) { /* causes HiZ corruption on ivb:gt1 */
6930                 /* enable HiZ Raw Stall Optimization */
6931                 I915_WRITE(CACHE_MODE_0_GEN7,
6932                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6933         }
6934
6935         /* WaDisable4x2SubspanOptimization:ivb */
6936         I915_WRITE(CACHE_MODE_1,
6937                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6938
6939         /*
6940          * BSpec recommends 8x4 when MSAA is used,
6941          * however in practice 16x4 seems fastest.
6942          *
6943          * Note that PS/WM thread counts depend on the WIZ hashing
6944          * disable bit, which we don't touch here, but it's good
6945          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6946          */
6947         I915_WRITE(GEN7_GT_MODE,
6948                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6949
6950         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6951         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6952         snpcr |= GEN6_MBC_SNPCR_MED;
6953         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6954
6955         if (!HAS_PCH_NOP(dev))
6956                 cpt_init_clock_gating(dev);
6957
6958         gen6_check_mch_setup(dev);
6959 }
6960
6961 static void valleyview_init_clock_gating(struct drm_device *dev)
6962 {
6963         struct drm_i915_private *dev_priv = dev->dev_private;
6964
6965         /* WaDisableEarlyCull:vlv */
6966         I915_WRITE(_3D_CHICKEN3,
6967                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6968
6969         /* WaDisableBackToBackFlipFix:vlv */
6970         I915_WRITE(IVB_CHICKEN3,
6971                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6972                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6973
6974         /* WaPsdDispatchEnable:vlv */
6975         /* WaDisablePSDDualDispatchEnable:vlv */
6976         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6977                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6978                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6979
6980         /* WaDisable_RenderCache_OperationalFlush:vlv */
6981         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6982
6983         /* WaForceL3Serialization:vlv */
6984         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6985                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6986
6987         /* WaDisableDopClockGating:vlv */
6988         I915_WRITE(GEN7_ROW_CHICKEN2,
6989                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6990
6991         /* This is required by WaCatErrorRejectionIssue:vlv */
6992         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6993                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6994                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6995
6996         gen7_setup_fixed_func_scheduler(dev_priv);
6997
6998         /*
6999          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7000          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7001          */
7002         I915_WRITE(GEN6_UCGCTL2,
7003                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7004
7005         /* WaDisableL3Bank2xClockGate:vlv
7006          * Disabling L3 clock gating- MMIO 940c[25] = 1
7007          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7008         I915_WRITE(GEN7_UCGCTL4,
7009                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7010
7011         /*
7012          * BSpec says this must be set, even though
7013          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7014          */
7015         I915_WRITE(CACHE_MODE_1,
7016                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7017
7018         /*
7019          * BSpec recommends 8x4 when MSAA is used,
7020          * however in practice 16x4 seems fastest.
7021          *
7022          * Note that PS/WM thread counts depend on the WIZ hashing
7023          * disable bit, which we don't touch here, but it's good
7024          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7025          */
7026         I915_WRITE(GEN7_GT_MODE,
7027                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7028
7029         /*
7030          * WaIncreaseL3CreditsForVLVB0:vlv
7031          * This is the hardware default actually.
7032          */
7033         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7034
7035         /*
7036          * WaDisableVLVClockGating_VBIIssue:vlv
7037          * Disable clock gating on th GCFG unit to prevent a delay
7038          * in the reporting of vblank events.
7039          */
7040         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7041 }
7042
7043 static void cherryview_init_clock_gating(struct drm_device *dev)
7044 {
7045         struct drm_i915_private *dev_priv = dev->dev_private;
7046
7047         /* WaVSRefCountFullforceMissDisable:chv */
7048         /* WaDSRefCountFullforceMissDisable:chv */
7049         I915_WRITE(GEN7_FF_THREAD_MODE,
7050                    I915_READ(GEN7_FF_THREAD_MODE) &
7051                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7052
7053         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7054         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7055                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7056
7057         /* WaDisableCSUnitClockGating:chv */
7058         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7059                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7060
7061         /* WaDisableSDEUnitClockGating:chv */
7062         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7063                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7064
7065         /*
7066          * GTT cache may not work with big pages, so if those
7067          * are ever enabled GTT cache may need to be disabled.
7068          */
7069         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7070 }
7071
7072 static void g4x_init_clock_gating(struct drm_device *dev)
7073 {
7074         struct drm_i915_private *dev_priv = dev->dev_private;
7075         uint32_t dspclk_gate;
7076
7077         I915_WRITE(RENCLK_GATE_D1, 0);
7078         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7079                    GS_UNIT_CLOCK_GATE_DISABLE |
7080                    CL_UNIT_CLOCK_GATE_DISABLE);
7081         I915_WRITE(RAMCLK_GATE_D, 0);
7082         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7083                 OVRUNIT_CLOCK_GATE_DISABLE |
7084                 OVCUNIT_CLOCK_GATE_DISABLE;
7085         if (IS_GM45(dev))
7086                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7087         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7088
7089         /* WaDisableRenderCachePipelinedFlush */
7090         I915_WRITE(CACHE_MODE_0,
7091                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7092
7093         /* WaDisable_RenderCache_OperationalFlush:g4x */
7094         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7095
7096         g4x_disable_trickle_feed(dev);
7097 }
7098
7099 static void crestline_init_clock_gating(struct drm_device *dev)
7100 {
7101         struct drm_i915_private *dev_priv = dev->dev_private;
7102
7103         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7104         I915_WRITE(RENCLK_GATE_D2, 0);
7105         I915_WRITE(DSPCLK_GATE_D, 0);
7106         I915_WRITE(RAMCLK_GATE_D, 0);
7107         I915_WRITE16(DEUC, 0);
7108         I915_WRITE(MI_ARB_STATE,
7109                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7110
7111         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7112         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7113 }
7114
7115 static void broadwater_init_clock_gating(struct drm_device *dev)
7116 {
7117         struct drm_i915_private *dev_priv = dev->dev_private;
7118
7119         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7120                    I965_RCC_CLOCK_GATE_DISABLE |
7121                    I965_RCPB_CLOCK_GATE_DISABLE |
7122                    I965_ISC_CLOCK_GATE_DISABLE |
7123                    I965_FBC_CLOCK_GATE_DISABLE);
7124         I915_WRITE(RENCLK_GATE_D2, 0);
7125         I915_WRITE(MI_ARB_STATE,
7126                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7127
7128         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7129         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7130 }
7131
7132 static void gen3_init_clock_gating(struct drm_device *dev)
7133 {
7134         struct drm_i915_private *dev_priv = dev->dev_private;
7135         u32 dstate = I915_READ(D_STATE);
7136
7137         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7138                 DSTATE_DOT_CLOCK_GATING;
7139         I915_WRITE(D_STATE, dstate);
7140
7141         if (IS_PINEVIEW(dev))
7142                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7143
7144         /* IIR "flip pending" means done if this bit is set */
7145         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7146
7147         /* interrupts should cause a wake up from C3 */
7148         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7149
7150         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7151         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7152
7153         I915_WRITE(MI_ARB_STATE,
7154                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7155 }
7156
7157 static void i85x_init_clock_gating(struct drm_device *dev)
7158 {
7159         struct drm_i915_private *dev_priv = dev->dev_private;
7160
7161         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7162
7163         /* interrupts should cause a wake up from C3 */
7164         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7165                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7166
7167         I915_WRITE(MEM_MODE,
7168                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7169 }
7170
7171 static void i830_init_clock_gating(struct drm_device *dev)
7172 {
7173         struct drm_i915_private *dev_priv = dev->dev_private;
7174
7175         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7176
7177         I915_WRITE(MEM_MODE,
7178                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7179                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7180 }
7181
7182 void intel_init_clock_gating(struct drm_device *dev)
7183 {
7184         struct drm_i915_private *dev_priv = dev->dev_private;
7185
7186         dev_priv->display.init_clock_gating(dev);
7187 }
7188
7189 void intel_suspend_hw(struct drm_device *dev)
7190 {
7191         if (HAS_PCH_LPT(dev))
7192                 lpt_suspend_hw(dev);
7193 }
7194
7195 static void nop_init_clock_gating(struct drm_device *dev)
7196 {
7197         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7198 }
7199
7200 /**
7201  * intel_init_clock_gating_hooks - setup the clock gating hooks
7202  * @dev_priv: device private
7203  *
7204  * Setup the hooks that configure which clocks of a given platform can be
7205  * gated and also apply various GT and display specific workarounds for these
7206  * platforms. Note that some GT specific workarounds are applied separately
7207  * when GPU contexts or batchbuffers start their execution.
7208  */
7209 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7210 {
7211         if (IS_SKYLAKE(dev_priv))
7212                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7213         else if (IS_KABYLAKE(dev_priv))
7214                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7215         else if (IS_BROXTON(dev_priv))
7216                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7217         else if (IS_BROADWELL(dev_priv))
7218                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7219         else if (IS_CHERRYVIEW(dev_priv))
7220                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7221         else if (IS_HASWELL(dev_priv))
7222                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7223         else if (IS_IVYBRIDGE(dev_priv))
7224                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7225         else if (IS_VALLEYVIEW(dev_priv))
7226                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7227         else if (IS_GEN6(dev_priv))
7228                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7229         else if (IS_GEN5(dev_priv))
7230                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7231         else if (IS_G4X(dev_priv))
7232                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7233         else if (IS_CRESTLINE(dev_priv))
7234                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7235         else if (IS_BROADWATER(dev_priv))
7236                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7237         else if (IS_GEN3(dev_priv))
7238                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7239         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7240                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7241         else if (IS_GEN2(dev_priv))
7242                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7243         else {
7244                 MISSING_CASE(INTEL_DEVID(dev_priv));
7245                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7246         }
7247 }
7248
7249 /* Set up chip specific power management-related functions */
7250 void intel_init_pm(struct drm_device *dev)
7251 {
7252         struct drm_i915_private *dev_priv = dev->dev_private;
7253
7254         intel_fbc_init(dev_priv);
7255
7256         /* For cxsr */
7257         if (IS_PINEVIEW(dev))
7258                 i915_pineview_get_mem_freq(dev);
7259         else if (IS_GEN5(dev))
7260                 i915_ironlake_get_mem_freq(dev);
7261
7262         /* For FIFO watermark updates */
7263         if (INTEL_INFO(dev)->gen >= 9) {
7264                 skl_setup_wm_latency(dev);
7265                 dev_priv->display.update_wm = skl_update_wm;
7266         } else if (HAS_PCH_SPLIT(dev)) {
7267                 ilk_setup_wm_latency(dev);
7268
7269                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7270                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7271                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7272                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7273                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7274                         dev_priv->display.compute_intermediate_wm =
7275                                 ilk_compute_intermediate_wm;
7276                         dev_priv->display.initial_watermarks =
7277                                 ilk_initial_watermarks;
7278                         dev_priv->display.optimize_watermarks =
7279                                 ilk_optimize_watermarks;
7280                 } else {
7281                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7282                                       "Disable CxSR\n");
7283                 }
7284         } else if (IS_CHERRYVIEW(dev)) {
7285                 vlv_setup_wm_latency(dev);
7286                 dev_priv->display.update_wm = vlv_update_wm;
7287         } else if (IS_VALLEYVIEW(dev)) {
7288                 vlv_setup_wm_latency(dev);
7289                 dev_priv->display.update_wm = vlv_update_wm;
7290         } else if (IS_PINEVIEW(dev)) {
7291                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7292                                             dev_priv->is_ddr3,
7293                                             dev_priv->fsb_freq,
7294                                             dev_priv->mem_freq)) {
7295                         DRM_INFO("failed to find known CxSR latency "
7296                                  "(found ddr%s fsb freq %d, mem freq %d), "
7297                                  "disabling CxSR\n",
7298                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7299                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7300                         /* Disable CxSR and never update its watermark again */
7301                         intel_set_memory_cxsr(dev_priv, false);
7302                         dev_priv->display.update_wm = NULL;
7303                 } else
7304                         dev_priv->display.update_wm = pineview_update_wm;
7305         } else if (IS_G4X(dev)) {
7306                 dev_priv->display.update_wm = g4x_update_wm;
7307         } else if (IS_GEN4(dev)) {
7308                 dev_priv->display.update_wm = i965_update_wm;
7309         } else if (IS_GEN3(dev)) {
7310                 dev_priv->display.update_wm = i9xx_update_wm;
7311                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7312         } else if (IS_GEN2(dev)) {
7313                 if (INTEL_INFO(dev)->num_pipes == 1) {
7314                         dev_priv->display.update_wm = i845_update_wm;
7315                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7316                 } else {
7317                         dev_priv->display.update_wm = i9xx_update_wm;
7318                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7319                 }
7320         } else {
7321                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7322         }
7323 }
7324
7325 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7326 {
7327         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7328
7329         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7330                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7331                 return -EAGAIN;
7332         }
7333
7334         I915_WRITE(GEN6_PCODE_DATA, *val);
7335         I915_WRITE(GEN6_PCODE_DATA1, 0);
7336         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7337
7338         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7339                      500)) {
7340                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7341                 return -ETIMEDOUT;
7342         }
7343
7344         *val = I915_READ(GEN6_PCODE_DATA);
7345         I915_WRITE(GEN6_PCODE_DATA, 0);
7346
7347         return 0;
7348 }
7349
7350 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7351 {
7352         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7353
7354         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7355                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7356                 return -EAGAIN;
7357         }
7358
7359         I915_WRITE(GEN6_PCODE_DATA, val);
7360         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7361
7362         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7363                      500)) {
7364                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7365                 return -ETIMEDOUT;
7366         }
7367
7368         I915_WRITE(GEN6_PCODE_DATA, 0);
7369
7370         return 0;
7371 }
7372
7373 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7374 {
7375         /*
7376          * N = val - 0xb7
7377          * Slow = Fast = GPLL ref * N
7378          */
7379         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7380 }
7381
7382 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7383 {
7384         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7385 }
7386
7387 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7388 {
7389         /*
7390          * N = val / 2
7391          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7392          */
7393         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7394 }
7395
7396 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7397 {
7398         /* CHV needs even values */
7399         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7400 }
7401
7402 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7403 {
7404         if (IS_GEN9(dev_priv))
7405                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7406                                          GEN9_FREQ_SCALER);
7407         else if (IS_CHERRYVIEW(dev_priv))
7408                 return chv_gpu_freq(dev_priv, val);
7409         else if (IS_VALLEYVIEW(dev_priv))
7410                 return byt_gpu_freq(dev_priv, val);
7411         else
7412                 return val * GT_FREQUENCY_MULTIPLIER;
7413 }
7414
7415 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7416 {
7417         if (IS_GEN9(dev_priv))
7418                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7419                                          GT_FREQUENCY_MULTIPLIER);
7420         else if (IS_CHERRYVIEW(dev_priv))
7421                 return chv_freq_opcode(dev_priv, val);
7422         else if (IS_VALLEYVIEW(dev_priv))
7423                 return byt_freq_opcode(dev_priv, val);
7424         else
7425                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7426 }
7427
7428 struct request_boost {
7429         struct work_struct work;
7430         struct drm_i915_gem_request *req;
7431 };
7432
7433 static void __intel_rps_boost_work(struct work_struct *work)
7434 {
7435         struct request_boost *boost = container_of(work, struct request_boost, work);
7436         struct drm_i915_gem_request *req = boost->req;
7437
7438         if (!i915_gem_request_completed(req, true))
7439                 gen6_rps_boost(to_i915(req->engine->dev), NULL,
7440                                req->emitted_jiffies);
7441
7442         i915_gem_request_unreference__unlocked(req);
7443         kfree(boost);
7444 }
7445
7446 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7447                                        struct drm_i915_gem_request *req)
7448 {
7449         struct request_boost *boost;
7450
7451         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7452                 return;
7453
7454         if (i915_gem_request_completed(req, true))
7455                 return;
7456
7457         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7458         if (boost == NULL)
7459                 return;
7460
7461         i915_gem_request_reference(req);
7462         boost->req = req;
7463
7464         INIT_WORK(&boost->work, __intel_rps_boost_work);
7465         queue_work(to_i915(dev)->wq, &boost->work);
7466 }
7467
7468 void intel_pm_setup(struct drm_device *dev)
7469 {
7470         struct drm_i915_private *dev_priv = dev->dev_private;
7471
7472         mutex_init(&dev_priv->rps.hw_lock);
7473         spin_lock_init(&dev_priv->rps.client_lock);
7474
7475         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7476                           intel_gen6_powersave_work);
7477         INIT_LIST_HEAD(&dev_priv->rps.clients);
7478         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7479         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7480
7481         dev_priv->pm.suspended = false;
7482         atomic_set(&dev_priv->pm.wakeref_count, 0);
7483         atomic_set(&dev_priv->pm.atomic_seq, 0);
7484 }