drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 int __intel_ring_space(int head, int tail, int size)
  38 {
  39         int space = head - tail;
  40         if (space <= 0)
  41                 space += size;
  42         return space - I915_RING_FREE_SPACE;
  43 }
  44
  45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  46 {
  47         if (ringbuf->last_retired_head != -1) {
  48                 ringbuf->head = ringbuf->last_retired_head;
  49                 ringbuf->last_retired_head = -1;
  50         }
  51
  52         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  53                                             ringbuf->tail, ringbuf->size);
  54 }
  55
  56 bool intel_engine_stopped(struct intel_engine_cs *engine)
  57 {
  58         struct drm_i915_private *dev_priv = engine->dev->dev_private;
  59         return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
  60 }
  61
  62 static void __intel_ring_advance(struct intel_engine_cs *engine)
  63 {
  64         struct intel_ringbuffer *ringbuf = engine->buffer;
  65         ringbuf->tail &= ringbuf->size - 1;
  66         if (intel_engine_stopped(engine))
  67                 return;
  68         engine->write_tail(engine, ringbuf->tail);
  69 }
  70
  71 static int
  72 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  73                        u32      invalidate_domains,
  74                        u32      flush_domains)
  75 {
  76         struct intel_engine_cs *engine = req->engine;
  77         u32 cmd;
  78         int ret;
  79
  80         cmd = MI_FLUSH;
  81         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  82                 cmd |= MI_NO_WRITE_FLUSH;
  83
  84         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  85                 cmd |= MI_READ_FLUSH;
  86
  87         ret = intel_ring_begin(req, 2);
  88         if (ret)
  89                 return ret;
  90
  91         intel_ring_emit(engine, cmd);
  92         intel_ring_emit(engine, MI_NOOP);
  93         intel_ring_advance(engine);
  94
  95         return 0;
  96 }
  97
  98 static int
  99 gen4_render_ring_flush(struct drm_i915_gem_request *req,
 100                        u32      invalidate_domains,
 101                        u32      flush_domains)
 102 {
 103         struct intel_engine_cs *engine = req->engine;
 104         struct drm_device *dev = engine->dev;
 105         u32 cmd;
 106         int ret;
 107
 108         /*
 109          * read/write caches:
 110          *
 111          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 112          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 113          * also flushed at 2d versus 3d pipeline switches.
 114          *
 115          * read-only caches:
 116          *
 117          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 118          * MI_READ_FLUSH is set, and is always flushed on 965.
 119          *
 120          * I915_GEM_DOMAIN_COMMAND may not exist?
 121          *
 122          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 123          * invalidated when MI_EXE_FLUSH is set.
 124          *
 125          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 126          * invalidated with every MI_FLUSH.
 127          *
 128          * TLBs:
 129          *
 130          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 131          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 132          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 133          * are flushed at any MI_FLUSH.
 134          */
 135
 136         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 137         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 138                 cmd &= ~MI_NO_WRITE_FLUSH;
 139         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 140                 cmd |= MI_EXE_FLUSH;
 141
 142         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 143             (IS_G4X(dev) || IS_GEN5(dev)))
 144                 cmd |= MI_INVALIDATE_ISP;
 145
 146         ret = intel_ring_begin(req, 2);
 147         if (ret)
 148                 return ret;
 149
 150         intel_ring_emit(engine, cmd);
 151         intel_ring_emit(engine, MI_NOOP);
 152         intel_ring_advance(engine);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 159  * implementing two workarounds on gen6.  From section 1.4.7.1
 160  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 161  *
 162  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 163  * produced by non-pipelined state commands), software needs to first
 164  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 165  * 0.
 166  *
 167  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 168  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 169  *
 170  * And the workaround for these two requires this workaround first:
 171  *
 172  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 173  * BEFORE the pipe-control with a post-sync op and no write-cache
 174  * flushes.
 175  *
 176  * And this last workaround is tricky because of the requirements on
 177  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 178  * volume 2 part 1:
 179  *
 180  *     "1 of the following must also be set:
 181  *      - Render Target Cache Flush Enable ([12] of DW1)
 182  *      - Depth Cache Flush Enable ([0] of DW1)
 183  *      - Stall at Pixel Scoreboard ([1] of DW1)
 184  *      - Depth Stall ([13] of DW1)
 185  *      - Post-Sync Operation ([13] of DW1)
 186  *      - Notify Enable ([8] of DW1)"
 187  *
 188  * The cache flushes require the workaround flush that triggered this
 189  * one, so we can't use it.  Depth stall would trigger the same.
 190  * Post-sync nonzero is what triggered this second workaround, so we
 191  * can't use that one either.  Notify enable is IRQs, which aren't
 192  * really our business.  That leaves only stall at scoreboard.
 193  */
 194 static int
 195 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 196 {
 197         struct intel_engine_cs *engine = req->engine;
 198         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 199         int ret;
 200
 201         ret = intel_ring_begin(req, 6);
 202         if (ret)
 203                 return ret;
 204
 205         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 206         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 207                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 208         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 209         intel_ring_emit(engine, 0); /* low dword */
 210         intel_ring_emit(engine, 0); /* high dword */
 211         intel_ring_emit(engine, MI_NOOP);
 212         intel_ring_advance(engine);
 213
 214         ret = intel_ring_begin(req, 6);
 215         if (ret)
 216                 return ret;
 217
 218         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 219         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 220         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 221         intel_ring_emit(engine, 0);
 222         intel_ring_emit(engine, 0);
 223         intel_ring_emit(engine, MI_NOOP);
 224         intel_ring_advance(engine);
 225
 226         return 0;
 227 }
 228
 229 static int
 230 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 231                        u32 invalidate_domains, u32 flush_domains)
 232 {
 233         struct intel_engine_cs *engine = req->engine;
 234         u32 flags = 0;
 235         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 236         int ret;
 237
 238         /* Force SNB workarounds for PIPE_CONTROL flushes */
 239         ret = intel_emit_post_sync_nonzero_flush(req);
 240         if (ret)
 241                 return ret;
 242
 243         /* Just flush everything.  Experiments have shown that reducing the
 244          * number of bits based on the write domains has little performance
 245          * impact.
 246          */
 247         if (flush_domains) {
 248                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 249                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 250                 /*
 251                  * Ensure that any following seqno writes only happen
 252                  * when the render cache is indeed flushed.
 253                  */
 254                 flags |= PIPE_CONTROL_CS_STALL;
 255         }
 256         if (invalidate_domains) {
 257                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 258                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 259                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 260                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 261                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 262                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 263                 /*
 264                  * TLB invalidate requires a post-sync write.
 265                  */
 266                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 267         }
 268
 269         ret = intel_ring_begin(req, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(engine, flags);
 275         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 276         intel_ring_emit(engine, 0);
 277         intel_ring_advance(engine);
 278
 279         return 0;
 280 }
 281
 282 static int
 283 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 284 {
 285         struct intel_engine_cs *engine = req->engine;
 286         int ret;
 287
 288         ret = intel_ring_begin(req, 4);
 289         if (ret)
 290                 return ret;
 291
 292         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 293         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 294                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 295         intel_ring_emit(engine, 0);
 296         intel_ring_emit(engine, 0);
 297         intel_ring_advance(engine);
 298
 299         return 0;
 300 }
 301
 302 static int
 303 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 304                        u32 invalidate_domains, u32 flush_domains)
 305 {
 306         struct intel_engine_cs *engine = req->engine;
 307         u32 flags = 0;
 308         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 309         int ret;
 310
 311         /*
 312          * Ensure that any following seqno writes only happen when the render
 313          * cache is indeed flushed.
 314          *
 315          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 316          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 317          * don't try to be clever and just set it unconditionally.
 318          */
 319         flags |= PIPE_CONTROL_CS_STALL;
 320
 321         /* Just flush everything.  Experiments have shown that reducing the
 322          * number of bits based on the write domains has little performance
 323          * impact.
 324          */
 325         if (flush_domains) {
 326                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 327                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 329                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 339                 /*
 340                  * TLB invalidate requires a post-sync write.
 341                  */
 342                 flags |= PIPE_CONTROL_QW_WRITE;
 343                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 344
 345                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 346
 347                 /* Workaround: we must issue a pipe_control with CS-stall bit
 348                  * set before a pipe_control command that has the state cache
 349                  * invalidate bit set. */
 350                 gen7_render_ring_cs_stall_wa(req);
 351         }
 352
 353         ret = intel_ring_begin(req, 4);
 354         if (ret)
 355                 return ret;
 356
 357         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 358         intel_ring_emit(engine, flags);
 359         intel_ring_emit(engine, scratch_addr);
 360         intel_ring_emit(engine, 0);
 361         intel_ring_advance(engine);
 362
 363         return 0;
 364 }
 365
 366 static int
 367 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 368                        u32 flags, u32 scratch_addr)
 369 {
 370         struct intel_engine_cs *engine = req->engine;
 371         int ret;
 372
 373         ret = intel_ring_begin(req, 6);
 374         if (ret)
 375                 return ret;
 376
 377         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 378         intel_ring_emit(engine, flags);
 379         intel_ring_emit(engine, scratch_addr);
 380         intel_ring_emit(engine, 0);
 381         intel_ring_emit(engine, 0);
 382         intel_ring_emit(engine, 0);
 383         intel_ring_advance(engine);
 384
 385         return 0;
 386 }
 387
 388 static int
 389 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 390                        u32 invalidate_domains, u32 flush_domains)
 391 {
 392         u32 flags = 0;
 393         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 394         int ret;
 395
 396         flags |= PIPE_CONTROL_CS_STALL;
 397
 398         if (flush_domains) {
 399                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 400                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 401                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 402                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 403         }
 404         if (invalidate_domains) {
 405                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 406                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 407                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 408                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 409                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 410                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 411                 flags |= PIPE_CONTROL_QW_WRITE;
 412                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 413
 414                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 415                 ret = gen8_emit_pipe_control(req,
 416                                              PIPE_CONTROL_CS_STALL |
 417                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 418                                              0);
 419                 if (ret)
 420                         return ret;
 421         }
 422
 423         return gen8_emit_pipe_control(req, flags, scratch_addr);
 424 }
 425
 426 static void ring_write_tail(struct intel_engine_cs *engine,
 427                             u32 value)
 428 {
 429         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 430         I915_WRITE_TAIL(engine, value);
 431 }
 432
 433 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 434 {
 435         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 436         u64 acthd;
 437
 438         if (INTEL_INFO(engine->dev)->gen >= 8)
 439                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 440                                          RING_ACTHD_UDW(engine->mmio_base));
 441         else if (INTEL_INFO(engine->dev)->gen >= 4)
 442                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 443         else
 444                 acthd = I915_READ(ACTHD);
 445
 446         return acthd;
 447 }
 448
 449 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 450 {
 451         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 452         u32 addr;
 453
 454         addr = dev_priv->status_page_dmah->busaddr;
 455         if (INTEL_INFO(engine->dev)->gen >= 4)
 456                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 457         I915_WRITE(HWS_PGA, addr);
 458 }
 459
 460 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 461 {
 462         struct drm_device *dev = engine->dev;
 463         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 464         i915_reg_t mmio;
 465
 466         /* The ring status page addresses are no longer next to the rest of
 467          * the ring registers as of gen7.
 468          */
 469         if (IS_GEN7(dev)) {
 470                 switch (engine->id) {
 471                 case RCS:
 472                         mmio = RENDER_HWS_PGA_GEN7;
 473                         break;
 474                 case BCS:
 475                         mmio = BLT_HWS_PGA_GEN7;
 476                         break;
 477                 /*
 478                  * VCS2 actually doesn't exist on Gen7. Only shut up
 479                  * gcc switch check warning
 480                  */
 481                 case VCS2:
 482                 case VCS:
 483                         mmio = BSD_HWS_PGA_GEN7;
 484                         break;
 485                 case VECS:
 486                         mmio = VEBOX_HWS_PGA_GEN7;
 487                         break;
 488                 }
 489         } else if (IS_GEN6(engine->dev)) {
 490                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 491         } else {
 492                 /* XXX: gen8 returns to sanity */
 493                 mmio = RING_HWS_PGA(engine->mmio_base);
 494         }
 495
 496         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 497         POSTING_READ(mmio);
 498
 499         /*
 500          * Flush the TLB for this page
 501          *
 502          * FIXME: These two bits have disappeared on gen8, so a question
 503          * arises: do we still need this and if so how should we go about
 504          * invalidating the TLB?
 505          */
 506         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
 507                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 508
 509                 /* ring should be idle before issuing a sync flush*/
 510                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 511
 512                 I915_WRITE(reg,
 513                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 514                                               INSTPM_SYNC_FLUSH));
 515                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 516                              1000))
 517                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 518                                   engine->name);
 519         }
 520 }
 521
 522 static bool stop_ring(struct intel_engine_cs *engine)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(engine->dev);
 525
 526         if (!IS_GEN2(engine->dev)) {
 527                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 528                 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
 529                         DRM_ERROR("%s : timed out trying to stop ring\n",
 530                                   engine->name);
 531                         /* Sometimes we observe that the idle flag is not
 532                          * set even though the ring is empty. So double
 533                          * check before giving up.
 534                          */
 535                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 536                                 return false;
 537                 }
 538         }
 539
 540         I915_WRITE_CTL(engine, 0);
 541         I915_WRITE_HEAD(engine, 0);
 542         engine->write_tail(engine, 0);
 543
 544         if (!IS_GEN2(engine->dev)) {
 545                 (void)I915_READ_CTL(engine);
 546                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 547         }
 548
 549         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 550 }
 551
 552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 553 {
 554         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *engine)
 558 {
 559         struct drm_device *dev = engine->dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct intel_ringbuffer *ringbuf = engine->buffer;
 562         struct drm_i915_gem_object *obj = ringbuf->obj;
 563         int ret = 0;
 564
 565         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 566
 567         if (!stop_ring(engine)) {
 568                 /* G45 ring initialization often fails to reset head to zero */
 569                 DRM_DEBUG_KMS("%s head not reset to zero "
 570                               "ctl %08x head %08x tail %08x start %08x\n",
 571                               engine->name,
 572                               I915_READ_CTL(engine),
 573                               I915_READ_HEAD(engine),
 574                               I915_READ_TAIL(engine),
 575                               I915_READ_START(engine));
 576
 577                 if (!stop_ring(engine)) {
 578                         DRM_ERROR("failed to set %s head to zero "
 579                                   "ctl %08x head %08x tail %08x start %08x\n",
 580                                   engine->name,
 581                                   I915_READ_CTL(engine),
 582                                   I915_READ_HEAD(engine),
 583                                   I915_READ_TAIL(engine),
 584                                   I915_READ_START(engine));
 585                         ret = -EIO;
 586                         goto out;
 587                 }
 588         }
 589
 590         if (I915_NEED_GFX_HWS(dev))
 591                 intel_ring_setup_status_page(engine);
 592         else
 593                 ring_setup_phys_status_page(engine);
 594
 595         /* Enforce ordering by reading HEAD register back */
 596         I915_READ_HEAD(engine);
 597
 598         /* Initialize the ring. This must happen _after_ we've cleared the ring
 599          * registers with the above sequence (the readback of the HEAD registers
 600          * also enforces ordering), otherwise the hw might lose the new ring
 601          * register values. */
 602         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 603
 604         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 605         if (I915_READ_HEAD(engine))
 606                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 607                           engine->name, I915_READ_HEAD(engine));
 608         I915_WRITE_HEAD(engine, 0);
 609         (void)I915_READ_HEAD(engine);
 610
 611         I915_WRITE_CTL(engine,
 612                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 613                         | RING_VALID);
 614
 615         /* If the head is still not zero, the ring is dead */
 616         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 617                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 618                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 619                 DRM_ERROR("%s initialization failed "
 620                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 621                           engine->name,
 622                           I915_READ_CTL(engine),
 623                           I915_READ_CTL(engine) & RING_VALID,
 624                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 625                           I915_READ_START(engine),
 626                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 627                 ret = -EIO;
 628                 goto out;
 629         }
 630
 631         ringbuf->last_retired_head = -1;
 632         ringbuf->head = I915_READ_HEAD(engine);
 633         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 634         intel_ring_update_space(ringbuf);
 635
 636         intel_engine_init_hangcheck(engine);
 637
 638 out:
 639         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 640
 641         return ret;
 642 }
 643
 644 void
 645 intel_fini_pipe_control(struct intel_engine_cs *engine)
 646 {
 647         struct drm_device *dev = engine->dev;
 648
 649         if (engine->scratch.obj == NULL)
 650                 return;
 651
 652         if (INTEL_INFO(dev)->gen >= 5) {
 653                 kunmap(sg_page(engine->scratch.obj->pages->sgl));
 654                 i915_gem_object_ggtt_unpin(engine->scratch.obj);
 655         }
 656
 657         drm_gem_object_unreference(&engine->scratch.obj->base);
 658         engine->scratch.obj = NULL;
 659 }
 660
 661 int
 662 intel_init_pipe_control(struct intel_engine_cs *engine)
 663 {
 664         int ret;
 665
 666         WARN_ON(engine->scratch.obj);
 667
 668         engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
 669         if (engine->scratch.obj == NULL) {
 670                 DRM_ERROR("Failed to allocate seqno page\n");
 671                 ret = -ENOMEM;
 672                 goto err;
 673         }
 674
 675         ret = i915_gem_object_set_cache_level(engine->scratch.obj,
 676                                               I915_CACHE_LLC);
 677         if (ret)
 678                 goto err_unref;
 679
 680         ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
 681         if (ret)
 682                 goto err_unref;
 683
 684         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
 685         engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
 686         if (engine->scratch.cpu_page == NULL) {
 687                 ret = -ENOMEM;
 688                 goto err_unpin;
 689         }
 690
 691         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 692                          engine->name, engine->scratch.gtt_offset);
 693         return 0;
 694
 695 err_unpin:
 696         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 697 err_unref:
 698         drm_gem_object_unreference(&engine->scratch.obj->base);
 699 err:
 700         return ret;
 701 }
 702
 703 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 704 {
 705         int ret, i;
 706         struct intel_engine_cs *engine = req->engine;
 707         struct drm_device *dev = engine->dev;
 708         struct drm_i915_private *dev_priv = dev->dev_private;
 709         struct i915_workarounds *w = &dev_priv->workarounds;
 710
 711         if (w->count == 0)
 712                 return 0;
 713
 714         engine->gpu_caches_dirty = true;
 715         ret = intel_ring_flush_all_caches(req);
 716         if (ret)
 717                 return ret;
 718
 719         ret = intel_ring_begin(req, (w->count * 2 + 2));
 720         if (ret)
 721                 return ret;
 722
 723         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 724         for (i = 0; i < w->count; i++) {
 725                 intel_ring_emit_reg(engine, w->reg[i].addr);
 726                 intel_ring_emit(engine, w->reg[i].value);
 727         }
 728         intel_ring_emit(engine, MI_NOOP);
 729
 730         intel_ring_advance(engine);
 731
 732         engine->gpu_caches_dirty = true;
 733         ret = intel_ring_flush_all_caches(req);
 734         if (ret)
 735                 return ret;
 736
 737         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 738
 739         return 0;
 740 }
 741
 742 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 743 {
 744         int ret;
 745
 746         ret = intel_ring_workarounds_emit(req);
 747         if (ret != 0)
 748                 return ret;
 749
 750         ret = i915_gem_render_state_init(req);
 751         if (ret)
 752                 return ret;
 753
 754         return 0;
 755 }
 756
 757 static int wa_add(struct drm_i915_private *dev_priv,
 758                   i915_reg_t addr,
 759                   const u32 mask, const u32 val)
 760 {
 761         const u32 idx = dev_priv->workarounds.count;
 762
 763         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 764                 return -ENOSPC;
 765
 766         dev_priv->workarounds.reg[idx].addr = addr;
 767         dev_priv->workarounds.reg[idx].value = val;
 768         dev_priv->workarounds.reg[idx].mask = mask;
 769
 770         dev_priv->workarounds.count++;
 771
 772         return 0;
 773 }
 774
 775 #define WA_REG(addr, mask, val) do { \
 776                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 777                 if (r) \
 778                         return r; \
 779         } while (0)
 780
 781 #define WA_SET_BIT_MASKED(addr, mask) \
 782         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 783
 784 #define WA_CLR_BIT_MASKED(addr, mask) \
 785         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 786
 787 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 788         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 789
 790 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 791 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 792
 793 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 794
 795 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 796                                  i915_reg_t reg)
 797 {
 798         struct drm_i915_private *dev_priv = engine->dev->dev_private;
 799         struct i915_workarounds *wa = &dev_priv->workarounds;
 800         const uint32_t index = wa->hw_whitelist_count[engine->id];
 801
 802         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 803                 return -EINVAL;
 804
 805         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 806                  i915_mmio_reg_offset(reg));
 807         wa->hw_whitelist_count[engine->id]++;
 808
 809         return 0;
 810 }
 811
 812 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 813 {
 814         struct drm_device *dev = engine->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816
 817         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 818
 819         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 820         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 821
 822         /* WaDisablePartialInstShootdown:bdw,chv */
 823         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 824                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 825
 826         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 827          * workaround for for a possible hang in the unlikely event a TLB
 828          * invalidation occurs during a PSD flush.
 829          */
 830         /* WaForceEnableNonCoherent:bdw,chv */
 831         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 832         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 833                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 834                           HDC_FORCE_NON_COHERENT);
 835
 836         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 837          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 838          *  polygons in the same 8x4 pixel/sample area to be processed without
 839          *  stalling waiting for the earlier ones to write to Hierarchical Z
 840          *  buffer."
 841          *
 842          * This optimization is off by default for BDW and CHV; turn it on.
 843          */
 844         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 845
 846         /* Wa4x4STCOptimizationDisable:bdw,chv */
 847         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 848
 849         /*
 850          * BSpec recommends 8x4 when MSAA is used,
 851          * however in practice 16x4 seems fastest.
 852          *
 853          * Note that PS/WM thread counts depend on the WIZ hashing
 854          * disable bit, which we don't touch here, but it's good
 855          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 856          */
 857         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 858                             GEN6_WIZ_HASHING_MASK,
 859                             GEN6_WIZ_HASHING_16x4);
 860
 861         return 0;
 862 }
 863
 864 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 865 {
 866         int ret;
 867         struct drm_device *dev = engine->dev;
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         ret = gen8_init_workarounds(engine);
 871         if (ret)
 872                 return ret;
 873
 874         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 875         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 876
 877         /* WaDisableDopClockGating:bdw */
 878         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 879                           DOP_CLOCK_GATING_DISABLE);
 880
 881         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 882                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 883
 884         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 885                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 886                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 887                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 888                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 889
 890         return 0;
 891 }
 892
 893 static int chv_init_workarounds(struct intel_engine_cs *engine)
 894 {
 895         int ret;
 896         struct drm_device *dev = engine->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898
 899         ret = gen8_init_workarounds(engine);
 900         if (ret)
 901                 return ret;
 902
 903         /* WaDisableThreadStallDopClockGating:chv */
 904         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 905
 906         /* Improve HiZ throughput on CHV. */
 907         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 908
 909         return 0;
 910 }
 911
 912 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 913 {
 914         struct drm_device *dev = engine->dev;
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int ret;
 917
 918         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 919         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 920                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 921
 922         /* WaDisableKillLogic:bxt,skl,kbl */
 923         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 924                    ECOCHK_DIS_TLB);
 925
 926         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
 927         /* WaDisablePartialInstShootdown:skl,bxt,kbl */
 928         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 929                           FLOW_CONTROL_ENABLE |
 930                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 931
 932         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 933         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 934                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 935
 936         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 937         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 938             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 939                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 940                                   GEN9_DG_MIRROR_FIX_ENABLE);
 941
 942         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 943         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
 944             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
 945                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 946                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 947                 /*
 948                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 949                  * but we do that in per ctx batchbuffer as there is an issue
 950                  * with this register not getting restored on ctx restore
 951                  */
 952         }
 953
 954         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
 955         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 956         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 957                           GEN9_ENABLE_YV12_BUGFIX |
 958                           GEN9_ENABLE_GPGPU_PREEMPTION);
 959
 960         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
 961         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 962         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 963                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 964
 965         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 966         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 967                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 968
 969         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 970         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
 971             IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 972                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 973                                   PIXEL_MASK_CAMMING_DISABLE);
 974
 975         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 976         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 977                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 978                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 979
 980         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 981          * both tied to WaForceContextSaveRestoreNonCoherent
 982          * in some hsds for skl. We keep the tie for all gen9. The
 983          * documentation is a bit hazy and so we want to get common behaviour,
 984          * even though there is no clear evidence we would need both on kbl/bxt.
 985          * This area has been source of system hangs so we play it safe
 986          * and mimic the skl regardless of what bspec says.
 987          *
 988          * Use Force Non-Coherent whenever executing a 3D context. This
 989          * is a workaround for a possible hang in the unlikely event
 990          * a TLB invalidation occurs during a PSD flush.
 991          */
 992
 993         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 994         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 995                           HDC_FORCE_NON_COHERENT);
 996
 997         /* WaDisableHDCInvalidation:skl,bxt,kbl */
 998         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 999                    BDW_DISABLE_HDC_INVALIDATION);
1000
1001         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1002         if (IS_SKYLAKE(dev_priv) ||
1003             IS_KABYLAKE(dev_priv) ||
1004             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1005                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1006                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
1007
1008         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
1009         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1010
1011         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
1012         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1013                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
1014
1015         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1016         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1017         if (ret)
1018                 return ret;
1019
1020         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1021         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1022         if (ret)
1023                 return ret;
1024
1025         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1026         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1027         if (ret)
1028                 return ret;
1029
1030         return 0;
1031 }
1032
1033 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1034 {
1035         struct drm_device *dev = engine->dev;
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037         u8 vals[3] = { 0, 0, 0 };
1038         unsigned int i;
1039
1040         for (i = 0; i < 3; i++) {
1041                 u8 ss;
1042
1043                 /*
1044                  * Only consider slices where one, and only one, subslice has 7
1045                  * EUs
1046                  */
1047                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1048                         continue;
1049
1050                 /*
1051                  * subslice_7eu[i] != 0 (because of the check above) and
1052                  * ss_max == 4 (maximum number of subslices possible per slice)
1053                  *
1054                  * ->    0 <= ss <= 3;
1055                  */
1056                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1057                 vals[i] = 3 - ss;
1058         }
1059
1060         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1061                 return 0;
1062
1063         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1064         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1065                             GEN9_IZ_HASHING_MASK(2) |
1066                             GEN9_IZ_HASHING_MASK(1) |
1067                             GEN9_IZ_HASHING_MASK(0),
1068                             GEN9_IZ_HASHING(2, vals[2]) |
1069                             GEN9_IZ_HASHING(1, vals[1]) |
1070                             GEN9_IZ_HASHING(0, vals[0]));
1071
1072         return 0;
1073 }
1074
1075 static int skl_init_workarounds(struct intel_engine_cs *engine)
1076 {
1077         int ret;
1078         struct drm_device *dev = engine->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080
1081         ret = gen9_init_workarounds(engine);
1082         if (ret)
1083                 return ret;
1084
1085         /*
1086          * Actual WA is to disable percontext preemption granularity control
1087          * until D0 which is the default case so this is equivalent to
1088          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1089          */
1090         if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1091                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1092                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1093         }
1094
1095         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1096                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1097                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1098                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1099         }
1100
1101         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1102          * involving this register should also be added to WA batch as required.
1103          */
1104         if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1105                 /* WaDisableLSQCROPERFforOCL:skl */
1106                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1107                            GEN8_LQSC_RO_PERF_DIS);
1108
1109         /* WaEnableGapsTsvCreditFix:skl */
1110         if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1111                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1112                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1113         }
1114
1115         /* WaDisablePowerCompilerClockGating:skl */
1116         if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1117                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1118                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1119
1120         /* WaBarrierPerformanceFixDisable:skl */
1121         if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1122                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1123                                   HDC_FENCE_DEST_SLM_DISABLE |
1124                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1125
1126         /* WaDisableSbeCacheDispatchPortSharing:skl */
1127         if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1128                 WA_SET_BIT_MASKED(
1129                         GEN7_HALF_SLICE_CHICKEN1,
1130                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1131
1132         /* WaDisableGafsUnitClkGating:skl */
1133         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1134
1135         /* WaDisableLSQCROPERFforOCL:skl */
1136         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1137         if (ret)
1138                 return ret;
1139
1140         return skl_tune_iz_hashing(engine);
1141 }
1142
1143 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1144 {
1145         int ret;
1146         struct drm_device *dev = engine->dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149         ret = gen9_init_workarounds(engine);
1150         if (ret)
1151                 return ret;
1152
1153         /* WaStoreMultiplePTEenable:bxt */
1154         /* This is a requirement according to Hardware specification */
1155         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1156                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1157
1158         /* WaSetClckGatingDisableMedia:bxt */
1159         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1160                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1161                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1162         }
1163
1164         /* WaDisableThreadStallDopClockGating:bxt */
1165         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1166                           STALL_DOP_GATING_DISABLE);
1167
1168         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1169         if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1170                 WA_SET_BIT_MASKED(
1171                         GEN7_HALF_SLICE_CHICKEN1,
1172                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1173         }
1174
1175         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1176         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1177         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1178         /* WaDisableLSQCROPERFforOCL:bxt */
1179         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1180                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1181                 if (ret)
1182                         return ret;
1183
1184                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1185                 if (ret)
1186                         return ret;
1187         }
1188
1189         return 0;
1190 }
1191
1192 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1193 {
1194         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1195         int ret;
1196
1197         ret = gen9_init_workarounds(engine);
1198         if (ret)
1199                 return ret;
1200
1201         /* WaEnableGapsTsvCreditFix:kbl */
1202         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1203                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
1204
1205         return 0;
1206 }
1207
1208 int init_workarounds_ring(struct intel_engine_cs *engine)
1209 {
1210         struct drm_device *dev = engine->dev;
1211         struct drm_i915_private *dev_priv = dev->dev_private;
1212
1213         WARN_ON(engine->id != RCS);
1214
1215         dev_priv->workarounds.count = 0;
1216         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1217
1218         if (IS_BROADWELL(dev))
1219                 return bdw_init_workarounds(engine);
1220
1221         if (IS_CHERRYVIEW(dev))
1222                 return chv_init_workarounds(engine);
1223
1224         if (IS_SKYLAKE(dev))
1225                 return skl_init_workarounds(engine);
1226
1227         if (IS_BROXTON(dev))
1228                 return bxt_init_workarounds(engine);
1229
1230         if (IS_KABYLAKE(dev_priv))
1231                 return kbl_init_workarounds(engine);
1232
1233         return 0;
1234 }
1235
1236 static int init_render_ring(struct intel_engine_cs *engine)
1237 {
1238         struct drm_device *dev = engine->dev;
1239         struct drm_i915_private *dev_priv = dev->dev_private;
1240         int ret = init_ring_common(engine);
1241         if (ret)
1242                 return ret;
1243
1244         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1245         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1246                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1247
1248         /* We need to disable the AsyncFlip performance optimisations in order
1249          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1250          * programmed to '1' on all products.
1251          *
1252          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1253          */
1254         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1255                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1256
1257         /* Required for the hardware to program scanline values for waiting */
1258         /* WaEnableFlushTlbInvalidationMode:snb */
1259         if (INTEL_INFO(dev)->gen == 6)
1260                 I915_WRITE(GFX_MODE,
1261                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1262
1263         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1264         if (IS_GEN7(dev))
1265                 I915_WRITE(GFX_MODE_GEN7,
1266                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1267                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1268
1269         if (IS_GEN6(dev)) {
1270                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1271                  * "If this bit is set, STCunit will have LRA as replacement
1272                  *  policy. [...] This bit must be reset.  LRA replacement
1273                  *  policy is not supported."
1274                  */
1275                 I915_WRITE(CACHE_MODE_0,
1276                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1277         }
1278
1279         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1280                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1281
1282         if (HAS_L3_DPF(dev))
1283                 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1284
1285         return init_workarounds_ring(engine);
1286 }
1287
1288 static void render_ring_cleanup(struct intel_engine_cs *engine)
1289 {
1290         struct drm_device *dev = engine->dev;
1291         struct drm_i915_private *dev_priv = dev->dev_private;
1292
1293         if (dev_priv->semaphore_obj) {
1294                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1295                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1296                 dev_priv->semaphore_obj = NULL;
1297         }
1298
1299         intel_fini_pipe_control(engine);
1300 }
1301
1302 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1303                            unsigned int num_dwords)
1304 {
1305 #define MBOX_UPDATE_DWORDS 8
1306         struct intel_engine_cs *signaller = signaller_req->engine;
1307         struct drm_device *dev = signaller->dev;
1308         struct drm_i915_private *dev_priv = dev->dev_private;
1309         struct intel_engine_cs *waiter;
1310         enum intel_engine_id id;
1311         int ret, num_rings;
1312
1313         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1314         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1315 #undef MBOX_UPDATE_DWORDS
1316
1317         ret = intel_ring_begin(signaller_req, num_dwords);
1318         if (ret)
1319                 return ret;
1320
1321         for_each_engine_id(waiter, dev_priv, id) {
1322                 u32 seqno;
1323                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1324                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1325                         continue;
1326
1327                 seqno = i915_gem_request_get_seqno(signaller_req);
1328                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1329                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1330                                            PIPE_CONTROL_QW_WRITE |
1331                                            PIPE_CONTROL_FLUSH_ENABLE);
1332                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1333                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1334                 intel_ring_emit(signaller, seqno);
1335                 intel_ring_emit(signaller, 0);
1336                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1337                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1338                 intel_ring_emit(signaller, 0);
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1345                            unsigned int num_dwords)
1346 {
1347 #define MBOX_UPDATE_DWORDS 6
1348         struct intel_engine_cs *signaller = signaller_req->engine;
1349         struct drm_device *dev = signaller->dev;
1350         struct drm_i915_private *dev_priv = dev->dev_private;
1351         struct intel_engine_cs *waiter;
1352         enum intel_engine_id id;
1353         int ret, num_rings;
1354
1355         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1356         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1357 #undef MBOX_UPDATE_DWORDS
1358
1359         ret = intel_ring_begin(signaller_req, num_dwords);
1360         if (ret)
1361                 return ret;
1362
1363         for_each_engine_id(waiter, dev_priv, id) {
1364                 u32 seqno;
1365                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1366                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1367                         continue;
1368
1369                 seqno = i915_gem_request_get_seqno(signaller_req);
1370                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1371                                            MI_FLUSH_DW_OP_STOREDW);
1372                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1373                                            MI_FLUSH_DW_USE_GTT);
1374                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1375                 intel_ring_emit(signaller, seqno);
1376                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1377                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1378                 intel_ring_emit(signaller, 0);
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1385                        unsigned int num_dwords)
1386 {
1387         struct intel_engine_cs *signaller = signaller_req->engine;
1388         struct drm_device *dev = signaller->dev;
1389         struct drm_i915_private *dev_priv = dev->dev_private;
1390         struct intel_engine_cs *useless;
1391         enum intel_engine_id id;
1392         int ret, num_rings;
1393
1394 #define MBOX_UPDATE_DWORDS 3
1395         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1396         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1397 #undef MBOX_UPDATE_DWORDS
1398
1399         ret = intel_ring_begin(signaller_req, num_dwords);
1400         if (ret)
1401                 return ret;
1402
1403         for_each_engine_id(useless, dev_priv, id) {
1404                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1405
1406                 if (i915_mmio_reg_valid(mbox_reg)) {
1407                         u32 seqno = i915_gem_request_get_seqno(signaller_req);
1408
1409                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1410                         intel_ring_emit_reg(signaller, mbox_reg);
1411                         intel_ring_emit(signaller, seqno);
1412                 }
1413         }
1414
1415         /* If num_dwords was rounded, make sure the tail pointer is correct */
1416         if (num_rings % 2 == 0)
1417                 intel_ring_emit(signaller, MI_NOOP);
1418
1419         return 0;
1420 }
1421
1422 /**
1423  * gen6_add_request - Update the semaphore mailbox registers
1424  *
1425  * @request - request to write to the ring
1426  *
1427  * Update the mailbox registers in the *other* rings with the current seqno.
1428  * This acts like a signal in the canonical semaphore.
1429  */
1430 static int
1431 gen6_add_request(struct drm_i915_gem_request *req)
1432 {
1433         struct intel_engine_cs *engine = req->engine;
1434         int ret;
1435
1436         if (engine->semaphore.signal)
1437                 ret = engine->semaphore.signal(req, 4);
1438         else
1439                 ret = intel_ring_begin(req, 4);
1440
1441         if (ret)
1442                 return ret;
1443
1444         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1445         intel_ring_emit(engine,
1446                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1447         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1448         intel_ring_emit(engine, MI_USER_INTERRUPT);
1449         __intel_ring_advance(engine);
1450
1451         return 0;
1452 }
1453
1454 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1455                                               u32 seqno)
1456 {
1457         struct drm_i915_private *dev_priv = dev->dev_private;
1458         return dev_priv->last_seqno < seqno;
1459 }
1460
1461 /**
1462  * intel_ring_sync - sync the waiter to the signaller on seqno
1463  *
1464  * @waiter - ring that is waiting
1465  * @signaller - ring which has, or will signal
1466  * @seqno - seqno which the waiter will block on
1467  */
1468
1469 static int
1470 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1471                struct intel_engine_cs *signaller,
1472                u32 seqno)
1473 {
1474         struct intel_engine_cs *waiter = waiter_req->engine;
1475         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1476         int ret;
1477
1478         ret = intel_ring_begin(waiter_req, 4);
1479         if (ret)
1480                 return ret;
1481
1482         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1483                                 MI_SEMAPHORE_GLOBAL_GTT |
1484                                 MI_SEMAPHORE_POLL |
1485                                 MI_SEMAPHORE_SAD_GTE_SDD);
1486         intel_ring_emit(waiter, seqno);
1487         intel_ring_emit(waiter,
1488                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1489         intel_ring_emit(waiter,
1490                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1491         intel_ring_advance(waiter);
1492         return 0;
1493 }
1494
1495 static int
1496 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1497                struct intel_engine_cs *signaller,
1498                u32 seqno)
1499 {
1500         struct intel_engine_cs *waiter = waiter_req->engine;
1501         u32 dw1 = MI_SEMAPHORE_MBOX |
1502                   MI_SEMAPHORE_COMPARE |
1503                   MI_SEMAPHORE_REGISTER;
1504         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1505         int ret;
1506
1507         /* Throughout all of the GEM code, seqno passed implies our current
1508          * seqno is >= the last seqno executed. However for hardware the
1509          * comparison is strictly greater than.
1510          */
1511         seqno -= 1;
1512
1513         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1514
1515         ret = intel_ring_begin(waiter_req, 4);
1516         if (ret)
1517                 return ret;
1518
1519         /* If seqno wrap happened, omit the wait with no-ops */
1520         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1521                 intel_ring_emit(waiter, dw1 | wait_mbox);
1522                 intel_ring_emit(waiter, seqno);
1523                 intel_ring_emit(waiter, 0);
1524                 intel_ring_emit(waiter, MI_NOOP);
1525         } else {
1526                 intel_ring_emit(waiter, MI_NOOP);
1527                 intel_ring_emit(waiter, MI_NOOP);
1528                 intel_ring_emit(waiter, MI_NOOP);
1529                 intel_ring_emit(waiter, MI_NOOP);
1530         }
1531         intel_ring_advance(waiter);
1532
1533         return 0;
1534 }
1535
1536 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1537 do {                                                                    \
1538         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1539                  PIPE_CONTROL_DEPTH_STALL);                             \
1540         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1541         intel_ring_emit(ring__, 0);                                                     \
1542         intel_ring_emit(ring__, 0);                                                     \
1543 } while (0)
1544
1545 static int
1546 pc_render_add_request(struct drm_i915_gem_request *req)
1547 {
1548         struct intel_engine_cs *engine = req->engine;
1549         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1550         int ret;
1551
1552         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1553          * incoherent with writes to memory, i.e. completely fubar,
1554          * so we need to use PIPE_NOTIFY instead.
1555          *
1556          * However, we also need to workaround the qword write
1557          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1558          * memory before requesting an interrupt.
1559          */
1560         ret = intel_ring_begin(req, 32);
1561         if (ret)
1562                 return ret;
1563
1564         intel_ring_emit(engine,
1565                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1566                         PIPE_CONTROL_WRITE_FLUSH |
1567                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1568         intel_ring_emit(engine,
1569                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1570         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1571         intel_ring_emit(engine, 0);
1572         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1573         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1574         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1575         scratch_addr += 2 * CACHELINE_BYTES;
1576         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1577         scratch_addr += 2 * CACHELINE_BYTES;
1578         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1579         scratch_addr += 2 * CACHELINE_BYTES;
1580         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1581         scratch_addr += 2 * CACHELINE_BYTES;
1582         PIPE_CONTROL_FLUSH(engine, scratch_addr);
1583
1584         intel_ring_emit(engine,
1585                         GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1586                         PIPE_CONTROL_WRITE_FLUSH |
1587                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1588                         PIPE_CONTROL_NOTIFY);
1589         intel_ring_emit(engine,
1590                         engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1591         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1592         intel_ring_emit(engine, 0);
1593         __intel_ring_advance(engine);
1594
1595         return 0;
1596 }
1597
1598 static void
1599 gen6_seqno_barrier(struct intel_engine_cs *engine)
1600 {
1601         struct drm_i915_private *dev_priv = engine->dev->dev_private;
1602
1603         /* Workaround to force correct ordering between irq and seqno writes on
1604          * ivb (and maybe also on snb) by reading from a CS register (like
1605          * ACTHD) before reading the status page.
1606          *
1607          * Note that this effectively stalls the read by the time it takes to
1608          * do a memory transaction, which more or less ensures that the write
1609          * from the GPU has sufficient time to invalidate the CPU cacheline.
1610          * Alternatively we could delay the interrupt from the CS ring to give
1611          * the write time to land, but that would incur a delay after every
1612          * batch i.e. much more frequent than a delay when waiting for the
1613          * interrupt (with the same net latency).
1614          *
1615          * Also note that to prevent whole machine hangs on gen7, we have to
1616          * take the spinlock to guard against concurrent cacheline access.
1617          */
1618         spin_lock_irq(&dev_priv->uncore.lock);
1619         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1620         spin_unlock_irq(&dev_priv->uncore.lock);
1621 }
1622
1623 static u32
1624 ring_get_seqno(struct intel_engine_cs *engine)
1625 {
1626         return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1627 }
1628
1629 static void
1630 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1631 {
1632         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1633 }
1634
1635 static u32
1636 pc_render_get_seqno(struct intel_engine_cs *engine)
1637 {
1638         return engine->scratch.cpu_page[0];
1639 }
1640
1641 static void
1642 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1643 {
1644         engine->scratch.cpu_page[0] = seqno;
1645 }
1646
1647 static bool
1648 gen5_ring_get_irq(struct intel_engine_cs *engine)
1649 {
1650         struct drm_device *dev = engine->dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652         unsigned long flags;
1653
1654         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1655                 return false;
1656
1657         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1658         if (engine->irq_refcount++ == 0)
1659                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1660         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1661
1662         return true;
1663 }
1664
1665 static void
1666 gen5_ring_put_irq(struct intel_engine_cs *engine)
1667 {
1668         struct drm_device *dev = engine->dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         unsigned long flags;
1671
1672         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1673         if (--engine->irq_refcount == 0)
1674                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1675         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1676 }
1677
1678 static bool
1679 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1680 {
1681         struct drm_device *dev = engine->dev;
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683         unsigned long flags;
1684
1685         if (!intel_irqs_enabled(dev_priv))
1686                 return false;
1687
1688         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1689         if (engine->irq_refcount++ == 0) {
1690                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1691                 I915_WRITE(IMR, dev_priv->irq_mask);
1692                 POSTING_READ(IMR);
1693         }
1694         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1695
1696         return true;
1697 }
1698
1699 static void
1700 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1701 {
1702         struct drm_device *dev = engine->dev;
1703         struct drm_i915_private *dev_priv = dev->dev_private;
1704         unsigned long flags;
1705
1706         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1707         if (--engine->irq_refcount == 0) {
1708                 dev_priv->irq_mask |= engine->irq_enable_mask;
1709                 I915_WRITE(IMR, dev_priv->irq_mask);
1710                 POSTING_READ(IMR);
1711         }
1712         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1713 }
1714
1715 static bool
1716 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1717 {
1718         struct drm_device *dev = engine->dev;
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720         unsigned long flags;
1721
1722         if (!intel_irqs_enabled(dev_priv))
1723                 return false;
1724
1725         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1726         if (engine->irq_refcount++ == 0) {
1727                 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1728                 I915_WRITE16(IMR, dev_priv->irq_mask);
1729                 POSTING_READ16(IMR);
1730         }
1731         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1732
1733         return true;
1734 }
1735
1736 static void
1737 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1738 {
1739         struct drm_device *dev = engine->dev;
1740         struct drm_i915_private *dev_priv = dev->dev_private;
1741         unsigned long flags;
1742
1743         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1744         if (--engine->irq_refcount == 0) {
1745                 dev_priv->irq_mask |= engine->irq_enable_mask;
1746                 I915_WRITE16(IMR, dev_priv->irq_mask);
1747                 POSTING_READ16(IMR);
1748         }
1749         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1750 }
1751
1752 static int
1753 bsd_ring_flush(struct drm_i915_gem_request *req,
1754                u32     invalidate_domains,
1755                u32     flush_domains)
1756 {
1757         struct intel_engine_cs *engine = req->engine;
1758         int ret;
1759
1760         ret = intel_ring_begin(req, 2);
1761         if (ret)
1762                 return ret;
1763
1764         intel_ring_emit(engine, MI_FLUSH);
1765         intel_ring_emit(engine, MI_NOOP);
1766         intel_ring_advance(engine);
1767         return 0;
1768 }
1769
1770 static int
1771 i9xx_add_request(struct drm_i915_gem_request *req)
1772 {
1773         struct intel_engine_cs *engine = req->engine;
1774         int ret;
1775
1776         ret = intel_ring_begin(req, 4);
1777         if (ret)
1778                 return ret;
1779
1780         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1781         intel_ring_emit(engine,
1782                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1783         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1784         intel_ring_emit(engine, MI_USER_INTERRUPT);
1785         __intel_ring_advance(engine);
1786
1787         return 0;
1788 }
1789
1790 static bool
1791 gen6_ring_get_irq(struct intel_engine_cs *engine)
1792 {
1793         struct drm_device *dev = engine->dev;
1794         struct drm_i915_private *dev_priv = dev->dev_private;
1795         unsigned long flags;
1796
1797         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1798                 return false;
1799
1800         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1801         if (engine->irq_refcount++ == 0) {
1802                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1803                         I915_WRITE_IMR(engine,
1804                                        ~(engine->irq_enable_mask |
1805                                          GT_PARITY_ERROR(dev)));
1806                 else
1807                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1808                 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1809         }
1810         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1811
1812         return true;
1813 }
1814
1815 static void
1816 gen6_ring_put_irq(struct intel_engine_cs *engine)
1817 {
1818         struct drm_device *dev = engine->dev;
1819         struct drm_i915_private *dev_priv = dev->dev_private;
1820         unsigned long flags;
1821
1822         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1823         if (--engine->irq_refcount == 0) {
1824                 if (HAS_L3_DPF(dev) && engine->id == RCS)
1825                         I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1826                 else
1827                         I915_WRITE_IMR(engine, ~0);
1828                 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1829         }
1830         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1831 }
1832
1833 static bool
1834 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1835 {
1836         struct drm_device *dev = engine->dev;
1837         struct drm_i915_private *dev_priv = dev->dev_private;
1838         unsigned long flags;
1839
1840         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1841                 return false;
1842
1843         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1844         if (engine->irq_refcount++ == 0) {
1845                 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1846                 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1847         }
1848         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1849
1850         return true;
1851 }
1852
1853 static void
1854 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1855 {
1856         struct drm_device *dev = engine->dev;
1857         struct drm_i915_private *dev_priv = dev->dev_private;
1858         unsigned long flags;
1859
1860         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1861         if (--engine->irq_refcount == 0) {
1862                 I915_WRITE_IMR(engine, ~0);
1863                 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1864         }
1865         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1866 }
1867
1868 static bool
1869 gen8_ring_get_irq(struct intel_engine_cs *engine)
1870 {
1871         struct drm_device *dev = engine->dev;
1872         struct drm_i915_private *dev_priv = dev->dev_private;
1873         unsigned long flags;
1874
1875         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1876                 return false;
1877
1878         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1879         if (engine->irq_refcount++ == 0) {
1880                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1881                         I915_WRITE_IMR(engine,
1882                                        ~(engine->irq_enable_mask |
1883                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1884                 } else {
1885                         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1886                 }
1887                 POSTING_READ(RING_IMR(engine->mmio_base));
1888         }
1889         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1890
1891         return true;
1892 }
1893
1894 static void
1895 gen8_ring_put_irq(struct intel_engine_cs *engine)
1896 {
1897         struct drm_device *dev = engine->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         unsigned long flags;
1900
1901         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1902         if (--engine->irq_refcount == 0) {
1903                 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1904                         I915_WRITE_IMR(engine,
1905                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1906                 } else {
1907                         I915_WRITE_IMR(engine, ~0);
1908                 }
1909                 POSTING_READ(RING_IMR(engine->mmio_base));
1910         }
1911         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1912 }
1913
1914 static int
1915 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1916                          u64 offset, u32 length,
1917                          unsigned dispatch_flags)
1918 {
1919         struct intel_engine_cs *engine = req->engine;
1920         int ret;
1921
1922         ret = intel_ring_begin(req, 2);
1923         if (ret)
1924                 return ret;
1925
1926         intel_ring_emit(engine,
1927                         MI_BATCH_BUFFER_START |
1928                         MI_BATCH_GTT |
1929                         (dispatch_flags & I915_DISPATCH_SECURE ?
1930                          0 : MI_BATCH_NON_SECURE_I965));
1931         intel_ring_emit(engine, offset);
1932         intel_ring_advance(engine);
1933
1934         return 0;
1935 }
1936
1937 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1938 #define I830_BATCH_LIMIT (256*1024)
1939 #define I830_TLB_ENTRIES (2)
1940 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1941 static int
1942 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1943                          u64 offset, u32 len,
1944                          unsigned dispatch_flags)
1945 {
1946         struct intel_engine_cs *engine = req->engine;
1947         u32 cs_offset = engine->scratch.gtt_offset;
1948         int ret;
1949
1950         ret = intel_ring_begin(req, 6);
1951         if (ret)
1952                 return ret;
1953
1954         /* Evict the invalid PTE TLBs */
1955         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1956         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1957         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1958         intel_ring_emit(engine, cs_offset);
1959         intel_ring_emit(engine, 0xdeadbeef);
1960         intel_ring_emit(engine, MI_NOOP);
1961         intel_ring_advance(engine);
1962
1963         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1964                 if (len > I830_BATCH_LIMIT)
1965                         return -ENOSPC;
1966
1967                 ret = intel_ring_begin(req, 6 + 2);
1968                 if (ret)
1969                         return ret;
1970
1971                 /* Blit the batch (which has now all relocs applied) to the
1972                  * stable batch scratch bo area (so that the CS never
1973                  * stumbles over its tlb invalidation bug) ...
1974                  */
1975                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1976                 intel_ring_emit(engine,
1977                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1978                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1979                 intel_ring_emit(engine, cs_offset);
1980                 intel_ring_emit(engine, 4096);
1981                 intel_ring_emit(engine, offset);
1982
1983                 intel_ring_emit(engine, MI_FLUSH);
1984                 intel_ring_emit(engine, MI_NOOP);
1985                 intel_ring_advance(engine);
1986
1987                 /* ... and execute it. */
1988                 offset = cs_offset;
1989         }
1990
1991         ret = intel_ring_begin(req, 2);
1992         if (ret)
1993                 return ret;
1994
1995         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1996         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1997                                           0 : MI_BATCH_NON_SECURE));
1998         intel_ring_advance(engine);
1999
2000         return 0;
2001 }
2002
2003 static int
2004 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
2005                          u64 offset, u32 len,
2006                          unsigned dispatch_flags)
2007 {
2008         struct intel_engine_cs *engine = req->engine;
2009         int ret;
2010
2011         ret = intel_ring_begin(req, 2);
2012         if (ret)
2013                 return ret;
2014
2015         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2016         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2017                                           0 : MI_BATCH_NON_SECURE));
2018         intel_ring_advance(engine);
2019
2020         return 0;
2021 }
2022
2023 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
2024 {
2025         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2026
2027         if (!dev_priv->status_page_dmah)
2028                 return;
2029
2030         drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2031         engine->status_page.page_addr = NULL;
2032 }
2033
2034 static void cleanup_status_page(struct intel_engine_cs *engine)
2035 {
2036         struct drm_i915_gem_object *obj;
2037
2038         obj = engine->status_page.obj;
2039         if (obj == NULL)
2040                 return;
2041
2042         kunmap(sg_page(obj->pages->sgl));
2043         i915_gem_object_ggtt_unpin(obj);
2044         drm_gem_object_unreference(&obj->base);
2045         engine->status_page.obj = NULL;
2046 }
2047
2048 static int init_status_page(struct intel_engine_cs *engine)
2049 {
2050         struct drm_i915_gem_object *obj = engine->status_page.obj;
2051
2052         if (obj == NULL) {
2053                 unsigned flags;
2054                 int ret;
2055
2056                 obj = i915_gem_alloc_object(engine->dev, 4096);
2057                 if (obj == NULL) {
2058                         DRM_ERROR("Failed to allocate status page\n");
2059                         return -ENOMEM;
2060                 }
2061
2062                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2063                 if (ret)
2064                         goto err_unref;
2065
2066                 flags = 0;
2067                 if (!HAS_LLC(engine->dev))
2068                         /* On g33, we cannot place HWS above 256MiB, so
2069                          * restrict its pinning to the low mappable arena.
2070                          * Though this restriction is not documented for
2071                          * gen4, gen5, or byt, they also behave similarly
2072                          * and hang if the HWS is placed at the top of the
2073                          * GTT. To generalise, it appears that all !llc
2074                          * platforms have issues with us placing the HWS
2075                          * above the mappable region (even though we never
2076                          * actualy map it).
2077                          */
2078                         flags |= PIN_MAPPABLE;
2079                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2080                 if (ret) {
2081 err_unref:
2082                         drm_gem_object_unreference(&obj->base);
2083                         return ret;
2084                 }
2085
2086                 engine->status_page.obj = obj;
2087         }
2088
2089         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2090         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2091         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2092
2093         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2094                         engine->name, engine->status_page.gfx_addr);
2095
2096         return 0;
2097 }
2098
2099 static int init_phys_status_page(struct intel_engine_cs *engine)
2100 {
2101         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2102
2103         if (!dev_priv->status_page_dmah) {
2104                 dev_priv->status_page_dmah =
2105                         drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2106                 if (!dev_priv->status_page_dmah)
2107                         return -ENOMEM;
2108         }
2109
2110         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2111         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2112
2113         return 0;
2114 }
2115
2116 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2117 {
2118         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2119                 i915_gem_object_unpin_map(ringbuf->obj);
2120         else
2121                 iounmap(ringbuf->virtual_start);
2122         ringbuf->virtual_start = NULL;
2123         ringbuf->vma = NULL;
2124         i915_gem_object_ggtt_unpin(ringbuf->obj);
2125 }
2126
2127 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2128                                      struct intel_ringbuffer *ringbuf)
2129 {
2130         struct drm_i915_private *dev_priv = to_i915(dev);
2131         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2132         struct drm_i915_gem_object *obj = ringbuf->obj;
2133         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2134         unsigned flags = PIN_OFFSET_BIAS | 4096;
2135         void *addr;
2136         int ret;
2137
2138         if (HAS_LLC(dev_priv) && !obj->stolen) {
2139                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2140                 if (ret)
2141                         return ret;
2142
2143                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2144                 if (ret)
2145                         goto err_unpin;
2146
2147                 addr = i915_gem_object_pin_map(obj);
2148                 if (IS_ERR(addr)) {
2149                         ret = PTR_ERR(addr);
2150                         goto err_unpin;
2151                 }
2152         } else {
2153                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2154                                             flags | PIN_MAPPABLE);
2155                 if (ret)
2156                         return ret;
2157
2158                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2159                 if (ret)
2160                         goto err_unpin;
2161
2162                 /* Access through the GTT requires the device to be awake. */
2163                 assert_rpm_wakelock_held(dev_priv);
2164
2165                 addr = ioremap_wc(ggtt->mappable_base +
2166                                   i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2167                 if (addr == NULL) {
2168                         ret = -ENOMEM;
2169                         goto err_unpin;
2170                 }
2171         }
2172
2173         ringbuf->virtual_start = addr;
2174         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2175         return 0;
2176
2177 err_unpin:
2178         i915_gem_object_ggtt_unpin(obj);
2179         return ret;
2180 }
2181
2182 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2183 {
2184         drm_gem_object_unreference(&ringbuf->obj->base);
2185         ringbuf->obj = NULL;
2186 }
2187
2188 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2189                                       struct intel_ringbuffer *ringbuf)
2190 {
2191         struct drm_i915_gem_object *obj;
2192
2193         obj = NULL;
2194         if (!HAS_LLC(dev))
2195                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2196         if (obj == NULL)
2197                 obj = i915_gem_alloc_object(dev, ringbuf->size);
2198         if (obj == NULL)
2199                 return -ENOMEM;
2200
2201         /* mark ring buffers as read-only from GPU side by default */
2202         obj->gt_ro = 1;
2203
2204         ringbuf->obj = obj;
2205
2206         return 0;
2207 }
2208
2209 struct intel_ringbuffer *
2210 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2211 {
2212         struct intel_ringbuffer *ring;
2213         int ret;
2214
2215         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2216         if (ring == NULL) {
2217                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2218                                  engine->name);
2219                 return ERR_PTR(-ENOMEM);
2220         }
2221
2222         ring->engine = engine;
2223         list_add(&ring->link, &engine->buffers);
2224
2225         ring->size = size;
2226         /* Workaround an erratum on the i830 which causes a hang if
2227          * the TAIL pointer points to within the last 2 cachelines
2228          * of the buffer.
2229          */
2230         ring->effective_size = size;
2231         if (IS_I830(engine->dev) || IS_845G(engine->dev))
2232                 ring->effective_size -= 2 * CACHELINE_BYTES;
2233
2234         ring->last_retired_head = -1;
2235         intel_ring_update_space(ring);
2236
2237         ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2238         if (ret) {
2239                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2240                                  engine->name, ret);
2241                 list_del(&ring->link);
2242                 kfree(ring);
2243                 return ERR_PTR(ret);
2244         }
2245
2246         return ring;
2247 }
2248
2249 void
2250 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2251 {
2252         intel_destroy_ringbuffer_obj(ring);
2253         list_del(&ring->link);
2254         kfree(ring);
2255 }
2256
2257 static int intel_init_ring_buffer(struct drm_device *dev,
2258                                   struct intel_engine_cs *engine)
2259 {
2260         struct intel_ringbuffer *ringbuf;
2261         int ret;
2262
2263         WARN_ON(engine->buffer);
2264
2265         engine->dev = dev;
2266         INIT_LIST_HEAD(&engine->active_list);
2267         INIT_LIST_HEAD(&engine->request_list);
2268         INIT_LIST_HEAD(&engine->execlist_queue);
2269         INIT_LIST_HEAD(&engine->buffers);
2270         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2271         memset(engine->semaphore.sync_seqno, 0,
2272                sizeof(engine->semaphore.sync_seqno));
2273
2274         init_waitqueue_head(&engine->irq_queue);
2275
2276         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2277         if (IS_ERR(ringbuf)) {
2278                 ret = PTR_ERR(ringbuf);
2279                 goto error;
2280         }
2281         engine->buffer = ringbuf;
2282
2283         if (I915_NEED_GFX_HWS(dev)) {
2284                 ret = init_status_page(engine);
2285                 if (ret)
2286                         goto error;
2287         } else {
2288                 WARN_ON(engine->id != RCS);
2289                 ret = init_phys_status_page(engine);
2290                 if (ret)
2291                         goto error;
2292         }
2293
2294         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2295         if (ret) {
2296                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2297                                 engine->name, ret);
2298                 intel_destroy_ringbuffer_obj(ringbuf);
2299                 goto error;
2300         }
2301
2302         ret = i915_cmd_parser_init_ring(engine);
2303         if (ret)
2304                 goto error;
2305
2306         return 0;
2307
2308 error:
2309         intel_cleanup_engine(engine);
2310         return ret;
2311 }
2312
2313 void intel_cleanup_engine(struct intel_engine_cs *engine)
2314 {
2315         struct drm_i915_private *dev_priv;
2316
2317         if (!intel_engine_initialized(engine))
2318                 return;
2319
2320         dev_priv = to_i915(engine->dev);
2321
2322         if (engine->buffer) {
2323                 intel_stop_engine(engine);
2324                 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2325
2326                 intel_unpin_ringbuffer_obj(engine->buffer);
2327                 intel_ringbuffer_free(engine->buffer);
2328                 engine->buffer = NULL;
2329         }
2330
2331         if (engine->cleanup)
2332                 engine->cleanup(engine);
2333
2334         if (I915_NEED_GFX_HWS(engine->dev)) {
2335                 cleanup_status_page(engine);
2336         } else {
2337                 WARN_ON(engine->id != RCS);
2338                 cleanup_phys_status_page(engine);
2339         }
2340
2341         i915_cmd_parser_fini_ring(engine);
2342         i915_gem_batch_pool_fini(&engine->batch_pool);
2343         engine->dev = NULL;
2344 }
2345
2346 int intel_engine_idle(struct intel_engine_cs *engine)
2347 {
2348         struct drm_i915_gem_request *req;
2349
2350         /* Wait upon the last request to be completed */
2351         if (list_empty(&engine->request_list))
2352                 return 0;
2353
2354         req = list_entry(engine->request_list.prev,
2355                          struct drm_i915_gem_request,
2356                          list);
2357
2358         /* Make sure we do not trigger any retires */
2359         return __i915_wait_request(req,
2360                                    req->i915->mm.interruptible,
2361                                    NULL, NULL);
2362 }
2363
2364 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2365 {
2366         request->ringbuf = request->engine->buffer;
2367         return 0;
2368 }
2369
2370 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2371 {
2372         /*
2373          * The first call merely notes the reserve request and is common for
2374          * all back ends. The subsequent localised _begin() call actually
2375          * ensures that the reservation is available. Without the begin, if
2376          * the request creator immediately submitted the request without
2377          * adding any commands to it then there might not actually be
2378          * sufficient room for the submission commands.
2379          */
2380         intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2381
2382         return intel_ring_begin(request, 0);
2383 }
2384
2385 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2386 {
2387         GEM_BUG_ON(ringbuf->reserved_size);
2388         ringbuf->reserved_size = size;
2389 }
2390
2391 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2392 {
2393         GEM_BUG_ON(!ringbuf->reserved_size);
2394         ringbuf->reserved_size   = 0;
2395 }
2396
2397 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2398 {
2399         GEM_BUG_ON(!ringbuf->reserved_size);
2400         ringbuf->reserved_size   = 0;
2401 }
2402
2403 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2404 {
2405         GEM_BUG_ON(ringbuf->reserved_size);
2406 }
2407
2408 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2409 {
2410         struct intel_ringbuffer *ringbuf = req->ringbuf;
2411         struct intel_engine_cs *engine = req->engine;
2412         struct drm_i915_gem_request *target;
2413
2414         intel_ring_update_space(ringbuf);
2415         if (ringbuf->space >= bytes)
2416                 return 0;
2417
2418         /*
2419          * Space is reserved in the ringbuffer for finalising the request,
2420          * as that cannot be allowed to fail. During request finalisation,
2421          * reserved_space is set to 0 to stop the overallocation and the
2422          * assumption is that then we never need to wait (which has the
2423          * risk of failing with EINTR).
2424          *
2425          * See also i915_gem_request_alloc() and i915_add_request().
2426          */
2427         GEM_BUG_ON(!ringbuf->reserved_size);
2428
2429         list_for_each_entry(target, &engine->request_list, list) {
2430                 unsigned space;
2431
2432                 /*
2433                  * The request queue is per-engine, so can contain requests
2434                  * from multiple ringbuffers. Here, we must ignore any that
2435                  * aren't from the ringbuffer we're considering.
2436                  */
2437                 if (target->ringbuf != ringbuf)
2438                         continue;
2439
2440                 /* Would completion of this request free enough space? */
2441                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2442                                            ringbuf->size);
2443                 if (space >= bytes)
2444                         break;
2445         }
2446
2447         if (WARN_ON(&target->list == &engine->request_list))
2448                 return -ENOSPC;
2449
2450         return i915_wait_request(target);
2451 }
2452
2453 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2454 {
2455         struct intel_ringbuffer *ringbuf = req->ringbuf;
2456         int remain_actual = ringbuf->size - ringbuf->tail;
2457         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2458         int bytes = num_dwords * sizeof(u32);
2459         int total_bytes, wait_bytes;
2460         bool need_wrap = false;
2461
2462         total_bytes = bytes + ringbuf->reserved_size;
2463
2464         if (unlikely(bytes > remain_usable)) {
2465                 /*
2466                  * Not enough space for the basic request. So need to flush
2467                  * out the remainder and then wait for base + reserved.
2468                  */
2469                 wait_bytes = remain_actual + total_bytes;
2470                 need_wrap = true;
2471         } else if (unlikely(total_bytes > remain_usable)) {
2472                 /*
2473                  * The base request will fit but the reserved space
2474                  * falls off the end. So we don't need an immediate wrap
2475                  * and only need to effectively wait for the reserved
2476                  * size space from the start of ringbuffer.
2477                  */
2478                 wait_bytes = remain_actual + ringbuf->reserved_size;
2479         } else {
2480                 /* No wrapping required, just waiting. */
2481                 wait_bytes = total_bytes;
2482         }
2483
2484         if (wait_bytes > ringbuf->space) {
2485                 int ret = wait_for_space(req, wait_bytes);
2486                 if (unlikely(ret))
2487                         return ret;
2488
2489                 intel_ring_update_space(ringbuf);
2490                 if (unlikely(ringbuf->space < wait_bytes))
2491                         return -EAGAIN;
2492         }
2493
2494         if (unlikely(need_wrap)) {
2495                 GEM_BUG_ON(remain_actual > ringbuf->space);
2496                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2497
2498                 /* Fill the tail with MI_NOOP */
2499                 memset(ringbuf->virtual_start + ringbuf->tail,
2500                        0, remain_actual);
2501                 ringbuf->tail = 0;
2502                 ringbuf->space -= remain_actual;
2503         }
2504
2505         ringbuf->space -= bytes;
2506         GEM_BUG_ON(ringbuf->space < 0);
2507         return 0;
2508 }
2509
2510 /* Align the ring tail to a cacheline boundary */
2511 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2512 {
2513         struct intel_engine_cs *engine = req->engine;
2514         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2515         int ret;
2516
2517         if (num_dwords == 0)
2518                 return 0;
2519
2520         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2521         ret = intel_ring_begin(req, num_dwords);
2522         if (ret)
2523                 return ret;
2524
2525         while (num_dwords--)
2526                 intel_ring_emit(engine, MI_NOOP);
2527
2528         intel_ring_advance(engine);
2529
2530         return 0;
2531 }
2532
2533 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2534 {
2535         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2536
2537         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2538          * so long as the semaphore value in the register/page is greater
2539          * than the sync value), so whenever we reset the seqno,
2540          * so long as we reset the tracking semaphore value to 0, it will
2541          * always be before the next request's seqno. If we don't reset
2542          * the semaphore value, then when the seqno moves backwards all
2543          * future waits will complete instantly (causing rendering corruption).
2544          */
2545         if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
2546                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2547                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2548                 if (HAS_VEBOX(dev_priv))
2549                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2550         }
2551         if (dev_priv->semaphore_obj) {
2552                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2553                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2554                 void *semaphores = kmap(page);
2555                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2556                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2557                 kunmap(page);
2558         }
2559         memset(engine->semaphore.sync_seqno, 0,
2560                sizeof(engine->semaphore.sync_seqno));
2561
2562         engine->set_seqno(engine, seqno);
2563         engine->last_submitted_seqno = seqno;
2564
2565         engine->hangcheck.seqno = seqno;
2566 }
2567
2568 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2569                                      u32 value)
2570 {
2571         struct drm_i915_private *dev_priv = engine->dev->dev_private;
2572
2573        /* Every tail move must follow the sequence below */
2574
2575         /* Disable notification that the ring is IDLE. The GT
2576          * will then assume that it is busy and bring it out of rc6.
2577          */
2578         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2579                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2580
2581         /* Clear the context id. Here be magic! */
2582         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2583
2584         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2585         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2586                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2587                      50))
2588                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2589
2590         /* Now that the ring is fully powered up, update the tail */
2591         I915_WRITE_TAIL(engine, value);
2592         POSTING_READ(RING_TAIL(engine->mmio_base));
2593
2594         /* Let the ring send IDLE messages to the GT again,
2595          * and so let it sleep to conserve power when idle.
2596          */
2597         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2598                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2599 }
2600
2601 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2602                                u32 invalidate, u32 flush)
2603 {
2604         struct intel_engine_cs *engine = req->engine;
2605         uint32_t cmd;
2606         int ret;
2607
2608         ret = intel_ring_begin(req, 4);
2609         if (ret)
2610                 return ret;
2611
2612         cmd = MI_FLUSH_DW;
2613         if (INTEL_INFO(engine->dev)->gen >= 8)
2614                 cmd += 1;
2615
2616         /* We always require a command barrier so that subsequent
2617          * commands, such as breadcrumb interrupts, are strictly ordered
2618          * wrt the contents of the write cache being flushed to memory
2619          * (and thus being coherent from the CPU).
2620          */
2621         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2622
2623         /*
2624          * Bspec vol 1c.5 - video engine command streamer:
2625          * "If ENABLED, all TLBs will be invalidated once the flush
2626          * operation is complete. This bit is only valid when the
2627          * Post-Sync Operation field is a value of 1h or 3h."
2628          */
2629         if (invalidate & I915_GEM_GPU_DOMAINS)
2630                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2631
2632         intel_ring_emit(engine, cmd);
2633         intel_ring_emit(engine,
2634                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2635         if (INTEL_INFO(engine->dev)->gen >= 8) {
2636                 intel_ring_emit(engine, 0); /* upper addr */
2637                 intel_ring_emit(engine, 0); /* value */
2638         } else  {
2639                 intel_ring_emit(engine, 0);
2640                 intel_ring_emit(engine, MI_NOOP);
2641         }
2642         intel_ring_advance(engine);
2643         return 0;
2644 }
2645
2646 static int
2647 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2648                               u64 offset, u32 len,
2649                               unsigned dispatch_flags)
2650 {
2651         struct intel_engine_cs *engine = req->engine;
2652         bool ppgtt = USES_PPGTT(engine->dev) &&
2653                         !(dispatch_flags & I915_DISPATCH_SECURE);
2654         int ret;
2655
2656         ret = intel_ring_begin(req, 4);
2657         if (ret)
2658                 return ret;
2659
2660         /* FIXME(BDW): Address space and security selectors. */
2661         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2662                         (dispatch_flags & I915_DISPATCH_RS ?
2663                          MI_BATCH_RESOURCE_STREAMER : 0));
2664         intel_ring_emit(engine, lower_32_bits(offset));
2665         intel_ring_emit(engine, upper_32_bits(offset));
2666         intel_ring_emit(engine, MI_NOOP);
2667         intel_ring_advance(engine);
2668
2669         return 0;
2670 }
2671
2672 static int
2673 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2674                              u64 offset, u32 len,
2675                              unsigned dispatch_flags)
2676 {
2677         struct intel_engine_cs *engine = req->engine;
2678         int ret;
2679
2680         ret = intel_ring_begin(req, 2);
2681         if (ret)
2682                 return ret;
2683
2684         intel_ring_emit(engine,
2685                         MI_BATCH_BUFFER_START |
2686                         (dispatch_flags & I915_DISPATCH_SECURE ?
2687                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2688                         (dispatch_flags & I915_DISPATCH_RS ?
2689                          MI_BATCH_RESOURCE_STREAMER : 0));
2690         /* bit0-7 is the length on GEN6+ */
2691         intel_ring_emit(engine, offset);
2692         intel_ring_advance(engine);
2693
2694         return 0;
2695 }
2696
2697 static int
2698 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2699                               u64 offset, u32 len,
2700                               unsigned dispatch_flags)
2701 {
2702         struct intel_engine_cs *engine = req->engine;
2703         int ret;
2704
2705         ret = intel_ring_begin(req, 2);
2706         if (ret)
2707                 return ret;
2708
2709         intel_ring_emit(engine,
2710                         MI_BATCH_BUFFER_START |
2711                         (dispatch_flags & I915_DISPATCH_SECURE ?
2712                          0 : MI_BATCH_NON_SECURE_I965));
2713         /* bit0-7 is the length on GEN6+ */
2714         intel_ring_emit(engine, offset);
2715         intel_ring_advance(engine);
2716
2717         return 0;
2718 }
2719
2720 /* Blitter support (SandyBridge+) */
2721
2722 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2723                            u32 invalidate, u32 flush)
2724 {
2725         struct intel_engine_cs *engine = req->engine;
2726         struct drm_device *dev = engine->dev;
2727         uint32_t cmd;
2728         int ret;
2729
2730         ret = intel_ring_begin(req, 4);
2731         if (ret)
2732                 return ret;
2733
2734         cmd = MI_FLUSH_DW;
2735         if (INTEL_INFO(dev)->gen >= 8)
2736                 cmd += 1;
2737
2738         /* We always require a command barrier so that subsequent
2739          * commands, such as breadcrumb interrupts, are strictly ordered
2740          * wrt the contents of the write cache being flushed to memory
2741          * (and thus being coherent from the CPU).
2742          */
2743         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2744
2745         /*
2746          * Bspec vol 1c.3 - blitter engine command streamer:
2747          * "If ENABLED, all TLBs will be invalidated once the flush
2748          * operation is complete. This bit is only valid when the
2749          * Post-Sync Operation field is a value of 1h or 3h."
2750          */
2751         if (invalidate & I915_GEM_DOMAIN_RENDER)
2752                 cmd |= MI_INVALIDATE_TLB;
2753         intel_ring_emit(engine, cmd);
2754         intel_ring_emit(engine,
2755                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2756         if (INTEL_INFO(dev)->gen >= 8) {
2757                 intel_ring_emit(engine, 0); /* upper addr */
2758                 intel_ring_emit(engine, 0); /* value */
2759         } else  {
2760                 intel_ring_emit(engine, 0);
2761                 intel_ring_emit(engine, MI_NOOP);
2762         }
2763         intel_ring_advance(engine);
2764
2765         return 0;
2766 }
2767
2768 int intel_init_render_ring_buffer(struct drm_device *dev)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2772         struct drm_i915_gem_object *obj;
2773         int ret;
2774
2775         engine->name = "render ring";
2776         engine->id = RCS;
2777         engine->exec_id = I915_EXEC_RENDER;
2778         engine->hw_id = 0;
2779         engine->mmio_base = RENDER_RING_BASE;
2780
2781         if (INTEL_INFO(dev)->gen >= 8) {
2782                 if (i915_semaphore_is_enabled(dev)) {
2783                         obj = i915_gem_alloc_object(dev, 4096);
2784                         if (obj == NULL) {
2785                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2786                                 i915.semaphores = 0;
2787                         } else {
2788                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2789                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2790                                 if (ret != 0) {
2791                                         drm_gem_object_unreference(&obj->base);
2792                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2793                                         i915.semaphores = 0;
2794                                 } else
2795                                         dev_priv->semaphore_obj = obj;
2796                         }
2797                 }
2798
2799                 engine->init_context = intel_rcs_ctx_init;
2800                 engine->add_request = gen6_add_request;
2801                 engine->flush = gen8_render_ring_flush;
2802                 engine->irq_get = gen8_ring_get_irq;
2803                 engine->irq_put = gen8_ring_put_irq;
2804                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2805                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2806                 engine->get_seqno = ring_get_seqno;
2807                 engine->set_seqno = ring_set_seqno;
2808                 if (i915_semaphore_is_enabled(dev)) {
2809                         WARN_ON(!dev_priv->semaphore_obj);
2810                         engine->semaphore.sync_to = gen8_ring_sync;
2811                         engine->semaphore.signal = gen8_rcs_signal;
2812                         GEN8_RING_SEMAPHORE_INIT(engine);
2813                 }
2814         } else if (INTEL_INFO(dev)->gen >= 6) {
2815                 engine->init_context = intel_rcs_ctx_init;
2816                 engine->add_request = gen6_add_request;
2817                 engine->flush = gen7_render_ring_flush;
2818                 if (INTEL_INFO(dev)->gen == 6)
2819                         engine->flush = gen6_render_ring_flush;
2820                 engine->irq_get = gen6_ring_get_irq;
2821                 engine->irq_put = gen6_ring_put_irq;
2822                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2823                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2824                 engine->get_seqno = ring_get_seqno;
2825                 engine->set_seqno = ring_set_seqno;
2826                 if (i915_semaphore_is_enabled(dev)) {
2827                         engine->semaphore.sync_to = gen6_ring_sync;
2828                         engine->semaphore.signal = gen6_signal;
2829                         /*
2830                          * The current semaphore is only applied on pre-gen8
2831                          * platform.  And there is no VCS2 ring on the pre-gen8
2832                          * platform. So the semaphore between RCS and VCS2 is
2833                          * initialized as INVALID.  Gen8 will initialize the
2834                          * sema between VCS2 and RCS later.
2835                          */
2836                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2837                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2838                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2839                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2840                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2841                         engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2842                         engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2843                         engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2844                         engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2845                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2846                 }
2847         } else if (IS_GEN5(dev)) {
2848                 engine->add_request = pc_render_add_request;
2849                 engine->flush = gen4_render_ring_flush;
2850                 engine->get_seqno = pc_render_get_seqno;
2851                 engine->set_seqno = pc_render_set_seqno;
2852                 engine->irq_get = gen5_ring_get_irq;
2853                 engine->irq_put = gen5_ring_put_irq;
2854                 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2855                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2856         } else {
2857                 engine->add_request = i9xx_add_request;
2858                 if (INTEL_INFO(dev)->gen < 4)
2859                         engine->flush = gen2_render_ring_flush;
2860                 else
2861                         engine->flush = gen4_render_ring_flush;
2862                 engine->get_seqno = ring_get_seqno;
2863                 engine->set_seqno = ring_set_seqno;
2864                 if (IS_GEN2(dev)) {
2865                         engine->irq_get = i8xx_ring_get_irq;
2866                         engine->irq_put = i8xx_ring_put_irq;
2867                 } else {
2868                         engine->irq_get = i9xx_ring_get_irq;
2869                         engine->irq_put = i9xx_ring_put_irq;
2870                 }
2871                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2872         }
2873         engine->write_tail = ring_write_tail;
2874
2875         if (IS_HASWELL(dev))
2876                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2877         else if (IS_GEN8(dev))
2878                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2879         else if (INTEL_INFO(dev)->gen >= 6)
2880                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2881         else if (INTEL_INFO(dev)->gen >= 4)
2882                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2883         else if (IS_I830(dev) || IS_845G(dev))
2884                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2885         else
2886                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2887         engine->init_hw = init_render_ring;
2888         engine->cleanup = render_ring_cleanup;
2889
2890         /* Workaround batchbuffer to combat CS tlb bug. */
2891         if (HAS_BROKEN_CS_TLB(dev)) {
2892                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2893                 if (obj == NULL) {
2894                         DRM_ERROR("Failed to allocate batch bo\n");
2895                         return -ENOMEM;
2896                 }
2897
2898                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2899                 if (ret != 0) {
2900                         drm_gem_object_unreference(&obj->base);
2901                         DRM_ERROR("Failed to ping batch bo\n");
2902                         return ret;
2903                 }
2904
2905                 engine->scratch.obj = obj;
2906                 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2907         }
2908
2909         ret = intel_init_ring_buffer(dev, engine);
2910         if (ret)
2911                 return ret;
2912
2913         if (INTEL_INFO(dev)->gen >= 5) {
2914                 ret = intel_init_pipe_control(engine);
2915                 if (ret)
2916                         return ret;
2917         }
2918
2919         return 0;
2920 }
2921
2922 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2923 {
2924         struct drm_i915_private *dev_priv = dev->dev_private;
2925         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2926
2927         engine->name = "bsd ring";
2928         engine->id = VCS;
2929         engine->exec_id = I915_EXEC_BSD;
2930         engine->hw_id = 1;
2931
2932         engine->write_tail = ring_write_tail;
2933         if (INTEL_INFO(dev)->gen >= 6) {
2934                 engine->mmio_base = GEN6_BSD_RING_BASE;
2935                 /* gen6 bsd needs a special wa for tail updates */
2936                 if (IS_GEN6(dev))
2937                         engine->write_tail = gen6_bsd_ring_write_tail;
2938                 engine->flush = gen6_bsd_ring_flush;
2939                 engine->add_request = gen6_add_request;
2940                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2941                 engine->get_seqno = ring_get_seqno;
2942                 engine->set_seqno = ring_set_seqno;
2943                 if (INTEL_INFO(dev)->gen >= 8) {
2944                         engine->irq_enable_mask =
2945                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2946                         engine->irq_get = gen8_ring_get_irq;
2947                         engine->irq_put = gen8_ring_put_irq;
2948                         engine->dispatch_execbuffer =
2949                                 gen8_ring_dispatch_execbuffer;
2950                         if (i915_semaphore_is_enabled(dev)) {
2951                                 engine->semaphore.sync_to = gen8_ring_sync;
2952                                 engine->semaphore.signal = gen8_xcs_signal;
2953                                 GEN8_RING_SEMAPHORE_INIT(engine);
2954                         }
2955                 } else {
2956                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2957                         engine->irq_get = gen6_ring_get_irq;
2958                         engine->irq_put = gen6_ring_put_irq;
2959                         engine->dispatch_execbuffer =
2960                                 gen6_ring_dispatch_execbuffer;
2961                         if (i915_semaphore_is_enabled(dev)) {
2962                                 engine->semaphore.sync_to = gen6_ring_sync;
2963                                 engine->semaphore.signal = gen6_signal;
2964                                 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2965                                 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2966                                 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2967                                 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2968                                 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2969                                 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2970                                 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2971                                 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2972                                 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2973                                 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2974                         }
2975                 }
2976         } else {
2977                 engine->mmio_base = BSD_RING_BASE;
2978                 engine->flush = bsd_ring_flush;
2979                 engine->add_request = i9xx_add_request;
2980                 engine->get_seqno = ring_get_seqno;
2981                 engine->set_seqno = ring_set_seqno;
2982                 if (IS_GEN5(dev)) {
2983                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2984                         engine->irq_get = gen5_ring_get_irq;
2985                         engine->irq_put = gen5_ring_put_irq;
2986                 } else {
2987                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2988                         engine->irq_get = i9xx_ring_get_irq;
2989                         engine->irq_put = i9xx_ring_put_irq;
2990                 }
2991                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2992         }
2993         engine->init_hw = init_ring_common;
2994
2995         return intel_init_ring_buffer(dev, engine);
2996 }
2997
2998 /**
2999  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
3000  */
3001 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
3005
3006         engine->name = "bsd2 ring";
3007         engine->id = VCS2;
3008         engine->exec_id = I915_EXEC_BSD;
3009         engine->hw_id = 4;
3010
3011         engine->write_tail = ring_write_tail;
3012         engine->mmio_base = GEN8_BSD2_RING_BASE;
3013         engine->flush = gen6_bsd_ring_flush;
3014         engine->add_request = gen6_add_request;
3015         engine->irq_seqno_barrier = gen6_seqno_barrier;
3016         engine->get_seqno = ring_get_seqno;
3017         engine->set_seqno = ring_set_seqno;
3018         engine->irq_enable_mask =
3019                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3020         engine->irq_get = gen8_ring_get_irq;
3021         engine->irq_put = gen8_ring_put_irq;
3022         engine->dispatch_execbuffer =
3023                         gen8_ring_dispatch_execbuffer;
3024         if (i915_semaphore_is_enabled(dev)) {
3025                 engine->semaphore.sync_to = gen8_ring_sync;
3026                 engine->semaphore.signal = gen8_xcs_signal;
3027                 GEN8_RING_SEMAPHORE_INIT(engine);
3028         }
3029         engine->init_hw = init_ring_common;
3030
3031         return intel_init_ring_buffer(dev, engine);
3032 }
3033
3034 int intel_init_blt_ring_buffer(struct drm_device *dev)
3035 {
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3038
3039         engine->name = "blitter ring";
3040         engine->id = BCS;
3041         engine->exec_id = I915_EXEC_BLT;
3042         engine->hw_id = 2;
3043
3044         engine->mmio_base = BLT_RING_BASE;
3045         engine->write_tail = ring_write_tail;
3046         engine->flush = gen6_ring_flush;
3047         engine->add_request = gen6_add_request;
3048         engine->irq_seqno_barrier = gen6_seqno_barrier;
3049         engine->get_seqno = ring_get_seqno;
3050         engine->set_seqno = ring_set_seqno;
3051         if (INTEL_INFO(dev)->gen >= 8) {
3052                 engine->irq_enable_mask =
3053                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3054                 engine->irq_get = gen8_ring_get_irq;
3055                 engine->irq_put = gen8_ring_put_irq;
3056                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3057                 if (i915_semaphore_is_enabled(dev)) {
3058                         engine->semaphore.sync_to = gen8_ring_sync;
3059                         engine->semaphore.signal = gen8_xcs_signal;
3060                         GEN8_RING_SEMAPHORE_INIT(engine);
3061                 }
3062         } else {
3063                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3064                 engine->irq_get = gen6_ring_get_irq;
3065                 engine->irq_put = gen6_ring_put_irq;
3066                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3067                 if (i915_semaphore_is_enabled(dev)) {
3068                         engine->semaphore.signal = gen6_signal;
3069                         engine->semaphore.sync_to = gen6_ring_sync;
3070                         /*
3071                          * The current semaphore is only applied on pre-gen8
3072                          * platform.  And there is no VCS2 ring on the pre-gen8
3073                          * platform. So the semaphore between BCS and VCS2 is
3074                          * initialized as INVALID.  Gen8 will initialize the
3075                          * sema between BCS and VCS2 later.
3076                          */
3077                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3078                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3079                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3080                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3081                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3082                         engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3083                         engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3084                         engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3085                         engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3086                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3087                 }
3088         }
3089         engine->init_hw = init_ring_common;
3090
3091         return intel_init_ring_buffer(dev, engine);
3092 }
3093
3094 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3095 {
3096         struct drm_i915_private *dev_priv = dev->dev_private;
3097         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3098
3099         engine->name = "video enhancement ring";
3100         engine->id = VECS;
3101         engine->exec_id = I915_EXEC_VEBOX;
3102         engine->hw_id = 3;
3103
3104         engine->mmio_base = VEBOX_RING_BASE;
3105         engine->write_tail = ring_write_tail;
3106         engine->flush = gen6_ring_flush;
3107         engine->add_request = gen6_add_request;
3108         engine->irq_seqno_barrier = gen6_seqno_barrier;
3109         engine->get_seqno = ring_get_seqno;
3110         engine->set_seqno = ring_set_seqno;
3111
3112         if (INTEL_INFO(dev)->gen >= 8) {
3113                 engine->irq_enable_mask =
3114                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3115                 engine->irq_get = gen8_ring_get_irq;
3116                 engine->irq_put = gen8_ring_put_irq;
3117                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3118                 if (i915_semaphore_is_enabled(dev)) {
3119                         engine->semaphore.sync_to = gen8_ring_sync;
3120                         engine->semaphore.signal = gen8_xcs_signal;
3121                         GEN8_RING_SEMAPHORE_INIT(engine);
3122                 }
3123         } else {
3124                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3125                 engine->irq_get = hsw_vebox_get_irq;
3126                 engine->irq_put = hsw_vebox_put_irq;
3127                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3128                 if (i915_semaphore_is_enabled(dev)) {
3129                         engine->semaphore.sync_to = gen6_ring_sync;
3130                         engine->semaphore.signal = gen6_signal;
3131                         engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3132                         engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3133                         engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3134                         engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3135                         engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3136                         engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3137                         engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3138                         engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3139                         engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3140                         engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3141                 }
3142         }
3143         engine->init_hw = init_ring_common;
3144
3145         return intel_init_ring_buffer(dev, engine);
3146 }
3147
3148 int
3149 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3150 {
3151         struct intel_engine_cs *engine = req->engine;
3152         int ret;
3153
3154         if (!engine->gpu_caches_dirty)
3155                 return 0;
3156
3157         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3158         if (ret)
3159                 return ret;
3160
3161         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3162
3163         engine->gpu_caches_dirty = false;
3164         return 0;
3165 }
3166
3167 int
3168 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3169 {
3170         struct intel_engine_cs *engine = req->engine;
3171         uint32_t flush_domains;
3172         int ret;
3173
3174         flush_domains = 0;
3175         if (engine->gpu_caches_dirty)
3176                 flush_domains = I915_GEM_GPU_DOMAINS;
3177
3178         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3179         if (ret)
3180                 return ret;
3181
3182         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3183
3184         engine->gpu_caches_dirty = false;
3185         return 0;
3186 }
3187
3188 void
3189 intel_stop_engine(struct intel_engine_cs *engine)
3190 {
3191         int ret;
3192
3193         if (!intel_engine_initialized(engine))
3194                 return;
3195
3196         ret = intel_engine_idle(engine);
3197         if (ret)
3198                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3199                           engine->name, ret);
3200
3201         stop_ring(engine);
3202 }