drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 #ifndef ETH_ALEN
  94 #define ETH_ALEN        6
  95 #endif
  96 static inline u64 mlx4_mac_to_u64(u8 *addr)
  97 {
  98         u64 mac = 0;
  99         int i;
 100
 101         for (i = 0; i < ETH_ALEN; i++) {
 102                 mac <<= 8;
 103                 mac |= addr[i];
 104         }
 105         return mac;
 106 }
 107
 108 static const __be32 mlx4_ib_opcode[] = {
 109         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 110         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 111         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 112         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 113         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 114         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 115         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 116         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 117         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 118         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 119         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 120         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 121         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 122         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 123 };
 124
 125 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 126 {
 127         return container_of(mqp, struct mlx4_ib_sqp, qp);
 128 }
 129
 130 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 131 {
 132         if (!mlx4_is_master(dev->dev))
 133                 return 0;
 134
 135         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 136                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 137                 8 * MLX4_MFUNC_MAX;
 138 }
 139
 140 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 141 {
 142         int proxy_sqp = 0;
 143         int real_sqp = 0;
 144         int i;
 145         /* PPF or Native -- real SQP */
 146         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 147                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 148                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 149         if (real_sqp)
 150                 return 1;
 151         /* VF or PF -- proxy SQP */
 152         if (mlx4_is_mfunc(dev->dev)) {
 153                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 154                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 155                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 156                                 proxy_sqp = 1;
 157                                 break;
 158                         }
 159                 }
 160         }
 161         return proxy_sqp;
 162 }
 163
 164 /* used for INIT/CLOSE port logic */
 165 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 166 {
 167         int proxy_qp0 = 0;
 168         int real_qp0 = 0;
 169         int i;
 170         /* PPF or Native -- real QP0 */
 171         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 172                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 173                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 174         if (real_qp0)
 175                 return 1;
 176         /* VF or PF -- proxy QP0 */
 177         if (mlx4_is_mfunc(dev->dev)) {
 178                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 179                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 180                                 proxy_qp0 = 1;
 181                                 break;
 182                         }
 183                 }
 184         }
 185         return proxy_qp0;
 186 }
 187
 188 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 189 {
 190         return mlx4_buf_offset(&qp->buf, offset);
 191 }
 192
 193 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 196 }
 197
 198 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 199 {
 200         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 201 }
 202
 203 /*
 204  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 205  * first four bytes of every 64 byte chunk with
 206  *     0x7FFFFFF | (invalid_ownership_value << 31).
 207  *
 208  * When the max work request size is less than or equal to the WQE
 209  * basic block size, as an optimization, we can stamp all WQEs with
 210  * 0xffffffff, and skip the very first chunk of each WQE.
 211  */
 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 213 {
 214         __be32 *wqe;
 215         int i;
 216         int s;
 217         int ind;
 218         void *buf;
 219         __be32 stamp;
 220         struct mlx4_wqe_ctrl_seg *ctrl;
 221
 222         if (qp->sq_max_wqes_per_wr > 1) {
 223                 s = roundup(size, 1U << qp->sq.wqe_shift);
 224                 for (i = 0; i < s; i += 64) {
 225                         ind = (i >> qp->sq.wqe_shift) + n;
 226                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 227                                                        cpu_to_be32(0xffffffff);
 228                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 229                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 230                         *wqe = stamp;
 231                 }
 232         } else {
 233                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 234                 s = (ctrl->fence_size & 0x3f) << 4;
 235                 for (i = 64; i < s; i += 64) {
 236                         wqe = buf + i;
 237                         *wqe = cpu_to_be32(0xffffffff);
 238                 }
 239         }
 240 }
 241
 242 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 243 {
 244         struct mlx4_wqe_ctrl_seg *ctrl;
 245         struct mlx4_wqe_inline_seg *inl;
 246         void *wqe;
 247         int s;
 248
 249         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 250         s = sizeof(struct mlx4_wqe_ctrl_seg);
 251
 252         if (qp->ibqp.qp_type == IB_QPT_UD) {
 253                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 254                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 255                 memset(dgram, 0, sizeof *dgram);
 256                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 257                 s += sizeof(struct mlx4_wqe_datagram_seg);
 258         }
 259
 260         /* Pad the remainder of the WQE with an inline data segment. */
 261         if (size > s) {
 262                 inl = wqe + s;
 263                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 264         }
 265         ctrl->srcrb_flags = 0;
 266         ctrl->fence_size = size / 16;
 267         /*
 268          * Make sure descriptor is fully written before setting ownership bit
 269          * (because HW can start executing as soon as we do).
 270          */
 271         wmb();
 272
 273         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 274                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 275
 276         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 277 }
 278
 279 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 280 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 281 {
 282         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 283         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 284                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 285                 ind += s;
 286         }
 287         return ind;
 288 }
 289
 290 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 291 {
 292         struct ib_event event;
 293         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 294
 295         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 296                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 297
 298         if (ibqp->event_handler) {
 299                 event.device     = ibqp->device;
 300                 event.element.qp = ibqp;
 301                 switch (type) {
 302                 case MLX4_EVENT_TYPE_PATH_MIG:
 303                         event.event = IB_EVENT_PATH_MIG;
 304                         break;
 305                 case MLX4_EVENT_TYPE_COMM_EST:
 306                         event.event = IB_EVENT_COMM_EST;
 307                         break;
 308                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 309                         event.event = IB_EVENT_SQ_DRAINED;
 310                         break;
 311                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 312                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 313                         break;
 314                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 315                         event.event = IB_EVENT_QP_FATAL;
 316                         break;
 317                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 318                         event.event = IB_EVENT_PATH_MIG_ERR;
 319                         break;
 320                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 321                         event.event = IB_EVENT_QP_REQ_ERR;
 322                         break;
 323                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 324                         event.event = IB_EVENT_QP_ACCESS_ERR;
 325                         break;
 326                 default:
 327                         pr_warn("Unexpected event type %d "
 328                                "on QP %06x\n", type, qp->qpn);
 329                         return;
 330                 }
 331
 332                 ibqp->event_handler(&event, ibqp->qp_context);
 333         }
 334 }
 335
 336 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 337 {
 338         /*
 339          * UD WQEs must have a datagram segment.
 340          * RC and UC WQEs might have a remote address segment.
 341          * MLX WQEs need two extra inline data segments (for the UD
 342          * header and space for the ICRC).
 343          */
 344         switch (type) {
 345         case MLX4_IB_QPT_UD:
 346                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 347                         sizeof (struct mlx4_wqe_datagram_seg) +
 348                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 349         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 350         case MLX4_IB_QPT_PROXY_SMI:
 351         case MLX4_IB_QPT_PROXY_GSI:
 352                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 353                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 354         case MLX4_IB_QPT_TUN_SMI_OWNER:
 355         case MLX4_IB_QPT_TUN_GSI:
 356                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 357                         sizeof (struct mlx4_wqe_datagram_seg);
 358
 359         case MLX4_IB_QPT_UC:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_raddr_seg);
 362         case MLX4_IB_QPT_RC:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         sizeof (struct mlx4_wqe_atomic_seg) +
 365                         sizeof (struct mlx4_wqe_raddr_seg);
 366         case MLX4_IB_QPT_SMI:
 367         case MLX4_IB_QPT_GSI:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 370                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 371                                            MLX4_INLINE_ALIGN) *
 372                               sizeof (struct mlx4_wqe_inline_seg),
 373                               sizeof (struct mlx4_wqe_data_seg)) +
 374                         ALIGN(4 +
 375                               sizeof (struct mlx4_wqe_inline_seg),
 376                               sizeof (struct mlx4_wqe_data_seg));
 377         default:
 378                 return sizeof (struct mlx4_wqe_ctrl_seg);
 379         }
 380 }
 381
 382 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 383                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 384 {
 385         /* Sanity check RQ size before proceeding */
 386         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 387             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 388                 return -EINVAL;
 389
 390         if (!has_rq) {
 391                 if (cap->max_recv_wr)
 392                         return -EINVAL;
 393
 394                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 395         } else {
 396                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 397                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 398                         return -EINVAL;
 399
 400                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 401                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 402                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 403         }
 404
 405         /* leave userspace return values as they were, so as not to break ABI */
 406         if (is_user) {
 407                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 408                 cap->max_recv_sge = qp->rq.max_gs;
 409         } else {
 410                 cap->max_recv_wr  = qp->rq.max_post =
 411                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 412                 cap->max_recv_sge = min(qp->rq.max_gs,
 413                                         min(dev->dev->caps.max_sq_sg,
 414                                             dev->dev->caps.max_rq_sg));
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 421                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 422 {
 423         int s;
 424
 425         /* Sanity check SQ size before proceeding */
 426         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 427             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 428             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 429             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 430                 return -EINVAL;
 431
 432         /*
 433          * For MLX transport we need 2 extra S/G entries:
 434          * one for the header and one for the checksum at the end
 435          */
 436         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 437              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 438             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 439                 return -EINVAL;
 440
 441         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 442                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 443                 send_wqe_overhead(type, qp->flags);
 444
 445         if (s > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * Hermon supports shrinking WQEs, such that a single work
 450          * request can include multiple units of 1 << wqe_shift.  This
 451          * way, work requests can differ in size, and do not have to
 452          * be a power of 2 in size, saving memory and speeding up send
 453          * WR posting.  Unfortunately, if we do this then the
 454          * wqe_index field in CQEs can't be used to look up the WR ID
 455          * anymore, so we do this only if selective signaling is off.
 456          *
 457          * Further, on 32-bit platforms, we can't use vmap() to make
 458          * the QP buffer virtually contiguous.  Thus we have to use
 459          * constant-sized WRs to make sure a WR is always fully within
 460          * a single page-sized chunk.
 461          *
 462          * Finally, we use NOP work requests to pad the end of the
 463          * work queue, to avoid wrap-around in the middle of WR.  We
 464          * set NEC bit to avoid getting completions with error for
 465          * these NOP WRs, but since NEC is only supported starting
 466          * with firmware 2.2.232, we use constant-sized WRs for older
 467          * firmware.
 468          *
 469          * And, since MLX QPs only support SEND, we use constant-sized
 470          * WRs in this case.
 471          *
 472          * We look for the smallest value of wqe_shift such that the
 473          * resulting number of wqes does not exceed device
 474          * capabilities.
 475          *
 476          * We set WQE size to at least 64 bytes, this way stamping
 477          * invalidates each WQE.
 478          */
 479         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 480             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 481             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 482             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 483                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 484                 qp->sq.wqe_shift = ilog2(64);
 485         else
 486                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 487
 488         for (;;) {
 489                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 490
 491                 /*
 492                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 493                  * allow HW to prefetch.
 494                  */
 495                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 496                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 497                                                     qp->sq_max_wqes_per_wr +
 498                                                     qp->sq_spare_wqes);
 499
 500                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 501                         break;
 502
 503                 if (qp->sq_max_wqes_per_wr <= 1)
 504                         return -EINVAL;
 505
 506                 ++qp->sq.wqe_shift;
 507         }
 508
 509         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 510                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 511                          send_wqe_overhead(type, qp->flags)) /
 512                 sizeof (struct mlx4_wqe_data_seg);
 513
 514         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 515                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 516         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 517                 qp->rq.offset = 0;
 518                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 519         } else {
 520                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 521                 qp->sq.offset = 0;
 522         }
 523
 524         cap->max_send_wr  = qp->sq.max_post =
 525                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 526         cap->max_send_sge = min(qp->sq.max_gs,
 527                                 min(dev->dev->caps.max_sq_sg,
 528                                     dev->dev->caps.max_rq_sg));
 529         /* We don't support inline sends for kernel QPs (yet) */
 530         cap->max_inline_data = 0;
 531
 532         return 0;
 533 }
 534
 535 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 536                             struct mlx4_ib_qp *qp,
 537                             struct mlx4_ib_create_qp *ucmd)
 538 {
 539         /* Sanity check SQ size before proceeding */
 540         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 541             ucmd->log_sq_stride >
 542                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 543             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 544                 return -EINVAL;
 545
 546         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 547         qp->sq.wqe_shift = ucmd->log_sq_stride;
 548
 549         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 550                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 551
 552         return 0;
 553 }
 554
 555 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 556 {
 557         int i;
 558
 559         qp->sqp_proxy_rcv =
 560                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 561                         GFP_KERNEL);
 562         if (!qp->sqp_proxy_rcv)
 563                 return -ENOMEM;
 564         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 565                 qp->sqp_proxy_rcv[i].addr =
 566                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 567                                 GFP_KERNEL);
 568                 if (!qp->sqp_proxy_rcv[i].addr)
 569                         goto err;
 570                 qp->sqp_proxy_rcv[i].map =
 571                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 572                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 573                                           DMA_FROM_DEVICE);
 574         }
 575         return 0;
 576
 577 err:
 578         while (i > 0) {
 579                 --i;
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586         qp->sqp_proxy_rcv = NULL;
 587         return -ENOMEM;
 588 }
 589
 590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 591 {
 592         int i;
 593
 594         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 595                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 596                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 597                                     DMA_FROM_DEVICE);
 598                 kfree(qp->sqp_proxy_rcv[i].addr);
 599         }
 600         kfree(qp->sqp_proxy_rcv);
 601 }
 602
 603 static int qp_has_rq(struct ib_qp_init_attr *attr)
 604 {
 605         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 606                 return 0;
 607
 608         return !attr->srq;
 609 }
 610
 611 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 612 {
 613         int i;
 614         for (i = 0; i < dev->caps.num_ports; i++) {
 615                 if (qpn == dev->caps.qp0_proxy[i])
 616                         return !!dev->caps.qp0_qkey[i];
 617         }
 618         return 0;
 619 }
 620
 621 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 622                             struct ib_qp_init_attr *init_attr,
 623                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
 624                             gfp_t gfp)
 625 {
 626         int qpn;
 627         int err;
 628         struct mlx4_ib_sqp *sqp;
 629         struct mlx4_ib_qp *qp;
 630         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 631
 632         /* When tunneling special qps, we use a plain UD qp */
 633         if (sqpn) {
 634                 if (mlx4_is_mfunc(dev->dev) &&
 635                     (!mlx4_is_master(dev->dev) ||
 636                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 637                         if (init_attr->qp_type == IB_QPT_GSI)
 638                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 639                         else {
 640                                 if (mlx4_is_master(dev->dev) ||
 641                                     qp0_enabled_vf(dev->dev, sqpn))
 642                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 643                                 else
 644                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 645                         }
 646                 }
 647                 qpn = sqpn;
 648                 /* add extra sg entry for tunneling */
 649                 init_attr->cap.max_recv_sge++;
 650         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 651                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 652                         container_of(init_attr,
 653                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 654                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 655                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 656                     !mlx4_is_master(dev->dev))
 657                         return -EINVAL;
 658                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 659                         qp_type = MLX4_IB_QPT_TUN_GSI;
 660                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 661                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 662                                              tnl_init->port))
 663                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 664                 else
 665                         qp_type = MLX4_IB_QPT_TUN_SMI;
 666                 /* we are definitely in the PPF here, since we are creating
 667                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 668                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 669                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 670                 sqpn = qpn;
 671         }
 672
 673         if (!*caller_qp) {
 674                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 675                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 676                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 677                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
 678                         if (!sqp)
 679                                 return -ENOMEM;
 680                         qp = &sqp->qp;
 681                         qp->pri.vid = 0xFFFF;
 682                         qp->alt.vid = 0xFFFF;
 683                 } else {
 684                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
 685                         if (!qp)
 686                                 return -ENOMEM;
 687                         qp->pri.vid = 0xFFFF;
 688                         qp->alt.vid = 0xFFFF;
 689                 }
 690         } else
 691                 qp = *caller_qp;
 692
 693         qp->mlx4_ib_qp_type = qp_type;
 694
 695         mutex_init(&qp->mutex);
 696         spin_lock_init(&qp->sq.lock);
 697         spin_lock_init(&qp->rq.lock);
 698         INIT_LIST_HEAD(&qp->gid_list);
 699         INIT_LIST_HEAD(&qp->steering_rules);
 700
 701         qp->state        = IB_QPS_RESET;
 702         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 703                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 704
 705         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 706         if (err)
 707                 goto err;
 708
 709         if (pd->uobject) {
 710                 struct mlx4_ib_create_qp ucmd;
 711
 712                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 713                         err = -EFAULT;
 714                         goto err;
 715                 }
 716
 717                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 718
 719                 err = set_user_sq_size(dev, qp, &ucmd);
 720                 if (err)
 721                         goto err;
 722
 723                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 724                                        qp->buf_size, 0, 0);
 725                 if (IS_ERR(qp->umem)) {
 726                         err = PTR_ERR(qp->umem);
 727                         goto err;
 728                 }
 729
 730                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 731                                     ilog2(qp->umem->page_size), &qp->mtt);
 732                 if (err)
 733                         goto err_buf;
 734
 735                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 736                 if (err)
 737                         goto err_mtt;
 738
 739                 if (qp_has_rq(init_attr)) {
 740                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 741                                                   ucmd.db_addr, &qp->db);
 742                         if (err)
 743                                 goto err_mtt;
 744                 }
 745         } else {
 746                 qp->sq_no_prefetch = 0;
 747
 748                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 749                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 750
 751                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 752                         qp->flags |= MLX4_IB_QP_LSO;
 753
 754                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 755                         if (dev->steering_support ==
 756                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 757                                 qp->flags |= MLX4_IB_QP_NETIF;
 758                         else
 759                                 goto err;
 760                 }
 761
 762                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 763                 if (err)
 764                         goto err;
 765
 766                 if (qp_has_rq(init_attr)) {
 767                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
 768                         if (err)
 769                                 goto err;
 770
 771                         *qp->db.db = 0;
 772                 }
 773
 774                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
 775                         err = -ENOMEM;
 776                         goto err_db;
 777                 }
 778
 779                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 780                                     &qp->mtt);
 781                 if (err)
 782                         goto err_buf;
 783
 784                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
 785                 if (err)
 786                         goto err_mtt;
 787
 788                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
 789                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
 790                 if (!qp->sq.wrid || !qp->rq.wrid) {
 791                         err = -ENOMEM;
 792                         goto err_wrid;
 793                 }
 794         }
 795
 796         if (sqpn) {
 797                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 798                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 799                         if (alloc_proxy_bufs(pd->device, qp)) {
 800                                 err = -ENOMEM;
 801                                 goto err_wrid;
 802                         }
 803                 }
 804         } else {
 805                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 806                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 807                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 808                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 809                 else
 810                         if (qp->flags & MLX4_IB_QP_NETIF)
 811                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 812                         else
 813                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 814                                                             &qpn);
 815                 if (err)
 816                         goto err_proxy;
 817         }
 818
 819         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
 820         if (err)
 821                 goto err_qpn;
 822
 823         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 824                 qp->mqp.qpn |= (1 << 23);
 825
 826         /*
 827          * Hardware wants QPN written in big-endian order (after
 828          * shifting) for send doorbell.  Precompute this value to save
 829          * a little bit when posting sends.
 830          */
 831         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 832
 833         qp->mqp.event = mlx4_ib_qp_event;
 834         if (!*caller_qp)
 835                 *caller_qp = qp;
 836         return 0;
 837
 838 err_qpn:
 839         if (!sqpn) {
 840                 if (qp->flags & MLX4_IB_QP_NETIF)
 841                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 842                 else
 843                         mlx4_qp_release_range(dev->dev, qpn, 1);
 844         }
 845 err_proxy:
 846         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 847                 free_proxy_bufs(pd->device, qp);
 848 err_wrid:
 849         if (pd->uobject) {
 850                 if (qp_has_rq(init_attr))
 851                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 852         } else {
 853                 kfree(qp->sq.wrid);
 854                 kfree(qp->rq.wrid);
 855         }
 856
 857 err_mtt:
 858         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 859
 860 err_buf:
 861         if (pd->uobject)
 862                 ib_umem_release(qp->umem);
 863         else
 864                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 865
 866 err_db:
 867         if (!pd->uobject && qp_has_rq(init_attr))
 868                 mlx4_db_free(dev->dev, &qp->db);
 869
 870 err:
 871         if (!*caller_qp)
 872                 kfree(qp);
 873         return err;
 874 }
 875
 876 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 877 {
 878         switch (state) {
 879         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 880         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 881         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 882         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 883         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 884         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 885         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 886         default:                return -1;
 887         }
 888 }
 889
 890 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 891         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 892 {
 893         if (send_cq == recv_cq) {
 894                 spin_lock_irq(&send_cq->lock);
 895                 __acquire(&recv_cq->lock);
 896         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 897                 spin_lock_irq(&send_cq->lock);
 898                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 899         } else {
 900                 spin_lock_irq(&recv_cq->lock);
 901                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 902         }
 903 }
 904
 905 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 906         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 907 {
 908         if (send_cq == recv_cq) {
 909                 __release(&recv_cq->lock);
 910                 spin_unlock_irq(&send_cq->lock);
 911         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 912                 spin_unlock(&recv_cq->lock);
 913                 spin_unlock_irq(&send_cq->lock);
 914         } else {
 915                 spin_unlock(&send_cq->lock);
 916                 spin_unlock_irq(&recv_cq->lock);
 917         }
 918 }
 919
 920 static void del_gid_entries(struct mlx4_ib_qp *qp)
 921 {
 922         struct mlx4_ib_gid_entry *ge, *tmp;
 923
 924         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 925                 list_del(&ge->list);
 926                 kfree(ge);
 927         }
 928 }
 929
 930 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 931 {
 932         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 933                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 934         else
 935                 return to_mpd(qp->ibqp.pd);
 936 }
 937
 938 static void get_cqs(struct mlx4_ib_qp *qp,
 939                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 940 {
 941         switch (qp->ibqp.qp_type) {
 942         case IB_QPT_XRC_TGT:
 943                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 944                 *recv_cq = *send_cq;
 945                 break;
 946         case IB_QPT_XRC_INI:
 947                 *send_cq = to_mcq(qp->ibqp.send_cq);
 948                 *recv_cq = *send_cq;
 949                 break;
 950         default:
 951                 *send_cq = to_mcq(qp->ibqp.send_cq);
 952                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 953                 break;
 954         }
 955 }
 956
 957 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 958                               int is_user)
 959 {
 960         struct mlx4_ib_cq *send_cq, *recv_cq;
 961
 962         if (qp->state != IB_QPS_RESET) {
 963                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 964                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 965                         pr_warn("modify QP %06x to RESET failed.\n",
 966                                qp->mqp.qpn);
 967                 if (qp->pri.smac) {
 968                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
 969                         qp->pri.smac = 0;
 970                 }
 971                 if (qp->alt.smac) {
 972                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
 973                         qp->alt.smac = 0;
 974                 }
 975                 if (qp->pri.vid < 0x1000) {
 976                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
 977                         qp->pri.vid = 0xFFFF;
 978                         qp->pri.candidate_vid = 0xFFFF;
 979                         qp->pri.update_vid = 0;
 980                 }
 981                 if (qp->alt.vid < 0x1000) {
 982                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
 983                         qp->alt.vid = 0xFFFF;
 984                         qp->alt.candidate_vid = 0xFFFF;
 985                         qp->alt.update_vid = 0;
 986                 }
 987         }
 988
 989         get_cqs(qp, &send_cq, &recv_cq);
 990
 991         mlx4_ib_lock_cqs(send_cq, recv_cq);
 992
 993         if (!is_user) {
 994                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 995                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 996                 if (send_cq != recv_cq)
 997                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 998         }
 999
1000         mlx4_qp_remove(dev->dev, &qp->mqp);
1001
1002         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1003
1004         mlx4_qp_free(dev->dev, &qp->mqp);
1005
1006         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1007                 if (qp->flags & MLX4_IB_QP_NETIF)
1008                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1009                 else
1010                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1011         }
1012
1013         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1014
1015         if (is_user) {
1016                 if (qp->rq.wqe_cnt)
1017                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1018                                               &qp->db);
1019                 ib_umem_release(qp->umem);
1020         } else {
1021                 kfree(qp->sq.wrid);
1022                 kfree(qp->rq.wrid);
1023                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1024                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1025                         free_proxy_bufs(&dev->ib_dev, qp);
1026                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1027                 if (qp->rq.wqe_cnt)
1028                         mlx4_db_free(dev->dev, &qp->db);
1029         }
1030
1031         del_gid_entries(qp);
1032 }
1033
1034 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1035 {
1036         /* Native or PPF */
1037         if (!mlx4_is_mfunc(dev->dev) ||
1038             (mlx4_is_master(dev->dev) &&
1039              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1040                 return  dev->dev->phys_caps.base_sqpn +
1041                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1042                         attr->port_num - 1;
1043         }
1044         /* PF or VF -- creating proxies */
1045         if (attr->qp_type == IB_QPT_SMI)
1046                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1047         else
1048                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1049 }
1050
1051 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1052                                 struct ib_qp_init_attr *init_attr,
1053                                 struct ib_udata *udata)
1054 {
1055         struct mlx4_ib_qp *qp = NULL;
1056         int err;
1057         u16 xrcdn = 0;
1058         gfp_t gfp;
1059
1060         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1061                 GFP_NOIO : GFP_KERNEL;
1062         /*
1063          * We only support LSO, vendor flag1, and multicast loopback blocking,
1064          * and only for kernel UD QPs.
1065          */
1066         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1067                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1068                                         MLX4_IB_SRIOV_TUNNEL_QP |
1069                                         MLX4_IB_SRIOV_SQP |
1070                                         MLX4_IB_QP_NETIF |
1071                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1072                 return ERR_PTR(-EINVAL);
1073
1074         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1075                 if (init_attr->qp_type != IB_QPT_UD)
1076                         return ERR_PTR(-EINVAL);
1077         }
1078
1079         if (init_attr->create_flags &&
1080             (udata ||
1081              ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1082               init_attr->qp_type != IB_QPT_UD) ||
1083              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1084               init_attr->qp_type > IB_QPT_GSI)))
1085                 return ERR_PTR(-EINVAL);
1086
1087         switch (init_attr->qp_type) {
1088         case IB_QPT_XRC_TGT:
1089                 pd = to_mxrcd(init_attr->xrcd)->pd;
1090                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1091                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1092                 /* fall through */
1093         case IB_QPT_XRC_INI:
1094                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1095                         return ERR_PTR(-ENOSYS);
1096                 init_attr->recv_cq = init_attr->send_cq;
1097                 /* fall through */
1098         case IB_QPT_RC:
1099         case IB_QPT_UC:
1100         case IB_QPT_RAW_PACKET:
1101                 qp = kzalloc(sizeof *qp, gfp);
1102                 if (!qp)
1103                         return ERR_PTR(-ENOMEM);
1104                 qp->pri.vid = 0xFFFF;
1105                 qp->alt.vid = 0xFFFF;
1106                 /* fall through */
1107         case IB_QPT_UD:
1108         {
1109                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1110                                        udata, 0, &qp, gfp);
1111                 if (err)
1112                         return ERR_PTR(err);
1113
1114                 qp->ibqp.qp_num = qp->mqp.qpn;
1115                 qp->xrcdn = xrcdn;
1116
1117                 break;
1118         }
1119         case IB_QPT_SMI:
1120         case IB_QPT_GSI:
1121         {
1122                 /* Userspace is not allowed to create special QPs: */
1123                 if (udata)
1124                         return ERR_PTR(-EINVAL);
1125
1126                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1127                                        get_sqp_num(to_mdev(pd->device), init_attr),
1128                                        &qp, gfp);
1129                 if (err)
1130                         return ERR_PTR(err);
1131
1132                 qp->port        = init_attr->port_num;
1133                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1134
1135                 break;
1136         }
1137         default:
1138                 /* Don't support raw QPs */
1139                 return ERR_PTR(-EINVAL);
1140         }
1141
1142         return &qp->ibqp;
1143 }
1144
1145 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1146 {
1147         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1148         struct mlx4_ib_qp *mqp = to_mqp(qp);
1149         struct mlx4_ib_pd *pd;
1150
1151         if (is_qp0(dev, mqp))
1152                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1153
1154         if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1155                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1156                 dev->qp1_proxy[mqp->port - 1] = NULL;
1157                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1158         }
1159
1160         pd = get_pd(mqp);
1161         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1162
1163         if (is_sqp(dev, mqp))
1164                 kfree(to_msqp(mqp));
1165         else
1166                 kfree(mqp);
1167
1168         return 0;
1169 }
1170
1171 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1172 {
1173         switch (type) {
1174         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1175         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1176         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1177         case MLX4_IB_QPT_XRC_INI:
1178         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1179         case MLX4_IB_QPT_SMI:
1180         case MLX4_IB_QPT_GSI:
1181         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1182
1183         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1184         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1185                                                 MLX4_QP_ST_MLX : -1);
1186         case MLX4_IB_QPT_PROXY_SMI:
1187         case MLX4_IB_QPT_TUN_SMI:
1188         case MLX4_IB_QPT_PROXY_GSI:
1189         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1190                                                 MLX4_QP_ST_UD : -1);
1191         default:                        return -1;
1192         }
1193 }
1194
1195 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1196                                    int attr_mask)
1197 {
1198         u8 dest_rd_atomic;
1199         u32 access_flags;
1200         u32 hw_access_flags = 0;
1201
1202         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1203                 dest_rd_atomic = attr->max_dest_rd_atomic;
1204         else
1205                 dest_rd_atomic = qp->resp_depth;
1206
1207         if (attr_mask & IB_QP_ACCESS_FLAGS)
1208                 access_flags = attr->qp_access_flags;
1209         else
1210                 access_flags = qp->atomic_rd_en;
1211
1212         if (!dest_rd_atomic)
1213                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1214
1215         if (access_flags & IB_ACCESS_REMOTE_READ)
1216                 hw_access_flags |= MLX4_QP_BIT_RRE;
1217         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1218                 hw_access_flags |= MLX4_QP_BIT_RAE;
1219         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1220                 hw_access_flags |= MLX4_QP_BIT_RWE;
1221
1222         return cpu_to_be32(hw_access_flags);
1223 }
1224
1225 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1226                             int attr_mask)
1227 {
1228         if (attr_mask & IB_QP_PKEY_INDEX)
1229                 sqp->pkey_index = attr->pkey_index;
1230         if (attr_mask & IB_QP_QKEY)
1231                 sqp->qkey = attr->qkey;
1232         if (attr_mask & IB_QP_SQ_PSN)
1233                 sqp->send_psn = attr->sq_psn;
1234 }
1235
1236 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1237 {
1238         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1239 }
1240
1241 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1242                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1243                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1244 {
1245         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1246                 IB_LINK_LAYER_ETHERNET;
1247         int vidx;
1248         int smac_index;
1249         int err;
1250
1251
1252         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1253         path->rlid          = cpu_to_be16(ah->dlid);
1254         if (ah->static_rate) {
1255                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1256                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1257                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1258                         --path->static_rate;
1259         } else
1260                 path->static_rate = 0;
1261
1262         if (ah->ah_flags & IB_AH_GRH) {
1263                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1264                         pr_err("sgid_index (%u) too large. max is %d\n",
1265                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1266                         return -1;
1267                 }
1268
1269                 path->grh_mylmc |= 1 << 7;
1270                 path->mgid_index = ah->grh.sgid_index;
1271                 path->hop_limit  = ah->grh.hop_limit;
1272                 path->tclass_flowlabel =
1273                         cpu_to_be32((ah->grh.traffic_class << 20) |
1274                                     (ah->grh.flow_label));
1275                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1276         }
1277
1278         if (is_eth) {
1279                 if (!(ah->ah_flags & IB_AH_GRH))
1280                         return -1;
1281
1282                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1283                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1284
1285                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1286                 if (vlan_tag < 0x1000) {
1287                         if (smac_info->vid < 0x1000) {
1288                                 /* both valid vlan ids */
1289                                 if (smac_info->vid != vlan_tag) {
1290                                         /* different VIDs.  unreg old and reg new */
1291                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1292                                         if (err)
1293                                                 return err;
1294                                         smac_info->candidate_vid = vlan_tag;
1295                                         smac_info->candidate_vlan_index = vidx;
1296                                         smac_info->candidate_vlan_port = port;
1297                                         smac_info->update_vid = 1;
1298                                         path->vlan_index = vidx;
1299                                 } else {
1300                                         path->vlan_index = smac_info->vlan_index;
1301                                 }
1302                         } else {
1303                                 /* no current vlan tag in qp */
1304                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1305                                 if (err)
1306                                         return err;
1307                                 smac_info->candidate_vid = vlan_tag;
1308                                 smac_info->candidate_vlan_index = vidx;
1309                                 smac_info->candidate_vlan_port = port;
1310                                 smac_info->update_vid = 1;
1311                                 path->vlan_index = vidx;
1312                         }
1313                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1314                         path->fl = 1 << 6;
1315                 } else {
1316                         /* have current vlan tag. unregister it at modify-qp success */
1317                         if (smac_info->vid < 0x1000) {
1318                                 smac_info->candidate_vid = 0xFFFF;
1319                                 smac_info->update_vid = 1;
1320                         }
1321                 }
1322
1323                 /* get smac_index for RoCE use.
1324                  * If no smac was yet assigned, register one.
1325                  * If one was already assigned, but the new mac differs,
1326                  * unregister the old one and register the new one.
1327                 */
1328                 if (!smac_info->smac || smac_info->smac != smac) {
1329                         /* register candidate now, unreg if needed, after success */
1330                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1331                         if (smac_index >= 0) {
1332                                 smac_info->candidate_smac_index = smac_index;
1333                                 smac_info->candidate_smac = smac;
1334                                 smac_info->candidate_smac_port = port;
1335                         } else {
1336                                 return -EINVAL;
1337                         }
1338                 } else {
1339                         smac_index = smac_info->smac_index;
1340                 }
1341
1342                 memcpy(path->dmac, ah->dmac, 6);
1343                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1344                 /* put MAC table smac index for IBoE */
1345                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1346         } else {
1347                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1348                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1349         }
1350
1351         return 0;
1352 }
1353
1354 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1355                          enum ib_qp_attr_mask qp_attr_mask,
1356                          struct mlx4_ib_qp *mqp,
1357                          struct mlx4_qp_path *path, u8 port)
1358 {
1359         return _mlx4_set_path(dev, &qp->ah_attr,
1360                               mlx4_mac_to_u64((u8 *)qp->smac),
1361                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1362                               path, &mqp->pri, port);
1363 }
1364
1365 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1366                              const struct ib_qp_attr *qp,
1367                              enum ib_qp_attr_mask qp_attr_mask,
1368                              struct mlx4_ib_qp *mqp,
1369                              struct mlx4_qp_path *path, u8 port)
1370 {
1371         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1372                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1373                               (qp_attr_mask & IB_QP_ALT_VID) ?
1374                               qp->alt_vlan_id : 0xffff,
1375                               path, &mqp->alt, port);
1376 }
1377
1378 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1379 {
1380         struct mlx4_ib_gid_entry *ge, *tmp;
1381
1382         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1383                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1384                         ge->added = 1;
1385                         ge->port = qp->port;
1386                 }
1387         }
1388 }
1389
1390 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1391                                     struct mlx4_qp_context *context)
1392 {
1393         u64 u64_mac;
1394         int smac_index;
1395
1396         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1397
1398         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1399         if (!qp->pri.smac) {
1400                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1401                 if (smac_index >= 0) {
1402                         qp->pri.candidate_smac_index = smac_index;
1403                         qp->pri.candidate_smac = u64_mac;
1404                         qp->pri.candidate_smac_port = qp->port;
1405                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1406                 } else {
1407                         return -ENOENT;
1408                 }
1409         }
1410         return 0;
1411 }
1412
1413 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1414                                const struct ib_qp_attr *attr, int attr_mask,
1415                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1416 {
1417         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1418         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1419         struct mlx4_ib_pd *pd;
1420         struct mlx4_ib_cq *send_cq, *recv_cq;
1421         struct mlx4_qp_context *context;
1422         enum mlx4_qp_optpar optpar = 0;
1423         int sqd_event;
1424         int steer_qp = 0;
1425         int err = -EINVAL;
1426
1427         /* APM is not supported under RoCE */
1428         if (attr_mask & IB_QP_ALT_PATH &&
1429             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1430             IB_LINK_LAYER_ETHERNET)
1431                 return -ENOTSUPP;
1432
1433         context = kzalloc(sizeof *context, GFP_KERNEL);
1434         if (!context)
1435                 return -ENOMEM;
1436
1437         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1438                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1439
1440         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1441                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1442         else {
1443                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1444                 switch (attr->path_mig_state) {
1445                 case IB_MIG_MIGRATED:
1446                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1447                         break;
1448                 case IB_MIG_REARM:
1449                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1450                         break;
1451                 case IB_MIG_ARMED:
1452                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1453                         break;
1454                 }
1455         }
1456
1457         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1458                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1459         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1460                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1461         else if (ibqp->qp_type == IB_QPT_UD) {
1462                 if (qp->flags & MLX4_IB_QP_LSO)
1463                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1464                                               ilog2(dev->dev->caps.max_gso_sz);
1465                 else
1466                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1467         } else if (attr_mask & IB_QP_PATH_MTU) {
1468                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1469                         pr_err("path MTU (%u) is invalid\n",
1470                                attr->path_mtu);
1471                         goto out;
1472                 }
1473                 context->mtu_msgmax = (attr->path_mtu << 5) |
1474                         ilog2(dev->dev->caps.max_msg_sz);
1475         }
1476
1477         if (qp->rq.wqe_cnt)
1478                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1479         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1480
1481         if (qp->sq.wqe_cnt)
1482                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1483         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1484
1485         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1486                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1487                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1488                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1489                         context->param3 |= cpu_to_be32(1 << 30);
1490         }
1491
1492         if (qp->ibqp.uobject)
1493                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1494         else
1495                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1496
1497         if (attr_mask & IB_QP_DEST_QPN)
1498                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1499
1500         if (attr_mask & IB_QP_PORT) {
1501                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1502                     !(attr_mask & IB_QP_AV)) {
1503                         mlx4_set_sched(&context->pri_path, attr->port_num);
1504                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1505                 }
1506         }
1507
1508         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1509                 if (dev->counters[qp->port - 1] != -1) {
1510                         context->pri_path.counter_index =
1511                                                 dev->counters[qp->port - 1];
1512                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1513                 } else
1514                         context->pri_path.counter_index = 0xff;
1515
1516                 if (qp->flags & MLX4_IB_QP_NETIF) {
1517                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1518                         steer_qp = 1;
1519                 }
1520         }
1521
1522         if (attr_mask & IB_QP_PKEY_INDEX) {
1523                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1524                         context->pri_path.disable_pkey_check = 0x40;
1525                 context->pri_path.pkey_index = attr->pkey_index;
1526                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1527         }
1528
1529         if (attr_mask & IB_QP_AV) {
1530                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1531                                   attr_mask & IB_QP_PORT ?
1532                                   attr->port_num : qp->port))
1533                         goto out;
1534
1535                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1536                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1537         }
1538
1539         if (attr_mask & IB_QP_TIMEOUT) {
1540                 context->pri_path.ackto |= attr->timeout << 3;
1541                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1542         }
1543
1544         if (attr_mask & IB_QP_ALT_PATH) {
1545                 if (attr->alt_port_num == 0 ||
1546                     attr->alt_port_num > dev->dev->caps.num_ports)
1547                         goto out;
1548
1549                 if (attr->alt_pkey_index >=
1550                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1551                         goto out;
1552
1553                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1554                                       &context->alt_path,
1555                                       attr->alt_port_num))
1556                         goto out;
1557
1558                 context->alt_path.pkey_index = attr->alt_pkey_index;
1559                 context->alt_path.ackto = attr->alt_timeout << 3;
1560                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1561         }
1562
1563         pd = get_pd(qp);
1564         get_cqs(qp, &send_cq, &recv_cq);
1565         context->pd       = cpu_to_be32(pd->pdn);
1566         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1567         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1568         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1569
1570         /* Set "fast registration enabled" for all kernel QPs */
1571         if (!qp->ibqp.uobject)
1572                 context->params1 |= cpu_to_be32(1 << 11);
1573
1574         if (attr_mask & IB_QP_RNR_RETRY) {
1575                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1576                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1577         }
1578
1579         if (attr_mask & IB_QP_RETRY_CNT) {
1580                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1581                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1582         }
1583
1584         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1585                 if (attr->max_rd_atomic)
1586                         context->params1 |=
1587                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1588                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1589         }
1590
1591         if (attr_mask & IB_QP_SQ_PSN)
1592                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1593
1594         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1595                 if (attr->max_dest_rd_atomic)
1596                         context->params2 |=
1597                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1598                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1599         }
1600
1601         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1602                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1603                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1604         }
1605
1606         if (ibqp->srq)
1607                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1608
1609         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1610                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1611                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1612         }
1613         if (attr_mask & IB_QP_RQ_PSN)
1614                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1615
1616         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1617         if (attr_mask & IB_QP_QKEY) {
1618                 if (qp->mlx4_ib_qp_type &
1619                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1620                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1621                 else {
1622                         if (mlx4_is_mfunc(dev->dev) &&
1623                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1624                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1625                             MLX4_RESERVED_QKEY_BASE) {
1626                                 pr_err("Cannot use reserved QKEY"
1627                                        " 0x%x (range 0xffff0000..0xffffffff"
1628                                        " is reserved)\n", attr->qkey);
1629                                 err = -EINVAL;
1630                                 goto out;
1631                         }
1632                         context->qkey = cpu_to_be32(attr->qkey);
1633                 }
1634                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1635         }
1636
1637         if (ibqp->srq)
1638                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1639
1640         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1641                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1642
1643         if (cur_state == IB_QPS_INIT &&
1644             new_state == IB_QPS_RTR  &&
1645             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1646              ibqp->qp_type == IB_QPT_UD ||
1647              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1648                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1649                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1650                     qp->mlx4_ib_qp_type &
1651                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1652                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1653                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1654                                 context->pri_path.fl = 0x80;
1655                 } else {
1656                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1657                                 context->pri_path.fl = 0x80;
1658                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1659                 }
1660                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1661                     IB_LINK_LAYER_ETHERNET) {
1662                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1663                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1664                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1665                         /* handle smac_index */
1666                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1667                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1668                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1669                                 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1670                                 if (err)
1671                                         return -EINVAL;
1672                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1673                                         dev->qp1_proxy[qp->port - 1] = qp;
1674                         }
1675                 }
1676         }
1677
1678         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
1679                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1680                                         MLX4_IB_LINK_TYPE_ETH;
1681
1682         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1683                 int is_eth = rdma_port_get_link_layer(
1684                                 &dev->ib_dev, qp->port) ==
1685                                 IB_LINK_LAYER_ETHERNET;
1686                 if (is_eth) {
1687                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1688                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1689                 }
1690         }
1691
1692
1693         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1694             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1695                 sqd_event = 1;
1696         else
1697                 sqd_event = 0;
1698
1699         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1700                 context->rlkey |= (1 << 4);
1701
1702         /*
1703          * Before passing a kernel QP to the HW, make sure that the
1704          * ownership bits of the send queue are set and the SQ
1705          * headroom is stamped so that the hardware doesn't start
1706          * processing stale work requests.
1707          */
1708         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1709                 struct mlx4_wqe_ctrl_seg *ctrl;
1710                 int i;
1711
1712                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1713                         ctrl = get_send_wqe(qp, i);
1714                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1715                         if (qp->sq_max_wqes_per_wr == 1)
1716                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1717
1718                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1719                 }
1720         }
1721
1722         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1723                              to_mlx4_state(new_state), context, optpar,
1724                              sqd_event, &qp->mqp);
1725         if (err)
1726                 goto out;
1727
1728         qp->state = new_state;
1729
1730         if (attr_mask & IB_QP_ACCESS_FLAGS)
1731                 qp->atomic_rd_en = attr->qp_access_flags;
1732         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1733                 qp->resp_depth = attr->max_dest_rd_atomic;
1734         if (attr_mask & IB_QP_PORT) {
1735                 qp->port = attr->port_num;
1736                 update_mcg_macs(dev, qp);
1737         }
1738         if (attr_mask & IB_QP_ALT_PATH)
1739                 qp->alt_port = attr->alt_port_num;
1740
1741         if (is_sqp(dev, qp))
1742                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1743
1744         /*
1745          * If we moved QP0 to RTR, bring the IB link up; if we moved
1746          * QP0 to RESET or ERROR, bring the link back down.
1747          */
1748         if (is_qp0(dev, qp)) {
1749                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1750                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1751                                 pr_warn("INIT_PORT failed for port %d\n",
1752                                        qp->port);
1753
1754                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1755                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1756                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1757         }
1758
1759         /*
1760          * If we moved a kernel QP to RESET, clean up all old CQ
1761          * entries and reinitialize the QP.
1762          */
1763         if (new_state == IB_QPS_RESET) {
1764                 if (!ibqp->uobject) {
1765                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1766                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1767                         if (send_cq != recv_cq)
1768                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1769
1770                         qp->rq.head = 0;
1771                         qp->rq.tail = 0;
1772                         qp->sq.head = 0;
1773                         qp->sq.tail = 0;
1774                         qp->sq_next_wqe = 0;
1775                         if (qp->rq.wqe_cnt)
1776                                 *qp->db.db  = 0;
1777
1778                         if (qp->flags & MLX4_IB_QP_NETIF)
1779                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1780                 }
1781                 if (qp->pri.smac) {
1782                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1783                         qp->pri.smac = 0;
1784                 }
1785                 if (qp->alt.smac) {
1786                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1787                         qp->alt.smac = 0;
1788                 }
1789                 if (qp->pri.vid < 0x1000) {
1790                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1791                         qp->pri.vid = 0xFFFF;
1792                         qp->pri.candidate_vid = 0xFFFF;
1793                         qp->pri.update_vid = 0;
1794                 }
1795
1796                 if (qp->alt.vid < 0x1000) {
1797                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1798                         qp->alt.vid = 0xFFFF;
1799                         qp->alt.candidate_vid = 0xFFFF;
1800                         qp->alt.update_vid = 0;
1801                 }
1802         }
1803 out:
1804         if (err && steer_qp)
1805                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1806         kfree(context);
1807         if (qp->pri.candidate_smac) {
1808                 if (err) {
1809                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1810                 } else {
1811                         if (qp->pri.smac)
1812                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1813                         qp->pri.smac = qp->pri.candidate_smac;
1814                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1815                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1816                 }
1817                 qp->pri.candidate_smac = 0;
1818                 qp->pri.candidate_smac_index = 0;
1819                 qp->pri.candidate_smac_port = 0;
1820         }
1821         if (qp->alt.candidate_smac) {
1822                 if (err) {
1823                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1824                 } else {
1825                         if (qp->alt.smac)
1826                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1827                         qp->alt.smac = qp->alt.candidate_smac;
1828                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1829                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1830                 }
1831                 qp->alt.candidate_smac = 0;
1832                 qp->alt.candidate_smac_index = 0;
1833                 qp->alt.candidate_smac_port = 0;
1834         }
1835
1836         if (qp->pri.update_vid) {
1837                 if (err) {
1838                         if (qp->pri.candidate_vid < 0x1000)
1839                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1840                                                      qp->pri.candidate_vid);
1841                 } else {
1842                         if (qp->pri.vid < 0x1000)
1843                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1844                                                      qp->pri.vid);
1845                         qp->pri.vid = qp->pri.candidate_vid;
1846                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1847                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1848                 }
1849                 qp->pri.candidate_vid = 0xFFFF;
1850                 qp->pri.update_vid = 0;
1851         }
1852
1853         if (qp->alt.update_vid) {
1854                 if (err) {
1855                         if (qp->alt.candidate_vid < 0x1000)
1856                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1857                                                      qp->alt.candidate_vid);
1858                 } else {
1859                         if (qp->alt.vid < 0x1000)
1860                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1861                                                      qp->alt.vid);
1862                         qp->alt.vid = qp->alt.candidate_vid;
1863                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1864                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1865                 }
1866                 qp->alt.candidate_vid = 0xFFFF;
1867                 qp->alt.update_vid = 0;
1868         }
1869
1870         return err;
1871 }
1872
1873 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1874                       int attr_mask, struct ib_udata *udata)
1875 {
1876         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1877         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1878         enum ib_qp_state cur_state, new_state;
1879         int err = -EINVAL;
1880         int ll;
1881         mutex_lock(&qp->mutex);
1882
1883         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1884         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1885
1886         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1887                 ll = IB_LINK_LAYER_UNSPECIFIED;
1888         } else {
1889                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1890                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1891         }
1892
1893         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1894                                 attr_mask, ll)) {
1895                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1896                          "for transition %d to %d. qp_type %d,"
1897                          " attr_mask 0x%x\n",
1898                          ibqp->qp_num, cur_state, new_state,
1899                          ibqp->qp_type, attr_mask);
1900                 goto out;
1901         }
1902
1903         if ((attr_mask & IB_QP_PORT) &&
1904             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1905                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1906                          "for transition %d to %d. qp_type %d\n",
1907                          ibqp->qp_num, attr->port_num, cur_state,
1908                          new_state, ibqp->qp_type);
1909                 goto out;
1910         }
1911
1912         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1913             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1914              IB_LINK_LAYER_ETHERNET))
1915                 goto out;
1916
1917         if (attr_mask & IB_QP_PKEY_INDEX) {
1918                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1919                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1920                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1921                                  "for transition %d to %d. qp_type %d\n",
1922                                  ibqp->qp_num, attr->pkey_index, cur_state,
1923                                  new_state, ibqp->qp_type);
1924                         goto out;
1925                 }
1926         }
1927
1928         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1929             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1930                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1931                          "Transition %d to %d. qp_type %d\n",
1932                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1933                          new_state, ibqp->qp_type);
1934                 goto out;
1935         }
1936
1937         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1938             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1939                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1940                          "Transition %d to %d. qp_type %d\n",
1941                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1942                          new_state, ibqp->qp_type);
1943                 goto out;
1944         }
1945
1946         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1947                 err = 0;
1948                 goto out;
1949         }
1950
1951         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1952
1953 out:
1954         mutex_unlock(&qp->mutex);
1955         return err;
1956 }
1957
1958 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
1959 {
1960         int i;
1961         for (i = 0; i < dev->caps.num_ports; i++) {
1962                 if (qpn == dev->caps.qp0_proxy[i] ||
1963                     qpn == dev->caps.qp0_tunnel[i]) {
1964                         *qkey = dev->caps.qp0_qkey[i];
1965                         return 0;
1966                 }
1967         }
1968         return -EINVAL;
1969 }
1970
1971 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1972                                   struct ib_send_wr *wr,
1973                                   void *wqe, unsigned *mlx_seg_len)
1974 {
1975         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1976         struct ib_device *ib_dev = &mdev->ib_dev;
1977         struct mlx4_wqe_mlx_seg *mlx = wqe;
1978         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1979         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1980         u16 pkey;
1981         u32 qkey;
1982         int send_size;
1983         int header_size;
1984         int spc;
1985         int i;
1986
1987         if (wr->opcode != IB_WR_SEND)
1988                 return -EINVAL;
1989
1990         send_size = 0;
1991
1992         for (i = 0; i < wr->num_sge; ++i)
1993                 send_size += wr->sg_list[i].length;
1994
1995         /* for proxy-qp0 sends, need to add in size of tunnel header */
1996         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1997         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1998                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1999
2000         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2001
2002         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2003                 sqp->ud_header.lrh.service_level =
2004                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2005                 sqp->ud_header.lrh.destination_lid =
2006                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2007                 sqp->ud_header.lrh.source_lid =
2008                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2009         }
2010
2011         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2012
2013         /* force loopback */
2014         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2015         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2016
2017         sqp->ud_header.lrh.virtual_lane    = 0;
2018         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2019         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2020         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2021         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2022                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2023         else
2024                 sqp->ud_header.bth.destination_qpn =
2025                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2026
2027         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2028         if (mlx4_is_master(mdev->dev)) {
2029                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2030                         return -EINVAL;
2031         } else {
2032                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2033                         return -EINVAL;
2034         }
2035         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2036         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2037
2038         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2039         sqp->ud_header.immediate_present = 0;
2040
2041         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2042
2043         /*
2044          * Inline data segments may not cross a 64 byte boundary.  If
2045          * our UD header is bigger than the space available up to the
2046          * next 64 byte boundary in the WQE, use two inline data
2047          * segments to hold the UD header.
2048          */
2049         spc = MLX4_INLINE_ALIGN -
2050               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2051         if (header_size <= spc) {
2052                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2053                 memcpy(inl + 1, sqp->header_buf, header_size);
2054                 i = 1;
2055         } else {
2056                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2057                 memcpy(inl + 1, sqp->header_buf, spc);
2058
2059                 inl = (void *) (inl + 1) + spc;
2060                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2061                 /*
2062                  * Need a barrier here to make sure all the data is
2063                  * visible before the byte_count field is set.
2064                  * Otherwise the HCA prefetcher could grab the 64-byte
2065                  * chunk with this inline segment and get a valid (!=
2066                  * 0xffffffff) byte count but stale data, and end up
2067                  * generating a packet with bad headers.
2068                  *
2069                  * The first inline segment's byte_count field doesn't
2070                  * need a barrier, because it comes after a
2071                  * control/MLX segment and therefore is at an offset
2072                  * of 16 mod 64.
2073                  */
2074                 wmb();
2075                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2076                 i = 2;
2077         }
2078
2079         *mlx_seg_len =
2080         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2081         return 0;
2082 }
2083
2084 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2085 {
2086         int i;
2087
2088         for (i = ETH_ALEN; i; i--) {
2089                 dst_mac[i - 1] = src_mac & 0xff;
2090                 src_mac >>= 8;
2091         }
2092 }
2093
2094 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2095                             void *wqe, unsigned *mlx_seg_len)
2096 {
2097         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2098         struct mlx4_wqe_mlx_seg *mlx = wqe;
2099         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2100         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2101         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2102         union ib_gid sgid;
2103         u16 pkey;
2104         int send_size;
2105         int header_size;
2106         int spc;
2107         int i;
2108         int err = 0;
2109         u16 vlan = 0xffff;
2110         bool is_eth;
2111         bool is_vlan = false;
2112         bool is_grh;
2113
2114         send_size = 0;
2115         for (i = 0; i < wr->num_sge; ++i)
2116                 send_size += wr->sg_list[i].length;
2117
2118         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2119         is_grh = mlx4_ib_ah_grh_present(ah);
2120         if (is_eth) {
2121                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2122                         /* When multi-function is enabled, the ib_core gid
2123                          * indexes don't necessarily match the hw ones, so
2124                          * we must use our own cache */
2125                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2126                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2127                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2128                         if (err)
2129                                 return err;
2130                 } else  {
2131                         err = ib_get_cached_gid(ib_dev,
2132                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2133                                                 ah->av.ib.gid_index, &sgid);
2134                         if (err)
2135                                 return err;
2136                 }
2137
2138                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2139                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2140                         is_vlan = 1;
2141                 }
2142         }
2143         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2144
2145         if (!is_eth) {
2146                 sqp->ud_header.lrh.service_level =
2147                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2148                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2149                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2150         }
2151
2152         if (is_grh) {
2153                 sqp->ud_header.grh.traffic_class =
2154                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2155                 sqp->ud_header.grh.flow_label    =
2156                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2157                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2158                 if (is_eth)
2159                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2160                 else {
2161                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2162                         /* When multi-function is enabled, the ib_core gid
2163                          * indexes don't necessarily match the hw ones, so
2164                          * we must use our own cache */
2165                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2166                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2167                                                        subnet_prefix;
2168                         sqp->ud_header.grh.source_gid.global.interface_id =
2169                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2170                                                guid_cache[ah->av.ib.gid_index];
2171                 } else
2172                         ib_get_cached_gid(ib_dev,
2173                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2174                                           ah->av.ib.gid_index,
2175                                           &sqp->ud_header.grh.source_gid);
2176                 }
2177                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2178                        ah->av.ib.dgid, 16);
2179         }
2180
2181         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2182
2183         if (!is_eth) {
2184                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2185                                           (sqp->ud_header.lrh.destination_lid ==
2186                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2187                                           (sqp->ud_header.lrh.service_level << 8));
2188                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2189                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2190                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2191         }
2192
2193         switch (wr->opcode) {
2194         case IB_WR_SEND:
2195                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2196                 sqp->ud_header.immediate_present = 0;
2197                 break;
2198         case IB_WR_SEND_WITH_IMM:
2199                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2200                 sqp->ud_header.immediate_present = 1;
2201                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
2202                 break;
2203         default:
2204                 return -EINVAL;
2205         }
2206
2207         if (is_eth) {
2208                 struct in6_addr in6;
2209
2210                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2211
2212                 mlx->sched_prio = cpu_to_be16(pcp);
2213
2214                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2215                 /* FIXME: cache smac value? */
2216                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2217                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2218                 memcpy(&in6, sgid.raw, sizeof(in6));
2219
2220                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2221                         u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2222                         u8 smac[ETH_ALEN];
2223
2224                         mlx4_u64_to_smac(smac, mac);
2225                         memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2226                 } else {
2227                         /* use the src mac of the tunnel */
2228                         memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2229                 }
2230
2231                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2232                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2233                 if (!is_vlan) {
2234                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2235                 } else {
2236                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2237                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2238                 }
2239         } else {
2240                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2241                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2242                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2243         }
2244         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2245         if (!sqp->qp.ibqp.qp_num)
2246                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2247         else
2248                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2249         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2250         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2251         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2252         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2253                                                sqp->qkey : wr->wr.ud.remote_qkey);
2254         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2255
2256         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2257
2258         if (0) {
2259                 pr_err("built UD header of size %d:\n", header_size);
2260                 for (i = 0; i < header_size / 4; ++i) {
2261                         if (i % 8 == 0)
2262                                 pr_err("  [%02x] ", i * 4);
2263                         pr_cont(" %08x",
2264                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2265                         if ((i + 1) % 8 == 0)
2266                                 pr_cont("\n");
2267                 }
2268                 pr_err("\n");
2269         }
2270
2271         /*
2272          * Inline data segments may not cross a 64 byte boundary.  If
2273          * our UD header is bigger than the space available up to the
2274          * next 64 byte boundary in the WQE, use two inline data
2275          * segments to hold the UD header.
2276          */
2277         spc = MLX4_INLINE_ALIGN -
2278                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2279         if (header_size <= spc) {
2280                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2281                 memcpy(inl + 1, sqp->header_buf, header_size);
2282                 i = 1;
2283         } else {
2284                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2285                 memcpy(inl + 1, sqp->header_buf, spc);
2286
2287                 inl = (void *) (inl + 1) + spc;
2288                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2289                 /*
2290                  * Need a barrier here to make sure all the data is
2291                  * visible before the byte_count field is set.
2292                  * Otherwise the HCA prefetcher could grab the 64-byte
2293                  * chunk with this inline segment and get a valid (!=
2294                  * 0xffffffff) byte count but stale data, and end up
2295                  * generating a packet with bad headers.
2296                  *
2297                  * The first inline segment's byte_count field doesn't
2298                  * need a barrier, because it comes after a
2299                  * control/MLX segment and therefore is at an offset
2300                  * of 16 mod 64.
2301                  */
2302                 wmb();
2303                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2304                 i = 2;
2305         }
2306
2307         *mlx_seg_len =
2308                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2309         return 0;
2310 }
2311
2312 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2313 {
2314         unsigned cur;
2315         struct mlx4_ib_cq *cq;
2316
2317         cur = wq->head - wq->tail;
2318         if (likely(cur + nreq < wq->max_post))
2319                 return 0;
2320
2321         cq = to_mcq(ib_cq);
2322         spin_lock(&cq->lock);
2323         cur = wq->head - wq->tail;
2324         spin_unlock(&cq->lock);
2325
2326         return cur + nreq >= wq->max_post;
2327 }
2328
2329 static __be32 convert_access(int acc)
2330 {
2331         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2332                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2333                (acc & IB_ACCESS_REMOTE_WRITE  ?
2334                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2335                (acc & IB_ACCESS_REMOTE_READ   ?
2336                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2337                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2338                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2339 }
2340
2341 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2342 {
2343         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2344         int i;
2345
2346         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2347                 mfrpl->mapped_page_list[i] =
2348                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2349                                     MLX4_MTT_FLAG_PRESENT);
2350
2351         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2352         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2353         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2354         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2355         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2356         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2357         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2358         fseg->reserved[0]       = 0;
2359         fseg->reserved[1]       = 0;
2360 }
2361
2362 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2363 {
2364         bseg->flags1 =
2365                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2366                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2367                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2368                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2369         bseg->flags2 = 0;
2370         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2371                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2372         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2373                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2374         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2375         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2376         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2377         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2378 }
2379
2380 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2381 {
2382         memset(iseg, 0, sizeof(*iseg));
2383         iseg->mem_key = cpu_to_be32(rkey);
2384 }
2385
2386 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2387                                           u64 remote_addr, u32 rkey)
2388 {
2389         rseg->raddr    = cpu_to_be64(remote_addr);
2390         rseg->rkey     = cpu_to_be32(rkey);
2391         rseg->reserved = 0;
2392 }
2393
2394 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2395 {
2396         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2397                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2398                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2399         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2400                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2401                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2402         } else {
2403                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2404                 aseg->compare  = 0;
2405         }
2406
2407 }
2408
2409 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2410                                   struct ib_send_wr *wr)
2411 {
2412         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2413         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2414         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2415         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2416 }
2417
2418 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2419                              struct ib_send_wr *wr)
2420 {
2421         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2422         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2423         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2424         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2425         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2426 }
2427
2428 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2429                                     struct mlx4_wqe_datagram_seg *dseg,
2430                                     struct ib_send_wr *wr,
2431                                     enum mlx4_ib_qp_type qpt)
2432 {
2433         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2434         struct mlx4_av sqp_av = {0};
2435         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2436
2437         /* force loopback */
2438         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2439         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2440         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2441                         cpu_to_be32(0xf0000000);
2442
2443         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2444         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2445                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2446         else
2447                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2448         /* Use QKEY from the QP context, which is set by master */
2449         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2450 }
2451
2452 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2453 {
2454         struct mlx4_wqe_inline_seg *inl = wqe;
2455         struct mlx4_ib_tunnel_header hdr;
2456         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2457         int spc;
2458         int i;
2459
2460         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2461         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2462         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2463         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2464         memcpy(hdr.mac, ah->av.eth.mac, 6);
2465         hdr.vlan = ah->av.eth.vlan;
2466
2467         spc = MLX4_INLINE_ALIGN -
2468                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2469         if (sizeof (hdr) <= spc) {
2470                 memcpy(inl + 1, &hdr, sizeof (hdr));
2471                 wmb();
2472                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2473                 i = 1;
2474         } else {
2475                 memcpy(inl + 1, &hdr, spc);
2476                 wmb();
2477                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2478
2479                 inl = (void *) (inl + 1) + spc;
2480                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2481                 wmb();
2482                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2483                 i = 2;
2484         }
2485
2486         *mlx_seg_len =
2487                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2488 }
2489
2490 static void set_mlx_icrc_seg(void *dseg)
2491 {
2492         u32 *t = dseg;
2493         struct mlx4_wqe_inline_seg *iseg = dseg;
2494
2495         t[1] = 0;
2496
2497         /*
2498          * Need a barrier here before writing the byte_count field to
2499          * make sure that all the data is visible before the
2500          * byte_count field is set.  Otherwise, if the segment begins
2501          * a new cacheline, the HCA prefetcher could grab the 64-byte
2502          * chunk and get a valid (!= * 0xffffffff) byte count but
2503          * stale data, and end up sending the wrong data.
2504          */
2505         wmb();
2506
2507         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2508 }
2509
2510 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2511 {
2512         dseg->lkey       = cpu_to_be32(sg->lkey);
2513         dseg->addr       = cpu_to_be64(sg->addr);
2514
2515         /*
2516          * Need a barrier here before writing the byte_count field to
2517          * make sure that all the data is visible before the
2518          * byte_count field is set.  Otherwise, if the segment begins
2519          * a new cacheline, the HCA prefetcher could grab the 64-byte
2520          * chunk and get a valid (!= * 0xffffffff) byte count but
2521          * stale data, and end up sending the wrong data.
2522          */
2523         wmb();
2524
2525         dseg->byte_count = cpu_to_be32(sg->length);
2526 }
2527
2528 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2529 {
2530         dseg->byte_count = cpu_to_be32(sg->length);
2531         dseg->lkey       = cpu_to_be32(sg->lkey);
2532         dseg->addr       = cpu_to_be64(sg->addr);
2533 }
2534
2535 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2536                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2537                          __be32 *lso_hdr_sz, __be32 *blh)
2538 {
2539         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2540
2541         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2542                 *blh = cpu_to_be32(1 << 6);
2543
2544         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2545                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2546                 return -EINVAL;
2547
2548         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2549
2550         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2551                                    wr->wr.ud.hlen);
2552         *lso_seg_len = halign;
2553         return 0;
2554 }
2555
2556 static __be32 send_ieth(struct ib_send_wr *wr)
2557 {
2558         switch (wr->opcode) {
2559         case IB_WR_SEND_WITH_IMM:
2560         case IB_WR_RDMA_WRITE_WITH_IMM:
2561                 return wr->ex.imm_data;
2562
2563         case IB_WR_SEND_WITH_INV:
2564                 return cpu_to_be32(wr->ex.invalidate_rkey);
2565
2566         default:
2567                 return 0;
2568         }
2569 }
2570
2571 static void add_zero_len_inline(void *wqe)
2572 {
2573         struct mlx4_wqe_inline_seg *inl = wqe;
2574         memset(wqe, 0, 16);
2575         inl->byte_count = cpu_to_be32(1 << 31);
2576 }
2577
2578 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2579                       struct ib_send_wr **bad_wr)
2580 {
2581         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2582         void *wqe;
2583         struct mlx4_wqe_ctrl_seg *ctrl;
2584         struct mlx4_wqe_data_seg *dseg;
2585         unsigned long flags;
2586         int nreq;
2587         int err = 0;
2588         unsigned ind;
2589         int uninitialized_var(stamp);
2590         int uninitialized_var(size);
2591         unsigned uninitialized_var(seglen);
2592         __be32 dummy;
2593         __be32 *lso_wqe;
2594         __be32 uninitialized_var(lso_hdr_sz);
2595         __be32 blh;
2596         int i;
2597
2598         spin_lock_irqsave(&qp->sq.lock, flags);
2599
2600         ind = qp->sq_next_wqe;
2601
2602         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2603                 lso_wqe = &dummy;
2604                 blh = 0;
2605
2606                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2607                         err = -ENOMEM;
2608                         *bad_wr = wr;
2609                         goto out;
2610                 }
2611
2612                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2613                         err = -EINVAL;
2614                         *bad_wr = wr;
2615                         goto out;
2616                 }
2617
2618                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2619                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2620
2621                 ctrl->srcrb_flags =
2622                         (wr->send_flags & IB_SEND_SIGNALED ?
2623                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2624                         (wr->send_flags & IB_SEND_SOLICITED ?
2625                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2626                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2627                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2628                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2629                         qp->sq_signal_bits;
2630
2631                 ctrl->imm = send_ieth(wr);
2632
2633                 wqe += sizeof *ctrl;
2634                 size = sizeof *ctrl / 16;
2635
2636                 switch (qp->mlx4_ib_qp_type) {
2637                 case MLX4_IB_QPT_RC:
2638                 case MLX4_IB_QPT_UC:
2639                         switch (wr->opcode) {
2640                         case IB_WR_ATOMIC_CMP_AND_SWP:
2641                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2642                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2643                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2644                                               wr->wr.atomic.rkey);
2645                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2646
2647                                 set_atomic_seg(wqe, wr);
2648                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2649
2650                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2651                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2652
2653                                 break;
2654
2655                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2656                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2657                                               wr->wr.atomic.rkey);
2658                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2659
2660                                 set_masked_atomic_seg(wqe, wr);
2661                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2662
2663                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2664                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2665
2666                                 break;
2667
2668                         case IB_WR_RDMA_READ:
2669                         case IB_WR_RDMA_WRITE:
2670                         case IB_WR_RDMA_WRITE_WITH_IMM:
2671                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2672                                               wr->wr.rdma.rkey);
2673                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2674                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2675                                 break;
2676
2677                         case IB_WR_LOCAL_INV:
2678                                 ctrl->srcrb_flags |=
2679                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2680                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2681                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2682                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2683                                 break;
2684
2685                         case IB_WR_FAST_REG_MR:
2686                                 ctrl->srcrb_flags |=
2687                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2688                                 set_fmr_seg(wqe, wr);
2689                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2690                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2691                                 break;
2692
2693                         case IB_WR_BIND_MW:
2694                                 ctrl->srcrb_flags |=
2695                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2696                                 set_bind_seg(wqe, wr);
2697                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2698                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2699                                 break;
2700                         default:
2701                                 /* No extra segments required for sends */
2702                                 break;
2703                         }
2704                         break;
2705
2706                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2707                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2708                         if (unlikely(err)) {
2709                                 *bad_wr = wr;
2710                                 goto out;
2711                         }
2712                         wqe  += seglen;
2713                         size += seglen / 16;
2714                         break;
2715                 case MLX4_IB_QPT_TUN_SMI:
2716                 case MLX4_IB_QPT_TUN_GSI:
2717                         /* this is a UD qp used in MAD responses to slaves. */
2718                         set_datagram_seg(wqe, wr);
2719                         /* set the forced-loopback bit in the data seg av */
2720                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2721                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2722                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2723                         break;
2724                 case MLX4_IB_QPT_UD:
2725                         set_datagram_seg(wqe, wr);
2726                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2727                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2728
2729                         if (wr->opcode == IB_WR_LSO) {
2730                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2731                                 if (unlikely(err)) {
2732                                         *bad_wr = wr;
2733                                         goto out;
2734                                 }
2735                                 lso_wqe = (__be32 *) wqe;
2736                                 wqe  += seglen;
2737                                 size += seglen / 16;
2738                         }
2739                         break;
2740
2741                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2742                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2743                         if (unlikely(err)) {
2744                                 *bad_wr = wr;
2745                                 goto out;
2746                         }
2747                         wqe  += seglen;
2748                         size += seglen / 16;
2749                         /* to start tunnel header on a cache-line boundary */
2750                         add_zero_len_inline(wqe);
2751                         wqe += 16;
2752                         size++;
2753                         build_tunnel_header(wr, wqe, &seglen);
2754                         wqe  += seglen;
2755                         size += seglen / 16;
2756                         break;
2757                 case MLX4_IB_QPT_PROXY_SMI:
2758                 case MLX4_IB_QPT_PROXY_GSI:
2759                         /* If we are tunneling special qps, this is a UD qp.
2760                          * In this case we first add a UD segment targeting
2761                          * the tunnel qp, and then add a header with address
2762                          * information */
2763                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2764                                                 qp->mlx4_ib_qp_type);
2765                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2766                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2767                         build_tunnel_header(wr, wqe, &seglen);
2768                         wqe  += seglen;
2769                         size += seglen / 16;
2770                         break;
2771
2772                 case MLX4_IB_QPT_SMI:
2773                 case MLX4_IB_QPT_GSI:
2774                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2775                         if (unlikely(err)) {
2776                                 *bad_wr = wr;
2777                                 goto out;
2778                         }
2779                         wqe  += seglen;
2780                         size += seglen / 16;
2781                         break;
2782
2783                 default:
2784                         break;
2785                 }
2786
2787                 /*
2788                  * Write data segments in reverse order, so as to
2789                  * overwrite cacheline stamp last within each
2790                  * cacheline.  This avoids issues with WQE
2791                  * prefetching.
2792                  */
2793
2794                 dseg = wqe;
2795                 dseg += wr->num_sge - 1;
2796                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2797
2798                 /* Add one more inline data segment for ICRC for MLX sends */
2799                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2800                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2801                              qp->mlx4_ib_qp_type &
2802                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2803                         set_mlx_icrc_seg(dseg + 1);
2804                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2805                 }
2806
2807                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2808                         set_data_seg(dseg, wr->sg_list + i);
2809
2810                 /*
2811                  * Possibly overwrite stamping in cacheline with LSO
2812                  * segment only after making sure all data segments
2813                  * are written.
2814                  */
2815                 wmb();
2816                 *lso_wqe = lso_hdr_sz;
2817
2818                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2819                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2820
2821                 /*
2822                  * Make sure descriptor is fully written before
2823                  * setting ownership bit (because HW can start
2824                  * executing as soon as we do).
2825                  */
2826                 wmb();
2827
2828                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2829                         *bad_wr = wr;
2830                         err = -EINVAL;
2831                         goto out;
2832                 }
2833
2834                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2835                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2836
2837                 stamp = ind + qp->sq_spare_wqes;
2838                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2839
2840                 /*
2841                  * We can improve latency by not stamping the last
2842                  * send queue WQE until after ringing the doorbell, so
2843                  * only stamp here if there are still more WQEs to post.
2844                  *
2845                  * Same optimization applies to padding with NOP wqe
2846                  * in case of WQE shrinking (used to prevent wrap-around
2847                  * in the middle of WR).
2848                  */
2849                 if (wr->next) {
2850                         stamp_send_wqe(qp, stamp, size * 16);
2851                         ind = pad_wraparound(qp, ind);
2852                 }
2853         }
2854
2855 out:
2856         if (likely(nreq)) {
2857                 qp->sq.head += nreq;
2858
2859                 /*
2860                  * Make sure that descriptors are written before
2861                  * doorbell record.
2862                  */
2863                 wmb();
2864
2865                 writel(qp->doorbell_qpn,
2866                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2867
2868                 /*
2869                  * Make sure doorbells don't leak out of SQ spinlock
2870                  * and reach the HCA out of order.
2871                  */
2872                 mmiowb();
2873
2874                 stamp_send_wqe(qp, stamp, size * 16);
2875
2876                 ind = pad_wraparound(qp, ind);
2877                 qp->sq_next_wqe = ind;
2878         }
2879
2880         spin_unlock_irqrestore(&qp->sq.lock, flags);
2881
2882         return err;
2883 }
2884
2885 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2886                       struct ib_recv_wr **bad_wr)
2887 {
2888         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2889         struct mlx4_wqe_data_seg *scat;
2890         unsigned long flags;
2891         int err = 0;
2892         int nreq;
2893         int ind;
2894         int max_gs;
2895         int i;
2896
2897         max_gs = qp->rq.max_gs;
2898         spin_lock_irqsave(&qp->rq.lock, flags);
2899
2900         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2901
2902         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2903                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2904                         err = -ENOMEM;
2905                         *bad_wr = wr;
2906                         goto out;
2907                 }
2908
2909                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2910                         err = -EINVAL;
2911                         *bad_wr = wr;
2912                         goto out;
2913                 }
2914
2915                 scat = get_recv_wqe(qp, ind);
2916
2917                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2918                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2919                         ib_dma_sync_single_for_device(ibqp->device,
2920                                                       qp->sqp_proxy_rcv[ind].map,
2921                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2922                                                       DMA_FROM_DEVICE);
2923                         scat->byte_count =
2924                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2925                         /* use dma lkey from upper layer entry */
2926                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2927                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2928                         scat++;
2929                         max_gs--;
2930                 }
2931
2932                 for (i = 0; i < wr->num_sge; ++i)
2933                         __set_data_seg(scat + i, wr->sg_list + i);
2934
2935                 if (i < max_gs) {
2936                         scat[i].byte_count = 0;
2937                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2938                         scat[i].addr       = 0;
2939                 }
2940
2941                 qp->rq.wrid[ind] = wr->wr_id;
2942
2943                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2944         }
2945
2946 out:
2947         if (likely(nreq)) {
2948                 qp->rq.head += nreq;
2949
2950                 /*
2951                  * Make sure that descriptors are written before
2952                  * doorbell record.
2953                  */
2954                 wmb();
2955
2956                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2957         }
2958
2959         spin_unlock_irqrestore(&qp->rq.lock, flags);
2960
2961         return err;
2962 }
2963
2964 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2965 {
2966         switch (mlx4_state) {
2967         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2968         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2969         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2970         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2971         case MLX4_QP_STATE_SQ_DRAINING:
2972         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2973         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2974         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2975         default:                     return -1;
2976         }
2977 }
2978
2979 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2980 {
2981         switch (mlx4_mig_state) {
2982         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2983         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2984         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2985         default: return -1;
2986         }
2987 }
2988
2989 static int to_ib_qp_access_flags(int mlx4_flags)
2990 {
2991         int ib_flags = 0;
2992
2993         if (mlx4_flags & MLX4_QP_BIT_RRE)
2994                 ib_flags |= IB_ACCESS_REMOTE_READ;
2995         if (mlx4_flags & MLX4_QP_BIT_RWE)
2996                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2997         if (mlx4_flags & MLX4_QP_BIT_RAE)
2998                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2999
3000         return ib_flags;
3001 }
3002
3003 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3004                                 struct mlx4_qp_path *path)
3005 {
3006         struct mlx4_dev *dev = ibdev->dev;
3007         int is_eth;
3008
3009         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3010         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
3011
3012         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3013                 return;
3014
3015         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3016                 IB_LINK_LAYER_ETHERNET;
3017         if (is_eth)
3018                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3019                 ((path->sched_queue & 4) << 1);
3020         else
3021                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3022
3023         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3024         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3025         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3026         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3027         if (ib_ah_attr->ah_flags) {
3028                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3029                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3030                 ib_ah_attr->grh.traffic_class =
3031                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3032                 ib_ah_attr->grh.flow_label =
3033                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3034                 memcpy(ib_ah_attr->grh.dgid.raw,
3035                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3036         }
3037 }
3038
3039 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3040                      struct ib_qp_init_attr *qp_init_attr)
3041 {
3042         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3043         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3044         struct mlx4_qp_context context;
3045         int mlx4_state;
3046         int err = 0;
3047
3048         mutex_lock(&qp->mutex);
3049
3050         if (qp->state == IB_QPS_RESET) {
3051                 qp_attr->qp_state = IB_QPS_RESET;
3052                 goto done;
3053         }
3054
3055         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3056         if (err) {
3057                 err = -EINVAL;
3058                 goto out;
3059         }
3060
3061         mlx4_state = be32_to_cpu(context.flags) >> 28;
3062
3063         qp->state                    = to_ib_qp_state(mlx4_state);
3064         qp_attr->qp_state            = qp->state;
3065         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3066         qp_attr->path_mig_state      =
3067                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3068         qp_attr->qkey                = be32_to_cpu(context.qkey);
3069         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3070         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3071         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3072         qp_attr->qp_access_flags     =
3073                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3074
3075         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3076                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3077                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3078                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3079                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3080         }
3081
3082         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3083         if (qp_attr->qp_state == IB_QPS_INIT)
3084                 qp_attr->port_num = qp->port;
3085         else
3086                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3087
3088         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3089         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3090
3091         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3092
3093         qp_attr->max_dest_rd_atomic =
3094                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3095         qp_attr->min_rnr_timer      =
3096                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3097         qp_attr->timeout            = context.pri_path.ackto >> 3;
3098         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3099         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3100         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3101
3102 done:
3103         qp_attr->cur_qp_state        = qp_attr->qp_state;
3104         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3105         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3106
3107         if (!ibqp->uobject) {
3108                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3109                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3110         } else {
3111                 qp_attr->cap.max_send_wr  = 0;
3112                 qp_attr->cap.max_send_sge = 0;
3113         }
3114
3115         /*
3116          * We don't support inline sends for kernel QPs (yet), and we
3117          * don't know what userspace's value should be.
3118          */
3119         qp_attr->cap.max_inline_data = 0;
3120
3121         qp_init_attr->cap            = qp_attr->cap;
3122
3123         qp_init_attr->create_flags = 0;
3124         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3125                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3126
3127         if (qp->flags & MLX4_IB_QP_LSO)
3128                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3129
3130         if (qp->flags & MLX4_IB_QP_NETIF)
3131                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3132
3133         qp_init_attr->sq_sig_type =
3134                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3135                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3136
3137 out:
3138         mutex_unlock(&qp->mutex);
3139         return err;
3140 }
3141