drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 #ifndef ETH_ALEN
  94 #define ETH_ALEN        6
  95 #endif
  96 static inline u64 mlx4_mac_to_u64(u8 *addr)
  97 {
  98         u64 mac = 0;
  99         int i;
 100
 101         for (i = 0; i < ETH_ALEN; i++) {
 102                 mac <<= 8;
 103                 mac |= addr[i];
 104         }
 105         return mac;
 106 }
 107
 108 static const __be32 mlx4_ib_opcode[] = {
 109         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 110         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 111         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 112         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 113         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 114         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 115         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 116         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 117         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 118         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 119         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 120         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 121         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 122         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 123 };
 124
 125 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 126 {
 127         return container_of(mqp, struct mlx4_ib_sqp, qp);
 128 }
 129
 130 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 131 {
 132         if (!mlx4_is_master(dev->dev))
 133                 return 0;
 134
 135         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 136                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 137                 8 * MLX4_MFUNC_MAX;
 138 }
 139
 140 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 141 {
 142         int proxy_sqp = 0;
 143         int real_sqp = 0;
 144         int i;
 145         /* PPF or Native -- real SQP */
 146         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 147                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 148                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 149         if (real_sqp)
 150                 return 1;
 151         /* VF or PF -- proxy SQP */
 152         if (mlx4_is_mfunc(dev->dev)) {
 153                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 154                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 155                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 156                                 proxy_sqp = 1;
 157                                 break;
 158                         }
 159                 }
 160         }
 161         return proxy_sqp;
 162 }
 163
 164 /* used for INIT/CLOSE port logic */
 165 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 166 {
 167         int proxy_qp0 = 0;
 168         int real_qp0 = 0;
 169         int i;
 170         /* PPF or Native -- real QP0 */
 171         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 172                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 173                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 174         if (real_qp0)
 175                 return 1;
 176         /* VF or PF -- proxy QP0 */
 177         if (mlx4_is_mfunc(dev->dev)) {
 178                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 179                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 180                                 proxy_qp0 = 1;
 181                                 break;
 182                         }
 183                 }
 184         }
 185         return proxy_qp0;
 186 }
 187
 188 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 189 {
 190         return mlx4_buf_offset(&qp->buf, offset);
 191 }
 192
 193 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 196 }
 197
 198 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 199 {
 200         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 201 }
 202
 203 /*
 204  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 205  * first four bytes of every 64 byte chunk with
 206  *     0x7FFFFFF | (invalid_ownership_value << 31).
 207  *
 208  * When the max work request size is less than or equal to the WQE
 209  * basic block size, as an optimization, we can stamp all WQEs with
 210  * 0xffffffff, and skip the very first chunk of each WQE.
 211  */
 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 213 {
 214         __be32 *wqe;
 215         int i;
 216         int s;
 217         int ind;
 218         void *buf;
 219         __be32 stamp;
 220         struct mlx4_wqe_ctrl_seg *ctrl;
 221
 222         if (qp->sq_max_wqes_per_wr > 1) {
 223                 s = roundup(size, 1U << qp->sq.wqe_shift);
 224                 for (i = 0; i < s; i += 64) {
 225                         ind = (i >> qp->sq.wqe_shift) + n;
 226                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 227                                                        cpu_to_be32(0xffffffff);
 228                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 229                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 230                         *wqe = stamp;
 231                 }
 232         } else {
 233                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 234                 s = (ctrl->fence_size & 0x3f) << 4;
 235                 for (i = 64; i < s; i += 64) {
 236                         wqe = buf + i;
 237                         *wqe = cpu_to_be32(0xffffffff);
 238                 }
 239         }
 240 }
 241
 242 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 243 {
 244         struct mlx4_wqe_ctrl_seg *ctrl;
 245         struct mlx4_wqe_inline_seg *inl;
 246         void *wqe;
 247         int s;
 248
 249         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 250         s = sizeof(struct mlx4_wqe_ctrl_seg);
 251
 252         if (qp->ibqp.qp_type == IB_QPT_UD) {
 253                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 254                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 255                 memset(dgram, 0, sizeof *dgram);
 256                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 257                 s += sizeof(struct mlx4_wqe_datagram_seg);
 258         }
 259
 260         /* Pad the remainder of the WQE with an inline data segment. */
 261         if (size > s) {
 262                 inl = wqe + s;
 263                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 264         }
 265         ctrl->srcrb_flags = 0;
 266         ctrl->fence_size = size / 16;
 267         /*
 268          * Make sure descriptor is fully written before setting ownership bit
 269          * (because HW can start executing as soon as we do).
 270          */
 271         wmb();
 272
 273         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 274                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 275
 276         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 277 }
 278
 279 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 280 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 281 {
 282         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 283         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 284                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 285                 ind += s;
 286         }
 287         return ind;
 288 }
 289
 290 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 291 {
 292         struct ib_event event;
 293         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 294
 295         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 296                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 297
 298         if (ibqp->event_handler) {
 299                 event.device     = ibqp->device;
 300                 event.element.qp = ibqp;
 301                 switch (type) {
 302                 case MLX4_EVENT_TYPE_PATH_MIG:
 303                         event.event = IB_EVENT_PATH_MIG;
 304                         break;
 305                 case MLX4_EVENT_TYPE_COMM_EST:
 306                         event.event = IB_EVENT_COMM_EST;
 307                         break;
 308                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 309                         event.event = IB_EVENT_SQ_DRAINED;
 310                         break;
 311                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 312                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 313                         break;
 314                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 315                         event.event = IB_EVENT_QP_FATAL;
 316                         break;
 317                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 318                         event.event = IB_EVENT_PATH_MIG_ERR;
 319                         break;
 320                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 321                         event.event = IB_EVENT_QP_REQ_ERR;
 322                         break;
 323                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 324                         event.event = IB_EVENT_QP_ACCESS_ERR;
 325                         break;
 326                 default:
 327                         pr_warn("Unexpected event type %d "
 328                                "on QP %06x\n", type, qp->qpn);
 329                         return;
 330                 }
 331
 332                 ibqp->event_handler(&event, ibqp->qp_context);
 333         }
 334 }
 335
 336 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 337 {
 338         /*
 339          * UD WQEs must have a datagram segment.
 340          * RC and UC WQEs might have a remote address segment.
 341          * MLX WQEs need two extra inline data segments (for the UD
 342          * header and space for the ICRC).
 343          */
 344         switch (type) {
 345         case MLX4_IB_QPT_UD:
 346                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 347                         sizeof (struct mlx4_wqe_datagram_seg) +
 348                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 349         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 350         case MLX4_IB_QPT_PROXY_SMI:
 351         case MLX4_IB_QPT_PROXY_GSI:
 352                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 353                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 354         case MLX4_IB_QPT_TUN_SMI_OWNER:
 355         case MLX4_IB_QPT_TUN_GSI:
 356                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 357                         sizeof (struct mlx4_wqe_datagram_seg);
 358
 359         case MLX4_IB_QPT_UC:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_raddr_seg);
 362         case MLX4_IB_QPT_RC:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         sizeof (struct mlx4_wqe_atomic_seg) +
 365                         sizeof (struct mlx4_wqe_raddr_seg);
 366         case MLX4_IB_QPT_SMI:
 367         case MLX4_IB_QPT_GSI:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 370                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 371                                            MLX4_INLINE_ALIGN) *
 372                               sizeof (struct mlx4_wqe_inline_seg),
 373                               sizeof (struct mlx4_wqe_data_seg)) +
 374                         ALIGN(4 +
 375                               sizeof (struct mlx4_wqe_inline_seg),
 376                               sizeof (struct mlx4_wqe_data_seg));
 377         default:
 378                 return sizeof (struct mlx4_wqe_ctrl_seg);
 379         }
 380 }
 381
 382 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 383                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 384 {
 385         /* Sanity check RQ size before proceeding */
 386         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 387             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 388                 return -EINVAL;
 389
 390         if (!has_rq) {
 391                 if (cap->max_recv_wr)
 392                         return -EINVAL;
 393
 394                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 395         } else {
 396                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 397                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 398                         return -EINVAL;
 399
 400                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 401                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 402                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 403         }
 404
 405         /* leave userspace return values as they were, so as not to break ABI */
 406         if (is_user) {
 407                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 408                 cap->max_recv_sge = qp->rq.max_gs;
 409         } else {
 410                 cap->max_recv_wr  = qp->rq.max_post =
 411                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 412                 cap->max_recv_sge = min(qp->rq.max_gs,
 413                                         min(dev->dev->caps.max_sq_sg,
 414                                             dev->dev->caps.max_rq_sg));
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 421                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 422 {
 423         int s;
 424
 425         /* Sanity check SQ size before proceeding */
 426         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 427             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 428             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 429             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 430                 return -EINVAL;
 431
 432         /*
 433          * For MLX transport we need 2 extra S/G entries:
 434          * one for the header and one for the checksum at the end
 435          */
 436         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 437              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 438             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 439                 return -EINVAL;
 440
 441         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 442                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 443                 send_wqe_overhead(type, qp->flags);
 444
 445         if (s > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * Hermon supports shrinking WQEs, such that a single work
 450          * request can include multiple units of 1 << wqe_shift.  This
 451          * way, work requests can differ in size, and do not have to
 452          * be a power of 2 in size, saving memory and speeding up send
 453          * WR posting.  Unfortunately, if we do this then the
 454          * wqe_index field in CQEs can't be used to look up the WR ID
 455          * anymore, so we do this only if selective signaling is off.
 456          *
 457          * Further, on 32-bit platforms, we can't use vmap() to make
 458          * the QP buffer virtually contiguous.  Thus we have to use
 459          * constant-sized WRs to make sure a WR is always fully within
 460          * a single page-sized chunk.
 461          *
 462          * Finally, we use NOP work requests to pad the end of the
 463          * work queue, to avoid wrap-around in the middle of WR.  We
 464          * set NEC bit to avoid getting completions with error for
 465          * these NOP WRs, but since NEC is only supported starting
 466          * with firmware 2.2.232, we use constant-sized WRs for older
 467          * firmware.
 468          *
 469          * And, since MLX QPs only support SEND, we use constant-sized
 470          * WRs in this case.
 471          *
 472          * We look for the smallest value of wqe_shift such that the
 473          * resulting number of wqes does not exceed device
 474          * capabilities.
 475          *
 476          * We set WQE size to at least 64 bytes, this way stamping
 477          * invalidates each WQE.
 478          */
 479         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 480             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 481             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 482             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 483                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 484                 qp->sq.wqe_shift = ilog2(64);
 485         else
 486                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 487
 488         for (;;) {
 489                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 490
 491                 /*
 492                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 493                  * allow HW to prefetch.
 494                  */
 495                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 496                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 497                                                     qp->sq_max_wqes_per_wr +
 498                                                     qp->sq_spare_wqes);
 499
 500                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 501                         break;
 502
 503                 if (qp->sq_max_wqes_per_wr <= 1)
 504                         return -EINVAL;
 505
 506                 ++qp->sq.wqe_shift;
 507         }
 508
 509         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 510                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 511                          send_wqe_overhead(type, qp->flags)) /
 512                 sizeof (struct mlx4_wqe_data_seg);
 513
 514         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 515                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 516         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 517                 qp->rq.offset = 0;
 518                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 519         } else {
 520                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 521                 qp->sq.offset = 0;
 522         }
 523
 524         cap->max_send_wr  = qp->sq.max_post =
 525                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 526         cap->max_send_sge = min(qp->sq.max_gs,
 527                                 min(dev->dev->caps.max_sq_sg,
 528                                     dev->dev->caps.max_rq_sg));
 529         /* We don't support inline sends for kernel QPs (yet) */
 530         cap->max_inline_data = 0;
 531
 532         return 0;
 533 }
 534
 535 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 536                             struct mlx4_ib_qp *qp,
 537                             struct mlx4_ib_create_qp *ucmd)
 538 {
 539         /* Sanity check SQ size before proceeding */
 540         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 541             ucmd->log_sq_stride >
 542                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 543             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 544                 return -EINVAL;
 545
 546         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 547         qp->sq.wqe_shift = ucmd->log_sq_stride;
 548
 549         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 550                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 551
 552         return 0;
 553 }
 554
 555 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 556 {
 557         int i;
 558
 559         qp->sqp_proxy_rcv =
 560                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 561                         GFP_KERNEL);
 562         if (!qp->sqp_proxy_rcv)
 563                 return -ENOMEM;
 564         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 565                 qp->sqp_proxy_rcv[i].addr =
 566                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 567                                 GFP_KERNEL);
 568                 if (!qp->sqp_proxy_rcv[i].addr)
 569                         goto err;
 570                 qp->sqp_proxy_rcv[i].map =
 571                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 572                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 573                                           DMA_FROM_DEVICE);
 574         }
 575         return 0;
 576
 577 err:
 578         while (i > 0) {
 579                 --i;
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586         qp->sqp_proxy_rcv = NULL;
 587         return -ENOMEM;
 588 }
 589
 590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 591 {
 592         int i;
 593
 594         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 595                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 596                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 597                                     DMA_FROM_DEVICE);
 598                 kfree(qp->sqp_proxy_rcv[i].addr);
 599         }
 600         kfree(qp->sqp_proxy_rcv);
 601 }
 602
 603 static int qp_has_rq(struct ib_qp_init_attr *attr)
 604 {
 605         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 606                 return 0;
 607
 608         return !attr->srq;
 609 }
 610
 611 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 612                             struct ib_qp_init_attr *init_attr,
 613                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
 614 {
 615         int qpn;
 616         int err;
 617         struct mlx4_ib_sqp *sqp;
 618         struct mlx4_ib_qp *qp;
 619         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 620
 621         /* When tunneling special qps, we use a plain UD qp */
 622         if (sqpn) {
 623                 if (mlx4_is_mfunc(dev->dev) &&
 624                     (!mlx4_is_master(dev->dev) ||
 625                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 626                         if (init_attr->qp_type == IB_QPT_GSI)
 627                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 628                         else if (mlx4_is_master(dev->dev))
 629                                 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 630                         else
 631                                 qp_type = MLX4_IB_QPT_PROXY_SMI;
 632                 }
 633                 qpn = sqpn;
 634                 /* add extra sg entry for tunneling */
 635                 init_attr->cap.max_recv_sge++;
 636         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 637                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 638                         container_of(init_attr,
 639                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 640                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 641                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 642                     !mlx4_is_master(dev->dev))
 643                         return -EINVAL;
 644                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 645                         qp_type = MLX4_IB_QPT_TUN_GSI;
 646                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev))
 647                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 648                 else
 649                         qp_type = MLX4_IB_QPT_TUN_SMI;
 650                 /* we are definitely in the PPF here, since we are creating
 651                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 652                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 653                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 654                 sqpn = qpn;
 655         }
 656
 657         if (!*caller_qp) {
 658                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 659                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 660                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 661                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
 662                         if (!sqp)
 663                                 return -ENOMEM;
 664                         qp = &sqp->qp;
 665                         qp->pri.vid = 0xFFFF;
 666                         qp->alt.vid = 0xFFFF;
 667                 } else {
 668                         qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
 669                         if (!qp)
 670                                 return -ENOMEM;
 671                         qp->pri.vid = 0xFFFF;
 672                         qp->alt.vid = 0xFFFF;
 673                 }
 674         } else
 675                 qp = *caller_qp;
 676
 677         qp->mlx4_ib_qp_type = qp_type;
 678
 679         mutex_init(&qp->mutex);
 680         spin_lock_init(&qp->sq.lock);
 681         spin_lock_init(&qp->rq.lock);
 682         INIT_LIST_HEAD(&qp->gid_list);
 683         INIT_LIST_HEAD(&qp->steering_rules);
 684
 685         qp->state        = IB_QPS_RESET;
 686         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 687                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 688
 689         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 690         if (err)
 691                 goto err;
 692
 693         if (pd->uobject) {
 694                 struct mlx4_ib_create_qp ucmd;
 695
 696                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 697                         err = -EFAULT;
 698                         goto err;
 699                 }
 700
 701                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 702
 703                 err = set_user_sq_size(dev, qp, &ucmd);
 704                 if (err)
 705                         goto err;
 706
 707                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 708                                        qp->buf_size, 0, 0);
 709                 if (IS_ERR(qp->umem)) {
 710                         err = PTR_ERR(qp->umem);
 711                         goto err;
 712                 }
 713
 714                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 715                                     ilog2(qp->umem->page_size), &qp->mtt);
 716                 if (err)
 717                         goto err_buf;
 718
 719                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 720                 if (err)
 721                         goto err_mtt;
 722
 723                 if (qp_has_rq(init_attr)) {
 724                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 725                                                   ucmd.db_addr, &qp->db);
 726                         if (err)
 727                                 goto err_mtt;
 728                 }
 729         } else {
 730                 qp->sq_no_prefetch = 0;
 731
 732                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 733                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 734
 735                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 736                         qp->flags |= MLX4_IB_QP_LSO;
 737
 738                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 739                         if (dev->steering_support ==
 740                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 741                                 qp->flags |= MLX4_IB_QP_NETIF;
 742                         else
 743                                 goto err;
 744                 }
 745
 746                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 747                 if (err)
 748                         goto err;
 749
 750                 if (qp_has_rq(init_attr)) {
 751                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 752                         if (err)
 753                                 goto err;
 754
 755                         *qp->db.db = 0;
 756                 }
 757
 758                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 759                         err = -ENOMEM;
 760                         goto err_db;
 761                 }
 762
 763                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 764                                     &qp->mtt);
 765                 if (err)
 766                         goto err_buf;
 767
 768                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 769                 if (err)
 770                         goto err_mtt;
 771
 772                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 773                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 774
 775                 if (!qp->sq.wrid || !qp->rq.wrid) {
 776                         err = -ENOMEM;
 777                         goto err_wrid;
 778                 }
 779         }
 780
 781         if (sqpn) {
 782                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 783                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 784                         if (alloc_proxy_bufs(pd->device, qp)) {
 785                                 err = -ENOMEM;
 786                                 goto err_wrid;
 787                         }
 788                 }
 789         } else {
 790                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 791                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 792                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 793                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 794                 else
 795                         if (qp->flags & MLX4_IB_QP_NETIF)
 796                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 797                         else
 798                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 799                                                             &qpn);
 800                 if (err)
 801                         goto err_proxy;
 802         }
 803
 804         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 805         if (err)
 806                 goto err_qpn;
 807
 808         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 809                 qp->mqp.qpn |= (1 << 23);
 810
 811         /*
 812          * Hardware wants QPN written in big-endian order (after
 813          * shifting) for send doorbell.  Precompute this value to save
 814          * a little bit when posting sends.
 815          */
 816         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 817
 818         qp->mqp.event = mlx4_ib_qp_event;
 819         if (!*caller_qp)
 820                 *caller_qp = qp;
 821         return 0;
 822
 823 err_qpn:
 824         if (!sqpn) {
 825                 if (qp->flags & MLX4_IB_QP_NETIF)
 826                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 827                 else
 828                         mlx4_qp_release_range(dev->dev, qpn, 1);
 829         }
 830 err_proxy:
 831         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 832                 free_proxy_bufs(pd->device, qp);
 833 err_wrid:
 834         if (pd->uobject) {
 835                 if (qp_has_rq(init_attr))
 836                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 837         } else {
 838                 kfree(qp->sq.wrid);
 839                 kfree(qp->rq.wrid);
 840         }
 841
 842 err_mtt:
 843         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 844
 845 err_buf:
 846         if (pd->uobject)
 847                 ib_umem_release(qp->umem);
 848         else
 849                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 850
 851 err_db:
 852         if (!pd->uobject && qp_has_rq(init_attr))
 853                 mlx4_db_free(dev->dev, &qp->db);
 854
 855 err:
 856         if (!*caller_qp)
 857                 kfree(qp);
 858         return err;
 859 }
 860
 861 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 862 {
 863         switch (state) {
 864         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 865         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 866         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 867         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 868         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 869         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 870         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 871         default:                return -1;
 872         }
 873 }
 874
 875 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 876         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 877 {
 878         if (send_cq == recv_cq) {
 879                 spin_lock_irq(&send_cq->lock);
 880                 __acquire(&recv_cq->lock);
 881         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 882                 spin_lock_irq(&send_cq->lock);
 883                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 884         } else {
 885                 spin_lock_irq(&recv_cq->lock);
 886                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 887         }
 888 }
 889
 890 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 891         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 892 {
 893         if (send_cq == recv_cq) {
 894                 __release(&recv_cq->lock);
 895                 spin_unlock_irq(&send_cq->lock);
 896         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 897                 spin_unlock(&recv_cq->lock);
 898                 spin_unlock_irq(&send_cq->lock);
 899         } else {
 900                 spin_unlock(&send_cq->lock);
 901                 spin_unlock_irq(&recv_cq->lock);
 902         }
 903 }
 904
 905 static void del_gid_entries(struct mlx4_ib_qp *qp)
 906 {
 907         struct mlx4_ib_gid_entry *ge, *tmp;
 908
 909         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 910                 list_del(&ge->list);
 911                 kfree(ge);
 912         }
 913 }
 914
 915 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 916 {
 917         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 918                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 919         else
 920                 return to_mpd(qp->ibqp.pd);
 921 }
 922
 923 static void get_cqs(struct mlx4_ib_qp *qp,
 924                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 925 {
 926         switch (qp->ibqp.qp_type) {
 927         case IB_QPT_XRC_TGT:
 928                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 929                 *recv_cq = *send_cq;
 930                 break;
 931         case IB_QPT_XRC_INI:
 932                 *send_cq = to_mcq(qp->ibqp.send_cq);
 933                 *recv_cq = *send_cq;
 934                 break;
 935         default:
 936                 *send_cq = to_mcq(qp->ibqp.send_cq);
 937                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 938                 break;
 939         }
 940 }
 941
 942 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 943                               int is_user)
 944 {
 945         struct mlx4_ib_cq *send_cq, *recv_cq;
 946
 947         if (qp->state != IB_QPS_RESET) {
 948                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 949                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 950                         pr_warn("modify QP %06x to RESET failed.\n",
 951                                qp->mqp.qpn);
 952                 if (qp->pri.smac) {
 953                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
 954                         qp->pri.smac = 0;
 955                 }
 956                 if (qp->alt.smac) {
 957                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
 958                         qp->alt.smac = 0;
 959                 }
 960                 if (qp->pri.vid < 0x1000) {
 961                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
 962                         qp->pri.vid = 0xFFFF;
 963                         qp->pri.candidate_vid = 0xFFFF;
 964                         qp->pri.update_vid = 0;
 965                 }
 966                 if (qp->alt.vid < 0x1000) {
 967                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
 968                         qp->alt.vid = 0xFFFF;
 969                         qp->alt.candidate_vid = 0xFFFF;
 970                         qp->alt.update_vid = 0;
 971                 }
 972         }
 973
 974         get_cqs(qp, &send_cq, &recv_cq);
 975
 976         mlx4_ib_lock_cqs(send_cq, recv_cq);
 977
 978         if (!is_user) {
 979                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 980                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 981                 if (send_cq != recv_cq)
 982                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 983         }
 984
 985         mlx4_qp_remove(dev->dev, &qp->mqp);
 986
 987         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 988
 989         mlx4_qp_free(dev->dev, &qp->mqp);
 990
 991         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
 992                 if (qp->flags & MLX4_IB_QP_NETIF)
 993                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
 994                 else
 995                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 996         }
 997
 998         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 999
1000         if (is_user) {
1001                 if (qp->rq.wqe_cnt)
1002                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1003                                               &qp->db);
1004                 ib_umem_release(qp->umem);
1005         } else {
1006                 kfree(qp->sq.wrid);
1007                 kfree(qp->rq.wrid);
1008                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1009                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1010                         free_proxy_bufs(&dev->ib_dev, qp);
1011                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1012                 if (qp->rq.wqe_cnt)
1013                         mlx4_db_free(dev->dev, &qp->db);
1014         }
1015
1016         del_gid_entries(qp);
1017 }
1018
1019 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1020 {
1021         /* Native or PPF */
1022         if (!mlx4_is_mfunc(dev->dev) ||
1023             (mlx4_is_master(dev->dev) &&
1024              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1025                 return  dev->dev->phys_caps.base_sqpn +
1026                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1027                         attr->port_num - 1;
1028         }
1029         /* PF or VF -- creating proxies */
1030         if (attr->qp_type == IB_QPT_SMI)
1031                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1032         else
1033                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1034 }
1035
1036 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1037                                 struct ib_qp_init_attr *init_attr,
1038                                 struct ib_udata *udata)
1039 {
1040         struct mlx4_ib_qp *qp = NULL;
1041         int err;
1042         u16 xrcdn = 0;
1043
1044         /*
1045          * We only support LSO, vendor flag1, and multicast loopback blocking,
1046          * and only for kernel UD QPs.
1047          */
1048         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1049                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1050                                         MLX4_IB_SRIOV_TUNNEL_QP |
1051                                         MLX4_IB_SRIOV_SQP |
1052                                         MLX4_IB_QP_NETIF))
1053                 return ERR_PTR(-EINVAL);
1054
1055         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1056                 if (init_attr->qp_type != IB_QPT_UD)
1057                         return ERR_PTR(-EINVAL);
1058         }
1059
1060         if (init_attr->create_flags &&
1061             (udata ||
1062              ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
1063               init_attr->qp_type != IB_QPT_UD) ||
1064              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1065               init_attr->qp_type > IB_QPT_GSI)))
1066                 return ERR_PTR(-EINVAL);
1067
1068         switch (init_attr->qp_type) {
1069         case IB_QPT_XRC_TGT:
1070                 pd = to_mxrcd(init_attr->xrcd)->pd;
1071                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1072                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1073                 /* fall through */
1074         case IB_QPT_XRC_INI:
1075                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1076                         return ERR_PTR(-ENOSYS);
1077                 init_attr->recv_cq = init_attr->send_cq;
1078                 /* fall through */
1079         case IB_QPT_RC:
1080         case IB_QPT_UC:
1081         case IB_QPT_RAW_PACKET:
1082                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
1083                 if (!qp)
1084                         return ERR_PTR(-ENOMEM);
1085                 qp->pri.vid = 0xFFFF;
1086                 qp->alt.vid = 0xFFFF;
1087                 /* fall through */
1088         case IB_QPT_UD:
1089         {
1090                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1091                                        udata, 0, &qp);
1092                 if (err)
1093                         return ERR_PTR(err);
1094
1095                 qp->ibqp.qp_num = qp->mqp.qpn;
1096                 qp->xrcdn = xrcdn;
1097
1098                 break;
1099         }
1100         case IB_QPT_SMI:
1101         case IB_QPT_GSI:
1102         {
1103                 /* Userspace is not allowed to create special QPs: */
1104                 if (udata)
1105                         return ERR_PTR(-EINVAL);
1106
1107                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1108                                        get_sqp_num(to_mdev(pd->device), init_attr),
1109                                        &qp);
1110                 if (err)
1111                         return ERR_PTR(err);
1112
1113                 qp->port        = init_attr->port_num;
1114                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1115
1116                 break;
1117         }
1118         default:
1119                 /* Don't support raw QPs */
1120                 return ERR_PTR(-EINVAL);
1121         }
1122
1123         return &qp->ibqp;
1124 }
1125
1126 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1127 {
1128         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1129         struct mlx4_ib_qp *mqp = to_mqp(qp);
1130         struct mlx4_ib_pd *pd;
1131
1132         if (is_qp0(dev, mqp))
1133                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1134
1135         pd = get_pd(mqp);
1136         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1137
1138         if (is_sqp(dev, mqp))
1139                 kfree(to_msqp(mqp));
1140         else
1141                 kfree(mqp);
1142
1143         return 0;
1144 }
1145
1146 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1147 {
1148         switch (type) {
1149         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1150         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1151         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1152         case MLX4_IB_QPT_XRC_INI:
1153         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1154         case MLX4_IB_QPT_SMI:
1155         case MLX4_IB_QPT_GSI:
1156         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1157
1158         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1159         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1160                                                 MLX4_QP_ST_MLX : -1);
1161         case MLX4_IB_QPT_PROXY_SMI:
1162         case MLX4_IB_QPT_TUN_SMI:
1163         case MLX4_IB_QPT_PROXY_GSI:
1164         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1165                                                 MLX4_QP_ST_UD : -1);
1166         default:                        return -1;
1167         }
1168 }
1169
1170 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1171                                    int attr_mask)
1172 {
1173         u8 dest_rd_atomic;
1174         u32 access_flags;
1175         u32 hw_access_flags = 0;
1176
1177         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1178                 dest_rd_atomic = attr->max_dest_rd_atomic;
1179         else
1180                 dest_rd_atomic = qp->resp_depth;
1181
1182         if (attr_mask & IB_QP_ACCESS_FLAGS)
1183                 access_flags = attr->qp_access_flags;
1184         else
1185                 access_flags = qp->atomic_rd_en;
1186
1187         if (!dest_rd_atomic)
1188                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1189
1190         if (access_flags & IB_ACCESS_REMOTE_READ)
1191                 hw_access_flags |= MLX4_QP_BIT_RRE;
1192         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1193                 hw_access_flags |= MLX4_QP_BIT_RAE;
1194         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1195                 hw_access_flags |= MLX4_QP_BIT_RWE;
1196
1197         return cpu_to_be32(hw_access_flags);
1198 }
1199
1200 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1201                             int attr_mask)
1202 {
1203         if (attr_mask & IB_QP_PKEY_INDEX)
1204                 sqp->pkey_index = attr->pkey_index;
1205         if (attr_mask & IB_QP_QKEY)
1206                 sqp->qkey = attr->qkey;
1207         if (attr_mask & IB_QP_SQ_PSN)
1208                 sqp->send_psn = attr->sq_psn;
1209 }
1210
1211 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1212 {
1213         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1214 }
1215
1216 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1217                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1218                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1219 {
1220         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1221                 IB_LINK_LAYER_ETHERNET;
1222         int vidx;
1223         int smac_index;
1224         int err;
1225
1226
1227         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1228         path->rlid          = cpu_to_be16(ah->dlid);
1229         if (ah->static_rate) {
1230                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1231                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1232                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1233                         --path->static_rate;
1234         } else
1235                 path->static_rate = 0;
1236
1237         if (ah->ah_flags & IB_AH_GRH) {
1238                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1239                         pr_err("sgid_index (%u) too large. max is %d\n",
1240                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1241                         return -1;
1242                 }
1243
1244                 path->grh_mylmc |= 1 << 7;
1245                 path->mgid_index = ah->grh.sgid_index;
1246                 path->hop_limit  = ah->grh.hop_limit;
1247                 path->tclass_flowlabel =
1248                         cpu_to_be32((ah->grh.traffic_class << 20) |
1249                                     (ah->grh.flow_label));
1250                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1251         }
1252
1253         if (is_eth) {
1254                 if (!(ah->ah_flags & IB_AH_GRH))
1255                         return -1;
1256
1257                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1258                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1259
1260                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1261                 if (vlan_tag < 0x1000) {
1262                         if (smac_info->vid < 0x1000) {
1263                                 /* both valid vlan ids */
1264                                 if (smac_info->vid != vlan_tag) {
1265                                         /* different VIDs.  unreg old and reg new */
1266                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1267                                         if (err)
1268                                                 return err;
1269                                         smac_info->candidate_vid = vlan_tag;
1270                                         smac_info->candidate_vlan_index = vidx;
1271                                         smac_info->candidate_vlan_port = port;
1272                                         smac_info->update_vid = 1;
1273                                         path->vlan_index = vidx;
1274                                 } else {
1275                                         path->vlan_index = smac_info->vlan_index;
1276                                 }
1277                         } else {
1278                                 /* no current vlan tag in qp */
1279                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1280                                 if (err)
1281                                         return err;
1282                                 smac_info->candidate_vid = vlan_tag;
1283                                 smac_info->candidate_vlan_index = vidx;
1284                                 smac_info->candidate_vlan_port = port;
1285                                 smac_info->update_vid = 1;
1286                                 path->vlan_index = vidx;
1287                         }
1288                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1289                         path->fl = 1 << 6;
1290                 } else {
1291                         /* have current vlan tag. unregister it at modify-qp success */
1292                         if (smac_info->vid < 0x1000) {
1293                                 smac_info->candidate_vid = 0xFFFF;
1294                                 smac_info->update_vid = 1;
1295                         }
1296                 }
1297
1298                 /* get smac_index for RoCE use.
1299                  * If no smac was yet assigned, register one.
1300                  * If one was already assigned, but the new mac differs,
1301                  * unregister the old one and register the new one.
1302                 */
1303                 if (!smac_info->smac || smac_info->smac != smac) {
1304                         /* register candidate now, unreg if needed, after success */
1305                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1306                         if (smac_index >= 0) {
1307                                 smac_info->candidate_smac_index = smac_index;
1308                                 smac_info->candidate_smac = smac;
1309                                 smac_info->candidate_smac_port = port;
1310                         } else {
1311                                 return -EINVAL;
1312                         }
1313                 } else {
1314                         smac_index = smac_info->smac_index;
1315                 }
1316
1317                 memcpy(path->dmac, ah->dmac, 6);
1318                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1319                 /* put MAC table smac index for IBoE */
1320                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1321         } else {
1322                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1323                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1330                          enum ib_qp_attr_mask qp_attr_mask,
1331                          struct mlx4_ib_qp *mqp,
1332                          struct mlx4_qp_path *path, u8 port)
1333 {
1334         return _mlx4_set_path(dev, &qp->ah_attr,
1335                               mlx4_mac_to_u64((u8 *)qp->smac),
1336                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1337                               path, &mqp->pri, port);
1338 }
1339
1340 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1341                              const struct ib_qp_attr *qp,
1342                              enum ib_qp_attr_mask qp_attr_mask,
1343                              struct mlx4_ib_qp *mqp,
1344                              struct mlx4_qp_path *path, u8 port)
1345 {
1346         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1347                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1348                               (qp_attr_mask & IB_QP_ALT_VID) ?
1349                               qp->alt_vlan_id : 0xffff,
1350                               path, &mqp->alt, port);
1351 }
1352
1353 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1354 {
1355         struct mlx4_ib_gid_entry *ge, *tmp;
1356
1357         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1358                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1359                         ge->added = 1;
1360                         ge->port = qp->port;
1361                 }
1362         }
1363 }
1364
1365 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1366                                     struct mlx4_qp_context *context)
1367 {
1368         struct net_device *ndev;
1369         u64 u64_mac;
1370         int smac_index;
1371
1372
1373         ndev = dev->iboe.netdevs[qp->port - 1];
1374         if (ndev) {
1375                 smac = ndev->dev_addr;
1376                 u64_mac = mlx4_mac_to_u64(smac);
1377         } else {
1378                 u64_mac = dev->dev->caps.def_mac[qp->port];
1379         }
1380
1381         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1382         if (!qp->pri.smac) {
1383                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1384                 if (smac_index >= 0) {
1385                         qp->pri.candidate_smac_index = smac_index;
1386                         qp->pri.candidate_smac = u64_mac;
1387                         qp->pri.candidate_smac_port = qp->port;
1388                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1389                 } else {
1390                         return -ENOENT;
1391                 }
1392         }
1393         return 0;
1394 }
1395
1396 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1397                                const struct ib_qp_attr *attr, int attr_mask,
1398                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1399 {
1400         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1401         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1402         struct mlx4_ib_pd *pd;
1403         struct mlx4_ib_cq *send_cq, *recv_cq;
1404         struct mlx4_qp_context *context;
1405         enum mlx4_qp_optpar optpar = 0;
1406         int sqd_event;
1407         int steer_qp = 0;
1408         int err = -EINVAL;
1409
1410         context = kzalloc(sizeof *context, GFP_KERNEL);
1411         if (!context)
1412                 return -ENOMEM;
1413
1414         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1415                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1416
1417         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1418                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1419         else {
1420                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1421                 switch (attr->path_mig_state) {
1422                 case IB_MIG_MIGRATED:
1423                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1424                         break;
1425                 case IB_MIG_REARM:
1426                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1427                         break;
1428                 case IB_MIG_ARMED:
1429                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1430                         break;
1431                 }
1432         }
1433
1434         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1435                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1436         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1437                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1438         else if (ibqp->qp_type == IB_QPT_UD) {
1439                 if (qp->flags & MLX4_IB_QP_LSO)
1440                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1441                                               ilog2(dev->dev->caps.max_gso_sz);
1442                 else
1443                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1444         } else if (attr_mask & IB_QP_PATH_MTU) {
1445                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1446                         pr_err("path MTU (%u) is invalid\n",
1447                                attr->path_mtu);
1448                         goto out;
1449                 }
1450                 context->mtu_msgmax = (attr->path_mtu << 5) |
1451                         ilog2(dev->dev->caps.max_msg_sz);
1452         }
1453
1454         if (qp->rq.wqe_cnt)
1455                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1456         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1457
1458         if (qp->sq.wqe_cnt)
1459                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1460         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1461
1462         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1463                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1464                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1465                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1466                         context->param3 |= cpu_to_be32(1 << 30);
1467         }
1468
1469         if (qp->ibqp.uobject)
1470                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1471         else
1472                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1473
1474         if (attr_mask & IB_QP_DEST_QPN)
1475                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1476
1477         if (attr_mask & IB_QP_PORT) {
1478                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1479                     !(attr_mask & IB_QP_AV)) {
1480                         mlx4_set_sched(&context->pri_path, attr->port_num);
1481                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1482                 }
1483         }
1484
1485         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1486                 if (dev->counters[qp->port - 1] != -1) {
1487                         context->pri_path.counter_index =
1488                                                 dev->counters[qp->port - 1];
1489                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1490                 } else
1491                         context->pri_path.counter_index = 0xff;
1492
1493                 if (qp->flags & MLX4_IB_QP_NETIF) {
1494                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1495                         steer_qp = 1;
1496                 }
1497         }
1498
1499         if (attr_mask & IB_QP_PKEY_INDEX) {
1500                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1501                         context->pri_path.disable_pkey_check = 0x40;
1502                 context->pri_path.pkey_index = attr->pkey_index;
1503                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1504         }
1505
1506         if (attr_mask & IB_QP_AV) {
1507                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1508                                   attr_mask & IB_QP_PORT ?
1509                                   attr->port_num : qp->port))
1510                         goto out;
1511
1512                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1513                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1514         }
1515
1516         if (attr_mask & IB_QP_TIMEOUT) {
1517                 context->pri_path.ackto |= attr->timeout << 3;
1518                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1519         }
1520
1521         if (attr_mask & IB_QP_ALT_PATH) {
1522                 if (attr->alt_port_num == 0 ||
1523                     attr->alt_port_num > dev->dev->caps.num_ports)
1524                         goto out;
1525
1526                 if (attr->alt_pkey_index >=
1527                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1528                         goto out;
1529
1530                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1531                                       &context->alt_path,
1532                                       attr->alt_port_num))
1533                         goto out;
1534
1535                 context->alt_path.pkey_index = attr->alt_pkey_index;
1536                 context->alt_path.ackto = attr->alt_timeout << 3;
1537                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1538         }
1539
1540         pd = get_pd(qp);
1541         get_cqs(qp, &send_cq, &recv_cq);
1542         context->pd       = cpu_to_be32(pd->pdn);
1543         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1544         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1545         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1546
1547         /* Set "fast registration enabled" for all kernel QPs */
1548         if (!qp->ibqp.uobject)
1549                 context->params1 |= cpu_to_be32(1 << 11);
1550
1551         if (attr_mask & IB_QP_RNR_RETRY) {
1552                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1553                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1554         }
1555
1556         if (attr_mask & IB_QP_RETRY_CNT) {
1557                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1558                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1559         }
1560
1561         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1562                 if (attr->max_rd_atomic)
1563                         context->params1 |=
1564                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1565                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1566         }
1567
1568         if (attr_mask & IB_QP_SQ_PSN)
1569                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1570
1571         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1572                 if (attr->max_dest_rd_atomic)
1573                         context->params2 |=
1574                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1575                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1576         }
1577
1578         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1579                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1580                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1581         }
1582
1583         if (ibqp->srq)
1584                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1585
1586         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1587                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1588                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1589         }
1590         if (attr_mask & IB_QP_RQ_PSN)
1591                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1592
1593         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1594         if (attr_mask & IB_QP_QKEY) {
1595                 if (qp->mlx4_ib_qp_type &
1596                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1597                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1598                 else {
1599                         if (mlx4_is_mfunc(dev->dev) &&
1600                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1601                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1602                             MLX4_RESERVED_QKEY_BASE) {
1603                                 pr_err("Cannot use reserved QKEY"
1604                                        " 0x%x (range 0xffff0000..0xffffffff"
1605                                        " is reserved)\n", attr->qkey);
1606                                 err = -EINVAL;
1607                                 goto out;
1608                         }
1609                         context->qkey = cpu_to_be32(attr->qkey);
1610                 }
1611                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1612         }
1613
1614         if (ibqp->srq)
1615                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1616
1617         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1618                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1619
1620         if (cur_state == IB_QPS_INIT &&
1621             new_state == IB_QPS_RTR  &&
1622             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1623              ibqp->qp_type == IB_QPT_UD ||
1624              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1625                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1626                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1627                     qp->mlx4_ib_qp_type &
1628                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1629                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1630                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1631                                 context->pri_path.fl = 0x80;
1632                 } else {
1633                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1634                                 context->pri_path.fl = 0x80;
1635                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1636                 }
1637                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1638                     IB_LINK_LAYER_ETHERNET) {
1639                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1640                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1641                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1642                         /* handle smac_index */
1643                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1644                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1645                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1646                                 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1647                                 if (err)
1648                                         return -EINVAL;
1649                         }
1650                 }
1651         }
1652
1653         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
1654                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1655                                         MLX4_IB_LINK_TYPE_ETH;
1656
1657         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1658                 int is_eth = rdma_port_get_link_layer(
1659                                 &dev->ib_dev, qp->port) ==
1660                                 IB_LINK_LAYER_ETHERNET;
1661                 if (is_eth) {
1662                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1663                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1664                 }
1665         }
1666
1667
1668         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1669             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1670                 sqd_event = 1;
1671         else
1672                 sqd_event = 0;
1673
1674         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1675                 context->rlkey |= (1 << 4);
1676
1677         /*
1678          * Before passing a kernel QP to the HW, make sure that the
1679          * ownership bits of the send queue are set and the SQ
1680          * headroom is stamped so that the hardware doesn't start
1681          * processing stale work requests.
1682          */
1683         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1684                 struct mlx4_wqe_ctrl_seg *ctrl;
1685                 int i;
1686
1687                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1688                         ctrl = get_send_wqe(qp, i);
1689                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1690                         if (qp->sq_max_wqes_per_wr == 1)
1691                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1692
1693                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1694                 }
1695         }
1696
1697         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1698                              to_mlx4_state(new_state), context, optpar,
1699                              sqd_event, &qp->mqp);
1700         if (err)
1701                 goto out;
1702
1703         qp->state = new_state;
1704
1705         if (attr_mask & IB_QP_ACCESS_FLAGS)
1706                 qp->atomic_rd_en = attr->qp_access_flags;
1707         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1708                 qp->resp_depth = attr->max_dest_rd_atomic;
1709         if (attr_mask & IB_QP_PORT) {
1710                 qp->port = attr->port_num;
1711                 update_mcg_macs(dev, qp);
1712         }
1713         if (attr_mask & IB_QP_ALT_PATH)
1714                 qp->alt_port = attr->alt_port_num;
1715
1716         if (is_sqp(dev, qp))
1717                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1718
1719         /*
1720          * If we moved QP0 to RTR, bring the IB link up; if we moved
1721          * QP0 to RESET or ERROR, bring the link back down.
1722          */
1723         if (is_qp0(dev, qp)) {
1724                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1725                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1726                                 pr_warn("INIT_PORT failed for port %d\n",
1727                                        qp->port);
1728
1729                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1730                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1731                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1732         }
1733
1734         /*
1735          * If we moved a kernel QP to RESET, clean up all old CQ
1736          * entries and reinitialize the QP.
1737          */
1738         if (new_state == IB_QPS_RESET) {
1739                 if (!ibqp->uobject) {
1740                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1741                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1742                         if (send_cq != recv_cq)
1743                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1744
1745                         qp->rq.head = 0;
1746                         qp->rq.tail = 0;
1747                         qp->sq.head = 0;
1748                         qp->sq.tail = 0;
1749                         qp->sq_next_wqe = 0;
1750                         if (qp->rq.wqe_cnt)
1751                                 *qp->db.db  = 0;
1752
1753                         if (qp->flags & MLX4_IB_QP_NETIF)
1754                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1755                 }
1756                 if (qp->pri.smac) {
1757                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1758                         qp->pri.smac = 0;
1759                 }
1760                 if (qp->alt.smac) {
1761                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1762                         qp->alt.smac = 0;
1763                 }
1764                 if (qp->pri.vid < 0x1000) {
1765                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1766                         qp->pri.vid = 0xFFFF;
1767                         qp->pri.candidate_vid = 0xFFFF;
1768                         qp->pri.update_vid = 0;
1769                 }
1770
1771                 if (qp->alt.vid < 0x1000) {
1772                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1773                         qp->alt.vid = 0xFFFF;
1774                         qp->alt.candidate_vid = 0xFFFF;
1775                         qp->alt.update_vid = 0;
1776                 }
1777         }
1778 out:
1779         if (err && steer_qp)
1780                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1781         kfree(context);
1782         if (qp->pri.candidate_smac) {
1783                 if (err) {
1784                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1785                 } else {
1786                         if (qp->pri.smac)
1787                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1788                         qp->pri.smac = qp->pri.candidate_smac;
1789                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1790                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1791                 }
1792                 qp->pri.candidate_smac = 0;
1793                 qp->pri.candidate_smac_index = 0;
1794                 qp->pri.candidate_smac_port = 0;
1795         }
1796         if (qp->alt.candidate_smac) {
1797                 if (err) {
1798                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1799                 } else {
1800                         if (qp->alt.smac)
1801                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1802                         qp->alt.smac = qp->alt.candidate_smac;
1803                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1804                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1805                 }
1806                 qp->alt.candidate_smac = 0;
1807                 qp->alt.candidate_smac_index = 0;
1808                 qp->alt.candidate_smac_port = 0;
1809         }
1810
1811         if (qp->pri.update_vid) {
1812                 if (err) {
1813                         if (qp->pri.candidate_vid < 0x1000)
1814                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1815                                                      qp->pri.candidate_vid);
1816                 } else {
1817                         if (qp->pri.vid < 0x1000)
1818                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1819                                                      qp->pri.vid);
1820                         qp->pri.vid = qp->pri.candidate_vid;
1821                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1822                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1823                 }
1824                 qp->pri.candidate_vid = 0xFFFF;
1825                 qp->pri.update_vid = 0;
1826         }
1827
1828         if (qp->alt.update_vid) {
1829                 if (err) {
1830                         if (qp->alt.candidate_vid < 0x1000)
1831                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1832                                                      qp->alt.candidate_vid);
1833                 } else {
1834                         if (qp->alt.vid < 0x1000)
1835                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1836                                                      qp->alt.vid);
1837                         qp->alt.vid = qp->alt.candidate_vid;
1838                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1839                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1840                 }
1841                 qp->alt.candidate_vid = 0xFFFF;
1842                 qp->alt.update_vid = 0;
1843         }
1844
1845         return err;
1846 }
1847
1848 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1849                       int attr_mask, struct ib_udata *udata)
1850 {
1851         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1852         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1853         enum ib_qp_state cur_state, new_state;
1854         int err = -EINVAL;
1855         int ll;
1856         mutex_lock(&qp->mutex);
1857
1858         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1859         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1860
1861         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1862                 ll = IB_LINK_LAYER_UNSPECIFIED;
1863         } else {
1864                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1865                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1866         }
1867
1868         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1869                                 attr_mask, ll)) {
1870                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1871                          "for transition %d to %d. qp_type %d,"
1872                          " attr_mask 0x%x\n",
1873                          ibqp->qp_num, cur_state, new_state,
1874                          ibqp->qp_type, attr_mask);
1875                 goto out;
1876         }
1877
1878         if ((attr_mask & IB_QP_PORT) &&
1879             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1880                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1881                          "for transition %d to %d. qp_type %d\n",
1882                          ibqp->qp_num, attr->port_num, cur_state,
1883                          new_state, ibqp->qp_type);
1884                 goto out;
1885         }
1886
1887         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1888             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1889              IB_LINK_LAYER_ETHERNET))
1890                 goto out;
1891
1892         if (attr_mask & IB_QP_PKEY_INDEX) {
1893                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1894                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1895                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1896                                  "for transition %d to %d. qp_type %d\n",
1897                                  ibqp->qp_num, attr->pkey_index, cur_state,
1898                                  new_state, ibqp->qp_type);
1899                         goto out;
1900                 }
1901         }
1902
1903         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1904             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1905                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1906                          "Transition %d to %d. qp_type %d\n",
1907                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1908                          new_state, ibqp->qp_type);
1909                 goto out;
1910         }
1911
1912         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1913             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1914                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1915                          "Transition %d to %d. qp_type %d\n",
1916                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1917                          new_state, ibqp->qp_type);
1918                 goto out;
1919         }
1920
1921         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1922                 err = 0;
1923                 goto out;
1924         }
1925
1926         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1927
1928 out:
1929         mutex_unlock(&qp->mutex);
1930         return err;
1931 }
1932
1933 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1934                                   struct ib_send_wr *wr,
1935                                   void *wqe, unsigned *mlx_seg_len)
1936 {
1937         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1938         struct ib_device *ib_dev = &mdev->ib_dev;
1939         struct mlx4_wqe_mlx_seg *mlx = wqe;
1940         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1941         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1942         u16 pkey;
1943         u32 qkey;
1944         int send_size;
1945         int header_size;
1946         int spc;
1947         int i;
1948
1949         if (wr->opcode != IB_WR_SEND)
1950                 return -EINVAL;
1951
1952         send_size = 0;
1953
1954         for (i = 0; i < wr->num_sge; ++i)
1955                 send_size += wr->sg_list[i].length;
1956
1957         /* for proxy-qp0 sends, need to add in size of tunnel header */
1958         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1959         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1960                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1961
1962         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1963
1964         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1965                 sqp->ud_header.lrh.service_level =
1966                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1967                 sqp->ud_header.lrh.destination_lid =
1968                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1969                 sqp->ud_header.lrh.source_lid =
1970                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1971         }
1972
1973         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1974
1975         /* force loopback */
1976         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
1977         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1978
1979         sqp->ud_header.lrh.virtual_lane    = 0;
1980         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1981         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
1982         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1983         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
1984                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1985         else
1986                 sqp->ud_header.bth.destination_qpn =
1987                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1988
1989         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1990         if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
1991                 return -EINVAL;
1992         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
1993         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
1994
1995         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1996         sqp->ud_header.immediate_present = 0;
1997
1998         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1999
2000         /*
2001          * Inline data segments may not cross a 64 byte boundary.  If
2002          * our UD header is bigger than the space available up to the
2003          * next 64 byte boundary in the WQE, use two inline data
2004          * segments to hold the UD header.
2005          */
2006         spc = MLX4_INLINE_ALIGN -
2007               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2008         if (header_size <= spc) {
2009                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2010                 memcpy(inl + 1, sqp->header_buf, header_size);
2011                 i = 1;
2012         } else {
2013                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2014                 memcpy(inl + 1, sqp->header_buf, spc);
2015
2016                 inl = (void *) (inl + 1) + spc;
2017                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2018                 /*
2019                  * Need a barrier here to make sure all the data is
2020                  * visible before the byte_count field is set.
2021                  * Otherwise the HCA prefetcher could grab the 64-byte
2022                  * chunk with this inline segment and get a valid (!=
2023                  * 0xffffffff) byte count but stale data, and end up
2024                  * generating a packet with bad headers.
2025                  *
2026                  * The first inline segment's byte_count field doesn't
2027                  * need a barrier, because it comes after a
2028                  * control/MLX segment and therefore is at an offset
2029                  * of 16 mod 64.
2030                  */
2031                 wmb();
2032                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2033                 i = 2;
2034         }
2035
2036         *mlx_seg_len =
2037         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2038         return 0;
2039 }
2040
2041 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2042                             void *wqe, unsigned *mlx_seg_len)
2043 {
2044         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2045         struct mlx4_wqe_mlx_seg *mlx = wqe;
2046         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2047         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2048         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2049         union ib_gid sgid;
2050         u16 pkey;
2051         int send_size;
2052         int header_size;
2053         int spc;
2054         int i;
2055         int err = 0;
2056         u16 vlan = 0xffff;
2057         bool is_eth;
2058         bool is_vlan = false;
2059         bool is_grh;
2060
2061         send_size = 0;
2062         for (i = 0; i < wr->num_sge; ++i)
2063                 send_size += wr->sg_list[i].length;
2064
2065         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2066         is_grh = mlx4_ib_ah_grh_present(ah);
2067         if (is_eth) {
2068                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2069                         /* When multi-function is enabled, the ib_core gid
2070                          * indexes don't necessarily match the hw ones, so
2071                          * we must use our own cache */
2072                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2073                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2074                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2075                         if (err)
2076                                 return err;
2077                 } else  {
2078                         err = ib_get_cached_gid(ib_dev,
2079                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2080                                                 ah->av.ib.gid_index, &sgid);
2081                         if (err)
2082                                 return err;
2083                 }
2084
2085                 if (ah->av.eth.vlan != 0xffff) {
2086                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2087                         is_vlan = 1;
2088                 }
2089         }
2090         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2091
2092         if (!is_eth) {
2093                 sqp->ud_header.lrh.service_level =
2094                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2095                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2096                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2097         }
2098
2099         if (is_grh) {
2100                 sqp->ud_header.grh.traffic_class =
2101                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2102                 sqp->ud_header.grh.flow_label    =
2103                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2104                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2105                 if (is_eth)
2106                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2107                 else {
2108                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2109                         /* When multi-function is enabled, the ib_core gid
2110                          * indexes don't necessarily match the hw ones, so
2111                          * we must use our own cache */
2112                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2113                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2114                                                        subnet_prefix;
2115                         sqp->ud_header.grh.source_gid.global.interface_id =
2116                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2117                                                guid_cache[ah->av.ib.gid_index];
2118                 } else
2119                         ib_get_cached_gid(ib_dev,
2120                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2121                                           ah->av.ib.gid_index,
2122                                           &sqp->ud_header.grh.source_gid);
2123                 }
2124                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2125                        ah->av.ib.dgid, 16);
2126         }
2127
2128         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2129
2130         if (!is_eth) {
2131                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2132                                           (sqp->ud_header.lrh.destination_lid ==
2133                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2134                                           (sqp->ud_header.lrh.service_level << 8));
2135                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2136                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2137                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2138         }
2139
2140         switch (wr->opcode) {
2141         case IB_WR_SEND:
2142                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2143                 sqp->ud_header.immediate_present = 0;
2144                 break;
2145         case IB_WR_SEND_WITH_IMM:
2146                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2147                 sqp->ud_header.immediate_present = 1;
2148                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
2149                 break;
2150         default:
2151                 return -EINVAL;
2152         }
2153
2154         if (is_eth) {
2155                 u8 *smac;
2156                 struct in6_addr in6;
2157
2158                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2159
2160                 mlx->sched_prio = cpu_to_be16(pcp);
2161
2162                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2163                 /* FIXME: cache smac value? */
2164                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2165                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2166                 memcpy(&in6, sgid.raw, sizeof(in6));
2167
2168                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev))
2169                         smac = to_mdev(sqp->qp.ibqp.device)->
2170                                 iboe.netdevs[sqp->qp.port - 1]->dev_addr;
2171                 else    /* use the src mac of the tunnel */
2172                         smac = ah->av.eth.s_mac;
2173                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
2174                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2175                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2176                 if (!is_vlan) {
2177                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2178                 } else {
2179                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2180                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2181                 }
2182         } else {
2183                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2184                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2185                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2186         }
2187         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2188         if (!sqp->qp.ibqp.qp_num)
2189                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2190         else
2191                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2192         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2193         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2194         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2195         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2196                                                sqp->qkey : wr->wr.ud.remote_qkey);
2197         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2198
2199         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2200
2201         if (0) {
2202                 pr_err("built UD header of size %d:\n", header_size);
2203                 for (i = 0; i < header_size / 4; ++i) {
2204                         if (i % 8 == 0)
2205                                 pr_err("  [%02x] ", i * 4);
2206                         pr_cont(" %08x",
2207                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2208                         if ((i + 1) % 8 == 0)
2209                                 pr_cont("\n");
2210                 }
2211                 pr_err("\n");
2212         }
2213
2214         /*
2215          * Inline data segments may not cross a 64 byte boundary.  If
2216          * our UD header is bigger than the space available up to the
2217          * next 64 byte boundary in the WQE, use two inline data
2218          * segments to hold the UD header.
2219          */
2220         spc = MLX4_INLINE_ALIGN -
2221                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2222         if (header_size <= spc) {
2223                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2224                 memcpy(inl + 1, sqp->header_buf, header_size);
2225                 i = 1;
2226         } else {
2227                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2228                 memcpy(inl + 1, sqp->header_buf, spc);
2229
2230                 inl = (void *) (inl + 1) + spc;
2231                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2232                 /*
2233                  * Need a barrier here to make sure all the data is
2234                  * visible before the byte_count field is set.
2235                  * Otherwise the HCA prefetcher could grab the 64-byte
2236                  * chunk with this inline segment and get a valid (!=
2237                  * 0xffffffff) byte count but stale data, and end up
2238                  * generating a packet with bad headers.
2239                  *
2240                  * The first inline segment's byte_count field doesn't
2241                  * need a barrier, because it comes after a
2242                  * control/MLX segment and therefore is at an offset
2243                  * of 16 mod 64.
2244                  */
2245                 wmb();
2246                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2247                 i = 2;
2248         }
2249
2250         *mlx_seg_len =
2251                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2252         return 0;
2253 }
2254
2255 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2256 {
2257         unsigned cur;
2258         struct mlx4_ib_cq *cq;
2259
2260         cur = wq->head - wq->tail;
2261         if (likely(cur + nreq < wq->max_post))
2262                 return 0;
2263
2264         cq = to_mcq(ib_cq);
2265         spin_lock(&cq->lock);
2266         cur = wq->head - wq->tail;
2267         spin_unlock(&cq->lock);
2268
2269         return cur + nreq >= wq->max_post;
2270 }
2271
2272 static __be32 convert_access(int acc)
2273 {
2274         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2275                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2276                (acc & IB_ACCESS_REMOTE_WRITE  ?
2277                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2278                (acc & IB_ACCESS_REMOTE_READ   ?
2279                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2280                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2281                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2282 }
2283
2284 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2285 {
2286         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2287         int i;
2288
2289         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2290                 mfrpl->mapped_page_list[i] =
2291                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2292                                     MLX4_MTT_FLAG_PRESENT);
2293
2294         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2295         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2296         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2297         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2298         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2299         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2300         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2301         fseg->reserved[0]       = 0;
2302         fseg->reserved[1]       = 0;
2303 }
2304
2305 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2306 {
2307         bseg->flags1 =
2308                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2309                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2310                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2311                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2312         bseg->flags2 = 0;
2313         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2314                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2315         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2316                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2317         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2318         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2319         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2320         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2321 }
2322
2323 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2324 {
2325         memset(iseg, 0, sizeof(*iseg));
2326         iseg->mem_key = cpu_to_be32(rkey);
2327 }
2328
2329 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2330                                           u64 remote_addr, u32 rkey)
2331 {
2332         rseg->raddr    = cpu_to_be64(remote_addr);
2333         rseg->rkey     = cpu_to_be32(rkey);
2334         rseg->reserved = 0;
2335 }
2336
2337 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2338 {
2339         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2340                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2341                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2342         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2343                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2344                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2345         } else {
2346                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2347                 aseg->compare  = 0;
2348         }
2349
2350 }
2351
2352 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2353                                   struct ib_send_wr *wr)
2354 {
2355         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2356         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2357         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2358         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2359 }
2360
2361 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2362                              struct ib_send_wr *wr)
2363 {
2364         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2365         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2366         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2367         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2368         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2369 }
2370
2371 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2372                                     struct mlx4_wqe_datagram_seg *dseg,
2373                                     struct ib_send_wr *wr, enum ib_qp_type qpt)
2374 {
2375         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2376         struct mlx4_av sqp_av = {0};
2377         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2378
2379         /* force loopback */
2380         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2381         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2382         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2383                         cpu_to_be32(0xf0000000);
2384
2385         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2386         /* This function used only for sending on QP1 proxies */
2387         dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2388         /* Use QKEY from the QP context, which is set by master */
2389         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2390 }
2391
2392 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2393 {
2394         struct mlx4_wqe_inline_seg *inl = wqe;
2395         struct mlx4_ib_tunnel_header hdr;
2396         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2397         int spc;
2398         int i;
2399
2400         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2401         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2402         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2403         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2404         memcpy(hdr.mac, ah->av.eth.mac, 6);
2405         hdr.vlan = ah->av.eth.vlan;
2406
2407         spc = MLX4_INLINE_ALIGN -
2408                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2409         if (sizeof (hdr) <= spc) {
2410                 memcpy(inl + 1, &hdr, sizeof (hdr));
2411                 wmb();
2412                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2413                 i = 1;
2414         } else {
2415                 memcpy(inl + 1, &hdr, spc);
2416                 wmb();
2417                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2418
2419                 inl = (void *) (inl + 1) + spc;
2420                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2421                 wmb();
2422                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2423                 i = 2;
2424         }
2425
2426         *mlx_seg_len =
2427                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2428 }
2429
2430 static void set_mlx_icrc_seg(void *dseg)
2431 {
2432         u32 *t = dseg;
2433         struct mlx4_wqe_inline_seg *iseg = dseg;
2434
2435         t[1] = 0;
2436
2437         /*
2438          * Need a barrier here before writing the byte_count field to
2439          * make sure that all the data is visible before the
2440          * byte_count field is set.  Otherwise, if the segment begins
2441          * a new cacheline, the HCA prefetcher could grab the 64-byte
2442          * chunk and get a valid (!= * 0xffffffff) byte count but
2443          * stale data, and end up sending the wrong data.
2444          */
2445         wmb();
2446
2447         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2448 }
2449
2450 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2451 {
2452         dseg->lkey       = cpu_to_be32(sg->lkey);
2453         dseg->addr       = cpu_to_be64(sg->addr);
2454
2455         /*
2456          * Need a barrier here before writing the byte_count field to
2457          * make sure that all the data is visible before the
2458          * byte_count field is set.  Otherwise, if the segment begins
2459          * a new cacheline, the HCA prefetcher could grab the 64-byte
2460          * chunk and get a valid (!= * 0xffffffff) byte count but
2461          * stale data, and end up sending the wrong data.
2462          */
2463         wmb();
2464
2465         dseg->byte_count = cpu_to_be32(sg->length);
2466 }
2467
2468 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2469 {
2470         dseg->byte_count = cpu_to_be32(sg->length);
2471         dseg->lkey       = cpu_to_be32(sg->lkey);
2472         dseg->addr       = cpu_to_be64(sg->addr);
2473 }
2474
2475 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2476                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2477                          __be32 *lso_hdr_sz, __be32 *blh)
2478 {
2479         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2480
2481         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2482                 *blh = cpu_to_be32(1 << 6);
2483
2484         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2485                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2486                 return -EINVAL;
2487
2488         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2489
2490         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2491                                    wr->wr.ud.hlen);
2492         *lso_seg_len = halign;
2493         return 0;
2494 }
2495
2496 static __be32 send_ieth(struct ib_send_wr *wr)
2497 {
2498         switch (wr->opcode) {
2499         case IB_WR_SEND_WITH_IMM:
2500         case IB_WR_RDMA_WRITE_WITH_IMM:
2501                 return wr->ex.imm_data;
2502
2503         case IB_WR_SEND_WITH_INV:
2504                 return cpu_to_be32(wr->ex.invalidate_rkey);
2505
2506         default:
2507                 return 0;
2508         }
2509 }
2510
2511 static void add_zero_len_inline(void *wqe)
2512 {
2513         struct mlx4_wqe_inline_seg *inl = wqe;
2514         memset(wqe, 0, 16);
2515         inl->byte_count = cpu_to_be32(1 << 31);
2516 }
2517
2518 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2519                       struct ib_send_wr **bad_wr)
2520 {
2521         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2522         void *wqe;
2523         struct mlx4_wqe_ctrl_seg *ctrl;
2524         struct mlx4_wqe_data_seg *dseg;
2525         unsigned long flags;
2526         int nreq;
2527         int err = 0;
2528         unsigned ind;
2529         int uninitialized_var(stamp);
2530         int uninitialized_var(size);
2531         unsigned uninitialized_var(seglen);
2532         __be32 dummy;
2533         __be32 *lso_wqe;
2534         __be32 uninitialized_var(lso_hdr_sz);
2535         __be32 blh;
2536         int i;
2537
2538         spin_lock_irqsave(&qp->sq.lock, flags);
2539
2540         ind = qp->sq_next_wqe;
2541
2542         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2543                 lso_wqe = &dummy;
2544                 blh = 0;
2545
2546                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2547                         err = -ENOMEM;
2548                         *bad_wr = wr;
2549                         goto out;
2550                 }
2551
2552                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2553                         err = -EINVAL;
2554                         *bad_wr = wr;
2555                         goto out;
2556                 }
2557
2558                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2559                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2560
2561                 ctrl->srcrb_flags =
2562                         (wr->send_flags & IB_SEND_SIGNALED ?
2563                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2564                         (wr->send_flags & IB_SEND_SOLICITED ?
2565                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2566                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2567                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2568                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2569                         qp->sq_signal_bits;
2570
2571                 ctrl->imm = send_ieth(wr);
2572
2573                 wqe += sizeof *ctrl;
2574                 size = sizeof *ctrl / 16;
2575
2576                 switch (qp->mlx4_ib_qp_type) {
2577                 case MLX4_IB_QPT_RC:
2578                 case MLX4_IB_QPT_UC:
2579                         switch (wr->opcode) {
2580                         case IB_WR_ATOMIC_CMP_AND_SWP:
2581                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2582                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2583                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2584                                               wr->wr.atomic.rkey);
2585                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2586
2587                                 set_atomic_seg(wqe, wr);
2588                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2589
2590                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2591                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2592
2593                                 break;
2594
2595                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2596                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2597                                               wr->wr.atomic.rkey);
2598                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2599
2600                                 set_masked_atomic_seg(wqe, wr);
2601                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2602
2603                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2604                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2605
2606                                 break;
2607
2608                         case IB_WR_RDMA_READ:
2609                         case IB_WR_RDMA_WRITE:
2610                         case IB_WR_RDMA_WRITE_WITH_IMM:
2611                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2612                                               wr->wr.rdma.rkey);
2613                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2614                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2615                                 break;
2616
2617                         case IB_WR_LOCAL_INV:
2618                                 ctrl->srcrb_flags |=
2619                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2620                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2621                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2622                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2623                                 break;
2624
2625                         case IB_WR_FAST_REG_MR:
2626                                 ctrl->srcrb_flags |=
2627                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2628                                 set_fmr_seg(wqe, wr);
2629                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2630                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2631                                 break;
2632
2633                         case IB_WR_BIND_MW:
2634                                 ctrl->srcrb_flags |=
2635                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2636                                 set_bind_seg(wqe, wr);
2637                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2638                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2639                                 break;
2640                         default:
2641                                 /* No extra segments required for sends */
2642                                 break;
2643                         }
2644                         break;
2645
2646                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2647                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2648                         if (unlikely(err)) {
2649                                 *bad_wr = wr;
2650                                 goto out;
2651                         }
2652                         wqe  += seglen;
2653                         size += seglen / 16;
2654                         break;
2655                 case MLX4_IB_QPT_TUN_SMI:
2656                 case MLX4_IB_QPT_TUN_GSI:
2657                         /* this is a UD qp used in MAD responses to slaves. */
2658                         set_datagram_seg(wqe, wr);
2659                         /* set the forced-loopback bit in the data seg av */
2660                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2661                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2662                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2663                         break;
2664                 case MLX4_IB_QPT_UD:
2665                         set_datagram_seg(wqe, wr);
2666                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2667                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2668
2669                         if (wr->opcode == IB_WR_LSO) {
2670                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2671                                 if (unlikely(err)) {
2672                                         *bad_wr = wr;
2673                                         goto out;
2674                                 }
2675                                 lso_wqe = (__be32 *) wqe;
2676                                 wqe  += seglen;
2677                                 size += seglen / 16;
2678                         }
2679                         break;
2680
2681                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2682                         if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) {
2683                                 err = -ENOSYS;
2684                                 *bad_wr = wr;
2685                                 goto out;
2686                         }
2687                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2688                         if (unlikely(err)) {
2689                                 *bad_wr = wr;
2690                                 goto out;
2691                         }
2692                         wqe  += seglen;
2693                         size += seglen / 16;
2694                         /* to start tunnel header on a cache-line boundary */
2695                         add_zero_len_inline(wqe);
2696                         wqe += 16;
2697                         size++;
2698                         build_tunnel_header(wr, wqe, &seglen);
2699                         wqe  += seglen;
2700                         size += seglen / 16;
2701                         break;
2702                 case MLX4_IB_QPT_PROXY_SMI:
2703                         /* don't allow QP0 sends on guests */
2704                         err = -ENOSYS;
2705                         *bad_wr = wr;
2706                         goto out;
2707                 case MLX4_IB_QPT_PROXY_GSI:
2708                         /* If we are tunneling special qps, this is a UD qp.
2709                          * In this case we first add a UD segment targeting
2710                          * the tunnel qp, and then add a header with address
2711                          * information */
2712                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type);
2713                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2714                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2715                         build_tunnel_header(wr, wqe, &seglen);
2716                         wqe  += seglen;
2717                         size += seglen / 16;
2718                         break;
2719
2720                 case MLX4_IB_QPT_SMI:
2721                 case MLX4_IB_QPT_GSI:
2722                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2723                         if (unlikely(err)) {
2724                                 *bad_wr = wr;
2725                                 goto out;
2726                         }
2727                         wqe  += seglen;
2728                         size += seglen / 16;
2729                         break;
2730
2731                 default:
2732                         break;
2733                 }
2734
2735                 /*
2736                  * Write data segments in reverse order, so as to
2737                  * overwrite cacheline stamp last within each
2738                  * cacheline.  This avoids issues with WQE
2739                  * prefetching.
2740                  */
2741
2742                 dseg = wqe;
2743                 dseg += wr->num_sge - 1;
2744                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2745
2746                 /* Add one more inline data segment for ICRC for MLX sends */
2747                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2748                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2749                              qp->mlx4_ib_qp_type &
2750                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2751                         set_mlx_icrc_seg(dseg + 1);
2752                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2753                 }
2754
2755                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2756                         set_data_seg(dseg, wr->sg_list + i);
2757
2758                 /*
2759                  * Possibly overwrite stamping in cacheline with LSO
2760                  * segment only after making sure all data segments
2761                  * are written.
2762                  */
2763                 wmb();
2764                 *lso_wqe = lso_hdr_sz;
2765
2766                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2767                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2768
2769                 /*
2770                  * Make sure descriptor is fully written before
2771                  * setting ownership bit (because HW can start
2772                  * executing as soon as we do).
2773                  */
2774                 wmb();
2775
2776                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2777                         *bad_wr = wr;
2778                         err = -EINVAL;
2779                         goto out;
2780                 }
2781
2782                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2783                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2784
2785                 stamp = ind + qp->sq_spare_wqes;
2786                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2787
2788                 /*
2789                  * We can improve latency by not stamping the last
2790                  * send queue WQE until after ringing the doorbell, so
2791                  * only stamp here if there are still more WQEs to post.
2792                  *
2793                  * Same optimization applies to padding with NOP wqe
2794                  * in case of WQE shrinking (used to prevent wrap-around
2795                  * in the middle of WR).
2796                  */
2797                 if (wr->next) {
2798                         stamp_send_wqe(qp, stamp, size * 16);
2799                         ind = pad_wraparound(qp, ind);
2800                 }
2801         }
2802
2803 out:
2804         if (likely(nreq)) {
2805                 qp->sq.head += nreq;
2806
2807                 /*
2808                  * Make sure that descriptors are written before
2809                  * doorbell record.
2810                  */
2811                 wmb();
2812
2813                 writel(qp->doorbell_qpn,
2814                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2815
2816                 /*
2817                  * Make sure doorbells don't leak out of SQ spinlock
2818                  * and reach the HCA out of order.
2819                  */
2820                 mmiowb();
2821
2822                 stamp_send_wqe(qp, stamp, size * 16);
2823
2824                 ind = pad_wraparound(qp, ind);
2825                 qp->sq_next_wqe = ind;
2826         }
2827
2828         spin_unlock_irqrestore(&qp->sq.lock, flags);
2829
2830         return err;
2831 }
2832
2833 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2834                       struct ib_recv_wr **bad_wr)
2835 {
2836         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2837         struct mlx4_wqe_data_seg *scat;
2838         unsigned long flags;
2839         int err = 0;
2840         int nreq;
2841         int ind;
2842         int max_gs;
2843         int i;
2844
2845         max_gs = qp->rq.max_gs;
2846         spin_lock_irqsave(&qp->rq.lock, flags);
2847
2848         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2849
2850         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2851                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2852                         err = -ENOMEM;
2853                         *bad_wr = wr;
2854                         goto out;
2855                 }
2856
2857                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2858                         err = -EINVAL;
2859                         *bad_wr = wr;
2860                         goto out;
2861                 }
2862
2863                 scat = get_recv_wqe(qp, ind);
2864
2865                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2866                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2867                         ib_dma_sync_single_for_device(ibqp->device,
2868                                                       qp->sqp_proxy_rcv[ind].map,
2869                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2870                                                       DMA_FROM_DEVICE);
2871                         scat->byte_count =
2872                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2873                         /* use dma lkey from upper layer entry */
2874                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2875                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2876                         scat++;
2877                         max_gs--;
2878                 }
2879
2880                 for (i = 0; i < wr->num_sge; ++i)
2881                         __set_data_seg(scat + i, wr->sg_list + i);
2882
2883                 if (i < max_gs) {
2884                         scat[i].byte_count = 0;
2885                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2886                         scat[i].addr       = 0;
2887                 }
2888
2889                 qp->rq.wrid[ind] = wr->wr_id;
2890
2891                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2892         }
2893
2894 out:
2895         if (likely(nreq)) {
2896                 qp->rq.head += nreq;
2897
2898                 /*
2899                  * Make sure that descriptors are written before
2900                  * doorbell record.
2901                  */
2902                 wmb();
2903
2904                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2905         }
2906
2907         spin_unlock_irqrestore(&qp->rq.lock, flags);
2908
2909         return err;
2910 }
2911
2912 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2913 {
2914         switch (mlx4_state) {
2915         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2916         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2917         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2918         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2919         case MLX4_QP_STATE_SQ_DRAINING:
2920         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2921         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2922         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2923         default:                     return -1;
2924         }
2925 }
2926
2927 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2928 {
2929         switch (mlx4_mig_state) {
2930         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2931         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2932         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2933         default: return -1;
2934         }
2935 }
2936
2937 static int to_ib_qp_access_flags(int mlx4_flags)
2938 {
2939         int ib_flags = 0;
2940
2941         if (mlx4_flags & MLX4_QP_BIT_RRE)
2942                 ib_flags |= IB_ACCESS_REMOTE_READ;
2943         if (mlx4_flags & MLX4_QP_BIT_RWE)
2944                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2945         if (mlx4_flags & MLX4_QP_BIT_RAE)
2946                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2947
2948         return ib_flags;
2949 }
2950
2951 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2952                                 struct mlx4_qp_path *path)
2953 {
2954         struct mlx4_dev *dev = ibdev->dev;
2955         int is_eth;
2956
2957         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2958         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2959
2960         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2961                 return;
2962
2963         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2964                 IB_LINK_LAYER_ETHERNET;
2965         if (is_eth)
2966                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2967                 ((path->sched_queue & 4) << 1);
2968         else
2969                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2970
2971         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2972         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2973         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2974         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2975         if (ib_ah_attr->ah_flags) {
2976                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2977                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2978                 ib_ah_attr->grh.traffic_class =
2979                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2980                 ib_ah_attr->grh.flow_label =
2981                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2982                 memcpy(ib_ah_attr->grh.dgid.raw,
2983                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2984         }
2985 }
2986
2987 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2988                      struct ib_qp_init_attr *qp_init_attr)
2989 {
2990         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2991         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2992         struct mlx4_qp_context context;
2993         int mlx4_state;
2994         int err = 0;
2995
2996         mutex_lock(&qp->mutex);
2997
2998         if (qp->state == IB_QPS_RESET) {
2999                 qp_attr->qp_state = IB_QPS_RESET;
3000                 goto done;
3001         }
3002
3003         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3004         if (err) {
3005                 err = -EINVAL;
3006                 goto out;
3007         }
3008
3009         mlx4_state = be32_to_cpu(context.flags) >> 28;
3010
3011         qp->state                    = to_ib_qp_state(mlx4_state);
3012         qp_attr->qp_state            = qp->state;
3013         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3014         qp_attr->path_mig_state      =
3015                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3016         qp_attr->qkey                = be32_to_cpu(context.qkey);
3017         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3018         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3019         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3020         qp_attr->qp_access_flags     =
3021                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3022
3023         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3024                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3025                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3026                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3027                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3028         }
3029
3030         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3031         if (qp_attr->qp_state == IB_QPS_INIT)
3032                 qp_attr->port_num = qp->port;
3033         else
3034                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3035
3036         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3037         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3038
3039         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3040
3041         qp_attr->max_dest_rd_atomic =
3042                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3043         qp_attr->min_rnr_timer      =
3044                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3045         qp_attr->timeout            = context.pri_path.ackto >> 3;
3046         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3047         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3048         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3049
3050 done:
3051         qp_attr->cur_qp_state        = qp_attr->qp_state;
3052         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3053         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3054
3055         if (!ibqp->uobject) {
3056                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3057                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3058         } else {
3059                 qp_attr->cap.max_send_wr  = 0;
3060                 qp_attr->cap.max_send_sge = 0;
3061         }
3062
3063         /*
3064          * We don't support inline sends for kernel QPs (yet), and we
3065          * don't know what userspace's value should be.
3066          */
3067         qp_attr->cap.max_inline_data = 0;
3068
3069         qp_init_attr->cap            = qp_attr->cap;
3070
3071         qp_init_attr->create_flags = 0;
3072         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3073                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3074
3075         if (qp->flags & MLX4_IB_QP_LSO)
3076                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3077
3078         if (qp->flags & MLX4_IB_QP_NETIF)
3079                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3080
3081         qp_init_attr->sq_sig_type =
3082                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3083                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3084
3085 out:
3086         mutex_unlock(&qp->mutex);
3087         return err;
3088 }
3089