drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 #ifndef ETH_ALEN
  94 #define ETH_ALEN        6
  95 #endif
  96 static inline u64 mlx4_mac_to_u64(u8 *addr)
  97 {
  98         u64 mac = 0;
  99         int i;
 100
 101         for (i = 0; i < ETH_ALEN; i++) {
 102                 mac <<= 8;
 103                 mac |= addr[i];
 104         }
 105         return mac;
 106 }
 107
 108 static const __be32 mlx4_ib_opcode[] = {
 109         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 110         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 111         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 112         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 113         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 114         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 115         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 116         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 117         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 118         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 119         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 120         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 121         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 122         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 123 };
 124
 125 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 126 {
 127         return container_of(mqp, struct mlx4_ib_sqp, qp);
 128 }
 129
 130 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 131 {
 132         if (!mlx4_is_master(dev->dev))
 133                 return 0;
 134
 135         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 136                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 137                 8 * MLX4_MFUNC_MAX;
 138 }
 139
 140 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 141 {
 142         int proxy_sqp = 0;
 143         int real_sqp = 0;
 144         int i;
 145         /* PPF or Native -- real SQP */
 146         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 147                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 148                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 149         if (real_sqp)
 150                 return 1;
 151         /* VF or PF -- proxy SQP */
 152         if (mlx4_is_mfunc(dev->dev)) {
 153                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 154                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 155                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 156                                 proxy_sqp = 1;
 157                                 break;
 158                         }
 159                 }
 160         }
 161         return proxy_sqp;
 162 }
 163
 164 /* used for INIT/CLOSE port logic */
 165 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 166 {
 167         int proxy_qp0 = 0;
 168         int real_qp0 = 0;
 169         int i;
 170         /* PPF or Native -- real QP0 */
 171         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 172                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 173                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 174         if (real_qp0)
 175                 return 1;
 176         /* VF or PF -- proxy QP0 */
 177         if (mlx4_is_mfunc(dev->dev)) {
 178                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 179                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 180                                 proxy_qp0 = 1;
 181                                 break;
 182                         }
 183                 }
 184         }
 185         return proxy_qp0;
 186 }
 187
 188 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 189 {
 190         return mlx4_buf_offset(&qp->buf, offset);
 191 }
 192
 193 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 196 }
 197
 198 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 199 {
 200         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 201 }
 202
 203 /*
 204  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 205  * first four bytes of every 64 byte chunk with
 206  *     0x7FFFFFF | (invalid_ownership_value << 31).
 207  *
 208  * When the max work request size is less than or equal to the WQE
 209  * basic block size, as an optimization, we can stamp all WQEs with
 210  * 0xffffffff, and skip the very first chunk of each WQE.
 211  */
 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 213 {
 214         __be32 *wqe;
 215         int i;
 216         int s;
 217         int ind;
 218         void *buf;
 219         __be32 stamp;
 220         struct mlx4_wqe_ctrl_seg *ctrl;
 221
 222         if (qp->sq_max_wqes_per_wr > 1) {
 223                 s = roundup(size, 1U << qp->sq.wqe_shift);
 224                 for (i = 0; i < s; i += 64) {
 225                         ind = (i >> qp->sq.wqe_shift) + n;
 226                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 227                                                        cpu_to_be32(0xffffffff);
 228                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 229                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 230                         *wqe = stamp;
 231                 }
 232         } else {
 233                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 234                 s = (ctrl->fence_size & 0x3f) << 4;
 235                 for (i = 64; i < s; i += 64) {
 236                         wqe = buf + i;
 237                         *wqe = cpu_to_be32(0xffffffff);
 238                 }
 239         }
 240 }
 241
 242 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 243 {
 244         struct mlx4_wqe_ctrl_seg *ctrl;
 245         struct mlx4_wqe_inline_seg *inl;
 246         void *wqe;
 247         int s;
 248
 249         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 250         s = sizeof(struct mlx4_wqe_ctrl_seg);
 251
 252         if (qp->ibqp.qp_type == IB_QPT_UD) {
 253                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 254                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 255                 memset(dgram, 0, sizeof *dgram);
 256                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 257                 s += sizeof(struct mlx4_wqe_datagram_seg);
 258         }
 259
 260         /* Pad the remainder of the WQE with an inline data segment. */
 261         if (size > s) {
 262                 inl = wqe + s;
 263                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 264         }
 265         ctrl->srcrb_flags = 0;
 266         ctrl->fence_size = size / 16;
 267         /*
 268          * Make sure descriptor is fully written before setting ownership bit
 269          * (because HW can start executing as soon as we do).
 270          */
 271         wmb();
 272
 273         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 274                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 275
 276         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 277 }
 278
 279 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 280 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 281 {
 282         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 283         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 284                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 285                 ind += s;
 286         }
 287         return ind;
 288 }
 289
 290 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 291 {
 292         struct ib_event event;
 293         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 294
 295         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 296                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 297
 298         if (ibqp->event_handler) {
 299                 event.device     = ibqp->device;
 300                 event.element.qp = ibqp;
 301                 switch (type) {
 302                 case MLX4_EVENT_TYPE_PATH_MIG:
 303                         event.event = IB_EVENT_PATH_MIG;
 304                         break;
 305                 case MLX4_EVENT_TYPE_COMM_EST:
 306                         event.event = IB_EVENT_COMM_EST;
 307                         break;
 308                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 309                         event.event = IB_EVENT_SQ_DRAINED;
 310                         break;
 311                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 312                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 313                         break;
 314                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 315                         event.event = IB_EVENT_QP_FATAL;
 316                         break;
 317                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 318                         event.event = IB_EVENT_PATH_MIG_ERR;
 319                         break;
 320                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 321                         event.event = IB_EVENT_QP_REQ_ERR;
 322                         break;
 323                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 324                         event.event = IB_EVENT_QP_ACCESS_ERR;
 325                         break;
 326                 default:
 327                         pr_warn("Unexpected event type %d "
 328                                "on QP %06x\n", type, qp->qpn);
 329                         return;
 330                 }
 331
 332                 ibqp->event_handler(&event, ibqp->qp_context);
 333         }
 334 }
 335
 336 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 337 {
 338         /*
 339          * UD WQEs must have a datagram segment.
 340          * RC and UC WQEs might have a remote address segment.
 341          * MLX WQEs need two extra inline data segments (for the UD
 342          * header and space for the ICRC).
 343          */
 344         switch (type) {
 345         case MLX4_IB_QPT_UD:
 346                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 347                         sizeof (struct mlx4_wqe_datagram_seg) +
 348                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 349         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 350         case MLX4_IB_QPT_PROXY_SMI:
 351         case MLX4_IB_QPT_PROXY_GSI:
 352                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 353                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 354         case MLX4_IB_QPT_TUN_SMI_OWNER:
 355         case MLX4_IB_QPT_TUN_GSI:
 356                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 357                         sizeof (struct mlx4_wqe_datagram_seg);
 358
 359         case MLX4_IB_QPT_UC:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_raddr_seg);
 362         case MLX4_IB_QPT_RC:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         sizeof (struct mlx4_wqe_atomic_seg) +
 365                         sizeof (struct mlx4_wqe_raddr_seg);
 366         case MLX4_IB_QPT_SMI:
 367         case MLX4_IB_QPT_GSI:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 370                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 371                                            MLX4_INLINE_ALIGN) *
 372                               sizeof (struct mlx4_wqe_inline_seg),
 373                               sizeof (struct mlx4_wqe_data_seg)) +
 374                         ALIGN(4 +
 375                               sizeof (struct mlx4_wqe_inline_seg),
 376                               sizeof (struct mlx4_wqe_data_seg));
 377         default:
 378                 return sizeof (struct mlx4_wqe_ctrl_seg);
 379         }
 380 }
 381
 382 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 383                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 384 {
 385         /* Sanity check RQ size before proceeding */
 386         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 387             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 388                 return -EINVAL;
 389
 390         if (!has_rq) {
 391                 if (cap->max_recv_wr)
 392                         return -EINVAL;
 393
 394                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 395         } else {
 396                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 397                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 398                         return -EINVAL;
 399
 400                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 401                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 402                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 403         }
 404
 405         /* leave userspace return values as they were, so as not to break ABI */
 406         if (is_user) {
 407                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 408                 cap->max_recv_sge = qp->rq.max_gs;
 409         } else {
 410                 cap->max_recv_wr  = qp->rq.max_post =
 411                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 412                 cap->max_recv_sge = min(qp->rq.max_gs,
 413                                         min(dev->dev->caps.max_sq_sg,
 414                                             dev->dev->caps.max_rq_sg));
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 421                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 422 {
 423         int s;
 424
 425         /* Sanity check SQ size before proceeding */
 426         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 427             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 428             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 429             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 430                 return -EINVAL;
 431
 432         /*
 433          * For MLX transport we need 2 extra S/G entries:
 434          * one for the header and one for the checksum at the end
 435          */
 436         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 437              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 438             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 439                 return -EINVAL;
 440
 441         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 442                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 443                 send_wqe_overhead(type, qp->flags);
 444
 445         if (s > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * Hermon supports shrinking WQEs, such that a single work
 450          * request can include multiple units of 1 << wqe_shift.  This
 451          * way, work requests can differ in size, and do not have to
 452          * be a power of 2 in size, saving memory and speeding up send
 453          * WR posting.  Unfortunately, if we do this then the
 454          * wqe_index field in CQEs can't be used to look up the WR ID
 455          * anymore, so we do this only if selective signaling is off.
 456          *
 457          * Further, on 32-bit platforms, we can't use vmap() to make
 458          * the QP buffer virtually contiguous.  Thus we have to use
 459          * constant-sized WRs to make sure a WR is always fully within
 460          * a single page-sized chunk.
 461          *
 462          * Finally, we use NOP work requests to pad the end of the
 463          * work queue, to avoid wrap-around in the middle of WR.  We
 464          * set NEC bit to avoid getting completions with error for
 465          * these NOP WRs, but since NEC is only supported starting
 466          * with firmware 2.2.232, we use constant-sized WRs for older
 467          * firmware.
 468          *
 469          * And, since MLX QPs only support SEND, we use constant-sized
 470          * WRs in this case.
 471          *
 472          * We look for the smallest value of wqe_shift such that the
 473          * resulting number of wqes does not exceed device
 474          * capabilities.
 475          *
 476          * We set WQE size to at least 64 bytes, this way stamping
 477          * invalidates each WQE.
 478          */
 479         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 480             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 481             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 482             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 483                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 484                 qp->sq.wqe_shift = ilog2(64);
 485         else
 486                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 487
 488         for (;;) {
 489                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 490
 491                 /*
 492                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 493                  * allow HW to prefetch.
 494                  */
 495                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 496                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 497                                                     qp->sq_max_wqes_per_wr +
 498                                                     qp->sq_spare_wqes);
 499
 500                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 501                         break;
 502
 503                 if (qp->sq_max_wqes_per_wr <= 1)
 504                         return -EINVAL;
 505
 506                 ++qp->sq.wqe_shift;
 507         }
 508
 509         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 510                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 511                          send_wqe_overhead(type, qp->flags)) /
 512                 sizeof (struct mlx4_wqe_data_seg);
 513
 514         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 515                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 516         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 517                 qp->rq.offset = 0;
 518                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 519         } else {
 520                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 521                 qp->sq.offset = 0;
 522         }
 523
 524         cap->max_send_wr  = qp->sq.max_post =
 525                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 526         cap->max_send_sge = min(qp->sq.max_gs,
 527                                 min(dev->dev->caps.max_sq_sg,
 528                                     dev->dev->caps.max_rq_sg));
 529         /* We don't support inline sends for kernel QPs (yet) */
 530         cap->max_inline_data = 0;
 531
 532         return 0;
 533 }
 534
 535 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 536                             struct mlx4_ib_qp *qp,
 537                             struct mlx4_ib_create_qp *ucmd)
 538 {
 539         /* Sanity check SQ size before proceeding */
 540         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 541             ucmd->log_sq_stride >
 542                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 543             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 544                 return -EINVAL;
 545
 546         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 547         qp->sq.wqe_shift = ucmd->log_sq_stride;
 548
 549         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 550                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 551
 552         return 0;
 553 }
 554
 555 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 556 {
 557         int i;
 558
 559         qp->sqp_proxy_rcv =
 560                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 561                         GFP_KERNEL);
 562         if (!qp->sqp_proxy_rcv)
 563                 return -ENOMEM;
 564         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 565                 qp->sqp_proxy_rcv[i].addr =
 566                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 567                                 GFP_KERNEL);
 568                 if (!qp->sqp_proxy_rcv[i].addr)
 569                         goto err;
 570                 qp->sqp_proxy_rcv[i].map =
 571                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 572                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 573                                           DMA_FROM_DEVICE);
 574         }
 575         return 0;
 576
 577 err:
 578         while (i > 0) {
 579                 --i;
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586         qp->sqp_proxy_rcv = NULL;
 587         return -ENOMEM;
 588 }
 589
 590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 591 {
 592         int i;
 593
 594         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 595                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 596                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 597                                     DMA_FROM_DEVICE);
 598                 kfree(qp->sqp_proxy_rcv[i].addr);
 599         }
 600         kfree(qp->sqp_proxy_rcv);
 601 }
 602
 603 static int qp_has_rq(struct ib_qp_init_attr *attr)
 604 {
 605         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 606                 return 0;
 607
 608         return !attr->srq;
 609 }
 610
 611 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 612 {
 613         int i;
 614         for (i = 0; i < dev->caps.num_ports; i++) {
 615                 if (qpn == dev->caps.qp0_proxy[i])
 616                         return !!dev->caps.qp0_qkey[i];
 617         }
 618         return 0;
 619 }
 620
 621 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 622                             struct ib_qp_init_attr *init_attr,
 623                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
 624 {
 625         int qpn;
 626         int err;
 627         struct mlx4_ib_sqp *sqp;
 628         struct mlx4_ib_qp *qp;
 629         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 630
 631         /* When tunneling special qps, we use a plain UD qp */
 632         if (sqpn) {
 633                 if (mlx4_is_mfunc(dev->dev) &&
 634                     (!mlx4_is_master(dev->dev) ||
 635                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 636                         if (init_attr->qp_type == IB_QPT_GSI)
 637                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 638                         else {
 639                                 if (mlx4_is_master(dev->dev) ||
 640                                     qp0_enabled_vf(dev->dev, sqpn))
 641                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 642                                 else
 643                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 644                         }
 645                 }
 646                 qpn = sqpn;
 647                 /* add extra sg entry for tunneling */
 648                 init_attr->cap.max_recv_sge++;
 649         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 650                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 651                         container_of(init_attr,
 652                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 653                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 654                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 655                     !mlx4_is_master(dev->dev))
 656                         return -EINVAL;
 657                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 658                         qp_type = MLX4_IB_QPT_TUN_GSI;
 659                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 660                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 661                                              tnl_init->port))
 662                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 663                 else
 664                         qp_type = MLX4_IB_QPT_TUN_SMI;
 665                 /* we are definitely in the PPF here, since we are creating
 666                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 667                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 668                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 669                 sqpn = qpn;
 670         }
 671
 672         if (!*caller_qp) {
 673                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 674                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 675                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 676                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
 677                         if (!sqp)
 678                                 return -ENOMEM;
 679                         qp = &sqp->qp;
 680                         qp->pri.vid = 0xFFFF;
 681                         qp->alt.vid = 0xFFFF;
 682                 } else {
 683                         qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
 684                         if (!qp)
 685                                 return -ENOMEM;
 686                         qp->pri.vid = 0xFFFF;
 687                         qp->alt.vid = 0xFFFF;
 688                 }
 689         } else
 690                 qp = *caller_qp;
 691
 692         qp->mlx4_ib_qp_type = qp_type;
 693
 694         mutex_init(&qp->mutex);
 695         spin_lock_init(&qp->sq.lock);
 696         spin_lock_init(&qp->rq.lock);
 697         INIT_LIST_HEAD(&qp->gid_list);
 698         INIT_LIST_HEAD(&qp->steering_rules);
 699
 700         qp->state        = IB_QPS_RESET;
 701         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 702                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 703
 704         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 705         if (err)
 706                 goto err;
 707
 708         if (pd->uobject) {
 709                 struct mlx4_ib_create_qp ucmd;
 710
 711                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 712                         err = -EFAULT;
 713                         goto err;
 714                 }
 715
 716                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 717
 718                 err = set_user_sq_size(dev, qp, &ucmd);
 719                 if (err)
 720                         goto err;
 721
 722                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 723                                        qp->buf_size, 0, 0);
 724                 if (IS_ERR(qp->umem)) {
 725                         err = PTR_ERR(qp->umem);
 726                         goto err;
 727                 }
 728
 729                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 730                                     ilog2(qp->umem->page_size), &qp->mtt);
 731                 if (err)
 732                         goto err_buf;
 733
 734                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 735                 if (err)
 736                         goto err_mtt;
 737
 738                 if (qp_has_rq(init_attr)) {
 739                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 740                                                   ucmd.db_addr, &qp->db);
 741                         if (err)
 742                                 goto err_mtt;
 743                 }
 744         } else {
 745                 qp->sq_no_prefetch = 0;
 746
 747                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 748                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 749
 750                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 751                         qp->flags |= MLX4_IB_QP_LSO;
 752
 753                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 754                         if (dev->steering_support ==
 755                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 756                                 qp->flags |= MLX4_IB_QP_NETIF;
 757                         else
 758                                 goto err;
 759                 }
 760
 761                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 762                 if (err)
 763                         goto err;
 764
 765                 if (qp_has_rq(init_attr)) {
 766                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 767                         if (err)
 768                                 goto err;
 769
 770                         *qp->db.db = 0;
 771                 }
 772
 773                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 774                         err = -ENOMEM;
 775                         goto err_db;
 776                 }
 777
 778                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 779                                     &qp->mtt);
 780                 if (err)
 781                         goto err_buf;
 782
 783                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 784                 if (err)
 785                         goto err_mtt;
 786
 787                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 788                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 789
 790                 if (!qp->sq.wrid || !qp->rq.wrid) {
 791                         err = -ENOMEM;
 792                         goto err_wrid;
 793                 }
 794         }
 795
 796         if (sqpn) {
 797                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 798                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 799                         if (alloc_proxy_bufs(pd->device, qp)) {
 800                                 err = -ENOMEM;
 801                                 goto err_wrid;
 802                         }
 803                 }
 804         } else {
 805                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 806                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 807                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 808                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 809                 else
 810                         if (qp->flags & MLX4_IB_QP_NETIF)
 811                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 812                         else
 813                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 814                                                             &qpn);
 815                 if (err)
 816                         goto err_proxy;
 817         }
 818
 819         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 820         if (err)
 821                 goto err_qpn;
 822
 823         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 824                 qp->mqp.qpn |= (1 << 23);
 825
 826         /*
 827          * Hardware wants QPN written in big-endian order (after
 828          * shifting) for send doorbell.  Precompute this value to save
 829          * a little bit when posting sends.
 830          */
 831         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 832
 833         qp->mqp.event = mlx4_ib_qp_event;
 834         if (!*caller_qp)
 835                 *caller_qp = qp;
 836         return 0;
 837
 838 err_qpn:
 839         if (!sqpn) {
 840                 if (qp->flags & MLX4_IB_QP_NETIF)
 841                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 842                 else
 843                         mlx4_qp_release_range(dev->dev, qpn, 1);
 844         }
 845 err_proxy:
 846         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 847                 free_proxy_bufs(pd->device, qp);
 848 err_wrid:
 849         if (pd->uobject) {
 850                 if (qp_has_rq(init_attr))
 851                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 852         } else {
 853                 kfree(qp->sq.wrid);
 854                 kfree(qp->rq.wrid);
 855         }
 856
 857 err_mtt:
 858         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 859
 860 err_buf:
 861         if (pd->uobject)
 862                 ib_umem_release(qp->umem);
 863         else
 864                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 865
 866 err_db:
 867         if (!pd->uobject && qp_has_rq(init_attr))
 868                 mlx4_db_free(dev->dev, &qp->db);
 869
 870 err:
 871         if (!*caller_qp)
 872                 kfree(qp);
 873         return err;
 874 }
 875
 876 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 877 {
 878         switch (state) {
 879         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 880         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 881         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 882         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 883         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 884         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 885         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 886         default:                return -1;
 887         }
 888 }
 889
 890 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 891         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 892 {
 893         if (send_cq == recv_cq) {
 894                 spin_lock_irq(&send_cq->lock);
 895                 __acquire(&recv_cq->lock);
 896         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 897                 spin_lock_irq(&send_cq->lock);
 898                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 899         } else {
 900                 spin_lock_irq(&recv_cq->lock);
 901                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 902         }
 903 }
 904
 905 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 906         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 907 {
 908         if (send_cq == recv_cq) {
 909                 __release(&recv_cq->lock);
 910                 spin_unlock_irq(&send_cq->lock);
 911         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 912                 spin_unlock(&recv_cq->lock);
 913                 spin_unlock_irq(&send_cq->lock);
 914         } else {
 915                 spin_unlock(&send_cq->lock);
 916                 spin_unlock_irq(&recv_cq->lock);
 917         }
 918 }
 919
 920 static void del_gid_entries(struct mlx4_ib_qp *qp)
 921 {
 922         struct mlx4_ib_gid_entry *ge, *tmp;
 923
 924         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 925                 list_del(&ge->list);
 926                 kfree(ge);
 927         }
 928 }
 929
 930 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 931 {
 932         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 933                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 934         else
 935                 return to_mpd(qp->ibqp.pd);
 936 }
 937
 938 static void get_cqs(struct mlx4_ib_qp *qp,
 939                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 940 {
 941         switch (qp->ibqp.qp_type) {
 942         case IB_QPT_XRC_TGT:
 943                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 944                 *recv_cq = *send_cq;
 945                 break;
 946         case IB_QPT_XRC_INI:
 947                 *send_cq = to_mcq(qp->ibqp.send_cq);
 948                 *recv_cq = *send_cq;
 949                 break;
 950         default:
 951                 *send_cq = to_mcq(qp->ibqp.send_cq);
 952                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 953                 break;
 954         }
 955 }
 956
 957 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 958                               int is_user)
 959 {
 960         struct mlx4_ib_cq *send_cq, *recv_cq;
 961
 962         if (qp->state != IB_QPS_RESET) {
 963                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 964                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 965                         pr_warn("modify QP %06x to RESET failed.\n",
 966                                qp->mqp.qpn);
 967                 if (qp->pri.smac) {
 968                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
 969                         qp->pri.smac = 0;
 970                 }
 971                 if (qp->alt.smac) {
 972                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
 973                         qp->alt.smac = 0;
 974                 }
 975                 if (qp->pri.vid < 0x1000) {
 976                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
 977                         qp->pri.vid = 0xFFFF;
 978                         qp->pri.candidate_vid = 0xFFFF;
 979                         qp->pri.update_vid = 0;
 980                 }
 981                 if (qp->alt.vid < 0x1000) {
 982                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
 983                         qp->alt.vid = 0xFFFF;
 984                         qp->alt.candidate_vid = 0xFFFF;
 985                         qp->alt.update_vid = 0;
 986                 }
 987         }
 988
 989         get_cqs(qp, &send_cq, &recv_cq);
 990
 991         mlx4_ib_lock_cqs(send_cq, recv_cq);
 992
 993         if (!is_user) {
 994                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 995                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 996                 if (send_cq != recv_cq)
 997                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 998         }
 999
1000         mlx4_qp_remove(dev->dev, &qp->mqp);
1001
1002         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1003
1004         mlx4_qp_free(dev->dev, &qp->mqp);
1005
1006         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1007                 if (qp->flags & MLX4_IB_QP_NETIF)
1008                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1009                 else
1010                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1011         }
1012
1013         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1014
1015         if (is_user) {
1016                 if (qp->rq.wqe_cnt)
1017                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1018                                               &qp->db);
1019                 ib_umem_release(qp->umem);
1020         } else {
1021                 kfree(qp->sq.wrid);
1022                 kfree(qp->rq.wrid);
1023                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1024                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1025                         free_proxy_bufs(&dev->ib_dev, qp);
1026                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1027                 if (qp->rq.wqe_cnt)
1028                         mlx4_db_free(dev->dev, &qp->db);
1029         }
1030
1031         del_gid_entries(qp);
1032 }
1033
1034 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1035 {
1036         /* Native or PPF */
1037         if (!mlx4_is_mfunc(dev->dev) ||
1038             (mlx4_is_master(dev->dev) &&
1039              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1040                 return  dev->dev->phys_caps.base_sqpn +
1041                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1042                         attr->port_num - 1;
1043         }
1044         /* PF or VF -- creating proxies */
1045         if (attr->qp_type == IB_QPT_SMI)
1046                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1047         else
1048                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1049 }
1050
1051 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1052                                 struct ib_qp_init_attr *init_attr,
1053                                 struct ib_udata *udata)
1054 {
1055         struct mlx4_ib_qp *qp = NULL;
1056         int err;
1057         u16 xrcdn = 0;
1058
1059         /*
1060          * We only support LSO, vendor flag1, and multicast loopback blocking,
1061          * and only for kernel UD QPs.
1062          */
1063         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1064                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1065                                         MLX4_IB_SRIOV_TUNNEL_QP |
1066                                         MLX4_IB_SRIOV_SQP |
1067                                         MLX4_IB_QP_NETIF))
1068                 return ERR_PTR(-EINVAL);
1069
1070         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1071                 if (init_attr->qp_type != IB_QPT_UD)
1072                         return ERR_PTR(-EINVAL);
1073         }
1074
1075         if (init_attr->create_flags &&
1076             (udata ||
1077              ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
1078               init_attr->qp_type != IB_QPT_UD) ||
1079              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1080               init_attr->qp_type > IB_QPT_GSI)))
1081                 return ERR_PTR(-EINVAL);
1082
1083         switch (init_attr->qp_type) {
1084         case IB_QPT_XRC_TGT:
1085                 pd = to_mxrcd(init_attr->xrcd)->pd;
1086                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1087                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1088                 /* fall through */
1089         case IB_QPT_XRC_INI:
1090                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1091                         return ERR_PTR(-ENOSYS);
1092                 init_attr->recv_cq = init_attr->send_cq;
1093                 /* fall through */
1094         case IB_QPT_RC:
1095         case IB_QPT_UC:
1096         case IB_QPT_RAW_PACKET:
1097                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
1098                 if (!qp)
1099                         return ERR_PTR(-ENOMEM);
1100                 qp->pri.vid = 0xFFFF;
1101                 qp->alt.vid = 0xFFFF;
1102                 /* fall through */
1103         case IB_QPT_UD:
1104         {
1105                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1106                                        udata, 0, &qp);
1107                 if (err)
1108                         return ERR_PTR(err);
1109
1110                 qp->ibqp.qp_num = qp->mqp.qpn;
1111                 qp->xrcdn = xrcdn;
1112
1113                 break;
1114         }
1115         case IB_QPT_SMI:
1116         case IB_QPT_GSI:
1117         {
1118                 /* Userspace is not allowed to create special QPs: */
1119                 if (udata)
1120                         return ERR_PTR(-EINVAL);
1121
1122                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1123                                        get_sqp_num(to_mdev(pd->device), init_attr),
1124                                        &qp);
1125                 if (err)
1126                         return ERR_PTR(err);
1127
1128                 qp->port        = init_attr->port_num;
1129                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1130
1131                 break;
1132         }
1133         default:
1134                 /* Don't support raw QPs */
1135                 return ERR_PTR(-EINVAL);
1136         }
1137
1138         return &qp->ibqp;
1139 }
1140
1141 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1142 {
1143         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1144         struct mlx4_ib_qp *mqp = to_mqp(qp);
1145         struct mlx4_ib_pd *pd;
1146
1147         if (is_qp0(dev, mqp))
1148                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1149
1150         pd = get_pd(mqp);
1151         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1152
1153         if (is_sqp(dev, mqp))
1154                 kfree(to_msqp(mqp));
1155         else
1156                 kfree(mqp);
1157
1158         return 0;
1159 }
1160
1161 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1162 {
1163         switch (type) {
1164         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1165         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1166         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1167         case MLX4_IB_QPT_XRC_INI:
1168         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1169         case MLX4_IB_QPT_SMI:
1170         case MLX4_IB_QPT_GSI:
1171         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1172
1173         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1174         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1175                                                 MLX4_QP_ST_MLX : -1);
1176         case MLX4_IB_QPT_PROXY_SMI:
1177         case MLX4_IB_QPT_TUN_SMI:
1178         case MLX4_IB_QPT_PROXY_GSI:
1179         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1180                                                 MLX4_QP_ST_UD : -1);
1181         default:                        return -1;
1182         }
1183 }
1184
1185 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1186                                    int attr_mask)
1187 {
1188         u8 dest_rd_atomic;
1189         u32 access_flags;
1190         u32 hw_access_flags = 0;
1191
1192         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1193                 dest_rd_atomic = attr->max_dest_rd_atomic;
1194         else
1195                 dest_rd_atomic = qp->resp_depth;
1196
1197         if (attr_mask & IB_QP_ACCESS_FLAGS)
1198                 access_flags = attr->qp_access_flags;
1199         else
1200                 access_flags = qp->atomic_rd_en;
1201
1202         if (!dest_rd_atomic)
1203                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1204
1205         if (access_flags & IB_ACCESS_REMOTE_READ)
1206                 hw_access_flags |= MLX4_QP_BIT_RRE;
1207         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1208                 hw_access_flags |= MLX4_QP_BIT_RAE;
1209         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1210                 hw_access_flags |= MLX4_QP_BIT_RWE;
1211
1212         return cpu_to_be32(hw_access_flags);
1213 }
1214
1215 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1216                             int attr_mask)
1217 {
1218         if (attr_mask & IB_QP_PKEY_INDEX)
1219                 sqp->pkey_index = attr->pkey_index;
1220         if (attr_mask & IB_QP_QKEY)
1221                 sqp->qkey = attr->qkey;
1222         if (attr_mask & IB_QP_SQ_PSN)
1223                 sqp->send_psn = attr->sq_psn;
1224 }
1225
1226 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1227 {
1228         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1229 }
1230
1231 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1232                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1233                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1234 {
1235         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1236                 IB_LINK_LAYER_ETHERNET;
1237         int vidx;
1238         int smac_index;
1239         int err;
1240
1241
1242         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1243         path->rlid          = cpu_to_be16(ah->dlid);
1244         if (ah->static_rate) {
1245                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1246                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1247                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1248                         --path->static_rate;
1249         } else
1250                 path->static_rate = 0;
1251
1252         if (ah->ah_flags & IB_AH_GRH) {
1253                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1254                         pr_err("sgid_index (%u) too large. max is %d\n",
1255                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1256                         return -1;
1257                 }
1258
1259                 path->grh_mylmc |= 1 << 7;
1260                 path->mgid_index = ah->grh.sgid_index;
1261                 path->hop_limit  = ah->grh.hop_limit;
1262                 path->tclass_flowlabel =
1263                         cpu_to_be32((ah->grh.traffic_class << 20) |
1264                                     (ah->grh.flow_label));
1265                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1266         }
1267
1268         if (is_eth) {
1269                 if (!(ah->ah_flags & IB_AH_GRH))
1270                         return -1;
1271
1272                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1273                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1274
1275                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1276                 if (vlan_tag < 0x1000) {
1277                         if (smac_info->vid < 0x1000) {
1278                                 /* both valid vlan ids */
1279                                 if (smac_info->vid != vlan_tag) {
1280                                         /* different VIDs.  unreg old and reg new */
1281                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1282                                         if (err)
1283                                                 return err;
1284                                         smac_info->candidate_vid = vlan_tag;
1285                                         smac_info->candidate_vlan_index = vidx;
1286                                         smac_info->candidate_vlan_port = port;
1287                                         smac_info->update_vid = 1;
1288                                         path->vlan_index = vidx;
1289                                 } else {
1290                                         path->vlan_index = smac_info->vlan_index;
1291                                 }
1292                         } else {
1293                                 /* no current vlan tag in qp */
1294                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1295                                 if (err)
1296                                         return err;
1297                                 smac_info->candidate_vid = vlan_tag;
1298                                 smac_info->candidate_vlan_index = vidx;
1299                                 smac_info->candidate_vlan_port = port;
1300                                 smac_info->update_vid = 1;
1301                                 path->vlan_index = vidx;
1302                         }
1303                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1304                         path->fl = 1 << 6;
1305                 } else {
1306                         /* have current vlan tag. unregister it at modify-qp success */
1307                         if (smac_info->vid < 0x1000) {
1308                                 smac_info->candidate_vid = 0xFFFF;
1309                                 smac_info->update_vid = 1;
1310                         }
1311                 }
1312
1313                 /* get smac_index for RoCE use.
1314                  * If no smac was yet assigned, register one.
1315                  * If one was already assigned, but the new mac differs,
1316                  * unregister the old one and register the new one.
1317                 */
1318                 if (!smac_info->smac || smac_info->smac != smac) {
1319                         /* register candidate now, unreg if needed, after success */
1320                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1321                         if (smac_index >= 0) {
1322                                 smac_info->candidate_smac_index = smac_index;
1323                                 smac_info->candidate_smac = smac;
1324                                 smac_info->candidate_smac_port = port;
1325                         } else {
1326                                 return -EINVAL;
1327                         }
1328                 } else {
1329                         smac_index = smac_info->smac_index;
1330                 }
1331
1332                 memcpy(path->dmac, ah->dmac, 6);
1333                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1334                 /* put MAC table smac index for IBoE */
1335                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1336         } else {
1337                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1338                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1345                          enum ib_qp_attr_mask qp_attr_mask,
1346                          struct mlx4_ib_qp *mqp,
1347                          struct mlx4_qp_path *path, u8 port)
1348 {
1349         return _mlx4_set_path(dev, &qp->ah_attr,
1350                               mlx4_mac_to_u64((u8 *)qp->smac),
1351                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1352                               path, &mqp->pri, port);
1353 }
1354
1355 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1356                              const struct ib_qp_attr *qp,
1357                              enum ib_qp_attr_mask qp_attr_mask,
1358                              struct mlx4_ib_qp *mqp,
1359                              struct mlx4_qp_path *path, u8 port)
1360 {
1361         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1362                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1363                               (qp_attr_mask & IB_QP_ALT_VID) ?
1364                               qp->alt_vlan_id : 0xffff,
1365                               path, &mqp->alt, port);
1366 }
1367
1368 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1369 {
1370         struct mlx4_ib_gid_entry *ge, *tmp;
1371
1372         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1373                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1374                         ge->added = 1;
1375                         ge->port = qp->port;
1376                 }
1377         }
1378 }
1379
1380 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1381                                     struct mlx4_qp_context *context)
1382 {
1383         struct net_device *ndev;
1384         u64 u64_mac;
1385         int smac_index;
1386
1387
1388         ndev = dev->iboe.netdevs[qp->port - 1];
1389         if (ndev) {
1390                 smac = ndev->dev_addr;
1391                 u64_mac = mlx4_mac_to_u64(smac);
1392         } else {
1393                 u64_mac = dev->dev->caps.def_mac[qp->port];
1394         }
1395
1396         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1397         if (!qp->pri.smac) {
1398                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1399                 if (smac_index >= 0) {
1400                         qp->pri.candidate_smac_index = smac_index;
1401                         qp->pri.candidate_smac = u64_mac;
1402                         qp->pri.candidate_smac_port = qp->port;
1403                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1404                 } else {
1405                         return -ENOENT;
1406                 }
1407         }
1408         return 0;
1409 }
1410
1411 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1412                                const struct ib_qp_attr *attr, int attr_mask,
1413                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1414 {
1415         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1416         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1417         struct mlx4_ib_pd *pd;
1418         struct mlx4_ib_cq *send_cq, *recv_cq;
1419         struct mlx4_qp_context *context;
1420         enum mlx4_qp_optpar optpar = 0;
1421         int sqd_event;
1422         int steer_qp = 0;
1423         int err = -EINVAL;
1424
1425         context = kzalloc(sizeof *context, GFP_KERNEL);
1426         if (!context)
1427                 return -ENOMEM;
1428
1429         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1430                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1431
1432         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1433                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1434         else {
1435                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1436                 switch (attr->path_mig_state) {
1437                 case IB_MIG_MIGRATED:
1438                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1439                         break;
1440                 case IB_MIG_REARM:
1441                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1442                         break;
1443                 case IB_MIG_ARMED:
1444                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1445                         break;
1446                 }
1447         }
1448
1449         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1450                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1451         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1452                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1453         else if (ibqp->qp_type == IB_QPT_UD) {
1454                 if (qp->flags & MLX4_IB_QP_LSO)
1455                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1456                                               ilog2(dev->dev->caps.max_gso_sz);
1457                 else
1458                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1459         } else if (attr_mask & IB_QP_PATH_MTU) {
1460                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1461                         pr_err("path MTU (%u) is invalid\n",
1462                                attr->path_mtu);
1463                         goto out;
1464                 }
1465                 context->mtu_msgmax = (attr->path_mtu << 5) |
1466                         ilog2(dev->dev->caps.max_msg_sz);
1467         }
1468
1469         if (qp->rq.wqe_cnt)
1470                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1471         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1472
1473         if (qp->sq.wqe_cnt)
1474                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1475         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1476
1477         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1478                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1479                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1480                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1481                         context->param3 |= cpu_to_be32(1 << 30);
1482         }
1483
1484         if (qp->ibqp.uobject)
1485                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1486         else
1487                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1488
1489         if (attr_mask & IB_QP_DEST_QPN)
1490                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1491
1492         if (attr_mask & IB_QP_PORT) {
1493                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1494                     !(attr_mask & IB_QP_AV)) {
1495                         mlx4_set_sched(&context->pri_path, attr->port_num);
1496                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1497                 }
1498         }
1499
1500         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1501                 if (dev->counters[qp->port - 1] != -1) {
1502                         context->pri_path.counter_index =
1503                                                 dev->counters[qp->port - 1];
1504                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1505                 } else
1506                         context->pri_path.counter_index = 0xff;
1507
1508                 if (qp->flags & MLX4_IB_QP_NETIF) {
1509                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1510                         steer_qp = 1;
1511                 }
1512         }
1513
1514         if (attr_mask & IB_QP_PKEY_INDEX) {
1515                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1516                         context->pri_path.disable_pkey_check = 0x40;
1517                 context->pri_path.pkey_index = attr->pkey_index;
1518                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1519         }
1520
1521         if (attr_mask & IB_QP_AV) {
1522                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1523                                   attr_mask & IB_QP_PORT ?
1524                                   attr->port_num : qp->port))
1525                         goto out;
1526
1527                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1528                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1529         }
1530
1531         if (attr_mask & IB_QP_TIMEOUT) {
1532                 context->pri_path.ackto |= attr->timeout << 3;
1533                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1534         }
1535
1536         if (attr_mask & IB_QP_ALT_PATH) {
1537                 if (attr->alt_port_num == 0 ||
1538                     attr->alt_port_num > dev->dev->caps.num_ports)
1539                         goto out;
1540
1541                 if (attr->alt_pkey_index >=
1542                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1543                         goto out;
1544
1545                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1546                                       &context->alt_path,
1547                                       attr->alt_port_num))
1548                         goto out;
1549
1550                 context->alt_path.pkey_index = attr->alt_pkey_index;
1551                 context->alt_path.ackto = attr->alt_timeout << 3;
1552                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1553         }
1554
1555         pd = get_pd(qp);
1556         get_cqs(qp, &send_cq, &recv_cq);
1557         context->pd       = cpu_to_be32(pd->pdn);
1558         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1559         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1560         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1561
1562         /* Set "fast registration enabled" for all kernel QPs */
1563         if (!qp->ibqp.uobject)
1564                 context->params1 |= cpu_to_be32(1 << 11);
1565
1566         if (attr_mask & IB_QP_RNR_RETRY) {
1567                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1568                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1569         }
1570
1571         if (attr_mask & IB_QP_RETRY_CNT) {
1572                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1573                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1574         }
1575
1576         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1577                 if (attr->max_rd_atomic)
1578                         context->params1 |=
1579                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1580                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1581         }
1582
1583         if (attr_mask & IB_QP_SQ_PSN)
1584                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1585
1586         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1587                 if (attr->max_dest_rd_atomic)
1588                         context->params2 |=
1589                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1590                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1591         }
1592
1593         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1594                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1595                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1596         }
1597
1598         if (ibqp->srq)
1599                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1600
1601         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1602                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1603                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1604         }
1605         if (attr_mask & IB_QP_RQ_PSN)
1606                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1607
1608         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1609         if (attr_mask & IB_QP_QKEY) {
1610                 if (qp->mlx4_ib_qp_type &
1611                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1612                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1613                 else {
1614                         if (mlx4_is_mfunc(dev->dev) &&
1615                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1616                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1617                             MLX4_RESERVED_QKEY_BASE) {
1618                                 pr_err("Cannot use reserved QKEY"
1619                                        " 0x%x (range 0xffff0000..0xffffffff"
1620                                        " is reserved)\n", attr->qkey);
1621                                 err = -EINVAL;
1622                                 goto out;
1623                         }
1624                         context->qkey = cpu_to_be32(attr->qkey);
1625                 }
1626                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1627         }
1628
1629         if (ibqp->srq)
1630                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1631
1632         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1633                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1634
1635         if (cur_state == IB_QPS_INIT &&
1636             new_state == IB_QPS_RTR  &&
1637             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1638              ibqp->qp_type == IB_QPT_UD ||
1639              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1640                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1641                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1642                     qp->mlx4_ib_qp_type &
1643                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1644                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1645                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1646                                 context->pri_path.fl = 0x80;
1647                 } else {
1648                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1649                                 context->pri_path.fl = 0x80;
1650                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1651                 }
1652                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1653                     IB_LINK_LAYER_ETHERNET) {
1654                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1655                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1656                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1657                         /* handle smac_index */
1658                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1659                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1660                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1661                                 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1662                                 if (err)
1663                                         return -EINVAL;
1664                         }
1665                 }
1666         }
1667
1668         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
1669                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1670                                         MLX4_IB_LINK_TYPE_ETH;
1671
1672         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1673                 int is_eth = rdma_port_get_link_layer(
1674                                 &dev->ib_dev, qp->port) ==
1675                                 IB_LINK_LAYER_ETHERNET;
1676                 if (is_eth) {
1677                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1678                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1679                 }
1680         }
1681
1682
1683         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1684             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1685                 sqd_event = 1;
1686         else
1687                 sqd_event = 0;
1688
1689         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1690                 context->rlkey |= (1 << 4);
1691
1692         /*
1693          * Before passing a kernel QP to the HW, make sure that the
1694          * ownership bits of the send queue are set and the SQ
1695          * headroom is stamped so that the hardware doesn't start
1696          * processing stale work requests.
1697          */
1698         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1699                 struct mlx4_wqe_ctrl_seg *ctrl;
1700                 int i;
1701
1702                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1703                         ctrl = get_send_wqe(qp, i);
1704                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1705                         if (qp->sq_max_wqes_per_wr == 1)
1706                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1707
1708                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1709                 }
1710         }
1711
1712         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1713                              to_mlx4_state(new_state), context, optpar,
1714                              sqd_event, &qp->mqp);
1715         if (err)
1716                 goto out;
1717
1718         qp->state = new_state;
1719
1720         if (attr_mask & IB_QP_ACCESS_FLAGS)
1721                 qp->atomic_rd_en = attr->qp_access_flags;
1722         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1723                 qp->resp_depth = attr->max_dest_rd_atomic;
1724         if (attr_mask & IB_QP_PORT) {
1725                 qp->port = attr->port_num;
1726                 update_mcg_macs(dev, qp);
1727         }
1728         if (attr_mask & IB_QP_ALT_PATH)
1729                 qp->alt_port = attr->alt_port_num;
1730
1731         if (is_sqp(dev, qp))
1732                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1733
1734         /*
1735          * If we moved QP0 to RTR, bring the IB link up; if we moved
1736          * QP0 to RESET or ERROR, bring the link back down.
1737          */
1738         if (is_qp0(dev, qp)) {
1739                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1740                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1741                                 pr_warn("INIT_PORT failed for port %d\n",
1742                                        qp->port);
1743
1744                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1745                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1746                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1747         }
1748
1749         /*
1750          * If we moved a kernel QP to RESET, clean up all old CQ
1751          * entries and reinitialize the QP.
1752          */
1753         if (new_state == IB_QPS_RESET) {
1754                 if (!ibqp->uobject) {
1755                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1756                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1757                         if (send_cq != recv_cq)
1758                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1759
1760                         qp->rq.head = 0;
1761                         qp->rq.tail = 0;
1762                         qp->sq.head = 0;
1763                         qp->sq.tail = 0;
1764                         qp->sq_next_wqe = 0;
1765                         if (qp->rq.wqe_cnt)
1766                                 *qp->db.db  = 0;
1767
1768                         if (qp->flags & MLX4_IB_QP_NETIF)
1769                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1770                 }
1771                 if (qp->pri.smac) {
1772                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1773                         qp->pri.smac = 0;
1774                 }
1775                 if (qp->alt.smac) {
1776                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1777                         qp->alt.smac = 0;
1778                 }
1779                 if (qp->pri.vid < 0x1000) {
1780                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1781                         qp->pri.vid = 0xFFFF;
1782                         qp->pri.candidate_vid = 0xFFFF;
1783                         qp->pri.update_vid = 0;
1784                 }
1785
1786                 if (qp->alt.vid < 0x1000) {
1787                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1788                         qp->alt.vid = 0xFFFF;
1789                         qp->alt.candidate_vid = 0xFFFF;
1790                         qp->alt.update_vid = 0;
1791                 }
1792         }
1793 out:
1794         if (err && steer_qp)
1795                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1796         kfree(context);
1797         if (qp->pri.candidate_smac) {
1798                 if (err) {
1799                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1800                 } else {
1801                         if (qp->pri.smac)
1802                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1803                         qp->pri.smac = qp->pri.candidate_smac;
1804                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1805                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1806                 }
1807                 qp->pri.candidate_smac = 0;
1808                 qp->pri.candidate_smac_index = 0;
1809                 qp->pri.candidate_smac_port = 0;
1810         }
1811         if (qp->alt.candidate_smac) {
1812                 if (err) {
1813                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1814                 } else {
1815                         if (qp->alt.smac)
1816                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1817                         qp->alt.smac = qp->alt.candidate_smac;
1818                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1819                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1820                 }
1821                 qp->alt.candidate_smac = 0;
1822                 qp->alt.candidate_smac_index = 0;
1823                 qp->alt.candidate_smac_port = 0;
1824         }
1825
1826         if (qp->pri.update_vid) {
1827                 if (err) {
1828                         if (qp->pri.candidate_vid < 0x1000)
1829                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1830                                                      qp->pri.candidate_vid);
1831                 } else {
1832                         if (qp->pri.vid < 0x1000)
1833                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1834                                                      qp->pri.vid);
1835                         qp->pri.vid = qp->pri.candidate_vid;
1836                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1837                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1838                 }
1839                 qp->pri.candidate_vid = 0xFFFF;
1840                 qp->pri.update_vid = 0;
1841         }
1842
1843         if (qp->alt.update_vid) {
1844                 if (err) {
1845                         if (qp->alt.candidate_vid < 0x1000)
1846                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1847                                                      qp->alt.candidate_vid);
1848                 } else {
1849                         if (qp->alt.vid < 0x1000)
1850                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1851                                                      qp->alt.vid);
1852                         qp->alt.vid = qp->alt.candidate_vid;
1853                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1854                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1855                 }
1856                 qp->alt.candidate_vid = 0xFFFF;
1857                 qp->alt.update_vid = 0;
1858         }
1859
1860         return err;
1861 }
1862
1863 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1864                       int attr_mask, struct ib_udata *udata)
1865 {
1866         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1867         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1868         enum ib_qp_state cur_state, new_state;
1869         int err = -EINVAL;
1870         int ll;
1871         mutex_lock(&qp->mutex);
1872
1873         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1874         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1875
1876         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1877                 ll = IB_LINK_LAYER_UNSPECIFIED;
1878         } else {
1879                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1880                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1881         }
1882
1883         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1884                                 attr_mask, ll)) {
1885                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1886                          "for transition %d to %d. qp_type %d,"
1887                          " attr_mask 0x%x\n",
1888                          ibqp->qp_num, cur_state, new_state,
1889                          ibqp->qp_type, attr_mask);
1890                 goto out;
1891         }
1892
1893         if ((attr_mask & IB_QP_PORT) &&
1894             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1895                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1896                          "for transition %d to %d. qp_type %d\n",
1897                          ibqp->qp_num, attr->port_num, cur_state,
1898                          new_state, ibqp->qp_type);
1899                 goto out;
1900         }
1901
1902         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1903             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1904              IB_LINK_LAYER_ETHERNET))
1905                 goto out;
1906
1907         if (attr_mask & IB_QP_PKEY_INDEX) {
1908                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1909                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1910                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1911                                  "for transition %d to %d. qp_type %d\n",
1912                                  ibqp->qp_num, attr->pkey_index, cur_state,
1913                                  new_state, ibqp->qp_type);
1914                         goto out;
1915                 }
1916         }
1917
1918         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1919             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1920                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1921                          "Transition %d to %d. qp_type %d\n",
1922                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1923                          new_state, ibqp->qp_type);
1924                 goto out;
1925         }
1926
1927         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1928             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1929                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1930                          "Transition %d to %d. qp_type %d\n",
1931                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1932                          new_state, ibqp->qp_type);
1933                 goto out;
1934         }
1935
1936         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1937                 err = 0;
1938                 goto out;
1939         }
1940
1941         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1942
1943 out:
1944         mutex_unlock(&qp->mutex);
1945         return err;
1946 }
1947
1948 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
1949 {
1950         int i;
1951         for (i = 0; i < dev->caps.num_ports; i++) {
1952                 if (qpn == dev->caps.qp0_proxy[i] ||
1953                     qpn == dev->caps.qp0_tunnel[i]) {
1954                         *qkey = dev->caps.qp0_qkey[i];
1955                         return 0;
1956                 }
1957         }
1958         return -EINVAL;
1959 }
1960
1961 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1962                                   struct ib_send_wr *wr,
1963                                   void *wqe, unsigned *mlx_seg_len)
1964 {
1965         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1966         struct ib_device *ib_dev = &mdev->ib_dev;
1967         struct mlx4_wqe_mlx_seg *mlx = wqe;
1968         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1969         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1970         u16 pkey;
1971         u32 qkey;
1972         int send_size;
1973         int header_size;
1974         int spc;
1975         int i;
1976
1977         if (wr->opcode != IB_WR_SEND)
1978                 return -EINVAL;
1979
1980         send_size = 0;
1981
1982         for (i = 0; i < wr->num_sge; ++i)
1983                 send_size += wr->sg_list[i].length;
1984
1985         /* for proxy-qp0 sends, need to add in size of tunnel header */
1986         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1987         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1988                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1989
1990         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1991
1992         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1993                 sqp->ud_header.lrh.service_level =
1994                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1995                 sqp->ud_header.lrh.destination_lid =
1996                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1997                 sqp->ud_header.lrh.source_lid =
1998                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1999         }
2000
2001         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2002
2003         /* force loopback */
2004         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2005         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2006
2007         sqp->ud_header.lrh.virtual_lane    = 0;
2008         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2009         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2010         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2011         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2012                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2013         else
2014                 sqp->ud_header.bth.destination_qpn =
2015                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2016
2017         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2018         if (mlx4_is_master(mdev->dev)) {
2019                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2020                         return -EINVAL;
2021         } else {
2022                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2023                         return -EINVAL;
2024         }
2025         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2026         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2027
2028         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2029         sqp->ud_header.immediate_present = 0;
2030
2031         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2032
2033         /*
2034          * Inline data segments may not cross a 64 byte boundary.  If
2035          * our UD header is bigger than the space available up to the
2036          * next 64 byte boundary in the WQE, use two inline data
2037          * segments to hold the UD header.
2038          */
2039         spc = MLX4_INLINE_ALIGN -
2040               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2041         if (header_size <= spc) {
2042                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2043                 memcpy(inl + 1, sqp->header_buf, header_size);
2044                 i = 1;
2045         } else {
2046                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2047                 memcpy(inl + 1, sqp->header_buf, spc);
2048
2049                 inl = (void *) (inl + 1) + spc;
2050                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2051                 /*
2052                  * Need a barrier here to make sure all the data is
2053                  * visible before the byte_count field is set.
2054                  * Otherwise the HCA prefetcher could grab the 64-byte
2055                  * chunk with this inline segment and get a valid (!=
2056                  * 0xffffffff) byte count but stale data, and end up
2057                  * generating a packet with bad headers.
2058                  *
2059                  * The first inline segment's byte_count field doesn't
2060                  * need a barrier, because it comes after a
2061                  * control/MLX segment and therefore is at an offset
2062                  * of 16 mod 64.
2063                  */
2064                 wmb();
2065                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2066                 i = 2;
2067         }
2068
2069         *mlx_seg_len =
2070         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2071         return 0;
2072 }
2073
2074 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2075                             void *wqe, unsigned *mlx_seg_len)
2076 {
2077         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2078         struct mlx4_wqe_mlx_seg *mlx = wqe;
2079         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2080         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2081         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2082         union ib_gid sgid;
2083         u16 pkey;
2084         int send_size;
2085         int header_size;
2086         int spc;
2087         int i;
2088         int err = 0;
2089         u16 vlan = 0xffff;
2090         bool is_eth;
2091         bool is_vlan = false;
2092         bool is_grh;
2093
2094         send_size = 0;
2095         for (i = 0; i < wr->num_sge; ++i)
2096                 send_size += wr->sg_list[i].length;
2097
2098         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2099         is_grh = mlx4_ib_ah_grh_present(ah);
2100         if (is_eth) {
2101                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2102                         /* When multi-function is enabled, the ib_core gid
2103                          * indexes don't necessarily match the hw ones, so
2104                          * we must use our own cache */
2105                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2106                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2107                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2108                         if (err)
2109                                 return err;
2110                 } else  {
2111                         err = ib_get_cached_gid(ib_dev,
2112                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2113                                                 ah->av.ib.gid_index, &sgid);
2114                         if (err)
2115                                 return err;
2116                 }
2117
2118                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2119                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2120                         is_vlan = 1;
2121                 }
2122         }
2123         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2124
2125         if (!is_eth) {
2126                 sqp->ud_header.lrh.service_level =
2127                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2128                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2129                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2130         }
2131
2132         if (is_grh) {
2133                 sqp->ud_header.grh.traffic_class =
2134                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2135                 sqp->ud_header.grh.flow_label    =
2136                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2137                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2138                 if (is_eth)
2139                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2140                 else {
2141                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2142                         /* When multi-function is enabled, the ib_core gid
2143                          * indexes don't necessarily match the hw ones, so
2144                          * we must use our own cache */
2145                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2146                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2147                                                        subnet_prefix;
2148                         sqp->ud_header.grh.source_gid.global.interface_id =
2149                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2150                                                guid_cache[ah->av.ib.gid_index];
2151                 } else
2152                         ib_get_cached_gid(ib_dev,
2153                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2154                                           ah->av.ib.gid_index,
2155                                           &sqp->ud_header.grh.source_gid);
2156                 }
2157                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2158                        ah->av.ib.dgid, 16);
2159         }
2160
2161         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2162
2163         if (!is_eth) {
2164                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2165                                           (sqp->ud_header.lrh.destination_lid ==
2166                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2167                                           (sqp->ud_header.lrh.service_level << 8));
2168                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2169                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2170                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2171         }
2172
2173         switch (wr->opcode) {
2174         case IB_WR_SEND:
2175                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2176                 sqp->ud_header.immediate_present = 0;
2177                 break;
2178         case IB_WR_SEND_WITH_IMM:
2179                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2180                 sqp->ud_header.immediate_present = 1;
2181                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
2182                 break;
2183         default:
2184                 return -EINVAL;
2185         }
2186
2187         if (is_eth) {
2188                 u8 *smac;
2189                 struct in6_addr in6;
2190
2191                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2192
2193                 mlx->sched_prio = cpu_to_be16(pcp);
2194
2195                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2196                 /* FIXME: cache smac value? */
2197                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2198                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2199                 memcpy(&in6, sgid.raw, sizeof(in6));
2200
2201                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev))
2202                         smac = to_mdev(sqp->qp.ibqp.device)->
2203                                 iboe.netdevs[sqp->qp.port - 1]->dev_addr;
2204                 else    /* use the src mac of the tunnel */
2205                         smac = ah->av.eth.s_mac;
2206                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
2207                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2208                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2209                 if (!is_vlan) {
2210                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2211                 } else {
2212                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2213                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2214                 }
2215         } else {
2216                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2217                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2218                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2219         }
2220         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2221         if (!sqp->qp.ibqp.qp_num)
2222                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2223         else
2224                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2225         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2226         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2227         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2228         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2229                                                sqp->qkey : wr->wr.ud.remote_qkey);
2230         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2231
2232         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2233
2234         if (0) {
2235                 pr_err("built UD header of size %d:\n", header_size);
2236                 for (i = 0; i < header_size / 4; ++i) {
2237                         if (i % 8 == 0)
2238                                 pr_err("  [%02x] ", i * 4);
2239                         pr_cont(" %08x",
2240                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2241                         if ((i + 1) % 8 == 0)
2242                                 pr_cont("\n");
2243                 }
2244                 pr_err("\n");
2245         }
2246
2247         /*
2248          * Inline data segments may not cross a 64 byte boundary.  If
2249          * our UD header is bigger than the space available up to the
2250          * next 64 byte boundary in the WQE, use two inline data
2251          * segments to hold the UD header.
2252          */
2253         spc = MLX4_INLINE_ALIGN -
2254                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2255         if (header_size <= spc) {
2256                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2257                 memcpy(inl + 1, sqp->header_buf, header_size);
2258                 i = 1;
2259         } else {
2260                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2261                 memcpy(inl + 1, sqp->header_buf, spc);
2262
2263                 inl = (void *) (inl + 1) + spc;
2264                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2265                 /*
2266                  * Need a barrier here to make sure all the data is
2267                  * visible before the byte_count field is set.
2268                  * Otherwise the HCA prefetcher could grab the 64-byte
2269                  * chunk with this inline segment and get a valid (!=
2270                  * 0xffffffff) byte count but stale data, and end up
2271                  * generating a packet with bad headers.
2272                  *
2273                  * The first inline segment's byte_count field doesn't
2274                  * need a barrier, because it comes after a
2275                  * control/MLX segment and therefore is at an offset
2276                  * of 16 mod 64.
2277                  */
2278                 wmb();
2279                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2280                 i = 2;
2281         }
2282
2283         *mlx_seg_len =
2284                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2285         return 0;
2286 }
2287
2288 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2289 {
2290         unsigned cur;
2291         struct mlx4_ib_cq *cq;
2292
2293         cur = wq->head - wq->tail;
2294         if (likely(cur + nreq < wq->max_post))
2295                 return 0;
2296
2297         cq = to_mcq(ib_cq);
2298         spin_lock(&cq->lock);
2299         cur = wq->head - wq->tail;
2300         spin_unlock(&cq->lock);
2301
2302         return cur + nreq >= wq->max_post;
2303 }
2304
2305 static __be32 convert_access(int acc)
2306 {
2307         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2308                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2309                (acc & IB_ACCESS_REMOTE_WRITE  ?
2310                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2311                (acc & IB_ACCESS_REMOTE_READ   ?
2312                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2313                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2314                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2315 }
2316
2317 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2318 {
2319         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2320         int i;
2321
2322         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2323                 mfrpl->mapped_page_list[i] =
2324                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2325                                     MLX4_MTT_FLAG_PRESENT);
2326
2327         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2328         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2329         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2330         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2331         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2332         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2333         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2334         fseg->reserved[0]       = 0;
2335         fseg->reserved[1]       = 0;
2336 }
2337
2338 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2339 {
2340         bseg->flags1 =
2341                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2342                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2343                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2344                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2345         bseg->flags2 = 0;
2346         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2347                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2348         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2349                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2350         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2351         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2352         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2353         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2354 }
2355
2356 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2357 {
2358         memset(iseg, 0, sizeof(*iseg));
2359         iseg->mem_key = cpu_to_be32(rkey);
2360 }
2361
2362 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2363                                           u64 remote_addr, u32 rkey)
2364 {
2365         rseg->raddr    = cpu_to_be64(remote_addr);
2366         rseg->rkey     = cpu_to_be32(rkey);
2367         rseg->reserved = 0;
2368 }
2369
2370 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2371 {
2372         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2373                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2374                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2375         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2376                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2377                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2378         } else {
2379                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2380                 aseg->compare  = 0;
2381         }
2382
2383 }
2384
2385 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2386                                   struct ib_send_wr *wr)
2387 {
2388         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2389         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2390         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2391         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2392 }
2393
2394 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2395                              struct ib_send_wr *wr)
2396 {
2397         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2398         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2399         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2400         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2401         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2402 }
2403
2404 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2405                                     struct mlx4_wqe_datagram_seg *dseg,
2406                                     struct ib_send_wr *wr,
2407                                     enum mlx4_ib_qp_type qpt)
2408 {
2409         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2410         struct mlx4_av sqp_av = {0};
2411         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2412
2413         /* force loopback */
2414         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2415         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2416         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2417                         cpu_to_be32(0xf0000000);
2418
2419         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2420         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2421                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2422         else
2423                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2424         /* Use QKEY from the QP context, which is set by master */
2425         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2426 }
2427
2428 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2429 {
2430         struct mlx4_wqe_inline_seg *inl = wqe;
2431         struct mlx4_ib_tunnel_header hdr;
2432         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2433         int spc;
2434         int i;
2435
2436         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2437         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2438         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2439         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2440         memcpy(hdr.mac, ah->av.eth.mac, 6);
2441         hdr.vlan = ah->av.eth.vlan;
2442
2443         spc = MLX4_INLINE_ALIGN -
2444                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2445         if (sizeof (hdr) <= spc) {
2446                 memcpy(inl + 1, &hdr, sizeof (hdr));
2447                 wmb();
2448                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2449                 i = 1;
2450         } else {
2451                 memcpy(inl + 1, &hdr, spc);
2452                 wmb();
2453                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2454
2455                 inl = (void *) (inl + 1) + spc;
2456                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2457                 wmb();
2458                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2459                 i = 2;
2460         }
2461
2462         *mlx_seg_len =
2463                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2464 }
2465
2466 static void set_mlx_icrc_seg(void *dseg)
2467 {
2468         u32 *t = dseg;
2469         struct mlx4_wqe_inline_seg *iseg = dseg;
2470
2471         t[1] = 0;
2472
2473         /*
2474          * Need a barrier here before writing the byte_count field to
2475          * make sure that all the data is visible before the
2476          * byte_count field is set.  Otherwise, if the segment begins
2477          * a new cacheline, the HCA prefetcher could grab the 64-byte
2478          * chunk and get a valid (!= * 0xffffffff) byte count but
2479          * stale data, and end up sending the wrong data.
2480          */
2481         wmb();
2482
2483         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2484 }
2485
2486 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2487 {
2488         dseg->lkey       = cpu_to_be32(sg->lkey);
2489         dseg->addr       = cpu_to_be64(sg->addr);
2490
2491         /*
2492          * Need a barrier here before writing the byte_count field to
2493          * make sure that all the data is visible before the
2494          * byte_count field is set.  Otherwise, if the segment begins
2495          * a new cacheline, the HCA prefetcher could grab the 64-byte
2496          * chunk and get a valid (!= * 0xffffffff) byte count but
2497          * stale data, and end up sending the wrong data.
2498          */
2499         wmb();
2500
2501         dseg->byte_count = cpu_to_be32(sg->length);
2502 }
2503
2504 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2505 {
2506         dseg->byte_count = cpu_to_be32(sg->length);
2507         dseg->lkey       = cpu_to_be32(sg->lkey);
2508         dseg->addr       = cpu_to_be64(sg->addr);
2509 }
2510
2511 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2512                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2513                          __be32 *lso_hdr_sz, __be32 *blh)
2514 {
2515         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2516
2517         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2518                 *blh = cpu_to_be32(1 << 6);
2519
2520         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2521                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2522                 return -EINVAL;
2523
2524         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2525
2526         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2527                                    wr->wr.ud.hlen);
2528         *lso_seg_len = halign;
2529         return 0;
2530 }
2531
2532 static __be32 send_ieth(struct ib_send_wr *wr)
2533 {
2534         switch (wr->opcode) {
2535         case IB_WR_SEND_WITH_IMM:
2536         case IB_WR_RDMA_WRITE_WITH_IMM:
2537                 return wr->ex.imm_data;
2538
2539         case IB_WR_SEND_WITH_INV:
2540                 return cpu_to_be32(wr->ex.invalidate_rkey);
2541
2542         default:
2543                 return 0;
2544         }
2545 }
2546
2547 static void add_zero_len_inline(void *wqe)
2548 {
2549         struct mlx4_wqe_inline_seg *inl = wqe;
2550         memset(wqe, 0, 16);
2551         inl->byte_count = cpu_to_be32(1 << 31);
2552 }
2553
2554 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2555                       struct ib_send_wr **bad_wr)
2556 {
2557         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2558         void *wqe;
2559         struct mlx4_wqe_ctrl_seg *ctrl;
2560         struct mlx4_wqe_data_seg *dseg;
2561         unsigned long flags;
2562         int nreq;
2563         int err = 0;
2564         unsigned ind;
2565         int uninitialized_var(stamp);
2566         int uninitialized_var(size);
2567         unsigned uninitialized_var(seglen);
2568         __be32 dummy;
2569         __be32 *lso_wqe;
2570         __be32 uninitialized_var(lso_hdr_sz);
2571         __be32 blh;
2572         int i;
2573
2574         spin_lock_irqsave(&qp->sq.lock, flags);
2575
2576         ind = qp->sq_next_wqe;
2577
2578         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2579                 lso_wqe = &dummy;
2580                 blh = 0;
2581
2582                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2583                         err = -ENOMEM;
2584                         *bad_wr = wr;
2585                         goto out;
2586                 }
2587
2588                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2589                         err = -EINVAL;
2590                         *bad_wr = wr;
2591                         goto out;
2592                 }
2593
2594                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2595                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2596
2597                 ctrl->srcrb_flags =
2598                         (wr->send_flags & IB_SEND_SIGNALED ?
2599                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2600                         (wr->send_flags & IB_SEND_SOLICITED ?
2601                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2602                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2603                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2604                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2605                         qp->sq_signal_bits;
2606
2607                 ctrl->imm = send_ieth(wr);
2608
2609                 wqe += sizeof *ctrl;
2610                 size = sizeof *ctrl / 16;
2611
2612                 switch (qp->mlx4_ib_qp_type) {
2613                 case MLX4_IB_QPT_RC:
2614                 case MLX4_IB_QPT_UC:
2615                         switch (wr->opcode) {
2616                         case IB_WR_ATOMIC_CMP_AND_SWP:
2617                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2618                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2619                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2620                                               wr->wr.atomic.rkey);
2621                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2622
2623                                 set_atomic_seg(wqe, wr);
2624                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2625
2626                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2627                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2628
2629                                 break;
2630
2631                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2632                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2633                                               wr->wr.atomic.rkey);
2634                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2635
2636                                 set_masked_atomic_seg(wqe, wr);
2637                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2638
2639                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2640                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2641
2642                                 break;
2643
2644                         case IB_WR_RDMA_READ:
2645                         case IB_WR_RDMA_WRITE:
2646                         case IB_WR_RDMA_WRITE_WITH_IMM:
2647                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2648                                               wr->wr.rdma.rkey);
2649                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2650                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2651                                 break;
2652
2653                         case IB_WR_LOCAL_INV:
2654                                 ctrl->srcrb_flags |=
2655                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2656                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2657                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2658                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2659                                 break;
2660
2661                         case IB_WR_FAST_REG_MR:
2662                                 ctrl->srcrb_flags |=
2663                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2664                                 set_fmr_seg(wqe, wr);
2665                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2666                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2667                                 break;
2668
2669                         case IB_WR_BIND_MW:
2670                                 ctrl->srcrb_flags |=
2671                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2672                                 set_bind_seg(wqe, wr);
2673                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2674                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2675                                 break;
2676                         default:
2677                                 /* No extra segments required for sends */
2678                                 break;
2679                         }
2680                         break;
2681
2682                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2683                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2684                         if (unlikely(err)) {
2685                                 *bad_wr = wr;
2686                                 goto out;
2687                         }
2688                         wqe  += seglen;
2689                         size += seglen / 16;
2690                         break;
2691                 case MLX4_IB_QPT_TUN_SMI:
2692                 case MLX4_IB_QPT_TUN_GSI:
2693                         /* this is a UD qp used in MAD responses to slaves. */
2694                         set_datagram_seg(wqe, wr);
2695                         /* set the forced-loopback bit in the data seg av */
2696                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2697                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2698                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2699                         break;
2700                 case MLX4_IB_QPT_UD:
2701                         set_datagram_seg(wqe, wr);
2702                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2703                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2704
2705                         if (wr->opcode == IB_WR_LSO) {
2706                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2707                                 if (unlikely(err)) {
2708                                         *bad_wr = wr;
2709                                         goto out;
2710                                 }
2711                                 lso_wqe = (__be32 *) wqe;
2712                                 wqe  += seglen;
2713                                 size += seglen / 16;
2714                         }
2715                         break;
2716
2717                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2718                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2719                         if (unlikely(err)) {
2720                                 *bad_wr = wr;
2721                                 goto out;
2722                         }
2723                         wqe  += seglen;
2724                         size += seglen / 16;
2725                         /* to start tunnel header on a cache-line boundary */
2726                         add_zero_len_inline(wqe);
2727                         wqe += 16;
2728                         size++;
2729                         build_tunnel_header(wr, wqe, &seglen);
2730                         wqe  += seglen;
2731                         size += seglen / 16;
2732                         break;
2733                 case MLX4_IB_QPT_PROXY_SMI:
2734                 case MLX4_IB_QPT_PROXY_GSI:
2735                         /* If we are tunneling special qps, this is a UD qp.
2736                          * In this case we first add a UD segment targeting
2737                          * the tunnel qp, and then add a header with address
2738                          * information */
2739                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2740                                                 qp->mlx4_ib_qp_type);
2741                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2742                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2743                         build_tunnel_header(wr, wqe, &seglen);
2744                         wqe  += seglen;
2745                         size += seglen / 16;
2746                         break;
2747
2748                 case MLX4_IB_QPT_SMI:
2749                 case MLX4_IB_QPT_GSI:
2750                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2751                         if (unlikely(err)) {
2752                                 *bad_wr = wr;
2753                                 goto out;
2754                         }
2755                         wqe  += seglen;
2756                         size += seglen / 16;
2757                         break;
2758
2759                 default:
2760                         break;
2761                 }
2762
2763                 /*
2764                  * Write data segments in reverse order, so as to
2765                  * overwrite cacheline stamp last within each
2766                  * cacheline.  This avoids issues with WQE
2767                  * prefetching.
2768                  */
2769
2770                 dseg = wqe;
2771                 dseg += wr->num_sge - 1;
2772                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2773
2774                 /* Add one more inline data segment for ICRC for MLX sends */
2775                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2776                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2777                              qp->mlx4_ib_qp_type &
2778                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2779                         set_mlx_icrc_seg(dseg + 1);
2780                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2781                 }
2782
2783                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2784                         set_data_seg(dseg, wr->sg_list + i);
2785
2786                 /*
2787                  * Possibly overwrite stamping in cacheline with LSO
2788                  * segment only after making sure all data segments
2789                  * are written.
2790                  */
2791                 wmb();
2792                 *lso_wqe = lso_hdr_sz;
2793
2794                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2795                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2796
2797                 /*
2798                  * Make sure descriptor is fully written before
2799                  * setting ownership bit (because HW can start
2800                  * executing as soon as we do).
2801                  */
2802                 wmb();
2803
2804                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2805                         *bad_wr = wr;
2806                         err = -EINVAL;
2807                         goto out;
2808                 }
2809
2810                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2811                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2812
2813                 stamp = ind + qp->sq_spare_wqes;
2814                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2815
2816                 /*
2817                  * We can improve latency by not stamping the last
2818                  * send queue WQE until after ringing the doorbell, so
2819                  * only stamp here if there are still more WQEs to post.
2820                  *
2821                  * Same optimization applies to padding with NOP wqe
2822                  * in case of WQE shrinking (used to prevent wrap-around
2823                  * in the middle of WR).
2824                  */
2825                 if (wr->next) {
2826                         stamp_send_wqe(qp, stamp, size * 16);
2827                         ind = pad_wraparound(qp, ind);
2828                 }
2829         }
2830
2831 out:
2832         if (likely(nreq)) {
2833                 qp->sq.head += nreq;
2834
2835                 /*
2836                  * Make sure that descriptors are written before
2837                  * doorbell record.
2838                  */
2839                 wmb();
2840
2841                 writel(qp->doorbell_qpn,
2842                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2843
2844                 /*
2845                  * Make sure doorbells don't leak out of SQ spinlock
2846                  * and reach the HCA out of order.
2847                  */
2848                 mmiowb();
2849
2850                 stamp_send_wqe(qp, stamp, size * 16);
2851
2852                 ind = pad_wraparound(qp, ind);
2853                 qp->sq_next_wqe = ind;
2854         }
2855
2856         spin_unlock_irqrestore(&qp->sq.lock, flags);
2857
2858         return err;
2859 }
2860
2861 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2862                       struct ib_recv_wr **bad_wr)
2863 {
2864         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2865         struct mlx4_wqe_data_seg *scat;
2866         unsigned long flags;
2867         int err = 0;
2868         int nreq;
2869         int ind;
2870         int max_gs;
2871         int i;
2872
2873         max_gs = qp->rq.max_gs;
2874         spin_lock_irqsave(&qp->rq.lock, flags);
2875
2876         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2877
2878         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2879                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2880                         err = -ENOMEM;
2881                         *bad_wr = wr;
2882                         goto out;
2883                 }
2884
2885                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2886                         err = -EINVAL;
2887                         *bad_wr = wr;
2888                         goto out;
2889                 }
2890
2891                 scat = get_recv_wqe(qp, ind);
2892
2893                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2894                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2895                         ib_dma_sync_single_for_device(ibqp->device,
2896                                                       qp->sqp_proxy_rcv[ind].map,
2897                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2898                                                       DMA_FROM_DEVICE);
2899                         scat->byte_count =
2900                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2901                         /* use dma lkey from upper layer entry */
2902                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2903                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2904                         scat++;
2905                         max_gs--;
2906                 }
2907
2908                 for (i = 0; i < wr->num_sge; ++i)
2909                         __set_data_seg(scat + i, wr->sg_list + i);
2910
2911                 if (i < max_gs) {
2912                         scat[i].byte_count = 0;
2913                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2914                         scat[i].addr       = 0;
2915                 }
2916
2917                 qp->rq.wrid[ind] = wr->wr_id;
2918
2919                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2920         }
2921
2922 out:
2923         if (likely(nreq)) {
2924                 qp->rq.head += nreq;
2925
2926                 /*
2927                  * Make sure that descriptors are written before
2928                  * doorbell record.
2929                  */
2930                 wmb();
2931
2932                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2933         }
2934
2935         spin_unlock_irqrestore(&qp->rq.lock, flags);
2936
2937         return err;
2938 }
2939
2940 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2941 {
2942         switch (mlx4_state) {
2943         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2944         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2945         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2946         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2947         case MLX4_QP_STATE_SQ_DRAINING:
2948         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2949         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2950         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2951         default:                     return -1;
2952         }
2953 }
2954
2955 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2956 {
2957         switch (mlx4_mig_state) {
2958         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2959         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2960         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2961         default: return -1;
2962         }
2963 }
2964
2965 static int to_ib_qp_access_flags(int mlx4_flags)
2966 {
2967         int ib_flags = 0;
2968
2969         if (mlx4_flags & MLX4_QP_BIT_RRE)
2970                 ib_flags |= IB_ACCESS_REMOTE_READ;
2971         if (mlx4_flags & MLX4_QP_BIT_RWE)
2972                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2973         if (mlx4_flags & MLX4_QP_BIT_RAE)
2974                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2975
2976         return ib_flags;
2977 }
2978
2979 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2980                                 struct mlx4_qp_path *path)
2981 {
2982         struct mlx4_dev *dev = ibdev->dev;
2983         int is_eth;
2984
2985         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2986         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2987
2988         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2989                 return;
2990
2991         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2992                 IB_LINK_LAYER_ETHERNET;
2993         if (is_eth)
2994                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2995                 ((path->sched_queue & 4) << 1);
2996         else
2997                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2998
2999         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3000         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3001         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3002         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3003         if (ib_ah_attr->ah_flags) {
3004                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3005                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3006                 ib_ah_attr->grh.traffic_class =
3007                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3008                 ib_ah_attr->grh.flow_label =
3009                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3010                 memcpy(ib_ah_attr->grh.dgid.raw,
3011                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3012         }
3013 }
3014
3015 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3016                      struct ib_qp_init_attr *qp_init_attr)
3017 {
3018         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3019         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3020         struct mlx4_qp_context context;
3021         int mlx4_state;
3022         int err = 0;
3023
3024         mutex_lock(&qp->mutex);
3025
3026         if (qp->state == IB_QPS_RESET) {
3027                 qp_attr->qp_state = IB_QPS_RESET;
3028                 goto done;
3029         }
3030
3031         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3032         if (err) {
3033                 err = -EINVAL;
3034                 goto out;
3035         }
3036
3037         mlx4_state = be32_to_cpu(context.flags) >> 28;
3038
3039         qp->state                    = to_ib_qp_state(mlx4_state);
3040         qp_attr->qp_state            = qp->state;
3041         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3042         qp_attr->path_mig_state      =
3043                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3044         qp_attr->qkey                = be32_to_cpu(context.qkey);
3045         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3046         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3047         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3048         qp_attr->qp_access_flags     =
3049                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3050
3051         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3052                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3053                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3054                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3055                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3056         }
3057
3058         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3059         if (qp_attr->qp_state == IB_QPS_INIT)
3060                 qp_attr->port_num = qp->port;
3061         else
3062                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3063
3064         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3065         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3066
3067         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3068
3069         qp_attr->max_dest_rd_atomic =
3070                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3071         qp_attr->min_rnr_timer      =
3072                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3073         qp_attr->timeout            = context.pri_path.ackto >> 3;
3074         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3075         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3076         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3077
3078 done:
3079         qp_attr->cur_qp_state        = qp_attr->qp_state;
3080         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3081         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3082
3083         if (!ibqp->uobject) {
3084                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3085                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3086         } else {
3087                 qp_attr->cap.max_send_wr  = 0;
3088                 qp_attr->cap.max_send_sge = 0;
3089         }
3090
3091         /*
3092          * We don't support inline sends for kernel QPs (yet), and we
3093          * don't know what userspace's value should be.
3094          */
3095         qp_attr->cap.max_inline_data = 0;
3096
3097         qp_init_attr->cap            = qp_attr->cap;
3098
3099         qp_init_attr->create_flags = 0;
3100         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3101                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3102
3103         if (qp->flags & MLX4_IB_QP_LSO)
3104                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3105
3106         if (qp->flags & MLX4_IB_QP_NETIF)
3107                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3108
3109         qp_init_attr->sq_sig_type =
3110                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3111                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3112
3113 out:
3114         mutex_unlock(&qp->mutex);
3115         return err;
3116 }
3117