drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 #ifndef ETH_ALEN
  94 #define ETH_ALEN        6
  95 #endif
  96 static inline u64 mlx4_mac_to_u64(u8 *addr)
  97 {
  98         u64 mac = 0;
  99         int i;
 100
 101         for (i = 0; i < ETH_ALEN; i++) {
 102                 mac <<= 8;
 103                 mac |= addr[i];
 104         }
 105         return mac;
 106 }
 107
 108 static const __be32 mlx4_ib_opcode[] = {
 109         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 110         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 111         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 112         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 113         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 114         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 115         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 116         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 117         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 118         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 119         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 120         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 121         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 122         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 123 };
 124
 125 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 126 {
 127         return container_of(mqp, struct mlx4_ib_sqp, qp);
 128 }
 129
 130 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 131 {
 132         if (!mlx4_is_master(dev->dev))
 133                 return 0;
 134
 135         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 136                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 137                 8 * MLX4_MFUNC_MAX;
 138 }
 139
 140 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 141 {
 142         int proxy_sqp = 0;
 143         int real_sqp = 0;
 144         int i;
 145         /* PPF or Native -- real SQP */
 146         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 147                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 148                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 149         if (real_sqp)
 150                 return 1;
 151         /* VF or PF -- proxy SQP */
 152         if (mlx4_is_mfunc(dev->dev)) {
 153                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 154                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 155                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 156                                 proxy_sqp = 1;
 157                                 break;
 158                         }
 159                 }
 160         }
 161         return proxy_sqp;
 162 }
 163
 164 /* used for INIT/CLOSE port logic */
 165 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 166 {
 167         int proxy_qp0 = 0;
 168         int real_qp0 = 0;
 169         int i;
 170         /* PPF or Native -- real QP0 */
 171         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 172                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 173                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 174         if (real_qp0)
 175                 return 1;
 176         /* VF or PF -- proxy QP0 */
 177         if (mlx4_is_mfunc(dev->dev)) {
 178                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 179                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 180                                 proxy_qp0 = 1;
 181                                 break;
 182                         }
 183                 }
 184         }
 185         return proxy_qp0;
 186 }
 187
 188 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 189 {
 190         return mlx4_buf_offset(&qp->buf, offset);
 191 }
 192
 193 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 196 }
 197
 198 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 199 {
 200         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 201 }
 202
 203 /*
 204  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 205  * first four bytes of every 64 byte chunk with
 206  *     0x7FFFFFF | (invalid_ownership_value << 31).
 207  *
 208  * When the max work request size is less than or equal to the WQE
 209  * basic block size, as an optimization, we can stamp all WQEs with
 210  * 0xffffffff, and skip the very first chunk of each WQE.
 211  */
 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 213 {
 214         __be32 *wqe;
 215         int i;
 216         int s;
 217         int ind;
 218         void *buf;
 219         __be32 stamp;
 220         struct mlx4_wqe_ctrl_seg *ctrl;
 221
 222         if (qp->sq_max_wqes_per_wr > 1) {
 223                 s = roundup(size, 1U << qp->sq.wqe_shift);
 224                 for (i = 0; i < s; i += 64) {
 225                         ind = (i >> qp->sq.wqe_shift) + n;
 226                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 227                                                        cpu_to_be32(0xffffffff);
 228                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 229                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 230                         *wqe = stamp;
 231                 }
 232         } else {
 233                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 234                 s = (ctrl->fence_size & 0x3f) << 4;
 235                 for (i = 64; i < s; i += 64) {
 236                         wqe = buf + i;
 237                         *wqe = cpu_to_be32(0xffffffff);
 238                 }
 239         }
 240 }
 241
 242 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 243 {
 244         struct mlx4_wqe_ctrl_seg *ctrl;
 245         struct mlx4_wqe_inline_seg *inl;
 246         void *wqe;
 247         int s;
 248
 249         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 250         s = sizeof(struct mlx4_wqe_ctrl_seg);
 251
 252         if (qp->ibqp.qp_type == IB_QPT_UD) {
 253                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 254                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 255                 memset(dgram, 0, sizeof *dgram);
 256                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 257                 s += sizeof(struct mlx4_wqe_datagram_seg);
 258         }
 259
 260         /* Pad the remainder of the WQE with an inline data segment. */
 261         if (size > s) {
 262                 inl = wqe + s;
 263                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 264         }
 265         ctrl->srcrb_flags = 0;
 266         ctrl->fence_size = size / 16;
 267         /*
 268          * Make sure descriptor is fully written before setting ownership bit
 269          * (because HW can start executing as soon as we do).
 270          */
 271         wmb();
 272
 273         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 274                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 275
 276         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 277 }
 278
 279 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 280 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 281 {
 282         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 283         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 284                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 285                 ind += s;
 286         }
 287         return ind;
 288 }
 289
 290 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 291 {
 292         struct ib_event event;
 293         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 294
 295         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 296                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 297
 298         if (ibqp->event_handler) {
 299                 event.device     = ibqp->device;
 300                 event.element.qp = ibqp;
 301                 switch (type) {
 302                 case MLX4_EVENT_TYPE_PATH_MIG:
 303                         event.event = IB_EVENT_PATH_MIG;
 304                         break;
 305                 case MLX4_EVENT_TYPE_COMM_EST:
 306                         event.event = IB_EVENT_COMM_EST;
 307                         break;
 308                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 309                         event.event = IB_EVENT_SQ_DRAINED;
 310                         break;
 311                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 312                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 313                         break;
 314                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 315                         event.event = IB_EVENT_QP_FATAL;
 316                         break;
 317                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 318                         event.event = IB_EVENT_PATH_MIG_ERR;
 319                         break;
 320                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 321                         event.event = IB_EVENT_QP_REQ_ERR;
 322                         break;
 323                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 324                         event.event = IB_EVENT_QP_ACCESS_ERR;
 325                         break;
 326                 default:
 327                         pr_warn("Unexpected event type %d "
 328                                "on QP %06x\n", type, qp->qpn);
 329                         return;
 330                 }
 331
 332                 ibqp->event_handler(&event, ibqp->qp_context);
 333         }
 334 }
 335
 336 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 337 {
 338         /*
 339          * UD WQEs must have a datagram segment.
 340          * RC and UC WQEs might have a remote address segment.
 341          * MLX WQEs need two extra inline data segments (for the UD
 342          * header and space for the ICRC).
 343          */
 344         switch (type) {
 345         case MLX4_IB_QPT_UD:
 346                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 347                         sizeof (struct mlx4_wqe_datagram_seg) +
 348                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 349         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 350         case MLX4_IB_QPT_PROXY_SMI:
 351         case MLX4_IB_QPT_PROXY_GSI:
 352                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 353                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 354         case MLX4_IB_QPT_TUN_SMI_OWNER:
 355         case MLX4_IB_QPT_TUN_GSI:
 356                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 357                         sizeof (struct mlx4_wqe_datagram_seg);
 358
 359         case MLX4_IB_QPT_UC:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_raddr_seg);
 362         case MLX4_IB_QPT_RC:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         sizeof (struct mlx4_wqe_atomic_seg) +
 365                         sizeof (struct mlx4_wqe_raddr_seg);
 366         case MLX4_IB_QPT_SMI:
 367         case MLX4_IB_QPT_GSI:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 370                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 371                                            MLX4_INLINE_ALIGN) *
 372                               sizeof (struct mlx4_wqe_inline_seg),
 373                               sizeof (struct mlx4_wqe_data_seg)) +
 374                         ALIGN(4 +
 375                               sizeof (struct mlx4_wqe_inline_seg),
 376                               sizeof (struct mlx4_wqe_data_seg));
 377         default:
 378                 return sizeof (struct mlx4_wqe_ctrl_seg);
 379         }
 380 }
 381
 382 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 383                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 384 {
 385         /* Sanity check RQ size before proceeding */
 386         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 387             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 388                 return -EINVAL;
 389
 390         if (!has_rq) {
 391                 if (cap->max_recv_wr)
 392                         return -EINVAL;
 393
 394                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 395         } else {
 396                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 397                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 398                         return -EINVAL;
 399
 400                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 401                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 402                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 403         }
 404
 405         /* leave userspace return values as they were, so as not to break ABI */
 406         if (is_user) {
 407                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 408                 cap->max_recv_sge = qp->rq.max_gs;
 409         } else {
 410                 cap->max_recv_wr  = qp->rq.max_post =
 411                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 412                 cap->max_recv_sge = min(qp->rq.max_gs,
 413                                         min(dev->dev->caps.max_sq_sg,
 414                                             dev->dev->caps.max_rq_sg));
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 421                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 422 {
 423         int s;
 424
 425         /* Sanity check SQ size before proceeding */
 426         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 427             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 428             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 429             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 430                 return -EINVAL;
 431
 432         /*
 433          * For MLX transport we need 2 extra S/G entries:
 434          * one for the header and one for the checksum at the end
 435          */
 436         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 437              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 438             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 439                 return -EINVAL;
 440
 441         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 442                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 443                 send_wqe_overhead(type, qp->flags);
 444
 445         if (s > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * Hermon supports shrinking WQEs, such that a single work
 450          * request can include multiple units of 1 << wqe_shift.  This
 451          * way, work requests can differ in size, and do not have to
 452          * be a power of 2 in size, saving memory and speeding up send
 453          * WR posting.  Unfortunately, if we do this then the
 454          * wqe_index field in CQEs can't be used to look up the WR ID
 455          * anymore, so we do this only if selective signaling is off.
 456          *
 457          * Further, on 32-bit platforms, we can't use vmap() to make
 458          * the QP buffer virtually contiguous.  Thus we have to use
 459          * constant-sized WRs to make sure a WR is always fully within
 460          * a single page-sized chunk.
 461          *
 462          * Finally, we use NOP work requests to pad the end of the
 463          * work queue, to avoid wrap-around in the middle of WR.  We
 464          * set NEC bit to avoid getting completions with error for
 465          * these NOP WRs, but since NEC is only supported starting
 466          * with firmware 2.2.232, we use constant-sized WRs for older
 467          * firmware.
 468          *
 469          * And, since MLX QPs only support SEND, we use constant-sized
 470          * WRs in this case.
 471          *
 472          * We look for the smallest value of wqe_shift such that the
 473          * resulting number of wqes does not exceed device
 474          * capabilities.
 475          *
 476          * We set WQE size to at least 64 bytes, this way stamping
 477          * invalidates each WQE.
 478          */
 479         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 480             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 481             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 482             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 483                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 484                 qp->sq.wqe_shift = ilog2(64);
 485         else
 486                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 487
 488         for (;;) {
 489                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 490
 491                 /*
 492                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 493                  * allow HW to prefetch.
 494                  */
 495                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 496                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 497                                                     qp->sq_max_wqes_per_wr +
 498                                                     qp->sq_spare_wqes);
 499
 500                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 501                         break;
 502
 503                 if (qp->sq_max_wqes_per_wr <= 1)
 504                         return -EINVAL;
 505
 506                 ++qp->sq.wqe_shift;
 507         }
 508
 509         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 510                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 511                          send_wqe_overhead(type, qp->flags)) /
 512                 sizeof (struct mlx4_wqe_data_seg);
 513
 514         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 515                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 516         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 517                 qp->rq.offset = 0;
 518                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 519         } else {
 520                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 521                 qp->sq.offset = 0;
 522         }
 523
 524         cap->max_send_wr  = qp->sq.max_post =
 525                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 526         cap->max_send_sge = min(qp->sq.max_gs,
 527                                 min(dev->dev->caps.max_sq_sg,
 528                                     dev->dev->caps.max_rq_sg));
 529         /* We don't support inline sends for kernel QPs (yet) */
 530         cap->max_inline_data = 0;
 531
 532         return 0;
 533 }
 534
 535 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 536                             struct mlx4_ib_qp *qp,
 537                             struct mlx4_ib_create_qp *ucmd)
 538 {
 539         /* Sanity check SQ size before proceeding */
 540         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 541             ucmd->log_sq_stride >
 542                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 543             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 544                 return -EINVAL;
 545
 546         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 547         qp->sq.wqe_shift = ucmd->log_sq_stride;
 548
 549         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 550                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 551
 552         return 0;
 553 }
 554
 555 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 556 {
 557         int i;
 558
 559         qp->sqp_proxy_rcv =
 560                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 561                         GFP_KERNEL);
 562         if (!qp->sqp_proxy_rcv)
 563                 return -ENOMEM;
 564         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 565                 qp->sqp_proxy_rcv[i].addr =
 566                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 567                                 GFP_KERNEL);
 568                 if (!qp->sqp_proxy_rcv[i].addr)
 569                         goto err;
 570                 qp->sqp_proxy_rcv[i].map =
 571                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 572                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 573                                           DMA_FROM_DEVICE);
 574         }
 575         return 0;
 576
 577 err:
 578         while (i > 0) {
 579                 --i;
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586         qp->sqp_proxy_rcv = NULL;
 587         return -ENOMEM;
 588 }
 589
 590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 591 {
 592         int i;
 593
 594         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 595                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 596                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 597                                     DMA_FROM_DEVICE);
 598                 kfree(qp->sqp_proxy_rcv[i].addr);
 599         }
 600         kfree(qp->sqp_proxy_rcv);
 601 }
 602
 603 static int qp_has_rq(struct ib_qp_init_attr *attr)
 604 {
 605         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 606                 return 0;
 607
 608         return !attr->srq;
 609 }
 610
 611 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 612                             struct ib_qp_init_attr *init_attr,
 613                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
 614 {
 615         int qpn;
 616         int err;
 617         struct mlx4_ib_sqp *sqp;
 618         struct mlx4_ib_qp *qp;
 619         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 620
 621         /* When tunneling special qps, we use a plain UD qp */
 622         if (sqpn) {
 623                 if (mlx4_is_mfunc(dev->dev) &&
 624                     (!mlx4_is_master(dev->dev) ||
 625                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 626                         if (init_attr->qp_type == IB_QPT_GSI)
 627                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 628                         else if (mlx4_is_master(dev->dev))
 629                                 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 630                         else
 631                                 qp_type = MLX4_IB_QPT_PROXY_SMI;
 632                 }
 633                 qpn = sqpn;
 634                 /* add extra sg entry for tunneling */
 635                 init_attr->cap.max_recv_sge++;
 636         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 637                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 638                         container_of(init_attr,
 639                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 640                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 641                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 642                     !mlx4_is_master(dev->dev))
 643                         return -EINVAL;
 644                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 645                         qp_type = MLX4_IB_QPT_TUN_GSI;
 646                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev))
 647                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 648                 else
 649                         qp_type = MLX4_IB_QPT_TUN_SMI;
 650                 /* we are definitely in the PPF here, since we are creating
 651                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 652                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 653                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 654                 sqpn = qpn;
 655         }
 656
 657         if (!*caller_qp) {
 658                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 659                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 660                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 661                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
 662                         if (!sqp)
 663                                 return -ENOMEM;
 664                         qp = &sqp->qp;
 665                 } else {
 666                         qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
 667                         if (!qp)
 668                                 return -ENOMEM;
 669                 }
 670         } else
 671                 qp = *caller_qp;
 672
 673         qp->mlx4_ib_qp_type = qp_type;
 674
 675         mutex_init(&qp->mutex);
 676         spin_lock_init(&qp->sq.lock);
 677         spin_lock_init(&qp->rq.lock);
 678         INIT_LIST_HEAD(&qp->gid_list);
 679         INIT_LIST_HEAD(&qp->steering_rules);
 680
 681         qp->state        = IB_QPS_RESET;
 682         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 683                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 684
 685         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 686         if (err)
 687                 goto err;
 688
 689         if (pd->uobject) {
 690                 struct mlx4_ib_create_qp ucmd;
 691
 692                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 693                         err = -EFAULT;
 694                         goto err;
 695                 }
 696
 697                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 698
 699                 err = set_user_sq_size(dev, qp, &ucmd);
 700                 if (err)
 701                         goto err;
 702
 703                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 704                                        qp->buf_size, 0, 0);
 705                 if (IS_ERR(qp->umem)) {
 706                         err = PTR_ERR(qp->umem);
 707                         goto err;
 708                 }
 709
 710                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 711                                     ilog2(qp->umem->page_size), &qp->mtt);
 712                 if (err)
 713                         goto err_buf;
 714
 715                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 716                 if (err)
 717                         goto err_mtt;
 718
 719                 if (qp_has_rq(init_attr)) {
 720                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 721                                                   ucmd.db_addr, &qp->db);
 722                         if (err)
 723                                 goto err_mtt;
 724                 }
 725         } else {
 726                 qp->sq_no_prefetch = 0;
 727
 728                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 729                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 730
 731                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 732                         qp->flags |= MLX4_IB_QP_LSO;
 733
 734                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 735                         if (dev->steering_support ==
 736                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 737                                 qp->flags |= MLX4_IB_QP_NETIF;
 738                         else
 739                                 goto err;
 740                 }
 741
 742                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 743                 if (err)
 744                         goto err;
 745
 746                 if (qp_has_rq(init_attr)) {
 747                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 748                         if (err)
 749                                 goto err;
 750
 751                         *qp->db.db = 0;
 752                 }
 753
 754                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 755                         err = -ENOMEM;
 756                         goto err_db;
 757                 }
 758
 759                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 760                                     &qp->mtt);
 761                 if (err)
 762                         goto err_buf;
 763
 764                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 765                 if (err)
 766                         goto err_mtt;
 767
 768                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 769                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 770
 771                 if (!qp->sq.wrid || !qp->rq.wrid) {
 772                         err = -ENOMEM;
 773                         goto err_wrid;
 774                 }
 775         }
 776
 777         if (sqpn) {
 778                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 779                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 780                         if (alloc_proxy_bufs(pd->device, qp)) {
 781                                 err = -ENOMEM;
 782                                 goto err_wrid;
 783                         }
 784                 }
 785         } else {
 786                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 787                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 788                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 789                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 790                 else
 791                         if (qp->flags & MLX4_IB_QP_NETIF)
 792                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 793                         else
 794                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 795                                                             &qpn);
 796                 if (err)
 797                         goto err_proxy;
 798         }
 799
 800         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 801         if (err)
 802                 goto err_qpn;
 803
 804         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 805                 qp->mqp.qpn |= (1 << 23);
 806
 807         /*
 808          * Hardware wants QPN written in big-endian order (after
 809          * shifting) for send doorbell.  Precompute this value to save
 810          * a little bit when posting sends.
 811          */
 812         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 813
 814         qp->mqp.event = mlx4_ib_qp_event;
 815         if (!*caller_qp)
 816                 *caller_qp = qp;
 817         return 0;
 818
 819 err_qpn:
 820         if (!sqpn) {
 821                 if (qp->flags & MLX4_IB_QP_NETIF)
 822                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 823                 else
 824                         mlx4_qp_release_range(dev->dev, qpn, 1);
 825         }
 826 err_proxy:
 827         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 828                 free_proxy_bufs(pd->device, qp);
 829 err_wrid:
 830         if (pd->uobject) {
 831                 if (qp_has_rq(init_attr))
 832                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 833         } else {
 834                 kfree(qp->sq.wrid);
 835                 kfree(qp->rq.wrid);
 836         }
 837
 838 err_mtt:
 839         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 840
 841 err_buf:
 842         if (pd->uobject)
 843                 ib_umem_release(qp->umem);
 844         else
 845                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 846
 847 err_db:
 848         if (!pd->uobject && qp_has_rq(init_attr))
 849                 mlx4_db_free(dev->dev, &qp->db);
 850
 851 err:
 852         if (!*caller_qp)
 853                 kfree(qp);
 854         return err;
 855 }
 856
 857 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 858 {
 859         switch (state) {
 860         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 861         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 862         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 863         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 864         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 865         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 866         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 867         default:                return -1;
 868         }
 869 }
 870
 871 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 872         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 873 {
 874         if (send_cq == recv_cq) {
 875                 spin_lock_irq(&send_cq->lock);
 876                 __acquire(&recv_cq->lock);
 877         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 878                 spin_lock_irq(&send_cq->lock);
 879                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 880         } else {
 881                 spin_lock_irq(&recv_cq->lock);
 882                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 883         }
 884 }
 885
 886 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 887         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 888 {
 889         if (send_cq == recv_cq) {
 890                 __release(&recv_cq->lock);
 891                 spin_unlock_irq(&send_cq->lock);
 892         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 893                 spin_unlock(&recv_cq->lock);
 894                 spin_unlock_irq(&send_cq->lock);
 895         } else {
 896                 spin_unlock(&send_cq->lock);
 897                 spin_unlock_irq(&recv_cq->lock);
 898         }
 899 }
 900
 901 static void del_gid_entries(struct mlx4_ib_qp *qp)
 902 {
 903         struct mlx4_ib_gid_entry *ge, *tmp;
 904
 905         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 906                 list_del(&ge->list);
 907                 kfree(ge);
 908         }
 909 }
 910
 911 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 912 {
 913         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 914                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 915         else
 916                 return to_mpd(qp->ibqp.pd);
 917 }
 918
 919 static void get_cqs(struct mlx4_ib_qp *qp,
 920                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 921 {
 922         switch (qp->ibqp.qp_type) {
 923         case IB_QPT_XRC_TGT:
 924                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 925                 *recv_cq = *send_cq;
 926                 break;
 927         case IB_QPT_XRC_INI:
 928                 *send_cq = to_mcq(qp->ibqp.send_cq);
 929                 *recv_cq = *send_cq;
 930                 break;
 931         default:
 932                 *send_cq = to_mcq(qp->ibqp.send_cq);
 933                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 934                 break;
 935         }
 936 }
 937
 938 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 939                               int is_user)
 940 {
 941         struct mlx4_ib_cq *send_cq, *recv_cq;
 942
 943         if (qp->state != IB_QPS_RESET)
 944                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 945                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 946                         pr_warn("modify QP %06x to RESET failed.\n",
 947                                qp->mqp.qpn);
 948
 949         get_cqs(qp, &send_cq, &recv_cq);
 950
 951         mlx4_ib_lock_cqs(send_cq, recv_cq);
 952
 953         if (!is_user) {
 954                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 955                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 956                 if (send_cq != recv_cq)
 957                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 958         }
 959
 960         mlx4_qp_remove(dev->dev, &qp->mqp);
 961
 962         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 963
 964         mlx4_qp_free(dev->dev, &qp->mqp);
 965
 966         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
 967                 if (qp->flags & MLX4_IB_QP_NETIF)
 968                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
 969                 else
 970                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 971         }
 972
 973         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 974
 975         if (is_user) {
 976                 if (qp->rq.wqe_cnt)
 977                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 978                                               &qp->db);
 979                 ib_umem_release(qp->umem);
 980         } else {
 981                 kfree(qp->sq.wrid);
 982                 kfree(qp->rq.wrid);
 983                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 984                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
 985                         free_proxy_bufs(&dev->ib_dev, qp);
 986                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 987                 if (qp->rq.wqe_cnt)
 988                         mlx4_db_free(dev->dev, &qp->db);
 989         }
 990
 991         del_gid_entries(qp);
 992 }
 993
 994 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
 995 {
 996         /* Native or PPF */
 997         if (!mlx4_is_mfunc(dev->dev) ||
 998             (mlx4_is_master(dev->dev) &&
 999              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1000                 return  dev->dev->phys_caps.base_sqpn +
1001                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1002                         attr->port_num - 1;
1003         }
1004         /* PF or VF -- creating proxies */
1005         if (attr->qp_type == IB_QPT_SMI)
1006                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1007         else
1008                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1009 }
1010
1011 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1012                                 struct ib_qp_init_attr *init_attr,
1013                                 struct ib_udata *udata)
1014 {
1015         struct mlx4_ib_qp *qp = NULL;
1016         int err;
1017         u16 xrcdn = 0;
1018
1019         /*
1020          * We only support LSO, vendor flag1, and multicast loopback blocking,
1021          * and only for kernel UD QPs.
1022          */
1023         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1024                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1025                                         MLX4_IB_SRIOV_TUNNEL_QP |
1026                                         MLX4_IB_SRIOV_SQP |
1027                                         MLX4_IB_QP_NETIF))
1028                 return ERR_PTR(-EINVAL);
1029
1030         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1031                 if (init_attr->qp_type != IB_QPT_UD)
1032                         return ERR_PTR(-EINVAL);
1033         }
1034
1035         if (init_attr->create_flags &&
1036             (udata ||
1037              ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
1038               init_attr->qp_type != IB_QPT_UD) ||
1039              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1040               init_attr->qp_type > IB_QPT_GSI)))
1041                 return ERR_PTR(-EINVAL);
1042
1043         switch (init_attr->qp_type) {
1044         case IB_QPT_XRC_TGT:
1045                 pd = to_mxrcd(init_attr->xrcd)->pd;
1046                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1047                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1048                 /* fall through */
1049         case IB_QPT_XRC_INI:
1050                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1051                         return ERR_PTR(-ENOSYS);
1052                 init_attr->recv_cq = init_attr->send_cq;
1053                 /* fall through */
1054         case IB_QPT_RC:
1055         case IB_QPT_UC:
1056         case IB_QPT_RAW_PACKET:
1057                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
1058                 if (!qp)
1059                         return ERR_PTR(-ENOMEM);
1060                 /* fall through */
1061         case IB_QPT_UD:
1062         {
1063                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1064                                        udata, 0, &qp);
1065                 if (err)
1066                         return ERR_PTR(err);
1067
1068                 qp->ibqp.qp_num = qp->mqp.qpn;
1069                 qp->xrcdn = xrcdn;
1070
1071                 break;
1072         }
1073         case IB_QPT_SMI:
1074         case IB_QPT_GSI:
1075         {
1076                 /* Userspace is not allowed to create special QPs: */
1077                 if (udata)
1078                         return ERR_PTR(-EINVAL);
1079
1080                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1081                                        get_sqp_num(to_mdev(pd->device), init_attr),
1082                                        &qp);
1083                 if (err)
1084                         return ERR_PTR(err);
1085
1086                 qp->port        = init_attr->port_num;
1087                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1088
1089                 break;
1090         }
1091         default:
1092                 /* Don't support raw QPs */
1093                 return ERR_PTR(-EINVAL);
1094         }
1095
1096         return &qp->ibqp;
1097 }
1098
1099 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1100 {
1101         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1102         struct mlx4_ib_qp *mqp = to_mqp(qp);
1103         struct mlx4_ib_pd *pd;
1104
1105         if (is_qp0(dev, mqp))
1106                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1107
1108         pd = get_pd(mqp);
1109         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1110
1111         if (is_sqp(dev, mqp))
1112                 kfree(to_msqp(mqp));
1113         else
1114                 kfree(mqp);
1115
1116         return 0;
1117 }
1118
1119 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1120 {
1121         switch (type) {
1122         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1123         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1124         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1125         case MLX4_IB_QPT_XRC_INI:
1126         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1127         case MLX4_IB_QPT_SMI:
1128         case MLX4_IB_QPT_GSI:
1129         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1130
1131         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1132         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1133                                                 MLX4_QP_ST_MLX : -1);
1134         case MLX4_IB_QPT_PROXY_SMI:
1135         case MLX4_IB_QPT_TUN_SMI:
1136         case MLX4_IB_QPT_PROXY_GSI:
1137         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1138                                                 MLX4_QP_ST_UD : -1);
1139         default:                        return -1;
1140         }
1141 }
1142
1143 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1144                                    int attr_mask)
1145 {
1146         u8 dest_rd_atomic;
1147         u32 access_flags;
1148         u32 hw_access_flags = 0;
1149
1150         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1151                 dest_rd_atomic = attr->max_dest_rd_atomic;
1152         else
1153                 dest_rd_atomic = qp->resp_depth;
1154
1155         if (attr_mask & IB_QP_ACCESS_FLAGS)
1156                 access_flags = attr->qp_access_flags;
1157         else
1158                 access_flags = qp->atomic_rd_en;
1159
1160         if (!dest_rd_atomic)
1161                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1162
1163         if (access_flags & IB_ACCESS_REMOTE_READ)
1164                 hw_access_flags |= MLX4_QP_BIT_RRE;
1165         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1166                 hw_access_flags |= MLX4_QP_BIT_RAE;
1167         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1168                 hw_access_flags |= MLX4_QP_BIT_RWE;
1169
1170         return cpu_to_be32(hw_access_flags);
1171 }
1172
1173 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1174                             int attr_mask)
1175 {
1176         if (attr_mask & IB_QP_PKEY_INDEX)
1177                 sqp->pkey_index = attr->pkey_index;
1178         if (attr_mask & IB_QP_QKEY)
1179                 sqp->qkey = attr->qkey;
1180         if (attr_mask & IB_QP_SQ_PSN)
1181                 sqp->send_psn = attr->sq_psn;
1182 }
1183
1184 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1185 {
1186         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1187 }
1188
1189 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1190                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1191                           u8 port)
1192 {
1193         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1194                 IB_LINK_LAYER_ETHERNET;
1195         int vidx;
1196         int smac_index;
1197
1198
1199         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1200         path->rlid          = cpu_to_be16(ah->dlid);
1201         if (ah->static_rate) {
1202                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1203                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1204                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1205                         --path->static_rate;
1206         } else
1207                 path->static_rate = 0;
1208
1209         if (ah->ah_flags & IB_AH_GRH) {
1210                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1211                         pr_err("sgid_index (%u) too large. max is %d\n",
1212                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1213                         return -1;
1214                 }
1215
1216                 path->grh_mylmc |= 1 << 7;
1217                 path->mgid_index = ah->grh.sgid_index;
1218                 path->hop_limit  = ah->grh.hop_limit;
1219                 path->tclass_flowlabel =
1220                         cpu_to_be32((ah->grh.traffic_class << 20) |
1221                                     (ah->grh.flow_label));
1222                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1223         }
1224
1225         if (is_eth) {
1226                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1227                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1228
1229                 if (!(ah->ah_flags & IB_AH_GRH))
1230                         return -1;
1231
1232                 memcpy(path->dmac, ah->dmac, ETH_ALEN);
1233                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1234                 /* find the index  into MAC table for IBoE */
1235                 if (!is_zero_ether_addr((const u8 *)&smac)) {
1236                         if (mlx4_find_cached_mac(dev->dev, port, smac,
1237                                                  &smac_index))
1238                                 return -ENOENT;
1239                 } else {
1240                         smac_index = 0;
1241                 }
1242
1243                 path->grh_mylmc &= 0x80 | smac_index;
1244
1245                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1246                 if (vlan_tag < 0x1000) {
1247                         if (mlx4_find_cached_vlan(dev->dev, port, vlan_tag, &vidx))
1248                                 return -ENOENT;
1249
1250                         path->vlan_index = vidx;
1251                         path->fl = 1 << 6;
1252                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1253                 }
1254         } else
1255                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1256                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1257
1258         return 0;
1259 }
1260
1261 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1262                          enum ib_qp_attr_mask qp_attr_mask,
1263                          struct mlx4_qp_path *path, u8 port)
1264 {
1265         return _mlx4_set_path(dev, &qp->ah_attr,
1266                               mlx4_mac_to_u64((u8 *)qp->smac),
1267                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1268                               path, port);
1269 }
1270
1271 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1272                              const struct ib_qp_attr *qp,
1273                              enum ib_qp_attr_mask qp_attr_mask,
1274                              struct mlx4_qp_path *path, u8 port)
1275 {
1276         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1277                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1278                               (qp_attr_mask & IB_QP_ALT_VID) ?
1279                               qp->alt_vlan_id : 0xffff,
1280                               path, port);
1281 }
1282
1283 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1284 {
1285         struct mlx4_ib_gid_entry *ge, *tmp;
1286
1287         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1288                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1289                         ge->added = 1;
1290                         ge->port = qp->port;
1291                 }
1292         }
1293 }
1294
1295 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1296                                const struct ib_qp_attr *attr, int attr_mask,
1297                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1298 {
1299         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1300         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1301         struct mlx4_ib_pd *pd;
1302         struct mlx4_ib_cq *send_cq, *recv_cq;
1303         struct mlx4_qp_context *context;
1304         enum mlx4_qp_optpar optpar = 0;
1305         int sqd_event;
1306         int steer_qp = 0;
1307         int err = -EINVAL;
1308
1309         context = kzalloc(sizeof *context, GFP_KERNEL);
1310         if (!context)
1311                 return -ENOMEM;
1312
1313         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1314                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1315
1316         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1317                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1318         else {
1319                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1320                 switch (attr->path_mig_state) {
1321                 case IB_MIG_MIGRATED:
1322                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1323                         break;
1324                 case IB_MIG_REARM:
1325                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1326                         break;
1327                 case IB_MIG_ARMED:
1328                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1329                         break;
1330                 }
1331         }
1332
1333         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1334                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1335         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1336                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1337         else if (ibqp->qp_type == IB_QPT_UD) {
1338                 if (qp->flags & MLX4_IB_QP_LSO)
1339                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1340                                               ilog2(dev->dev->caps.max_gso_sz);
1341                 else
1342                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1343         } else if (attr_mask & IB_QP_PATH_MTU) {
1344                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1345                         pr_err("path MTU (%u) is invalid\n",
1346                                attr->path_mtu);
1347                         goto out;
1348                 }
1349                 context->mtu_msgmax = (attr->path_mtu << 5) |
1350                         ilog2(dev->dev->caps.max_msg_sz);
1351         }
1352
1353         if (qp->rq.wqe_cnt)
1354                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1355         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1356
1357         if (qp->sq.wqe_cnt)
1358                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1359         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1360
1361         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1362                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1363                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1364                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1365                         context->param3 |= cpu_to_be32(1 << 30);
1366         }
1367
1368         if (qp->ibqp.uobject)
1369                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1370         else
1371                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1372
1373         if (attr_mask & IB_QP_DEST_QPN)
1374                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1375
1376         if (attr_mask & IB_QP_PORT) {
1377                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1378                     !(attr_mask & IB_QP_AV)) {
1379                         mlx4_set_sched(&context->pri_path, attr->port_num);
1380                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1381                 }
1382         }
1383
1384         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1385                 if (dev->counters[qp->port - 1] != -1) {
1386                         context->pri_path.counter_index =
1387                                                 dev->counters[qp->port - 1];
1388                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1389                 } else
1390                         context->pri_path.counter_index = 0xff;
1391
1392                 if (qp->flags & MLX4_IB_QP_NETIF) {
1393                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1394                         steer_qp = 1;
1395                 }
1396         }
1397
1398         if (attr_mask & IB_QP_PKEY_INDEX) {
1399                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1400                         context->pri_path.disable_pkey_check = 0x40;
1401                 context->pri_path.pkey_index = attr->pkey_index;
1402                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1403         }
1404
1405         if (attr_mask & IB_QP_AV) {
1406                 if (mlx4_set_path(dev, attr, attr_mask, &context->pri_path,
1407                                   attr_mask & IB_QP_PORT ?
1408                                   attr->port_num : qp->port))
1409                         goto out;
1410
1411                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1412                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1413         }
1414
1415         if (attr_mask & IB_QP_TIMEOUT) {
1416                 context->pri_path.ackto |= attr->timeout << 3;
1417                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1418         }
1419
1420         if (attr_mask & IB_QP_ALT_PATH) {
1421                 if (attr->alt_port_num == 0 ||
1422                     attr->alt_port_num > dev->dev->caps.num_ports)
1423                         goto out;
1424
1425                 if (attr->alt_pkey_index >=
1426                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1427                         goto out;
1428
1429                 if (mlx4_set_alt_path(dev, attr, attr_mask, &context->alt_path,
1430                                       attr->alt_port_num))
1431                         goto out;
1432
1433                 context->alt_path.pkey_index = attr->alt_pkey_index;
1434                 context->alt_path.ackto = attr->alt_timeout << 3;
1435                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1436         }
1437
1438         pd = get_pd(qp);
1439         get_cqs(qp, &send_cq, &recv_cq);
1440         context->pd       = cpu_to_be32(pd->pdn);
1441         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1442         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1443         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1444
1445         /* Set "fast registration enabled" for all kernel QPs */
1446         if (!qp->ibqp.uobject)
1447                 context->params1 |= cpu_to_be32(1 << 11);
1448
1449         if (attr_mask & IB_QP_RNR_RETRY) {
1450                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1451                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1452         }
1453
1454         if (attr_mask & IB_QP_RETRY_CNT) {
1455                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1456                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1457         }
1458
1459         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1460                 if (attr->max_rd_atomic)
1461                         context->params1 |=
1462                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1463                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1464         }
1465
1466         if (attr_mask & IB_QP_SQ_PSN)
1467                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1468
1469         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1470                 if (attr->max_dest_rd_atomic)
1471                         context->params2 |=
1472                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1473                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1474         }
1475
1476         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1477                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1478                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1479         }
1480
1481         if (ibqp->srq)
1482                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1483
1484         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1485                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1486                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1487         }
1488         if (attr_mask & IB_QP_RQ_PSN)
1489                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1490
1491         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1492         if (attr_mask & IB_QP_QKEY) {
1493                 if (qp->mlx4_ib_qp_type &
1494                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1495                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1496                 else {
1497                         if (mlx4_is_mfunc(dev->dev) &&
1498                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1499                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1500                             MLX4_RESERVED_QKEY_BASE) {
1501                                 pr_err("Cannot use reserved QKEY"
1502                                        " 0x%x (range 0xffff0000..0xffffffff"
1503                                        " is reserved)\n", attr->qkey);
1504                                 err = -EINVAL;
1505                                 goto out;
1506                         }
1507                         context->qkey = cpu_to_be32(attr->qkey);
1508                 }
1509                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1510         }
1511
1512         if (ibqp->srq)
1513                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1514
1515         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1516                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1517
1518         if (cur_state == IB_QPS_INIT &&
1519             new_state == IB_QPS_RTR  &&
1520             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1521              ibqp->qp_type == IB_QPT_UD ||
1522              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1523                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1524                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1525                     qp->mlx4_ib_qp_type &
1526                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1527                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1528                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1529                                 context->pri_path.fl = 0x80;
1530                 } else {
1531                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1532                                 context->pri_path.fl = 0x80;
1533                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1534                 }
1535         }
1536
1537         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
1538                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1539                                         MLX4_IB_LINK_TYPE_ETH;
1540
1541         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1542                 int is_eth = rdma_port_get_link_layer(
1543                                 &dev->ib_dev, qp->port) ==
1544                                 IB_LINK_LAYER_ETHERNET;
1545                 if (is_eth) {
1546                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1547                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1548                 }
1549         }
1550
1551
1552         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1553             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1554                 sqd_event = 1;
1555         else
1556                 sqd_event = 0;
1557
1558         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1559                 context->rlkey |= (1 << 4);
1560
1561         /*
1562          * Before passing a kernel QP to the HW, make sure that the
1563          * ownership bits of the send queue are set and the SQ
1564          * headroom is stamped so that the hardware doesn't start
1565          * processing stale work requests.
1566          */
1567         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1568                 struct mlx4_wqe_ctrl_seg *ctrl;
1569                 int i;
1570
1571                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1572                         ctrl = get_send_wqe(qp, i);
1573                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1574                         if (qp->sq_max_wqes_per_wr == 1)
1575                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1576
1577                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1578                 }
1579         }
1580
1581         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1582                              to_mlx4_state(new_state), context, optpar,
1583                              sqd_event, &qp->mqp);
1584         if (err)
1585                 goto out;
1586
1587         qp->state = new_state;
1588
1589         if (attr_mask & IB_QP_ACCESS_FLAGS)
1590                 qp->atomic_rd_en = attr->qp_access_flags;
1591         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1592                 qp->resp_depth = attr->max_dest_rd_atomic;
1593         if (attr_mask & IB_QP_PORT) {
1594                 qp->port = attr->port_num;
1595                 update_mcg_macs(dev, qp);
1596         }
1597         if (attr_mask & IB_QP_ALT_PATH)
1598                 qp->alt_port = attr->alt_port_num;
1599
1600         if (is_sqp(dev, qp))
1601                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1602
1603         /*
1604          * If we moved QP0 to RTR, bring the IB link up; if we moved
1605          * QP0 to RESET or ERROR, bring the link back down.
1606          */
1607         if (is_qp0(dev, qp)) {
1608                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1609                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1610                                 pr_warn("INIT_PORT failed for port %d\n",
1611                                        qp->port);
1612
1613                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1614                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1615                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1616         }
1617
1618         /*
1619          * If we moved a kernel QP to RESET, clean up all old CQ
1620          * entries and reinitialize the QP.
1621          */
1622         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1623                 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1624                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1625                 if (send_cq != recv_cq)
1626                         mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1627
1628                 qp->rq.head = 0;
1629                 qp->rq.tail = 0;
1630                 qp->sq.head = 0;
1631                 qp->sq.tail = 0;
1632                 qp->sq_next_wqe = 0;
1633                 if (qp->rq.wqe_cnt)
1634                         *qp->db.db  = 0;
1635
1636                 if (qp->flags & MLX4_IB_QP_NETIF)
1637                         mlx4_ib_steer_qp_reg(dev, qp, 0);
1638         }
1639
1640 out:
1641         if (err && steer_qp)
1642                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1643         kfree(context);
1644         return err;
1645 }
1646
1647 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1648                       int attr_mask, struct ib_udata *udata)
1649 {
1650         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1651         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1652         enum ib_qp_state cur_state, new_state;
1653         int err = -EINVAL;
1654         int ll;
1655         mutex_lock(&qp->mutex);
1656
1657         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1658         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1659
1660         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1661                 ll = IB_LINK_LAYER_UNSPECIFIED;
1662         } else {
1663                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1664                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1665         }
1666
1667         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1668                                 attr_mask, ll)) {
1669                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1670                          "for transition %d to %d. qp_type %d,"
1671                          " attr_mask 0x%x\n",
1672                          ibqp->qp_num, cur_state, new_state,
1673                          ibqp->qp_type, attr_mask);
1674                 goto out;
1675         }
1676
1677         if ((attr_mask & IB_QP_PORT) &&
1678             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1679                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1680                          "for transition %d to %d. qp_type %d\n",
1681                          ibqp->qp_num, attr->port_num, cur_state,
1682                          new_state, ibqp->qp_type);
1683                 goto out;
1684         }
1685
1686         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1687             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1688              IB_LINK_LAYER_ETHERNET))
1689                 goto out;
1690
1691         if (attr_mask & IB_QP_PKEY_INDEX) {
1692                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1693                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1694                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1695                                  "for transition %d to %d. qp_type %d\n",
1696                                  ibqp->qp_num, attr->pkey_index, cur_state,
1697                                  new_state, ibqp->qp_type);
1698                         goto out;
1699                 }
1700         }
1701
1702         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1703             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1704                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1705                          "Transition %d to %d. qp_type %d\n",
1706                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1707                          new_state, ibqp->qp_type);
1708                 goto out;
1709         }
1710
1711         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1712             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1713                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1714                          "Transition %d to %d. qp_type %d\n",
1715                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1716                          new_state, ibqp->qp_type);
1717                 goto out;
1718         }
1719
1720         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1721                 err = 0;
1722                 goto out;
1723         }
1724
1725         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1726
1727 out:
1728         mutex_unlock(&qp->mutex);
1729         return err;
1730 }
1731
1732 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1733                                   struct ib_send_wr *wr,
1734                                   void *wqe, unsigned *mlx_seg_len)
1735 {
1736         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1737         struct ib_device *ib_dev = &mdev->ib_dev;
1738         struct mlx4_wqe_mlx_seg *mlx = wqe;
1739         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1740         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1741         u16 pkey;
1742         u32 qkey;
1743         int send_size;
1744         int header_size;
1745         int spc;
1746         int i;
1747
1748         if (wr->opcode != IB_WR_SEND)
1749                 return -EINVAL;
1750
1751         send_size = 0;
1752
1753         for (i = 0; i < wr->num_sge; ++i)
1754                 send_size += wr->sg_list[i].length;
1755
1756         /* for proxy-qp0 sends, need to add in size of tunnel header */
1757         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1758         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1759                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1760
1761         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1762
1763         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1764                 sqp->ud_header.lrh.service_level =
1765                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1766                 sqp->ud_header.lrh.destination_lid =
1767                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1768                 sqp->ud_header.lrh.source_lid =
1769                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1770         }
1771
1772         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1773
1774         /* force loopback */
1775         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
1776         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1777
1778         sqp->ud_header.lrh.virtual_lane    = 0;
1779         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1780         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
1781         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1782         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
1783                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1784         else
1785                 sqp->ud_header.bth.destination_qpn =
1786                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1787
1788         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1789         if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
1790                 return -EINVAL;
1791         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
1792         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
1793
1794         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1795         sqp->ud_header.immediate_present = 0;
1796
1797         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1798
1799         /*
1800          * Inline data segments may not cross a 64 byte boundary.  If
1801          * our UD header is bigger than the space available up to the
1802          * next 64 byte boundary in the WQE, use two inline data
1803          * segments to hold the UD header.
1804          */
1805         spc = MLX4_INLINE_ALIGN -
1806               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1807         if (header_size <= spc) {
1808                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1809                 memcpy(inl + 1, sqp->header_buf, header_size);
1810                 i = 1;
1811         } else {
1812                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1813                 memcpy(inl + 1, sqp->header_buf, spc);
1814
1815                 inl = (void *) (inl + 1) + spc;
1816                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1817                 /*
1818                  * Need a barrier here to make sure all the data is
1819                  * visible before the byte_count field is set.
1820                  * Otherwise the HCA prefetcher could grab the 64-byte
1821                  * chunk with this inline segment and get a valid (!=
1822                  * 0xffffffff) byte count but stale data, and end up
1823                  * generating a packet with bad headers.
1824                  *
1825                  * The first inline segment's byte_count field doesn't
1826                  * need a barrier, because it comes after a
1827                  * control/MLX segment and therefore is at an offset
1828                  * of 16 mod 64.
1829                  */
1830                 wmb();
1831                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1832                 i = 2;
1833         }
1834
1835         *mlx_seg_len =
1836         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1837         return 0;
1838 }
1839
1840 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1841                             void *wqe, unsigned *mlx_seg_len)
1842 {
1843         struct ib_device *ib_dev = sqp->qp.ibqp.device;
1844         struct mlx4_wqe_mlx_seg *mlx = wqe;
1845         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
1846         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1847         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1848         union ib_gid sgid;
1849         u16 pkey;
1850         int send_size;
1851         int header_size;
1852         int spc;
1853         int i;
1854         int err = 0;
1855         u16 vlan = 0xffff;
1856         bool is_eth;
1857         bool is_vlan = false;
1858         bool is_grh;
1859
1860         send_size = 0;
1861         for (i = 0; i < wr->num_sge; ++i)
1862                 send_size += wr->sg_list[i].length;
1863
1864         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1865         is_grh = mlx4_ib_ah_grh_present(ah);
1866         if (is_eth) {
1867                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1868                         /* When multi-function is enabled, the ib_core gid
1869                          * indexes don't necessarily match the hw ones, so
1870                          * we must use our own cache */
1871                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
1872                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
1873                                                            ah->av.ib.gid_index, &sgid.raw[0]);
1874                         if (err)
1875                                 return err;
1876                 } else  {
1877                         err = ib_get_cached_gid(ib_dev,
1878                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
1879                                                 ah->av.ib.gid_index, &sgid);
1880                         if (err)
1881                                 return err;
1882                 }
1883
1884                 if (ah->av.eth.vlan != 0xffff) {
1885                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
1886                         is_vlan = 1;
1887                 }
1888         }
1889         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
1890
1891         if (!is_eth) {
1892                 sqp->ud_header.lrh.service_level =
1893                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1894                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1895                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1896         }
1897
1898         if (is_grh) {
1899                 sqp->ud_header.grh.traffic_class =
1900                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
1901                 sqp->ud_header.grh.flow_label    =
1902                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1903                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
1904                 if (is_eth)
1905                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
1906                 else {
1907                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1908                         /* When multi-function is enabled, the ib_core gid
1909                          * indexes don't necessarily match the hw ones, so
1910                          * we must use our own cache */
1911                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
1912                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1913                                                        subnet_prefix;
1914                         sqp->ud_header.grh.source_gid.global.interface_id =
1915                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1916                                                guid_cache[ah->av.ib.gid_index];
1917                 } else
1918                         ib_get_cached_gid(ib_dev,
1919                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
1920                                           ah->av.ib.gid_index,
1921                                           &sqp->ud_header.grh.source_gid);
1922                 }
1923                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1924                        ah->av.ib.dgid, 16);
1925         }
1926
1927         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1928
1929         if (!is_eth) {
1930                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1931                                           (sqp->ud_header.lrh.destination_lid ==
1932                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1933                                           (sqp->ud_header.lrh.service_level << 8));
1934                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
1935                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
1936                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1937         }
1938
1939         switch (wr->opcode) {
1940         case IB_WR_SEND:
1941                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1942                 sqp->ud_header.immediate_present = 0;
1943                 break;
1944         case IB_WR_SEND_WITH_IMM:
1945                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1946                 sqp->ud_header.immediate_present = 1;
1947                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1948                 break;
1949         default:
1950                 return -EINVAL;
1951         }
1952
1953         if (is_eth) {
1954                 u8 smac[6];
1955                 struct in6_addr in6;
1956
1957                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
1958
1959                 mlx->sched_prio = cpu_to_be16(pcp);
1960
1961                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1962                 /* FIXME: cache smac value? */
1963                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
1964                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
1965                 memcpy(&in6, sgid.raw, sizeof(in6));
1966                 rdma_get_ll_mac(&in6, smac);
1967                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1968                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1969                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
1970                 if (!is_vlan) {
1971                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1972                 } else {
1973                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1974                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
1975                 }
1976         } else {
1977                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1978                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1979                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1980         }
1981         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1982         if (!sqp->qp.ibqp.qp_num)
1983                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1984         else
1985                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1986         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1987         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1988         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1989         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1990                                                sqp->qkey : wr->wr.ud.remote_qkey);
1991         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1992
1993         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1994
1995         if (0) {
1996                 pr_err("built UD header of size %d:\n", header_size);
1997                 for (i = 0; i < header_size / 4; ++i) {
1998                         if (i % 8 == 0)
1999                                 pr_err("  [%02x] ", i * 4);
2000                         pr_cont(" %08x",
2001                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2002                         if ((i + 1) % 8 == 0)
2003                                 pr_cont("\n");
2004                 }
2005                 pr_err("\n");
2006         }
2007
2008         /*
2009          * Inline data segments may not cross a 64 byte boundary.  If
2010          * our UD header is bigger than the space available up to the
2011          * next 64 byte boundary in the WQE, use two inline data
2012          * segments to hold the UD header.
2013          */
2014         spc = MLX4_INLINE_ALIGN -
2015                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2016         if (header_size <= spc) {
2017                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2018                 memcpy(inl + 1, sqp->header_buf, header_size);
2019                 i = 1;
2020         } else {
2021                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2022                 memcpy(inl + 1, sqp->header_buf, spc);
2023
2024                 inl = (void *) (inl + 1) + spc;
2025                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2026                 /*
2027                  * Need a barrier here to make sure all the data is
2028                  * visible before the byte_count field is set.
2029                  * Otherwise the HCA prefetcher could grab the 64-byte
2030                  * chunk with this inline segment and get a valid (!=
2031                  * 0xffffffff) byte count but stale data, and end up
2032                  * generating a packet with bad headers.
2033                  *
2034                  * The first inline segment's byte_count field doesn't
2035                  * need a barrier, because it comes after a
2036                  * control/MLX segment and therefore is at an offset
2037                  * of 16 mod 64.
2038                  */
2039                 wmb();
2040                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2041                 i = 2;
2042         }
2043
2044         *mlx_seg_len =
2045                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2046         return 0;
2047 }
2048
2049 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2050 {
2051         unsigned cur;
2052         struct mlx4_ib_cq *cq;
2053
2054         cur = wq->head - wq->tail;
2055         if (likely(cur + nreq < wq->max_post))
2056                 return 0;
2057
2058         cq = to_mcq(ib_cq);
2059         spin_lock(&cq->lock);
2060         cur = wq->head - wq->tail;
2061         spin_unlock(&cq->lock);
2062
2063         return cur + nreq >= wq->max_post;
2064 }
2065
2066 static __be32 convert_access(int acc)
2067 {
2068         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2069                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2070                (acc & IB_ACCESS_REMOTE_WRITE  ?
2071                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2072                (acc & IB_ACCESS_REMOTE_READ   ?
2073                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2074                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2075                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2076 }
2077
2078 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2079 {
2080         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2081         int i;
2082
2083         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2084                 mfrpl->mapped_page_list[i] =
2085                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2086                                     MLX4_MTT_FLAG_PRESENT);
2087
2088         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2089         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2090         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2091         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2092         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2093         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2094         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2095         fseg->reserved[0]       = 0;
2096         fseg->reserved[1]       = 0;
2097 }
2098
2099 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2100 {
2101         bseg->flags1 =
2102                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2103                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2104                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2105                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2106         bseg->flags2 = 0;
2107         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2108                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2109         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2110                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2111         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2112         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2113         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2114         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2115 }
2116
2117 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2118 {
2119         memset(iseg, 0, sizeof(*iseg));
2120         iseg->mem_key = cpu_to_be32(rkey);
2121 }
2122
2123 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2124                                           u64 remote_addr, u32 rkey)
2125 {
2126         rseg->raddr    = cpu_to_be64(remote_addr);
2127         rseg->rkey     = cpu_to_be32(rkey);
2128         rseg->reserved = 0;
2129 }
2130
2131 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2132 {
2133         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2134                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2135                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2136         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2137                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2138                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2139         } else {
2140                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2141                 aseg->compare  = 0;
2142         }
2143
2144 }
2145
2146 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2147                                   struct ib_send_wr *wr)
2148 {
2149         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2150         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2151         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2152         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2153 }
2154
2155 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2156                              struct ib_send_wr *wr)
2157 {
2158         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2159         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2160         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2161         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2162         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2163 }
2164
2165 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2166                                     struct mlx4_wqe_datagram_seg *dseg,
2167                                     struct ib_send_wr *wr, enum ib_qp_type qpt)
2168 {
2169         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2170         struct mlx4_av sqp_av = {0};
2171         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2172
2173         /* force loopback */
2174         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2175         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2176         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2177                         cpu_to_be32(0xf0000000);
2178
2179         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2180         /* This function used only for sending on QP1 proxies */
2181         dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2182         /* Use QKEY from the QP context, which is set by master */
2183         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2184 }
2185
2186 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2187 {
2188         struct mlx4_wqe_inline_seg *inl = wqe;
2189         struct mlx4_ib_tunnel_header hdr;
2190         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2191         int spc;
2192         int i;
2193
2194         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2195         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2196         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2197         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2198
2199         spc = MLX4_INLINE_ALIGN -
2200                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2201         if (sizeof (hdr) <= spc) {
2202                 memcpy(inl + 1, &hdr, sizeof (hdr));
2203                 wmb();
2204                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2205                 i = 1;
2206         } else {
2207                 memcpy(inl + 1, &hdr, spc);
2208                 wmb();
2209                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2210
2211                 inl = (void *) (inl + 1) + spc;
2212                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2213                 wmb();
2214                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2215                 i = 2;
2216         }
2217
2218         *mlx_seg_len =
2219                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2220 }
2221
2222 static void set_mlx_icrc_seg(void *dseg)
2223 {
2224         u32 *t = dseg;
2225         struct mlx4_wqe_inline_seg *iseg = dseg;
2226
2227         t[1] = 0;
2228
2229         /*
2230          * Need a barrier here before writing the byte_count field to
2231          * make sure that all the data is visible before the
2232          * byte_count field is set.  Otherwise, if the segment begins
2233          * a new cacheline, the HCA prefetcher could grab the 64-byte
2234          * chunk and get a valid (!= * 0xffffffff) byte count but
2235          * stale data, and end up sending the wrong data.
2236          */
2237         wmb();
2238
2239         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2240 }
2241
2242 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2243 {
2244         dseg->lkey       = cpu_to_be32(sg->lkey);
2245         dseg->addr       = cpu_to_be64(sg->addr);
2246
2247         /*
2248          * Need a barrier here before writing the byte_count field to
2249          * make sure that all the data is visible before the
2250          * byte_count field is set.  Otherwise, if the segment begins
2251          * a new cacheline, the HCA prefetcher could grab the 64-byte
2252          * chunk and get a valid (!= * 0xffffffff) byte count but
2253          * stale data, and end up sending the wrong data.
2254          */
2255         wmb();
2256
2257         dseg->byte_count = cpu_to_be32(sg->length);
2258 }
2259
2260 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2261 {
2262         dseg->byte_count = cpu_to_be32(sg->length);
2263         dseg->lkey       = cpu_to_be32(sg->lkey);
2264         dseg->addr       = cpu_to_be64(sg->addr);
2265 }
2266
2267 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2268                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2269                          __be32 *lso_hdr_sz, __be32 *blh)
2270 {
2271         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2272
2273         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2274                 *blh = cpu_to_be32(1 << 6);
2275
2276         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2277                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2278                 return -EINVAL;
2279
2280         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2281
2282         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2283                                    wr->wr.ud.hlen);
2284         *lso_seg_len = halign;
2285         return 0;
2286 }
2287
2288 static __be32 send_ieth(struct ib_send_wr *wr)
2289 {
2290         switch (wr->opcode) {
2291         case IB_WR_SEND_WITH_IMM:
2292         case IB_WR_RDMA_WRITE_WITH_IMM:
2293                 return wr->ex.imm_data;
2294
2295         case IB_WR_SEND_WITH_INV:
2296                 return cpu_to_be32(wr->ex.invalidate_rkey);
2297
2298         default:
2299                 return 0;
2300         }
2301 }
2302
2303 static void add_zero_len_inline(void *wqe)
2304 {
2305         struct mlx4_wqe_inline_seg *inl = wqe;
2306         memset(wqe, 0, 16);
2307         inl->byte_count = cpu_to_be32(1 << 31);
2308 }
2309
2310 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2311                       struct ib_send_wr **bad_wr)
2312 {
2313         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2314         void *wqe;
2315         struct mlx4_wqe_ctrl_seg *ctrl;
2316         struct mlx4_wqe_data_seg *dseg;
2317         unsigned long flags;
2318         int nreq;
2319         int err = 0;
2320         unsigned ind;
2321         int uninitialized_var(stamp);
2322         int uninitialized_var(size);
2323         unsigned uninitialized_var(seglen);
2324         __be32 dummy;
2325         __be32 *lso_wqe;
2326         __be32 uninitialized_var(lso_hdr_sz);
2327         __be32 blh;
2328         int i;
2329
2330         spin_lock_irqsave(&qp->sq.lock, flags);
2331
2332         ind = qp->sq_next_wqe;
2333
2334         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2335                 lso_wqe = &dummy;
2336                 blh = 0;
2337
2338                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2339                         err = -ENOMEM;
2340                         *bad_wr = wr;
2341                         goto out;
2342                 }
2343
2344                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2345                         err = -EINVAL;
2346                         *bad_wr = wr;
2347                         goto out;
2348                 }
2349
2350                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2351                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2352
2353                 ctrl->srcrb_flags =
2354                         (wr->send_flags & IB_SEND_SIGNALED ?
2355                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2356                         (wr->send_flags & IB_SEND_SOLICITED ?
2357                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2358                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2359                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2360                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2361                         qp->sq_signal_bits;
2362
2363                 ctrl->imm = send_ieth(wr);
2364
2365                 wqe += sizeof *ctrl;
2366                 size = sizeof *ctrl / 16;
2367
2368                 switch (qp->mlx4_ib_qp_type) {
2369                 case MLX4_IB_QPT_RC:
2370                 case MLX4_IB_QPT_UC:
2371                         switch (wr->opcode) {
2372                         case IB_WR_ATOMIC_CMP_AND_SWP:
2373                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2374                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2375                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2376                                               wr->wr.atomic.rkey);
2377                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2378
2379                                 set_atomic_seg(wqe, wr);
2380                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2381
2382                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2383                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2384
2385                                 break;
2386
2387                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2388                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2389                                               wr->wr.atomic.rkey);
2390                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2391
2392                                 set_masked_atomic_seg(wqe, wr);
2393                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2394
2395                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2396                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2397
2398                                 break;
2399
2400                         case IB_WR_RDMA_READ:
2401                         case IB_WR_RDMA_WRITE:
2402                         case IB_WR_RDMA_WRITE_WITH_IMM:
2403                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2404                                               wr->wr.rdma.rkey);
2405                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2406                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2407                                 break;
2408
2409                         case IB_WR_LOCAL_INV:
2410                                 ctrl->srcrb_flags |=
2411                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2412                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2413                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2414                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2415                                 break;
2416
2417                         case IB_WR_FAST_REG_MR:
2418                                 ctrl->srcrb_flags |=
2419                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2420                                 set_fmr_seg(wqe, wr);
2421                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2422                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2423                                 break;
2424
2425                         case IB_WR_BIND_MW:
2426                                 ctrl->srcrb_flags |=
2427                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2428                                 set_bind_seg(wqe, wr);
2429                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2430                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2431                                 break;
2432                         default:
2433                                 /* No extra segments required for sends */
2434                                 break;
2435                         }
2436                         break;
2437
2438                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2439                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2440                         if (unlikely(err)) {
2441                                 *bad_wr = wr;
2442                                 goto out;
2443                         }
2444                         wqe  += seglen;
2445                         size += seglen / 16;
2446                         break;
2447                 case MLX4_IB_QPT_TUN_SMI:
2448                 case MLX4_IB_QPT_TUN_GSI:
2449                         /* this is a UD qp used in MAD responses to slaves. */
2450                         set_datagram_seg(wqe, wr);
2451                         /* set the forced-loopback bit in the data seg av */
2452                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2453                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2454                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2455                         break;
2456                 case MLX4_IB_QPT_UD:
2457                         set_datagram_seg(wqe, wr);
2458                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2459                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2460
2461                         if (wr->opcode == IB_WR_LSO) {
2462                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2463                                 if (unlikely(err)) {
2464                                         *bad_wr = wr;
2465                                         goto out;
2466                                 }
2467                                 lso_wqe = (__be32 *) wqe;
2468                                 wqe  += seglen;
2469                                 size += seglen / 16;
2470                         }
2471                         break;
2472
2473                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2474                         if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) {
2475                                 err = -ENOSYS;
2476                                 *bad_wr = wr;
2477                                 goto out;
2478                         }
2479                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2480                         if (unlikely(err)) {
2481                                 *bad_wr = wr;
2482                                 goto out;
2483                         }
2484                         wqe  += seglen;
2485                         size += seglen / 16;
2486                         /* to start tunnel header on a cache-line boundary */
2487                         add_zero_len_inline(wqe);
2488                         wqe += 16;
2489                         size++;
2490                         build_tunnel_header(wr, wqe, &seglen);
2491                         wqe  += seglen;
2492                         size += seglen / 16;
2493                         break;
2494                 case MLX4_IB_QPT_PROXY_SMI:
2495                         /* don't allow QP0 sends on guests */
2496                         err = -ENOSYS;
2497                         *bad_wr = wr;
2498                         goto out;
2499                 case MLX4_IB_QPT_PROXY_GSI:
2500                         /* If we are tunneling special qps, this is a UD qp.
2501                          * In this case we first add a UD segment targeting
2502                          * the tunnel qp, and then add a header with address
2503                          * information */
2504                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type);
2505                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2506                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2507                         build_tunnel_header(wr, wqe, &seglen);
2508                         wqe  += seglen;
2509                         size += seglen / 16;
2510                         break;
2511
2512                 case MLX4_IB_QPT_SMI:
2513                 case MLX4_IB_QPT_GSI:
2514                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2515                         if (unlikely(err)) {
2516                                 *bad_wr = wr;
2517                                 goto out;
2518                         }
2519                         wqe  += seglen;
2520                         size += seglen / 16;
2521                         break;
2522
2523                 default:
2524                         break;
2525                 }
2526
2527                 /*
2528                  * Write data segments in reverse order, so as to
2529                  * overwrite cacheline stamp last within each
2530                  * cacheline.  This avoids issues with WQE
2531                  * prefetching.
2532                  */
2533
2534                 dseg = wqe;
2535                 dseg += wr->num_sge - 1;
2536                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2537
2538                 /* Add one more inline data segment for ICRC for MLX sends */
2539                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2540                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2541                              qp->mlx4_ib_qp_type &
2542                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2543                         set_mlx_icrc_seg(dseg + 1);
2544                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2545                 }
2546
2547                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2548                         set_data_seg(dseg, wr->sg_list + i);
2549
2550                 /*
2551                  * Possibly overwrite stamping in cacheline with LSO
2552                  * segment only after making sure all data segments
2553                  * are written.
2554                  */
2555                 wmb();
2556                 *lso_wqe = lso_hdr_sz;
2557
2558                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2559                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2560
2561                 /*
2562                  * Make sure descriptor is fully written before
2563                  * setting ownership bit (because HW can start
2564                  * executing as soon as we do).
2565                  */
2566                 wmb();
2567
2568                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2569                         *bad_wr = wr;
2570                         err = -EINVAL;
2571                         goto out;
2572                 }
2573
2574                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2575                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2576
2577                 stamp = ind + qp->sq_spare_wqes;
2578                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2579
2580                 /*
2581                  * We can improve latency by not stamping the last
2582                  * send queue WQE until after ringing the doorbell, so
2583                  * only stamp here if there are still more WQEs to post.
2584                  *
2585                  * Same optimization applies to padding with NOP wqe
2586                  * in case of WQE shrinking (used to prevent wrap-around
2587                  * in the middle of WR).
2588                  */
2589                 if (wr->next) {
2590                         stamp_send_wqe(qp, stamp, size * 16);
2591                         ind = pad_wraparound(qp, ind);
2592                 }
2593         }
2594
2595 out:
2596         if (likely(nreq)) {
2597                 qp->sq.head += nreq;
2598
2599                 /*
2600                  * Make sure that descriptors are written before
2601                  * doorbell record.
2602                  */
2603                 wmb();
2604
2605                 writel(qp->doorbell_qpn,
2606                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2607
2608                 /*
2609                  * Make sure doorbells don't leak out of SQ spinlock
2610                  * and reach the HCA out of order.
2611                  */
2612                 mmiowb();
2613
2614                 stamp_send_wqe(qp, stamp, size * 16);
2615
2616                 ind = pad_wraparound(qp, ind);
2617                 qp->sq_next_wqe = ind;
2618         }
2619
2620         spin_unlock_irqrestore(&qp->sq.lock, flags);
2621
2622         return err;
2623 }
2624
2625 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2626                       struct ib_recv_wr **bad_wr)
2627 {
2628         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2629         struct mlx4_wqe_data_seg *scat;
2630         unsigned long flags;
2631         int err = 0;
2632         int nreq;
2633         int ind;
2634         int max_gs;
2635         int i;
2636
2637         max_gs = qp->rq.max_gs;
2638         spin_lock_irqsave(&qp->rq.lock, flags);
2639
2640         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2641
2642         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2643                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2644                         err = -ENOMEM;
2645                         *bad_wr = wr;
2646                         goto out;
2647                 }
2648
2649                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2650                         err = -EINVAL;
2651                         *bad_wr = wr;
2652                         goto out;
2653                 }
2654
2655                 scat = get_recv_wqe(qp, ind);
2656
2657                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2658                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2659                         ib_dma_sync_single_for_device(ibqp->device,
2660                                                       qp->sqp_proxy_rcv[ind].map,
2661                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2662                                                       DMA_FROM_DEVICE);
2663                         scat->byte_count =
2664                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2665                         /* use dma lkey from upper layer entry */
2666                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2667                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2668                         scat++;
2669                         max_gs--;
2670                 }
2671
2672                 for (i = 0; i < wr->num_sge; ++i)
2673                         __set_data_seg(scat + i, wr->sg_list + i);
2674
2675                 if (i < max_gs) {
2676                         scat[i].byte_count = 0;
2677                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2678                         scat[i].addr       = 0;
2679                 }
2680
2681                 qp->rq.wrid[ind] = wr->wr_id;
2682
2683                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2684         }
2685
2686 out:
2687         if (likely(nreq)) {
2688                 qp->rq.head += nreq;
2689
2690                 /*
2691                  * Make sure that descriptors are written before
2692                  * doorbell record.
2693                  */
2694                 wmb();
2695
2696                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2697         }
2698
2699         spin_unlock_irqrestore(&qp->rq.lock, flags);
2700
2701         return err;
2702 }
2703
2704 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2705 {
2706         switch (mlx4_state) {
2707         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2708         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2709         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2710         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2711         case MLX4_QP_STATE_SQ_DRAINING:
2712         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2713         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2714         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2715         default:                     return -1;
2716         }
2717 }
2718
2719 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2720 {
2721         switch (mlx4_mig_state) {
2722         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2723         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2724         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2725         default: return -1;
2726         }
2727 }
2728
2729 static int to_ib_qp_access_flags(int mlx4_flags)
2730 {
2731         int ib_flags = 0;
2732
2733         if (mlx4_flags & MLX4_QP_BIT_RRE)
2734                 ib_flags |= IB_ACCESS_REMOTE_READ;
2735         if (mlx4_flags & MLX4_QP_BIT_RWE)
2736                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2737         if (mlx4_flags & MLX4_QP_BIT_RAE)
2738                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2739
2740         return ib_flags;
2741 }
2742
2743 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2744                                 struct mlx4_qp_path *path)
2745 {
2746         struct mlx4_dev *dev = ibdev->dev;
2747         int is_eth;
2748
2749         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2750         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2751
2752         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2753                 return;
2754
2755         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2756                 IB_LINK_LAYER_ETHERNET;
2757         if (is_eth)
2758                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2759                 ((path->sched_queue & 4) << 1);
2760         else
2761                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2762
2763         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2764         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2765         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2766         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2767         if (ib_ah_attr->ah_flags) {
2768                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2769                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2770                 ib_ah_attr->grh.traffic_class =
2771                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2772                 ib_ah_attr->grh.flow_label =
2773                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2774                 memcpy(ib_ah_attr->grh.dgid.raw,
2775                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2776         }
2777 }
2778
2779 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2780                      struct ib_qp_init_attr *qp_init_attr)
2781 {
2782         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2783         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2784         struct mlx4_qp_context context;
2785         int mlx4_state;
2786         int err = 0;
2787
2788         mutex_lock(&qp->mutex);
2789
2790         if (qp->state == IB_QPS_RESET) {
2791                 qp_attr->qp_state = IB_QPS_RESET;
2792                 goto done;
2793         }
2794
2795         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
2796         if (err) {
2797                 err = -EINVAL;
2798                 goto out;
2799         }
2800
2801         mlx4_state = be32_to_cpu(context.flags) >> 28;
2802
2803         qp->state                    = to_ib_qp_state(mlx4_state);
2804         qp_attr->qp_state            = qp->state;
2805         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
2806         qp_attr->path_mig_state      =
2807                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2808         qp_attr->qkey                = be32_to_cpu(context.qkey);
2809         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2810         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
2811         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
2812         qp_attr->qp_access_flags     =
2813                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2814
2815         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2816                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
2817                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
2818                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2819                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2820         }
2821
2822         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
2823         if (qp_attr->qp_state == IB_QPS_INIT)
2824                 qp_attr->port_num = qp->port;
2825         else
2826                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
2827
2828         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2829         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2830
2831         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2832
2833         qp_attr->max_dest_rd_atomic =
2834                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2835         qp_attr->min_rnr_timer      =
2836                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2837         qp_attr->timeout            = context.pri_path.ackto >> 3;
2838         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
2839         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
2840         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
2841
2842 done:
2843         qp_attr->cur_qp_state        = qp_attr->qp_state;
2844         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2845         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2846
2847         if (!ibqp->uobject) {
2848                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2849                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2850         } else {
2851                 qp_attr->cap.max_send_wr  = 0;
2852                 qp_attr->cap.max_send_sge = 0;
2853         }
2854
2855         /*
2856          * We don't support inline sends for kernel QPs (yet), and we
2857          * don't know what userspace's value should be.
2858          */
2859         qp_attr->cap.max_inline_data = 0;
2860
2861         qp_init_attr->cap            = qp_attr->cap;
2862
2863         qp_init_attr->create_flags = 0;
2864         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2865                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2866
2867         if (qp->flags & MLX4_IB_QP_LSO)
2868                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2869
2870         if (qp->flags & MLX4_IB_QP_NETIF)
2871                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
2872
2873         qp_init_attr->sq_sig_type =
2874                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
2875                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2876
2877 out:
2878         mutex_unlock(&qp->mutex);
2879         return err;
2880 }
2881