drivers/infiniband/hw/mlx5/cq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kref.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/ib_cache.h>
  37 #include "mlx5_ib.h"
  38 #include "user.h"
  39
  40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
  41 {
  42         struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  43
  44         ibcq->comp_handler(ibcq, ibcq->cq_context);
  45 }
  46
  47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
  48 {
  49         struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
  50         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
  51         struct ib_cq *ibcq = &cq->ibcq;
  52         struct ib_event event;
  53
  54         if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
  55                 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
  56                              type, mcq->cqn);
  57                 return;
  58         }
  59
  60         if (ibcq->event_handler) {
  61                 event.device     = &dev->ib_dev;
  62                 event.event      = IB_EVENT_CQ_ERR;
  63                 event.element.cq = ibcq;
  64                 ibcq->event_handler(&event, ibcq->cq_context);
  65         }
  66 }
  67
  68 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
  69 {
  70         return mlx5_buf_offset(&buf->buf, n * size);
  71 }
  72
  73 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
  74 {
  75         return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
  76 }
  77
  78 static u8 sw_ownership_bit(int n, int nent)
  79 {
  80         return (n & nent) ? 1 : 0;
  81 }
  82
  83 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
  84 {
  85         void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  86         struct mlx5_cqe64 *cqe64;
  87
  88         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
  89
  90         if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
  91             !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
  92                 return cqe;
  93         } else {
  94                 return NULL;
  95         }
  96 }
  97
  98 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
  99 {
 100         return get_sw_cqe(cq, cq->mcq.cons_index);
 101 }
 102
 103 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
 104 {
 105         switch (wq->wr_data[idx]) {
 106         case MLX5_IB_WR_UMR:
 107                 return 0;
 108
 109         case IB_WR_LOCAL_INV:
 110                 return IB_WC_LOCAL_INV;
 111
 112         case IB_WR_REG_MR:
 113                 return IB_WC_REG_MR;
 114
 115         default:
 116                 pr_warn("unknown completion status\n");
 117                 return 0;
 118         }
 119 }
 120
 121 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 122                             struct mlx5_ib_wq *wq, int idx)
 123 {
 124         wc->wc_flags = 0;
 125         switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
 126         case MLX5_OPCODE_RDMA_WRITE_IMM:
 127                 wc->wc_flags |= IB_WC_WITH_IMM;
 128         case MLX5_OPCODE_RDMA_WRITE:
 129                 wc->opcode    = IB_WC_RDMA_WRITE;
 130                 break;
 131         case MLX5_OPCODE_SEND_IMM:
 132                 wc->wc_flags |= IB_WC_WITH_IMM;
 133         case MLX5_OPCODE_SEND:
 134         case MLX5_OPCODE_SEND_INVAL:
 135                 wc->opcode    = IB_WC_SEND;
 136                 break;
 137         case MLX5_OPCODE_RDMA_READ:
 138                 wc->opcode    = IB_WC_RDMA_READ;
 139                 wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
 140                 break;
 141         case MLX5_OPCODE_ATOMIC_CS:
 142                 wc->opcode    = IB_WC_COMP_SWAP;
 143                 wc->byte_len  = 8;
 144                 break;
 145         case MLX5_OPCODE_ATOMIC_FA:
 146                 wc->opcode    = IB_WC_FETCH_ADD;
 147                 wc->byte_len  = 8;
 148                 break;
 149         case MLX5_OPCODE_ATOMIC_MASKED_CS:
 150                 wc->opcode    = IB_WC_MASKED_COMP_SWAP;
 151                 wc->byte_len  = 8;
 152                 break;
 153         case MLX5_OPCODE_ATOMIC_MASKED_FA:
 154                 wc->opcode    = IB_WC_MASKED_FETCH_ADD;
 155                 wc->byte_len  = 8;
 156                 break;
 157         case MLX5_OPCODE_UMR:
 158                 wc->opcode = get_umr_comp(wq, idx);
 159                 break;
 160         }
 161 }
 162
 163 enum {
 164         MLX5_GRH_IN_BUFFER = 1,
 165         MLX5_GRH_IN_CQE    = 2,
 166 };
 167
 168 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
 169                              struct mlx5_ib_qp *qp)
 170 {
 171         enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
 172         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
 173         struct mlx5_ib_srq *srq;
 174         struct mlx5_ib_wq *wq;
 175         u16 wqe_ctr;
 176         u8 g;
 177
 178         if (qp->ibqp.srq || qp->ibqp.xrcd) {
 179                 struct mlx5_core_srq *msrq = NULL;
 180
 181                 if (qp->ibqp.xrcd) {
 182                         msrq = mlx5_core_get_srq(dev->mdev,
 183                                                  be32_to_cpu(cqe->srqn));
 184                         srq = to_mibsrq(msrq);
 185                 } else {
 186                         srq = to_msrq(qp->ibqp.srq);
 187                 }
 188                 if (srq) {
 189                         wqe_ctr = be16_to_cpu(cqe->wqe_counter);
 190                         wc->wr_id = srq->wrid[wqe_ctr];
 191                         mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 192                         if (msrq && atomic_dec_and_test(&msrq->refcount))
 193                                 complete(&msrq->free);
 194                 }
 195         } else {
 196                 wq        = &qp->rq;
 197                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 198                 ++wq->tail;
 199         }
 200         wc->byte_len = be32_to_cpu(cqe->byte_cnt);
 201
 202         switch (cqe->op_own >> 4) {
 203         case MLX5_CQE_RESP_WR_IMM:
 204                 wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
 205                 wc->wc_flags    = IB_WC_WITH_IMM;
 206                 wc->ex.imm_data = cqe->imm_inval_pkey;
 207                 break;
 208         case MLX5_CQE_RESP_SEND:
 209                 wc->opcode   = IB_WC_RECV;
 210                 wc->wc_flags = IB_WC_IP_CSUM_OK;
 211                 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
 212                                (cqe->hds_ip_ext & CQE_L4_OK))))
 213                         wc->wc_flags = 0;
 214                 break;
 215         case MLX5_CQE_RESP_SEND_IMM:
 216                 wc->opcode      = IB_WC_RECV;
 217                 wc->wc_flags    = IB_WC_WITH_IMM;
 218                 wc->ex.imm_data = cqe->imm_inval_pkey;
 219                 break;
 220         case MLX5_CQE_RESP_SEND_INV:
 221                 wc->opcode      = IB_WC_RECV;
 222                 wc->wc_flags    = IB_WC_WITH_INVALIDATE;
 223                 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
 224                 break;
 225         }
 226         wc->slid           = be16_to_cpu(cqe->slid);
 227         wc->sl             = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
 228         wc->src_qp         = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
 229         wc->dlid_path_bits = cqe->ml_path;
 230         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
 231         wc->wc_flags |= g ? IB_WC_GRH : 0;
 232         if (unlikely(is_qp1(qp->ibqp.qp_type))) {
 233                 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
 234
 235                 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
 236                                     &wc->pkey_index);
 237         } else {
 238                 wc->pkey_index = 0;
 239         }
 240
 241         if (ll != IB_LINK_LAYER_ETHERNET)
 242                 return;
 243
 244         switch (wc->sl & 0x3) {
 245         case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
 246                 wc->network_hdr_type = RDMA_NETWORK_IB;
 247                 break;
 248         case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
 249                 wc->network_hdr_type = RDMA_NETWORK_IPV6;
 250                 break;
 251         case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
 252                 wc->network_hdr_type = RDMA_NETWORK_IPV4;
 253                 break;
 254         }
 255         wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
 256 }
 257
 258 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
 259 {
 260         __be32 *p = (__be32 *)cqe;
 261         int i;
 262
 263         mlx5_ib_warn(dev, "dump error cqe\n");
 264         for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
 265                 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
 266                         be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 267                         be32_to_cpu(p[3]));
 268 }
 269
 270 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
 271                                   struct mlx5_err_cqe *cqe,
 272                                   struct ib_wc *wc)
 273 {
 274         int dump = 1;
 275
 276         switch (cqe->syndrome) {
 277         case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
 278                 wc->status = IB_WC_LOC_LEN_ERR;
 279                 break;
 280         case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
 281                 wc->status = IB_WC_LOC_QP_OP_ERR;
 282                 break;
 283         case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
 284                 wc->status = IB_WC_LOC_PROT_ERR;
 285                 break;
 286         case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
 287                 dump = 0;
 288                 wc->status = IB_WC_WR_FLUSH_ERR;
 289                 break;
 290         case MLX5_CQE_SYNDROME_MW_BIND_ERR:
 291                 wc->status = IB_WC_MW_BIND_ERR;
 292                 break;
 293         case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
 294                 wc->status = IB_WC_BAD_RESP_ERR;
 295                 break;
 296         case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
 297                 wc->status = IB_WC_LOC_ACCESS_ERR;
 298                 break;
 299         case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
 300                 wc->status = IB_WC_REM_INV_REQ_ERR;
 301                 break;
 302         case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
 303                 wc->status = IB_WC_REM_ACCESS_ERR;
 304                 break;
 305         case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
 306                 wc->status = IB_WC_REM_OP_ERR;
 307                 break;
 308         case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
 309                 wc->status = IB_WC_RETRY_EXC_ERR;
 310                 dump = 0;
 311                 break;
 312         case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
 313                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
 314                 dump = 0;
 315                 break;
 316         case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
 317                 wc->status = IB_WC_REM_ABORT_ERR;
 318                 break;
 319         default:
 320                 wc->status = IB_WC_GENERAL_ERR;
 321                 break;
 322         }
 323
 324         wc->vendor_err = cqe->vendor_err_synd;
 325         if (dump)
 326                 dump_cqe(dev, cqe);
 327 }
 328
 329 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
 330 {
 331         /* TBD: waiting decision
 332         */
 333         return 0;
 334 }
 335
 336 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
 337 {
 338         struct mlx5_wqe_data_seg *dpseg;
 339         void *addr;
 340
 341         dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
 342                 sizeof(struct mlx5_wqe_raddr_seg) +
 343                 sizeof(struct mlx5_wqe_atomic_seg);
 344         addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
 345         return addr;
 346 }
 347
 348 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
 349                           uint16_t idx)
 350 {
 351         void *addr;
 352         int byte_count;
 353         int i;
 354
 355         if (!is_atomic_response(qp, idx))
 356                 return;
 357
 358         byte_count = be32_to_cpu(cqe64->byte_cnt);
 359         addr = mlx5_get_atomic_laddr(qp, idx);
 360
 361         if (byte_count == 4) {
 362                 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
 363         } else {
 364                 for (i = 0; i < byte_count; i += 8) {
 365                         *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
 366                         addr += 8;
 367                 }
 368         }
 369
 370         return;
 371 }
 372
 373 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
 374                            u16 tail, u16 head)
 375 {
 376         u16 idx;
 377
 378         do {
 379                 idx = tail & (qp->sq.wqe_cnt - 1);
 380                 handle_atomic(qp, cqe64, idx);
 381                 if (idx == head)
 382                         break;
 383
 384                 tail = qp->sq.w_list[idx].next;
 385         } while (1);
 386         tail = qp->sq.w_list[idx].next;
 387         qp->sq.last_poll = tail;
 388 }
 389
 390 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
 391 {
 392         mlx5_buf_free(dev->mdev, &buf->buf);
 393 }
 394
 395 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
 396                              struct ib_sig_err *item)
 397 {
 398         u16 syndrome = be16_to_cpu(cqe->syndrome);
 399
 400 #define GUARD_ERR   (1 << 13)
 401 #define APPTAG_ERR  (1 << 12)
 402 #define REFTAG_ERR  (1 << 11)
 403
 404         if (syndrome & GUARD_ERR) {
 405                 item->err_type = IB_SIG_BAD_GUARD;
 406                 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
 407                 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
 408         } else
 409         if (syndrome & REFTAG_ERR) {
 410                 item->err_type = IB_SIG_BAD_REFTAG;
 411                 item->expected = be32_to_cpu(cqe->expected_reftag);
 412                 item->actual = be32_to_cpu(cqe->actual_reftag);
 413         } else
 414         if (syndrome & APPTAG_ERR) {
 415                 item->err_type = IB_SIG_BAD_APPTAG;
 416                 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
 417                 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
 418         } else {
 419                 pr_err("Got signature completion error with bad syndrome %04x\n",
 420                        syndrome);
 421         }
 422
 423         item->sig_err_offset = be64_to_cpu(cqe->err_offset);
 424         item->key = be32_to_cpu(cqe->mkey);
 425 }
 426
 427 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
 428                          struct mlx5_ib_qp **cur_qp,
 429                          struct ib_wc *wc)
 430 {
 431         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
 432         struct mlx5_err_cqe *err_cqe;
 433         struct mlx5_cqe64 *cqe64;
 434         struct mlx5_core_qp *mqp;
 435         struct mlx5_ib_wq *wq;
 436         struct mlx5_sig_err_cqe *sig_err_cqe;
 437         struct mlx5_core_mr *mmr;
 438         struct mlx5_ib_mr *mr;
 439         uint8_t opcode;
 440         uint32_t qpn;
 441         u16 wqe_ctr;
 442         void *cqe;
 443         int idx;
 444
 445 repoll:
 446         cqe = next_cqe_sw(cq);
 447         if (!cqe)
 448                 return -EAGAIN;
 449
 450         cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
 451
 452         ++cq->mcq.cons_index;
 453
 454         /* Make sure we read CQ entry contents after we've checked the
 455          * ownership bit.
 456          */
 457         rmb();
 458
 459         opcode = cqe64->op_own >> 4;
 460         if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
 461                 if (likely(cq->resize_buf)) {
 462                         free_cq_buf(dev, &cq->buf);
 463                         cq->buf = *cq->resize_buf;
 464                         kfree(cq->resize_buf);
 465                         cq->resize_buf = NULL;
 466                         goto repoll;
 467                 } else {
 468                         mlx5_ib_warn(dev, "unexpected resize cqe\n");
 469                 }
 470         }
 471
 472         qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
 473         if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
 474                 /* We do not have to take the QP table lock here,
 475                  * because CQs will be locked while QPs are removed
 476                  * from the table.
 477                  */
 478                 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
 479                 if (unlikely(!mqp)) {
 480                         mlx5_ib_warn(dev, "CQE@CQ %06x for unknown QPN %6x\n",
 481                                      cq->mcq.cqn, qpn);
 482                         return -EINVAL;
 483                 }
 484
 485                 *cur_qp = to_mibqp(mqp);
 486         }
 487
 488         wc->qp  = &(*cur_qp)->ibqp;
 489         switch (opcode) {
 490         case MLX5_CQE_REQ:
 491                 wq = &(*cur_qp)->sq;
 492                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 493                 idx = wqe_ctr & (wq->wqe_cnt - 1);
 494                 handle_good_req(wc, cqe64, wq, idx);
 495                 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
 496                 wc->wr_id = wq->wrid[idx];
 497                 wq->tail = wq->wqe_head[idx] + 1;
 498                 wc->status = IB_WC_SUCCESS;
 499                 break;
 500         case MLX5_CQE_RESP_WR_IMM:
 501         case MLX5_CQE_RESP_SEND:
 502         case MLX5_CQE_RESP_SEND_IMM:
 503         case MLX5_CQE_RESP_SEND_INV:
 504                 handle_responder(wc, cqe64, *cur_qp);
 505                 wc->status = IB_WC_SUCCESS;
 506                 break;
 507         case MLX5_CQE_RESIZE_CQ:
 508                 break;
 509         case MLX5_CQE_REQ_ERR:
 510         case MLX5_CQE_RESP_ERR:
 511                 err_cqe = (struct mlx5_err_cqe *)cqe64;
 512                 mlx5_handle_error_cqe(dev, err_cqe, wc);
 513                 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
 514                             opcode == MLX5_CQE_REQ_ERR ?
 515                             "Requestor" : "Responder", cq->mcq.cqn);
 516                 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
 517                             err_cqe->syndrome, err_cqe->vendor_err_synd);
 518                 if (opcode == MLX5_CQE_REQ_ERR) {
 519                         wq = &(*cur_qp)->sq;
 520                         wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 521                         idx = wqe_ctr & (wq->wqe_cnt - 1);
 522                         wc->wr_id = wq->wrid[idx];
 523                         wq->tail = wq->wqe_head[idx] + 1;
 524                 } else {
 525                         struct mlx5_ib_srq *srq;
 526
 527                         if ((*cur_qp)->ibqp.srq) {
 528                                 srq = to_msrq((*cur_qp)->ibqp.srq);
 529                                 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
 530                                 wc->wr_id = srq->wrid[wqe_ctr];
 531                                 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
 532                         } else {
 533                                 wq = &(*cur_qp)->rq;
 534                                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 535                                 ++wq->tail;
 536                         }
 537                 }
 538                 break;
 539         case MLX5_CQE_SIG_ERR:
 540                 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
 541
 542                 read_lock(&dev->mdev->priv.mr_table.lock);
 543                 mmr = __mlx5_mr_lookup(dev->mdev,
 544                                        mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
 545                 if (unlikely(!mmr)) {
 546                         read_unlock(&dev->mdev->priv.mr_table.lock);
 547                         mlx5_ib_warn(dev, "CQE@CQ %06x for unknown MR %6x\n",
 548                                      cq->mcq.cqn, be32_to_cpu(sig_err_cqe->mkey));
 549                         return -EINVAL;
 550                 }
 551
 552                 mr = to_mibmr(mmr);
 553                 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
 554                 mr->sig->sig_err_exists = true;
 555                 mr->sig->sigerr_count++;
 556
 557                 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
 558                              cq->mcq.cqn, mr->sig->err_item.key,
 559                              mr->sig->err_item.err_type,
 560                              mr->sig->err_item.sig_err_offset,
 561                              mr->sig->err_item.expected,
 562                              mr->sig->err_item.actual);
 563
 564                 read_unlock(&dev->mdev->priv.mr_table.lock);
 565                 goto repoll;
 566         }
 567
 568         return 0;
 569 }
 570
 571 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 572 {
 573         struct mlx5_ib_cq *cq = to_mcq(ibcq);
 574         struct mlx5_ib_qp *cur_qp = NULL;
 575         unsigned long flags;
 576         int npolled;
 577         int err = 0;
 578
 579         spin_lock_irqsave(&cq->lock, flags);
 580
 581         for (npolled = 0; npolled < num_entries; npolled++) {
 582                 err = mlx5_poll_one(cq, &cur_qp, wc + npolled);
 583                 if (err)
 584                         break;
 585         }
 586
 587         if (npolled)
 588                 mlx5_cq_set_ci(&cq->mcq);
 589
 590         spin_unlock_irqrestore(&cq->lock, flags);
 591
 592         if (err == 0 || err == -EAGAIN)
 593                 return npolled;
 594         else
 595                 return err;
 596 }
 597
 598 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 599 {
 600         struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
 601         void __iomem *uar_page = mdev->priv.uuari.uars[0].map;
 602
 603         mlx5_cq_arm(&to_mcq(ibcq)->mcq,
 604                     (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 605                     MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
 606                     uar_page,
 607                     MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),
 608                     to_mcq(ibcq)->mcq.cons_index);
 609
 610         return 0;
 611 }
 612
 613 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
 614                         int nent, int cqe_size)
 615 {
 616         int err;
 617
 618         err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
 619         if (err)
 620                 return err;
 621
 622         buf->cqe_size = cqe_size;
 623         buf->nent = nent;
 624
 625         return 0;
 626 }
 627
 628 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 629                           struct ib_ucontext *context, struct mlx5_ib_cq *cq,
 630                           int entries, struct mlx5_create_cq_mbox_in **cqb,
 631                           int *cqe_size, int *index, int *inlen)
 632 {
 633         struct mlx5_ib_create_cq ucmd;
 634         size_t ucmdlen;
 635         int page_shift;
 636         int npages;
 637         int ncont;
 638         int err;
 639
 640         ucmdlen =
 641                 (udata->inlen - sizeof(struct ib_uverbs_cmd_hdr) <
 642                  sizeof(ucmd)) ? (sizeof(ucmd) -
 643                                   sizeof(ucmd.reserved)) : sizeof(ucmd);
 644
 645         if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
 646                 return -EFAULT;
 647
 648         if (ucmdlen == sizeof(ucmd) &&
 649             ucmd.reserved != 0)
 650                 return -EINVAL;
 651
 652         if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
 653                 return -EINVAL;
 654
 655         *cqe_size = ucmd.cqe_size;
 656
 657         cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
 658                                    entries * ucmd.cqe_size,
 659                                    IB_ACCESS_LOCAL_WRITE, 1);
 660         if (IS_ERR(cq->buf.umem)) {
 661                 err = PTR_ERR(cq->buf.umem);
 662                 return err;
 663         }
 664
 665         err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
 666                                   &cq->db);
 667         if (err)
 668                 goto err_umem;
 669
 670         mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift,
 671                            &ncont, NULL);
 672         mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
 673                     ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
 674
 675         *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * ncont;
 676         *cqb = mlx5_vzalloc(*inlen);
 677         if (!*cqb) {
 678                 err = -ENOMEM;
 679                 goto err_db;
 680         }
 681         mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, (*cqb)->pas, 0);
 682         (*cqb)->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 683
 684         *index = to_mucontext(context)->uuari.uars[0].index;
 685
 686         return 0;
 687
 688 err_db:
 689         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 690
 691 err_umem:
 692         ib_umem_release(cq->buf.umem);
 693         return err;
 694 }
 695
 696 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
 697 {
 698         mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
 699         ib_umem_release(cq->buf.umem);
 700 }
 701
 702 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
 703 {
 704         int i;
 705         void *cqe;
 706         struct mlx5_cqe64 *cqe64;
 707
 708         for (i = 0; i < buf->nent; i++) {
 709                 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
 710                 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
 711                 cqe64->op_own = MLX5_CQE_INVALID << 4;
 712         }
 713 }
 714
 715 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 716                             int entries, int cqe_size,
 717                             struct mlx5_create_cq_mbox_in **cqb,
 718                             int *index, int *inlen)
 719 {
 720         int err;
 721
 722         err = mlx5_db_alloc(dev->mdev, &cq->db);
 723         if (err)
 724                 return err;
 725
 726         cq->mcq.set_ci_db  = cq->db.db;
 727         cq->mcq.arm_db     = cq->db.db + 1;
 728         cq->mcq.cqe_sz = cqe_size;
 729
 730         err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
 731         if (err)
 732                 goto err_db;
 733
 734         init_cq_buf(cq, &cq->buf);
 735
 736         *inlen = sizeof(**cqb) + sizeof(*(*cqb)->pas) * cq->buf.buf.npages;
 737         *cqb = mlx5_vzalloc(*inlen);
 738         if (!*cqb) {
 739                 err = -ENOMEM;
 740                 goto err_buf;
 741         }
 742         mlx5_fill_page_array(&cq->buf.buf, (*cqb)->pas);
 743
 744         (*cqb)->ctx.log_pg_sz = cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 745         *index = dev->mdev->priv.uuari.uars[0].index;
 746
 747         return 0;
 748
 749 err_buf:
 750         free_cq_buf(dev, &cq->buf);
 751
 752 err_db:
 753         mlx5_db_free(dev->mdev, &cq->db);
 754         return err;
 755 }
 756
 757 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
 758 {
 759         free_cq_buf(dev, &cq->buf);
 760         mlx5_db_free(dev->mdev, &cq->db);
 761 }
 762
 763 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
 764                                 const struct ib_cq_init_attr *attr,
 765                                 struct ib_ucontext *context,
 766                                 struct ib_udata *udata)
 767 {
 768         int entries = attr->cqe;
 769         int vector = attr->comp_vector;
 770         struct mlx5_create_cq_mbox_in *cqb = NULL;
 771         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 772         struct mlx5_ib_cq *cq;
 773         int uninitialized_var(index);
 774         int uninitialized_var(inlen);
 775         int cqe_size;
 776         unsigned int irqn;
 777         int eqn;
 778         int err;
 779
 780         if (entries < 0)
 781                 return ERR_PTR(-EINVAL);
 782
 783         if (check_cq_create_flags(attr->flags))
 784                 return ERR_PTR(-EOPNOTSUPP);
 785
 786         entries = roundup_pow_of_two(entries + 1);
 787         if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
 788                 return ERR_PTR(-EINVAL);
 789
 790         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
 791         if (!cq)
 792                 return ERR_PTR(-ENOMEM);
 793
 794         cq->ibcq.cqe = entries - 1;
 795         mutex_init(&cq->resize_mutex);
 796         spin_lock_init(&cq->lock);
 797         cq->resize_buf = NULL;
 798         cq->resize_umem = NULL;
 799         cq->create_flags = attr->flags;
 800
 801         if (context) {
 802                 err = create_cq_user(dev, udata, context, cq, entries,
 803                                      &cqb, &cqe_size, &index, &inlen);
 804                 if (err)
 805                         goto err_create;
 806         } else {
 807                 /* for now choose 64 bytes till we have a proper interface */
 808                 cqe_size = 64;
 809                 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
 810                                        &index, &inlen);
 811                 if (err)
 812                         goto err_create;
 813         }
 814
 815         cq->cqe_size = cqe_size;
 816         cqb->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
 817
 818         if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN)
 819                 cqb->ctx.cqe_sz_flags |= (1 << 1);
 820
 821         cqb->ctx.log_sz_usr_page = cpu_to_be32((ilog2(entries) << 24) | index);
 822         err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
 823         if (err)
 824                 goto err_cqb;
 825
 826         cqb->ctx.c_eqn = cpu_to_be16(eqn);
 827         cqb->ctx.db_record_addr = cpu_to_be64(cq->db.dma);
 828
 829         err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
 830         if (err)
 831                 goto err_cqb;
 832
 833         mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
 834         cq->mcq.irqn = irqn;
 835         cq->mcq.comp  = mlx5_ib_cq_comp;
 836         cq->mcq.event = mlx5_ib_cq_event;
 837
 838         if (context)
 839                 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
 840                         err = -EFAULT;
 841                         goto err_cmd;
 842                 }
 843
 844
 845         kvfree(cqb);
 846         return &cq->ibcq;
 847
 848 err_cmd:
 849         mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
 850
 851 err_cqb:
 852         kvfree(cqb);
 853         if (context)
 854                 destroy_cq_user(cq, context);
 855         else
 856                 destroy_cq_kernel(dev, cq);
 857
 858 err_create:
 859         kfree(cq);
 860
 861         return ERR_PTR(err);
 862 }
 863
 864
 865 int mlx5_ib_destroy_cq(struct ib_cq *cq)
 866 {
 867         struct mlx5_ib_dev *dev = to_mdev(cq->device);
 868         struct mlx5_ib_cq *mcq = to_mcq(cq);
 869         struct ib_ucontext *context = NULL;
 870
 871         if (cq->uobject)
 872                 context = cq->uobject->context;
 873
 874         mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
 875         if (context)
 876                 destroy_cq_user(mcq, context);
 877         else
 878                 destroy_cq_kernel(dev, mcq);
 879
 880         kfree(mcq);
 881
 882         return 0;
 883 }
 884
 885 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
 886 {
 887         return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
 888 }
 889
 890 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
 891 {
 892         struct mlx5_cqe64 *cqe64, *dest64;
 893         void *cqe, *dest;
 894         u32 prod_index;
 895         int nfreed = 0;
 896         u8 owner_bit;
 897
 898         if (!cq)
 899                 return;
 900
 901         /* First we need to find the current producer index, so we
 902          * know where to start cleaning from.  It doesn't matter if HW
 903          * adds new entries after this loop -- the QP we're worried
 904          * about is already in RESET, so the new entries won't come
 905          * from our QP and therefore don't need to be checked.
 906          */
 907         for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
 908                 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
 909                         break;
 910
 911         /* Now sweep backwards through the CQ, removing CQ entries
 912          * that match our QP by copying older entries on top of them.
 913          */
 914         while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
 915                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 916                 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
 917                 if (is_equal_rsn(cqe64, rsn)) {
 918                         if (srq && (ntohl(cqe64->srqn) & 0xffffff))
 919                                 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
 920                         ++nfreed;
 921                 } else if (nfreed) {
 922                         dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
 923                         dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
 924                         owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
 925                         memcpy(dest, cqe, cq->mcq.cqe_sz);
 926                         dest64->op_own = owner_bit |
 927                                 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
 928                 }
 929         }
 930
 931         if (nfreed) {
 932                 cq->mcq.cons_index += nfreed;
 933                 /* Make sure update of buffer contents is done before
 934                  * updating consumer index.
 935                  */
 936                 wmb();
 937                 mlx5_cq_set_ci(&cq->mcq);
 938         }
 939 }
 940
 941 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
 942 {
 943         if (!cq)
 944                 return;
 945
 946         spin_lock_irq(&cq->lock);
 947         __mlx5_ib_cq_clean(cq, qpn, srq);
 948         spin_unlock_irq(&cq->lock);
 949 }
 950
 951 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
 952 {
 953         struct mlx5_modify_cq_mbox_in *in;
 954         struct mlx5_ib_dev *dev = to_mdev(cq->device);
 955         struct mlx5_ib_cq *mcq = to_mcq(cq);
 956         int err;
 957         u32 fsel;
 958
 959         if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
 960                 return -ENOSYS;
 961
 962         in = kzalloc(sizeof(*in), GFP_KERNEL);
 963         if (!in)
 964                 return -ENOMEM;
 965
 966         in->cqn = cpu_to_be32(mcq->mcq.cqn);
 967         fsel = (MLX5_CQ_MODIFY_PERIOD | MLX5_CQ_MODIFY_COUNT);
 968         in->ctx.cq_period = cpu_to_be16(cq_period);
 969         in->ctx.cq_max_count = cpu_to_be16(cq_count);
 970         in->field_select = cpu_to_be32(fsel);
 971         err = mlx5_core_modify_cq(dev->mdev, &mcq->mcq, in, sizeof(*in));
 972         kfree(in);
 973
 974         if (err)
 975                 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
 976
 977         return err;
 978 }
 979
 980 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
 981                        int entries, struct ib_udata *udata, int *npas,
 982                        int *page_shift, int *cqe_size)
 983 {
 984         struct mlx5_ib_resize_cq ucmd;
 985         struct ib_umem *umem;
 986         int err;
 987         int npages;
 988         struct ib_ucontext *context = cq->buf.umem->context;
 989
 990         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 991         if (err)
 992                 return err;
 993
 994         if (ucmd.reserved0 || ucmd.reserved1)
 995                 return -EINVAL;
 996
 997         umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
 998                            IB_ACCESS_LOCAL_WRITE, 1);
 999         if (IS_ERR(umem)) {
1000                 err = PTR_ERR(umem);
1001                 return err;
1002         }
1003
1004         mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift,
1005                            npas, NULL);
1006
1007         cq->resize_umem = umem;
1008         *cqe_size = ucmd.cqe_size;
1009
1010         return 0;
1011 }
1012
1013 static void un_resize_user(struct mlx5_ib_cq *cq)
1014 {
1015         ib_umem_release(cq->resize_umem);
1016 }
1017
1018 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1019                          int entries, int cqe_size)
1020 {
1021         int err;
1022
1023         cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1024         if (!cq->resize_buf)
1025                 return -ENOMEM;
1026
1027         err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1028         if (err)
1029                 goto ex;
1030
1031         init_cq_buf(cq, cq->resize_buf);
1032
1033         return 0;
1034
1035 ex:
1036         kfree(cq->resize_buf);
1037         return err;
1038 }
1039
1040 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1041 {
1042         free_cq_buf(dev, cq->resize_buf);
1043         cq->resize_buf = NULL;
1044 }
1045
1046 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1047 {
1048         struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1049         struct mlx5_cqe64 *scqe64;
1050         struct mlx5_cqe64 *dcqe64;
1051         void *start_cqe;
1052         void *scqe;
1053         void *dcqe;
1054         int ssize;
1055         int dsize;
1056         int i;
1057         u8 sw_own;
1058
1059         ssize = cq->buf.cqe_size;
1060         dsize = cq->resize_buf->cqe_size;
1061         if (ssize != dsize) {
1062                 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1063                 return -EINVAL;
1064         }
1065
1066         i = cq->mcq.cons_index;
1067         scqe = get_sw_cqe(cq, i);
1068         scqe64 = ssize == 64 ? scqe : scqe + 64;
1069         start_cqe = scqe;
1070         if (!scqe) {
1071                 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1072                 return -EINVAL;
1073         }
1074
1075         while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1076                 dcqe = get_cqe_from_buf(cq->resize_buf,
1077                                         (i + 1) & (cq->resize_buf->nent),
1078                                         dsize);
1079                 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1080                 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1081                 memcpy(dcqe, scqe, dsize);
1082                 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1083
1084                 ++i;
1085                 scqe = get_sw_cqe(cq, i);
1086                 scqe64 = ssize == 64 ? scqe : scqe + 64;
1087                 if (!scqe) {
1088                         mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1089                         return -EINVAL;
1090                 }
1091
1092                 if (scqe == start_cqe) {
1093                         pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1094                                 cq->mcq.cqn);
1095                         return -ENOMEM;
1096                 }
1097         }
1098         ++cq->mcq.cons_index;
1099         return 0;
1100 }
1101
1102 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1103 {
1104         struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1105         struct mlx5_ib_cq *cq = to_mcq(ibcq);
1106         struct mlx5_modify_cq_mbox_in *in;
1107         int err;
1108         int npas;
1109         int page_shift;
1110         int inlen;
1111         int uninitialized_var(cqe_size);
1112         unsigned long flags;
1113
1114         if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1115                 pr_info("Firmware does not support resize CQ\n");
1116                 return -ENOSYS;
1117         }
1118
1119         if (entries < 1)
1120                 return -EINVAL;
1121
1122         entries = roundup_pow_of_two(entries + 1);
1123         if (entries >  (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1124                 return -EINVAL;
1125
1126         if (entries == ibcq->cqe + 1)
1127                 return 0;
1128
1129         mutex_lock(&cq->resize_mutex);
1130         if (udata) {
1131                 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1132                                   &cqe_size);
1133         } else {
1134                 cqe_size = 64;
1135                 err = resize_kernel(dev, cq, entries, cqe_size);
1136                 if (!err) {
1137                         npas = cq->resize_buf->buf.npages;
1138                         page_shift = cq->resize_buf->buf.page_shift;
1139                 }
1140         }
1141
1142         if (err)
1143                 goto ex;
1144
1145         inlen = sizeof(*in) + npas * sizeof(in->pas[0]);
1146         in = mlx5_vzalloc(inlen);
1147         if (!in) {
1148                 err = -ENOMEM;
1149                 goto ex_resize;
1150         }
1151
1152         if (udata)
1153                 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1154                                      in->pas, 0);
1155         else
1156                 mlx5_fill_page_array(&cq->resize_buf->buf, in->pas);
1157
1158         in->field_select = cpu_to_be32(MLX5_MODIFY_CQ_MASK_LOG_SIZE  |
1159                                        MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1160                                        MLX5_MODIFY_CQ_MASK_PG_SIZE);
1161         in->ctx.log_pg_sz = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
1162         in->ctx.cqe_sz_flags = cqe_sz_to_mlx_sz(cqe_size) << 5;
1163         in->ctx.page_offset = 0;
1164         in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(entries) << 24);
1165         in->hdr.opmod = cpu_to_be16(MLX5_CQ_OPMOD_RESIZE);
1166         in->cqn = cpu_to_be32(cq->mcq.cqn);
1167
1168         err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1169         if (err)
1170                 goto ex_alloc;
1171
1172         if (udata) {
1173                 cq->ibcq.cqe = entries - 1;
1174                 ib_umem_release(cq->buf.umem);
1175                 cq->buf.umem = cq->resize_umem;
1176                 cq->resize_umem = NULL;
1177         } else {
1178                 struct mlx5_ib_cq_buf tbuf;
1179                 int resized = 0;
1180
1181                 spin_lock_irqsave(&cq->lock, flags);
1182                 if (cq->resize_buf) {
1183                         err = copy_resize_cqes(cq);
1184                         if (!err) {
1185                                 tbuf = cq->buf;
1186                                 cq->buf = *cq->resize_buf;
1187                                 kfree(cq->resize_buf);
1188                                 cq->resize_buf = NULL;
1189                                 resized = 1;
1190                         }
1191                 }
1192                 cq->ibcq.cqe = entries - 1;
1193                 spin_unlock_irqrestore(&cq->lock, flags);
1194                 if (resized)
1195                         free_cq_buf(dev, &tbuf);
1196         }
1197         mutex_unlock(&cq->resize_mutex);
1198
1199         kvfree(in);
1200         return 0;
1201
1202 ex_alloc:
1203         kvfree(in);
1204
1205 ex_resize:
1206         if (udata)
1207                 un_resize_user(cq);
1208         else
1209                 un_resize_kernel(dev, cq);
1210 ex:
1211         mutex_unlock(&cq->resize_mutex);
1212         return err;
1213 }
1214
1215 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1216 {
1217         struct mlx5_ib_cq *cq;
1218
1219         if (!ibcq)
1220                 return 128;
1221
1222         cq = to_mcq(ibcq);
1223         return cq->cqe_size;
1224 }