drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include <rdma/ib_user_verbs.h>
  47 #include <rdma/ib_addr.h>
  48 #include <rdma/ib_cache.h>
  49 #include <linux/mlx5/port.h>
  50 #include <linux/mlx5/vport.h>
  51 #include <linux/list.h>
  52 #include <rdma/ib_smi.h>
  53 #include <rdma/ib_umem.h>
  54 #include <linux/in.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/mlx5/fs.h>
  57 #include "user.h"
  58 #include "mlx5_ib.h"
  59
  60 #define DRIVER_NAME "mlx5_ib"
  61 #define DRIVER_VERSION "2.2-1"
  62 #define DRIVER_RELDATE  "Feb 2014"
  63
  64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  65 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  66 MODULE_LICENSE("Dual BSD/GPL");
  67 MODULE_VERSION(DRIVER_VERSION);
  68
  69 static int deprecated_prof_sel = 2;
  70 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  71 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  72
  73 static char mlx5_version[] =
  74         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  75         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  76
  77 enum {
  78         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  79 };
  80
  81 static enum rdma_link_layer
  82 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  83 {
  84         switch (port_type_cap) {
  85         case MLX5_CAP_PORT_TYPE_IB:
  86                 return IB_LINK_LAYER_INFINIBAND;
  87         case MLX5_CAP_PORT_TYPE_ETH:
  88                 return IB_LINK_LAYER_ETHERNET;
  89         default:
  90                 return IB_LINK_LAYER_UNSPECIFIED;
  91         }
  92 }
  93
  94 static enum rdma_link_layer
  95 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  96 {
  97         struct mlx5_ib_dev *dev = to_mdev(device);
  98         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  99
 100         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 101 }
 102
 103 static int mlx5_netdev_event(struct notifier_block *this,
 104                              unsigned long event, void *ptr)
 105 {
 106         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 107         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 108                                                  roce.nb);
 109
 110         switch (event) {
 111         case NETDEV_REGISTER:
 112         case NETDEV_UNREGISTER:
 113                 write_lock(&ibdev->roce.netdev_lock);
 114                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 115                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 116                                              NULL : ndev;
 117                 write_unlock(&ibdev->roce.netdev_lock);
 118                 break;
 119
 120         case NETDEV_UP:
 121         case NETDEV_DOWN: {
 122                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 123                 struct net_device *upper = NULL;
 124
 125                 if (lag_ndev) {
 126                         upper = netdev_master_upper_dev_get(lag_ndev);
 127                         dev_put(lag_ndev);
 128                 }
 129
 130                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 131                     && ibdev->ib_active) {
 132                         struct ib_event ibev = {0};
 133
 134                         ibev.device = &ibdev->ib_dev;
 135                         ibev.event = (event == NETDEV_UP) ?
 136                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 137                         ibev.element.port_num = 1;
 138                         ib_dispatch_event(&ibev);
 139                 }
 140                 break;
 141         }
 142
 143         default:
 144                 break;
 145         }
 146
 147         return NOTIFY_DONE;
 148 }
 149
 150 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 151                                              u8 port_num)
 152 {
 153         struct mlx5_ib_dev *ibdev = to_mdev(device);
 154         struct net_device *ndev;
 155
 156         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 157         if (ndev)
 158                 return ndev;
 159
 160         /* Ensure ndev does not disappear before we invoke dev_hold()
 161          */
 162         read_lock(&ibdev->roce.netdev_lock);
 163         ndev = ibdev->roce.netdev;
 164         if (ndev)
 165                 dev_hold(ndev);
 166         read_unlock(&ibdev->roce.netdev_lock);
 167
 168         return ndev;
 169 }
 170
 171 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 172                                 struct ib_port_attr *props)
 173 {
 174         struct mlx5_ib_dev *dev = to_mdev(device);
 175         struct net_device *ndev, *upper;
 176         enum ib_mtu ndev_ib_mtu;
 177         u16 qkey_viol_cntr;
 178
 179         memset(props, 0, sizeof(*props));
 180
 181         props->port_cap_flags  |= IB_PORT_CM_SUP;
 182         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 183
 184         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 185                                                 roce_address_table_size);
 186         props->max_mtu          = IB_MTU_4096;
 187         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 188         props->pkey_tbl_len     = 1;
 189         props->state            = IB_PORT_DOWN;
 190         props->phys_state       = 3;
 191
 192         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 193         props->qkey_viol_cntr = qkey_viol_cntr;
 194
 195         ndev = mlx5_ib_get_netdev(device, port_num);
 196         if (!ndev)
 197                 return 0;
 198
 199         if (mlx5_lag_is_active(dev->mdev)) {
 200                 rcu_read_lock();
 201                 upper = netdev_master_upper_dev_get_rcu(ndev);
 202                 if (upper) {
 203                         dev_put(ndev);
 204                         ndev = upper;
 205                         dev_hold(ndev);
 206                 }
 207                 rcu_read_unlock();
 208         }
 209
 210         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 211                 props->state      = IB_PORT_ACTIVE;
 212                 props->phys_state = 5;
 213         }
 214
 215         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 216
 217         dev_put(ndev);
 218
 219         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 220
 221         props->active_width     = IB_WIDTH_4X;  /* TODO */
 222         props->active_speed     = IB_SPEED_QDR; /* TODO */
 223
 224         return 0;
 225 }
 226
 227 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 228                                      const struct ib_gid_attr *attr,
 229                                      void *mlx5_addr)
 230 {
 231 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 232         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 233                                                source_l3_address);
 234         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 235                                                source_mac_47_32);
 236
 237         if (!gid)
 238                 return;
 239
 240         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 241
 242         if (is_vlan_dev(attr->ndev)) {
 243                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 244                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 245         }
 246
 247         switch (attr->gid_type) {
 248         case IB_GID_TYPE_IB:
 249                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 250                 break;
 251         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 252                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 253                 break;
 254
 255         default:
 256                 WARN_ON(true);
 257         }
 258
 259         if (attr->gid_type != IB_GID_TYPE_IB) {
 260                 if (ipv6_addr_v4mapped((void *)gid))
 261                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 262                                     MLX5_ROCE_L3_TYPE_IPV4);
 263                 else
 264                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 265                                     MLX5_ROCE_L3_TYPE_IPV6);
 266         }
 267
 268         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 269             !ipv6_addr_v4mapped((void *)gid))
 270                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 271         else
 272                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 273 }
 274
 275 static int set_roce_addr(struct ib_device *device, u8 port_num,
 276                          unsigned int index,
 277                          const union ib_gid *gid,
 278                          const struct ib_gid_attr *attr)
 279 {
 280         struct mlx5_ib_dev *dev = to_mdev(device);
 281         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 282         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 283         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 284         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 285
 286         if (ll != IB_LINK_LAYER_ETHERNET)
 287                 return -EINVAL;
 288
 289         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 290
 291         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 292         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 293         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 294 }
 295
 296 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 297                            unsigned int index, const union ib_gid *gid,
 298                            const struct ib_gid_attr *attr,
 299                            __always_unused void **context)
 300 {
 301         return set_roce_addr(device, port_num, index, gid, attr);
 302 }
 303
 304 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 305                            unsigned int index, __always_unused void **context)
 306 {
 307         return set_roce_addr(device, port_num, index, NULL, NULL);
 308 }
 309
 310 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 311                                int index)
 312 {
 313         struct ib_gid_attr attr;
 314         union ib_gid gid;
 315
 316         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 317                 return 0;
 318
 319         if (!attr.ndev)
 320                 return 0;
 321
 322         dev_put(attr.ndev);
 323
 324         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 325                 return 0;
 326
 327         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 328 }
 329
 330 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 331 {
 332         return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 333 }
 334
 335 enum {
 336         MLX5_VPORT_ACCESS_METHOD_MAD,
 337         MLX5_VPORT_ACCESS_METHOD_HCA,
 338         MLX5_VPORT_ACCESS_METHOD_NIC,
 339 };
 340
 341 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 342 {
 343         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 344                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 345
 346         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 347             IB_LINK_LAYER_ETHERNET)
 348                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 349
 350         return MLX5_VPORT_ACCESS_METHOD_HCA;
 351 }
 352
 353 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 354                             struct ib_device_attr *props)
 355 {
 356         u8 tmp;
 357         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 358         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 359         u8 atomic_req_8B_endianness_mode =
 360                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 361
 362         /* Check if HW supports 8 bytes standard atomic operations and capable
 363          * of host endianness respond
 364          */
 365         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 366         if (((atomic_operations & tmp) == tmp) &&
 367             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 368             (atomic_req_8B_endianness_mode)) {
 369                 props->atomic_cap = IB_ATOMIC_HCA;
 370         } else {
 371                 props->atomic_cap = IB_ATOMIC_NONE;
 372         }
 373 }
 374
 375 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 376                                         __be64 *sys_image_guid)
 377 {
 378         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 379         struct mlx5_core_dev *mdev = dev->mdev;
 380         u64 tmp;
 381         int err;
 382
 383         switch (mlx5_get_vport_access_method(ibdev)) {
 384         case MLX5_VPORT_ACCESS_METHOD_MAD:
 385                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 386                                                             sys_image_guid);
 387
 388         case MLX5_VPORT_ACCESS_METHOD_HCA:
 389                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 390                 break;
 391
 392         case MLX5_VPORT_ACCESS_METHOD_NIC:
 393                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 394                 break;
 395
 396         default:
 397                 return -EINVAL;
 398         }
 399
 400         if (!err)
 401                 *sys_image_guid = cpu_to_be64(tmp);
 402
 403         return err;
 404
 405 }
 406
 407 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 408                                 u16 *max_pkeys)
 409 {
 410         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 411         struct mlx5_core_dev *mdev = dev->mdev;
 412
 413         switch (mlx5_get_vport_access_method(ibdev)) {
 414         case MLX5_VPORT_ACCESS_METHOD_MAD:
 415                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 416
 417         case MLX5_VPORT_ACCESS_METHOD_HCA:
 418         case MLX5_VPORT_ACCESS_METHOD_NIC:
 419                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 420                                                 pkey_table_size));
 421                 return 0;
 422
 423         default:
 424                 return -EINVAL;
 425         }
 426 }
 427
 428 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 429                                 u32 *vendor_id)
 430 {
 431         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 432
 433         switch (mlx5_get_vport_access_method(ibdev)) {
 434         case MLX5_VPORT_ACCESS_METHOD_MAD:
 435                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 436
 437         case MLX5_VPORT_ACCESS_METHOD_HCA:
 438         case MLX5_VPORT_ACCESS_METHOD_NIC:
 439                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 440
 441         default:
 442                 return -EINVAL;
 443         }
 444 }
 445
 446 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 447                                 __be64 *node_guid)
 448 {
 449         u64 tmp;
 450         int err;
 451
 452         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 453         case MLX5_VPORT_ACCESS_METHOD_MAD:
 454                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 455
 456         case MLX5_VPORT_ACCESS_METHOD_HCA:
 457                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 458                 break;
 459
 460         case MLX5_VPORT_ACCESS_METHOD_NIC:
 461                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 462                 break;
 463
 464         default:
 465                 return -EINVAL;
 466         }
 467
 468         if (!err)
 469                 *node_guid = cpu_to_be64(tmp);
 470
 471         return err;
 472 }
 473
 474 struct mlx5_reg_node_desc {
 475         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 476 };
 477
 478 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 479 {
 480         struct mlx5_reg_node_desc in;
 481
 482         if (mlx5_use_mad_ifc(dev))
 483                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 484
 485         memset(&in, 0, sizeof(in));
 486
 487         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 488                                     sizeof(struct mlx5_reg_node_desc),
 489                                     MLX5_REG_NODE_DESC, 0, 0);
 490 }
 491
 492 static int mlx5_ib_query_device(struct ib_device *ibdev,
 493                                 struct ib_device_attr *props,
 494                                 struct ib_udata *uhw)
 495 {
 496         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 497         struct mlx5_core_dev *mdev = dev->mdev;
 498         int err = -ENOMEM;
 499         int max_rq_sg;
 500         int max_sq_sg;
 501         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 502         struct mlx5_ib_query_device_resp resp = {};
 503         size_t resp_len;
 504         u64 max_tso;
 505
 506         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 507         if (uhw->outlen && uhw->outlen < resp_len)
 508                 return -EINVAL;
 509         else
 510                 resp.response_length = resp_len;
 511
 512         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 513                 return -EINVAL;
 514
 515         memset(props, 0, sizeof(*props));
 516         err = mlx5_query_system_image_guid(ibdev,
 517                                            &props->sys_image_guid);
 518         if (err)
 519                 return err;
 520
 521         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 522         if (err)
 523                 return err;
 524
 525         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 526         if (err)
 527                 return err;
 528
 529         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 530                 (fw_rev_min(dev->mdev) << 16) |
 531                 fw_rev_sub(dev->mdev);
 532         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 533                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 534                 IB_DEVICE_SYS_IMAGE_GUID                |
 535                 IB_DEVICE_RC_RNR_NAK_GEN;
 536
 537         if (MLX5_CAP_GEN(mdev, pkv))
 538                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 539         if (MLX5_CAP_GEN(mdev, qkv))
 540                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 541         if (MLX5_CAP_GEN(mdev, apm))
 542                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 543         if (MLX5_CAP_GEN(mdev, xrc))
 544                 props->device_cap_flags |= IB_DEVICE_XRC;
 545         if (MLX5_CAP_GEN(mdev, imaicl)) {
 546                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 547                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 548                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 549                 /* We support 'Gappy' memory registration too */
 550                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 551         }
 552         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 553         if (MLX5_CAP_GEN(mdev, sho)) {
 554                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 555                 /* At this stage no support for signature handover */
 556                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 557                                       IB_PROT_T10DIF_TYPE_2 |
 558                                       IB_PROT_T10DIF_TYPE_3;
 559                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 560                                        IB_GUARD_T10DIF_CSUM;
 561         }
 562         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 563                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 564
 565         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 566                 if (MLX5_CAP_ETH(mdev, csum_cap))
 567                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 568
 569                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 570                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 571                         if (max_tso) {
 572                                 resp.tso_caps.max_tso = 1 << max_tso;
 573                                 resp.tso_caps.supported_qpts |=
 574                                         1 << IB_QPT_RAW_PACKET;
 575                                 resp.response_length += sizeof(resp.tso_caps);
 576                         }
 577                 }
 578
 579                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 580                         resp.rss_caps.rx_hash_function =
 581                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 582                         resp.rss_caps.rx_hash_fields_mask =
 583                                                 MLX5_RX_HASH_SRC_IPV4 |
 584                                                 MLX5_RX_HASH_DST_IPV4 |
 585                                                 MLX5_RX_HASH_SRC_IPV6 |
 586                                                 MLX5_RX_HASH_DST_IPV6 |
 587                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 588                                                 MLX5_RX_HASH_DST_PORT_TCP |
 589                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 590                                                 MLX5_RX_HASH_DST_PORT_UDP;
 591                         resp.response_length += sizeof(resp.rss_caps);
 592                 }
 593         } else {
 594                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 595                         resp.response_length += sizeof(resp.tso_caps);
 596                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 597                         resp.response_length += sizeof(resp.rss_caps);
 598         }
 599
 600         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 601                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 602                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 603         }
 604
 605         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 606             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 607                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 608
 609         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 610                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 611
 612         props->vendor_part_id      = mdev->pdev->device;
 613         props->hw_ver              = mdev->pdev->revision;
 614
 615         props->max_mr_size         = ~0ull;
 616         props->page_size_cap       = ~(min_page_size - 1);
 617         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 618         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 619         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 620                      sizeof(struct mlx5_wqe_data_seg);
 621         max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
 622                      sizeof(struct mlx5_wqe_ctrl_seg)) /
 623                      sizeof(struct mlx5_wqe_data_seg);
 624         props->max_sge = min(max_rq_sg, max_sq_sg);
 625         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 626         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 627         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 628         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 629         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 630         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 631         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 632         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 633         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 634         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 635         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 636         props->max_srq_sge         = max_rq_sg - 1;
 637         props->max_fast_reg_page_list_len =
 638                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 639         get_atomic_caps(dev, props);
 640         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 641         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 642         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 643         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 644                                            props->max_mcast_grp;
 645         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 646         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 647         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 648
 649 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 650         if (MLX5_CAP_GEN(mdev, pg))
 651                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 652         props->odp_caps = dev->odp_caps;
 653 #endif
 654
 655         if (MLX5_CAP_GEN(mdev, cd))
 656                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 657
 658         if (!mlx5_core_is_pf(mdev))
 659                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 660
 661         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 662             IB_LINK_LAYER_ETHERNET) {
 663                 props->rss_caps.max_rwq_indirection_tables =
 664                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 665                 props->rss_caps.max_rwq_indirection_table_size =
 666                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 667                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 668                 props->max_wq_type_rq =
 669                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 670         }
 671
 672         if (uhw->outlen) {
 673                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 674
 675                 if (err)
 676                         return err;
 677         }
 678
 679         return 0;
 680 }
 681
 682 enum mlx5_ib_width {
 683         MLX5_IB_WIDTH_1X        = 1 << 0,
 684         MLX5_IB_WIDTH_2X        = 1 << 1,
 685         MLX5_IB_WIDTH_4X        = 1 << 2,
 686         MLX5_IB_WIDTH_8X        = 1 << 3,
 687         MLX5_IB_WIDTH_12X       = 1 << 4
 688 };
 689
 690 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 691                                   u8 *ib_width)
 692 {
 693         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 694         int err = 0;
 695
 696         if (active_width & MLX5_IB_WIDTH_1X) {
 697                 *ib_width = IB_WIDTH_1X;
 698         } else if (active_width & MLX5_IB_WIDTH_2X) {
 699                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 700                             (int)active_width);
 701                 err = -EINVAL;
 702         } else if (active_width & MLX5_IB_WIDTH_4X) {
 703                 *ib_width = IB_WIDTH_4X;
 704         } else if (active_width & MLX5_IB_WIDTH_8X) {
 705                 *ib_width = IB_WIDTH_8X;
 706         } else if (active_width & MLX5_IB_WIDTH_12X) {
 707                 *ib_width = IB_WIDTH_12X;
 708         } else {
 709                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 710                             (int)active_width);
 711                 err = -EINVAL;
 712         }
 713
 714         return err;
 715 }
 716
 717 static int mlx5_mtu_to_ib_mtu(int mtu)
 718 {
 719         switch (mtu) {
 720         case 256: return 1;
 721         case 512: return 2;
 722         case 1024: return 3;
 723         case 2048: return 4;
 724         case 4096: return 5;
 725         default:
 726                 pr_warn("invalid mtu\n");
 727                 return -1;
 728         }
 729 }
 730
 731 enum ib_max_vl_num {
 732         __IB_MAX_VL_0           = 1,
 733         __IB_MAX_VL_0_1         = 2,
 734         __IB_MAX_VL_0_3         = 3,
 735         __IB_MAX_VL_0_7         = 4,
 736         __IB_MAX_VL_0_14        = 5,
 737 };
 738
 739 enum mlx5_vl_hw_cap {
 740         MLX5_VL_HW_0    = 1,
 741         MLX5_VL_HW_0_1  = 2,
 742         MLX5_VL_HW_0_2  = 3,
 743         MLX5_VL_HW_0_3  = 4,
 744         MLX5_VL_HW_0_4  = 5,
 745         MLX5_VL_HW_0_5  = 6,
 746         MLX5_VL_HW_0_6  = 7,
 747         MLX5_VL_HW_0_7  = 8,
 748         MLX5_VL_HW_0_14 = 15
 749 };
 750
 751 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 752                                 u8 *max_vl_num)
 753 {
 754         switch (vl_hw_cap) {
 755         case MLX5_VL_HW_0:
 756                 *max_vl_num = __IB_MAX_VL_0;
 757                 break;
 758         case MLX5_VL_HW_0_1:
 759                 *max_vl_num = __IB_MAX_VL_0_1;
 760                 break;
 761         case MLX5_VL_HW_0_3:
 762                 *max_vl_num = __IB_MAX_VL_0_3;
 763                 break;
 764         case MLX5_VL_HW_0_7:
 765                 *max_vl_num = __IB_MAX_VL_0_7;
 766                 break;
 767         case MLX5_VL_HW_0_14:
 768                 *max_vl_num = __IB_MAX_VL_0_14;
 769                 break;
 770
 771         default:
 772                 return -EINVAL;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 779                                struct ib_port_attr *props)
 780 {
 781         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 782         struct mlx5_core_dev *mdev = dev->mdev;
 783         struct mlx5_hca_vport_context *rep;
 784         u16 max_mtu;
 785         u16 oper_mtu;
 786         int err;
 787         u8 ib_link_width_oper;
 788         u8 vl_hw_cap;
 789
 790         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 791         if (!rep) {
 792                 err = -ENOMEM;
 793                 goto out;
 794         }
 795
 796         memset(props, 0, sizeof(*props));
 797
 798         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 799         if (err)
 800                 goto out;
 801
 802         props->lid              = rep->lid;
 803         props->lmc              = rep->lmc;
 804         props->sm_lid           = rep->sm_lid;
 805         props->sm_sl            = rep->sm_sl;
 806         props->state            = rep->vport_state;
 807         props->phys_state       = rep->port_physical_state;
 808         props->port_cap_flags   = rep->cap_mask1;
 809         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 810         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 811         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 812         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 813         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 814         props->subnet_timeout   = rep->subnet_timeout;
 815         props->init_type_reply  = rep->init_type_reply;
 816         props->grh_required     = rep->grh_required;
 817
 818         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 819         if (err)
 820                 goto out;
 821
 822         err = translate_active_width(ibdev, ib_link_width_oper,
 823                                      &props->active_width);
 824         if (err)
 825                 goto out;
 826         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 827         if (err)
 828                 goto out;
 829
 830         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 831
 832         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 833
 834         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 835
 836         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 837
 838         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 839         if (err)
 840                 goto out;
 841
 842         err = translate_max_vl_num(ibdev, vl_hw_cap,
 843                                    &props->max_vl_num);
 844 out:
 845         kfree(rep);
 846         return err;
 847 }
 848
 849 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 850                        struct ib_port_attr *props)
 851 {
 852         switch (mlx5_get_vport_access_method(ibdev)) {
 853         case MLX5_VPORT_ACCESS_METHOD_MAD:
 854                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 855
 856         case MLX5_VPORT_ACCESS_METHOD_HCA:
 857                 return mlx5_query_hca_port(ibdev, port, props);
 858
 859         case MLX5_VPORT_ACCESS_METHOD_NIC:
 860                 return mlx5_query_port_roce(ibdev, port, props);
 861
 862         default:
 863                 return -EINVAL;
 864         }
 865 }
 866
 867 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 868                              union ib_gid *gid)
 869 {
 870         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 871         struct mlx5_core_dev *mdev = dev->mdev;
 872
 873         switch (mlx5_get_vport_access_method(ibdev)) {
 874         case MLX5_VPORT_ACCESS_METHOD_MAD:
 875                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 876
 877         case MLX5_VPORT_ACCESS_METHOD_HCA:
 878                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 879
 880         default:
 881                 return -EINVAL;
 882         }
 883
 884 }
 885
 886 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 887                               u16 *pkey)
 888 {
 889         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 890         struct mlx5_core_dev *mdev = dev->mdev;
 891
 892         switch (mlx5_get_vport_access_method(ibdev)) {
 893         case MLX5_VPORT_ACCESS_METHOD_MAD:
 894                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 895
 896         case MLX5_VPORT_ACCESS_METHOD_HCA:
 897         case MLX5_VPORT_ACCESS_METHOD_NIC:
 898                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 899                                                  pkey);
 900         default:
 901                 return -EINVAL;
 902         }
 903 }
 904
 905 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 906                                  struct ib_device_modify *props)
 907 {
 908         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 909         struct mlx5_reg_node_desc in;
 910         struct mlx5_reg_node_desc out;
 911         int err;
 912
 913         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 914                 return -EOPNOTSUPP;
 915
 916         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 917                 return 0;
 918
 919         /*
 920          * If possible, pass node desc to FW, so it can generate
 921          * a 144 trap.  If cmd fails, just ignore.
 922          */
 923         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 924         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 925                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 926         if (err)
 927                 return err;
 928
 929         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 930
 931         return err;
 932 }
 933
 934 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 935                                struct ib_port_modify *props)
 936 {
 937         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 938         struct ib_port_attr attr;
 939         u32 tmp;
 940         int err;
 941
 942         mutex_lock(&dev->cap_mask_mutex);
 943
 944         err = mlx5_ib_query_port(ibdev, port, &attr);
 945         if (err)
 946                 goto out;
 947
 948         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 949                 ~props->clr_port_cap_mask;
 950
 951         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 952
 953 out:
 954         mutex_unlock(&dev->cap_mask_mutex);
 955         return err;
 956 }
 957
 958 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 959                                                   struct ib_udata *udata)
 960 {
 961         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 962         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 963         struct mlx5_ib_alloc_ucontext_resp resp = {};
 964         struct mlx5_ib_ucontext *context;
 965         struct mlx5_uuar_info *uuari;
 966         struct mlx5_uar *uars;
 967         int gross_uuars;
 968         int num_uars;
 969         int ver;
 970         int uuarn;
 971         int err;
 972         int i;
 973         size_t reqlen;
 974         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 975                                      max_cqe_version);
 976
 977         if (!dev->ib_active)
 978                 return ERR_PTR(-EAGAIN);
 979
 980         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
 981                 return ERR_PTR(-EINVAL);
 982
 983         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
 984         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
 985                 ver = 0;
 986         else if (reqlen >= min_req_v2)
 987                 ver = 2;
 988         else
 989                 return ERR_PTR(-EINVAL);
 990
 991         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
 992         if (err)
 993                 return ERR_PTR(err);
 994
 995         if (req.flags)
 996                 return ERR_PTR(-EINVAL);
 997
 998         if (req.total_num_uuars > MLX5_MAX_UUARS)
 999                 return ERR_PTR(-ENOMEM);
1000
1001         if (req.total_num_uuars == 0)
1002                 return ERR_PTR(-EINVAL);
1003
1004         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1005                 return ERR_PTR(-EOPNOTSUPP);
1006
1007         if (reqlen > sizeof(req) &&
1008             !ib_is_udata_cleared(udata, sizeof(req),
1009                                  reqlen - sizeof(req)))
1010                 return ERR_PTR(-EOPNOTSUPP);
1011
1012         req.total_num_uuars = ALIGN(req.total_num_uuars,
1013                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
1014         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1015                 return ERR_PTR(-EINVAL);
1016
1017         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1018         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1019         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1020         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1021                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1022         resp.cache_line_size = L1_CACHE_BYTES;
1023         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1024         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1025         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1026         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1027         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1028         resp.cqe_version = min_t(__u8,
1029                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1030                                  req.max_cqe_version);
1031         resp.response_length = min(offsetof(typeof(resp), response_length) +
1032                                    sizeof(resp.response_length), udata->outlen);
1033
1034         context = kzalloc(sizeof(*context), GFP_KERNEL);
1035         if (!context)
1036                 return ERR_PTR(-ENOMEM);
1037
1038         uuari = &context->uuari;
1039         mutex_init(&uuari->lock);
1040         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1041         if (!uars) {
1042                 err = -ENOMEM;
1043                 goto out_ctx;
1044         }
1045
1046         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1047                                 sizeof(*uuari->bitmap),
1048                                 GFP_KERNEL);
1049         if (!uuari->bitmap) {
1050                 err = -ENOMEM;
1051                 goto out_uar_ctx;
1052         }
1053         /*
1054          * clear all fast path uuars
1055          */
1056         for (i = 0; i < gross_uuars; i++) {
1057                 uuarn = i & 3;
1058                 if (uuarn == 2 || uuarn == 3)
1059                         set_bit(i, uuari->bitmap);
1060         }
1061
1062         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1063         if (!uuari->count) {
1064                 err = -ENOMEM;
1065                 goto out_bitmap;
1066         }
1067
1068         for (i = 0; i < num_uars; i++) {
1069                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1070                 if (err)
1071                         goto out_count;
1072         }
1073
1074 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1075         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1076 #endif
1077
1078         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1079                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1080                                                        &context->tdn);
1081                 if (err)
1082                         goto out_uars;
1083         }
1084
1085         INIT_LIST_HEAD(&context->vma_private_list);
1086         INIT_LIST_HEAD(&context->db_page_list);
1087         mutex_init(&context->db_page_mutex);
1088
1089         resp.tot_uuars = req.total_num_uuars;
1090         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1091
1092         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1093                 resp.response_length += sizeof(resp.cqe_version);
1094
1095         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1096                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1097                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1098         }
1099
1100         /*
1101          * We don't want to expose information from the PCI bar that is located
1102          * after 4096 bytes, so if the arch only supports larger pages, let's
1103          * pretend we don't support reading the HCA's core clock. This is also
1104          * forced by mmap function.
1105          */
1106         if (PAGE_SIZE <= 4096 &&
1107             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1108                 resp.comp_mask |=
1109                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1110                 resp.hca_core_clock_offset =
1111                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1112                         PAGE_SIZE;
1113                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1114                                         sizeof(resp.reserved2);
1115         }
1116
1117         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1118         if (err)
1119                 goto out_td;
1120
1121         uuari->ver = ver;
1122         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1123         uuari->uars = uars;
1124         uuari->num_uars = num_uars;
1125         context->cqe_version = resp.cqe_version;
1126
1127         return &context->ibucontext;
1128
1129 out_td:
1130         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1131                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1132
1133 out_uars:
1134         for (i--; i >= 0; i--)
1135                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1136 out_count:
1137         kfree(uuari->count);
1138
1139 out_bitmap:
1140         kfree(uuari->bitmap);
1141
1142 out_uar_ctx:
1143         kfree(uars);
1144
1145 out_ctx:
1146         kfree(context);
1147         return ERR_PTR(err);
1148 }
1149
1150 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1151 {
1152         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1153         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1154         struct mlx5_uuar_info *uuari = &context->uuari;
1155         int i;
1156
1157         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1158                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1159
1160         for (i = 0; i < uuari->num_uars; i++) {
1161                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1162                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1163         }
1164
1165         kfree(uuari->count);
1166         kfree(uuari->bitmap);
1167         kfree(uuari->uars);
1168         kfree(context);
1169
1170         return 0;
1171 }
1172
1173 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1174 {
1175         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1176 }
1177
1178 static int get_command(unsigned long offset)
1179 {
1180         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1181 }
1182
1183 static int get_arg(unsigned long offset)
1184 {
1185         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1186 }
1187
1188 static int get_index(unsigned long offset)
1189 {
1190         return get_arg(offset);
1191 }
1192
1193 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1194 {
1195         /* vma_open is called when a new VMA is created on top of our VMA.  This
1196          * is done through either mremap flow or split_vma (usually due to
1197          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1198          * as this VMA is strongly hardware related.  Therefore we set the
1199          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1200          * calling us again and trying to do incorrect actions.  We assume that
1201          * the original VMA size is exactly a single page, and therefore all
1202          * "splitting" operation will not happen to it.
1203          */
1204         area->vm_ops = NULL;
1205 }
1206
1207 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1208 {
1209         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1210
1211         /* It's guaranteed that all VMAs opened on a FD are closed before the
1212          * file itself is closed, therefore no sync is needed with the regular
1213          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1214          * However need a sync with accessing the vma as part of
1215          * mlx5_ib_disassociate_ucontext.
1216          * The close operation is usually called under mm->mmap_sem except when
1217          * process is exiting.
1218          * The exiting case is handled explicitly as part of
1219          * mlx5_ib_disassociate_ucontext.
1220          */
1221         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1222
1223         /* setting the vma context pointer to null in the mlx5_ib driver's
1224          * private data, to protect a race condition in
1225          * mlx5_ib_disassociate_ucontext().
1226          */
1227         mlx5_ib_vma_priv_data->vma = NULL;
1228         list_del(&mlx5_ib_vma_priv_data->list);
1229         kfree(mlx5_ib_vma_priv_data);
1230 }
1231
1232 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1233         .open = mlx5_ib_vma_open,
1234         .close = mlx5_ib_vma_close
1235 };
1236
1237 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1238                                 struct mlx5_ib_ucontext *ctx)
1239 {
1240         struct mlx5_ib_vma_private_data *vma_prv;
1241         struct list_head *vma_head = &ctx->vma_private_list;
1242
1243         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1244         if (!vma_prv)
1245                 return -ENOMEM;
1246
1247         vma_prv->vma = vma;
1248         vma->vm_private_data = vma_prv;
1249         vma->vm_ops =  &mlx5_ib_vm_ops;
1250
1251         list_add(&vma_prv->list, vma_head);
1252
1253         return 0;
1254 }
1255
1256 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1257 {
1258         int ret;
1259         struct vm_area_struct *vma;
1260         struct mlx5_ib_vma_private_data *vma_private, *n;
1261         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1262         struct task_struct *owning_process  = NULL;
1263         struct mm_struct   *owning_mm       = NULL;
1264
1265         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1266         if (!owning_process)
1267                 return;
1268
1269         owning_mm = get_task_mm(owning_process);
1270         if (!owning_mm) {
1271                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1272                 while (1) {
1273                         put_task_struct(owning_process);
1274                         usleep_range(1000, 2000);
1275                         owning_process = get_pid_task(ibcontext->tgid,
1276                                                       PIDTYPE_PID);
1277                         if (!owning_process ||
1278                             owning_process->state == TASK_DEAD) {
1279                                 pr_info("disassociate ucontext done, task was terminated\n");
1280                                 /* in case task was dead need to release the
1281                                  * task struct.
1282                                  */
1283                                 if (owning_process)
1284                                         put_task_struct(owning_process);
1285                                 return;
1286                         }
1287                 }
1288         }
1289
1290         /* need to protect from a race on closing the vma as part of
1291          * mlx5_ib_vma_close.
1292          */
1293         down_read(&owning_mm->mmap_sem);
1294         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1295                                  list) {
1296                 vma = vma_private->vma;
1297                 ret = zap_vma_ptes(vma, vma->vm_start,
1298                                    PAGE_SIZE);
1299                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1300                 /* context going to be destroyed, should
1301                  * not access ops any more.
1302                  */
1303                 vma->vm_ops = NULL;
1304                 list_del(&vma_private->list);
1305                 kfree(vma_private);
1306         }
1307         up_read(&owning_mm->mmap_sem);
1308         mmput(owning_mm);
1309         put_task_struct(owning_process);
1310 }
1311
1312 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1313 {
1314         switch (cmd) {
1315         case MLX5_IB_MMAP_WC_PAGE:
1316                 return "WC";
1317         case MLX5_IB_MMAP_REGULAR_PAGE:
1318                 return "best effort WC";
1319         case MLX5_IB_MMAP_NC_PAGE:
1320                 return "NC";
1321         default:
1322                 return NULL;
1323         }
1324 }
1325
1326 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1327                     struct vm_area_struct *vma,
1328                     struct mlx5_ib_ucontext *context)
1329 {
1330         struct mlx5_uuar_info *uuari = &context->uuari;
1331         int err;
1332         unsigned long idx;
1333         phys_addr_t pfn, pa;
1334         pgprot_t prot;
1335
1336         switch (cmd) {
1337         case MLX5_IB_MMAP_WC_PAGE:
1338 /* Some architectures don't support WC memory */
1339 #if defined(CONFIG_X86)
1340                 if (!pat_enabled())
1341                         return -EPERM;
1342 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1343                         return -EPERM;
1344 #endif
1345         /* fall through */
1346         case MLX5_IB_MMAP_REGULAR_PAGE:
1347                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1348                 prot = pgprot_writecombine(vma->vm_page_prot);
1349                 break;
1350         case MLX5_IB_MMAP_NC_PAGE:
1351                 prot = pgprot_noncached(vma->vm_page_prot);
1352                 break;
1353         default:
1354                 return -EINVAL;
1355         }
1356
1357         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1358                 return -EINVAL;
1359
1360         idx = get_index(vma->vm_pgoff);
1361         if (idx >= uuari->num_uars)
1362                 return -EINVAL;
1363
1364         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1365         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1366
1367         vma->vm_page_prot = prot;
1368         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1369                                  PAGE_SIZE, vma->vm_page_prot);
1370         if (err) {
1371                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1372                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1373                 return -EAGAIN;
1374         }
1375
1376         pa = pfn << PAGE_SHIFT;
1377         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1378                     vma->vm_start, &pa);
1379
1380         return mlx5_ib_set_vma_data(vma, context);
1381 }
1382
1383 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1384 {
1385         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1386         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1387         unsigned long command;
1388         phys_addr_t pfn;
1389
1390         command = get_command(vma->vm_pgoff);
1391         switch (command) {
1392         case MLX5_IB_MMAP_WC_PAGE:
1393         case MLX5_IB_MMAP_NC_PAGE:
1394         case MLX5_IB_MMAP_REGULAR_PAGE:
1395                 return uar_mmap(dev, command, vma, context);
1396
1397         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1398                 return -ENOSYS;
1399
1400         case MLX5_IB_MMAP_CORE_CLOCK:
1401                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1402                         return -EINVAL;
1403
1404                 if (vma->vm_flags & VM_WRITE)
1405                         return -EPERM;
1406
1407                 /* Don't expose to user-space information it shouldn't have */
1408                 if (PAGE_SIZE > 4096)
1409                         return -EOPNOTSUPP;
1410
1411                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1412                 pfn = (dev->mdev->iseg_base +
1413                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1414                         PAGE_SHIFT;
1415                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1416                                        PAGE_SIZE, vma->vm_page_prot))
1417                         return -EAGAIN;
1418
1419                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1420                             vma->vm_start,
1421                             (unsigned long long)pfn << PAGE_SHIFT);
1422                 break;
1423
1424         default:
1425                 return -EINVAL;
1426         }
1427
1428         return 0;
1429 }
1430
1431 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1432                                       struct ib_ucontext *context,
1433                                       struct ib_udata *udata)
1434 {
1435         struct mlx5_ib_alloc_pd_resp resp;
1436         struct mlx5_ib_pd *pd;
1437         int err;
1438
1439         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1440         if (!pd)
1441                 return ERR_PTR(-ENOMEM);
1442
1443         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1444         if (err) {
1445                 kfree(pd);
1446                 return ERR_PTR(err);
1447         }
1448
1449         if (context) {
1450                 resp.pdn = pd->pdn;
1451                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1452                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1453                         kfree(pd);
1454                         return ERR_PTR(-EFAULT);
1455                 }
1456         }
1457
1458         return &pd->ibpd;
1459 }
1460
1461 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1462 {
1463         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1464         struct mlx5_ib_pd *mpd = to_mpd(pd);
1465
1466         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1467         kfree(mpd);
1468
1469         return 0;
1470 }
1471
1472 enum {
1473         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1474         MATCH_CRITERIA_ENABLE_MISC_BIT,
1475         MATCH_CRITERIA_ENABLE_INNER_BIT
1476 };
1477
1478 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1479         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1480                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1481
1482 static u8 get_match_criteria_enable(u32 *match_criteria)
1483 {
1484         u8 match_criteria_enable;
1485
1486         match_criteria_enable =
1487                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1488                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1489         match_criteria_enable |=
1490                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1491                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1492         match_criteria_enable |=
1493                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1494                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1495
1496         return match_criteria_enable;
1497 }
1498
1499 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1500 {
1501         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1502         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1503 }
1504
1505 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1506 {
1507         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1508         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1509         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1510         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1511 }
1512
1513 #define LAST_ETH_FIELD vlan_tag
1514 #define LAST_IB_FIELD sl
1515 #define LAST_IPV4_FIELD tos
1516 #define LAST_IPV6_FIELD traffic_class
1517 #define LAST_TCP_UDP_FIELD src_port
1518
1519 /* Field is the last supported field */
1520 #define FIELDS_NOT_SUPPORTED(filter, field)\
1521         memchr_inv((void *)&filter.field  +\
1522                    sizeof(filter.field), 0,\
1523                    sizeof(filter) -\
1524                    offsetof(typeof(filter), field) -\
1525                    sizeof(filter.field))
1526
1527 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1528                            const union ib_flow_spec *ib_spec)
1529 {
1530         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1531                                              outer_headers);
1532         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1533                                              outer_headers);
1534         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1535                                            misc_parameters);
1536         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1537                                            misc_parameters);
1538
1539         switch (ib_spec->type) {
1540         case IB_FLOW_SPEC_ETH:
1541                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1542                         return -ENOTSUPP;
1543
1544                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1545                                              dmac_47_16),
1546                                 ib_spec->eth.mask.dst_mac);
1547                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1548                                              dmac_47_16),
1549                                 ib_spec->eth.val.dst_mac);
1550
1551                 if (ib_spec->eth.mask.vlan_tag) {
1552                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1553                                  vlan_tag, 1);
1554                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1555                                  vlan_tag, 1);
1556
1557                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1558                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1559                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1560                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1561
1562                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1563                                  first_cfi,
1564                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1565                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1566                                  first_cfi,
1567                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1568
1569                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1570                                  first_prio,
1571                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1572                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1573                                  first_prio,
1574                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1575                 }
1576                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1577                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1578                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1579                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1580                 break;
1581         case IB_FLOW_SPEC_IPV4:
1582                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1583                         return -ENOTSUPP;
1584
1585                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1586                          ethertype, 0xffff);
1587                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1588                          ethertype, ETH_P_IP);
1589
1590                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1591                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1592                        &ib_spec->ipv4.mask.src_ip,
1593                        sizeof(ib_spec->ipv4.mask.src_ip));
1594                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1595                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1596                        &ib_spec->ipv4.val.src_ip,
1597                        sizeof(ib_spec->ipv4.val.src_ip));
1598                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1599                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1600                        &ib_spec->ipv4.mask.dst_ip,
1601                        sizeof(ib_spec->ipv4.mask.dst_ip));
1602                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1603                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1604                        &ib_spec->ipv4.val.dst_ip,
1605                        sizeof(ib_spec->ipv4.val.dst_ip));
1606
1607                 set_tos(outer_headers_c, outer_headers_v,
1608                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1609
1610                 set_proto(outer_headers_c, outer_headers_v,
1611                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1612                 break;
1613         case IB_FLOW_SPEC_IPV6:
1614                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1615                         return -ENOTSUPP;
1616
1617                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1618                          ethertype, 0xffff);
1619                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1620                          ethertype, ETH_P_IPV6);
1621
1622                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1623                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1624                        &ib_spec->ipv6.mask.src_ip,
1625                        sizeof(ib_spec->ipv6.mask.src_ip));
1626                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1627                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1628                        &ib_spec->ipv6.val.src_ip,
1629                        sizeof(ib_spec->ipv6.val.src_ip));
1630                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1631                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1632                        &ib_spec->ipv6.mask.dst_ip,
1633                        sizeof(ib_spec->ipv6.mask.dst_ip));
1634                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1635                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1636                        &ib_spec->ipv6.val.dst_ip,
1637                        sizeof(ib_spec->ipv6.val.dst_ip));
1638
1639                 set_tos(outer_headers_c, outer_headers_v,
1640                         ib_spec->ipv6.mask.traffic_class,
1641                         ib_spec->ipv6.val.traffic_class);
1642
1643                 set_proto(outer_headers_c, outer_headers_v,
1644                           ib_spec->ipv6.mask.next_hdr,
1645                           ib_spec->ipv6.val.next_hdr);
1646
1647                 MLX5_SET(fte_match_set_misc, misc_params_c,
1648                          outer_ipv6_flow_label,
1649                          ntohl(ib_spec->ipv6.mask.flow_label));
1650                 MLX5_SET(fte_match_set_misc, misc_params_v,
1651                          outer_ipv6_flow_label,
1652                          ntohl(ib_spec->ipv6.val.flow_label));
1653                 break;
1654         case IB_FLOW_SPEC_TCP:
1655                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1656                                          LAST_TCP_UDP_FIELD))
1657                         return -ENOTSUPP;
1658
1659                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1660                          0xff);
1661                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1662                          IPPROTO_TCP);
1663
1664                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1665                          ntohs(ib_spec->tcp_udp.mask.src_port));
1666                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1667                          ntohs(ib_spec->tcp_udp.val.src_port));
1668
1669                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1670                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1671                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1672                          ntohs(ib_spec->tcp_udp.val.dst_port));
1673                 break;
1674         case IB_FLOW_SPEC_UDP:
1675                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1676                                          LAST_TCP_UDP_FIELD))
1677                         return -ENOTSUPP;
1678
1679                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1680                          0xff);
1681                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1682                          IPPROTO_UDP);
1683
1684                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1685                          ntohs(ib_spec->tcp_udp.mask.src_port));
1686                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1687                          ntohs(ib_spec->tcp_udp.val.src_port));
1688
1689                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1690                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1691                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1692                          ntohs(ib_spec->tcp_udp.val.dst_port));
1693                 break;
1694         default:
1695                 return -EINVAL;
1696         }
1697
1698         return 0;
1699 }
1700
1701 /* If a flow could catch both multicast and unicast packets,
1702  * it won't fall into the multicast flow steering table and this rule
1703  * could steal other multicast packets.
1704  */
1705 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1706 {
1707         struct ib_flow_spec_eth *eth_spec;
1708
1709         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1710             ib_attr->size < sizeof(struct ib_flow_attr) +
1711             sizeof(struct ib_flow_spec_eth) ||
1712             ib_attr->num_of_specs < 1)
1713                 return false;
1714
1715         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1716         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1717             eth_spec->size != sizeof(*eth_spec))
1718                 return false;
1719
1720         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1721                is_multicast_ether_addr(eth_spec->val.dst_mac);
1722 }
1723
1724 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1725 {
1726         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1727         bool has_ipv4_spec = false;
1728         bool eth_type_ipv4 = true;
1729         unsigned int spec_index;
1730
1731         /* Validate that ethertype is correct */
1732         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1733                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1734                     ib_spec->eth.mask.ether_type) {
1735                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1736                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1737                                 eth_type_ipv4 = false;
1738                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1739                         has_ipv4_spec = true;
1740                 }
1741                 ib_spec = (void *)ib_spec + ib_spec->size;
1742         }
1743         return !has_ipv4_spec || eth_type_ipv4;
1744 }
1745
1746 static void put_flow_table(struct mlx5_ib_dev *dev,
1747                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1748 {
1749         prio->refcount -= !!ft_added;
1750         if (!prio->refcount) {
1751                 mlx5_destroy_flow_table(prio->flow_table);
1752                 prio->flow_table = NULL;
1753         }
1754 }
1755
1756 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1757 {
1758         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1759         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1760                                                           struct mlx5_ib_flow_handler,
1761                                                           ibflow);
1762         struct mlx5_ib_flow_handler *iter, *tmp;
1763
1764         mutex_lock(&dev->flow_db.lock);
1765
1766         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1767                 mlx5_del_flow_rule(iter->rule);
1768                 put_flow_table(dev, iter->prio, true);
1769                 list_del(&iter->list);
1770                 kfree(iter);
1771         }
1772
1773         mlx5_del_flow_rule(handler->rule);
1774         put_flow_table(dev, handler->prio, true);
1775         mutex_unlock(&dev->flow_db.lock);
1776
1777         kfree(handler);
1778
1779         return 0;
1780 }
1781
1782 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1783 {
1784         priority *= 2;
1785         if (!dont_trap)
1786                 priority++;
1787         return priority;
1788 }
1789
1790 enum flow_table_type {
1791         MLX5_IB_FT_RX,
1792         MLX5_IB_FT_TX
1793 };
1794
1795 #define MLX5_FS_MAX_TYPES        10
1796 #define MLX5_FS_MAX_ENTRIES      32000UL
1797 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1798                                                 struct ib_flow_attr *flow_attr,
1799                                                 enum flow_table_type ft_type)
1800 {
1801         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1802         struct mlx5_flow_namespace *ns = NULL;
1803         struct mlx5_ib_flow_prio *prio;
1804         struct mlx5_flow_table *ft;
1805         int num_entries;
1806         int num_groups;
1807         int priority;
1808         int err = 0;
1809
1810         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1811                 if (flow_is_multicast_only(flow_attr) &&
1812                     !dont_trap)
1813                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1814                 else
1815                         priority = ib_prio_to_core_prio(flow_attr->priority,
1816                                                         dont_trap);
1817                 ns = mlx5_get_flow_namespace(dev->mdev,
1818                                              MLX5_FLOW_NAMESPACE_BYPASS);
1819                 num_entries = MLX5_FS_MAX_ENTRIES;
1820                 num_groups = MLX5_FS_MAX_TYPES;
1821                 prio = &dev->flow_db.prios[priority];
1822         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1823                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1824                 ns = mlx5_get_flow_namespace(dev->mdev,
1825                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1826                 build_leftovers_ft_param(&priority,
1827                                          &num_entries,
1828                                          &num_groups);
1829                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1830         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1831                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1832                                         allow_sniffer_and_nic_rx_shared_tir))
1833                         return ERR_PTR(-ENOTSUPP);
1834
1835                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1836                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1837                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1838
1839                 prio = &dev->flow_db.sniffer[ft_type];
1840                 priority = 0;
1841                 num_entries = 1;
1842                 num_groups = 1;
1843         }
1844
1845         if (!ns)
1846                 return ERR_PTR(-ENOTSUPP);
1847
1848         ft = prio->flow_table;
1849         if (!ft) {
1850                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1851                                                          num_entries,
1852                                                          num_groups,
1853                                                          0);
1854
1855                 if (!IS_ERR(ft)) {
1856                         prio->refcount = 0;
1857                         prio->flow_table = ft;
1858                 } else {
1859                         err = PTR_ERR(ft);
1860                 }
1861         }
1862
1863         return err ? ERR_PTR(err) : prio;
1864 }
1865
1866 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1867                                                      struct mlx5_ib_flow_prio *ft_prio,
1868                                                      const struct ib_flow_attr *flow_attr,
1869                                                      struct mlx5_flow_destination *dst)
1870 {
1871         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1872         struct mlx5_ib_flow_handler *handler;
1873         struct mlx5_flow_spec *spec;
1874         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1875         unsigned int spec_index;
1876         u32 action;
1877         int err = 0;
1878
1879         if (!is_valid_attr(flow_attr))
1880                 return ERR_PTR(-EINVAL);
1881
1882         spec = mlx5_vzalloc(sizeof(*spec));
1883         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1884         if (!handler || !spec) {
1885                 err = -ENOMEM;
1886                 goto free;
1887         }
1888
1889         INIT_LIST_HEAD(&handler->list);
1890
1891         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1892                 err = parse_flow_attr(spec->match_criteria,
1893                                       spec->match_value, ib_flow);
1894                 if (err < 0)
1895                         goto free;
1896
1897                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1898         }
1899
1900         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1901         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1902                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1903         handler->rule = mlx5_add_flow_rule(ft, spec,
1904                                            action,
1905                                            MLX5_FS_DEFAULT_FLOW_TAG,
1906                                            dst);
1907
1908         if (IS_ERR(handler->rule)) {
1909                 err = PTR_ERR(handler->rule);
1910                 goto free;
1911         }
1912
1913         ft_prio->refcount++;
1914         handler->prio = ft_prio;
1915
1916         ft_prio->flow_table = ft;
1917 free:
1918         if (err)
1919                 kfree(handler);
1920         kvfree(spec);
1921         return err ? ERR_PTR(err) : handler;
1922 }
1923
1924 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1925                                                           struct mlx5_ib_flow_prio *ft_prio,
1926                                                           struct ib_flow_attr *flow_attr,
1927                                                           struct mlx5_flow_destination *dst)
1928 {
1929         struct mlx5_ib_flow_handler *handler_dst = NULL;
1930         struct mlx5_ib_flow_handler *handler = NULL;
1931
1932         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1933         if (!IS_ERR(handler)) {
1934                 handler_dst = create_flow_rule(dev, ft_prio,
1935                                                flow_attr, dst);
1936                 if (IS_ERR(handler_dst)) {
1937                         mlx5_del_flow_rule(handler->rule);
1938                         ft_prio->refcount--;
1939                         kfree(handler);
1940                         handler = handler_dst;
1941                 } else {
1942                         list_add(&handler_dst->list, &handler->list);
1943                 }
1944         }
1945
1946         return handler;
1947 }
1948 enum {
1949         LEFTOVERS_MC,
1950         LEFTOVERS_UC,
1951 };
1952
1953 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1954                                                           struct mlx5_ib_flow_prio *ft_prio,
1955                                                           struct ib_flow_attr *flow_attr,
1956                                                           struct mlx5_flow_destination *dst)
1957 {
1958         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1959         struct mlx5_ib_flow_handler *handler = NULL;
1960
1961         static struct {
1962                 struct ib_flow_attr     flow_attr;
1963                 struct ib_flow_spec_eth eth_flow;
1964         } leftovers_specs[] = {
1965                 [LEFTOVERS_MC] = {
1966                         .flow_attr = {
1967                                 .num_of_specs = 1,
1968                                 .size = sizeof(leftovers_specs[0])
1969                         },
1970                         .eth_flow = {
1971                                 .type = IB_FLOW_SPEC_ETH,
1972                                 .size = sizeof(struct ib_flow_spec_eth),
1973                                 .mask = {.dst_mac = {0x1} },
1974                                 .val =  {.dst_mac = {0x1} }
1975                         }
1976                 },
1977                 [LEFTOVERS_UC] = {
1978                         .flow_attr = {
1979                                 .num_of_specs = 1,
1980                                 .size = sizeof(leftovers_specs[0])
1981                         },
1982                         .eth_flow = {
1983                                 .type = IB_FLOW_SPEC_ETH,
1984                                 .size = sizeof(struct ib_flow_spec_eth),
1985                                 .mask = {.dst_mac = {0x1} },
1986                                 .val = {.dst_mac = {} }
1987                         }
1988                 }
1989         };
1990
1991         handler = create_flow_rule(dev, ft_prio,
1992                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
1993                                    dst);
1994         if (!IS_ERR(handler) &&
1995             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1996                 handler_ucast = create_flow_rule(dev, ft_prio,
1997                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
1998                                                  dst);
1999                 if (IS_ERR(handler_ucast)) {
2000                         mlx5_del_flow_rule(handler->rule);
2001                         ft_prio->refcount--;
2002                         kfree(handler);
2003                         handler = handler_ucast;
2004                 } else {
2005                         list_add(&handler_ucast->list, &handler->list);
2006                 }
2007         }
2008
2009         return handler;
2010 }
2011
2012 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2013                                                         struct mlx5_ib_flow_prio *ft_rx,
2014                                                         struct mlx5_ib_flow_prio *ft_tx,
2015                                                         struct mlx5_flow_destination *dst)
2016 {
2017         struct mlx5_ib_flow_handler *handler_rx;
2018         struct mlx5_ib_flow_handler *handler_tx;
2019         int err;
2020         static const struct ib_flow_attr flow_attr  = {
2021                 .num_of_specs = 0,
2022                 .size = sizeof(flow_attr)
2023         };
2024
2025         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2026         if (IS_ERR(handler_rx)) {
2027                 err = PTR_ERR(handler_rx);
2028                 goto err;
2029         }
2030
2031         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2032         if (IS_ERR(handler_tx)) {
2033                 err = PTR_ERR(handler_tx);
2034                 goto err_tx;
2035         }
2036
2037         list_add(&handler_tx->list, &handler_rx->list);
2038
2039         return handler_rx;
2040
2041 err_tx:
2042         mlx5_del_flow_rule(handler_rx->rule);
2043         ft_rx->refcount--;
2044         kfree(handler_rx);
2045 err:
2046         return ERR_PTR(err);
2047 }
2048
2049 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2050                                            struct ib_flow_attr *flow_attr,
2051                                            int domain)
2052 {
2053         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2054         struct mlx5_ib_flow_handler *handler = NULL;
2055         struct mlx5_flow_destination *dst = NULL;
2056         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2057         struct mlx5_ib_flow_prio *ft_prio;
2058         int err;
2059
2060         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2061                 return ERR_PTR(-ENOSPC);
2062
2063         if (domain != IB_FLOW_DOMAIN_USER ||
2064             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2065             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2066                 return ERR_PTR(-EINVAL);
2067
2068         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2069         if (!dst)
2070                 return ERR_PTR(-ENOMEM);
2071
2072         mutex_lock(&dev->flow_db.lock);
2073
2074         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2075         if (IS_ERR(ft_prio)) {
2076                 err = PTR_ERR(ft_prio);
2077                 goto unlock;
2078         }
2079         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2080                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2081                 if (IS_ERR(ft_prio_tx)) {
2082                         err = PTR_ERR(ft_prio_tx);
2083                         ft_prio_tx = NULL;
2084                         goto destroy_ft;
2085                 }
2086         }
2087
2088         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2089         dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
2090
2091         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2092                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2093                         handler = create_dont_trap_rule(dev, ft_prio,
2094                                                         flow_attr, dst);
2095                 } else {
2096                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2097                                                    dst);
2098                 }
2099         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2100                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2101                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2102                                                 dst);
2103         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2104                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2105         } else {
2106                 err = -EINVAL;
2107                 goto destroy_ft;
2108         }
2109
2110         if (IS_ERR(handler)) {
2111                 err = PTR_ERR(handler);
2112                 handler = NULL;
2113                 goto destroy_ft;
2114         }
2115
2116         mutex_unlock(&dev->flow_db.lock);
2117         kfree(dst);
2118
2119         return &handler->ibflow;
2120
2121 destroy_ft:
2122         put_flow_table(dev, ft_prio, false);
2123         if (ft_prio_tx)
2124                 put_flow_table(dev, ft_prio_tx, false);
2125 unlock:
2126         mutex_unlock(&dev->flow_db.lock);
2127         kfree(dst);
2128         kfree(handler);
2129         return ERR_PTR(err);
2130 }
2131
2132 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2133 {
2134         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2135         int err;
2136
2137         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2138         if (err)
2139                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2140                              ibqp->qp_num, gid->raw);
2141
2142         return err;
2143 }
2144
2145 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2146 {
2147         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2148         int err;
2149
2150         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2151         if (err)
2152                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2153                              ibqp->qp_num, gid->raw);
2154
2155         return err;
2156 }
2157
2158 static int init_node_data(struct mlx5_ib_dev *dev)
2159 {
2160         int err;
2161
2162         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2163         if (err)
2164                 return err;
2165
2166         dev->mdev->rev_id = dev->mdev->pdev->revision;
2167
2168         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2169 }
2170
2171 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2172                              char *buf)
2173 {
2174         struct mlx5_ib_dev *dev =
2175                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2176
2177         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2178 }
2179
2180 static ssize_t show_reg_pages(struct device *device,
2181                               struct device_attribute *attr, char *buf)
2182 {
2183         struct mlx5_ib_dev *dev =
2184                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2185
2186         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2187 }
2188
2189 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2190                         char *buf)
2191 {
2192         struct mlx5_ib_dev *dev =
2193                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2194         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2195 }
2196
2197 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2198                         char *buf)
2199 {
2200         struct mlx5_ib_dev *dev =
2201                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2202         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2203 }
2204
2205 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2206                           char *buf)
2207 {
2208         struct mlx5_ib_dev *dev =
2209                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2210         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2211                        dev->mdev->board_id);
2212 }
2213
2214 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2215 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2216 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2217 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2218 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2219
2220 static struct device_attribute *mlx5_class_attributes[] = {
2221         &dev_attr_hw_rev,
2222         &dev_attr_hca_type,
2223         &dev_attr_board_id,
2224         &dev_attr_fw_pages,
2225         &dev_attr_reg_pages,
2226 };
2227
2228 static void pkey_change_handler(struct work_struct *work)
2229 {
2230         struct mlx5_ib_port_resources *ports =
2231                 container_of(work, struct mlx5_ib_port_resources,
2232                              pkey_change_work);
2233
2234         mutex_lock(&ports->devr->mutex);
2235         mlx5_ib_gsi_pkey_change(ports->gsi);
2236         mutex_unlock(&ports->devr->mutex);
2237 }
2238
2239 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2240 {
2241         struct mlx5_ib_qp *mqp;
2242         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2243         struct mlx5_core_cq *mcq;
2244         struct list_head cq_armed_list;
2245         unsigned long flags_qp;
2246         unsigned long flags_cq;
2247         unsigned long flags;
2248
2249         INIT_LIST_HEAD(&cq_armed_list);
2250
2251         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2252         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2253         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2254                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2255                 if (mqp->sq.tail != mqp->sq.head) {
2256                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2257                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2258                         if (send_mcq->mcq.comp &&
2259                             mqp->ibqp.send_cq->comp_handler) {
2260                                 if (!send_mcq->mcq.reset_notify_added) {
2261                                         send_mcq->mcq.reset_notify_added = 1;
2262                                         list_add_tail(&send_mcq->mcq.reset_notify,
2263                                                       &cq_armed_list);
2264                                 }
2265                         }
2266                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2267                 }
2268                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2269                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2270                 /* no handling is needed for SRQ */
2271                 if (!mqp->ibqp.srq) {
2272                         if (mqp->rq.tail != mqp->rq.head) {
2273                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2274                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2275                                 if (recv_mcq->mcq.comp &&
2276                                     mqp->ibqp.recv_cq->comp_handler) {
2277                                         if (!recv_mcq->mcq.reset_notify_added) {
2278                                                 recv_mcq->mcq.reset_notify_added = 1;
2279                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2280                                                               &cq_armed_list);
2281                                         }
2282                                 }
2283                                 spin_unlock_irqrestore(&recv_mcq->lock,
2284                                                        flags_cq);
2285                         }
2286                 }
2287                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2288         }
2289         /*At that point all inflight post send were put to be executed as of we
2290          * lock/unlock above locks Now need to arm all involved CQs.
2291          */
2292         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2293                 mcq->comp(mcq);
2294         }
2295         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2296 }
2297
2298 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2299                           enum mlx5_dev_event event, unsigned long param)
2300 {
2301         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2302         struct ib_event ibev;
2303
2304         u8 port = 0;
2305
2306         switch (event) {
2307         case MLX5_DEV_EVENT_SYS_ERROR:
2308                 ibdev->ib_active = false;
2309                 ibev.event = IB_EVENT_DEVICE_FATAL;
2310                 mlx5_ib_handle_internal_error(ibdev);
2311                 break;
2312
2313         case MLX5_DEV_EVENT_PORT_UP:
2314         case MLX5_DEV_EVENT_PORT_DOWN:
2315         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2316                 port = (u8)param;
2317
2318                 /* In RoCE, port up/down events are handled in
2319                  * mlx5_netdev_event().
2320                  */
2321                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2322                         IB_LINK_LAYER_ETHERNET)
2323                         return;
2324
2325                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2326                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2327                 break;
2328
2329         case MLX5_DEV_EVENT_LID_CHANGE:
2330                 ibev.event = IB_EVENT_LID_CHANGE;
2331                 port = (u8)param;
2332                 break;
2333
2334         case MLX5_DEV_EVENT_PKEY_CHANGE:
2335                 ibev.event = IB_EVENT_PKEY_CHANGE;
2336                 port = (u8)param;
2337
2338                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2339                 break;
2340
2341         case MLX5_DEV_EVENT_GUID_CHANGE:
2342                 ibev.event = IB_EVENT_GID_CHANGE;
2343                 port = (u8)param;
2344                 break;
2345
2346         case MLX5_DEV_EVENT_CLIENT_REREG:
2347                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2348                 port = (u8)param;
2349                 break;
2350         }
2351
2352         ibev.device           = &ibdev->ib_dev;
2353         ibev.element.port_num = port;
2354
2355         if (port < 1 || port > ibdev->num_ports) {
2356                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2357                 return;
2358         }
2359
2360         if (ibdev->ib_active)
2361                 ib_dispatch_event(&ibev);
2362 }
2363
2364 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2365 {
2366         int port;
2367
2368         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2369                 mlx5_query_ext_port_caps(dev, port);
2370 }
2371
2372 static int get_port_caps(struct mlx5_ib_dev *dev)
2373 {
2374         struct ib_device_attr *dprops = NULL;
2375         struct ib_port_attr *pprops = NULL;
2376         int err = -ENOMEM;
2377         int port;
2378         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2379
2380         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2381         if (!pprops)
2382                 goto out;
2383
2384         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2385         if (!dprops)
2386                 goto out;
2387
2388         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2389         if (err) {
2390                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2391                 goto out;
2392         }
2393
2394         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2395                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2396                 if (err) {
2397                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2398                                      port, err);
2399                         break;
2400                 }
2401                 dev->mdev->port_caps[port - 1].pkey_table_len =
2402                                                 dprops->max_pkeys;
2403                 dev->mdev->port_caps[port - 1].gid_table_len =
2404                                                 pprops->gid_tbl_len;
2405                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2406                             dprops->max_pkeys, pprops->gid_tbl_len);
2407         }
2408
2409 out:
2410         kfree(pprops);
2411         kfree(dprops);
2412
2413         return err;
2414 }
2415
2416 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2417 {
2418         int err;
2419
2420         err = mlx5_mr_cache_cleanup(dev);
2421         if (err)
2422                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2423
2424         mlx5_ib_destroy_qp(dev->umrc.qp);
2425         ib_free_cq(dev->umrc.cq);
2426         ib_dealloc_pd(dev->umrc.pd);
2427 }
2428
2429 enum {
2430         MAX_UMR_WR = 128,
2431 };
2432
2433 static int create_umr_res(struct mlx5_ib_dev *dev)
2434 {
2435         struct ib_qp_init_attr *init_attr = NULL;
2436         struct ib_qp_attr *attr = NULL;
2437         struct ib_pd *pd;
2438         struct ib_cq *cq;
2439         struct ib_qp *qp;
2440         int ret;
2441
2442         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2443         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2444         if (!attr || !init_attr) {
2445                 ret = -ENOMEM;
2446                 goto error_0;
2447         }
2448
2449         pd = ib_alloc_pd(&dev->ib_dev, 0);
2450         if (IS_ERR(pd)) {
2451                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2452                 ret = PTR_ERR(pd);
2453                 goto error_0;
2454         }
2455
2456         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2457         if (IS_ERR(cq)) {
2458                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2459                 ret = PTR_ERR(cq);
2460                 goto error_2;
2461         }
2462
2463         init_attr->send_cq = cq;
2464         init_attr->recv_cq = cq;
2465         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2466         init_attr->cap.max_send_wr = MAX_UMR_WR;
2467         init_attr->cap.max_send_sge = 1;
2468         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2469         init_attr->port_num = 1;
2470         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2471         if (IS_ERR(qp)) {
2472                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2473                 ret = PTR_ERR(qp);
2474                 goto error_3;
2475         }
2476         qp->device     = &dev->ib_dev;
2477         qp->real_qp    = qp;
2478         qp->uobject    = NULL;
2479         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2480
2481         attr->qp_state = IB_QPS_INIT;
2482         attr->port_num = 1;
2483         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2484                                 IB_QP_PORT, NULL);
2485         if (ret) {
2486                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2487                 goto error_4;
2488         }
2489
2490         memset(attr, 0, sizeof(*attr));
2491         attr->qp_state = IB_QPS_RTR;
2492         attr->path_mtu = IB_MTU_256;
2493
2494         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2495         if (ret) {
2496                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2497                 goto error_4;
2498         }
2499
2500         memset(attr, 0, sizeof(*attr));
2501         attr->qp_state = IB_QPS_RTS;
2502         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2503         if (ret) {
2504                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2505                 goto error_4;
2506         }
2507
2508         dev->umrc.qp = qp;
2509         dev->umrc.cq = cq;
2510         dev->umrc.pd = pd;
2511
2512         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2513         ret = mlx5_mr_cache_init(dev);
2514         if (ret) {
2515                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2516                 goto error_4;
2517         }
2518
2519         kfree(attr);
2520         kfree(init_attr);
2521
2522         return 0;
2523
2524 error_4:
2525         mlx5_ib_destroy_qp(qp);
2526
2527 error_3:
2528         ib_free_cq(cq);
2529
2530 error_2:
2531         ib_dealloc_pd(pd);
2532
2533 error_0:
2534         kfree(attr);
2535         kfree(init_attr);
2536         return ret;
2537 }
2538
2539 static int create_dev_resources(struct mlx5_ib_resources *devr)
2540 {
2541         struct ib_srq_init_attr attr;
2542         struct mlx5_ib_dev *dev;
2543         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2544         int port;
2545         int ret = 0;
2546
2547         dev = container_of(devr, struct mlx5_ib_dev, devr);
2548
2549         mutex_init(&devr->mutex);
2550
2551         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2552         if (IS_ERR(devr->p0)) {
2553                 ret = PTR_ERR(devr->p0);
2554                 goto error0;
2555         }
2556         devr->p0->device  = &dev->ib_dev;
2557         devr->p0->uobject = NULL;
2558         atomic_set(&devr->p0->usecnt, 0);
2559
2560         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2561         if (IS_ERR(devr->c0)) {
2562                 ret = PTR_ERR(devr->c0);
2563                 goto error1;
2564         }
2565         devr->c0->device        = &dev->ib_dev;
2566         devr->c0->uobject       = NULL;
2567         devr->c0->comp_handler  = NULL;
2568         devr->c0->event_handler = NULL;
2569         devr->c0->cq_context    = NULL;
2570         atomic_set(&devr->c0->usecnt, 0);
2571
2572         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2573         if (IS_ERR(devr->x0)) {
2574                 ret = PTR_ERR(devr->x0);
2575                 goto error2;
2576         }
2577         devr->x0->device = &dev->ib_dev;
2578         devr->x0->inode = NULL;
2579         atomic_set(&devr->x0->usecnt, 0);
2580         mutex_init(&devr->x0->tgt_qp_mutex);
2581         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2582
2583         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2584         if (IS_ERR(devr->x1)) {
2585                 ret = PTR_ERR(devr->x1);
2586                 goto error3;
2587         }
2588         devr->x1->device = &dev->ib_dev;
2589         devr->x1->inode = NULL;
2590         atomic_set(&devr->x1->usecnt, 0);
2591         mutex_init(&devr->x1->tgt_qp_mutex);
2592         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2593
2594         memset(&attr, 0, sizeof(attr));
2595         attr.attr.max_sge = 1;
2596         attr.attr.max_wr = 1;
2597         attr.srq_type = IB_SRQT_XRC;
2598         attr.ext.xrc.cq = devr->c0;
2599         attr.ext.xrc.xrcd = devr->x0;
2600
2601         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2602         if (IS_ERR(devr->s0)) {
2603                 ret = PTR_ERR(devr->s0);
2604                 goto error4;
2605         }
2606         devr->s0->device        = &dev->ib_dev;
2607         devr->s0->pd            = devr->p0;
2608         devr->s0->uobject       = NULL;
2609         devr->s0->event_handler = NULL;
2610         devr->s0->srq_context   = NULL;
2611         devr->s0->srq_type      = IB_SRQT_XRC;
2612         devr->s0->ext.xrc.xrcd  = devr->x0;
2613         devr->s0->ext.xrc.cq    = devr->c0;
2614         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2615         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2616         atomic_inc(&devr->p0->usecnt);
2617         atomic_set(&devr->s0->usecnt, 0);
2618
2619         memset(&attr, 0, sizeof(attr));
2620         attr.attr.max_sge = 1;
2621         attr.attr.max_wr = 1;
2622         attr.srq_type = IB_SRQT_BASIC;
2623         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2624         if (IS_ERR(devr->s1)) {
2625                 ret = PTR_ERR(devr->s1);
2626                 goto error5;
2627         }
2628         devr->s1->device        = &dev->ib_dev;
2629         devr->s1->pd            = devr->p0;
2630         devr->s1->uobject       = NULL;
2631         devr->s1->event_handler = NULL;
2632         devr->s1->srq_context   = NULL;
2633         devr->s1->srq_type      = IB_SRQT_BASIC;
2634         devr->s1->ext.xrc.cq    = devr->c0;
2635         atomic_inc(&devr->p0->usecnt);
2636         atomic_set(&devr->s0->usecnt, 0);
2637
2638         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2639                 INIT_WORK(&devr->ports[port].pkey_change_work,
2640                           pkey_change_handler);
2641                 devr->ports[port].devr = devr;
2642         }
2643
2644         return 0;
2645
2646 error5:
2647         mlx5_ib_destroy_srq(devr->s0);
2648 error4:
2649         mlx5_ib_dealloc_xrcd(devr->x1);
2650 error3:
2651         mlx5_ib_dealloc_xrcd(devr->x0);
2652 error2:
2653         mlx5_ib_destroy_cq(devr->c0);
2654 error1:
2655         mlx5_ib_dealloc_pd(devr->p0);
2656 error0:
2657         return ret;
2658 }
2659
2660 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2661 {
2662         struct mlx5_ib_dev *dev =
2663                 container_of(devr, struct mlx5_ib_dev, devr);
2664         int port;
2665
2666         mlx5_ib_destroy_srq(devr->s1);
2667         mlx5_ib_destroy_srq(devr->s0);
2668         mlx5_ib_dealloc_xrcd(devr->x0);
2669         mlx5_ib_dealloc_xrcd(devr->x1);
2670         mlx5_ib_destroy_cq(devr->c0);
2671         mlx5_ib_dealloc_pd(devr->p0);
2672
2673         /* Make sure no change P_Key work items are still executing */
2674         for (port = 0; port < dev->num_ports; ++port)
2675                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2676 }
2677
2678 static u32 get_core_cap_flags(struct ib_device *ibdev)
2679 {
2680         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2681         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2682         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2683         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2684         u32 ret = 0;
2685
2686         if (ll == IB_LINK_LAYER_INFINIBAND)
2687                 return RDMA_CORE_PORT_IBA_IB;
2688
2689         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2690                 return 0;
2691
2692         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2693                 return 0;
2694
2695         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2696                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2697
2698         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2699                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2700
2701         return ret;
2702 }
2703
2704 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2705                                struct ib_port_immutable *immutable)
2706 {
2707         struct ib_port_attr attr;
2708         int err;
2709
2710         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2711         if (err)
2712                 return err;
2713
2714         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2715         immutable->gid_tbl_len = attr.gid_tbl_len;
2716         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2717         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2718
2719         return 0;
2720 }
2721
2722 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2723                            size_t str_len)
2724 {
2725         struct mlx5_ib_dev *dev =
2726                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2727         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2728                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2729 }
2730
2731 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2732 {
2733         struct mlx5_core_dev *mdev = dev->mdev;
2734         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2735                                                                  MLX5_FLOW_NAMESPACE_LAG);
2736         struct mlx5_flow_table *ft;
2737         int err;
2738
2739         if (!ns || !mlx5_lag_is_active(mdev))
2740                 return 0;
2741
2742         err = mlx5_cmd_create_vport_lag(mdev);
2743         if (err)
2744                 return err;
2745
2746         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2747         if (IS_ERR(ft)) {
2748                 err = PTR_ERR(ft);
2749                 goto err_destroy_vport_lag;
2750         }
2751
2752         dev->flow_db.lag_demux_ft = ft;
2753         return 0;
2754
2755 err_destroy_vport_lag:
2756         mlx5_cmd_destroy_vport_lag(mdev);
2757         return err;
2758 }
2759
2760 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2761 {
2762         struct mlx5_core_dev *mdev = dev->mdev;
2763
2764         if (dev->flow_db.lag_demux_ft) {
2765                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2766                 dev->flow_db.lag_demux_ft = NULL;
2767
2768                 mlx5_cmd_destroy_vport_lag(mdev);
2769         }
2770 }
2771
2772 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2773 {
2774         if (dev->roce.nb.notifier_call) {
2775                 unregister_netdevice_notifier(&dev->roce.nb);
2776                 dev->roce.nb.notifier_call = NULL;
2777         }
2778 }
2779
2780 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2781 {
2782         int err;
2783
2784         dev->roce.nb.notifier_call = mlx5_netdev_event;
2785         err = register_netdevice_notifier(&dev->roce.nb);
2786         if (err) {
2787                 dev->roce.nb.notifier_call = NULL;
2788                 return err;
2789         }
2790
2791         err = mlx5_nic_vport_enable_roce(dev->mdev);
2792         if (err)
2793                 goto err_unregister_netdevice_notifier;
2794
2795         err = mlx5_roce_lag_init(dev);
2796         if (err)
2797                 goto err_disable_roce;
2798
2799         return 0;
2800
2801 err_disable_roce:
2802         mlx5_nic_vport_disable_roce(dev->mdev);
2803
2804 err_unregister_netdevice_notifier:
2805         mlx5_remove_roce_notifier(dev);
2806         return err;
2807 }
2808
2809 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2810 {
2811         mlx5_roce_lag_cleanup(dev);
2812         mlx5_nic_vport_disable_roce(dev->mdev);
2813 }
2814
2815 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2816 {
2817         unsigned int i;
2818
2819         for (i = 0; i < dev->num_ports; i++)
2820                 mlx5_core_dealloc_q_counter(dev->mdev,
2821                                             dev->port[i].q_cnt_id);
2822 }
2823
2824 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2825 {
2826         int i;
2827         int ret;
2828
2829         for (i = 0; i < dev->num_ports; i++) {
2830                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2831                                                 &dev->port[i].q_cnt_id);
2832                 if (ret) {
2833                         mlx5_ib_warn(dev,
2834                                      "couldn't allocate queue counter for port %d, err %d\n",
2835                                      i + 1, ret);
2836                         goto dealloc_counters;
2837                 }
2838         }
2839
2840         return 0;
2841
2842 dealloc_counters:
2843         while (--i >= 0)
2844                 mlx5_core_dealloc_q_counter(dev->mdev,
2845                                             dev->port[i].q_cnt_id);
2846
2847         return ret;
2848 }
2849
2850 static const char * const names[] = {
2851         "rx_write_requests",
2852         "rx_read_requests",
2853         "rx_atomic_requests",
2854         "out_of_buffer",
2855         "out_of_sequence",
2856         "duplicate_request",
2857         "rnr_nak_retry_err",
2858         "packet_seq_err",
2859         "implied_nak_seq_err",
2860         "local_ack_timeout_err",
2861 };
2862
2863 static const size_t stats_offsets[] = {
2864         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2865         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2866         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2867         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2868         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2869         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2870         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2871         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2872         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2873         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2874 };
2875
2876 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2877                                                     u8 port_num)
2878 {
2879         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2880
2881         /* We support only per port stats */
2882         if (port_num == 0)
2883                 return NULL;
2884
2885         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2886                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2887 }
2888
2889 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2890                                 struct rdma_hw_stats *stats,
2891                                 u8 port, int index)
2892 {
2893         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2894         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2895         void *out;
2896         __be32 val;
2897         int ret;
2898         int i;
2899
2900         if (!port || !stats)
2901                 return -ENOSYS;
2902
2903         out = mlx5_vzalloc(outlen);
2904         if (!out)
2905                 return -ENOMEM;
2906
2907         ret = mlx5_core_query_q_counter(dev->mdev,
2908                                         dev->port[port - 1].q_cnt_id, 0,
2909                                         out, outlen);
2910         if (ret)
2911                 goto free;
2912
2913         for (i = 0; i < ARRAY_SIZE(names); i++) {
2914                 val = *(__be32 *)(out + stats_offsets[i]);
2915                 stats->value[i] = (u64)be32_to_cpu(val);
2916         }
2917 free:
2918         kvfree(out);
2919         return ARRAY_SIZE(names);
2920 }
2921
2922 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2923 {
2924         struct mlx5_ib_dev *dev;
2925         enum rdma_link_layer ll;
2926         int port_type_cap;
2927         const char *name;
2928         int err;
2929         int i;
2930
2931         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2932         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2933
2934         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2935                 return NULL;
2936
2937         printk_once(KERN_INFO "%s", mlx5_version);
2938
2939         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2940         if (!dev)
2941                 return NULL;
2942
2943         dev->mdev = mdev;
2944
2945         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2946                             GFP_KERNEL);
2947         if (!dev->port)
2948                 goto err_dealloc;
2949
2950         rwlock_init(&dev->roce.netdev_lock);
2951         err = get_port_caps(dev);
2952         if (err)
2953                 goto err_free_port;
2954
2955         if (mlx5_use_mad_ifc(dev))
2956                 get_ext_port_caps(dev);
2957
2958         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2959
2960         if (!mlx5_lag_is_active(mdev))
2961                 name = "mlx5_%d";
2962         else
2963                 name = "mlx5_bond_%d";
2964
2965         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
2966         dev->ib_dev.owner               = THIS_MODULE;
2967         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
2968         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
2969         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
2970         dev->ib_dev.phys_port_cnt     = dev->num_ports;
2971         dev->ib_dev.num_comp_vectors    =
2972                 dev->mdev->priv.eq_table.num_comp_vectors;
2973         dev->ib_dev.dma_device  = &mdev->pdev->dev;
2974
2975         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
2976         dev->ib_dev.uverbs_cmd_mask     =
2977                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
2978                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
2979                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
2980                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
2981                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
2982                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2983                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
2984                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2985                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2986                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2987                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2988                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2989                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2990                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2991                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2992                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2993                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2994                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2995                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2996                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2997                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2998                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2999                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3000                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3001         dev->ib_dev.uverbs_ex_cmd_mask =
3002                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3003                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3004                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3005
3006         dev->ib_dev.query_device        = mlx5_ib_query_device;
3007         dev->ib_dev.query_port          = mlx5_ib_query_port;
3008         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3009         if (ll == IB_LINK_LAYER_ETHERNET)
3010                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3011         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3012         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3013         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3014         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3015         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3016         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3017         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3018         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3019         dev->ib_dev.mmap                = mlx5_ib_mmap;
3020         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3021         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3022         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3023         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3024         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3025         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3026         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3027         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3028         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3029         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3030         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3031         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3032         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3033         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3034         dev->ib_dev.post_send           = mlx5_ib_post_send;
3035         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3036         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3037         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3038         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3039         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3040         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3041         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3042         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3043         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3044         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3045         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3046         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3047         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3048         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3049         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3050         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3051         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3052         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3053         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3054         if (mlx5_core_is_pf(mdev)) {
3055                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3056                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3057                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3058                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3059         }
3060
3061         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3062
3063         mlx5_ib_internal_fill_odp_caps(dev);
3064
3065         if (MLX5_CAP_GEN(mdev, imaicl)) {
3066                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3067                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3068                 dev->ib_dev.uverbs_cmd_mask |=
3069                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3070                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3071         }
3072
3073         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3074             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3075                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3076                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3077         }
3078
3079         if (MLX5_CAP_GEN(mdev, xrc)) {
3080                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3081                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3082                 dev->ib_dev.uverbs_cmd_mask |=
3083                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3084                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3085         }
3086
3087         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3088             IB_LINK_LAYER_ETHERNET) {
3089                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3090                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3091                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3092                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3093                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3094                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3095                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3096                 dev->ib_dev.uverbs_ex_cmd_mask |=
3097                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3098                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3099                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3100                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3101                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3102                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3103                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3104         }
3105         err = init_node_data(dev);
3106         if (err)
3107                 goto err_dealloc;
3108
3109         mutex_init(&dev->flow_db.lock);
3110         mutex_init(&dev->cap_mask_mutex);
3111         INIT_LIST_HEAD(&dev->qp_list);
3112         spin_lock_init(&dev->reset_flow_resource_lock);
3113
3114         if (ll == IB_LINK_LAYER_ETHERNET) {
3115                 err = mlx5_enable_roce(dev);
3116                 if (err)
3117                         goto err_dealloc;
3118         }
3119
3120         err = create_dev_resources(&dev->devr);
3121         if (err)
3122                 goto err_disable_roce;
3123
3124         err = mlx5_ib_odp_init_one(dev);
3125         if (err)
3126                 goto err_rsrc;
3127
3128         err = mlx5_ib_alloc_q_counters(dev);
3129         if (err)
3130                 goto err_odp;
3131
3132         err = ib_register_device(&dev->ib_dev, NULL);
3133         if (err)
3134                 goto err_q_cnt;
3135
3136         err = create_umr_res(dev);
3137         if (err)
3138                 goto err_dev;
3139
3140         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3141                 err = device_create_file(&dev->ib_dev.dev,
3142                                          mlx5_class_attributes[i]);
3143                 if (err)
3144                         goto err_umrc;
3145         }
3146
3147         dev->ib_active = true;
3148
3149         return dev;
3150
3151 err_umrc:
3152         destroy_umrc_res(dev);
3153
3154 err_dev:
3155         ib_unregister_device(&dev->ib_dev);
3156
3157 err_q_cnt:
3158         mlx5_ib_dealloc_q_counters(dev);
3159
3160 err_odp:
3161         mlx5_ib_odp_remove_one(dev);
3162
3163 err_rsrc:
3164         destroy_dev_resources(&dev->devr);
3165
3166 err_disable_roce:
3167         if (ll == IB_LINK_LAYER_ETHERNET) {
3168                 mlx5_disable_roce(dev);
3169                 mlx5_remove_roce_notifier(dev);
3170         }
3171
3172 err_free_port:
3173         kfree(dev->port);
3174
3175 err_dealloc:
3176         ib_dealloc_device((struct ib_device *)dev);
3177
3178         return NULL;
3179 }
3180
3181 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3182 {
3183         struct mlx5_ib_dev *dev = context;
3184         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3185
3186         mlx5_remove_roce_notifier(dev);
3187         ib_unregister_device(&dev->ib_dev);
3188         mlx5_ib_dealloc_q_counters(dev);
3189         destroy_umrc_res(dev);
3190         mlx5_ib_odp_remove_one(dev);
3191         destroy_dev_resources(&dev->devr);
3192         if (ll == IB_LINK_LAYER_ETHERNET)
3193                 mlx5_disable_roce(dev);
3194         kfree(dev->port);
3195         ib_dealloc_device(&dev->ib_dev);
3196 }
3197
3198 static struct mlx5_interface mlx5_ib_interface = {
3199         .add            = mlx5_ib_add,
3200         .remove         = mlx5_ib_remove,
3201         .event          = mlx5_ib_event,
3202         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3203 };
3204
3205 static int __init mlx5_ib_init(void)
3206 {
3207         int err;
3208
3209         if (deprecated_prof_sel != 2)
3210                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3211
3212         err = mlx5_ib_odp_init();
3213         if (err)
3214                 return err;
3215
3216         err = mlx5_register_interface(&mlx5_ib_interface);
3217         if (err)
3218                 goto clean_odp;
3219
3220         return err;
3221
3222 clean_odp:
3223         mlx5_ib_odp_cleanup();
3224         return err;
3225 }
3226
3227 static void __exit mlx5_ib_cleanup(void)
3228 {
3229         mlx5_unregister_interface(&mlx5_ib_interface);
3230         mlx5_ib_odp_cleanup();
3231 }
3232
3233 module_init(mlx5_ib_init);
3234 module_exit(mlx5_ib_cleanup);