drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include "mlx5_ib.h"
  38 #include "user.h"
  39
  40 /* not supported currently */
  41 static int wq_signature;
  42
  43 enum {
  44         MLX5_IB_ACK_REQ_FREQ    = 8,
  45 };
  46
  47 enum {
  48         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  49         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  50         MLX5_IB_LINK_TYPE_IB            = 0,
  51         MLX5_IB_LINK_TYPE_ETH           = 1
  52 };
  53
  54 enum {
  55         MLX5_IB_SQ_STRIDE       = 6,
  56         MLX5_IB_CACHE_LINE_SIZE = 64,
  57 };
  58
  59 static const u32 mlx5_ib_opcode[] = {
  60         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  61         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  62         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  63         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  64         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  65         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  66         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  67         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  68         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  69         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  70         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  71         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  72         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  73         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  74 };
  75
  76 struct mlx5_wqe_eth_pad {
  77         u8 rsvd0[16];
  78 };
  79
  80 static int is_qp0(enum ib_qp_type qp_type)
  81 {
  82         return qp_type == IB_QPT_SMI;
  83 }
  84
  85 static int is_sqp(enum ib_qp_type qp_type)
  86 {
  87         return is_qp0(qp_type) || is_qp1(qp_type);
  88 }
  89
  90 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  91 {
  92         return mlx5_buf_offset(&qp->buf, offset);
  93 }
  94
  95 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
  96 {
  97         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
  98 }
  99
 100 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 101 {
 102         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 103 }
 104
 105 /**
 106  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 107  *
 108  * @qp: QP to copy from.
 109  * @send: copy from the send queue when non-zero, use the receive queue
 110  *        otherwise.
 111  * @wqe_index:  index to start copying from. For send work queues, the
 112  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 113  *              For receive work queue, it is the number of work queue
 114  *              element in the queue.
 115  * @buffer: destination buffer.
 116  * @length: maximum number of bytes to copy.
 117  *
 118  * Copies at least a single WQE, but may copy more data.
 119  *
 120  * Return: the number of bytes copied, or an error code.
 121  */
 122 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 123                           void *buffer, u32 length,
 124                           struct mlx5_ib_qp_base *base)
 125 {
 126         struct ib_device *ibdev = qp->ibqp.device;
 127         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 128         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 129         size_t offset;
 130         size_t wq_end;
 131         struct ib_umem *umem = base->ubuffer.umem;
 132         u32 first_copy_length;
 133         int wqe_length;
 134         int ret;
 135
 136         if (wq->wqe_cnt == 0) {
 137                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 138                             qp->ibqp.qp_type);
 139                 return -EINVAL;
 140         }
 141
 142         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 143         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 144
 145         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 146                 return -EINVAL;
 147
 148         if (offset > umem->length ||
 149             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 150                 return -EINVAL;
 151
 152         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 153         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 154         if (ret)
 155                 return ret;
 156
 157         if (send) {
 158                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 159                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 160
 161                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 162         } else {
 163                 wqe_length = 1 << wq->wqe_shift;
 164         }
 165
 166         if (wqe_length <= first_copy_length)
 167                 return first_copy_length;
 168
 169         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 170                                 wqe_length - first_copy_length);
 171         if (ret)
 172                 return ret;
 173
 174         return wqe_length;
 175 }
 176
 177 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 178 {
 179         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 180         struct ib_event event;
 181
 182         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 183                 /* This event is only valid for trans_qps */
 184                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 185         }
 186
 187         if (ibqp->event_handler) {
 188                 event.device     = ibqp->device;
 189                 event.element.qp = ibqp;
 190                 switch (type) {
 191                 case MLX5_EVENT_TYPE_PATH_MIG:
 192                         event.event = IB_EVENT_PATH_MIG;
 193                         break;
 194                 case MLX5_EVENT_TYPE_COMM_EST:
 195                         event.event = IB_EVENT_COMM_EST;
 196                         break;
 197                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 198                         event.event = IB_EVENT_SQ_DRAINED;
 199                         break;
 200                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 201                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 202                         break;
 203                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 204                         event.event = IB_EVENT_QP_FATAL;
 205                         break;
 206                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 207                         event.event = IB_EVENT_PATH_MIG_ERR;
 208                         break;
 209                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 210                         event.event = IB_EVENT_QP_REQ_ERR;
 211                         break;
 212                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 213                         event.event = IB_EVENT_QP_ACCESS_ERR;
 214                         break;
 215                 default:
 216                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 217                         return;
 218                 }
 219
 220                 ibqp->event_handler(&event, ibqp->qp_context);
 221         }
 222 }
 223
 224 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 225                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 226 {
 227         int wqe_size;
 228         int wq_size;
 229
 230         /* Sanity check RQ size before proceeding */
 231         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 232                 return -EINVAL;
 233
 234         if (!has_rq) {
 235                 qp->rq.max_gs = 0;
 236                 qp->rq.wqe_cnt = 0;
 237                 qp->rq.wqe_shift = 0;
 238                 cap->max_recv_wr = 0;
 239                 cap->max_recv_sge = 0;
 240         } else {
 241                 if (ucmd) {
 242                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 243                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 244                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 245                         qp->rq.max_post = qp->rq.wqe_cnt;
 246                 } else {
 247                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 248                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 249                         wqe_size = roundup_pow_of_two(wqe_size);
 250                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 251                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 252                         qp->rq.wqe_cnt = wq_size / wqe_size;
 253                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 254                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 255                                             wqe_size,
 256                                             MLX5_CAP_GEN(dev->mdev,
 257                                                          max_wqe_sz_rq));
 258                                 return -EINVAL;
 259                         }
 260                         qp->rq.wqe_shift = ilog2(wqe_size);
 261                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 262                         qp->rq.max_post = qp->rq.wqe_cnt;
 263                 }
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int sq_overhead(struct ib_qp_init_attr *attr)
 270 {
 271         int size = 0;
 272
 273         switch (attr->qp_type) {
 274         case IB_QPT_XRC_INI:
 275                 size += sizeof(struct mlx5_wqe_xrc_seg);
 276                 /* fall through */
 277         case IB_QPT_RC:
 278                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 279                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 280                             sizeof(struct mlx5_wqe_raddr_seg),
 281                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 282                             sizeof(struct mlx5_mkey_seg));
 283                 break;
 284
 285         case IB_QPT_XRC_TGT:
 286                 return 0;
 287
 288         case IB_QPT_UC:
 289                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 290                         max(sizeof(struct mlx5_wqe_raddr_seg),
 291                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 292                             sizeof(struct mlx5_mkey_seg));
 293                 break;
 294
 295         case IB_QPT_UD:
 296                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 297                         size += sizeof(struct mlx5_wqe_eth_pad) +
 298                                 sizeof(struct mlx5_wqe_eth_seg);
 299                 /* fall through */
 300         case IB_QPT_SMI:
 301         case MLX5_IB_QPT_HW_GSI:
 302                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 303                         sizeof(struct mlx5_wqe_datagram_seg);
 304                 break;
 305
 306         case MLX5_IB_QPT_REG_UMR:
 307                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 308                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 309                         sizeof(struct mlx5_mkey_seg);
 310                 break;
 311
 312         default:
 313                 return -EINVAL;
 314         }
 315
 316         return size;
 317 }
 318
 319 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 320 {
 321         int inl_size = 0;
 322         int size;
 323
 324         size = sq_overhead(attr);
 325         if (size < 0)
 326                 return size;
 327
 328         if (attr->cap.max_inline_data) {
 329                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 330                         attr->cap.max_inline_data;
 331         }
 332
 333         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 334         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 335             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 336                         return MLX5_SIG_WQE_SIZE;
 337         else
 338                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 339 }
 340
 341 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 342                         struct mlx5_ib_qp *qp)
 343 {
 344         int wqe_size;
 345         int wq_size;
 346
 347         if (!attr->cap.max_send_wr)
 348                 return 0;
 349
 350         wqe_size = calc_send_wqe(attr);
 351         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 352         if (wqe_size < 0)
 353                 return wqe_size;
 354
 355         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 356                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 357                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 358                 return -EINVAL;
 359         }
 360
 361         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 362                               sizeof(struct mlx5_wqe_inline_seg);
 363         attr->cap.max_inline_data = qp->max_inline_data;
 364
 365         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 366                 qp->signature_en = true;
 367
 368         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 369         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 370         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 371                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 372                             qp->sq.wqe_cnt,
 373                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 374                 return -ENOMEM;
 375         }
 376         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 377         qp->sq.max_gs = attr->cap.max_send_sge;
 378         qp->sq.max_post = wq_size / wqe_size;
 379         attr->cap.max_send_wr = qp->sq.max_post;
 380
 381         return wq_size;
 382 }
 383
 384 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 385                             struct mlx5_ib_qp *qp,
 386                             struct mlx5_ib_create_qp *ucmd,
 387                             struct mlx5_ib_qp_base *base,
 388                             struct ib_qp_init_attr *attr)
 389 {
 390         int desc_sz = 1 << qp->sq.wqe_shift;
 391
 392         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 393                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 394                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 395                 return -EINVAL;
 396         }
 397
 398         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 399                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 400                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 401                 return -EINVAL;
 402         }
 403
 404         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 405
 406         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 407                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 408                              qp->sq.wqe_cnt,
 409                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 410                 return -EINVAL;
 411         }
 412
 413         if (attr->qp_type == IB_QPT_RAW_PACKET) {
 414                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 415                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 416         } else {
 417                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 418                                          (qp->sq.wqe_cnt << 6);
 419         }
 420
 421         return 0;
 422 }
 423
 424 static int qp_has_rq(struct ib_qp_init_attr *attr)
 425 {
 426         if (attr->qp_type == IB_QPT_XRC_INI ||
 427             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 428             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 429             !attr->cap.max_recv_wr)
 430                 return 0;
 431
 432         return 1;
 433 }
 434
 435 static int first_med_uuar(void)
 436 {
 437         return 1;
 438 }
 439
 440 static int next_uuar(int n)
 441 {
 442         n++;
 443
 444         while (((n % 4) & 2))
 445                 n++;
 446
 447         return n;
 448 }
 449
 450 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 451 {
 452         int n;
 453
 454         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 455                 uuari->num_low_latency_uuars - 1;
 456
 457         return n >= 0 ? n : 0;
 458 }
 459
 460 static int max_uuari(struct mlx5_uuar_info *uuari)
 461 {
 462         return uuari->num_uars * 4;
 463 }
 464
 465 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 466 {
 467         int med;
 468         int i;
 469         int t;
 470
 471         med = num_med_uuar(uuari);
 472         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 473                 t++;
 474                 if (t == med)
 475                         return next_uuar(i);
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 482 {
 483         int i;
 484
 485         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 486                 if (!test_bit(i, uuari->bitmap)) {
 487                         set_bit(i, uuari->bitmap);
 488                         uuari->count[i]++;
 489                         return i;
 490                 }
 491         }
 492
 493         return -ENOMEM;
 494 }
 495
 496 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 497 {
 498         int minidx = first_med_uuar();
 499         int i;
 500
 501         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 502                 if (uuari->count[i] < uuari->count[minidx])
 503                         minidx = i;
 504         }
 505
 506         uuari->count[minidx]++;
 507         return minidx;
 508 }
 509
 510 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 511                       enum mlx5_ib_latency_class lat)
 512 {
 513         int uuarn = -EINVAL;
 514
 515         mutex_lock(&uuari->lock);
 516         switch (lat) {
 517         case MLX5_IB_LATENCY_CLASS_LOW:
 518                 uuarn = 0;
 519                 uuari->count[uuarn]++;
 520                 break;
 521
 522         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 523                 if (uuari->ver < 2)
 524                         uuarn = -ENOMEM;
 525                 else
 526                         uuarn = alloc_med_class_uuar(uuari);
 527                 break;
 528
 529         case MLX5_IB_LATENCY_CLASS_HIGH:
 530                 if (uuari->ver < 2)
 531                         uuarn = -ENOMEM;
 532                 else
 533                         uuarn = alloc_high_class_uuar(uuari);
 534                 break;
 535
 536         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 537                 uuarn = 2;
 538                 break;
 539         }
 540         mutex_unlock(&uuari->lock);
 541
 542         return uuarn;
 543 }
 544
 545 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 546 {
 547         clear_bit(uuarn, uuari->bitmap);
 548         --uuari->count[uuarn];
 549 }
 550
 551 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 552 {
 553         clear_bit(uuarn, uuari->bitmap);
 554         --uuari->count[uuarn];
 555 }
 556
 557 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 558 {
 559         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 560         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 561
 562         mutex_lock(&uuari->lock);
 563         if (uuarn == 0) {
 564                 --uuari->count[uuarn];
 565                 goto out;
 566         }
 567
 568         if (uuarn < high_uuar) {
 569                 free_med_class_uuar(uuari, uuarn);
 570                 goto out;
 571         }
 572
 573         free_high_class_uuar(uuari, uuarn);
 574
 575 out:
 576         mutex_unlock(&uuari->lock);
 577 }
 578
 579 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 580 {
 581         switch (state) {
 582         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 583         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 584         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 585         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 586         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 587         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 588         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 589         default:                return -1;
 590         }
 591 }
 592
 593 static int to_mlx5_st(enum ib_qp_type type)
 594 {
 595         switch (type) {
 596         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 597         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 598         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 599         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 600         case IB_QPT_XRC_INI:
 601         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 602         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 603         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 604         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 605         case IB_QPT_RAW_PACKET:
 606         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 607         case IB_QPT_MAX:
 608         default:                return -EINVAL;
 609         }
 610 }
 611
 612 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 613 {
 614         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 615 }
 616
 617 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 618                             struct ib_pd *pd,
 619                             unsigned long addr, size_t size,
 620                             struct ib_umem **umem,
 621                             int *npages, int *page_shift, int *ncont,
 622                             u32 *offset)
 623 {
 624         int err;
 625
 626         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 627         if (IS_ERR(*umem)) {
 628                 mlx5_ib_dbg(dev, "umem_get failed\n");
 629                 return PTR_ERR(*umem);
 630         }
 631
 632         mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
 633
 634         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 635         if (err) {
 636                 mlx5_ib_warn(dev, "bad offset\n");
 637                 goto err_umem;
 638         }
 639
 640         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 641                     addr, size, *npages, *page_shift, *ncont, *offset);
 642
 643         return 0;
 644
 645 err_umem:
 646         ib_umem_release(*umem);
 647         *umem = NULL;
 648
 649         return err;
 650 }
 651
 652 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
 653 {
 654         struct mlx5_ib_ucontext *context;
 655
 656         context = to_mucontext(pd->uobject->context);
 657         mlx5_ib_db_unmap_user(context, &rwq->db);
 658         if (rwq->umem)
 659                 ib_umem_release(rwq->umem);
 660 }
 661
 662 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 663                           struct mlx5_ib_rwq *rwq,
 664                           struct mlx5_ib_create_wq *ucmd)
 665 {
 666         struct mlx5_ib_ucontext *context;
 667         int page_shift = 0;
 668         int npages;
 669         u32 offset = 0;
 670         int ncont = 0;
 671         int err;
 672
 673         if (!ucmd->buf_addr)
 674                 return -EINVAL;
 675
 676         context = to_mucontext(pd->uobject->context);
 677         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 678                                rwq->buf_size, 0, 0);
 679         if (IS_ERR(rwq->umem)) {
 680                 mlx5_ib_dbg(dev, "umem_get failed\n");
 681                 err = PTR_ERR(rwq->umem);
 682                 return err;
 683         }
 684
 685         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
 686                            &ncont, NULL);
 687         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 688                                      &rwq->rq_page_offset);
 689         if (err) {
 690                 mlx5_ib_warn(dev, "bad offset\n");
 691                 goto err_umem;
 692         }
 693
 694         rwq->rq_num_pas = ncont;
 695         rwq->page_shift = page_shift;
 696         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 697         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 698
 699         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 700                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 701                     npages, page_shift, ncont, offset);
 702
 703         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 704         if (err) {
 705                 mlx5_ib_dbg(dev, "map failed\n");
 706                 goto err_umem;
 707         }
 708
 709         rwq->create_type = MLX5_WQ_USER;
 710         return 0;
 711
 712 err_umem:
 713         ib_umem_release(rwq->umem);
 714         return err;
 715 }
 716
 717 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 718                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 719                           struct ib_qp_init_attr *attr,
 720                           struct mlx5_create_qp_mbox_in **in,
 721                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 722                           struct mlx5_ib_qp_base *base)
 723 {
 724         struct mlx5_ib_ucontext *context;
 725         struct mlx5_ib_create_qp ucmd;
 726         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 727         int page_shift = 0;
 728         int uar_index;
 729         int npages;
 730         u32 offset = 0;
 731         int uuarn;
 732         int ncont = 0;
 733         int err;
 734
 735         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 736         if (err) {
 737                 mlx5_ib_dbg(dev, "copy failed\n");
 738                 return err;
 739         }
 740
 741         context = to_mucontext(pd->uobject->context);
 742         /*
 743          * TBD: should come from the verbs when we have the API
 744          */
 745         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
 746                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 747                 uuarn = MLX5_CROSS_CHANNEL_UUAR;
 748         else {
 749                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 750                 if (uuarn < 0) {
 751                         mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 752                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
 753                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 754                         if (uuarn < 0) {
 755                                 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 756                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
 757                                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 758                                 if (uuarn < 0) {
 759                                         mlx5_ib_warn(dev, "uuar allocation failed\n");
 760                                         return uuarn;
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 767         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 768
 769         qp->rq.offset = 0;
 770         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 771         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 772
 773         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 774         if (err)
 775                 goto err_uuar;
 776
 777         if (ucmd.buf_addr && ubuffer->buf_size) {
 778                 ubuffer->buf_addr = ucmd.buf_addr;
 779                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 780                                        ubuffer->buf_size,
 781                                        &ubuffer->umem, &npages, &page_shift,
 782                                        &ncont, &offset);
 783                 if (err)
 784                         goto err_uuar;
 785         } else {
 786                 ubuffer->umem = NULL;
 787         }
 788
 789         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 790         *in = mlx5_vzalloc(*inlen);
 791         if (!*in) {
 792                 err = -ENOMEM;
 793                 goto err_umem;
 794         }
 795         if (ubuffer->umem)
 796                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
 797                                      (*in)->pas, 0);
 798         (*in)->ctx.log_pg_sz_remote_qpn =
 799                 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 800         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 801
 802         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 803         resp->uuar_index = uuarn;
 804         qp->uuarn = uuarn;
 805
 806         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 807         if (err) {
 808                 mlx5_ib_dbg(dev, "map failed\n");
 809                 goto err_free;
 810         }
 811
 812         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 813         if (err) {
 814                 mlx5_ib_dbg(dev, "copy failed\n");
 815                 goto err_unmap;
 816         }
 817         qp->create_type = MLX5_QP_USER;
 818
 819         return 0;
 820
 821 err_unmap:
 822         mlx5_ib_db_unmap_user(context, &qp->db);
 823
 824 err_free:
 825         kvfree(*in);
 826
 827 err_umem:
 828         if (ubuffer->umem)
 829                 ib_umem_release(ubuffer->umem);
 830
 831 err_uuar:
 832         free_uuar(&context->uuari, uuarn);
 833         return err;
 834 }
 835
 836 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
 837                             struct mlx5_ib_qp_base *base)
 838 {
 839         struct mlx5_ib_ucontext *context;
 840
 841         context = to_mucontext(pd->uobject->context);
 842         mlx5_ib_db_unmap_user(context, &qp->db);
 843         if (base->ubuffer.umem)
 844                 ib_umem_release(base->ubuffer.umem);
 845         free_uuar(&context->uuari, qp->uuarn);
 846 }
 847
 848 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 849                             struct ib_qp_init_attr *init_attr,
 850                             struct mlx5_ib_qp *qp,
 851                             struct mlx5_create_qp_mbox_in **in, int *inlen,
 852                             struct mlx5_ib_qp_base *base)
 853 {
 854         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 855         struct mlx5_uuar_info *uuari;
 856         int uar_index;
 857         int uuarn;
 858         int err;
 859
 860         uuari = &dev->mdev->priv.uuari;
 861         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 862                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 863                                         IB_QP_CREATE_IPOIB_UD_LSO |
 864                                         mlx5_ib_create_qp_sqpn_qp1()))
 865                 return -EINVAL;
 866
 867         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 868                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 869
 870         uuarn = alloc_uuar(uuari, lc);
 871         if (uuarn < 0) {
 872                 mlx5_ib_dbg(dev, "\n");
 873                 return -ENOMEM;
 874         }
 875
 876         qp->bf = &uuari->bfs[uuarn];
 877         uar_index = qp->bf->uar->index;
 878
 879         err = calc_sq_size(dev, init_attr, qp);
 880         if (err < 0) {
 881                 mlx5_ib_dbg(dev, "err %d\n", err);
 882                 goto err_uuar;
 883         }
 884
 885         qp->rq.offset = 0;
 886         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 887         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 888
 889         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 890         if (err) {
 891                 mlx5_ib_dbg(dev, "err %d\n", err);
 892                 goto err_uuar;
 893         }
 894
 895         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 896         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 897         *in = mlx5_vzalloc(*inlen);
 898         if (!*in) {
 899                 err = -ENOMEM;
 900                 goto err_buf;
 901         }
 902         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 903         (*in)->ctx.log_pg_sz_remote_qpn =
 904                 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 905         /* Set "fast registration enabled" for all kernel QPs */
 906         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 907         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 908
 909         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 910                 (*in)->ctx.deth_sqpn = cpu_to_be32(1);
 911                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 912         }
 913
 914         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 915
 916         err = mlx5_db_alloc(dev->mdev, &qp->db);
 917         if (err) {
 918                 mlx5_ib_dbg(dev, "err %d\n", err);
 919                 goto err_free;
 920         }
 921
 922         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 923         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 924         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 925         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 926         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 927
 928         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 929             !qp->sq.w_list || !qp->sq.wqe_head) {
 930                 err = -ENOMEM;
 931                 goto err_wrid;
 932         }
 933         qp->create_type = MLX5_QP_KERNEL;
 934
 935         return 0;
 936
 937 err_wrid:
 938         mlx5_db_free(dev->mdev, &qp->db);
 939         kfree(qp->sq.wqe_head);
 940         kfree(qp->sq.w_list);
 941         kfree(qp->sq.wrid);
 942         kfree(qp->sq.wr_data);
 943         kfree(qp->rq.wrid);
 944
 945 err_free:
 946         kvfree(*in);
 947
 948 err_buf:
 949         mlx5_buf_free(dev->mdev, &qp->buf);
 950
 951 err_uuar:
 952         free_uuar(&dev->mdev->priv.uuari, uuarn);
 953         return err;
 954 }
 955
 956 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 957 {
 958         mlx5_db_free(dev->mdev, &qp->db);
 959         kfree(qp->sq.wqe_head);
 960         kfree(qp->sq.w_list);
 961         kfree(qp->sq.wrid);
 962         kfree(qp->sq.wr_data);
 963         kfree(qp->rq.wrid);
 964         mlx5_buf_free(dev->mdev, &qp->buf);
 965         free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
 966 }
 967
 968 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 969 {
 970         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 971             (attr->qp_type == IB_QPT_XRC_INI))
 972                 return cpu_to_be32(MLX5_SRQ_RQ);
 973         else if (!qp->has_rq)
 974                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 975         else
 976                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 977 }
 978
 979 static int is_connected(enum ib_qp_type qp_type)
 980 {
 981         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 982                 return 1;
 983
 984         return 0;
 985 }
 986
 987 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
 988                                     struct mlx5_ib_sq *sq, u32 tdn)
 989 {
 990         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
 991         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
 992
 993         memset(in, 0, sizeof(in));
 994
 995         MLX5_SET(tisc, tisc, transport_domain, tdn);
 996
 997         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
 998 }
 999
1000 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1001                                       struct mlx5_ib_sq *sq)
1002 {
1003         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1004 }
1005
1006 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1007                                    struct mlx5_ib_sq *sq, void *qpin,
1008                                    struct ib_pd *pd)
1009 {
1010         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1011         __be64 *pas;
1012         void *in;
1013         void *sqc;
1014         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1015         void *wq;
1016         int inlen;
1017         int err;
1018         int page_shift = 0;
1019         int npages;
1020         int ncont = 0;
1021         u32 offset = 0;
1022
1023         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1024                                &sq->ubuffer.umem, &npages, &page_shift,
1025                                &ncont, &offset);
1026         if (err)
1027                 return err;
1028
1029         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1030         in = mlx5_vzalloc(inlen);
1031         if (!in) {
1032                 err = -ENOMEM;
1033                 goto err_umem;
1034         }
1035
1036         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1037         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1038         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1039         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1040         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1041         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1042         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1043
1044         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1045         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1046         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1047         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1048         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1049         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1050         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1051         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1052         MLX5_SET(wq, wq, page_offset, offset);
1053
1054         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1055         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1056
1057         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1058
1059         kvfree(in);
1060
1061         if (err)
1062                 goto err_umem;
1063
1064         return 0;
1065
1066 err_umem:
1067         ib_umem_release(sq->ubuffer.umem);
1068         sq->ubuffer.umem = NULL;
1069
1070         return err;
1071 }
1072
1073 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1074                                      struct mlx5_ib_sq *sq)
1075 {
1076         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1077         ib_umem_release(sq->ubuffer.umem);
1078 }
1079
1080 static int get_rq_pas_size(void *qpc)
1081 {
1082         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1083         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1084         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1085         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1086         u32 po_quanta     = 1 << (log_page_size - 6);
1087         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1088         u32 page_size     = 1 << log_page_size;
1089         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1090         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1091
1092         return rq_num_pas * sizeof(u64);
1093 }
1094
1095 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1096                                    struct mlx5_ib_rq *rq, void *qpin)
1097 {
1098         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1099         __be64 *pas;
1100         __be64 *qp_pas;
1101         void *in;
1102         void *rqc;
1103         void *wq;
1104         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1105         int inlen;
1106         int err;
1107         u32 rq_pas_size = get_rq_pas_size(qpc);
1108
1109         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1110         in = mlx5_vzalloc(inlen);
1111         if (!in)
1112                 return -ENOMEM;
1113
1114         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1115         MLX5_SET(rqc, rqc, vsd, 1);
1116         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1117         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1118         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1119         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1120         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1121
1122         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1123                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1124
1125         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1126         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1127         MLX5_SET(wq, wq, end_padding_mode,
1128                  MLX5_GET(qpc, qpc, end_padding_mode));
1129         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1130         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1131         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1132         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1133         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1134         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1135
1136         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1137         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1138         memcpy(pas, qp_pas, rq_pas_size);
1139
1140         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1141
1142         kvfree(in);
1143
1144         return err;
1145 }
1146
1147 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1148                                      struct mlx5_ib_rq *rq)
1149 {
1150         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1151 }
1152
1153 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1154                                     struct mlx5_ib_rq *rq, u32 tdn)
1155 {
1156         u32 *in;
1157         void *tirc;
1158         int inlen;
1159         int err;
1160
1161         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1162         in = mlx5_vzalloc(inlen);
1163         if (!in)
1164                 return -ENOMEM;
1165
1166         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1167         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1168         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1169         MLX5_SET(tirc, tirc, transport_domain, tdn);
1170
1171         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1172
1173         kvfree(in);
1174
1175         return err;
1176 }
1177
1178 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1179                                       struct mlx5_ib_rq *rq)
1180 {
1181         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1182 }
1183
1184 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1185                                 struct mlx5_create_qp_mbox_in *in,
1186                                 struct ib_pd *pd)
1187 {
1188         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1189         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1190         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1191         struct ib_uobject *uobj = pd->uobject;
1192         struct ib_ucontext *ucontext = uobj->context;
1193         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1194         int err;
1195         u32 tdn = mucontext->tdn;
1196
1197         if (qp->sq.wqe_cnt) {
1198                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1199                 if (err)
1200                         return err;
1201
1202                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1203                 if (err)
1204                         goto err_destroy_tis;
1205
1206                 sq->base.container_mibqp = qp;
1207         }
1208
1209         if (qp->rq.wqe_cnt) {
1210                 rq->base.container_mibqp = qp;
1211
1212                 err = create_raw_packet_qp_rq(dev, rq, in);
1213                 if (err)
1214                         goto err_destroy_sq;
1215
1216
1217                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1218                 if (err)
1219                         goto err_destroy_rq;
1220         }
1221
1222         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1223                                                      rq->base.mqp.qpn;
1224
1225         return 0;
1226
1227 err_destroy_rq:
1228         destroy_raw_packet_qp_rq(dev, rq);
1229 err_destroy_sq:
1230         if (!qp->sq.wqe_cnt)
1231                 return err;
1232         destroy_raw_packet_qp_sq(dev, sq);
1233 err_destroy_tis:
1234         destroy_raw_packet_qp_tis(dev, sq);
1235
1236         return err;
1237 }
1238
1239 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1240                                   struct mlx5_ib_qp *qp)
1241 {
1242         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1243         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1244         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1245
1246         if (qp->rq.wqe_cnt) {
1247                 destroy_raw_packet_qp_tir(dev, rq);
1248                 destroy_raw_packet_qp_rq(dev, rq);
1249         }
1250
1251         if (qp->sq.wqe_cnt) {
1252                 destroy_raw_packet_qp_sq(dev, sq);
1253                 destroy_raw_packet_qp_tis(dev, sq);
1254         }
1255 }
1256
1257 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1258                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1259 {
1260         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1261         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1262
1263         sq->sq = &qp->sq;
1264         rq->rq = &qp->rq;
1265         sq->doorbell = &qp->db;
1266         rq->doorbell = &qp->db;
1267 }
1268
1269 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1270 {
1271         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1272 }
1273
1274 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1275                                  struct ib_pd *pd,
1276                                  struct ib_qp_init_attr *init_attr,
1277                                  struct ib_udata *udata)
1278 {
1279         struct ib_uobject *uobj = pd->uobject;
1280         struct ib_ucontext *ucontext = uobj->context;
1281         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1282         struct mlx5_ib_create_qp_resp resp = {};
1283         int inlen;
1284         int err;
1285         u32 *in;
1286         void *tirc;
1287         void *hfso;
1288         u32 selected_fields = 0;
1289         size_t min_resp_len;
1290         u32 tdn = mucontext->tdn;
1291         struct mlx5_ib_create_qp_rss ucmd = {};
1292         size_t required_cmd_sz;
1293
1294         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1295                 return -EOPNOTSUPP;
1296
1297         if (init_attr->create_flags || init_attr->send_cq)
1298                 return -EINVAL;
1299
1300         min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1301         if (udata->outlen < min_resp_len)
1302                 return -EINVAL;
1303
1304         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1305         if (udata->inlen < required_cmd_sz) {
1306                 mlx5_ib_dbg(dev, "invalid inlen\n");
1307                 return -EINVAL;
1308         }
1309
1310         if (udata->inlen > sizeof(ucmd) &&
1311             !ib_is_udata_cleared(udata, sizeof(ucmd),
1312                                  udata->inlen - sizeof(ucmd))) {
1313                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1314                 return -EOPNOTSUPP;
1315         }
1316
1317         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1318                 mlx5_ib_dbg(dev, "copy failed\n");
1319                 return -EFAULT;
1320         }
1321
1322         if (ucmd.comp_mask) {
1323                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1324                 return -EOPNOTSUPP;
1325         }
1326
1327         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1328                 mlx5_ib_dbg(dev, "invalid reserved\n");
1329                 return -EOPNOTSUPP;
1330         }
1331
1332         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1333         if (err) {
1334                 mlx5_ib_dbg(dev, "copy failed\n");
1335                 return -EINVAL;
1336         }
1337
1338         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1339         in = mlx5_vzalloc(inlen);
1340         if (!in)
1341                 return -ENOMEM;
1342
1343         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1344         MLX5_SET(tirc, tirc, disp_type,
1345                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1346         MLX5_SET(tirc, tirc, indirect_table,
1347                  init_attr->rwq_ind_tbl->ind_tbl_num);
1348         MLX5_SET(tirc, tirc, transport_domain, tdn);
1349
1350         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1351         switch (ucmd.rx_hash_function) {
1352         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1353         {
1354                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1355                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1356
1357                 if (len != ucmd.rx_key_len) {
1358                         err = -EINVAL;
1359                         goto err;
1360                 }
1361
1362                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1363                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1364                 memcpy(rss_key, ucmd.rx_hash_key, len);
1365                 break;
1366         }
1367         default:
1368                 err = -EOPNOTSUPP;
1369                 goto err;
1370         }
1371
1372         if (!ucmd.rx_hash_fields_mask) {
1373                 /* special case when this TIR serves as steering entry without hashing */
1374                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1375                         goto create_tir;
1376                 err = -EINVAL;
1377                 goto err;
1378         }
1379
1380         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1381              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1382              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1383              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1384                 err = -EINVAL;
1385                 goto err;
1386         }
1387
1388         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1389         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1390             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1391                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1392                          MLX5_L3_PROT_TYPE_IPV4);
1393         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1394                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1395                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1396                          MLX5_L3_PROT_TYPE_IPV6);
1397
1398         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1399              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1400              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1401              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1402                 err = -EINVAL;
1403                 goto err;
1404         }
1405
1406         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1407         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1408             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1409                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1410                          MLX5_L4_PROT_TYPE_TCP);
1411         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1412                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1413                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1414                          MLX5_L4_PROT_TYPE_UDP);
1415
1416         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1417             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1418                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1419
1420         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1421             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1422                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1423
1424         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1425             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1426                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1427
1428         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1429             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1430                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1431
1432         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1433
1434 create_tir:
1435         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1436
1437         if (err)
1438                 goto err;
1439
1440         kvfree(in);
1441         /* qpn is reserved for that QP */
1442         qp->trans_qp.base.mqp.qpn = 0;
1443         return 0;
1444
1445 err:
1446         kvfree(in);
1447         return err;
1448 }
1449
1450 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1451                             struct ib_qp_init_attr *init_attr,
1452                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1453 {
1454         struct mlx5_ib_resources *devr = &dev->devr;
1455         struct mlx5_core_dev *mdev = dev->mdev;
1456         struct mlx5_ib_qp_base *base;
1457         struct mlx5_ib_create_qp_resp resp;
1458         struct mlx5_create_qp_mbox_in *in;
1459         struct mlx5_ib_create_qp ucmd;
1460         int inlen = sizeof(*in);
1461         int err;
1462         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1463         void *qpc;
1464
1465         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1466                &qp->raw_packet_qp.rq.base :
1467                &qp->trans_qp.base;
1468
1469         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1470                 mlx5_ib_odp_create_qp(qp);
1471
1472         mutex_init(&qp->mutex);
1473         spin_lock_init(&qp->sq.lock);
1474         spin_lock_init(&qp->rq.lock);
1475
1476         if (init_attr->rwq_ind_tbl) {
1477                 if (!udata)
1478                         return -ENOSYS;
1479
1480                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1481                 return err;
1482         }
1483
1484         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1485                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1486                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1487                         return -EINVAL;
1488                 } else {
1489                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1490                 }
1491         }
1492
1493         if (init_attr->create_flags &
1494                         (IB_QP_CREATE_CROSS_CHANNEL |
1495                          IB_QP_CREATE_MANAGED_SEND |
1496                          IB_QP_CREATE_MANAGED_RECV)) {
1497                 if (!MLX5_CAP_GEN(mdev, cd)) {
1498                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1499                         return -EINVAL;
1500                 }
1501                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1502                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1503                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1504                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1505                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1506                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1507         }
1508
1509         if (init_attr->qp_type == IB_QPT_UD &&
1510             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1511                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1512                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1513                         return -EOPNOTSUPP;
1514                 }
1515
1516         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1517                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1518                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1519                         return -EOPNOTSUPP;
1520                 }
1521                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1522                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1523                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1524                         return -EOPNOTSUPP;
1525                 }
1526                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1527         }
1528
1529         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1530                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1531
1532         if (pd && pd->uobject) {
1533                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1534                         mlx5_ib_dbg(dev, "copy failed\n");
1535                         return -EFAULT;
1536                 }
1537
1538                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1539                                         &ucmd, udata->inlen, &uidx);
1540                 if (err)
1541                         return err;
1542
1543                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1544                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1545         } else {
1546                 qp->wq_sig = !!wq_signature;
1547         }
1548
1549         qp->has_rq = qp_has_rq(init_attr);
1550         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1551                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1552         if (err) {
1553                 mlx5_ib_dbg(dev, "err %d\n", err);
1554                 return err;
1555         }
1556
1557         if (pd) {
1558                 if (pd->uobject) {
1559                         __u32 max_wqes =
1560                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1561                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1562                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1563                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1564                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1565                                 return -EINVAL;
1566                         }
1567                         if (ucmd.sq_wqe_count > max_wqes) {
1568                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1569                                             ucmd.sq_wqe_count, max_wqes);
1570                                 return -EINVAL;
1571                         }
1572                         if (init_attr->create_flags &
1573                             mlx5_ib_create_qp_sqpn_qp1()) {
1574                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1575                                 return -EINVAL;
1576                         }
1577                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1578                                              &resp, &inlen, base);
1579                         if (err)
1580                                 mlx5_ib_dbg(dev, "err %d\n", err);
1581                 } else {
1582                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1583                                                base);
1584                         if (err)
1585                                 mlx5_ib_dbg(dev, "err %d\n", err);
1586                 }
1587
1588                 if (err)
1589                         return err;
1590         } else {
1591                 in = mlx5_vzalloc(sizeof(*in));
1592                 if (!in)
1593                         return -ENOMEM;
1594
1595                 qp->create_type = MLX5_QP_EMPTY;
1596         }
1597
1598         if (is_sqp(init_attr->qp_type))
1599                 qp->port = init_attr->port_num;
1600
1601         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1602                                     MLX5_QP_PM_MIGRATED << 11);
1603
1604         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1605                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1606         else
1607                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1608
1609         if (qp->wq_sig)
1610                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1611
1612         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1613                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1614
1615         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1616                 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1617         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1618                 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1619         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1620                 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1621
1622         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1623                 int rcqe_sz;
1624                 int scqe_sz;
1625
1626                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1627                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1628
1629                 if (rcqe_sz == 128)
1630                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1631                 else
1632                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1633
1634                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1635                         if (scqe_sz == 128)
1636                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1637                         else
1638                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1639                 }
1640         }
1641
1642         if (qp->rq.wqe_cnt) {
1643                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1644                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1645         }
1646
1647         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1648
1649         if (qp->sq.wqe_cnt)
1650                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1651         else
1652                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1653
1654         /* Set default resources */
1655         switch (init_attr->qp_type) {
1656         case IB_QPT_XRC_TGT:
1657                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1658                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1659                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1660                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1661                 break;
1662         case IB_QPT_XRC_INI:
1663                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1664                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1665                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1666                 break;
1667         default:
1668                 if (init_attr->srq) {
1669                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1670                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1671                 } else {
1672                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1673                         in->ctx.rq_type_srqn |=
1674                                 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
1675                 }
1676         }
1677
1678         if (init_attr->send_cq)
1679                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1680
1681         if (init_attr->recv_cq)
1682                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1683
1684         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1685
1686         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1687                 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1688                 /* 0xffffff means we ask to work with cqe version 0 */
1689                 MLX5_SET(qpc, qpc, user_index, uidx);
1690         }
1691         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1692         if (init_attr->qp_type == IB_QPT_UD &&
1693             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1694                 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1695                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1696                 qp->flags |= MLX5_IB_QP_LSO;
1697         }
1698
1699         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1700                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1701                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1702                 err = create_raw_packet_qp(dev, qp, in, pd);
1703         } else {
1704                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1705         }
1706
1707         if (err) {
1708                 mlx5_ib_dbg(dev, "create qp failed\n");
1709                 goto err_create;
1710         }
1711
1712         kvfree(in);
1713
1714         base->container_mibqp = qp;
1715         base->mqp.event = mlx5_ib_qp_event;
1716
1717         return 0;
1718
1719 err_create:
1720         if (qp->create_type == MLX5_QP_USER)
1721                 destroy_qp_user(pd, qp, base);
1722         else if (qp->create_type == MLX5_QP_KERNEL)
1723                 destroy_qp_kernel(dev, qp);
1724
1725         kvfree(in);
1726         return err;
1727 }
1728
1729 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1730         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1731 {
1732         if (send_cq) {
1733                 if (recv_cq) {
1734                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1735                                 spin_lock_irq(&send_cq->lock);
1736                                 spin_lock_nested(&recv_cq->lock,
1737                                                  SINGLE_DEPTH_NESTING);
1738                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1739                                 spin_lock_irq(&send_cq->lock);
1740                                 __acquire(&recv_cq->lock);
1741                         } else {
1742                                 spin_lock_irq(&recv_cq->lock);
1743                                 spin_lock_nested(&send_cq->lock,
1744                                                  SINGLE_DEPTH_NESTING);
1745                         }
1746                 } else {
1747                         spin_lock_irq(&send_cq->lock);
1748                         __acquire(&recv_cq->lock);
1749                 }
1750         } else if (recv_cq) {
1751                 spin_lock_irq(&recv_cq->lock);
1752                 __acquire(&send_cq->lock);
1753         } else {
1754                 __acquire(&send_cq->lock);
1755                 __acquire(&recv_cq->lock);
1756         }
1757 }
1758
1759 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1760         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1761 {
1762         if (send_cq) {
1763                 if (recv_cq) {
1764                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1765                                 spin_unlock(&recv_cq->lock);
1766                                 spin_unlock_irq(&send_cq->lock);
1767                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1768                                 __release(&recv_cq->lock);
1769                                 spin_unlock_irq(&send_cq->lock);
1770                         } else {
1771                                 spin_unlock(&send_cq->lock);
1772                                 spin_unlock_irq(&recv_cq->lock);
1773                         }
1774                 } else {
1775                         __release(&recv_cq->lock);
1776                         spin_unlock_irq(&send_cq->lock);
1777                 }
1778         } else if (recv_cq) {
1779                 __release(&send_cq->lock);
1780                 spin_unlock_irq(&recv_cq->lock);
1781         } else {
1782                 __release(&recv_cq->lock);
1783                 __release(&send_cq->lock);
1784         }
1785 }
1786
1787 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1788 {
1789         return to_mpd(qp->ibqp.pd);
1790 }
1791
1792 static void get_cqs(struct mlx5_ib_qp *qp,
1793                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1794 {
1795         switch (qp->ibqp.qp_type) {
1796         case IB_QPT_XRC_TGT:
1797                 *send_cq = NULL;
1798                 *recv_cq = NULL;
1799                 break;
1800         case MLX5_IB_QPT_REG_UMR:
1801         case IB_QPT_XRC_INI:
1802                 *send_cq = to_mcq(qp->ibqp.send_cq);
1803                 *recv_cq = NULL;
1804                 break;
1805
1806         case IB_QPT_SMI:
1807         case MLX5_IB_QPT_HW_GSI:
1808         case IB_QPT_RC:
1809         case IB_QPT_UC:
1810         case IB_QPT_UD:
1811         case IB_QPT_RAW_IPV6:
1812         case IB_QPT_RAW_ETHERTYPE:
1813         case IB_QPT_RAW_PACKET:
1814                 *send_cq = to_mcq(qp->ibqp.send_cq);
1815                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1816                 break;
1817
1818         case IB_QPT_MAX:
1819         default:
1820                 *send_cq = NULL;
1821                 *recv_cq = NULL;
1822                 break;
1823         }
1824 }
1825
1826 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1827                                 u16 operation);
1828
1829 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1830 {
1831         struct mlx5_ib_cq *send_cq, *recv_cq;
1832         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1833         struct mlx5_modify_qp_mbox_in *in;
1834         int err;
1835
1836         if (qp->ibqp.rwq_ind_tbl) {
1837                 destroy_rss_raw_qp_tir(dev, qp);
1838                 return;
1839         }
1840
1841         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1842                &qp->raw_packet_qp.rq.base :
1843                &qp->trans_qp.base;
1844
1845         in = kzalloc(sizeof(*in), GFP_KERNEL);
1846         if (!in)
1847                 return;
1848
1849         if (qp->state != IB_QPS_RESET) {
1850                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1851                         mlx5_ib_qp_disable_pagefaults(qp);
1852                         err = mlx5_core_qp_modify(dev->mdev,
1853                                                   MLX5_CMD_OP_2RST_QP, in, 0,
1854                                                   &base->mqp);
1855                 } else {
1856                         err = modify_raw_packet_qp(dev, qp,
1857                                                    MLX5_CMD_OP_2RST_QP);
1858                 }
1859                 if (err)
1860                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1861                                      base->mqp.qpn);
1862         }
1863
1864         get_cqs(qp, &send_cq, &recv_cq);
1865
1866         if (qp->create_type == MLX5_QP_KERNEL) {
1867                 mlx5_ib_lock_cqs(send_cq, recv_cq);
1868                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1869                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1870                 if (send_cq != recv_cq)
1871                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1872                                            NULL);
1873                 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1874         }
1875
1876         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1877                 destroy_raw_packet_qp(dev, qp);
1878         } else {
1879                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1880                 if (err)
1881                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1882                                      base->mqp.qpn);
1883         }
1884
1885         kfree(in);
1886
1887         if (qp->create_type == MLX5_QP_KERNEL)
1888                 destroy_qp_kernel(dev, qp);
1889         else if (qp->create_type == MLX5_QP_USER)
1890                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1891 }
1892
1893 static const char *ib_qp_type_str(enum ib_qp_type type)
1894 {
1895         switch (type) {
1896         case IB_QPT_SMI:
1897                 return "IB_QPT_SMI";
1898         case IB_QPT_GSI:
1899                 return "IB_QPT_GSI";
1900         case IB_QPT_RC:
1901                 return "IB_QPT_RC";
1902         case IB_QPT_UC:
1903                 return "IB_QPT_UC";
1904         case IB_QPT_UD:
1905                 return "IB_QPT_UD";
1906         case IB_QPT_RAW_IPV6:
1907                 return "IB_QPT_RAW_IPV6";
1908         case IB_QPT_RAW_ETHERTYPE:
1909                 return "IB_QPT_RAW_ETHERTYPE";
1910         case IB_QPT_XRC_INI:
1911                 return "IB_QPT_XRC_INI";
1912         case IB_QPT_XRC_TGT:
1913                 return "IB_QPT_XRC_TGT";
1914         case IB_QPT_RAW_PACKET:
1915                 return "IB_QPT_RAW_PACKET";
1916         case MLX5_IB_QPT_REG_UMR:
1917                 return "MLX5_IB_QPT_REG_UMR";
1918         case IB_QPT_MAX:
1919         default:
1920                 return "Invalid QP type";
1921         }
1922 }
1923
1924 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1925                                 struct ib_qp_init_attr *init_attr,
1926                                 struct ib_udata *udata)
1927 {
1928         struct mlx5_ib_dev *dev;
1929         struct mlx5_ib_qp *qp;
1930         u16 xrcdn = 0;
1931         int err;
1932
1933         if (pd) {
1934                 dev = to_mdev(pd->device);
1935
1936                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1937                         if (!pd->uobject) {
1938                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1939                                 return ERR_PTR(-EINVAL);
1940                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1941                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1942                                 return ERR_PTR(-EINVAL);
1943                         }
1944                 }
1945         } else {
1946                 /* being cautious here */
1947                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1948                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1949                         pr_warn("%s: no PD for transport %s\n", __func__,
1950                                 ib_qp_type_str(init_attr->qp_type));
1951                         return ERR_PTR(-EINVAL);
1952                 }
1953                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1954         }
1955
1956         switch (init_attr->qp_type) {
1957         case IB_QPT_XRC_TGT:
1958         case IB_QPT_XRC_INI:
1959                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
1960                         mlx5_ib_dbg(dev, "XRC not supported\n");
1961                         return ERR_PTR(-ENOSYS);
1962                 }
1963                 init_attr->recv_cq = NULL;
1964                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1965                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1966                         init_attr->send_cq = NULL;
1967                 }
1968
1969                 /* fall through */
1970         case IB_QPT_RAW_PACKET:
1971         case IB_QPT_RC:
1972         case IB_QPT_UC:
1973         case IB_QPT_UD:
1974         case IB_QPT_SMI:
1975         case MLX5_IB_QPT_HW_GSI:
1976         case MLX5_IB_QPT_REG_UMR:
1977                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1978                 if (!qp)
1979                         return ERR_PTR(-ENOMEM);
1980
1981                 err = create_qp_common(dev, pd, init_attr, udata, qp);
1982                 if (err) {
1983                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
1984                         kfree(qp);
1985                         return ERR_PTR(err);
1986                 }
1987
1988                 if (is_qp0(init_attr->qp_type))
1989                         qp->ibqp.qp_num = 0;
1990                 else if (is_qp1(init_attr->qp_type))
1991                         qp->ibqp.qp_num = 1;
1992                 else
1993                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
1994
1995                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1996                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
1997                             to_mcq(init_attr->recv_cq)->mcq.cqn,
1998                             to_mcq(init_attr->send_cq)->mcq.cqn);
1999
2000                 qp->trans_qp.xrcdn = xrcdn;
2001
2002                 break;
2003
2004         case IB_QPT_GSI:
2005                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2006
2007         case IB_QPT_RAW_IPV6:
2008         case IB_QPT_RAW_ETHERTYPE:
2009         case IB_QPT_MAX:
2010         default:
2011                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2012                             init_attr->qp_type);
2013                 /* Don't support raw QPs */
2014                 return ERR_PTR(-EINVAL);
2015         }
2016
2017         return &qp->ibqp;
2018 }
2019
2020 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2021 {
2022         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2023         struct mlx5_ib_qp *mqp = to_mqp(qp);
2024
2025         if (unlikely(qp->qp_type == IB_QPT_GSI))
2026                 return mlx5_ib_gsi_destroy_qp(qp);
2027
2028         destroy_qp_common(dev, mqp);
2029
2030         kfree(mqp);
2031
2032         return 0;
2033 }
2034
2035 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2036                                    int attr_mask)
2037 {
2038         u32 hw_access_flags = 0;
2039         u8 dest_rd_atomic;
2040         u32 access_flags;
2041
2042         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2043                 dest_rd_atomic = attr->max_dest_rd_atomic;
2044         else
2045                 dest_rd_atomic = qp->trans_qp.resp_depth;
2046
2047         if (attr_mask & IB_QP_ACCESS_FLAGS)
2048                 access_flags = attr->qp_access_flags;
2049         else
2050                 access_flags = qp->trans_qp.atomic_rd_en;
2051
2052         if (!dest_rd_atomic)
2053                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2054
2055         if (access_flags & IB_ACCESS_REMOTE_READ)
2056                 hw_access_flags |= MLX5_QP_BIT_RRE;
2057         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2058                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2059         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2060                 hw_access_flags |= MLX5_QP_BIT_RWE;
2061
2062         return cpu_to_be32(hw_access_flags);
2063 }
2064
2065 enum {
2066         MLX5_PATH_FLAG_FL       = 1 << 0,
2067         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2068         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2069 };
2070
2071 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2072 {
2073         if (rate == IB_RATE_PORT_CURRENT) {
2074                 return 0;
2075         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2076                 return -EINVAL;
2077         } else {
2078                 while (rate != IB_RATE_2_5_GBPS &&
2079                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2080                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2081                         --rate;
2082         }
2083
2084         return rate + MLX5_STAT_RATE_OFFSET;
2085 }
2086
2087 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2088                                       struct mlx5_ib_sq *sq, u8 sl)
2089 {
2090         void *in;
2091         void *tisc;
2092         int inlen;
2093         int err;
2094
2095         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2096         in = mlx5_vzalloc(inlen);
2097         if (!in)
2098                 return -ENOMEM;
2099
2100         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2101
2102         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2103         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2104
2105         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2106
2107         kvfree(in);
2108
2109         return err;
2110 }
2111
2112 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2113                          const struct ib_ah_attr *ah,
2114                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2115                          u32 path_flags, const struct ib_qp_attr *attr,
2116                          bool alt)
2117 {
2118         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2119         int err;
2120
2121         if (attr_mask & IB_QP_PKEY_INDEX)
2122                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2123                                                      attr->pkey_index);
2124
2125         if (ah->ah_flags & IB_AH_GRH) {
2126                 if (ah->grh.sgid_index >=
2127                     dev->mdev->port_caps[port - 1].gid_table_len) {
2128                         pr_err("sgid_index (%u) too large. max is %d\n",
2129                                ah->grh.sgid_index,
2130                                dev->mdev->port_caps[port - 1].gid_table_len);
2131                         return -EINVAL;
2132                 }
2133         }
2134
2135         if (ll == IB_LINK_LAYER_ETHERNET) {
2136                 if (!(ah->ah_flags & IB_AH_GRH))
2137                         return -EINVAL;
2138                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2139                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2140                                                           ah->grh.sgid_index);
2141                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2142         } else {
2143                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2144                 path->fl_free_ar |=
2145                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2146                 path->rlid = cpu_to_be16(ah->dlid);
2147                 path->grh_mlid = ah->src_path_bits & 0x7f;
2148                 if (ah->ah_flags & IB_AH_GRH)
2149                         path->grh_mlid  |= 1 << 7;
2150                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2151         }
2152
2153         if (ah->ah_flags & IB_AH_GRH) {
2154                 path->mgid_index = ah->grh.sgid_index;
2155                 path->hop_limit  = ah->grh.hop_limit;
2156                 path->tclass_flowlabel =
2157                         cpu_to_be32((ah->grh.traffic_class << 20) |
2158                                     (ah->grh.flow_label));
2159                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2160         }
2161
2162         err = ib_rate_to_mlx5(dev, ah->static_rate);
2163         if (err < 0)
2164                 return err;
2165         path->static_rate = err;
2166         path->port = port;
2167
2168         if (attr_mask & IB_QP_TIMEOUT)
2169                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2170
2171         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2172                 return modify_raw_packet_eth_prio(dev->mdev,
2173                                                   &qp->raw_packet_qp.sq,
2174                                                   ah->sl & 0xf);
2175
2176         return 0;
2177 }
2178
2179 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2180         [MLX5_QP_STATE_INIT] = {
2181                 [MLX5_QP_STATE_INIT] = {
2182                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2183                                           MLX5_QP_OPTPAR_RAE            |
2184                                           MLX5_QP_OPTPAR_RWE            |
2185                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2186                                           MLX5_QP_OPTPAR_PRI_PORT,
2187                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2188                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2189                                           MLX5_QP_OPTPAR_PRI_PORT,
2190                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2191                                           MLX5_QP_OPTPAR_Q_KEY          |
2192                                           MLX5_QP_OPTPAR_PRI_PORT,
2193                 },
2194                 [MLX5_QP_STATE_RTR] = {
2195                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2196                                           MLX5_QP_OPTPAR_RRE            |
2197                                           MLX5_QP_OPTPAR_RAE            |
2198                                           MLX5_QP_OPTPAR_RWE            |
2199                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2200                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2201                                           MLX5_QP_OPTPAR_RWE            |
2202                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2203                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2204                                           MLX5_QP_OPTPAR_Q_KEY,
2205                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2206                                            MLX5_QP_OPTPAR_Q_KEY,
2207                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2208                                           MLX5_QP_OPTPAR_RRE            |
2209                                           MLX5_QP_OPTPAR_RAE            |
2210                                           MLX5_QP_OPTPAR_RWE            |
2211                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2212                 },
2213         },
2214         [MLX5_QP_STATE_RTR] = {
2215                 [MLX5_QP_STATE_RTS] = {
2216                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2217                                           MLX5_QP_OPTPAR_RRE            |
2218                                           MLX5_QP_OPTPAR_RAE            |
2219                                           MLX5_QP_OPTPAR_RWE            |
2220                                           MLX5_QP_OPTPAR_PM_STATE       |
2221                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2222                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2223                                           MLX5_QP_OPTPAR_RWE            |
2224                                           MLX5_QP_OPTPAR_PM_STATE,
2225                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2226                 },
2227         },
2228         [MLX5_QP_STATE_RTS] = {
2229                 [MLX5_QP_STATE_RTS] = {
2230                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2231                                           MLX5_QP_OPTPAR_RAE            |
2232                                           MLX5_QP_OPTPAR_RWE            |
2233                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2234                                           MLX5_QP_OPTPAR_PM_STATE       |
2235                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2236                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2237                                           MLX5_QP_OPTPAR_PM_STATE       |
2238                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2239                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2240                                           MLX5_QP_OPTPAR_SRQN           |
2241                                           MLX5_QP_OPTPAR_CQN_RCV,
2242                 },
2243         },
2244         [MLX5_QP_STATE_SQER] = {
2245                 [MLX5_QP_STATE_RTS] = {
2246                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2247                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2248                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2249                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2250                                            MLX5_QP_OPTPAR_RWE           |
2251                                            MLX5_QP_OPTPAR_RAE           |
2252                                            MLX5_QP_OPTPAR_RRE,
2253                 },
2254         },
2255 };
2256
2257 static int ib_nr_to_mlx5_nr(int ib_mask)
2258 {
2259         switch (ib_mask) {
2260         case IB_QP_STATE:
2261                 return 0;
2262         case IB_QP_CUR_STATE:
2263                 return 0;
2264         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2265                 return 0;
2266         case IB_QP_ACCESS_FLAGS:
2267                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2268                         MLX5_QP_OPTPAR_RAE;
2269         case IB_QP_PKEY_INDEX:
2270                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2271         case IB_QP_PORT:
2272                 return MLX5_QP_OPTPAR_PRI_PORT;
2273         case IB_QP_QKEY:
2274                 return MLX5_QP_OPTPAR_Q_KEY;
2275         case IB_QP_AV:
2276                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2277                         MLX5_QP_OPTPAR_PRI_PORT;
2278         case IB_QP_PATH_MTU:
2279                 return 0;
2280         case IB_QP_TIMEOUT:
2281                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2282         case IB_QP_RETRY_CNT:
2283                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2284         case IB_QP_RNR_RETRY:
2285                 return MLX5_QP_OPTPAR_RNR_RETRY;
2286         case IB_QP_RQ_PSN:
2287                 return 0;
2288         case IB_QP_MAX_QP_RD_ATOMIC:
2289                 return MLX5_QP_OPTPAR_SRA_MAX;
2290         case IB_QP_ALT_PATH:
2291                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2292         case IB_QP_MIN_RNR_TIMER:
2293                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2294         case IB_QP_SQ_PSN:
2295                 return 0;
2296         case IB_QP_MAX_DEST_RD_ATOMIC:
2297                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2298                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2299         case IB_QP_PATH_MIG_STATE:
2300                 return MLX5_QP_OPTPAR_PM_STATE;
2301         case IB_QP_CAP:
2302                 return 0;
2303         case IB_QP_DEST_QPN:
2304                 return 0;
2305         }
2306         return 0;
2307 }
2308
2309 static int ib_mask_to_mlx5_opt(int ib_mask)
2310 {
2311         int result = 0;
2312         int i;
2313
2314         for (i = 0; i < 8 * sizeof(int); i++) {
2315                 if ((1 << i) & ib_mask)
2316                         result |= ib_nr_to_mlx5_nr(1 << i);
2317         }
2318
2319         return result;
2320 }
2321
2322 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2323                                    struct mlx5_ib_rq *rq, int new_state)
2324 {
2325         void *in;
2326         void *rqc;
2327         int inlen;
2328         int err;
2329
2330         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2331         in = mlx5_vzalloc(inlen);
2332         if (!in)
2333                 return -ENOMEM;
2334
2335         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2336
2337         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2338         MLX5_SET(rqc, rqc, state, new_state);
2339
2340         err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2341         if (err)
2342                 goto out;
2343
2344         rq->state = new_state;
2345
2346 out:
2347         kvfree(in);
2348         return err;
2349 }
2350
2351 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2352                                    struct mlx5_ib_sq *sq, int new_state)
2353 {
2354         void *in;
2355         void *sqc;
2356         int inlen;
2357         int err;
2358
2359         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2360         in = mlx5_vzalloc(inlen);
2361         if (!in)
2362                 return -ENOMEM;
2363
2364         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2365
2366         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2367         MLX5_SET(sqc, sqc, state, new_state);
2368
2369         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2370         if (err)
2371                 goto out;
2372
2373         sq->state = new_state;
2374
2375 out:
2376         kvfree(in);
2377         return err;
2378 }
2379
2380 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2381                                 u16 operation)
2382 {
2383         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2384         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2385         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2386         int rq_state;
2387         int sq_state;
2388         int err;
2389
2390         switch (operation) {
2391         case MLX5_CMD_OP_RST2INIT_QP:
2392                 rq_state = MLX5_RQC_STATE_RDY;
2393                 sq_state = MLX5_SQC_STATE_RDY;
2394                 break;
2395         case MLX5_CMD_OP_2ERR_QP:
2396                 rq_state = MLX5_RQC_STATE_ERR;
2397                 sq_state = MLX5_SQC_STATE_ERR;
2398                 break;
2399         case MLX5_CMD_OP_2RST_QP:
2400                 rq_state = MLX5_RQC_STATE_RST;
2401                 sq_state = MLX5_SQC_STATE_RST;
2402                 break;
2403         case MLX5_CMD_OP_INIT2INIT_QP:
2404         case MLX5_CMD_OP_INIT2RTR_QP:
2405         case MLX5_CMD_OP_RTR2RTS_QP:
2406         case MLX5_CMD_OP_RTS2RTS_QP:
2407                 /* Nothing to do here... */
2408                 return 0;
2409         default:
2410                 WARN_ON(1);
2411                 return -EINVAL;
2412         }
2413
2414         if (qp->rq.wqe_cnt) {
2415                 err =  modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2416                 if (err)
2417                         return err;
2418         }
2419
2420         if (qp->sq.wqe_cnt)
2421                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2422
2423         return 0;
2424 }
2425
2426 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2427                                const struct ib_qp_attr *attr, int attr_mask,
2428                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2429 {
2430         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2431                 [MLX5_QP_STATE_RST] = {
2432                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2433                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2434                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2435                 },
2436                 [MLX5_QP_STATE_INIT]  = {
2437                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2438                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2439                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2440                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2441                 },
2442                 [MLX5_QP_STATE_RTR]   = {
2443                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2444                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2445                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2446                 },
2447                 [MLX5_QP_STATE_RTS]   = {
2448                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2449                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2450                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2451                 },
2452                 [MLX5_QP_STATE_SQD] = {
2453                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2454                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2455                 },
2456                 [MLX5_QP_STATE_SQER] = {
2457                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2458                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2459                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2460                 },
2461                 [MLX5_QP_STATE_ERR] = {
2462                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2463                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2464                 }
2465         };
2466
2467         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2468         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2469         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2470         struct mlx5_ib_cq *send_cq, *recv_cq;
2471         struct mlx5_qp_context *context;
2472         struct mlx5_modify_qp_mbox_in *in;
2473         struct mlx5_ib_pd *pd;
2474         enum mlx5_qp_state mlx5_cur, mlx5_new;
2475         enum mlx5_qp_optpar optpar;
2476         int sqd_event;
2477         int mlx5_st;
2478         int err;
2479         u16 op;
2480
2481         in = kzalloc(sizeof(*in), GFP_KERNEL);
2482         if (!in)
2483                 return -ENOMEM;
2484
2485         context = &in->ctx;
2486         err = to_mlx5_st(ibqp->qp_type);
2487         if (err < 0) {
2488                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2489                 goto out;
2490         }
2491
2492         context->flags = cpu_to_be32(err << 16);
2493
2494         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2495                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2496         } else {
2497                 switch (attr->path_mig_state) {
2498                 case IB_MIG_MIGRATED:
2499                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2500                         break;
2501                 case IB_MIG_REARM:
2502                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2503                         break;
2504                 case IB_MIG_ARMED:
2505                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2506                         break;
2507                 }
2508         }
2509
2510         if (is_sqp(ibqp->qp_type)) {
2511                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2512         } else if (ibqp->qp_type == IB_QPT_UD ||
2513                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2514                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2515         } else if (attr_mask & IB_QP_PATH_MTU) {
2516                 if (attr->path_mtu < IB_MTU_256 ||
2517                     attr->path_mtu > IB_MTU_4096) {
2518                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2519                         err = -EINVAL;
2520                         goto out;
2521                 }
2522                 context->mtu_msgmax = (attr->path_mtu << 5) |
2523                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2524         }
2525
2526         if (attr_mask & IB_QP_DEST_QPN)
2527                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2528
2529         if (attr_mask & IB_QP_PKEY_INDEX)
2530                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2531
2532         /* todo implement counter_index functionality */
2533
2534         if (is_sqp(ibqp->qp_type))
2535                 context->pri_path.port = qp->port;
2536
2537         if (attr_mask & IB_QP_PORT)
2538                 context->pri_path.port = attr->port_num;
2539
2540         if (attr_mask & IB_QP_AV) {
2541                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2542                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2543                                     attr_mask, 0, attr, false);
2544                 if (err)
2545                         goto out;
2546         }
2547
2548         if (attr_mask & IB_QP_TIMEOUT)
2549                 context->pri_path.ackto_lt |= attr->timeout << 3;
2550
2551         if (attr_mask & IB_QP_ALT_PATH) {
2552                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2553                                     &context->alt_path,
2554                                     attr->alt_port_num,
2555                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2556                                     0, attr, true);
2557                 if (err)
2558                         goto out;
2559         }
2560
2561         pd = get_pd(qp);
2562         get_cqs(qp, &send_cq, &recv_cq);
2563
2564         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2565         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2566         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2567         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2568
2569         if (attr_mask & IB_QP_RNR_RETRY)
2570                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2571
2572         if (attr_mask & IB_QP_RETRY_CNT)
2573                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2574
2575         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2576                 if (attr->max_rd_atomic)
2577                         context->params1 |=
2578                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2579         }
2580
2581         if (attr_mask & IB_QP_SQ_PSN)
2582                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2583
2584         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2585                 if (attr->max_dest_rd_atomic)
2586                         context->params2 |=
2587                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2588         }
2589
2590         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2591                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2592
2593         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2594                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2595
2596         if (attr_mask & IB_QP_RQ_PSN)
2597                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2598
2599         if (attr_mask & IB_QP_QKEY)
2600                 context->qkey = cpu_to_be32(attr->qkey);
2601
2602         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2603                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2604
2605         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
2606             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2607                 sqd_event = 1;
2608         else
2609                 sqd_event = 0;
2610
2611         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2612                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2613
2614         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2615                 context->deth_sqpn = cpu_to_be32(1);
2616
2617         mlx5_cur = to_mlx5_state(cur_state);
2618         mlx5_new = to_mlx5_state(new_state);
2619         mlx5_st = to_mlx5_st(ibqp->qp_type);
2620         if (mlx5_st < 0)
2621                 goto out;
2622
2623         /* If moving to a reset or error state, we must disable page faults on
2624          * this QP and flush all current page faults. Otherwise a stale page
2625          * fault may attempt to work on this QP after it is reset and moved
2626          * again to RTS, and may cause the driver and the device to get out of
2627          * sync. */
2628         if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2629             (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2630             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2631                 mlx5_ib_qp_disable_pagefaults(qp);
2632
2633         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2634             !optab[mlx5_cur][mlx5_new])
2635                 goto out;
2636
2637         op = optab[mlx5_cur][mlx5_new];
2638         optpar = ib_mask_to_mlx5_opt(attr_mask);
2639         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2640         in->optparam = cpu_to_be32(optpar);
2641
2642         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2643                 err = modify_raw_packet_qp(dev, qp, op);
2644         else
2645                 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2646                                           &base->mqp);
2647         if (err)
2648                 goto out;
2649
2650         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2651             (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2652                 mlx5_ib_qp_enable_pagefaults(qp);
2653
2654         qp->state = new_state;
2655
2656         if (attr_mask & IB_QP_ACCESS_FLAGS)
2657                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2658         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2659                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2660         if (attr_mask & IB_QP_PORT)
2661                 qp->port = attr->port_num;
2662         if (attr_mask & IB_QP_ALT_PATH)
2663                 qp->trans_qp.alt_port = attr->alt_port_num;
2664
2665         /*
2666          * If we moved a kernel QP to RESET, clean up all old CQ
2667          * entries and reinitialize the QP.
2668          */
2669         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2670                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2671                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2672                 if (send_cq != recv_cq)
2673                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2674
2675                 qp->rq.head = 0;
2676                 qp->rq.tail = 0;
2677                 qp->sq.head = 0;
2678                 qp->sq.tail = 0;
2679                 qp->sq.cur_post = 0;
2680                 qp->sq.last_poll = 0;
2681                 qp->db.db[MLX5_RCV_DBR] = 0;
2682                 qp->db.db[MLX5_SND_DBR] = 0;
2683         }
2684
2685 out:
2686         kfree(in);
2687         return err;
2688 }
2689
2690 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2691                       int attr_mask, struct ib_udata *udata)
2692 {
2693         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2694         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2695         enum ib_qp_type qp_type;
2696         enum ib_qp_state cur_state, new_state;
2697         int err = -EINVAL;
2698         int port;
2699         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2700
2701         if (ibqp->rwq_ind_tbl)
2702                 return -ENOSYS;
2703
2704         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2705                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2706
2707         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2708                 IB_QPT_GSI : ibqp->qp_type;
2709
2710         mutex_lock(&qp->mutex);
2711
2712         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2713         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2714
2715         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2716                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2717                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2718         }
2719
2720         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2721             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2722                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2723                             cur_state, new_state, ibqp->qp_type, attr_mask);
2724                 goto out;
2725         }
2726
2727         if ((attr_mask & IB_QP_PORT) &&
2728             (attr->port_num == 0 ||
2729              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2730                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2731                             attr->port_num, dev->num_ports);
2732                 goto out;
2733         }
2734
2735         if (attr_mask & IB_QP_PKEY_INDEX) {
2736                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2737                 if (attr->pkey_index >=
2738                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2739                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2740                                     attr->pkey_index);
2741                         goto out;
2742                 }
2743         }
2744
2745         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2746             attr->max_rd_atomic >
2747             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2748                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2749                             attr->max_rd_atomic);
2750                 goto out;
2751         }
2752
2753         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2754             attr->max_dest_rd_atomic >
2755             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2756                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2757                             attr->max_dest_rd_atomic);
2758                 goto out;
2759         }
2760
2761         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2762                 err = 0;
2763                 goto out;
2764         }
2765
2766         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2767
2768 out:
2769         mutex_unlock(&qp->mutex);
2770         return err;
2771 }
2772
2773 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2774 {
2775         struct mlx5_ib_cq *cq;
2776         unsigned cur;
2777
2778         cur = wq->head - wq->tail;
2779         if (likely(cur + nreq < wq->max_post))
2780                 return 0;
2781
2782         cq = to_mcq(ib_cq);
2783         spin_lock(&cq->lock);
2784         cur = wq->head - wq->tail;
2785         spin_unlock(&cq->lock);
2786
2787         return cur + nreq >= wq->max_post;
2788 }
2789
2790 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2791                                           u64 remote_addr, u32 rkey)
2792 {
2793         rseg->raddr    = cpu_to_be64(remote_addr);
2794         rseg->rkey     = cpu_to_be32(rkey);
2795         rseg->reserved = 0;
2796 }
2797
2798 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2799                          struct ib_send_wr *wr, void *qend,
2800                          struct mlx5_ib_qp *qp, int *size)
2801 {
2802         void *seg = eseg;
2803
2804         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2805
2806         if (wr->send_flags & IB_SEND_IP_CSUM)
2807                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2808                                  MLX5_ETH_WQE_L4_CSUM;
2809
2810         seg += sizeof(struct mlx5_wqe_eth_seg);
2811         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2812
2813         if (wr->opcode == IB_WR_LSO) {
2814                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2815                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2816                 u64 left, leftlen, copysz;
2817                 void *pdata = ud_wr->header;
2818
2819                 left = ud_wr->hlen;
2820                 eseg->mss = cpu_to_be16(ud_wr->mss);
2821                 eseg->inline_hdr_sz = cpu_to_be16(left);
2822
2823                 /*
2824                  * check if there is space till the end of queue, if yes,
2825                  * copy all in one shot, otherwise copy till the end of queue,
2826                  * rollback and than the copy the left
2827                  */
2828                 leftlen = qend - (void *)eseg->inline_hdr_start;
2829                 copysz = min_t(u64, leftlen, left);
2830
2831                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2832
2833                 if (likely(copysz > size_of_inl_hdr_start)) {
2834                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2835                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2836                 }
2837
2838                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2839                         seg = mlx5_get_send_wqe(qp, 0);
2840                         left -= copysz;
2841                         pdata += copysz;
2842                         memcpy(seg, pdata, left);
2843                         seg += ALIGN(left, 16);
2844                         *size += ALIGN(left, 16) / 16;
2845                 }
2846         }
2847
2848         return seg;
2849 }
2850
2851 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2852                              struct ib_send_wr *wr)
2853 {
2854         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2855         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2856         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2857 }
2858
2859 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2860 {
2861         dseg->byte_count = cpu_to_be32(sg->length);
2862         dseg->lkey       = cpu_to_be32(sg->lkey);
2863         dseg->addr       = cpu_to_be64(sg->addr);
2864 }
2865
2866 static __be16 get_klm_octo(int npages)
2867 {
2868         return cpu_to_be16(ALIGN(npages, 8) / 2);
2869 }
2870
2871 static __be64 frwr_mkey_mask(void)
2872 {
2873         u64 result;
2874
2875         result = MLX5_MKEY_MASK_LEN             |
2876                 MLX5_MKEY_MASK_PAGE_SIZE        |
2877                 MLX5_MKEY_MASK_START_ADDR       |
2878                 MLX5_MKEY_MASK_EN_RINVAL        |
2879                 MLX5_MKEY_MASK_KEY              |
2880                 MLX5_MKEY_MASK_LR               |
2881                 MLX5_MKEY_MASK_LW               |
2882                 MLX5_MKEY_MASK_RR               |
2883                 MLX5_MKEY_MASK_RW               |
2884                 MLX5_MKEY_MASK_A                |
2885                 MLX5_MKEY_MASK_SMALL_FENCE      |
2886                 MLX5_MKEY_MASK_FREE;
2887
2888         return cpu_to_be64(result);
2889 }
2890
2891 static __be64 sig_mkey_mask(void)
2892 {
2893         u64 result;
2894
2895         result = MLX5_MKEY_MASK_LEN             |
2896                 MLX5_MKEY_MASK_PAGE_SIZE        |
2897                 MLX5_MKEY_MASK_START_ADDR       |
2898                 MLX5_MKEY_MASK_EN_SIGERR        |
2899                 MLX5_MKEY_MASK_EN_RINVAL        |
2900                 MLX5_MKEY_MASK_KEY              |
2901                 MLX5_MKEY_MASK_LR               |
2902                 MLX5_MKEY_MASK_LW               |
2903                 MLX5_MKEY_MASK_RR               |
2904                 MLX5_MKEY_MASK_RW               |
2905                 MLX5_MKEY_MASK_SMALL_FENCE      |
2906                 MLX5_MKEY_MASK_FREE             |
2907                 MLX5_MKEY_MASK_BSF_EN;
2908
2909         return cpu_to_be64(result);
2910 }
2911
2912 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2913                                 struct mlx5_ib_mr *mr)
2914 {
2915         int ndescs = mr->ndescs;
2916
2917         memset(umr, 0, sizeof(*umr));
2918
2919         if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2920                 /* KLMs take twice the size of MTTs */
2921                 ndescs *= 2;
2922
2923         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2924         umr->klm_octowords = get_klm_octo(ndescs);
2925         umr->mkey_mask = frwr_mkey_mask();
2926 }
2927
2928 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
2929 {
2930         memset(umr, 0, sizeof(*umr));
2931         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2932         umr->flags = 1 << 7;
2933 }
2934
2935 static __be64 get_umr_reg_mr_mask(void)
2936 {
2937         u64 result;
2938
2939         result = MLX5_MKEY_MASK_LEN             |
2940                  MLX5_MKEY_MASK_PAGE_SIZE       |
2941                  MLX5_MKEY_MASK_START_ADDR      |
2942                  MLX5_MKEY_MASK_PD              |
2943                  MLX5_MKEY_MASK_LR              |
2944                  MLX5_MKEY_MASK_LW              |
2945                  MLX5_MKEY_MASK_KEY             |
2946                  MLX5_MKEY_MASK_RR              |
2947                  MLX5_MKEY_MASK_RW              |
2948                  MLX5_MKEY_MASK_A               |
2949                  MLX5_MKEY_MASK_FREE;
2950
2951         return cpu_to_be64(result);
2952 }
2953
2954 static __be64 get_umr_unreg_mr_mask(void)
2955 {
2956         u64 result;
2957
2958         result = MLX5_MKEY_MASK_FREE;
2959
2960         return cpu_to_be64(result);
2961 }
2962
2963 static __be64 get_umr_update_mtt_mask(void)
2964 {
2965         u64 result;
2966
2967         result = MLX5_MKEY_MASK_FREE;
2968
2969         return cpu_to_be64(result);
2970 }
2971
2972 static __be64 get_umr_update_translation_mask(void)
2973 {
2974         u64 result;
2975
2976         result = MLX5_MKEY_MASK_LEN |
2977                  MLX5_MKEY_MASK_PAGE_SIZE |
2978                  MLX5_MKEY_MASK_START_ADDR |
2979                  MLX5_MKEY_MASK_KEY |
2980                  MLX5_MKEY_MASK_FREE;
2981
2982         return cpu_to_be64(result);
2983 }
2984
2985 static __be64 get_umr_update_access_mask(void)
2986 {
2987         u64 result;
2988
2989         result = MLX5_MKEY_MASK_LW |
2990                  MLX5_MKEY_MASK_RR |
2991                  MLX5_MKEY_MASK_RW |
2992                  MLX5_MKEY_MASK_A |
2993                  MLX5_MKEY_MASK_KEY |
2994                  MLX5_MKEY_MASK_FREE;
2995
2996         return cpu_to_be64(result);
2997 }
2998
2999 static __be64 get_umr_update_pd_mask(void)
3000 {
3001         u64 result;
3002
3003         result = MLX5_MKEY_MASK_PD |
3004                  MLX5_MKEY_MASK_KEY |
3005                  MLX5_MKEY_MASK_FREE;
3006
3007         return cpu_to_be64(result);
3008 }
3009
3010 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3011                                 struct ib_send_wr *wr)
3012 {
3013         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3014
3015         memset(umr, 0, sizeof(*umr));
3016
3017         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3018                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3019         else
3020                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3021
3022         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3023                 umr->klm_octowords = get_klm_octo(umrwr->npages);
3024                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3025                         umr->mkey_mask = get_umr_update_mtt_mask();
3026                         umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3027                         umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3028                 }
3029                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3030                         umr->mkey_mask |= get_umr_update_translation_mask();
3031                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3032                         umr->mkey_mask |= get_umr_update_access_mask();
3033                 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3034                         umr->mkey_mask |= get_umr_update_pd_mask();
3035                 if (!umr->mkey_mask)
3036                         umr->mkey_mask = get_umr_reg_mr_mask();
3037         } else {
3038                 umr->mkey_mask = get_umr_unreg_mr_mask();
3039         }
3040
3041         if (!wr->num_sge)
3042                 umr->flags |= MLX5_UMR_INLINE;
3043 }
3044
3045 static u8 get_umr_flags(int acc)
3046 {
3047         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3048                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3049                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3050                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3051                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3052 }
3053
3054 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3055                              struct mlx5_ib_mr *mr,
3056                              u32 key, int access)
3057 {
3058         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3059
3060         memset(seg, 0, sizeof(*seg));
3061
3062         if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3063                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3064         else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3065                 /* KLMs take twice the size of MTTs */
3066                 ndescs *= 2;
3067
3068         seg->flags = get_umr_flags(access) | mr->access_mode;
3069         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3070         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3071         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3072         seg->len = cpu_to_be64(mr->ibmr.length);
3073         seg->xlt_oct_size = cpu_to_be32(ndescs);
3074 }
3075
3076 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3077 {
3078         memset(seg, 0, sizeof(*seg));
3079         seg->status = MLX5_MKEY_STATUS_FREE;
3080 }
3081
3082 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3083 {
3084         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3085
3086         memset(seg, 0, sizeof(*seg));
3087         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3088                 seg->status = MLX5_MKEY_STATUS_FREE;
3089                 return;
3090         }
3091
3092         seg->flags = convert_access(umrwr->access_flags);
3093         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3094                 if (umrwr->pd)
3095                         seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3096                 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3097         }
3098         seg->len = cpu_to_be64(umrwr->length);
3099         seg->log2_page_size = umrwr->page_shift;
3100         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3101                                        mlx5_mkey_variant(umrwr->mkey));
3102 }
3103
3104 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3105                              struct mlx5_ib_mr *mr,
3106                              struct mlx5_ib_pd *pd)
3107 {
3108         int bcount = mr->desc_size * mr->ndescs;
3109
3110         dseg->addr = cpu_to_be64(mr->desc_map);
3111         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3112         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3113 }
3114
3115 static __be32 send_ieth(struct ib_send_wr *wr)
3116 {
3117         switch (wr->opcode) {
3118         case IB_WR_SEND_WITH_IMM:
3119         case IB_WR_RDMA_WRITE_WITH_IMM:
3120                 return wr->ex.imm_data;
3121
3122         case IB_WR_SEND_WITH_INV:
3123                 return cpu_to_be32(wr->ex.invalidate_rkey);
3124
3125         default:
3126                 return 0;
3127         }
3128 }
3129
3130 static u8 calc_sig(void *wqe, int size)
3131 {
3132         u8 *p = wqe;
3133         u8 res = 0;
3134         int i;
3135
3136         for (i = 0; i < size; i++)
3137                 res ^= p[i];
3138
3139         return ~res;
3140 }
3141
3142 static u8 wq_sig(void *wqe)
3143 {
3144         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3145 }
3146
3147 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3148                             void *wqe, int *sz)
3149 {
3150         struct mlx5_wqe_inline_seg *seg;
3151         void *qend = qp->sq.qend;
3152         void *addr;
3153         int inl = 0;
3154         int copy;
3155         int len;
3156         int i;
3157
3158         seg = wqe;
3159         wqe += sizeof(*seg);
3160         for (i = 0; i < wr->num_sge; i++) {
3161                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3162                 len  = wr->sg_list[i].length;
3163                 inl += len;
3164
3165                 if (unlikely(inl > qp->max_inline_data))
3166                         return -ENOMEM;
3167
3168                 if (unlikely(wqe + len > qend)) {
3169                         copy = qend - wqe;
3170                         memcpy(wqe, addr, copy);
3171                         addr += copy;
3172                         len -= copy;
3173                         wqe = mlx5_get_send_wqe(qp, 0);
3174                 }
3175                 memcpy(wqe, addr, len);
3176                 wqe += len;
3177         }
3178
3179         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3180
3181         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3182
3183         return 0;
3184 }
3185
3186 static u16 prot_field_size(enum ib_signature_type type)
3187 {
3188         switch (type) {
3189         case IB_SIG_TYPE_T10_DIF:
3190                 return MLX5_DIF_SIZE;
3191         default:
3192                 return 0;
3193         }
3194 }
3195
3196 static u8 bs_selector(int block_size)
3197 {
3198         switch (block_size) {
3199         case 512:           return 0x1;
3200         case 520:           return 0x2;
3201         case 4096:          return 0x3;
3202         case 4160:          return 0x4;
3203         case 1073741824:    return 0x5;
3204         default:            return 0;
3205         }
3206 }
3207
3208 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3209                               struct mlx5_bsf_inl *inl)
3210 {
3211         /* Valid inline section and allow BSF refresh */
3212         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3213                                        MLX5_BSF_REFRESH_DIF);
3214         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3215         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3216         /* repeating block */
3217         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3218         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3219                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3220
3221         if (domain->sig.dif.ref_remap)
3222                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3223
3224         if (domain->sig.dif.app_escape) {
3225                 if (domain->sig.dif.ref_escape)
3226                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3227                 else
3228                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3229         }
3230
3231         inl->dif_app_bitmask_check =
3232                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3233 }
3234
3235 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3236                         struct ib_sig_attrs *sig_attrs,
3237                         struct mlx5_bsf *bsf, u32 data_size)
3238 {
3239         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3240         struct mlx5_bsf_basic *basic = &bsf->basic;
3241         struct ib_sig_domain *mem = &sig_attrs->mem;
3242         struct ib_sig_domain *wire = &sig_attrs->wire;
3243
3244         memset(bsf, 0, sizeof(*bsf));
3245
3246         /* Basic + Extended + Inline */
3247         basic->bsf_size_sbs = 1 << 7;
3248         /* Input domain check byte mask */
3249         basic->check_byte_mask = sig_attrs->check_mask;
3250         basic->raw_data_size = cpu_to_be32(data_size);
3251
3252         /* Memory domain */
3253         switch (sig_attrs->mem.sig_type) {
3254         case IB_SIG_TYPE_NONE:
3255                 break;
3256         case IB_SIG_TYPE_T10_DIF:
3257                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3258                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3259                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3260                 break;
3261         default:
3262                 return -EINVAL;
3263         }
3264
3265         /* Wire domain */
3266         switch (sig_attrs->wire.sig_type) {
3267         case IB_SIG_TYPE_NONE:
3268                 break;
3269         case IB_SIG_TYPE_T10_DIF:
3270                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3271                     mem->sig_type == wire->sig_type) {
3272                         /* Same block structure */
3273                         basic->bsf_size_sbs |= 1 << 4;
3274                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3275                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3276                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3277                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3278                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3279                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3280                 } else
3281                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3282
3283                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3284                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3285                 break;
3286         default:
3287                 return -EINVAL;
3288         }
3289
3290         return 0;
3291 }
3292
3293 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3294                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3295 {
3296         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3297         struct ib_mr *sig_mr = wr->sig_mr;
3298         struct mlx5_bsf *bsf;
3299         u32 data_len = wr->wr.sg_list->length;
3300         u32 data_key = wr->wr.sg_list->lkey;
3301         u64 data_va = wr->wr.sg_list->addr;
3302         int ret;
3303         int wqe_size;
3304
3305         if (!wr->prot ||
3306             (data_key == wr->prot->lkey &&
3307              data_va == wr->prot->addr &&
3308              data_len == wr->prot->length)) {
3309                 /**
3310                  * Source domain doesn't contain signature information
3311                  * or data and protection are interleaved in memory.
3312                  * So need construct:
3313                  *                  ------------------
3314                  *                 |     data_klm     |
3315                  *                  ------------------
3316                  *                 |       BSF        |
3317                  *                  ------------------
3318                  **/
3319                 struct mlx5_klm *data_klm = *seg;
3320
3321                 data_klm->bcount = cpu_to_be32(data_len);
3322                 data_klm->key = cpu_to_be32(data_key);
3323                 data_klm->va = cpu_to_be64(data_va);
3324                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3325         } else {
3326                 /**
3327                  * Source domain contains signature information
3328                  * So need construct a strided block format:
3329                  *               ---------------------------
3330                  *              |     stride_block_ctrl     |
3331                  *               ---------------------------
3332                  *              |          data_klm         |
3333                  *               ---------------------------
3334                  *              |          prot_klm         |
3335                  *               ---------------------------
3336                  *              |             BSF           |
3337                  *               ---------------------------
3338                  **/
3339                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3340                 struct mlx5_stride_block_entry *data_sentry;
3341                 struct mlx5_stride_block_entry *prot_sentry;
3342                 u32 prot_key = wr->prot->lkey;
3343                 u64 prot_va = wr->prot->addr;
3344                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3345                 int prot_size;
3346
3347                 sblock_ctrl = *seg;
3348                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3349                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3350
3351                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3352                 if (!prot_size) {
3353                         pr_err("Bad block size given: %u\n", block_size);
3354                         return -EINVAL;
3355                 }
3356                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3357                                                             prot_size);
3358                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3359                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3360                 sblock_ctrl->num_entries = cpu_to_be16(2);
3361
3362                 data_sentry->bcount = cpu_to_be16(block_size);
3363                 data_sentry->key = cpu_to_be32(data_key);
3364                 data_sentry->va = cpu_to_be64(data_va);
3365                 data_sentry->stride = cpu_to_be16(block_size);
3366
3367                 prot_sentry->bcount = cpu_to_be16(prot_size);
3368                 prot_sentry->key = cpu_to_be32(prot_key);
3369                 prot_sentry->va = cpu_to_be64(prot_va);
3370                 prot_sentry->stride = cpu_to_be16(prot_size);
3371
3372                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3373                                  sizeof(*prot_sentry), 64);
3374         }
3375
3376         *seg += wqe_size;
3377         *size += wqe_size / 16;
3378         if (unlikely((*seg == qp->sq.qend)))
3379                 *seg = mlx5_get_send_wqe(qp, 0);
3380
3381         bsf = *seg;
3382         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3383         if (ret)
3384                 return -EINVAL;
3385
3386         *seg += sizeof(*bsf);
3387         *size += sizeof(*bsf) / 16;
3388         if (unlikely((*seg == qp->sq.qend)))
3389                 *seg = mlx5_get_send_wqe(qp, 0);
3390
3391         return 0;
3392 }
3393
3394 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3395                                  struct ib_sig_handover_wr *wr, u32 nelements,
3396                                  u32 length, u32 pdn)
3397 {
3398         struct ib_mr *sig_mr = wr->sig_mr;
3399         u32 sig_key = sig_mr->rkey;
3400         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3401
3402         memset(seg, 0, sizeof(*seg));
3403
3404         seg->flags = get_umr_flags(wr->access_flags) |
3405                                    MLX5_ACCESS_MODE_KLM;
3406         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3407         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3408                                     MLX5_MKEY_BSF_EN | pdn);
3409         seg->len = cpu_to_be64(length);
3410         seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3411         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3412 }
3413
3414 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3415                                 u32 nelements)
3416 {
3417         memset(umr, 0, sizeof(*umr));
3418
3419         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3420         umr->klm_octowords = get_klm_octo(nelements);
3421         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3422         umr->mkey_mask = sig_mkey_mask();
3423 }
3424
3425
3426 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3427                           void **seg, int *size)
3428 {
3429         struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3430         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3431         u32 pdn = get_pd(qp)->pdn;
3432         u32 klm_oct_size;
3433         int region_len, ret;
3434
3435         if (unlikely(wr->wr.num_sge != 1) ||
3436             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3437             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3438             unlikely(!sig_mr->sig->sig_status_checked))
3439                 return -EINVAL;
3440
3441         /* length of the protected region, data + protection */
3442         region_len = wr->wr.sg_list->length;
3443         if (wr->prot &&
3444             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3445              wr->prot->addr != wr->wr.sg_list->addr  ||
3446              wr->prot->length != wr->wr.sg_list->length))
3447                 region_len += wr->prot->length;
3448
3449         /**
3450          * KLM octoword size - if protection was provided
3451          * then we use strided block format (3 octowords),
3452          * else we use single KLM (1 octoword)
3453          **/
3454         klm_oct_size = wr->prot ? 3 : 1;
3455
3456         set_sig_umr_segment(*seg, klm_oct_size);
3457         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3458         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3459         if (unlikely((*seg == qp->sq.qend)))
3460                 *seg = mlx5_get_send_wqe(qp, 0);
3461
3462         set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3463         *seg += sizeof(struct mlx5_mkey_seg);
3464         *size += sizeof(struct mlx5_mkey_seg) / 16;
3465         if (unlikely((*seg == qp->sq.qend)))
3466                 *seg = mlx5_get_send_wqe(qp, 0);
3467
3468         ret = set_sig_data_segment(wr, qp, seg, size);
3469         if (ret)
3470                 return ret;
3471
3472         sig_mr->sig->sig_status_checked = false;
3473         return 0;
3474 }
3475
3476 static int set_psv_wr(struct ib_sig_domain *domain,
3477                       u32 psv_idx, void **seg, int *size)
3478 {
3479         struct mlx5_seg_set_psv *psv_seg = *seg;
3480
3481         memset(psv_seg, 0, sizeof(*psv_seg));
3482         psv_seg->psv_num = cpu_to_be32(psv_idx);
3483         switch (domain->sig_type) {
3484         case IB_SIG_TYPE_NONE:
3485                 break;
3486         case IB_SIG_TYPE_T10_DIF:
3487                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3488                                                      domain->sig.dif.app_tag);
3489                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3490                 break;
3491         default:
3492                 pr_err("Bad signature type given.\n");
3493                 return 1;
3494         }
3495
3496         *seg += sizeof(*psv_seg);
3497         *size += sizeof(*psv_seg) / 16;
3498
3499         return 0;
3500 }
3501
3502 static int set_reg_wr(struct mlx5_ib_qp *qp,
3503                       struct ib_reg_wr *wr,
3504                       void **seg, int *size)
3505 {
3506         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3507         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3508
3509         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3510                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3511                              "Invalid IB_SEND_INLINE send flag\n");
3512                 return -EINVAL;
3513         }
3514
3515         set_reg_umr_seg(*seg, mr);
3516         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3517         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3518         if (unlikely((*seg == qp->sq.qend)))
3519                 *seg = mlx5_get_send_wqe(qp, 0);
3520
3521         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3522         *seg += sizeof(struct mlx5_mkey_seg);
3523         *size += sizeof(struct mlx5_mkey_seg) / 16;
3524         if (unlikely((*seg == qp->sq.qend)))
3525                 *seg = mlx5_get_send_wqe(qp, 0);
3526
3527         set_reg_data_seg(*seg, mr, pd);
3528         *seg += sizeof(struct mlx5_wqe_data_seg);
3529         *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3530
3531         return 0;
3532 }
3533
3534 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3535 {
3536         set_linv_umr_seg(*seg);
3537         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3538         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3539         if (unlikely((*seg == qp->sq.qend)))
3540                 *seg = mlx5_get_send_wqe(qp, 0);
3541         set_linv_mkey_seg(*seg);
3542         *seg += sizeof(struct mlx5_mkey_seg);
3543         *size += sizeof(struct mlx5_mkey_seg) / 16;
3544         if (unlikely((*seg == qp->sq.qend)))
3545                 *seg = mlx5_get_send_wqe(qp, 0);
3546 }
3547
3548 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3549 {
3550         __be32 *p = NULL;
3551         int tidx = idx;
3552         int i, j;
3553
3554         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3555         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3556                 if ((i & 0xf) == 0) {
3557                         void *buf = mlx5_get_send_wqe(qp, tidx);
3558                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3559                         p = buf;
3560                         j = 0;
3561                 }
3562                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3563                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3564                          be32_to_cpu(p[j + 3]));
3565         }
3566 }
3567
3568 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3569                          unsigned bytecnt, struct mlx5_ib_qp *qp)
3570 {
3571         while (bytecnt > 0) {
3572                 __iowrite64_copy(dst++, src++, 8);
3573                 __iowrite64_copy(dst++, src++, 8);
3574                 __iowrite64_copy(dst++, src++, 8);
3575                 __iowrite64_copy(dst++, src++, 8);
3576                 __iowrite64_copy(dst++, src++, 8);
3577                 __iowrite64_copy(dst++, src++, 8);
3578                 __iowrite64_copy(dst++, src++, 8);
3579                 __iowrite64_copy(dst++, src++, 8);
3580                 bytecnt -= 64;
3581                 if (unlikely(src == qp->sq.qend))
3582                         src = mlx5_get_send_wqe(qp, 0);
3583         }
3584 }
3585
3586 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3587 {
3588         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3589                      wr->send_flags & IB_SEND_FENCE))
3590                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3591
3592         if (unlikely(fence)) {
3593                 if (wr->send_flags & IB_SEND_FENCE)
3594                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3595                 else
3596                         return fence;
3597
3598         } else {
3599                 return 0;
3600         }
3601 }
3602
3603 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3604                      struct mlx5_wqe_ctrl_seg **ctrl,
3605                      struct ib_send_wr *wr, unsigned *idx,
3606                      int *size, int nreq)
3607 {
3608         int err = 0;
3609
3610         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3611                 err = -ENOMEM;
3612                 return err;
3613         }
3614
3615         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3616         *seg = mlx5_get_send_wqe(qp, *idx);
3617         *ctrl = *seg;
3618         *(uint32_t *)(*seg + 8) = 0;
3619         (*ctrl)->imm = send_ieth(wr);
3620         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3621                 (wr->send_flags & IB_SEND_SIGNALED ?
3622                  MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3623                 (wr->send_flags & IB_SEND_SOLICITED ?
3624                  MLX5_WQE_CTRL_SOLICITED : 0);
3625
3626         *seg += sizeof(**ctrl);
3627         *size = sizeof(**ctrl) / 16;
3628
3629         return err;
3630 }
3631
3632 static void finish_wqe(struct mlx5_ib_qp *qp,
3633                        struct mlx5_wqe_ctrl_seg *ctrl,
3634                        u8 size, unsigned idx, u64 wr_id,
3635                        int nreq, u8 fence, u8 next_fence,
3636                        u32 mlx5_opcode)
3637 {
3638         u8 opmod = 0;
3639
3640         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3641                                              mlx5_opcode | ((u32)opmod << 24));
3642         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3643         ctrl->fm_ce_se |= fence;
3644         qp->fm_cache = next_fence;
3645         if (unlikely(qp->wq_sig))
3646                 ctrl->signature = wq_sig(ctrl);
3647
3648         qp->sq.wrid[idx] = wr_id;
3649         qp->sq.w_list[idx].opcode = mlx5_opcode;
3650         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3651         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3652         qp->sq.w_list[idx].next = qp->sq.cur_post;
3653 }
3654
3655
3656 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3657                       struct ib_send_wr **bad_wr)
3658 {
3659         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3660         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3661         struct mlx5_ib_qp *qp;
3662         struct mlx5_ib_mr *mr;
3663         struct mlx5_wqe_data_seg *dpseg;
3664         struct mlx5_wqe_xrc_seg *xrc;
3665         struct mlx5_bf *bf;
3666         int uninitialized_var(size);
3667         void *qend;
3668         unsigned long flags;
3669         unsigned idx;
3670         int err = 0;
3671         int inl = 0;
3672         int num_sge;
3673         void *seg;
3674         int nreq;
3675         int i;
3676         u8 next_fence = 0;
3677         u8 fence;
3678
3679         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3680                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3681
3682         qp = to_mqp(ibqp);
3683         bf = qp->bf;
3684         qend = qp->sq.qend;
3685
3686         spin_lock_irqsave(&qp->sq.lock, flags);
3687
3688         for (nreq = 0; wr; nreq++, wr = wr->next) {
3689                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3690                         mlx5_ib_warn(dev, "\n");
3691                         err = -EINVAL;
3692                         *bad_wr = wr;
3693                         goto out;
3694                 }
3695
3696                 fence = qp->fm_cache;
3697                 num_sge = wr->num_sge;
3698                 if (unlikely(num_sge > qp->sq.max_gs)) {
3699                         mlx5_ib_warn(dev, "\n");
3700                         err = -ENOMEM;
3701                         *bad_wr = wr;
3702                         goto out;
3703                 }
3704
3705                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3706                 if (err) {
3707                         mlx5_ib_warn(dev, "\n");
3708                         err = -ENOMEM;
3709                         *bad_wr = wr;
3710                         goto out;
3711                 }
3712
3713                 switch (ibqp->qp_type) {
3714                 case IB_QPT_XRC_INI:
3715                         xrc = seg;
3716                         seg += sizeof(*xrc);
3717                         size += sizeof(*xrc) / 16;
3718                         /* fall through */
3719                 case IB_QPT_RC:
3720                         switch (wr->opcode) {
3721                         case IB_WR_RDMA_READ:
3722                         case IB_WR_RDMA_WRITE:
3723                         case IB_WR_RDMA_WRITE_WITH_IMM:
3724                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3725                                               rdma_wr(wr)->rkey);
3726                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
3727                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3728                                 break;
3729
3730                         case IB_WR_ATOMIC_CMP_AND_SWP:
3731                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3732                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3733                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3734                                 err = -ENOSYS;
3735                                 *bad_wr = wr;
3736                                 goto out;
3737
3738                         case IB_WR_LOCAL_INV:
3739                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3740                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3741                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3742                                 set_linv_wr(qp, &seg, &size);
3743                                 num_sge = 0;
3744                                 break;
3745
3746                         case IB_WR_REG_MR:
3747                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3748                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3749                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3750                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3751                                 if (err) {
3752                                         *bad_wr = wr;
3753                                         goto out;
3754                                 }
3755                                 num_sge = 0;
3756                                 break;
3757
3758                         case IB_WR_REG_SIG_MR:
3759                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3760                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3761
3762                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3763                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
3764                                 if (err) {
3765                                         mlx5_ib_warn(dev, "\n");
3766                                         *bad_wr = wr;
3767                                         goto out;
3768                                 }
3769
3770                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3771                                            nreq, get_fence(fence, wr),
3772                                            next_fence, MLX5_OPCODE_UMR);
3773                                 /*
3774                                  * SET_PSV WQEs are not signaled and solicited
3775                                  * on error
3776                                  */
3777                                 wr->send_flags &= ~IB_SEND_SIGNALED;
3778                                 wr->send_flags |= IB_SEND_SOLICITED;
3779                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3780                                                 &idx, &size, nreq);
3781                                 if (err) {
3782                                         mlx5_ib_warn(dev, "\n");
3783                                         err = -ENOMEM;
3784                                         *bad_wr = wr;
3785                                         goto out;
3786                                 }
3787
3788                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3789                                                  mr->sig->psv_memory.psv_idx, &seg,
3790                                                  &size);
3791                                 if (err) {
3792                                         mlx5_ib_warn(dev, "\n");
3793                                         *bad_wr = wr;
3794                                         goto out;
3795                                 }
3796
3797                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3798                                            nreq, get_fence(fence, wr),
3799                                            next_fence, MLX5_OPCODE_SET_PSV);
3800                                 err = begin_wqe(qp, &seg, &ctrl, wr,
3801                                                 &idx, &size, nreq);
3802                                 if (err) {
3803                                         mlx5_ib_warn(dev, "\n");
3804                                         err = -ENOMEM;
3805                                         *bad_wr = wr;
3806                                         goto out;
3807                                 }
3808
3809                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3810                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3811                                                  mr->sig->psv_wire.psv_idx, &seg,
3812                                                  &size);
3813                                 if (err) {
3814                                         mlx5_ib_warn(dev, "\n");
3815                                         *bad_wr = wr;
3816                                         goto out;
3817                                 }
3818
3819                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3820                                            nreq, get_fence(fence, wr),
3821                                            next_fence, MLX5_OPCODE_SET_PSV);
3822                                 num_sge = 0;
3823                                 goto skip_psv;
3824
3825                         default:
3826                                 break;
3827                         }
3828                         break;
3829
3830                 case IB_QPT_UC:
3831                         switch (wr->opcode) {
3832                         case IB_WR_RDMA_WRITE:
3833                         case IB_WR_RDMA_WRITE_WITH_IMM:
3834                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3835                                               rdma_wr(wr)->rkey);
3836                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
3837                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3838                                 break;
3839
3840                         default:
3841                                 break;
3842                         }
3843                         break;
3844
3845                 case IB_QPT_SMI:
3846                 case MLX5_IB_QPT_HW_GSI:
3847                         set_datagram_seg(seg, wr);
3848                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3849                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3850                         if (unlikely((seg == qend)))
3851                                 seg = mlx5_get_send_wqe(qp, 0);
3852                         break;
3853                 case IB_QPT_UD:
3854                         set_datagram_seg(seg, wr);
3855                         seg += sizeof(struct mlx5_wqe_datagram_seg);
3856                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3857
3858                         if (unlikely((seg == qend)))
3859                                 seg = mlx5_get_send_wqe(qp, 0);
3860
3861                         /* handle qp that supports ud offload */
3862                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3863                                 struct mlx5_wqe_eth_pad *pad;
3864
3865                                 pad = seg;
3866                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3867                                 seg += sizeof(struct mlx5_wqe_eth_pad);
3868                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3869
3870                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
3871
3872                                 if (unlikely((seg == qend)))
3873                                         seg = mlx5_get_send_wqe(qp, 0);
3874                         }
3875                         break;
3876                 case MLX5_IB_QPT_REG_UMR:
3877                         if (wr->opcode != MLX5_IB_WR_UMR) {
3878                                 err = -EINVAL;
3879                                 mlx5_ib_warn(dev, "bad opcode\n");
3880                                 goto out;
3881                         }
3882                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
3883                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
3884                         set_reg_umr_segment(seg, wr);
3885                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3886                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3887                         if (unlikely((seg == qend)))
3888                                 seg = mlx5_get_send_wqe(qp, 0);
3889                         set_reg_mkey_segment(seg, wr);
3890                         seg += sizeof(struct mlx5_mkey_seg);
3891                         size += sizeof(struct mlx5_mkey_seg) / 16;
3892                         if (unlikely((seg == qend)))
3893                                 seg = mlx5_get_send_wqe(qp, 0);
3894                         break;
3895
3896                 default:
3897                         break;
3898                 }
3899
3900                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3901                         int uninitialized_var(sz);
3902
3903                         err = set_data_inl_seg(qp, wr, seg, &sz);
3904                         if (unlikely(err)) {
3905                                 mlx5_ib_warn(dev, "\n");
3906                                 *bad_wr = wr;
3907                                 goto out;
3908                         }
3909                         inl = 1;
3910                         size += sz;
3911                 } else {
3912                         dpseg = seg;
3913                         for (i = 0; i < num_sge; i++) {
3914                                 if (unlikely(dpseg == qend)) {
3915                                         seg = mlx5_get_send_wqe(qp, 0);
3916                                         dpseg = seg;
3917                                 }
3918                                 if (likely(wr->sg_list[i].length)) {
3919                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
3920                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
3921                                         dpseg++;
3922                                 }
3923                         }
3924                 }
3925
3926                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3927                            get_fence(fence, wr), next_fence,
3928                            mlx5_ib_opcode[wr->opcode]);
3929 skip_psv:
3930                 if (0)
3931                         dump_wqe(qp, idx, size);
3932         }
3933
3934 out:
3935         if (likely(nreq)) {
3936                 qp->sq.head += nreq;
3937
3938                 /* Make sure that descriptors are written before
3939                  * updating doorbell record and ringing the doorbell
3940                  */
3941                 wmb();
3942
3943                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3944
3945                 /* Make sure doorbell record is visible to the HCA before
3946                  * we hit doorbell */
3947                 wmb();
3948
3949                 if (bf->need_lock)
3950                         spin_lock(&bf->lock);
3951                 else
3952                         __acquire(&bf->lock);
3953
3954                 /* TBD enable WC */
3955                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
3956                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
3957                         /* wc_wmb(); */
3958                 } else {
3959                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
3960                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
3961                         /* Make sure doorbells don't leak out of SQ spinlock
3962                          * and reach the HCA out of order.
3963                          */
3964                         mmiowb();
3965                 }
3966                 bf->offset ^= bf->buf_size;
3967                 if (bf->need_lock)
3968                         spin_unlock(&bf->lock);
3969                 else
3970                         __release(&bf->lock);
3971         }
3972
3973         spin_unlock_irqrestore(&qp->sq.lock, flags);
3974
3975         return err;
3976 }
3977
3978 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
3979 {
3980         sig->signature = calc_sig(sig, size);
3981 }
3982
3983 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3984                       struct ib_recv_wr **bad_wr)
3985 {
3986         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3987         struct mlx5_wqe_data_seg *scat;
3988         struct mlx5_rwqe_sig *sig;
3989         unsigned long flags;
3990         int err = 0;
3991         int nreq;
3992         int ind;
3993         int i;
3994
3995         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3996                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
3997
3998         spin_lock_irqsave(&qp->rq.lock, flags);
3999
4000         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4001
4002         for (nreq = 0; wr; nreq++, wr = wr->next) {
4003                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4004                         err = -ENOMEM;
4005                         *bad_wr = wr;
4006                         goto out;
4007                 }
4008
4009                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4010                         err = -EINVAL;
4011                         *bad_wr = wr;
4012                         goto out;
4013                 }
4014
4015                 scat = get_recv_wqe(qp, ind);
4016                 if (qp->wq_sig)
4017                         scat++;
4018
4019                 for (i = 0; i < wr->num_sge; i++)
4020                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4021
4022                 if (i < qp->rq.max_gs) {
4023                         scat[i].byte_count = 0;
4024                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4025                         scat[i].addr       = 0;
4026                 }
4027
4028                 if (qp->wq_sig) {
4029                         sig = (struct mlx5_rwqe_sig *)scat;
4030                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4031                 }
4032
4033                 qp->rq.wrid[ind] = wr->wr_id;
4034
4035                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4036         }
4037
4038 out:
4039         if (likely(nreq)) {
4040                 qp->rq.head += nreq;
4041
4042                 /* Make sure that descriptors are written before
4043                  * doorbell record.
4044                  */
4045                 wmb();
4046
4047                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4048         }
4049
4050         spin_unlock_irqrestore(&qp->rq.lock, flags);
4051
4052         return err;
4053 }
4054
4055 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4056 {
4057         switch (mlx5_state) {
4058         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4059         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4060         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4061         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4062         case MLX5_QP_STATE_SQ_DRAINING:
4063         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4064         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4065         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4066         default:                     return -1;
4067         }
4068 }
4069
4070 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4071 {
4072         switch (mlx5_mig_state) {
4073         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4074         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4075         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4076         default: return -1;
4077         }
4078 }
4079
4080 static int to_ib_qp_access_flags(int mlx5_flags)
4081 {
4082         int ib_flags = 0;
4083
4084         if (mlx5_flags & MLX5_QP_BIT_RRE)
4085                 ib_flags |= IB_ACCESS_REMOTE_READ;
4086         if (mlx5_flags & MLX5_QP_BIT_RWE)
4087                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4088         if (mlx5_flags & MLX5_QP_BIT_RAE)
4089                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4090
4091         return ib_flags;
4092 }
4093
4094 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4095                                 struct mlx5_qp_path *path)
4096 {
4097         struct mlx5_core_dev *dev = ibdev->mdev;
4098
4099         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4100         ib_ah_attr->port_num      = path->port;
4101
4102         if (ib_ah_attr->port_num == 0 ||
4103             ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4104                 return;
4105
4106         ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4107
4108         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
4109         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4110         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4111         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4112         if (ib_ah_attr->ah_flags) {
4113                 ib_ah_attr->grh.sgid_index = path->mgid_index;
4114                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
4115                 ib_ah_attr->grh.traffic_class =
4116                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4117                 ib_ah_attr->grh.flow_label =
4118                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4119                 memcpy(ib_ah_attr->grh.dgid.raw,
4120                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4121         }
4122 }
4123
4124 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4125                                         struct mlx5_ib_sq *sq,
4126                                         u8 *sq_state)
4127 {
4128         void *out;
4129         void *sqc;
4130         int inlen;
4131         int err;
4132
4133         inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4134         out = mlx5_vzalloc(inlen);
4135         if (!out)
4136                 return -ENOMEM;
4137
4138         err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4139         if (err)
4140                 goto out;
4141
4142         sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4143         *sq_state = MLX5_GET(sqc, sqc, state);
4144         sq->state = *sq_state;
4145
4146 out:
4147         kvfree(out);
4148         return err;
4149 }
4150
4151 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4152                                         struct mlx5_ib_rq *rq,
4153                                         u8 *rq_state)
4154 {
4155         void *out;
4156         void *rqc;
4157         int inlen;
4158         int err;
4159
4160         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4161         out = mlx5_vzalloc(inlen);
4162         if (!out)
4163                 return -ENOMEM;
4164
4165         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4166         if (err)
4167                 goto out;
4168
4169         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4170         *rq_state = MLX5_GET(rqc, rqc, state);
4171         rq->state = *rq_state;
4172
4173 out:
4174         kvfree(out);
4175         return err;
4176 }
4177
4178 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4179                                   struct mlx5_ib_qp *qp, u8 *qp_state)
4180 {
4181         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4182                 [MLX5_RQC_STATE_RST] = {
4183                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4184                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4185                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
4186                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
4187                 },
4188                 [MLX5_RQC_STATE_RDY] = {
4189                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4190                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4191                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
4192                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
4193                 },
4194                 [MLX5_RQC_STATE_ERR] = {
4195                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4196                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
4197                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
4198                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
4199                 },
4200                 [MLX5_RQ_STATE_NA] = {
4201                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4202                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
4203                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
4204                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
4205                 },
4206         };
4207
4208         *qp_state = sqrq_trans[rq_state][sq_state];
4209
4210         if (*qp_state == MLX5_QP_STATE_BAD) {
4211                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4212                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4213                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4214                 return -EINVAL;
4215         }
4216
4217         if (*qp_state == MLX5_QP_STATE)
4218                 *qp_state = qp->state;
4219
4220         return 0;
4221 }
4222
4223 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4224                                      struct mlx5_ib_qp *qp,
4225                                      u8 *raw_packet_qp_state)
4226 {
4227         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4228         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4229         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4230         int err;
4231         u8 sq_state = MLX5_SQ_STATE_NA;
4232         u8 rq_state = MLX5_RQ_STATE_NA;
4233
4234         if (qp->sq.wqe_cnt) {
4235                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4236                 if (err)
4237                         return err;
4238         }
4239
4240         if (qp->rq.wqe_cnt) {
4241                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4242                 if (err)
4243                         return err;
4244         }
4245
4246         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4247                                       raw_packet_qp_state);
4248 }
4249
4250 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4251                          struct ib_qp_attr *qp_attr)
4252 {
4253         struct mlx5_query_qp_mbox_out *outb;
4254         struct mlx5_qp_context *context;
4255         int mlx5_state;
4256         int err = 0;
4257
4258         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
4259         if (!outb)
4260                 return -ENOMEM;
4261
4262         context = &outb->ctx;
4263         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4264                                  sizeof(*outb));
4265         if (err)
4266                 goto out;
4267
4268         mlx5_state = be32_to_cpu(context->flags) >> 28;
4269
4270         qp->state                    = to_ib_qp_state(mlx5_state);
4271         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
4272         qp_attr->path_mig_state      =
4273                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4274         qp_attr->qkey                = be32_to_cpu(context->qkey);
4275         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4276         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
4277         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4278         qp_attr->qp_access_flags     =
4279                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4280
4281         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4282                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4283                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4284                 qp_attr->alt_pkey_index =
4285                         be16_to_cpu(context->alt_path.pkey_index);
4286                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
4287         }
4288
4289         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4290         qp_attr->port_num = context->pri_path.port;
4291
4292         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4293         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4294
4295         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4296
4297         qp_attr->max_dest_rd_atomic =
4298                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4299         qp_attr->min_rnr_timer      =
4300                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4301         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
4302         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
4303         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
4304         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
4305
4306 out:
4307         kfree(outb);
4308         return err;
4309 }
4310
4311 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4312                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4313 {
4314         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4315         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4316         int err = 0;
4317         u8 raw_packet_qp_state;
4318
4319         if (ibqp->rwq_ind_tbl)
4320                 return -ENOSYS;
4321
4322         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4323                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4324                                             qp_init_attr);
4325
4326 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4327         /*
4328          * Wait for any outstanding page faults, in case the user frees memory
4329          * based upon this query's result.
4330          */
4331         flush_workqueue(mlx5_ib_page_fault_wq);
4332 #endif
4333
4334         mutex_lock(&qp->mutex);
4335
4336         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4337                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4338                 if (err)
4339                         goto out;
4340                 qp->state = raw_packet_qp_state;
4341                 qp_attr->port_num = 1;
4342         } else {
4343                 err = query_qp_attr(dev, qp, qp_attr);
4344                 if (err)
4345                         goto out;
4346         }
4347
4348         qp_attr->qp_state            = qp->state;
4349         qp_attr->cur_qp_state        = qp_attr->qp_state;
4350         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4351         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4352
4353         if (!ibqp->uobject) {
4354                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
4355                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4356                 qp_init_attr->qp_context = ibqp->qp_context;
4357         } else {
4358                 qp_attr->cap.max_send_wr  = 0;
4359                 qp_attr->cap.max_send_sge = 0;
4360         }
4361
4362         qp_init_attr->qp_type = ibqp->qp_type;
4363         qp_init_attr->recv_cq = ibqp->recv_cq;
4364         qp_init_attr->send_cq = ibqp->send_cq;
4365         qp_init_attr->srq = ibqp->srq;
4366         qp_attr->cap.max_inline_data = qp->max_inline_data;
4367
4368         qp_init_attr->cap            = qp_attr->cap;
4369
4370         qp_init_attr->create_flags = 0;
4371         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4372                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4373
4374         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4375                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4376         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4377                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4378         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4379                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4380         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4381                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4382
4383         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4384                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4385
4386 out:
4387         mutex_unlock(&qp->mutex);
4388         return err;
4389 }
4390
4391 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4392                                           struct ib_ucontext *context,
4393                                           struct ib_udata *udata)
4394 {
4395         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4396         struct mlx5_ib_xrcd *xrcd;
4397         int err;
4398
4399         if (!MLX5_CAP_GEN(dev->mdev, xrc))
4400                 return ERR_PTR(-ENOSYS);
4401
4402         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4403         if (!xrcd)
4404                 return ERR_PTR(-ENOMEM);
4405
4406         err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4407         if (err) {
4408                 kfree(xrcd);
4409                 return ERR_PTR(-ENOMEM);
4410         }
4411
4412         return &xrcd->ibxrcd;
4413 }
4414
4415 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4416 {
4417         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4418         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4419         int err;
4420
4421         err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4422         if (err) {
4423                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4424                 return err;
4425         }
4426
4427         kfree(xrcd);
4428
4429         return 0;
4430 }
4431
4432 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4433                       struct ib_wq_init_attr *init_attr)
4434 {
4435         struct mlx5_ib_dev *dev;
4436         __be64 *rq_pas0;
4437         void *in;
4438         void *rqc;
4439         void *wq;
4440         int inlen;
4441         int err;
4442
4443         dev = to_mdev(pd->device);
4444
4445         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4446         in = mlx5_vzalloc(inlen);
4447         if (!in)
4448                 return -ENOMEM;
4449
4450         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4451         MLX5_SET(rqc,  rqc, mem_rq_type,
4452                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4453         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4454         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4455         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4456         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4457         wq = MLX5_ADDR_OF(rqc, rqc, wq);
4458         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4459         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4460         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4461         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4462         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4463         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4464         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4465         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4466         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4467         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4468         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4469         err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4470         kvfree(in);
4471         return err;
4472 }
4473
4474 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4475                             struct ib_wq_init_attr *wq_init_attr,
4476                             struct mlx5_ib_create_wq *ucmd,
4477                             struct mlx5_ib_rwq *rwq)
4478 {
4479         /* Sanity check RQ size before proceeding */
4480         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4481                 return -EINVAL;
4482
4483         if (!ucmd->rq_wqe_count)
4484                 return -EINVAL;
4485
4486         rwq->wqe_count = ucmd->rq_wqe_count;
4487         rwq->wqe_shift = ucmd->rq_wqe_shift;
4488         rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4489         rwq->log_rq_stride = rwq->wqe_shift;
4490         rwq->log_rq_size = ilog2(rwq->wqe_count);
4491         return 0;
4492 }
4493
4494 static int prepare_user_rq(struct ib_pd *pd,
4495                            struct ib_wq_init_attr *init_attr,
4496                            struct ib_udata *udata,
4497                            struct mlx5_ib_rwq *rwq)
4498 {
4499         struct mlx5_ib_dev *dev = to_mdev(pd->device);
4500         struct mlx5_ib_create_wq ucmd = {};
4501         int err;
4502         size_t required_cmd_sz;
4503
4504         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4505         if (udata->inlen < required_cmd_sz) {
4506                 mlx5_ib_dbg(dev, "invalid inlen\n");
4507                 return -EINVAL;
4508         }
4509
4510         if (udata->inlen > sizeof(ucmd) &&
4511             !ib_is_udata_cleared(udata, sizeof(ucmd),
4512                                  udata->inlen - sizeof(ucmd))) {
4513                 mlx5_ib_dbg(dev, "inlen is not supported\n");
4514                 return -EOPNOTSUPP;
4515         }
4516
4517         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4518                 mlx5_ib_dbg(dev, "copy failed\n");
4519                 return -EFAULT;
4520         }
4521
4522         if (ucmd.comp_mask) {
4523                 mlx5_ib_dbg(dev, "invalid comp mask\n");
4524                 return -EOPNOTSUPP;
4525         }
4526
4527         if (ucmd.reserved) {
4528                 mlx5_ib_dbg(dev, "invalid reserved\n");
4529                 return -EOPNOTSUPP;
4530         }
4531
4532         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4533         if (err) {
4534                 mlx5_ib_dbg(dev, "err %d\n", err);
4535                 return err;
4536         }
4537
4538         err = create_user_rq(dev, pd, rwq, &ucmd);
4539         if (err) {
4540                 mlx5_ib_dbg(dev, "err %d\n", err);
4541                 if (err)
4542                         return err;
4543         }
4544
4545         rwq->user_index = ucmd.user_index;
4546         return 0;
4547 }
4548
4549 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4550                                 struct ib_wq_init_attr *init_attr,
4551                                 struct ib_udata *udata)
4552 {
4553         struct mlx5_ib_dev *dev;
4554         struct mlx5_ib_rwq *rwq;
4555         struct mlx5_ib_create_wq_resp resp = {};
4556         size_t min_resp_len;
4557         int err;
4558
4559         if (!udata)
4560                 return ERR_PTR(-ENOSYS);
4561
4562         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4563         if (udata->outlen && udata->outlen < min_resp_len)
4564                 return ERR_PTR(-EINVAL);
4565
4566         dev = to_mdev(pd->device);
4567         switch (init_attr->wq_type) {
4568         case IB_WQT_RQ:
4569                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4570                 if (!rwq)
4571                         return ERR_PTR(-ENOMEM);
4572                 err = prepare_user_rq(pd, init_attr, udata, rwq);
4573                 if (err)
4574                         goto err;
4575                 err = create_rq(rwq, pd, init_attr);
4576                 if (err)
4577                         goto err_user_rq;
4578                 break;
4579         default:
4580                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4581                             init_attr->wq_type);
4582                 return ERR_PTR(-EINVAL);
4583         }
4584
4585         rwq->ibwq.wq_num = rwq->rqn;
4586         rwq->ibwq.state = IB_WQS_RESET;
4587         if (udata->outlen) {
4588                 resp.response_length = offsetof(typeof(resp), response_length) +
4589                                 sizeof(resp.response_length);
4590                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4591                 if (err)
4592                         goto err_copy;
4593         }
4594
4595         return &rwq->ibwq;
4596
4597 err_copy:
4598         mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4599 err_user_rq:
4600         destroy_user_rq(pd, rwq);
4601 err:
4602         kfree(rwq);
4603         return ERR_PTR(err);
4604 }
4605
4606 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4607 {
4608         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4609         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4610
4611         mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4612         destroy_user_rq(wq->pd, rwq);
4613         kfree(rwq);
4614
4615         return 0;
4616 }
4617
4618 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4619                                                       struct ib_rwq_ind_table_init_attr *init_attr,
4620                                                       struct ib_udata *udata)
4621 {
4622         struct mlx5_ib_dev *dev = to_mdev(device);
4623         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4624         int sz = 1 << init_attr->log_ind_tbl_size;
4625         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4626         size_t min_resp_len;
4627         int inlen;
4628         int err;
4629         int i;
4630         u32 *in;
4631         void *rqtc;
4632
4633         if (udata->inlen > 0 &&
4634             !ib_is_udata_cleared(udata, 0,
4635                                  udata->inlen))
4636                 return ERR_PTR(-EOPNOTSUPP);
4637
4638         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4639         if (udata->outlen && udata->outlen < min_resp_len)
4640                 return ERR_PTR(-EINVAL);
4641
4642         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4643         if (!rwq_ind_tbl)
4644                 return ERR_PTR(-ENOMEM);
4645
4646         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4647         in = mlx5_vzalloc(inlen);
4648         if (!in) {
4649                 err = -ENOMEM;
4650                 goto err;
4651         }
4652
4653         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4654
4655         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4656         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4657
4658         for (i = 0; i < sz; i++)
4659                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4660
4661         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4662         kvfree(in);
4663
4664         if (err)
4665                 goto err;
4666
4667         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4668         if (udata->outlen) {
4669                 resp.response_length = offsetof(typeof(resp), response_length) +
4670                                         sizeof(resp.response_length);
4671                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4672                 if (err)
4673                         goto err_copy;
4674         }
4675
4676         return &rwq_ind_tbl->ib_rwq_ind_tbl;
4677
4678 err_copy:
4679         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4680 err:
4681         kfree(rwq_ind_tbl);
4682         return ERR_PTR(err);
4683 }
4684
4685 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4686 {
4687         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4688         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4689
4690         mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4691
4692         kfree(rwq_ind_tbl);
4693         return 0;
4694 }
4695
4696 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4697                       u32 wq_attr_mask, struct ib_udata *udata)
4698 {
4699         struct mlx5_ib_dev *dev = to_mdev(wq->device);
4700         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4701         struct mlx5_ib_modify_wq ucmd = {};
4702         size_t required_cmd_sz;
4703         int curr_wq_state;
4704         int wq_state;
4705         int inlen;
4706         int err;
4707         void *rqc;
4708         void *in;
4709
4710         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4711         if (udata->inlen < required_cmd_sz)
4712                 return -EINVAL;
4713
4714         if (udata->inlen > sizeof(ucmd) &&
4715             !ib_is_udata_cleared(udata, sizeof(ucmd),
4716                                  udata->inlen - sizeof(ucmd)))
4717                 return -EOPNOTSUPP;
4718
4719         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4720                 return -EFAULT;
4721
4722         if (ucmd.comp_mask || ucmd.reserved)
4723                 return -EOPNOTSUPP;
4724
4725         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4726         in = mlx5_vzalloc(inlen);
4727         if (!in)
4728                 return -ENOMEM;
4729
4730         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4731
4732         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4733                 wq_attr->curr_wq_state : wq->state;
4734         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4735                 wq_attr->wq_state : curr_wq_state;
4736         if (curr_wq_state == IB_WQS_ERR)
4737                 curr_wq_state = MLX5_RQC_STATE_ERR;
4738         if (wq_state == IB_WQS_ERR)
4739                 wq_state = MLX5_RQC_STATE_ERR;
4740         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4741         MLX5_SET(rqc, rqc, state, wq_state);
4742
4743         err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4744         kvfree(in);
4745         if (!err)
4746                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4747
4748         return err;
4749 }