drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/iommu.h>
  38 #include <net/addrconf.h>
  39 #include <linux/qed/qede_roce.h>
  40 #include <linux/qed/qed_chain.h>
  41 #include <linux/qed/qed_if.h>
  42 #include "qedr.h"
  43 #include "verbs.h"
  44 #include <rdma/qedr-abi.h>
  45
  46 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  47 MODULE_AUTHOR("QLogic Corporation");
  48 MODULE_LICENSE("Dual BSD/GPL");
  49 MODULE_VERSION(QEDR_MODULE_VERSION);
  50
  51 #define QEDR_WQ_MULTIPLIER_DFT  (3)
  52
  53 void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  54                             enum ib_event_type type)
  55 {
  56         struct ib_event ibev;
  57
  58         ibev.device = &dev->ibdev;
  59         ibev.element.port_num = port_num;
  60         ibev.event = type;
  61
  62         ib_dispatch_event(&ibev);
  63 }
  64
  65 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  66                                             u8 port_num)
  67 {
  68         return IB_LINK_LAYER_ETHERNET;
  69 }
  70
  71 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
  72                                 size_t str_len)
  73 {
  74         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  75         u32 fw_ver = (u32)qedr->attr.fw_ver;
  76
  77         snprintf(str, str_len, "%d. %d. %d. %d",
  78                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  79                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  80 }
  81
  82 static int qedr_register_device(struct qedr_dev *dev)
  83 {
  84         strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
  85
  86         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
  87         dev->ibdev.owner = THIS_MODULE;
  88         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
  89
  90         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
  91                                      QEDR_UVERBS(QUERY_DEVICE) |
  92                                      QEDR_UVERBS(QUERY_PORT) |
  93                                      QEDR_UVERBS(ALLOC_PD) |
  94                                      QEDR_UVERBS(DEALLOC_PD) |
  95                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
  96                                      QEDR_UVERBS(CREATE_CQ) |
  97                                      QEDR_UVERBS(RESIZE_CQ) |
  98                                      QEDR_UVERBS(DESTROY_CQ) |
  99                                      QEDR_UVERBS(REQ_NOTIFY_CQ) |
 100                                      QEDR_UVERBS(CREATE_QP) |
 101                                      QEDR_UVERBS(MODIFY_QP) |
 102                                      QEDR_UVERBS(QUERY_QP) |
 103                                      QEDR_UVERBS(DESTROY_QP);
 104
 105         dev->ibdev.phys_port_cnt = 1;
 106         dev->ibdev.num_comp_vectors = dev->num_cnq;
 107         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 108
 109         dev->ibdev.query_device = qedr_query_device;
 110         dev->ibdev.query_port = qedr_query_port;
 111         dev->ibdev.modify_port = qedr_modify_port;
 112
 113         dev->ibdev.query_gid = qedr_query_gid;
 114         dev->ibdev.add_gid = qedr_add_gid;
 115         dev->ibdev.del_gid = qedr_del_gid;
 116
 117         dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
 118         dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
 119         dev->ibdev.mmap = qedr_mmap;
 120
 121         dev->ibdev.alloc_pd = qedr_alloc_pd;
 122         dev->ibdev.dealloc_pd = qedr_dealloc_pd;
 123
 124         dev->ibdev.create_cq = qedr_create_cq;
 125         dev->ibdev.destroy_cq = qedr_destroy_cq;
 126         dev->ibdev.resize_cq = qedr_resize_cq;
 127         dev->ibdev.req_notify_cq = qedr_arm_cq;
 128
 129         dev->ibdev.create_qp = qedr_create_qp;
 130         dev->ibdev.modify_qp = qedr_modify_qp;
 131         dev->ibdev.query_qp = qedr_query_qp;
 132         dev->ibdev.destroy_qp = qedr_destroy_qp;
 133
 134         dev->ibdev.query_pkey = qedr_query_pkey;
 135
 136         dev->ibdev.dma_device = &dev->pdev->dev;
 137
 138         dev->ibdev.get_link_layer = qedr_link_layer;
 139         dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
 140
 141         return 0;
 142 }
 143
 144 /* This function allocates fast-path status block memory */
 145 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 146                              struct qed_sb_info *sb_info, u16 sb_id)
 147 {
 148         struct status_block *sb_virt;
 149         dma_addr_t sb_phys;
 150         int rc;
 151
 152         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 153                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 154         if (!sb_virt)
 155                 return -ENOMEM;
 156
 157         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 158                                        sb_virt, sb_phys, sb_id,
 159                                        QED_SB_TYPE_CNQ);
 160         if (rc) {
 161                 pr_err("Status block initialization failed\n");
 162                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 163                                   sb_virt, sb_phys);
 164                 return rc;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static void qedr_free_mem_sb(struct qedr_dev *dev,
 171                              struct qed_sb_info *sb_info, int sb_id)
 172 {
 173         if (sb_info->sb_virt) {
 174                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 175                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 176                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 177         }
 178 }
 179
 180 static void qedr_free_resources(struct qedr_dev *dev)
 181 {
 182         int i;
 183
 184         for (i = 0; i < dev->num_cnq; i++) {
 185                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 186                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 187         }
 188
 189         kfree(dev->cnq_array);
 190         kfree(dev->sb_array);
 191         kfree(dev->sgid_tbl);
 192 }
 193
 194 static int qedr_alloc_resources(struct qedr_dev *dev)
 195 {
 196         struct qedr_cnq *cnq;
 197         __le16 *cons_pi;
 198         u16 n_entries;
 199         int i, rc;
 200
 201         dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
 202                                 QEDR_MAX_SGID, GFP_KERNEL);
 203         if (!dev->sgid_tbl)
 204                 return -ENOMEM;
 205
 206         spin_lock_init(&dev->sgid_lock);
 207
 208         /* Allocate Status blocks for CNQ */
 209         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 210                                 GFP_KERNEL);
 211         if (!dev->sb_array) {
 212                 rc = -ENOMEM;
 213                 goto err1;
 214         }
 215
 216         dev->cnq_array = kcalloc(dev->num_cnq,
 217                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 218         if (!dev->cnq_array) {
 219                 rc = -ENOMEM;
 220                 goto err2;
 221         }
 222
 223         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 224
 225         /* Allocate CNQ PBLs */
 226         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 227         for (i = 0; i < dev->num_cnq; i++) {
 228                 cnq = &dev->cnq_array[i];
 229
 230                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 231                                        dev->sb_start + i);
 232                 if (rc)
 233                         goto err3;
 234
 235                 rc = dev->ops->common->chain_alloc(dev->cdev,
 236                                                    QED_CHAIN_USE_TO_CONSUME,
 237                                                    QED_CHAIN_MODE_PBL,
 238                                                    QED_CHAIN_CNT_TYPE_U16,
 239                                                    n_entries,
 240                                                    sizeof(struct regpair *),
 241                                                    &cnq->pbl);
 242                 if (rc)
 243                         goto err4;
 244
 245                 cnq->dev = dev;
 246                 cnq->sb = &dev->sb_array[i];
 247                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 248                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 249                 cnq->index = i;
 250                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 251
 252                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 253                          i, qed_chain_get_cons_idx(&cnq->pbl));
 254         }
 255
 256         return 0;
 257 err4:
 258         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 259 err3:
 260         for (--i; i >= 0; i--) {
 261                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 262                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 263         }
 264         kfree(dev->cnq_array);
 265 err2:
 266         kfree(dev->sb_array);
 267 err1:
 268         kfree(dev->sgid_tbl);
 269         return rc;
 270 }
 271
 272 /* QEDR sysfs interface */
 273 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
 274                         char *buf)
 275 {
 276         struct qedr_dev *dev = dev_get_drvdata(device);
 277
 278         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 279 }
 280
 281 static ssize_t show_hca_type(struct device *device,
 282                              struct device_attribute *attr, char *buf)
 283 {
 284         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 285 }
 286
 287 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
 288 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
 289
 290 static struct device_attribute *qedr_attributes[] = {
 291         &dev_attr_hw_rev,
 292         &dev_attr_hca_type
 293 };
 294
 295 static void qedr_remove_sysfiles(struct qedr_dev *dev)
 296 {
 297         int i;
 298
 299         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 300                 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
 301 }
 302
 303 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 304 {
 305         struct pci_dev *bridge;
 306         u32 val;
 307
 308         dev->atomic_cap = IB_ATOMIC_NONE;
 309
 310         bridge = pdev->bus->self;
 311         if (!bridge)
 312                 return;
 313
 314         /* Check whether we are connected directly or via a switch */
 315         while (bridge && bridge->bus->parent) {
 316                 DP_DEBUG(dev, QEDR_MSG_INIT,
 317                          "Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
 318                          bridge->bus->number, bridge->bus->primary);
 319                 /* Need to check Atomic Op Routing Supported all the way to
 320                  * root complex.
 321                  */
 322                 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 323                 if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
 324                         pcie_capability_clear_word(pdev,
 325                                                    PCI_EXP_DEVCTL2,
 326                                                    PCI_EXP_DEVCTL2_ATOMIC_REQ);
 327                         return;
 328                 }
 329                 bridge = bridge->bus->parent->self;
 330         }
 331         bridge = pdev->bus->self;
 332
 333         /* according to bridge capability */
 334         pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 335         if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
 336                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
 337                                          PCI_EXP_DEVCTL2_ATOMIC_REQ);
 338                 dev->atomic_cap = IB_ATOMIC_GLOB;
 339         } else {
 340                 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
 341                                            PCI_EXP_DEVCTL2_ATOMIC_REQ);
 342         }
 343 }
 344
 345 static const struct qed_rdma_ops *qed_ops;
 346
 347 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 348
 349 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 350 {
 351         u16 hw_comp_cons, sw_comp_cons;
 352         struct qedr_cnq *cnq = handle;
 353         struct regpair *cq_handle;
 354         struct qedr_cq *cq;
 355
 356         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 357
 358         qed_sb_update_sb_idx(cnq->sb);
 359
 360         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 361         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 362
 363         /* Align protocol-index and chain reads */
 364         rmb();
 365
 366         while (sw_comp_cons != hw_comp_cons) {
 367                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 368                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 369                                 cq_handle->lo);
 370
 371                 if (cq == NULL) {
 372                         DP_ERR(cnq->dev,
 373                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 374                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 375                                hw_comp_cons);
 376
 377                         break;
 378                 }
 379
 380                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 381                         DP_ERR(cnq->dev,
 382                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 383                                cq_handle->hi, cq_handle->lo, cq);
 384                         break;
 385                 }
 386
 387                 cq->arm_flags = 0;
 388
 389                 if (cq->ibcq.comp_handler)
 390                         (*cq->ibcq.comp_handler)
 391                                 (&cq->ibcq, cq->ibcq.cq_context);
 392
 393                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 394
 395                 cnq->n_comp++;
 396
 397         }
 398
 399         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 400                                       sw_comp_cons);
 401
 402         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 403
 404         return IRQ_HANDLED;
 405 }
 406
 407 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 408 {
 409         u32 vector;
 410         int i;
 411
 412         for (i = 0; i < dev->int_info.used_cnt; i++) {
 413                 if (dev->int_info.msix_cnt) {
 414                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 415                         synchronize_irq(vector);
 416                         free_irq(vector, &dev->cnq_array[i]);
 417                 }
 418         }
 419
 420         dev->int_info.used_cnt = 0;
 421 }
 422
 423 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 424 {
 425         int i, rc = 0;
 426
 427         if (dev->num_cnq > dev->int_info.msix_cnt) {
 428                 DP_ERR(dev,
 429                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 430                        dev->num_cnq, dev->int_info.msix_cnt);
 431                 return -EINVAL;
 432         }
 433
 434         for (i = 0; i < dev->num_cnq; i++) {
 435                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 436                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 437                                  &dev->cnq_array[i]);
 438                 if (rc) {
 439                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 440                         qedr_sync_free_irqs(dev);
 441                 } else {
 442                         DP_DEBUG(dev, QEDR_MSG_INIT,
 443                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 444                                  dev->cnq_array[i].name, i,
 445                                  &dev->cnq_array[i]);
 446                         dev->int_info.used_cnt++;
 447                 }
 448         }
 449
 450         return rc;
 451 }
 452
 453 static int qedr_setup_irqs(struct qedr_dev *dev)
 454 {
 455         int rc;
 456
 457         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 458
 459         /* Learn Interrupt configuration */
 460         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 461         if (rc < 0)
 462                 return rc;
 463
 464         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 465         if (rc) {
 466                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 467                 return rc;
 468         }
 469
 470         if (dev->int_info.msix_cnt) {
 471                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 472                          dev->int_info.msix_cnt);
 473                 rc = qedr_req_msix_irqs(dev);
 474                 if (rc)
 475                         return rc;
 476         }
 477
 478         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 479
 480         return 0;
 481 }
 482
 483 static int qedr_set_device_attr(struct qedr_dev *dev)
 484 {
 485         struct qed_rdma_device *qed_attr;
 486         struct qedr_device_attr *attr;
 487         u32 page_size;
 488
 489         /* Part 1 - query core capabilities */
 490         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 491
 492         /* Part 2 - check capabilities */
 493         page_size = ~dev->attr.page_size_caps + 1;
 494         if (page_size > PAGE_SIZE) {
 495                 DP_ERR(dev,
 496                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 497                        PAGE_SIZE, page_size);
 498                 return -ENODEV;
 499         }
 500
 501         /* Part 3 - copy and update capabilities */
 502         attr = &dev->attr;
 503         attr->vendor_id = qed_attr->vendor_id;
 504         attr->vendor_part_id = qed_attr->vendor_part_id;
 505         attr->hw_ver = qed_attr->hw_ver;
 506         attr->fw_ver = qed_attr->fw_ver;
 507         attr->node_guid = qed_attr->node_guid;
 508         attr->sys_image_guid = qed_attr->sys_image_guid;
 509         attr->max_cnq = qed_attr->max_cnq;
 510         attr->max_sge = qed_attr->max_sge;
 511         attr->max_inline = qed_attr->max_inline;
 512         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 513         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 514         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 515         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 516         attr->max_dev_resp_rd_atomic_resc =
 517             qed_attr->max_dev_resp_rd_atomic_resc;
 518         attr->max_cq = qed_attr->max_cq;
 519         attr->max_qp = qed_attr->max_qp;
 520         attr->max_mr = qed_attr->max_mr;
 521         attr->max_mr_size = qed_attr->max_mr_size;
 522         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 523         attr->max_mw = qed_attr->max_mw;
 524         attr->max_fmr = qed_attr->max_fmr;
 525         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 526         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 527         attr->max_pd = qed_attr->max_pd;
 528         attr->max_ah = qed_attr->max_ah;
 529         attr->max_pkey = qed_attr->max_pkey;
 530         attr->max_srq = qed_attr->max_srq;
 531         attr->max_srq_wr = qed_attr->max_srq_wr;
 532         attr->dev_caps = qed_attr->dev_caps;
 533         attr->page_size_caps = qed_attr->page_size_caps;
 534         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 535         attr->reserved_lkey = qed_attr->reserved_lkey;
 536         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 537         attr->max_stats_queues = qed_attr->max_stats_queues;
 538
 539         return 0;
 540 }
 541
 542 static int qedr_init_hw(struct qedr_dev *dev)
 543 {
 544         struct qed_rdma_add_user_out_params out_params;
 545         struct qed_rdma_start_in_params *in_params;
 546         struct qed_rdma_cnq_params *cur_pbl;
 547         struct qed_rdma_events events;
 548         dma_addr_t p_phys_table;
 549         u32 page_cnt;
 550         int rc = 0;
 551         int i;
 552
 553         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 554         if (!in_params) {
 555                 rc = -ENOMEM;
 556                 goto out;
 557         }
 558
 559         in_params->desired_cnq = dev->num_cnq;
 560         for (i = 0; i < dev->num_cnq; i++) {
 561                 cur_pbl = &in_params->cnq_pbl_list[i];
 562
 563                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 564                 cur_pbl->num_pbl_pages = page_cnt;
 565
 566                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 567                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 568         }
 569
 570         events.context = dev;
 571
 572         in_params->events = &events;
 573         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 574         in_params->max_mtu = dev->ndev->mtu;
 575         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 576
 577         rc = dev->ops->rdma_init(dev->cdev, in_params);
 578         if (rc)
 579                 goto out;
 580
 581         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 582         if (rc)
 583                 goto out;
 584
 585         dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
 586         dev->db_phys_addr = out_params.dpi_phys_addr;
 587         dev->db_size = out_params.dpi_size;
 588         dev->dpi = out_params.dpi;
 589
 590         rc = qedr_set_device_attr(dev);
 591 out:
 592         kfree(in_params);
 593         if (rc)
 594                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 595
 596         return rc;
 597 }
 598
 599 void qedr_stop_hw(struct qedr_dev *dev)
 600 {
 601         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 602         dev->ops->rdma_stop(dev->rdma_ctx);
 603 }
 604
 605 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 606                                  struct net_device *ndev)
 607 {
 608         struct qed_dev_rdma_info dev_info;
 609         struct qedr_dev *dev;
 610         int rc = 0, i;
 611
 612         dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
 613         if (!dev) {
 614                 pr_err("Unable to allocate ib device\n");
 615                 return NULL;
 616         }
 617
 618         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 619
 620         dev->pdev = pdev;
 621         dev->ndev = ndev;
 622         dev->cdev = cdev;
 623
 624         qed_ops = qed_get_rdma_ops();
 625         if (!qed_ops) {
 626                 DP_ERR(dev, "Failed to get qed roce operations\n");
 627                 goto init_err;
 628         }
 629
 630         dev->ops = qed_ops;
 631         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 632         if (rc)
 633                 goto init_err;
 634
 635         dev->num_hwfns = dev_info.common.num_hwfns;
 636         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 637
 638         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 639         if (!dev->num_cnq) {
 640                 DP_ERR(dev, "not enough CNQ resources.\n");
 641                 goto init_err;
 642         }
 643
 644         dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
 645
 646         qedr_pci_set_atomic(dev, pdev);
 647
 648         rc = qedr_alloc_resources(dev);
 649         if (rc)
 650                 goto init_err;
 651
 652         rc = qedr_init_hw(dev);
 653         if (rc)
 654                 goto alloc_err;
 655
 656         rc = qedr_setup_irqs(dev);
 657         if (rc)
 658                 goto irq_err;
 659
 660         rc = qedr_register_device(dev);
 661         if (rc) {
 662                 DP_ERR(dev, "Unable to allocate register device\n");
 663                 goto reg_err;
 664         }
 665
 666         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 667                 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
 668                         goto reg_err;
 669
 670         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 671         return dev;
 672
 673 reg_err:
 674         qedr_sync_free_irqs(dev);
 675 irq_err:
 676         qedr_stop_hw(dev);
 677 alloc_err:
 678         qedr_free_resources(dev);
 679 init_err:
 680         ib_dealloc_device(&dev->ibdev);
 681         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 682
 683         return NULL;
 684 }
 685
 686 static void qedr_remove(struct qedr_dev *dev)
 687 {
 688         /* First unregister with stack to stop all the active traffic
 689          * of the registered clients.
 690          */
 691         qedr_remove_sysfiles(dev);
 692
 693         qedr_stop_hw(dev);
 694         qedr_sync_free_irqs(dev);
 695         qedr_free_resources(dev);
 696         ib_dealloc_device(&dev->ibdev);
 697 }
 698
 699 static int qedr_close(struct qedr_dev *dev)
 700 {
 701         qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
 702
 703         return 0;
 704 }
 705
 706 static void qedr_shutdown(struct qedr_dev *dev)
 707 {
 708         qedr_close(dev);
 709         qedr_remove(dev);
 710 }
 711
 712 /* event handling via NIC driver ensures that all the NIC specific
 713  * initialization done before RoCE driver notifies
 714  * event to stack.
 715  */
 716 static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
 717 {
 718         switch (event) {
 719         case QEDE_UP:
 720                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
 721                 break;
 722         case QEDE_DOWN:
 723                 qedr_close(dev);
 724                 break;
 725         case QEDE_CLOSE:
 726                 qedr_shutdown(dev);
 727                 break;
 728         case QEDE_CHANGE_ADDR:
 729                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
 730                 break;
 731         default:
 732                 pr_err("Event not supported\n");
 733         }
 734 }
 735
 736 static struct qedr_driver qedr_drv = {
 737         .name = "qedr_driver",
 738         .add = qedr_add,
 739         .remove = qedr_remove,
 740         .notify = qedr_notify,
 741 };
 742
 743 static int __init qedr_init_module(void)
 744 {
 745         return qede_roce_register_driver(&qedr_drv);
 746 }
 747
 748 static void __exit qedr_exit_module(void)
 749 {
 750         qede_roce_unregister_driver(&qedr_drv);
 751 }
 752
 753 module_init(qedr_init_module);
 754 module_exit(qedr_exit_module);