1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <linux/qed/qed_if.h>
38 #include <linux/qed/qed_chain.h>
39 #include <linux/qed/qed_roce_if.h>
40 #include <linux/qed/qede_roce.h>
43 #define QEDR_MODULE_VERSION "8.10.10.0"
44 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
45 #define DP_NAME(dev) ((dev)->ibdev.name)
47 #define DP_DEBUG(dev, module, fmt, ...) \
48 pr_debug("(%s) " module ": " fmt, \
49 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
51 #define QEDR_MSG_INIT "INIT"
52 #define QEDR_MSG_MISC "MISC"
53 #define QEDR_MSG_CQ " CQ"
54 #define QEDR_MSG_MR " MR"
55 #define QEDR_MSG_RQ " RQ"
56 #define QEDR_MSG_SQ " SQ"
57 #define QEDR_MSG_QP " QP"
59 #define QEDR_CQ_MAGIC_NUMBER (0x11223344)
66 struct qed_sb_info *sb;
73 #define QEDR_MAX_SGID 128
75 struct qedr_device_attr {
87 u8 max_qp_resp_rd_atomic_resc;
88 u8 max_qp_req_rd_atomic_resc;
89 u64 max_dev_resp_rd_atomic_resc;
97 u32 max_mr_mw_fmr_pbl;
98 u64 max_mr_mw_fmr_size;
111 u32 bad_pkey_counter;
112 struct qed_rdma_events events;
116 struct ib_device ibdev;
117 struct qed_dev *cdev;
118 struct pci_dev *pdev;
119 struct net_device *ndev;
121 enum ib_atomic_cap atomic_cap;
124 struct qedr_device_attr attr;
126 const struct qed_rdma_ops *ops;
127 struct qed_int_info int_info;
129 struct qed_sb_info *sb_array;
130 struct qedr_cnq *cnq_array;
134 void __iomem *db_addr;
139 union ib_gid *sgid_tbl;
141 /* Lock for sgid table */
142 spinlock_t sgid_lock;
150 u8 gsi_ll2_mac_address[ETH_ALEN];
153 #define QEDR_MAX_SQ_PBL (0x8000)
154 #define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
155 #define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
156 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
157 QEDR_SQE_ELEMENT_SIZE)
158 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
159 QEDR_SQE_ELEMENT_SIZE)
160 #define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
161 (RDMA_RING_PAGE_SIZE) / \
162 (QEDR_SQE_ELEMENT_SIZE) /\
163 (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
165 #define QEDR_MAX_RQ_PBL (0x2000)
166 #define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
167 #define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
168 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
169 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
170 QEDR_RQE_ELEMENT_SIZE)
171 #define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
172 (RDMA_RING_PAGE_SIZE) / \
173 (QEDR_RQE_ELEMENT_SIZE) /\
174 (QEDR_MAX_RQE_ELEMENTS_PER_RQE))
176 #define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
177 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
178 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
180 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
181 (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
183 #define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
185 #define QEDR_MAX_PORT (1)
187 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
189 #define QEDR_ROCE_PKEY_MAX 1
190 #define QEDR_ROCE_PKEY_TABLE_LEN 1
191 #define QEDR_ROCE_PKEY_DEFAULT 0xffff
194 struct list_head list_entry;
199 struct qedr_ucontext {
200 struct ib_ucontext ibucontext;
201 struct qedr_dev *dev;
208 struct list_head mm_head;
210 /* Lock to protect mm list */
211 struct mutex mm_list_lock;
215 struct rdma_pwm_val32_data data;
225 struct qedr_pbl_info {
234 struct ib_umem *umem;
235 struct qedr_pbl_info pbl_info;
236 struct qedr_pbl *pbl_tbl;
244 enum qedr_cq_type cq_type;
249 /* Lock to protect multiplem CQ's */
252 struct qed_chain pbl;
254 void __iomem *db_addr;
258 union rdma_cqe *latest_cqe;
259 union rdma_cqe *toggle_cqe;
269 struct qedr_ucontext *uctx;
277 struct list_head entry;
281 struct rdma_pwm_val16_data data;
285 struct qedr_qp_hwq_info {
287 struct qed_chain pbl;
299 union db_prod32 db_data;
302 #define QEDR_INC_SW_IDX(p_info, index) \
304 p_info->index = (p_info->index + 1) & \
305 qed_chain_get_capacity(p_info->pbl) \
308 enum qedr_qp_err_bitmap {
309 QEDR_QP_ERR_SQ_FULL = 1,
310 QEDR_QP_ERR_RQ_FULL = 2,
311 QEDR_QP_ERR_BAD_SR = 4,
312 QEDR_QP_ERR_BAD_RR = 8,
313 QEDR_QP_ERR_SQ_PBL_FULL = 16,
314 QEDR_QP_ERR_RQ_PBL_FULL = 32,
318 struct ib_qp ibqp; /* must be first */
319 struct qedr_dev *dev;
321 struct qedr_qp_hwq_info sq;
322 struct qedr_qp_hwq_info rq;
328 struct qedr_cq *sq_cq;
329 struct qedr_cq *rq_cq;
330 struct qedr_srq *srq;
331 enum qed_roce_qp_state state;
334 enum ib_qp_type qp_type;
335 struct qed_rdma_qp *qed_qp;
345 /* Relevant to qps created from kernel space only (ULPs) */
354 enum ib_wc_opcode opcode;
358 dma_addr_t icrc_mapping;
366 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
373 /* Relevant to qps created from user space only (applications) */
374 struct qedr_userq usq;
375 struct qedr_userq urq;
380 struct ib_ah_attr attr;
391 struct qedr_pbl *pbl_table;
392 struct qedr_pbl_info pbl_info;
393 struct list_head free_pbl_list;
394 struct list_head inuse_pbl_list;
396 u32 completed_handled;
401 struct ib_umem *umem;
403 struct qed_rdma_register_tid_in_params hw_mr;
404 enum qedr_mr_type type;
406 struct qedr_dev *dev;
413 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
415 #define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
416 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
417 #define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
418 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
419 #define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM | QEDR_RESP_RDMA)
421 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
423 info->cons = (info->cons + 1) % info->max_wr;
427 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
429 info->prod = (info->prod + 1) % info->max_wr;
432 static inline int qedr_get_dmac(struct qedr_dev *dev,
433 struct ib_ah_attr *ah_attr, u8 *mac_addr)
435 union ib_gid zero_sgid = { { 0 } };
438 if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) {
439 DP_ERR(dev, "Local port GID not supported\n");
440 eth_zero_addr(mac_addr);
444 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
445 ether_addr_copy(mac_addr, ah_attr->dmac);
451 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
453 return container_of(ibucontext, struct qedr_ucontext, ibucontext);
456 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
458 return container_of(ibdev, struct qedr_dev, ibdev);
461 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
463 return container_of(ibpd, struct qedr_pd, ibpd);
466 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
468 return container_of(ibcq, struct qedr_cq, ibcq);
471 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
473 return container_of(ibqp, struct qedr_qp, ibqp);
476 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
478 return container_of(ibmr, struct qedr_mr, ibmr);