drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_mtd.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36 #include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  83
  84 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  86 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  90
  91 #define GPMC_CS0_OFFSET         0x60
  92 #define GPMC_CS_SIZE            0x30
  93 #define GPMC_BCH_SIZE           0x10
  94
  95 #define GPMC_MEM_END            0x3FFFFFFF
  96
  97 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  98 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  99
 100 #define CS_NUM_SHIFT            24
 101 #define ENABLE_PREFETCH         (0x1 << 7)
 102 #define DMA_MPU_MODE            2
 103
 104 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 105 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 106
 107 #define GPMC_HAS_WR_ACCESS              0x1
 108 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 109 #define GPMC_HAS_MUX_AAD                0x4
 110
 111 #define GPMC_NR_WAITPINS                4
 112
 113 #define GPMC_CS_CONFIG1         0x00
 114 #define GPMC_CS_CONFIG2         0x04
 115 #define GPMC_CS_CONFIG3         0x08
 116 #define GPMC_CS_CONFIG4         0x0c
 117 #define GPMC_CS_CONFIG5         0x10
 118 #define GPMC_CS_CONFIG6         0x14
 119 #define GPMC_CS_CONFIG7         0x18
 120 #define GPMC_CS_NAND_COMMAND    0x1c
 121 #define GPMC_CS_NAND_ADDRESS    0x20
 122 #define GPMC_CS_NAND_DATA       0x24
 123
 124 /* Control Commands */
 125 #define GPMC_CONFIG_RDY_BSY     0x00000001
 126 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 127 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 128 #define GPMC_SET_IRQ_STATUS     0x00000004
 129
 130 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 131 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 132 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 133 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 134 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 135 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 136 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 137 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 138 /** CLKACTIVATIONTIME Max Ticks */
 139 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 140 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 141 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 142 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 143 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 144 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 145 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 146 /** WAITMONITORINGTIME Max Ticks */
 147 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 148 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 149 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 150 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 151 /** DEVICESIZE Max Value */
 152 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 153 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 154 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 155 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 156 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 157 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 158 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 159 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 160 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 161 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 162
 163 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 164 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 165 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 166 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 167 /* All CONFIG7 bits except reserved bits */
 168 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 169                                          GPMC_CONFIG7_CSVALID_MASK |     \
 170                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 171
 172 #define GPMC_DEVICETYPE_NOR             0
 173 #define GPMC_DEVICETYPE_NAND            2
 174 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 175 #define WR_RD_PIN_MONITORING            0x00600000
 176
 177 #define GPMC_ENABLE_IRQ         0x0000000d
 178
 179 /* ECC commands */
 180 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 181 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 182 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 183
 184 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 185  */
 186 #define GPMC_NR_IRQ             2
 187
 188 enum gpmc_clk_domain {
 189         GPMC_CD_FCLK,
 190         GPMC_CD_CLK
 191 };
 192
 193 struct gpmc_cs_data {
 194         const char *name;
 195
 196 #define GPMC_CS_RESERVED        (1 << 0)
 197         u32 flags;
 198
 199         struct resource mem;
 200 };
 201
 202 struct gpmc_client_irq  {
 203         unsigned                irq;
 204         u32                     bitmask;
 205 };
 206
 207 /* Structure to save gpmc cs context */
 208 struct gpmc_cs_config {
 209         u32 config1;
 210         u32 config2;
 211         u32 config3;
 212         u32 config4;
 213         u32 config5;
 214         u32 config6;
 215         u32 config7;
 216         int is_valid;
 217 };
 218
 219 /*
 220  * Structure to save/restore gpmc context
 221  * to support core off on OMAP3
 222  */
 223 struct omap3_gpmc_regs {
 224         u32 sysconfig;
 225         u32 irqenable;
 226         u32 timeout_ctrl;
 227         u32 config;
 228         u32 prefetch_config1;
 229         u32 prefetch_config2;
 230         u32 prefetch_control;
 231         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 232 };
 233
 234 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 235 static struct irq_chip gpmc_irq_chip;
 236 static int gpmc_irq_start;
 237
 238 static struct resource  gpmc_mem_root;
 239 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 240 static DEFINE_SPINLOCK(gpmc_mem_lock);
 241 /* Define chip-selects as reserved by default until probe completes */
 242 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 243 static unsigned int gpmc_nr_waitpins;
 244 static struct device *gpmc_dev;
 245 static int gpmc_irq;
 246 static resource_size_t phys_base, mem_size;
 247 static unsigned gpmc_capability;
 248 static void __iomem *gpmc_base;
 249
 250 static struct clk *gpmc_l3_clk;
 251
 252 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 253
 254 static void gpmc_write_reg(int idx, u32 val)
 255 {
 256         writel_relaxed(val, gpmc_base + idx);
 257 }
 258
 259 static u32 gpmc_read_reg(int idx)
 260 {
 261         return readl_relaxed(gpmc_base + idx);
 262 }
 263
 264 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 265 {
 266         void __iomem *reg_addr;
 267
 268         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 269         writel_relaxed(val, reg_addr);
 270 }
 271
 272 static u32 gpmc_cs_read_reg(int cs, int idx)
 273 {
 274         void __iomem *reg_addr;
 275
 276         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 277         return readl_relaxed(reg_addr);
 278 }
 279
 280 /* TODO: Add support for gpmc_fck to clock framework and use it */
 281 static unsigned long gpmc_get_fclk_period(void)
 282 {
 283         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 284
 285         rate /= 1000;
 286         rate = 1000000000 / rate;       /* In picoseconds */
 287
 288         return rate;
 289 }
 290
 291 /**
 292  * gpmc_get_clk_period - get period of selected clock domain in ps
 293  * @cs Chip Select Region.
 294  * @cd Clock Domain.
 295  *
 296  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 297  * prior to calling this function with GPMC_CD_CLK.
 298  */
 299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 300 {
 301
 302         unsigned long tick_ps = gpmc_get_fclk_period();
 303         u32 l;
 304         int div;
 305
 306         switch (cd) {
 307         case GPMC_CD_CLK:
 308                 /* get current clk divider */
 309                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 310                 div = (l & 0x03) + 1;
 311                 /* get GPMC_CLK period */
 312                 tick_ps *= div;
 313                 break;
 314         case GPMC_CD_FCLK:
 315                 /* FALL-THROUGH */
 316         default:
 317                 break;
 318         }
 319
 320         return tick_ps;
 321
 322 }
 323
 324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 325                                          enum gpmc_clk_domain cd)
 326 {
 327         unsigned long tick_ps;
 328
 329         /* Calculate in picosecs to yield more exact results */
 330         tick_ps = gpmc_get_clk_period(cs, cd);
 331
 332         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 333 }
 334
 335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 336 {
 337         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 338 }
 339
 340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 341 {
 342         unsigned long tick_ps;
 343
 344         /* Calculate in picosecs to yield more exact results */
 345         tick_ps = gpmc_get_fclk_period();
 346
 347         return (time_ps + tick_ps - 1) / tick_ps;
 348 }
 349
 350 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 351                                   enum gpmc_clk_domain cd)
 352 {
 353         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 354 }
 355
 356 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 357 {
 358         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 359 }
 360
 361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 362 {
 363         return ticks * gpmc_get_fclk_period();
 364 }
 365
 366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 367 {
 368         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 369
 370         return ticks * gpmc_get_fclk_period();
 371 }
 372
 373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 374 {
 375         u32 l;
 376
 377         l = gpmc_cs_read_reg(cs, reg);
 378         if (value)
 379                 l |= mask;
 380         else
 381                 l &= ~mask;
 382         gpmc_cs_write_reg(cs, reg, l);
 383 }
 384
 385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 386 {
 387         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 388                            GPMC_CONFIG1_TIME_PARA_GRAN,
 389                            p->time_para_granularity);
 390         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 391                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 393                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 395                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 397                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 399                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 400                            p->cycle2cyclesamecsen);
 401         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 402                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 403                            p->cycle2cyclediffcsen);
 404 }
 405
 406 #ifdef CONFIG_OMAP_GPMC_DEBUG
 407 /**
 408  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 409  * @cs:      Chip Select Region
 410  * @reg:     GPMC_CS_CONFIGn register offset.
 411  * @st_bit:  Start Bit
 412  * @end_bit: End Bit. Must be >= @st_bit.
 413  * @ma:x     Maximum parameter value (before optional @shift).
 414  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 415  * @name:    DTS node name, w/o "gpmc,"
 416  * @cd:      Clock Domain of timing parameter.
 417  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 418  * @raw:     Raw Format Option.
 419  *           raw format:  gpmc,name = <value>
 420  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 421  *           Where x ns -- y ns result in the same tick value.
 422  *           When @max is exceeded, "invalid" is printed inside comment.
 423  * @noval:   Parameter values equal to 0 are not printed.
 424  * @return:  Specified timing parameter (after optional @shift).
 425  *
 426  */
 427 static int get_gpmc_timing_reg(
 428         /* timing specifiers */
 429         int cs, int reg, int st_bit, int end_bit, int max,
 430         const char *name, const enum gpmc_clk_domain cd,
 431         /* value transform */
 432         int shift,
 433         /* format specifiers */
 434         bool raw, bool noval)
 435 {
 436         u32 l;
 437         int nr_bits;
 438         int mask;
 439         bool invalid;
 440
 441         l = gpmc_cs_read_reg(cs, reg);
 442         nr_bits = end_bit - st_bit + 1;
 443         mask = (1 << nr_bits) - 1;
 444         l = (l >> st_bit) & mask;
 445         if (!max)
 446                 max = mask;
 447         invalid = l > max;
 448         if (shift)
 449                 l = (shift << l);
 450         if (noval && (l == 0))
 451                 return 0;
 452         if (!raw) {
 453                 /* DTS tick format for timings in ns */
 454                 unsigned int time_ns;
 455                 unsigned int time_ns_min = 0;
 456
 457                 if (l)
 458                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 459                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 460                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 461                         name, time_ns, time_ns_min, time_ns, l,
 462                         invalid ? "; invalid " : " ");
 463         } else {
 464                 /* raw format */
 465                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 466                         invalid ? " /* invalid */" : "");
 467         }
 468
 469         return l;
 470 }
 471
 472 #define GPMC_PRINT_CONFIG(cs, config) \
 473         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 474                 gpmc_cs_read_reg(cs, config))
 475 #define GPMC_GET_RAW(reg, st, end, field) \
 476         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 483 #define GPMC_GET_TICKS(reg, st, end, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 489
 490 static void gpmc_show_regs(int cs, const char *desc)
 491 {
 492         pr_info("gpmc cs%i %s:\n", cs, desc);
 493         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 499 }
 500
 501 /*
 502  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 503  * see commit c9fb809.
 504  */
 505 static void gpmc_cs_show_timings(int cs, const char *desc)
 506 {
 507         gpmc_show_regs(cs, desc);
 508
 509         pr_info("gpmc cs%i access configuration:\n", cs);
 510         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 511         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 512         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 513                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 514         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 515         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 517         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 518                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 519                                "burst-length");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 521         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 525
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 527
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 532
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 535
 536         pr_info("gpmc cs%i timings configuration:\n", cs);
 537         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 540
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 544         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 545                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 546                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 547                                 "adv-aad-mux-rd-off-ns");
 548                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 549                                 "adv-aad-mux-wr-off-ns");
 550         }
 551
 552         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 553         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 554         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 555                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 556                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 557         }
 558         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 559         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 560
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 564
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 566
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 568         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 569
 570         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 571                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 572                               "wait-monitoring-ns", GPMC_CD_CLK);
 573         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 574                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 575                               "clk-activation-ns", GPMC_CD_FCLK);
 576
 577         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 578         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 579 }
 580 #else
 581 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 582 {
 583 }
 584 #endif
 585
 586 /**
 587  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 588  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 589  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 590  *
 591  * @cs:      Chip Select Region.
 592  * @reg:     GPMC_CS_CONFIGn register offset.
 593  * @st_bit:  Start Bit
 594  * @end_bit: End Bit. Must be >= @st_bit.
 595  * @max:     Maximum parameter value.
 596  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 597  * @time:    Timing parameter in ns.
 598  * @cd:      Timing parameter clock domain.
 599  * @name:    Timing parameter name.
 600  * @return:  0 on success, -1 on error.
 601  */
 602 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 603                                int time, enum gpmc_clk_domain cd, const char *name)
 604 {
 605         u32 l;
 606         int ticks, mask, nr_bits;
 607
 608         if (time == 0)
 609                 ticks = 0;
 610         else
 611                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 612         nr_bits = end_bit - st_bit + 1;
 613         mask = (1 << nr_bits) - 1;
 614
 615         if (!max)
 616                 max = mask;
 617
 618         if (ticks > max) {
 619                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 620                        __func__, cs, name, time, ticks, max);
 621
 622                 return -1;
 623         }
 624
 625         l = gpmc_cs_read_reg(cs, reg);
 626 #ifdef CONFIG_OMAP_GPMC_DEBUG
 627         pr_info(
 628                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 629                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 630                         (l >> st_bit) & mask, time);
 631 #endif
 632         l &= ~(mask << st_bit);
 633         l |= ticks << st_bit;
 634         gpmc_cs_write_reg(cs, reg, l);
 635
 636         return 0;
 637 }
 638
 639 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 640         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 641             t->field, (cd), #field) < 0)                       \
 642                 return -1
 643
 644 #define GPMC_SET_ONE(reg, st, end, field) \
 645         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 646
 647 /**
 648  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 649  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 650  * read  --> don't sample bus too early
 651  * write --> data is longer on bus
 652  *
 653  * Formula:
 654  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 655  *                    / waitmonitoring_ticks)
 656  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 657  * div <= 0 check.
 658  *
 659  * @wait_monitoring: WAITMONITORINGTIME in ns.
 660  * @return:          -1 on failure to scale, else proper divider > 0.
 661  */
 662 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 663 {
 664
 665         int div = gpmc_ns_to_ticks(wait_monitoring);
 666
 667         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 668         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 669
 670         if (div > 4)
 671                 return -1;
 672         if (div <= 0)
 673                 div = 1;
 674
 675         return div;
 676
 677 }
 678
 679 /**
 680  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 681  * @sync_clk: GPMC_CLK period in ps.
 682  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 683  *            Else, returns -1.
 684  */
 685 int gpmc_calc_divider(unsigned int sync_clk)
 686 {
 687         int div = gpmc_ps_to_ticks(sync_clk);
 688
 689         if (div > 4)
 690                 return -1;
 691         if (div <= 0)
 692                 div = 1;
 693
 694         return div;
 695 }
 696
 697 /**
 698  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 699  * @cs:     Chip Select Region.
 700  * @t:      GPMC timing parameters.
 701  * @s:      GPMC timing settings.
 702  * @return: 0 on success, -1 on error.
 703  */
 704 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 705                         const struct gpmc_settings *s)
 706 {
 707         int div;
 708         u32 l;
 709
 710         div = gpmc_calc_divider(t->sync_clk);
 711         if (div < 0)
 712                 return div;
 713
 714         /*
 715          * See if we need to change the divider for waitmonitoringtime.
 716          *
 717          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 718          * pure asynchronous accesses, i.e. both read and write asynchronous.
 719          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 720          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 721          *
 722          * This statement must not change div to scale async WAITMONITORINGTIME
 723          * to protect mixed synchronous and asynchronous accesses.
 724          *
 725          * We raise an error later if WAITMONITORINGTIME does not fit.
 726          */
 727         if (!s->sync_read && !s->sync_write &&
 728             (s->wait_on_read || s->wait_on_write)
 729            ) {
 730
 731                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 732                 if (div < 0) {
 733                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 734                                __func__,
 735                                t->wait_monitoring
 736                                );
 737                         return -1;
 738                 }
 739         }
 740
 741         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 742         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 743         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 744
 745         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 746         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 747         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 748         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 749                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 750                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 751                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 752         }
 753
 754         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 755         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 756         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 757                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 758                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 759         }
 760         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 761         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 762
 763         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 764         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 765         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 766
 767         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 768
 769         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 770         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 771
 772         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 773                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 774         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 775                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 776
 777         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 778         l &= ~0x03;
 779         l |= (div - 1);
 780         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 781
 782         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 783                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 784                             wait_monitoring, GPMC_CD_CLK);
 785         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 786                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 787                             clk_activation, GPMC_CD_FCLK);
 788
 789 #ifdef CONFIG_OMAP_GPMC_DEBUG
 790         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 791                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 792 #endif
 793
 794         gpmc_cs_bool_timings(cs, &t->bool_timings);
 795         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 796
 797         return 0;
 798 }
 799
 800 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 801 {
 802         u32 l;
 803         u32 mask;
 804
 805         /*
 806          * Ensure that base address is aligned on a
 807          * boundary equal to or greater than size.
 808          */
 809         if (base & (size - 1))
 810                 return -EINVAL;
 811
 812         base >>= GPMC_CHUNK_SHIFT;
 813         mask = (1 << GPMC_SECTION_SHIFT) - size;
 814         mask >>= GPMC_CHUNK_SHIFT;
 815         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 816
 817         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 818         l &= ~GPMC_CONFIG7_MASK;
 819         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 820         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 821         l |= GPMC_CONFIG7_CSVALID;
 822         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 823
 824         return 0;
 825 }
 826
 827 static void gpmc_cs_enable_mem(int cs)
 828 {
 829         u32 l;
 830
 831         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 832         l |= GPMC_CONFIG7_CSVALID;
 833         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 834 }
 835
 836 static void gpmc_cs_disable_mem(int cs)
 837 {
 838         u32 l;
 839
 840         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 841         l &= ~GPMC_CONFIG7_CSVALID;
 842         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 843 }
 844
 845 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 846 {
 847         u32 l;
 848         u32 mask;
 849
 850         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 851         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 852         mask = (l >> 8) & 0x0f;
 853         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 854 }
 855
 856 static int gpmc_cs_mem_enabled(int cs)
 857 {
 858         u32 l;
 859
 860         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 861         return l & GPMC_CONFIG7_CSVALID;
 862 }
 863
 864 static void gpmc_cs_set_reserved(int cs, int reserved)
 865 {
 866         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 867
 868         gpmc->flags |= GPMC_CS_RESERVED;
 869 }
 870
 871 static bool gpmc_cs_reserved(int cs)
 872 {
 873         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 874
 875         return gpmc->flags & GPMC_CS_RESERVED;
 876 }
 877
 878 static void gpmc_cs_set_name(int cs, const char *name)
 879 {
 880         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 881
 882         gpmc->name = name;
 883 }
 884
 885 static const char *gpmc_cs_get_name(int cs)
 886 {
 887         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 888
 889         return gpmc->name;
 890 }
 891
 892 static unsigned long gpmc_mem_align(unsigned long size)
 893 {
 894         int order;
 895
 896         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 897         order = GPMC_CHUNK_SHIFT - 1;
 898         do {
 899                 size >>= 1;
 900                 order++;
 901         } while (size);
 902         size = 1 << order;
 903         return size;
 904 }
 905
 906 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 907 {
 908         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 909         struct resource *res = &gpmc->mem;
 910         int r;
 911
 912         size = gpmc_mem_align(size);
 913         spin_lock(&gpmc_mem_lock);
 914         res->start = base;
 915         res->end = base + size - 1;
 916         r = request_resource(&gpmc_mem_root, res);
 917         spin_unlock(&gpmc_mem_lock);
 918
 919         return r;
 920 }
 921
 922 static int gpmc_cs_delete_mem(int cs)
 923 {
 924         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 925         struct resource *res = &gpmc->mem;
 926         int r;
 927
 928         spin_lock(&gpmc_mem_lock);
 929         r = release_resource(res);
 930         res->start = 0;
 931         res->end = 0;
 932         spin_unlock(&gpmc_mem_lock);
 933
 934         return r;
 935 }
 936
 937 /**
 938  * gpmc_cs_remap - remaps a chip-select physical base address
 939  * @cs:         chip-select to remap
 940  * @base:       physical base address to re-map chip-select to
 941  *
 942  * Re-maps a chip-select to a new physical base address specified by
 943  * "base". Returns 0 on success and appropriate negative error code
 944  * on failure.
 945  */
 946 static int gpmc_cs_remap(int cs, u32 base)
 947 {
 948         int ret;
 949         u32 old_base, size;
 950
 951         if (cs > gpmc_cs_num) {
 952                 pr_err("%s: requested chip-select is disabled\n", __func__);
 953                 return -ENODEV;
 954         }
 955
 956         /*
 957          * Make sure we ignore any device offsets from the GPMC partition
 958          * allocated for the chip select and that the new base confirms
 959          * to the GPMC 16MB minimum granularity.
 960          */
 961         base &= ~(SZ_16M - 1);
 962
 963         gpmc_cs_get_memconf(cs, &old_base, &size);
 964         if (base == old_base)
 965                 return 0;
 966
 967         ret = gpmc_cs_delete_mem(cs);
 968         if (ret < 0)
 969                 return ret;
 970
 971         ret = gpmc_cs_insert_mem(cs, base, size);
 972         if (ret < 0)
 973                 return ret;
 974
 975         ret = gpmc_cs_set_memconf(cs, base, size);
 976
 977         return ret;
 978 }
 979
 980 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 981 {
 982         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 983         struct resource *res = &gpmc->mem;
 984         int r = -1;
 985
 986         if (cs > gpmc_cs_num) {
 987                 pr_err("%s: requested chip-select is disabled\n", __func__);
 988                 return -ENODEV;
 989         }
 990         size = gpmc_mem_align(size);
 991         if (size > (1 << GPMC_SECTION_SHIFT))
 992                 return -ENOMEM;
 993
 994         spin_lock(&gpmc_mem_lock);
 995         if (gpmc_cs_reserved(cs)) {
 996                 r = -EBUSY;
 997                 goto out;
 998         }
 999         if (gpmc_cs_mem_enabled(cs))
1000                 r = adjust_resource(res, res->start & ~(size - 1), size);
1001         if (r < 0)
1002                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1003                                       size, NULL, NULL);
1004         if (r < 0)
1005                 goto out;
1006
1007         /* Disable CS while changing base address and size mask */
1008         gpmc_cs_disable_mem(cs);
1009
1010         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1011         if (r < 0) {
1012                 release_resource(res);
1013                 goto out;
1014         }
1015
1016         /* Enable CS */
1017         gpmc_cs_enable_mem(cs);
1018         *base = res->start;
1019         gpmc_cs_set_reserved(cs, 1);
1020 out:
1021         spin_unlock(&gpmc_mem_lock);
1022         return r;
1023 }
1024 EXPORT_SYMBOL(gpmc_cs_request);
1025
1026 void gpmc_cs_free(int cs)
1027 {
1028         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1029         struct resource *res = &gpmc->mem;
1030
1031         spin_lock(&gpmc_mem_lock);
1032         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1033                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1034                 BUG();
1035                 spin_unlock(&gpmc_mem_lock);
1036                 return;
1037         }
1038         gpmc_cs_disable_mem(cs);
1039         if (res->flags)
1040                 release_resource(res);
1041         gpmc_cs_set_reserved(cs, 0);
1042         spin_unlock(&gpmc_mem_lock);
1043 }
1044 EXPORT_SYMBOL(gpmc_cs_free);
1045
1046 /**
1047  * gpmc_configure - write request to configure gpmc
1048  * @cmd: command type
1049  * @wval: value to write
1050  * @return status of the operation
1051  */
1052 int gpmc_configure(int cmd, int wval)
1053 {
1054         u32 regval;
1055
1056         switch (cmd) {
1057         case GPMC_ENABLE_IRQ:
1058                 gpmc_write_reg(GPMC_IRQENABLE, wval);
1059                 break;
1060
1061         case GPMC_SET_IRQ_STATUS:
1062                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
1063                 break;
1064
1065         case GPMC_CONFIG_WP:
1066                 regval = gpmc_read_reg(GPMC_CONFIG);
1067                 if (wval)
1068                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1069                 else
1070                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1071                 gpmc_write_reg(GPMC_CONFIG, regval);
1072                 break;
1073
1074         default:
1075                 pr_err("%s: command not supported\n", __func__);
1076                 return -EINVAL;
1077         }
1078
1079         return 0;
1080 }
1081 EXPORT_SYMBOL(gpmc_configure);
1082
1083 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1084 {
1085         int i;
1086
1087         reg->gpmc_status = gpmc_base + GPMC_STATUS;
1088         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1089                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1090         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1091                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1092         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1093                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1094         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1095         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1096         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1097         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1098         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1099         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1100         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1101         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1102
1103         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1104                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1105                                            GPMC_BCH_SIZE * i;
1106                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1107                                            GPMC_BCH_SIZE * i;
1108                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1109                                            GPMC_BCH_SIZE * i;
1110                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1111                                            GPMC_BCH_SIZE * i;
1112                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1113                                            i * GPMC_BCH_SIZE;
1114                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1115                                            i * GPMC_BCH_SIZE;
1116                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1117                                            i * GPMC_BCH_SIZE;
1118         }
1119 }
1120
1121 static struct gpmc_nand_ops nand_ops;
1122
1123 /**
1124  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1125  * @regs: the GPMC NAND register map exclusive for NAND use.
1126  * @cs: GPMC chip select number on which the NAND sits. The
1127  *      register map returned will be specific to this chip select.
1128  *
1129  * Returns NULL on error e.g. invalid cs.
1130  */
1131 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1132 {
1133         if (cs >= gpmc_cs_num)
1134                 return NULL;
1135
1136         gpmc_update_nand_reg(reg, cs);
1137
1138         return &nand_ops;
1139 }
1140 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1141
1142 int gpmc_get_client_irq(unsigned irq_config)
1143 {
1144         int i;
1145
1146         if (hweight32(irq_config) > 1)
1147                 return 0;
1148
1149         for (i = 0; i < GPMC_NR_IRQ; i++)
1150                 if (gpmc_client_irq[i].bitmask & irq_config)
1151                         return gpmc_client_irq[i].irq;
1152
1153         return 0;
1154 }
1155
1156 static int gpmc_irq_endis(unsigned irq, bool endis)
1157 {
1158         int i;
1159         u32 regval;
1160
1161         for (i = 0; i < GPMC_NR_IRQ; i++)
1162                 if (irq == gpmc_client_irq[i].irq) {
1163                         regval = gpmc_read_reg(GPMC_IRQENABLE);
1164                         if (endis)
1165                                 regval |= gpmc_client_irq[i].bitmask;
1166                         else
1167                                 regval &= ~gpmc_client_irq[i].bitmask;
1168                         gpmc_write_reg(GPMC_IRQENABLE, regval);
1169                         break;
1170                 }
1171
1172         return 0;
1173 }
1174
1175 static void gpmc_irq_disable(struct irq_data *p)
1176 {
1177         gpmc_irq_endis(p->irq, false);
1178 }
1179
1180 static void gpmc_irq_enable(struct irq_data *p)
1181 {
1182         gpmc_irq_endis(p->irq, true);
1183 }
1184
1185 static void gpmc_irq_noop(struct irq_data *data) { }
1186
1187 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1188
1189 static int gpmc_setup_irq(void)
1190 {
1191         int i;
1192         u32 regval;
1193
1194         if (!gpmc_irq)
1195                 return -EINVAL;
1196
1197         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
1198         if (gpmc_irq_start < 0) {
1199                 pr_err("irq_alloc_descs failed\n");
1200                 return gpmc_irq_start;
1201         }
1202
1203         gpmc_irq_chip.name = "gpmc";
1204         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
1205         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
1206         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
1207         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
1208         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
1209         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
1210         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
1211
1212         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
1213         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
1214
1215         for (i = 0; i < GPMC_NR_IRQ; i++) {
1216                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
1217                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1218                                         &gpmc_irq_chip, handle_simple_irq);
1219                 irq_modify_status(gpmc_client_irq[i].irq, IRQ_NOREQUEST,
1220                                   IRQ_NOAUTOEN);
1221         }
1222
1223         /* Disable interrupts */
1224         gpmc_write_reg(GPMC_IRQENABLE, 0);
1225
1226         /* clear interrupts */
1227         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1228         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1229
1230         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1231 }
1232
1233 static int gpmc_free_irq(void)
1234 {
1235         int i;
1236
1237         if (gpmc_irq)
1238                 free_irq(gpmc_irq, NULL);
1239
1240         for (i = 0; i < GPMC_NR_IRQ; i++) {
1241                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1242                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1243         }
1244
1245         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1246
1247         return 0;
1248 }
1249
1250 static void gpmc_mem_exit(void)
1251 {
1252         int cs;
1253
1254         for (cs = 0; cs < gpmc_cs_num; cs++) {
1255                 if (!gpmc_cs_mem_enabled(cs))
1256                         continue;
1257                 gpmc_cs_delete_mem(cs);
1258         }
1259
1260 }
1261
1262 static void gpmc_mem_init(void)
1263 {
1264         int cs;
1265
1266         /*
1267          * The first 1MB of GPMC address space is typically mapped to
1268          * the internal ROM. Never allocate the first page, to
1269          * facilitate bug detection; even if we didn't boot from ROM.
1270          */
1271         gpmc_mem_root.start = SZ_1M;
1272         gpmc_mem_root.end = GPMC_MEM_END;
1273
1274         /* Reserve all regions that has been set up by bootloader */
1275         for (cs = 0; cs < gpmc_cs_num; cs++) {
1276                 u32 base, size;
1277
1278                 if (!gpmc_cs_mem_enabled(cs))
1279                         continue;
1280                 gpmc_cs_get_memconf(cs, &base, &size);
1281                 if (gpmc_cs_insert_mem(cs, base, size)) {
1282                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1283                                 __func__, cs, base, base + size);
1284                         gpmc_cs_disable_mem(cs);
1285                 }
1286         }
1287 }
1288
1289 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1290 {
1291         u32 temp;
1292         int div;
1293
1294         div = gpmc_calc_divider(sync_clk);
1295         temp = gpmc_ps_to_ticks(time_ps);
1296         temp = (temp + div - 1) / div;
1297         return gpmc_ticks_to_ps(temp * div);
1298 }
1299
1300 /* XXX: can the cycles be avoided ? */
1301 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1302                                        struct gpmc_device_timings *dev_t,
1303                                        bool mux)
1304 {
1305         u32 temp;
1306
1307         /* adv_rd_off */
1308         temp = dev_t->t_avdp_r;
1309         /* XXX: mux check required ? */
1310         if (mux) {
1311                 /* XXX: t_avdp not to be required for sync, only added for tusb
1312                  * this indirectly necessitates requirement of t_avdp_r and
1313                  * t_avdp_w instead of having a single t_avdp
1314                  */
1315                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1316                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1317         }
1318         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1319
1320         /* oe_on */
1321         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1322         if (mux) {
1323                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1324                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1325                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1326         }
1327         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1328
1329         /* access */
1330         /* XXX: any scope for improvement ?, by combining oe_on
1331          * and clk_activation, need to check whether
1332          * access = clk_activation + round to sync clk ?
1333          */
1334         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1335         temp += gpmc_t->clk_activation;
1336         if (dev_t->cyc_oe)
1337                 temp = max_t(u32, temp, gpmc_t->oe_on +
1338                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1339         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1340
1341         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1342         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1343
1344         /* rd_cycle */
1345         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1346         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1347                                                         gpmc_t->access;
1348         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1349         if (dev_t->t_ce_rdyz)
1350                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1351         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1352
1353         return 0;
1354 }
1355
1356 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1357                                         struct gpmc_device_timings *dev_t,
1358                                         bool mux)
1359 {
1360         u32 temp;
1361
1362         /* adv_wr_off */
1363         temp = dev_t->t_avdp_w;
1364         if (mux) {
1365                 temp = max_t(u32, temp,
1366                         gpmc_t->clk_activation + dev_t->t_avdh);
1367                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1368         }
1369         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1370
1371         /* wr_data_mux_bus */
1372         temp = max_t(u32, dev_t->t_weasu,
1373                         gpmc_t->clk_activation + dev_t->t_rdyo);
1374         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1375          * and in that case remember to handle we_on properly
1376          */
1377         if (mux) {
1378                 temp = max_t(u32, temp,
1379                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1380                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1381                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1382         }
1383         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1384
1385         /* we_on */
1386         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1387                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1388         else
1389                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1390
1391         /* wr_access */
1392         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1393         gpmc_t->wr_access = gpmc_t->access;
1394
1395         /* we_off */
1396         temp = gpmc_t->we_on + dev_t->t_wpl;
1397         temp = max_t(u32, temp,
1398                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1399         temp = max_t(u32, temp,
1400                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1401         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1402
1403         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1404                                                         dev_t->t_wph);
1405
1406         /* wr_cycle */
1407         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1408         temp += gpmc_t->wr_access;
1409         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1410         if (dev_t->t_ce_rdyz)
1411                 temp = max_t(u32, temp,
1412                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1413         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1414
1415         return 0;
1416 }
1417
1418 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1419                                         struct gpmc_device_timings *dev_t,
1420                                         bool mux)
1421 {
1422         u32 temp;
1423
1424         /* adv_rd_off */
1425         temp = dev_t->t_avdp_r;
1426         if (mux)
1427                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1428         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1429
1430         /* oe_on */
1431         temp = dev_t->t_oeasu;
1432         if (mux)
1433                 temp = max_t(u32, temp,
1434                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1435         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1436
1437         /* access */
1438         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1439                                 gpmc_t->oe_on + dev_t->t_oe);
1440         temp = max_t(u32, temp,
1441                                 gpmc_t->cs_on + dev_t->t_ce);
1442         temp = max_t(u32, temp,
1443                                 gpmc_t->adv_on + dev_t->t_aa);
1444         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1445
1446         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1447         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1448
1449         /* rd_cycle */
1450         temp = max_t(u32, dev_t->t_rd_cycle,
1451                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1452         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1453         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1454
1455         return 0;
1456 }
1457
1458 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1459                                          struct gpmc_device_timings *dev_t,
1460                                          bool mux)
1461 {
1462         u32 temp;
1463
1464         /* adv_wr_off */
1465         temp = dev_t->t_avdp_w;
1466         if (mux)
1467                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1468         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1469
1470         /* wr_data_mux_bus */
1471         temp = dev_t->t_weasu;
1472         if (mux) {
1473                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1474                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1475                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1476         }
1477         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1478
1479         /* we_on */
1480         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1481                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1482         else
1483                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1484
1485         /* we_off */
1486         temp = gpmc_t->we_on + dev_t->t_wpl;
1487         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1488
1489         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1490                                                         dev_t->t_wph);
1491
1492         /* wr_cycle */
1493         temp = max_t(u32, dev_t->t_wr_cycle,
1494                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1495         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1496
1497         return 0;
1498 }
1499
1500 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1501                         struct gpmc_device_timings *dev_t)
1502 {
1503         u32 temp;
1504
1505         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1506                                                 gpmc_get_fclk_period();
1507
1508         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1509                                         dev_t->t_bacc,
1510                                         gpmc_t->sync_clk);
1511
1512         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1513         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1514
1515         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1516                 return 0;
1517
1518         if (dev_t->ce_xdelay)
1519                 gpmc_t->bool_timings.cs_extra_delay = true;
1520         if (dev_t->avd_xdelay)
1521                 gpmc_t->bool_timings.adv_extra_delay = true;
1522         if (dev_t->oe_xdelay)
1523                 gpmc_t->bool_timings.oe_extra_delay = true;
1524         if (dev_t->we_xdelay)
1525                 gpmc_t->bool_timings.we_extra_delay = true;
1526
1527         return 0;
1528 }
1529
1530 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1531                                     struct gpmc_device_timings *dev_t,
1532                                     bool sync)
1533 {
1534         u32 temp;
1535
1536         /* cs_on */
1537         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1538
1539         /* adv_on */
1540         temp = dev_t->t_avdasu;
1541         if (dev_t->t_ce_avd)
1542                 temp = max_t(u32, temp,
1543                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1544         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1545
1546         if (sync)
1547                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1548
1549         return 0;
1550 }
1551
1552 /* TODO: remove this function once all peripherals are confirmed to
1553  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1554  * has to be modified to handle timings in ps instead of ns
1555 */
1556 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1557 {
1558         t->cs_on /= 1000;
1559         t->cs_rd_off /= 1000;
1560         t->cs_wr_off /= 1000;
1561         t->adv_on /= 1000;
1562         t->adv_rd_off /= 1000;
1563         t->adv_wr_off /= 1000;
1564         t->we_on /= 1000;
1565         t->we_off /= 1000;
1566         t->oe_on /= 1000;
1567         t->oe_off /= 1000;
1568         t->page_burst_access /= 1000;
1569         t->access /= 1000;
1570         t->rd_cycle /= 1000;
1571         t->wr_cycle /= 1000;
1572         t->bus_turnaround /= 1000;
1573         t->cycle2cycle_delay /= 1000;
1574         t->wait_monitoring /= 1000;
1575         t->clk_activation /= 1000;
1576         t->wr_access /= 1000;
1577         t->wr_data_mux_bus /= 1000;
1578 }
1579
1580 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1581                       struct gpmc_settings *gpmc_s,
1582                       struct gpmc_device_timings *dev_t)
1583 {
1584         bool mux = false, sync = false;
1585
1586         if (gpmc_s) {
1587                 mux = gpmc_s->mux_add_data ? true : false;
1588                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1589         }
1590
1591         memset(gpmc_t, 0, sizeof(*gpmc_t));
1592
1593         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1594
1595         if (gpmc_s && gpmc_s->sync_read)
1596                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1597         else
1598                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1599
1600         if (gpmc_s && gpmc_s->sync_write)
1601                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1602         else
1603                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1604
1605         /* TODO: remove, see function definition */
1606         gpmc_convert_ps_to_ns(gpmc_t);
1607
1608         return 0;
1609 }
1610
1611 /**
1612  * gpmc_cs_program_settings - programs non-timing related settings
1613  * @cs:         GPMC chip-select to program
1614  * @p:          pointer to GPMC settings structure
1615  *
1616  * Programs non-timing related settings for a GPMC chip-select, such as
1617  * bus-width, burst configuration, etc. Function should be called once
1618  * for each chip-select that is being used and must be called before
1619  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1620  * register will be initialised to zero by this function. Returns 0 on
1621  * success and appropriate negative error code on failure.
1622  */
1623 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1624 {
1625         u32 config1;
1626
1627         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1628                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1629                 return -EINVAL;
1630         }
1631
1632         /* Address-data multiplexing not supported for NAND devices */
1633         if (p->device_nand && p->mux_add_data) {
1634                 pr_err("%s: invalid configuration!\n", __func__);
1635                 return -EINVAL;
1636         }
1637
1638         if ((p->mux_add_data > GPMC_MUX_AD) ||
1639             ((p->mux_add_data == GPMC_MUX_AAD) &&
1640              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1641                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1642                 return -EINVAL;
1643         }
1644
1645         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1646         if (p->burst_read || p->burst_write) {
1647                 switch (p->burst_len) {
1648                 case GPMC_BURST_4:
1649                 case GPMC_BURST_8:
1650                 case GPMC_BURST_16:
1651                         break;
1652                 default:
1653                         pr_err("%s: invalid page/burst-length (%d)\n",
1654                                __func__, p->burst_len);
1655                         return -EINVAL;
1656                 }
1657         }
1658
1659         if (p->wait_pin > gpmc_nr_waitpins) {
1660                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1661                 return -EINVAL;
1662         }
1663
1664         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1665
1666         if (p->sync_read)
1667                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1668         if (p->sync_write)
1669                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1670         if (p->wait_on_read)
1671                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1672         if (p->wait_on_write)
1673                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1674         if (p->wait_on_read || p->wait_on_write)
1675                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1676         if (p->device_nand)
1677                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1678         if (p->mux_add_data)
1679                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1680         if (p->burst_read)
1681                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1682         if (p->burst_write)
1683                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1684         if (p->burst_read || p->burst_write) {
1685                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1686                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1687         }
1688
1689         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1690
1691         return 0;
1692 }
1693
1694 #ifdef CONFIG_OF
1695 static const struct of_device_id gpmc_dt_ids[] = {
1696         { .compatible = "ti,omap2420-gpmc" },
1697         { .compatible = "ti,omap2430-gpmc" },
1698         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1699         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1700         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1701         { }
1702 };
1703 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1704
1705 /**
1706  * gpmc_read_settings_dt - read gpmc settings from device-tree
1707  * @np:         pointer to device-tree node for a gpmc child device
1708  * @p:          pointer to gpmc settings structure
1709  *
1710  * Reads the GPMC settings for a GPMC child device from device-tree and
1711  * stores them in the GPMC settings structure passed. The GPMC settings
1712  * structure is initialised to zero by this function and so any
1713  * previously stored settings will be cleared.
1714  */
1715 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1716 {
1717         memset(p, 0, sizeof(struct gpmc_settings));
1718
1719         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1720         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1721         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1722         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1723
1724         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1725                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1726                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1727                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1728                 if (!p->burst_read && !p->burst_write)
1729                         pr_warn("%s: page/burst-length set but not used!\n",
1730                                 __func__);
1731         }
1732
1733         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1734                 p->wait_on_read = of_property_read_bool(np,
1735                                                         "gpmc,wait-on-read");
1736                 p->wait_on_write = of_property_read_bool(np,
1737                                                          "gpmc,wait-on-write");
1738                 if (!p->wait_on_read && !p->wait_on_write)
1739                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1740                                  __func__);
1741         }
1742 }
1743
1744 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1745                                                 struct gpmc_timings *gpmc_t)
1746 {
1747         struct gpmc_bool_timings *p;
1748
1749         if (!np || !gpmc_t)
1750                 return;
1751
1752         memset(gpmc_t, 0, sizeof(*gpmc_t));
1753
1754         /* minimum clock period for syncronous mode */
1755         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1756
1757         /* chip select timtings */
1758         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1759         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1760         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1761
1762         /* ADV signal timings */
1763         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1764         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1765         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1766         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1767                              &gpmc_t->adv_aad_mux_on);
1768         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1769                              &gpmc_t->adv_aad_mux_rd_off);
1770         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1771                              &gpmc_t->adv_aad_mux_wr_off);
1772
1773         /* WE signal timings */
1774         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1775         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1776
1777         /* OE signal timings */
1778         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1779         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1780         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1781                              &gpmc_t->oe_aad_mux_on);
1782         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1783                              &gpmc_t->oe_aad_mux_off);
1784
1785         /* access and cycle timings */
1786         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1787                              &gpmc_t->page_burst_access);
1788         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1789         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1790         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1791         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1792                              &gpmc_t->bus_turnaround);
1793         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1794                              &gpmc_t->cycle2cycle_delay);
1795         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1796                              &gpmc_t->wait_monitoring);
1797         of_property_read_u32(np, "gpmc,clk-activation-ns",
1798                              &gpmc_t->clk_activation);
1799
1800         /* only applicable to OMAP3+ */
1801         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1802         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1803                              &gpmc_t->wr_data_mux_bus);
1804
1805         /* bool timing parameters */
1806         p = &gpmc_t->bool_timings;
1807
1808         p->cycle2cyclediffcsen =
1809                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1810         p->cycle2cyclesamecsen =
1811                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1812         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1813         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1814         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1815         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1816         p->time_para_granularity =
1817                 of_property_read_bool(np, "gpmc,time-para-granularity");
1818 }
1819
1820 #if IS_ENABLED(CONFIG_MTD_NAND)
1821
1822 static const char * const nand_xfer_types[] = {
1823         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1824         [NAND_OMAP_POLLED]                      = "polled",
1825         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1826         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1827 };
1828
1829 static int gpmc_probe_nand_child(struct platform_device *pdev,
1830                                  struct device_node *child)
1831 {
1832         u32 val;
1833         const char *s;
1834         struct gpmc_timings gpmc_t;
1835         struct omap_nand_platform_data *gpmc_nand_data;
1836
1837         if (of_property_read_u32(child, "reg", &val) < 0) {
1838                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1839                         child->full_name);
1840                 return -ENODEV;
1841         }
1842
1843         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1844                                       GFP_KERNEL);
1845         if (!gpmc_nand_data)
1846                 return -ENOMEM;
1847
1848         gpmc_nand_data->cs = val;
1849         gpmc_nand_data->of_node = child;
1850
1851         /* Detect availability of ELM module */
1852         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1853         if (gpmc_nand_data->elm_of_node == NULL)
1854                 gpmc_nand_data->elm_of_node =
1855                                         of_parse_phandle(child, "elm_id", 0);
1856
1857         /* select ecc-scheme for NAND */
1858         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1859                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1860                 return -ENODEV;
1861         }
1862
1863         if (!strcmp(s, "sw"))
1864                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1865         else if (!strcmp(s, "ham1") ||
1866                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1867                 gpmc_nand_data->ecc_opt =
1868                                 OMAP_ECC_HAM1_CODE_HW;
1869         else if (!strcmp(s, "bch4"))
1870                 if (gpmc_nand_data->elm_of_node)
1871                         gpmc_nand_data->ecc_opt =
1872                                 OMAP_ECC_BCH4_CODE_HW;
1873                 else
1874                         gpmc_nand_data->ecc_opt =
1875                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1876         else if (!strcmp(s, "bch8"))
1877                 if (gpmc_nand_data->elm_of_node)
1878                         gpmc_nand_data->ecc_opt =
1879                                 OMAP_ECC_BCH8_CODE_HW;
1880                 else
1881                         gpmc_nand_data->ecc_opt =
1882                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1883         else if (!strcmp(s, "bch16"))
1884                 if (gpmc_nand_data->elm_of_node)
1885                         gpmc_nand_data->ecc_opt =
1886                                 OMAP_ECC_BCH16_CODE_HW;
1887                 else
1888                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1889         else
1890                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1891
1892         /* select data transfer mode for NAND controller */
1893         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1894                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1895                         if (!strcasecmp(s, nand_xfer_types[val])) {
1896                                 gpmc_nand_data->xfer_type = val;
1897                                 break;
1898                         }
1899
1900         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1901
1902         val = of_get_nand_bus_width(child);
1903         if (val == 16)
1904                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1905
1906         gpmc_read_timings_dt(child, &gpmc_t);
1907         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1908
1909         return 0;
1910 }
1911 #else
1912 static int gpmc_probe_nand_child(struct platform_device *pdev,
1913                                  struct device_node *child)
1914 {
1915         return 0;
1916 }
1917 #endif
1918
1919 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1920 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1921                                  struct device_node *child)
1922 {
1923         u32 val;
1924         struct omap_onenand_platform_data *gpmc_onenand_data;
1925
1926         if (of_property_read_u32(child, "reg", &val) < 0) {
1927                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1928                         child->full_name);
1929                 return -ENODEV;
1930         }
1931
1932         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1933                                          GFP_KERNEL);
1934         if (!gpmc_onenand_data)
1935                 return -ENOMEM;
1936
1937         gpmc_onenand_data->cs = val;
1938         gpmc_onenand_data->of_node = child;
1939         gpmc_onenand_data->dma_channel = -1;
1940
1941         if (!of_property_read_u32(child, "dma-channel", &val))
1942                 gpmc_onenand_data->dma_channel = val;
1943
1944         gpmc_onenand_init(gpmc_onenand_data);
1945
1946         return 0;
1947 }
1948 #else
1949 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1950                                     struct device_node *child)
1951 {
1952         return 0;
1953 }
1954 #endif
1955
1956 /**
1957  * gpmc_probe_generic_child - configures the gpmc for a child device
1958  * @pdev:       pointer to gpmc platform device
1959  * @child:      pointer to device-tree node for child device
1960  *
1961  * Allocates and configures a GPMC chip-select for a child device.
1962  * Returns 0 on success and appropriate negative error code on failure.
1963  */
1964 static int gpmc_probe_generic_child(struct platform_device *pdev,
1965                                 struct device_node *child)
1966 {
1967         struct gpmc_settings gpmc_s;
1968         struct gpmc_timings gpmc_t;
1969         struct resource res;
1970         unsigned long base;
1971         const char *name;
1972         int ret, cs;
1973         u32 val;
1974
1975         if (of_property_read_u32(child, "reg", &cs) < 0) {
1976                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1977                         child->full_name);
1978                 return -ENODEV;
1979         }
1980
1981         if (of_address_to_resource(child, 0, &res) < 0) {
1982                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1983                         child->full_name);
1984                 return -ENODEV;
1985         }
1986
1987         /*
1988          * Check if we have multiple instances of the same device
1989          * on a single chip select. If so, use the already initialized
1990          * timings.
1991          */
1992         name = gpmc_cs_get_name(cs);
1993         if (name && child->name && of_node_cmp(child->name, name) == 0)
1994                         goto no_timings;
1995
1996         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1997         if (ret < 0) {
1998                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1999                 return ret;
2000         }
2001         gpmc_cs_set_name(cs, child->name);
2002
2003         gpmc_read_settings_dt(child, &gpmc_s);
2004         gpmc_read_timings_dt(child, &gpmc_t);
2005
2006         /*
2007          * For some GPMC devices we still need to rely on the bootloader
2008          * timings because the devices can be connected via FPGA.
2009          * REVISIT: Add timing support from slls644g.pdf.
2010          */
2011         if (!gpmc_t.cs_rd_off) {
2012                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2013                         cs);
2014                 gpmc_cs_show_timings(cs,
2015                                      "please add GPMC bootloader timings to .dts");
2016                 goto no_timings;
2017         }
2018
2019         /* CS must be disabled while making changes to gpmc configuration */
2020         gpmc_cs_disable_mem(cs);
2021
2022         /*
2023          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2024          * location in the gpmc address space. When booting with
2025          * device-tree we want the NOR flash to be mapped to the
2026          * location specified in the device-tree blob. So remap the
2027          * CS to this location. Once DT migration is complete should
2028          * just make gpmc_cs_request() map a specific address.
2029          */
2030         ret = gpmc_cs_remap(cs, res.start);
2031         if (ret < 0) {
2032                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2033                         cs, &res.start);
2034                 goto err;
2035         }
2036
2037         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
2038         if (ret < 0)
2039                 goto err;
2040
2041         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2042         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2043         if (ret < 0)
2044                 goto err;
2045
2046         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2047         if (ret) {
2048                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2049                         child->name);
2050                 goto err;
2051         }
2052
2053         /* Clear limited address i.e. enable A26-A11 */
2054         val = gpmc_read_reg(GPMC_CONFIG);
2055         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2056         gpmc_write_reg(GPMC_CONFIG, val);
2057
2058         /* Enable CS region */
2059         gpmc_cs_enable_mem(cs);
2060
2061 no_timings:
2062
2063         /* create platform device, NULL on error or when disabled */
2064         if (!of_platform_device_create(child, NULL, &pdev->dev))
2065                 goto err_child_fail;
2066
2067         /* is child a common bus? */
2068         if (of_match_node(of_default_bus_match_table, child))
2069                 /* create children and other common bus children */
2070                 if (of_platform_populate(child, of_default_bus_match_table,
2071                                          NULL, &pdev->dev))
2072                         goto err_child_fail;
2073
2074         return 0;
2075
2076 err_child_fail:
2077
2078         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2079         ret = -ENODEV;
2080
2081 err:
2082         gpmc_cs_free(cs);
2083
2084         return ret;
2085 }
2086
2087 static int gpmc_probe_dt(struct platform_device *pdev)
2088 {
2089         int ret;
2090         struct device_node *child;
2091         const struct of_device_id *of_id =
2092                 of_match_device(gpmc_dt_ids, &pdev->dev);
2093
2094         if (!of_id)
2095                 return 0;
2096
2097         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2098                                    &gpmc_cs_num);
2099         if (ret < 0) {
2100                 pr_err("%s: number of chip-selects not defined\n", __func__);
2101                 return ret;
2102         } else if (gpmc_cs_num < 1) {
2103                 pr_err("%s: all chip-selects are disabled\n", __func__);
2104                 return -EINVAL;
2105         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2106                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2107                                          __func__, GPMC_CS_NUM);
2108                 return -EINVAL;
2109         }
2110
2111         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2112                                    &gpmc_nr_waitpins);
2113         if (ret < 0) {
2114                 pr_err("%s: number of wait pins not found!\n", __func__);
2115                 return ret;
2116         }
2117
2118         for_each_available_child_of_node(pdev->dev.of_node, child) {
2119
2120                 if (!child->name)
2121                         continue;
2122
2123                 if (of_node_cmp(child->name, "nand") == 0)
2124                         ret = gpmc_probe_nand_child(pdev, child);
2125                 else if (of_node_cmp(child->name, "onenand") == 0)
2126                         ret = gpmc_probe_onenand_child(pdev, child);
2127                 else
2128                         ret = gpmc_probe_generic_child(pdev, child);
2129         }
2130
2131         return 0;
2132 }
2133 #else
2134 static int gpmc_probe_dt(struct platform_device *pdev)
2135 {
2136         return 0;
2137 }
2138 #endif
2139
2140 static int gpmc_probe(struct platform_device *pdev)
2141 {
2142         int rc;
2143         u32 l;
2144         struct resource *res;
2145
2146         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2147         if (res == NULL)
2148                 return -ENOENT;
2149
2150         phys_base = res->start;
2151         mem_size = resource_size(res);
2152
2153         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2154         if (IS_ERR(gpmc_base))
2155                 return PTR_ERR(gpmc_base);
2156
2157         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2158         if (res == NULL)
2159                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
2160         else
2161                 gpmc_irq = res->start;
2162
2163         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2164         if (IS_ERR(gpmc_l3_clk)) {
2165                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2166                 gpmc_irq = 0;
2167                 return PTR_ERR(gpmc_l3_clk);
2168         }
2169
2170         if (!clk_get_rate(gpmc_l3_clk)) {
2171                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2172                 return -EINVAL;
2173         }
2174
2175         pm_runtime_enable(&pdev->dev);
2176         pm_runtime_get_sync(&pdev->dev);
2177
2178         gpmc_dev = &pdev->dev;
2179
2180         l = gpmc_read_reg(GPMC_REVISION);
2181
2182         /*
2183          * FIXME: Once device-tree migration is complete the below flags
2184          * should be populated based upon the device-tree compatible
2185          * string. For now just use the IP revision. OMAP3+ devices have
2186          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2187          * devices support the addr-addr-data multiplex protocol.
2188          *
2189          * GPMC IP revisions:
2190          * - OMAP24xx                   = 2.0
2191          * - OMAP3xxx                   = 5.0
2192          * - OMAP44xx/54xx/AM335x       = 6.0
2193          */
2194         if (GPMC_REVISION_MAJOR(l) > 0x4)
2195                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2196         if (GPMC_REVISION_MAJOR(l) > 0x5)
2197                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2198         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2199                  GPMC_REVISION_MINOR(l));
2200
2201         gpmc_mem_init();
2202
2203         if (gpmc_setup_irq() < 0)
2204                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
2205
2206         if (!pdev->dev.of_node) {
2207                 gpmc_cs_num      = GPMC_CS_NUM;
2208                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2209         }
2210
2211         rc = gpmc_probe_dt(pdev);
2212         if (rc < 0) {
2213                 pm_runtime_put_sync(&pdev->dev);
2214                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
2215                 return rc;
2216         }
2217
2218         return 0;
2219 }
2220
2221 static int gpmc_remove(struct platform_device *pdev)
2222 {
2223         gpmc_free_irq();
2224         gpmc_mem_exit();
2225         pm_runtime_put_sync(&pdev->dev);
2226         pm_runtime_disable(&pdev->dev);
2227         gpmc_dev = NULL;
2228         return 0;
2229 }
2230
2231 #ifdef CONFIG_PM_SLEEP
2232 static int gpmc_suspend(struct device *dev)
2233 {
2234         omap3_gpmc_save_context();
2235         pm_runtime_put_sync(dev);
2236         return 0;
2237 }
2238
2239 static int gpmc_resume(struct device *dev)
2240 {
2241         pm_runtime_get_sync(dev);
2242         omap3_gpmc_restore_context();
2243         return 0;
2244 }
2245 #endif
2246
2247 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2248
2249 static struct platform_driver gpmc_driver = {
2250         .probe          = gpmc_probe,
2251         .remove         = gpmc_remove,
2252         .driver         = {
2253                 .name   = DEVICE_NAME,
2254                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2255                 .pm     = &gpmc_pm_ops,
2256         },
2257 };
2258
2259 static __init int gpmc_init(void)
2260 {
2261         return platform_driver_register(&gpmc_driver);
2262 }
2263
2264 static __exit void gpmc_exit(void)
2265 {
2266         platform_driver_unregister(&gpmc_driver);
2267
2268 }
2269
2270 postcore_initcall(gpmc_init);
2271 module_exit(gpmc_exit);
2272
2273 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2274 {
2275         int i;
2276         u32 regval;
2277
2278         regval = gpmc_read_reg(GPMC_IRQSTATUS);
2279
2280         if (!regval)
2281                 return IRQ_NONE;
2282
2283         for (i = 0; i < GPMC_NR_IRQ; i++)
2284                 if (regval & gpmc_client_irq[i].bitmask)
2285                         generic_handle_irq(gpmc_client_irq[i].irq);
2286
2287         gpmc_write_reg(GPMC_IRQSTATUS, regval);
2288
2289         return IRQ_HANDLED;
2290 }
2291
2292 static struct omap3_gpmc_regs gpmc_context;
2293
2294 void omap3_gpmc_save_context(void)
2295 {
2296         int i;
2297
2298         if (!gpmc_base)
2299                 return;
2300
2301         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2302         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2303         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2304         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2305         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2306         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2307         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2308         for (i = 0; i < gpmc_cs_num; i++) {
2309                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2310                 if (gpmc_context.cs_context[i].is_valid) {
2311                         gpmc_context.cs_context[i].config1 =
2312                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2313                         gpmc_context.cs_context[i].config2 =
2314                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2315                         gpmc_context.cs_context[i].config3 =
2316                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2317                         gpmc_context.cs_context[i].config4 =
2318                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2319                         gpmc_context.cs_context[i].config5 =
2320                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2321                         gpmc_context.cs_context[i].config6 =
2322                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2323                         gpmc_context.cs_context[i].config7 =
2324                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2325                 }
2326         }
2327 }
2328
2329 void omap3_gpmc_restore_context(void)
2330 {
2331         int i;
2332
2333         if (!gpmc_base)
2334                 return;
2335
2336         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2337         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2338         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2339         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2340         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2341         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2342         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2343         for (i = 0; i < gpmc_cs_num; i++) {
2344                 if (gpmc_context.cs_context[i].is_valid) {
2345                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2346                                 gpmc_context.cs_context[i].config1);
2347                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2348                                 gpmc_context.cs_context[i].config2);
2349                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2350                                 gpmc_context.cs_context[i].config3);
2351                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2352                                 gpmc_context.cs_context[i].config4);
2353                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2354                                 gpmc_context.cs_context[i].config5);
2355                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2356                                 gpmc_context.cs_context[i].config6);
2357                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2358                                 gpmc_context.cs_context[i].config7);
2359                 }
2360         }
2361 }