drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/gpio/driver.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_mtd.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_platform.h>
  33 #include <linux/omap-gpmc.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <linux/platform_data/mtd-nand-omap2.h>
  37 #include <linux/platform_data/mtd-onenand-omap2.h>
  38
  39 #include <asm/mach-types.h>
  40
  41 #define DEVICE_NAME             "omap-gpmc"
  42
  43 /* GPMC register offsets */
  44 #define GPMC_REVISION           0x00
  45 #define GPMC_SYSCONFIG          0x10
  46 #define GPMC_SYSSTATUS          0x14
  47 #define GPMC_IRQSTATUS          0x18
  48 #define GPMC_IRQENABLE          0x1c
  49 #define GPMC_TIMEOUT_CONTROL    0x40
  50 #define GPMC_ERR_ADDRESS        0x44
  51 #define GPMC_ERR_TYPE           0x48
  52 #define GPMC_CONFIG             0x50
  53 #define GPMC_STATUS             0x54
  54 #define GPMC_PREFETCH_CONFIG1   0x1e0
  55 #define GPMC_PREFETCH_CONFIG2   0x1e4
  56 #define GPMC_PREFETCH_CONTROL   0x1ec
  57 #define GPMC_PREFETCH_STATUS    0x1f0
  58 #define GPMC_ECC_CONFIG         0x1f4
  59 #define GPMC_ECC_CONTROL        0x1f8
  60 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  61 #define GPMC_ECC1_RESULT        0x200
  62 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  68 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  69
  70 /* GPMC ECC control settings */
  71 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  72 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  73 #define GPMC_ECC_CTRL_ECCREG1           0x001
  74 #define GPMC_ECC_CTRL_ECCREG2           0x002
  75 #define GPMC_ECC_CTRL_ECCREG3           0x003
  76 #define GPMC_ECC_CTRL_ECCREG4           0x004
  77 #define GPMC_ECC_CTRL_ECCREG5           0x005
  78 #define GPMC_ECC_CTRL_ECCREG6           0x006
  79 #define GPMC_ECC_CTRL_ECCREG7           0x007
  80 #define GPMC_ECC_CTRL_ECCREG8           0x008
  81 #define GPMC_ECC_CTRL_ECCREG9           0x009
  82
  83 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  84
  85 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  86
  87 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  88 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  89 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  90 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  91 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  92 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  93
  94 #define GPMC_CS0_OFFSET         0x60
  95 #define GPMC_CS_SIZE            0x30
  96 #define GPMC_BCH_SIZE           0x10
  97
  98 /*
  99  * The first 1MB of GPMC address space is typically mapped to
 100  * the internal ROM. Never allocate the first page, to
 101  * facilitate bug detection; even if we didn't boot from ROM.
 102  * As GPMC minimum partition size is 16MB we can only start from
 103  * there.
 104  */
 105 #define GPMC_MEM_START          0x1000000
 106 #define GPMC_MEM_END            0x3FFFFFFF
 107
 108 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 109 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 110
 111 #define CS_NUM_SHIFT            24
 112 #define ENABLE_PREFETCH         (0x1 << 7)
 113 #define DMA_MPU_MODE            2
 114
 115 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 116 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 117
 118 #define GPMC_HAS_WR_ACCESS              0x1
 119 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 120 #define GPMC_HAS_MUX_AAD                0x4
 121
 122 #define GPMC_NR_WAITPINS                4
 123
 124 #define GPMC_CS_CONFIG1         0x00
 125 #define GPMC_CS_CONFIG2         0x04
 126 #define GPMC_CS_CONFIG3         0x08
 127 #define GPMC_CS_CONFIG4         0x0c
 128 #define GPMC_CS_CONFIG5         0x10
 129 #define GPMC_CS_CONFIG6         0x14
 130 #define GPMC_CS_CONFIG7         0x18
 131 #define GPMC_CS_NAND_COMMAND    0x1c
 132 #define GPMC_CS_NAND_ADDRESS    0x20
 133 #define GPMC_CS_NAND_DATA       0x24
 134
 135 /* Control Commands */
 136 #define GPMC_CONFIG_RDY_BSY     0x00000001
 137 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 138 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 139
 140 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 141 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 142 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 143 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 144 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 145 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 146 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 147 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 148 /** CLKACTIVATIONTIME Max Ticks */
 149 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 150 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 151 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 152 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 153 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 154 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 155 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 156 /** WAITMONITORINGTIME Max Ticks */
 157 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 158 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 159 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 160 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 161 /** DEVICESIZE Max Value */
 162 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 163 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 164 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 165 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 166 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 167 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 168 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 169 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 170 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 171 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 172
 173 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 174 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 175 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 176 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 177 /* All CONFIG7 bits except reserved bits */
 178 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 179                                          GPMC_CONFIG7_CSVALID_MASK |     \
 180                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 181
 182 #define GPMC_DEVICETYPE_NOR             0
 183 #define GPMC_DEVICETYPE_NAND            2
 184 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 185 #define WR_RD_PIN_MONITORING            0x00600000
 186
 187 /* ECC commands */
 188 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 189 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 190 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 191
 192 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 193  */
 194 #define GPMC_NR_IRQ             2
 195
 196 enum gpmc_clk_domain {
 197         GPMC_CD_FCLK,
 198         GPMC_CD_CLK
 199 };
 200
 201 struct gpmc_cs_data {
 202         const char *name;
 203
 204 #define GPMC_CS_RESERVED        (1 << 0)
 205         u32 flags;
 206
 207         struct resource mem;
 208 };
 209
 210 /* Structure to save gpmc cs context */
 211 struct gpmc_cs_config {
 212         u32 config1;
 213         u32 config2;
 214         u32 config3;
 215         u32 config4;
 216         u32 config5;
 217         u32 config6;
 218         u32 config7;
 219         int is_valid;
 220 };
 221
 222 /*
 223  * Structure to save/restore gpmc context
 224  * to support core off on OMAP3
 225  */
 226 struct omap3_gpmc_regs {
 227         u32 sysconfig;
 228         u32 irqenable;
 229         u32 timeout_ctrl;
 230         u32 config;
 231         u32 prefetch_config1;
 232         u32 prefetch_config2;
 233         u32 prefetch_control;
 234         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 235 };
 236
 237 struct gpmc_device {
 238         struct device *dev;
 239         int irq;
 240         struct irq_chip irq_chip;
 241         struct gpio_chip gpio_chip;
 242 };
 243
 244 static struct irq_domain *gpmc_irq_domain;
 245
 246 static struct resource  gpmc_mem_root;
 247 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 248 static DEFINE_SPINLOCK(gpmc_mem_lock);
 249 /* Define chip-selects as reserved by default until probe completes */
 250 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 251 static unsigned int gpmc_nr_waitpins;
 252 static resource_size_t phys_base, mem_size;
 253 static unsigned gpmc_capability;
 254 static void __iomem *gpmc_base;
 255
 256 static struct clk *gpmc_l3_clk;
 257
 258 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 259
 260 static void gpmc_write_reg(int idx, u32 val)
 261 {
 262         writel_relaxed(val, gpmc_base + idx);
 263 }
 264
 265 static u32 gpmc_read_reg(int idx)
 266 {
 267         return readl_relaxed(gpmc_base + idx);
 268 }
 269
 270 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 271 {
 272         void __iomem *reg_addr;
 273
 274         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 275         writel_relaxed(val, reg_addr);
 276 }
 277
 278 static u32 gpmc_cs_read_reg(int cs, int idx)
 279 {
 280         void __iomem *reg_addr;
 281
 282         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 283         return readl_relaxed(reg_addr);
 284 }
 285
 286 /* TODO: Add support for gpmc_fck to clock framework and use it */
 287 static unsigned long gpmc_get_fclk_period(void)
 288 {
 289         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 290
 291         rate /= 1000;
 292         rate = 1000000000 / rate;       /* In picoseconds */
 293
 294         return rate;
 295 }
 296
 297 /**
 298  * gpmc_get_clk_period - get period of selected clock domain in ps
 299  * @cs Chip Select Region.
 300  * @cd Clock Domain.
 301  *
 302  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 303  * prior to calling this function with GPMC_CD_CLK.
 304  */
 305 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 306 {
 307
 308         unsigned long tick_ps = gpmc_get_fclk_period();
 309         u32 l;
 310         int div;
 311
 312         switch (cd) {
 313         case GPMC_CD_CLK:
 314                 /* get current clk divider */
 315                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 316                 div = (l & 0x03) + 1;
 317                 /* get GPMC_CLK period */
 318                 tick_ps *= div;
 319                 break;
 320         case GPMC_CD_FCLK:
 321                 /* FALL-THROUGH */
 322         default:
 323                 break;
 324         }
 325
 326         return tick_ps;
 327
 328 }
 329
 330 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 331                                          enum gpmc_clk_domain cd)
 332 {
 333         unsigned long tick_ps;
 334
 335         /* Calculate in picosecs to yield more exact results */
 336         tick_ps = gpmc_get_clk_period(cs, cd);
 337
 338         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 339 }
 340
 341 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 342 {
 343         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 344 }
 345
 346 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 347 {
 348         unsigned long tick_ps;
 349
 350         /* Calculate in picosecs to yield more exact results */
 351         tick_ps = gpmc_get_fclk_period();
 352
 353         return (time_ps + tick_ps - 1) / tick_ps;
 354 }
 355
 356 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 357                                   enum gpmc_clk_domain cd)
 358 {
 359         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 360 }
 361
 362 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 363 {
 364         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 365 }
 366
 367 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 368 {
 369         return ticks * gpmc_get_fclk_period();
 370 }
 371
 372 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 373 {
 374         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 375
 376         return ticks * gpmc_get_fclk_period();
 377 }
 378
 379 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 380 {
 381         u32 l;
 382
 383         l = gpmc_cs_read_reg(cs, reg);
 384         if (value)
 385                 l |= mask;
 386         else
 387                 l &= ~mask;
 388         gpmc_cs_write_reg(cs, reg, l);
 389 }
 390
 391 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 392 {
 393         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 394                            GPMC_CONFIG1_TIME_PARA_GRAN,
 395                            p->time_para_granularity);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 397                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 399                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 400         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 401                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 402         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 403                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 404         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 405                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 406                            p->cycle2cyclesamecsen);
 407         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 408                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 409                            p->cycle2cyclediffcsen);
 410 }
 411
 412 #ifdef CONFIG_OMAP_GPMC_DEBUG
 413 /**
 414  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 415  * @cs:      Chip Select Region
 416  * @reg:     GPMC_CS_CONFIGn register offset.
 417  * @st_bit:  Start Bit
 418  * @end_bit: End Bit. Must be >= @st_bit.
 419  * @ma:x     Maximum parameter value (before optional @shift).
 420  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 421  * @name:    DTS node name, w/o "gpmc,"
 422  * @cd:      Clock Domain of timing parameter.
 423  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 424  * @raw:     Raw Format Option.
 425  *           raw format:  gpmc,name = <value>
 426  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 427  *           Where x ns -- y ns result in the same tick value.
 428  *           When @max is exceeded, "invalid" is printed inside comment.
 429  * @noval:   Parameter values equal to 0 are not printed.
 430  * @return:  Specified timing parameter (after optional @shift).
 431  *
 432  */
 433 static int get_gpmc_timing_reg(
 434         /* timing specifiers */
 435         int cs, int reg, int st_bit, int end_bit, int max,
 436         const char *name, const enum gpmc_clk_domain cd,
 437         /* value transform */
 438         int shift,
 439         /* format specifiers */
 440         bool raw, bool noval)
 441 {
 442         u32 l;
 443         int nr_bits;
 444         int mask;
 445         bool invalid;
 446
 447         l = gpmc_cs_read_reg(cs, reg);
 448         nr_bits = end_bit - st_bit + 1;
 449         mask = (1 << nr_bits) - 1;
 450         l = (l >> st_bit) & mask;
 451         if (!max)
 452                 max = mask;
 453         invalid = l > max;
 454         if (shift)
 455                 l = (shift << l);
 456         if (noval && (l == 0))
 457                 return 0;
 458         if (!raw) {
 459                 /* DTS tick format for timings in ns */
 460                 unsigned int time_ns;
 461                 unsigned int time_ns_min = 0;
 462
 463                 if (l)
 464                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 465                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 466                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 467                         name, time_ns, time_ns_min, time_ns, l,
 468                         invalid ? "; invalid " : " ");
 469         } else {
 470                 /* raw format */
 471                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 472                         invalid ? " /* invalid */" : "");
 473         }
 474
 475         return l;
 476 }
 477
 478 #define GPMC_PRINT_CONFIG(cs, config) \
 479         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 480                 gpmc_cs_read_reg(cs, config))
 481 #define GPMC_GET_RAW(reg, st, end, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 483 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 485 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 487 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 489 #define GPMC_GET_TICKS(reg, st, end, field) \
 490         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 491 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 492         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 493 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 494         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 495
 496 static void gpmc_show_regs(int cs, const char *desc)
 497 {
 498         pr_info("gpmc cs%i %s:\n", cs, desc);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 500         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 501         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 502         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 503         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 504         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 505 }
 506
 507 /*
 508  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 509  * see commit c9fb809.
 510  */
 511 static void gpmc_cs_show_timings(int cs, const char *desc)
 512 {
 513         gpmc_show_regs(cs, desc);
 514
 515         pr_info("gpmc cs%i access configuration:\n", cs);
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 517         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 518         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 519                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 520         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 521         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 523         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 524                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 525                                "burst-length");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 529         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 531
 532         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 533
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 535
 536         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 537         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 538
 539         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 540         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 541
 542         pr_info("gpmc cs%i timings configuration:\n", cs);
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 544         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 546
 547         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 548         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 549         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 550         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 551                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 552                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 553                                 "adv-aad-mux-rd-off-ns");
 554                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 555                                 "adv-aad-mux-wr-off-ns");
 556         }
 557
 558         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 559         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 560         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 561                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 562                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 563         }
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 566
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 568         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 569         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 570
 571         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 572
 573         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 574         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 575
 576         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 577                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 578                               "wait-monitoring-ns", GPMC_CD_CLK);
 579         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 580                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 581                               "clk-activation-ns", GPMC_CD_FCLK);
 582
 583         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 584         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 585 }
 586 #else
 587 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 588 {
 589 }
 590 #endif
 591
 592 /**
 593  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 594  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 595  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 596  *
 597  * @cs:      Chip Select Region.
 598  * @reg:     GPMC_CS_CONFIGn register offset.
 599  * @st_bit:  Start Bit
 600  * @end_bit: End Bit. Must be >= @st_bit.
 601  * @max:     Maximum parameter value.
 602  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 603  * @time:    Timing parameter in ns.
 604  * @cd:      Timing parameter clock domain.
 605  * @name:    Timing parameter name.
 606  * @return:  0 on success, -1 on error.
 607  */
 608 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 609                                int time, enum gpmc_clk_domain cd, const char *name)
 610 {
 611         u32 l;
 612         int ticks, mask, nr_bits;
 613
 614         if (time == 0)
 615                 ticks = 0;
 616         else
 617                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 618         nr_bits = end_bit - st_bit + 1;
 619         mask = (1 << nr_bits) - 1;
 620
 621         if (!max)
 622                 max = mask;
 623
 624         if (ticks > max) {
 625                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 626                        __func__, cs, name, time, ticks, max);
 627
 628                 return -1;
 629         }
 630
 631         l = gpmc_cs_read_reg(cs, reg);
 632 #ifdef CONFIG_OMAP_GPMC_DEBUG
 633         pr_info(
 634                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 635                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 636                         (l >> st_bit) & mask, time);
 637 #endif
 638         l &= ~(mask << st_bit);
 639         l |= ticks << st_bit;
 640         gpmc_cs_write_reg(cs, reg, l);
 641
 642         return 0;
 643 }
 644
 645 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 646         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 647             t->field, (cd), #field) < 0)                       \
 648                 return -1
 649
 650 #define GPMC_SET_ONE(reg, st, end, field) \
 651         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 652
 653 /**
 654  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 655  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 656  * read  --> don't sample bus too early
 657  * write --> data is longer on bus
 658  *
 659  * Formula:
 660  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 661  *                    / waitmonitoring_ticks)
 662  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 663  * div <= 0 check.
 664  *
 665  * @wait_monitoring: WAITMONITORINGTIME in ns.
 666  * @return:          -1 on failure to scale, else proper divider > 0.
 667  */
 668 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 669 {
 670
 671         int div = gpmc_ns_to_ticks(wait_monitoring);
 672
 673         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 674         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 675
 676         if (div > 4)
 677                 return -1;
 678         if (div <= 0)
 679                 div = 1;
 680
 681         return div;
 682
 683 }
 684
 685 /**
 686  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 687  * @sync_clk: GPMC_CLK period in ps.
 688  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 689  *            Else, returns -1.
 690  */
 691 int gpmc_calc_divider(unsigned int sync_clk)
 692 {
 693         int div = gpmc_ps_to_ticks(sync_clk);
 694
 695         if (div > 4)
 696                 return -1;
 697         if (div <= 0)
 698                 div = 1;
 699
 700         return div;
 701 }
 702
 703 /**
 704  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 705  * @cs:     Chip Select Region.
 706  * @t:      GPMC timing parameters.
 707  * @s:      GPMC timing settings.
 708  * @return: 0 on success, -1 on error.
 709  */
 710 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 711                         const struct gpmc_settings *s)
 712 {
 713         int div;
 714         u32 l;
 715
 716         div = gpmc_calc_divider(t->sync_clk);
 717         if (div < 0)
 718                 return div;
 719
 720         /*
 721          * See if we need to change the divider for waitmonitoringtime.
 722          *
 723          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 724          * pure asynchronous accesses, i.e. both read and write asynchronous.
 725          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 726          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 727          *
 728          * This statement must not change div to scale async WAITMONITORINGTIME
 729          * to protect mixed synchronous and asynchronous accesses.
 730          *
 731          * We raise an error later if WAITMONITORINGTIME does not fit.
 732          */
 733         if (!s->sync_read && !s->sync_write &&
 734             (s->wait_on_read || s->wait_on_write)
 735            ) {
 736
 737                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 738                 if (div < 0) {
 739                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 740                                __func__,
 741                                t->wait_monitoring
 742                                );
 743                         return -1;
 744                 }
 745         }
 746
 747         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 748         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 749         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 750
 751         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 752         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 753         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 754         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 755                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 756                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 757                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 758         }
 759
 760         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 761         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 762         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 763                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 764                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 765         }
 766         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 767         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 768
 769         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 770         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 771         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 772
 773         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 774
 775         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 776         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 777
 778         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 779                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 780         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 781                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 782
 783         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 784         l &= ~0x03;
 785         l |= (div - 1);
 786         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 787
 788         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 789                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 790                             wait_monitoring, GPMC_CD_CLK);
 791         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 792                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 793                             clk_activation, GPMC_CD_FCLK);
 794
 795 #ifdef CONFIG_OMAP_GPMC_DEBUG
 796         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 797                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 798 #endif
 799
 800         gpmc_cs_bool_timings(cs, &t->bool_timings);
 801         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 802
 803         return 0;
 804 }
 805
 806 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 807 {
 808         u32 l;
 809         u32 mask;
 810
 811         /*
 812          * Ensure that base address is aligned on a
 813          * boundary equal to or greater than size.
 814          */
 815         if (base & (size - 1))
 816                 return -EINVAL;
 817
 818         base >>= GPMC_CHUNK_SHIFT;
 819         mask = (1 << GPMC_SECTION_SHIFT) - size;
 820         mask >>= GPMC_CHUNK_SHIFT;
 821         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 822
 823         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 824         l &= ~GPMC_CONFIG7_MASK;
 825         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 826         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 827         l |= GPMC_CONFIG7_CSVALID;
 828         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 829
 830         return 0;
 831 }
 832
 833 static void gpmc_cs_enable_mem(int cs)
 834 {
 835         u32 l;
 836
 837         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 838         l |= GPMC_CONFIG7_CSVALID;
 839         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 840 }
 841
 842 static void gpmc_cs_disable_mem(int cs)
 843 {
 844         u32 l;
 845
 846         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 847         l &= ~GPMC_CONFIG7_CSVALID;
 848         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 849 }
 850
 851 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 852 {
 853         u32 l;
 854         u32 mask;
 855
 856         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 857         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 858         mask = (l >> 8) & 0x0f;
 859         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 860 }
 861
 862 static int gpmc_cs_mem_enabled(int cs)
 863 {
 864         u32 l;
 865
 866         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 867         return l & GPMC_CONFIG7_CSVALID;
 868 }
 869
 870 static void gpmc_cs_set_reserved(int cs, int reserved)
 871 {
 872         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 873
 874         gpmc->flags |= GPMC_CS_RESERVED;
 875 }
 876
 877 static bool gpmc_cs_reserved(int cs)
 878 {
 879         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 880
 881         return gpmc->flags & GPMC_CS_RESERVED;
 882 }
 883
 884 static void gpmc_cs_set_name(int cs, const char *name)
 885 {
 886         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 887
 888         gpmc->name = name;
 889 }
 890
 891 static const char *gpmc_cs_get_name(int cs)
 892 {
 893         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 894
 895         return gpmc->name;
 896 }
 897
 898 static unsigned long gpmc_mem_align(unsigned long size)
 899 {
 900         int order;
 901
 902         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 903         order = GPMC_CHUNK_SHIFT - 1;
 904         do {
 905                 size >>= 1;
 906                 order++;
 907         } while (size);
 908         size = 1 << order;
 909         return size;
 910 }
 911
 912 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 913 {
 914         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 915         struct resource *res = &gpmc->mem;
 916         int r;
 917
 918         size = gpmc_mem_align(size);
 919         spin_lock(&gpmc_mem_lock);
 920         res->start = base;
 921         res->end = base + size - 1;
 922         r = request_resource(&gpmc_mem_root, res);
 923         spin_unlock(&gpmc_mem_lock);
 924
 925         return r;
 926 }
 927
 928 static int gpmc_cs_delete_mem(int cs)
 929 {
 930         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 931         struct resource *res = &gpmc->mem;
 932         int r;
 933
 934         spin_lock(&gpmc_mem_lock);
 935         r = release_resource(res);
 936         res->start = 0;
 937         res->end = 0;
 938         spin_unlock(&gpmc_mem_lock);
 939
 940         return r;
 941 }
 942
 943 /**
 944  * gpmc_cs_remap - remaps a chip-select physical base address
 945  * @cs:         chip-select to remap
 946  * @base:       physical base address to re-map chip-select to
 947  *
 948  * Re-maps a chip-select to a new physical base address specified by
 949  * "base". Returns 0 on success and appropriate negative error code
 950  * on failure.
 951  */
 952 static int gpmc_cs_remap(int cs, u32 base)
 953 {
 954         int ret;
 955         u32 old_base, size;
 956
 957         if (cs > gpmc_cs_num) {
 958                 pr_err("%s: requested chip-select is disabled\n", __func__);
 959                 return -ENODEV;
 960         }
 961
 962         /*
 963          * Make sure we ignore any device offsets from the GPMC partition
 964          * allocated for the chip select and that the new base confirms
 965          * to the GPMC 16MB minimum granularity.
 966          */
 967         base &= ~(SZ_16M - 1);
 968
 969         gpmc_cs_get_memconf(cs, &old_base, &size);
 970         if (base == old_base)
 971                 return 0;
 972
 973         ret = gpmc_cs_delete_mem(cs);
 974         if (ret < 0)
 975                 return ret;
 976
 977         ret = gpmc_cs_insert_mem(cs, base, size);
 978         if (ret < 0)
 979                 return ret;
 980
 981         ret = gpmc_cs_set_memconf(cs, base, size);
 982
 983         return ret;
 984 }
 985
 986 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 987 {
 988         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 989         struct resource *res = &gpmc->mem;
 990         int r = -1;
 991
 992         if (cs > gpmc_cs_num) {
 993                 pr_err("%s: requested chip-select is disabled\n", __func__);
 994                 return -ENODEV;
 995         }
 996         size = gpmc_mem_align(size);
 997         if (size > (1 << GPMC_SECTION_SHIFT))
 998                 return -ENOMEM;
 999
1000         spin_lock(&gpmc_mem_lock);
1001         if (gpmc_cs_reserved(cs)) {
1002                 r = -EBUSY;
1003                 goto out;
1004         }
1005         if (gpmc_cs_mem_enabled(cs))
1006                 r = adjust_resource(res, res->start & ~(size - 1), size);
1007         if (r < 0)
1008                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1009                                       size, NULL, NULL);
1010         if (r < 0)
1011                 goto out;
1012
1013         /* Disable CS while changing base address and size mask */
1014         gpmc_cs_disable_mem(cs);
1015
1016         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1017         if (r < 0) {
1018                 release_resource(res);
1019                 goto out;
1020         }
1021
1022         /* Enable CS */
1023         gpmc_cs_enable_mem(cs);
1024         *base = res->start;
1025         gpmc_cs_set_reserved(cs, 1);
1026 out:
1027         spin_unlock(&gpmc_mem_lock);
1028         return r;
1029 }
1030 EXPORT_SYMBOL(gpmc_cs_request);
1031
1032 void gpmc_cs_free(int cs)
1033 {
1034         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1035         struct resource *res = &gpmc->mem;
1036
1037         spin_lock(&gpmc_mem_lock);
1038         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1039                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1040                 BUG();
1041                 spin_unlock(&gpmc_mem_lock);
1042                 return;
1043         }
1044         gpmc_cs_disable_mem(cs);
1045         if (res->flags)
1046                 release_resource(res);
1047         gpmc_cs_set_reserved(cs, 0);
1048         spin_unlock(&gpmc_mem_lock);
1049 }
1050 EXPORT_SYMBOL(gpmc_cs_free);
1051
1052 /**
1053  * gpmc_configure - write request to configure gpmc
1054  * @cmd: command type
1055  * @wval: value to write
1056  * @return status of the operation
1057  */
1058 int gpmc_configure(int cmd, int wval)
1059 {
1060         u32 regval;
1061
1062         switch (cmd) {
1063         case GPMC_CONFIG_WP:
1064                 regval = gpmc_read_reg(GPMC_CONFIG);
1065                 if (wval)
1066                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1067                 else
1068                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1069                 gpmc_write_reg(GPMC_CONFIG, regval);
1070                 break;
1071
1072         default:
1073                 pr_err("%s: command not supported\n", __func__);
1074                 return -EINVAL;
1075         }
1076
1077         return 0;
1078 }
1079 EXPORT_SYMBOL(gpmc_configure);
1080
1081 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1082 {
1083         int i;
1084
1085         reg->gpmc_status = gpmc_base + GPMC_STATUS;
1086         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1087                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1088         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1089                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1090         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1091                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1092         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1093         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1094         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1095         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1096         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1097         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1098         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1099         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1100
1101         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1102                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1103                                            GPMC_BCH_SIZE * i;
1104                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1105                                            GPMC_BCH_SIZE * i;
1106                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1107                                            GPMC_BCH_SIZE * i;
1108                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1109                                            GPMC_BCH_SIZE * i;
1110                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1111                                            i * GPMC_BCH_SIZE;
1112                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1113                                            i * GPMC_BCH_SIZE;
1114                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1115                                            i * GPMC_BCH_SIZE;
1116         }
1117 }
1118
1119 static bool gpmc_nand_writebuffer_empty(void)
1120 {
1121         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1122                 return true;
1123
1124         return false;
1125 }
1126
1127 static struct gpmc_nand_ops nand_ops = {
1128         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1129 };
1130
1131 /**
1132  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1133  * @regs: the GPMC NAND register map exclusive for NAND use.
1134  * @cs: GPMC chip select number on which the NAND sits. The
1135  *      register map returned will be specific to this chip select.
1136  *
1137  * Returns NULL on error e.g. invalid cs.
1138  */
1139 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1140 {
1141         if (cs >= gpmc_cs_num)
1142                 return NULL;
1143
1144         gpmc_update_nand_reg(reg, cs);
1145
1146         return &nand_ops;
1147 }
1148 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1149
1150 int gpmc_get_client_irq(unsigned irq_config)
1151 {
1152         if (!gpmc_irq_domain) {
1153                 pr_warn("%s called before GPMC IRQ domain available\n",
1154                         __func__);
1155                 return 0;
1156         }
1157
1158         if (irq_config >= GPMC_NR_IRQ)
1159                 return 0;
1160
1161         return irq_create_mapping(gpmc_irq_domain, irq_config);
1162 }
1163
1164 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1165 {
1166         u32 regval;
1167
1168         regval = gpmc_read_reg(GPMC_IRQENABLE);
1169         if (endis)
1170                 regval |= BIT(hwirq);
1171         else
1172                 regval &= ~BIT(hwirq);
1173         gpmc_write_reg(GPMC_IRQENABLE, regval);
1174
1175         return 0;
1176 }
1177
1178 static void gpmc_irq_disable(struct irq_data *p)
1179 {
1180         gpmc_irq_endis(p->hwirq, false);
1181 }
1182
1183 static void gpmc_irq_enable(struct irq_data *p)
1184 {
1185         gpmc_irq_endis(p->hwirq, true);
1186 }
1187
1188 static void gpmc_irq_noop(struct irq_data *data) { }
1189
1190 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1191
1192 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1193                         irq_hw_number_t hw)
1194 {
1195         struct gpmc_device *gpmc = d->host_data;
1196
1197         irq_set_chip_data(virq, gpmc);
1198         irq_set_chip_and_handler(virq, &gpmc->irq_chip, handle_simple_irq);
1199         irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1200
1201         return 0;
1202 }
1203
1204 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1205         .map    = gpmc_irq_map,
1206         .xlate  = irq_domain_xlate_twocell,
1207 };
1208
1209 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1210 {
1211         int hwirq, virq;
1212         u32 regval;
1213         struct gpmc_device *gpmc = data;
1214
1215         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1216
1217         if (!regval)
1218                 return IRQ_NONE;
1219
1220         for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++) {
1221                 if (regval & BIT(hwirq)) {
1222                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1223                         if (!virq) {
1224                                 dev_warn(gpmc->dev,
1225                                          "spurious irq detected hwirq %d, virq %d\n",
1226                                          hwirq, virq);
1227                         }
1228
1229                         generic_handle_irq(virq);
1230                 }
1231         }
1232
1233         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1234
1235         return IRQ_HANDLED;
1236 }
1237
1238 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1239 {
1240         u32 regval;
1241         int rc;
1242
1243         /* Disable interrupts */
1244         gpmc_write_reg(GPMC_IRQENABLE, 0);
1245
1246         /* clear interrupts */
1247         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1248         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1249
1250         gpmc->irq_chip.name = "gpmc";
1251         gpmc->irq_chip.irq_startup = gpmc_irq_noop_ret;
1252         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1253         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1254         gpmc->irq_chip.irq_shutdown = gpmc_irq_noop;
1255         gpmc->irq_chip.irq_ack = gpmc_irq_noop;
1256         gpmc->irq_chip.irq_mask = gpmc_irq_noop;
1257         gpmc->irq_chip.irq_unmask = gpmc_irq_noop;
1258
1259         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1260                                                 GPMC_NR_IRQ,
1261                                                 &gpmc_irq_domain_ops,
1262                                                 gpmc);
1263         if (!gpmc_irq_domain) {
1264                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1265                 return -ENODEV;
1266         }
1267
1268         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1269         if (rc) {
1270                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1271                         gpmc->irq, rc);
1272                 irq_domain_remove(gpmc_irq_domain);
1273                 gpmc_irq_domain = NULL;
1274         }
1275
1276         return rc;
1277 }
1278
1279 static int gpmc_free_irq(struct gpmc_device *gpmc)
1280 {
1281         int hwirq;
1282
1283         free_irq(gpmc->irq, gpmc);
1284
1285         for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++)
1286                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1287
1288         irq_domain_remove(gpmc_irq_domain);
1289         gpmc_irq_domain = NULL;
1290
1291         return 0;
1292 }
1293
1294 static void gpmc_mem_exit(void)
1295 {
1296         int cs;
1297
1298         for (cs = 0; cs < gpmc_cs_num; cs++) {
1299                 if (!gpmc_cs_mem_enabled(cs))
1300                         continue;
1301                 gpmc_cs_delete_mem(cs);
1302         }
1303
1304 }
1305
1306 static void gpmc_mem_init(void)
1307 {
1308         int cs;
1309
1310         gpmc_mem_root.start = GPMC_MEM_START;
1311         gpmc_mem_root.end = GPMC_MEM_END;
1312
1313         /* Reserve all regions that has been set up by bootloader */
1314         for (cs = 0; cs < gpmc_cs_num; cs++) {
1315                 u32 base, size;
1316
1317                 if (!gpmc_cs_mem_enabled(cs))
1318                         continue;
1319                 gpmc_cs_get_memconf(cs, &base, &size);
1320                 if (gpmc_cs_insert_mem(cs, base, size)) {
1321                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1322                                 __func__, cs, base, base + size);
1323                         gpmc_cs_disable_mem(cs);
1324                 }
1325         }
1326 }
1327
1328 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1329 {
1330         u32 temp;
1331         int div;
1332
1333         div = gpmc_calc_divider(sync_clk);
1334         temp = gpmc_ps_to_ticks(time_ps);
1335         temp = (temp + div - 1) / div;
1336         return gpmc_ticks_to_ps(temp * div);
1337 }
1338
1339 /* XXX: can the cycles be avoided ? */
1340 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1341                                        struct gpmc_device_timings *dev_t,
1342                                        bool mux)
1343 {
1344         u32 temp;
1345
1346         /* adv_rd_off */
1347         temp = dev_t->t_avdp_r;
1348         /* XXX: mux check required ? */
1349         if (mux) {
1350                 /* XXX: t_avdp not to be required for sync, only added for tusb
1351                  * this indirectly necessitates requirement of t_avdp_r and
1352                  * t_avdp_w instead of having a single t_avdp
1353                  */
1354                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1355                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1356         }
1357         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1358
1359         /* oe_on */
1360         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1361         if (mux) {
1362                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1363                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1364                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1365         }
1366         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1367
1368         /* access */
1369         /* XXX: any scope for improvement ?, by combining oe_on
1370          * and clk_activation, need to check whether
1371          * access = clk_activation + round to sync clk ?
1372          */
1373         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1374         temp += gpmc_t->clk_activation;
1375         if (dev_t->cyc_oe)
1376                 temp = max_t(u32, temp, gpmc_t->oe_on +
1377                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1378         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1379
1380         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1381         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1382
1383         /* rd_cycle */
1384         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1385         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1386                                                         gpmc_t->access;
1387         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1388         if (dev_t->t_ce_rdyz)
1389                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1390         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1391
1392         return 0;
1393 }
1394
1395 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1396                                         struct gpmc_device_timings *dev_t,
1397                                         bool mux)
1398 {
1399         u32 temp;
1400
1401         /* adv_wr_off */
1402         temp = dev_t->t_avdp_w;
1403         if (mux) {
1404                 temp = max_t(u32, temp,
1405                         gpmc_t->clk_activation + dev_t->t_avdh);
1406                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1407         }
1408         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1409
1410         /* wr_data_mux_bus */
1411         temp = max_t(u32, dev_t->t_weasu,
1412                         gpmc_t->clk_activation + dev_t->t_rdyo);
1413         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1414          * and in that case remember to handle we_on properly
1415          */
1416         if (mux) {
1417                 temp = max_t(u32, temp,
1418                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1419                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1420                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1421         }
1422         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1423
1424         /* we_on */
1425         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1426                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1427         else
1428                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1429
1430         /* wr_access */
1431         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1432         gpmc_t->wr_access = gpmc_t->access;
1433
1434         /* we_off */
1435         temp = gpmc_t->we_on + dev_t->t_wpl;
1436         temp = max_t(u32, temp,
1437                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1438         temp = max_t(u32, temp,
1439                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1440         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1441
1442         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1443                                                         dev_t->t_wph);
1444
1445         /* wr_cycle */
1446         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1447         temp += gpmc_t->wr_access;
1448         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1449         if (dev_t->t_ce_rdyz)
1450                 temp = max_t(u32, temp,
1451                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1452         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1453
1454         return 0;
1455 }
1456
1457 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1458                                         struct gpmc_device_timings *dev_t,
1459                                         bool mux)
1460 {
1461         u32 temp;
1462
1463         /* adv_rd_off */
1464         temp = dev_t->t_avdp_r;
1465         if (mux)
1466                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1467         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1468
1469         /* oe_on */
1470         temp = dev_t->t_oeasu;
1471         if (mux)
1472                 temp = max_t(u32, temp,
1473                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1474         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1475
1476         /* access */
1477         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1478                                 gpmc_t->oe_on + dev_t->t_oe);
1479         temp = max_t(u32, temp,
1480                                 gpmc_t->cs_on + dev_t->t_ce);
1481         temp = max_t(u32, temp,
1482                                 gpmc_t->adv_on + dev_t->t_aa);
1483         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1484
1485         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1486         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1487
1488         /* rd_cycle */
1489         temp = max_t(u32, dev_t->t_rd_cycle,
1490                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1491         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1492         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1493
1494         return 0;
1495 }
1496
1497 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1498                                          struct gpmc_device_timings *dev_t,
1499                                          bool mux)
1500 {
1501         u32 temp;
1502
1503         /* adv_wr_off */
1504         temp = dev_t->t_avdp_w;
1505         if (mux)
1506                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1507         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1508
1509         /* wr_data_mux_bus */
1510         temp = dev_t->t_weasu;
1511         if (mux) {
1512                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1513                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1514                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1515         }
1516         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1517
1518         /* we_on */
1519         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1520                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1521         else
1522                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1523
1524         /* we_off */
1525         temp = gpmc_t->we_on + dev_t->t_wpl;
1526         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1527
1528         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1529                                                         dev_t->t_wph);
1530
1531         /* wr_cycle */
1532         temp = max_t(u32, dev_t->t_wr_cycle,
1533                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1534         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1535
1536         return 0;
1537 }
1538
1539 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1540                         struct gpmc_device_timings *dev_t)
1541 {
1542         u32 temp;
1543
1544         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1545                                                 gpmc_get_fclk_period();
1546
1547         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1548                                         dev_t->t_bacc,
1549                                         gpmc_t->sync_clk);
1550
1551         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1552         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1553
1554         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1555                 return 0;
1556
1557         if (dev_t->ce_xdelay)
1558                 gpmc_t->bool_timings.cs_extra_delay = true;
1559         if (dev_t->avd_xdelay)
1560                 gpmc_t->bool_timings.adv_extra_delay = true;
1561         if (dev_t->oe_xdelay)
1562                 gpmc_t->bool_timings.oe_extra_delay = true;
1563         if (dev_t->we_xdelay)
1564                 gpmc_t->bool_timings.we_extra_delay = true;
1565
1566         return 0;
1567 }
1568
1569 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1570                                     struct gpmc_device_timings *dev_t,
1571                                     bool sync)
1572 {
1573         u32 temp;
1574
1575         /* cs_on */
1576         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1577
1578         /* adv_on */
1579         temp = dev_t->t_avdasu;
1580         if (dev_t->t_ce_avd)
1581                 temp = max_t(u32, temp,
1582                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1583         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1584
1585         if (sync)
1586                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1587
1588         return 0;
1589 }
1590
1591 /* TODO: remove this function once all peripherals are confirmed to
1592  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1593  * has to be modified to handle timings in ps instead of ns
1594 */
1595 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1596 {
1597         t->cs_on /= 1000;
1598         t->cs_rd_off /= 1000;
1599         t->cs_wr_off /= 1000;
1600         t->adv_on /= 1000;
1601         t->adv_rd_off /= 1000;
1602         t->adv_wr_off /= 1000;
1603         t->we_on /= 1000;
1604         t->we_off /= 1000;
1605         t->oe_on /= 1000;
1606         t->oe_off /= 1000;
1607         t->page_burst_access /= 1000;
1608         t->access /= 1000;
1609         t->rd_cycle /= 1000;
1610         t->wr_cycle /= 1000;
1611         t->bus_turnaround /= 1000;
1612         t->cycle2cycle_delay /= 1000;
1613         t->wait_monitoring /= 1000;
1614         t->clk_activation /= 1000;
1615         t->wr_access /= 1000;
1616         t->wr_data_mux_bus /= 1000;
1617 }
1618
1619 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1620                       struct gpmc_settings *gpmc_s,
1621                       struct gpmc_device_timings *dev_t)
1622 {
1623         bool mux = false, sync = false;
1624
1625         if (gpmc_s) {
1626                 mux = gpmc_s->mux_add_data ? true : false;
1627                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1628         }
1629
1630         memset(gpmc_t, 0, sizeof(*gpmc_t));
1631
1632         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1633
1634         if (gpmc_s && gpmc_s->sync_read)
1635                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1636         else
1637                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1638
1639         if (gpmc_s && gpmc_s->sync_write)
1640                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1641         else
1642                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1643
1644         /* TODO: remove, see function definition */
1645         gpmc_convert_ps_to_ns(gpmc_t);
1646
1647         return 0;
1648 }
1649
1650 /**
1651  * gpmc_cs_program_settings - programs non-timing related settings
1652  * @cs:         GPMC chip-select to program
1653  * @p:          pointer to GPMC settings structure
1654  *
1655  * Programs non-timing related settings for a GPMC chip-select, such as
1656  * bus-width, burst configuration, etc. Function should be called once
1657  * for each chip-select that is being used and must be called before
1658  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1659  * register will be initialised to zero by this function. Returns 0 on
1660  * success and appropriate negative error code on failure.
1661  */
1662 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1663 {
1664         u32 config1;
1665
1666         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1667                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1668                 return -EINVAL;
1669         }
1670
1671         /* Address-data multiplexing not supported for NAND devices */
1672         if (p->device_nand && p->mux_add_data) {
1673                 pr_err("%s: invalid configuration!\n", __func__);
1674                 return -EINVAL;
1675         }
1676
1677         if ((p->mux_add_data > GPMC_MUX_AD) ||
1678             ((p->mux_add_data == GPMC_MUX_AAD) &&
1679              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1680                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1681                 return -EINVAL;
1682         }
1683
1684         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1685         if (p->burst_read || p->burst_write) {
1686                 switch (p->burst_len) {
1687                 case GPMC_BURST_4:
1688                 case GPMC_BURST_8:
1689                 case GPMC_BURST_16:
1690                         break;
1691                 default:
1692                         pr_err("%s: invalid page/burst-length (%d)\n",
1693                                __func__, p->burst_len);
1694                         return -EINVAL;
1695                 }
1696         }
1697
1698         if (p->wait_pin > gpmc_nr_waitpins) {
1699                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1700                 return -EINVAL;
1701         }
1702
1703         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1704
1705         if (p->sync_read)
1706                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1707         if (p->sync_write)
1708                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1709         if (p->wait_on_read)
1710                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1711         if (p->wait_on_write)
1712                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1713         if (p->wait_on_read || p->wait_on_write)
1714                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1715         if (p->device_nand)
1716                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1717         if (p->mux_add_data)
1718                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1719         if (p->burst_read)
1720                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1721         if (p->burst_write)
1722                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1723         if (p->burst_read || p->burst_write) {
1724                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1725                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1726         }
1727
1728         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1729
1730         return 0;
1731 }
1732
1733 #ifdef CONFIG_OF
1734 static const struct of_device_id gpmc_dt_ids[] = {
1735         { .compatible = "ti,omap2420-gpmc" },
1736         { .compatible = "ti,omap2430-gpmc" },
1737         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1738         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1739         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1740         { }
1741 };
1742 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1743
1744 /**
1745  * gpmc_read_settings_dt - read gpmc settings from device-tree
1746  * @np:         pointer to device-tree node for a gpmc child device
1747  * @p:          pointer to gpmc settings structure
1748  *
1749  * Reads the GPMC settings for a GPMC child device from device-tree and
1750  * stores them in the GPMC settings structure passed. The GPMC settings
1751  * structure is initialised to zero by this function and so any
1752  * previously stored settings will be cleared.
1753  */
1754 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1755 {
1756         memset(p, 0, sizeof(struct gpmc_settings));
1757
1758         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1759         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1760         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1761         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1762
1763         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1764                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1765                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1766                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1767                 if (!p->burst_read && !p->burst_write)
1768                         pr_warn("%s: page/burst-length set but not used!\n",
1769                                 __func__);
1770         }
1771
1772         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1773                 p->wait_on_read = of_property_read_bool(np,
1774                                                         "gpmc,wait-on-read");
1775                 p->wait_on_write = of_property_read_bool(np,
1776                                                          "gpmc,wait-on-write");
1777                 if (!p->wait_on_read && !p->wait_on_write)
1778                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1779                                  __func__);
1780         }
1781 }
1782
1783 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1784                                                 struct gpmc_timings *gpmc_t)
1785 {
1786         struct gpmc_bool_timings *p;
1787
1788         if (!np || !gpmc_t)
1789                 return;
1790
1791         memset(gpmc_t, 0, sizeof(*gpmc_t));
1792
1793         /* minimum clock period for syncronous mode */
1794         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1795
1796         /* chip select timtings */
1797         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1798         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1799         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1800
1801         /* ADV signal timings */
1802         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1803         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1804         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1805         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1806                              &gpmc_t->adv_aad_mux_on);
1807         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1808                              &gpmc_t->adv_aad_mux_rd_off);
1809         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1810                              &gpmc_t->adv_aad_mux_wr_off);
1811
1812         /* WE signal timings */
1813         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1814         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1815
1816         /* OE signal timings */
1817         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1818         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1819         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1820                              &gpmc_t->oe_aad_mux_on);
1821         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1822                              &gpmc_t->oe_aad_mux_off);
1823
1824         /* access and cycle timings */
1825         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1826                              &gpmc_t->page_burst_access);
1827         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1828         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1829         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1830         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1831                              &gpmc_t->bus_turnaround);
1832         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1833                              &gpmc_t->cycle2cycle_delay);
1834         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1835                              &gpmc_t->wait_monitoring);
1836         of_property_read_u32(np, "gpmc,clk-activation-ns",
1837                              &gpmc_t->clk_activation);
1838
1839         /* only applicable to OMAP3+ */
1840         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1841         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1842                              &gpmc_t->wr_data_mux_bus);
1843
1844         /* bool timing parameters */
1845         p = &gpmc_t->bool_timings;
1846
1847         p->cycle2cyclediffcsen =
1848                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1849         p->cycle2cyclesamecsen =
1850                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1851         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1852         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1853         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1854         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1855         p->time_para_granularity =
1856                 of_property_read_bool(np, "gpmc,time-para-granularity");
1857 }
1858
1859 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1860 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1861                                  struct device_node *child)
1862 {
1863         u32 val;
1864         struct omap_onenand_platform_data *gpmc_onenand_data;
1865
1866         if (of_property_read_u32(child, "reg", &val) < 0) {
1867                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1868                         child->full_name);
1869                 return -ENODEV;
1870         }
1871
1872         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1873                                          GFP_KERNEL);
1874         if (!gpmc_onenand_data)
1875                 return -ENOMEM;
1876
1877         gpmc_onenand_data->cs = val;
1878         gpmc_onenand_data->of_node = child;
1879         gpmc_onenand_data->dma_channel = -1;
1880
1881         if (!of_property_read_u32(child, "dma-channel", &val))
1882                 gpmc_onenand_data->dma_channel = val;
1883
1884         gpmc_onenand_init(gpmc_onenand_data);
1885
1886         return 0;
1887 }
1888 #else
1889 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1890                                     struct device_node *child)
1891 {
1892         return 0;
1893 }
1894 #endif
1895
1896 /**
1897  * gpmc_probe_generic_child - configures the gpmc for a child device
1898  * @pdev:       pointer to gpmc platform device
1899  * @child:      pointer to device-tree node for child device
1900  *
1901  * Allocates and configures a GPMC chip-select for a child device.
1902  * Returns 0 on success and appropriate negative error code on failure.
1903  */
1904 static int gpmc_probe_generic_child(struct platform_device *pdev,
1905                                 struct device_node *child)
1906 {
1907         struct gpmc_settings gpmc_s;
1908         struct gpmc_timings gpmc_t;
1909         struct resource res;
1910         unsigned long base;
1911         const char *name;
1912         int ret, cs;
1913         u32 val;
1914
1915         if (of_property_read_u32(child, "reg", &cs) < 0) {
1916                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1917                         child->full_name);
1918                 return -ENODEV;
1919         }
1920
1921         if (of_address_to_resource(child, 0, &res) < 0) {
1922                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1923                         child->full_name);
1924                 return -ENODEV;
1925         }
1926
1927         /*
1928          * Check if we have multiple instances of the same device
1929          * on a single chip select. If so, use the already initialized
1930          * timings.
1931          */
1932         name = gpmc_cs_get_name(cs);
1933         if (name && child->name && of_node_cmp(child->name, name) == 0)
1934                         goto no_timings;
1935
1936         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1937         if (ret < 0) {
1938                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1939                 return ret;
1940         }
1941         gpmc_cs_set_name(cs, child->name);
1942
1943         gpmc_read_settings_dt(child, &gpmc_s);
1944         gpmc_read_timings_dt(child, &gpmc_t);
1945
1946         /*
1947          * For some GPMC devices we still need to rely on the bootloader
1948          * timings because the devices can be connected via FPGA.
1949          * REVISIT: Add timing support from slls644g.pdf.
1950          */
1951         if (!gpmc_t.cs_rd_off) {
1952                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1953                         cs);
1954                 gpmc_cs_show_timings(cs,
1955                                      "please add GPMC bootloader timings to .dts");
1956                 goto no_timings;
1957         }
1958
1959         /* CS must be disabled while making changes to gpmc configuration */
1960         gpmc_cs_disable_mem(cs);
1961
1962         /*
1963          * FIXME: gpmc_cs_request() will map the CS to an arbitary
1964          * location in the gpmc address space. When booting with
1965          * device-tree we want the NOR flash to be mapped to the
1966          * location specified in the device-tree blob. So remap the
1967          * CS to this location. Once DT migration is complete should
1968          * just make gpmc_cs_request() map a specific address.
1969          */
1970         ret = gpmc_cs_remap(cs, res.start);
1971         if (ret < 0) {
1972                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1973                         cs, &res.start);
1974                 if (res.start < GPMC_MEM_START) {
1975                         dev_info(&pdev->dev,
1976                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
1977                                  cs, GPMC_MEM_START);
1978                 } else if (res.end > GPMC_MEM_END) {
1979                         dev_info(&pdev->dev,
1980                                  "GPMC CS %d end cannot be greater than 0x%x\n",
1981                                  cs, GPMC_MEM_END);
1982                 }
1983                 goto err;
1984         }
1985
1986         if (of_node_cmp(child->name, "nand") == 0) {
1987                 /* Warn about older DT blobs with no compatible property */
1988                 if (!of_property_read_bool(child, "compatible")) {
1989                         dev_warn(&pdev->dev,
1990                                  "Incompatible NAND node: missing compatible");
1991                         ret = -EINVAL;
1992                         goto err;
1993                 }
1994         }
1995
1996         if (of_device_is_compatible(child, "ti,omap2-nand")) {
1997                 /* NAND specific setup */
1998                 val = of_get_nand_bus_width(child);
1999                 switch (val) {
2000                 case 8:
2001                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2002                         break;
2003                 case 16:
2004                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2005                         break;
2006                 default:
2007                         dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2008                                 child->name);
2009                         ret = -EINVAL;
2010                         goto err;
2011                 }
2012
2013                 /* disable write protect */
2014                 gpmc_configure(GPMC_CONFIG_WP, 0);
2015                 gpmc_s.device_nand = true;
2016         } else {
2017                 ret = of_property_read_u32(child, "bank-width",
2018                                            &gpmc_s.device_width);
2019                 if (ret < 0)
2020                         goto err;
2021         }
2022
2023         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2024         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2025         if (ret < 0)
2026                 goto err;
2027
2028         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2029         if (ret) {
2030                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2031                         child->name);
2032                 goto err;
2033         }
2034
2035         /* Clear limited address i.e. enable A26-A11 */
2036         val = gpmc_read_reg(GPMC_CONFIG);
2037         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2038         gpmc_write_reg(GPMC_CONFIG, val);
2039
2040         /* Enable CS region */
2041         gpmc_cs_enable_mem(cs);
2042
2043 no_timings:
2044
2045         /* create platform device, NULL on error or when disabled */
2046         if (!of_platform_device_create(child, NULL, &pdev->dev))
2047                 goto err_child_fail;
2048
2049         /* is child a common bus? */
2050         if (of_match_node(of_default_bus_match_table, child))
2051                 /* create children and other common bus children */
2052                 if (of_platform_populate(child, of_default_bus_match_table,
2053                                          NULL, &pdev->dev))
2054                         goto err_child_fail;
2055
2056         return 0;
2057
2058 err_child_fail:
2059
2060         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2061         ret = -ENODEV;
2062
2063 err:
2064         gpmc_cs_free(cs);
2065
2066         return ret;
2067 }
2068
2069 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2070 {
2071         return 1;       /* we're input only */
2072 }
2073
2074 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2075                                      unsigned int offset)
2076 {
2077         return 0;       /* we're input only */
2078 }
2079
2080 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2081                                       unsigned int offset, int value)
2082 {
2083         return -EINVAL; /* we're input only */
2084 }
2085
2086 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2087                           int value)
2088 {
2089 }
2090
2091 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2092 {
2093         u32 reg;
2094
2095         offset += 8;
2096
2097         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2098
2099         return !!reg;
2100 }
2101
2102 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2103 {
2104         int ret;
2105
2106         gpmc->gpio_chip.parent = gpmc->dev;
2107         gpmc->gpio_chip.owner = THIS_MODULE;
2108         gpmc->gpio_chip.label = DEVICE_NAME;
2109         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2110         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2111         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2112         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2113         gpmc->gpio_chip.set = gpmc_gpio_set;
2114         gpmc->gpio_chip.get = gpmc_gpio_get;
2115         gpmc->gpio_chip.base = -1;
2116
2117         ret = gpiochip_add(&gpmc->gpio_chip);
2118         if (ret < 0) {
2119                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2120                 return ret;
2121         }
2122
2123         return 0;
2124 }
2125
2126 static void gpmc_gpio_exit(struct gpmc_device *gpmc)
2127 {
2128         gpiochip_remove(&gpmc->gpio_chip);
2129 }
2130
2131 static int gpmc_probe_dt(struct platform_device *pdev)
2132 {
2133         int ret;
2134         const struct of_device_id *of_id =
2135                 of_match_device(gpmc_dt_ids, &pdev->dev);
2136
2137         if (!of_id)
2138                 return 0;
2139
2140         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2141                                    &gpmc_cs_num);
2142         if (ret < 0) {
2143                 pr_err("%s: number of chip-selects not defined\n", __func__);
2144                 return ret;
2145         } else if (gpmc_cs_num < 1) {
2146                 pr_err("%s: all chip-selects are disabled\n", __func__);
2147                 return -EINVAL;
2148         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2149                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2150                                          __func__, GPMC_CS_NUM);
2151                 return -EINVAL;
2152         }
2153
2154         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2155                                    &gpmc_nr_waitpins);
2156         if (ret < 0) {
2157                 pr_err("%s: number of wait pins not found!\n", __func__);
2158                 return ret;
2159         }
2160
2161         return 0;
2162 }
2163
2164 static int gpmc_probe_dt_children(struct platform_device *pdev)
2165 {
2166         int ret;
2167         struct device_node *child;
2168
2169         for_each_available_child_of_node(pdev->dev.of_node, child) {
2170
2171                 if (!child->name)
2172                         continue;
2173
2174                 if (of_node_cmp(child->name, "onenand") == 0)
2175                         ret = gpmc_probe_onenand_child(pdev, child);
2176                 else
2177                         ret = gpmc_probe_generic_child(pdev, child);
2178
2179                 if (ret)
2180                         return ret;
2181         }
2182
2183         return 0;
2184 }
2185 #else
2186 static int gpmc_probe_dt(struct platform_device *pdev)
2187 {
2188         return 0;
2189 }
2190
2191 static int gpmc_probe_dt_children(struct platform_device *pdev)
2192 {
2193         return 0;
2194 }
2195 #endif
2196
2197 static int gpmc_probe(struct platform_device *pdev)
2198 {
2199         int rc;
2200         u32 l;
2201         struct resource *res;
2202         struct gpmc_device *gpmc;
2203
2204         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2205         if (!gpmc)
2206                 return -ENOMEM;
2207
2208         gpmc->dev = &pdev->dev;
2209         platform_set_drvdata(pdev, gpmc);
2210
2211         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2212         if (res == NULL)
2213                 return -ENOENT;
2214
2215         phys_base = res->start;
2216         mem_size = resource_size(res);
2217
2218         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2219         if (IS_ERR(gpmc_base))
2220                 return PTR_ERR(gpmc_base);
2221
2222         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2223         if (!res) {
2224                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2225                 return -ENOENT;
2226         }
2227
2228         gpmc->irq = res->start;
2229
2230         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2231         if (IS_ERR(gpmc_l3_clk)) {
2232                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2233                 return PTR_ERR(gpmc_l3_clk);
2234         }
2235
2236         if (!clk_get_rate(gpmc_l3_clk)) {
2237                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2238                 return -EINVAL;
2239         }
2240
2241         if (pdev->dev.of_node) {
2242                 rc = gpmc_probe_dt(pdev);
2243                 if (rc)
2244                         return rc;
2245         } else {
2246                 gpmc_cs_num = GPMC_CS_NUM;
2247                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2248         }
2249
2250         pm_runtime_enable(&pdev->dev);
2251         pm_runtime_get_sync(&pdev->dev);
2252
2253         l = gpmc_read_reg(GPMC_REVISION);
2254
2255         /*
2256          * FIXME: Once device-tree migration is complete the below flags
2257          * should be populated based upon the device-tree compatible
2258          * string. For now just use the IP revision. OMAP3+ devices have
2259          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2260          * devices support the addr-addr-data multiplex protocol.
2261          *
2262          * GPMC IP revisions:
2263          * - OMAP24xx                   = 2.0
2264          * - OMAP3xxx                   = 5.0
2265          * - OMAP44xx/54xx/AM335x       = 6.0
2266          */
2267         if (GPMC_REVISION_MAJOR(l) > 0x4)
2268                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2269         if (GPMC_REVISION_MAJOR(l) > 0x5)
2270                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2271         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2272                  GPMC_REVISION_MINOR(l));
2273
2274         gpmc_mem_init();
2275         rc = gpmc_gpio_init(gpmc);
2276         if (rc)
2277                 goto gpio_init_failed;
2278
2279         rc = gpmc_setup_irq(gpmc);
2280         if (rc) {
2281                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2282                 goto setup_irq_failed;
2283         }
2284
2285         rc = gpmc_probe_dt_children(pdev);
2286         if (rc < 0) {
2287                 dev_err(gpmc->dev, "failed to probe DT children\n");
2288                 goto dt_children_failed;
2289         }
2290
2291         return 0;
2292
2293 dt_children_failed:
2294         gpmc_free_irq(gpmc);
2295 setup_irq_failed:
2296         gpmc_gpio_exit(gpmc);
2297 gpio_init_failed:
2298         gpmc_mem_exit();
2299         pm_runtime_put_sync(&pdev->dev);
2300         pm_runtime_disable(&pdev->dev);
2301
2302         return rc;
2303 }
2304
2305 static int gpmc_remove(struct platform_device *pdev)
2306 {
2307         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2308
2309         gpmc_free_irq(gpmc);
2310         gpmc_gpio_exit(gpmc);
2311         gpmc_mem_exit();
2312         pm_runtime_put_sync(&pdev->dev);
2313         pm_runtime_disable(&pdev->dev);
2314
2315         return 0;
2316 }
2317
2318 #ifdef CONFIG_PM_SLEEP
2319 static int gpmc_suspend(struct device *dev)
2320 {
2321         omap3_gpmc_save_context();
2322         pm_runtime_put_sync(dev);
2323         return 0;
2324 }
2325
2326 static int gpmc_resume(struct device *dev)
2327 {
2328         pm_runtime_get_sync(dev);
2329         omap3_gpmc_restore_context();
2330         return 0;
2331 }
2332 #endif
2333
2334 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2335
2336 static struct platform_driver gpmc_driver = {
2337         .probe          = gpmc_probe,
2338         .remove         = gpmc_remove,
2339         .driver         = {
2340                 .name   = DEVICE_NAME,
2341                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2342                 .pm     = &gpmc_pm_ops,
2343         },
2344 };
2345
2346 static __init int gpmc_init(void)
2347 {
2348         return platform_driver_register(&gpmc_driver);
2349 }
2350
2351 static __exit void gpmc_exit(void)
2352 {
2353         platform_driver_unregister(&gpmc_driver);
2354
2355 }
2356
2357 postcore_initcall(gpmc_init);
2358 module_exit(gpmc_exit);
2359
2360 static struct omap3_gpmc_regs gpmc_context;
2361
2362 void omap3_gpmc_save_context(void)
2363 {
2364         int i;
2365
2366         if (!gpmc_base)
2367                 return;
2368
2369         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2370         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2371         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2372         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2373         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2374         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2375         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2376         for (i = 0; i < gpmc_cs_num; i++) {
2377                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2378                 if (gpmc_context.cs_context[i].is_valid) {
2379                         gpmc_context.cs_context[i].config1 =
2380                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2381                         gpmc_context.cs_context[i].config2 =
2382                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2383                         gpmc_context.cs_context[i].config3 =
2384                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2385                         gpmc_context.cs_context[i].config4 =
2386                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2387                         gpmc_context.cs_context[i].config5 =
2388                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2389                         gpmc_context.cs_context[i].config6 =
2390                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2391                         gpmc_context.cs_context[i].config7 =
2392                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2393                 }
2394         }
2395 }
2396
2397 void omap3_gpmc_restore_context(void)
2398 {
2399         int i;
2400
2401         if (!gpmc_base)
2402                 return;
2403
2404         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2405         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2406         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2407         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2408         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2409         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2410         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2411         for (i = 0; i < gpmc_cs_num; i++) {
2412                 if (gpmc_context.cs_context[i].is_valid) {
2413                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2414                                 gpmc_context.cs_context[i].config1);
2415                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2416                                 gpmc_context.cs_context[i].config2);
2417                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2418                                 gpmc_context.cs_context[i].config3);
2419                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2420                                 gpmc_context.cs_context[i].config4);
2421                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2422                                 gpmc_context.cs_context[i].config5);
2423                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2424                                 gpmc_context.cs_context[i].config6);
2425                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2426                                 gpmc_context.cs_context[i].config7);
2427                 }
2428         }
2429 }