drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_mtd.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36 #include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  83
  84 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  85
  86 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  88 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  89 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  90 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  91 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  92
  93 #define GPMC_CS0_OFFSET         0x60
  94 #define GPMC_CS_SIZE            0x30
  95 #define GPMC_BCH_SIZE           0x10
  96
  97 #define GPMC_MEM_END            0x3FFFFFFF
  98
  99 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 100 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 101
 102 #define CS_NUM_SHIFT            24
 103 #define ENABLE_PREFETCH         (0x1 << 7)
 104 #define DMA_MPU_MODE            2
 105
 106 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 107 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 108
 109 #define GPMC_HAS_WR_ACCESS              0x1
 110 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 111 #define GPMC_HAS_MUX_AAD                0x4
 112
 113 #define GPMC_NR_WAITPINS                4
 114
 115 #define GPMC_CS_CONFIG1         0x00
 116 #define GPMC_CS_CONFIG2         0x04
 117 #define GPMC_CS_CONFIG3         0x08
 118 #define GPMC_CS_CONFIG4         0x0c
 119 #define GPMC_CS_CONFIG5         0x10
 120 #define GPMC_CS_CONFIG6         0x14
 121 #define GPMC_CS_CONFIG7         0x18
 122 #define GPMC_CS_NAND_COMMAND    0x1c
 123 #define GPMC_CS_NAND_ADDRESS    0x20
 124 #define GPMC_CS_NAND_DATA       0x24
 125
 126 /* Control Commands */
 127 #define GPMC_CONFIG_RDY_BSY     0x00000001
 128 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 129 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 130 #define GPMC_SET_IRQ_STATUS     0x00000004
 131
 132 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 133 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 134 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 135 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 136 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 137 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 138 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 139 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 140 /** CLKACTIVATIONTIME Max Ticks */
 141 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 142 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 143 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 144 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 145 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 146 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 147 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 148 /** WAITMONITORINGTIME Max Ticks */
 149 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 150 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 151 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 152 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 153 /** DEVICESIZE Max Value */
 154 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 155 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 156 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 157 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 158 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 159 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 160 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 161 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 162 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 163 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 164
 165 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 166 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 167 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 168 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 169 /* All CONFIG7 bits except reserved bits */
 170 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 171                                          GPMC_CONFIG7_CSVALID_MASK |     \
 172                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 173
 174 #define GPMC_DEVICETYPE_NOR             0
 175 #define GPMC_DEVICETYPE_NAND            2
 176 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 177 #define WR_RD_PIN_MONITORING            0x00600000
 178
 179 #define GPMC_ENABLE_IRQ         0x0000000d
 180
 181 /* ECC commands */
 182 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 183 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 184 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 185
 186 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 187  */
 188 #define GPMC_NR_IRQ             2
 189
 190 enum gpmc_clk_domain {
 191         GPMC_CD_FCLK,
 192         GPMC_CD_CLK
 193 };
 194
 195 struct gpmc_cs_data {
 196         const char *name;
 197
 198 #define GPMC_CS_RESERVED        (1 << 0)
 199         u32 flags;
 200
 201         struct resource mem;
 202 };
 203
 204 struct gpmc_client_irq  {
 205         unsigned                irq;
 206         u32                     bitmask;
 207 };
 208
 209 /* Structure to save gpmc cs context */
 210 struct gpmc_cs_config {
 211         u32 config1;
 212         u32 config2;
 213         u32 config3;
 214         u32 config4;
 215         u32 config5;
 216         u32 config6;
 217         u32 config7;
 218         int is_valid;
 219 };
 220
 221 /*
 222  * Structure to save/restore gpmc context
 223  * to support core off on OMAP3
 224  */
 225 struct omap3_gpmc_regs {
 226         u32 sysconfig;
 227         u32 irqenable;
 228         u32 timeout_ctrl;
 229         u32 config;
 230         u32 prefetch_config1;
 231         u32 prefetch_config2;
 232         u32 prefetch_control;
 233         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 234 };
 235
 236 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 237 static struct irq_chip gpmc_irq_chip;
 238 static int gpmc_irq_start;
 239
 240 static struct resource  gpmc_mem_root;
 241 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 242 static DEFINE_SPINLOCK(gpmc_mem_lock);
 243 /* Define chip-selects as reserved by default until probe completes */
 244 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 245 static unsigned int gpmc_nr_waitpins;
 246 static struct device *gpmc_dev;
 247 static int gpmc_irq;
 248 static resource_size_t phys_base, mem_size;
 249 static unsigned gpmc_capability;
 250 static void __iomem *gpmc_base;
 251
 252 static struct clk *gpmc_l3_clk;
 253
 254 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 255
 256 static void gpmc_write_reg(int idx, u32 val)
 257 {
 258         writel_relaxed(val, gpmc_base + idx);
 259 }
 260
 261 static u32 gpmc_read_reg(int idx)
 262 {
 263         return readl_relaxed(gpmc_base + idx);
 264 }
 265
 266 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 267 {
 268         void __iomem *reg_addr;
 269
 270         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 271         writel_relaxed(val, reg_addr);
 272 }
 273
 274 static u32 gpmc_cs_read_reg(int cs, int idx)
 275 {
 276         void __iomem *reg_addr;
 277
 278         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 279         return readl_relaxed(reg_addr);
 280 }
 281
 282 /* TODO: Add support for gpmc_fck to clock framework and use it */
 283 static unsigned long gpmc_get_fclk_period(void)
 284 {
 285         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 286
 287         rate /= 1000;
 288         rate = 1000000000 / rate;       /* In picoseconds */
 289
 290         return rate;
 291 }
 292
 293 /**
 294  * gpmc_get_clk_period - get period of selected clock domain in ps
 295  * @cs Chip Select Region.
 296  * @cd Clock Domain.
 297  *
 298  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 299  * prior to calling this function with GPMC_CD_CLK.
 300  */
 301 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 302 {
 303
 304         unsigned long tick_ps = gpmc_get_fclk_period();
 305         u32 l;
 306         int div;
 307
 308         switch (cd) {
 309         case GPMC_CD_CLK:
 310                 /* get current clk divider */
 311                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 312                 div = (l & 0x03) + 1;
 313                 /* get GPMC_CLK period */
 314                 tick_ps *= div;
 315                 break;
 316         case GPMC_CD_FCLK:
 317                 /* FALL-THROUGH */
 318         default:
 319                 break;
 320         }
 321
 322         return tick_ps;
 323
 324 }
 325
 326 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 327                                          enum gpmc_clk_domain cd)
 328 {
 329         unsigned long tick_ps;
 330
 331         /* Calculate in picosecs to yield more exact results */
 332         tick_ps = gpmc_get_clk_period(cs, cd);
 333
 334         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 335 }
 336
 337 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 338 {
 339         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 340 }
 341
 342 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 343 {
 344         unsigned long tick_ps;
 345
 346         /* Calculate in picosecs to yield more exact results */
 347         tick_ps = gpmc_get_fclk_period();
 348
 349         return (time_ps + tick_ps - 1) / tick_ps;
 350 }
 351
 352 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 353                                   enum gpmc_clk_domain cd)
 354 {
 355         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 356 }
 357
 358 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 359 {
 360         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 361 }
 362
 363 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 364 {
 365         return ticks * gpmc_get_fclk_period();
 366 }
 367
 368 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 369 {
 370         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 371
 372         return ticks * gpmc_get_fclk_period();
 373 }
 374
 375 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 376 {
 377         u32 l;
 378
 379         l = gpmc_cs_read_reg(cs, reg);
 380         if (value)
 381                 l |= mask;
 382         else
 383                 l &= ~mask;
 384         gpmc_cs_write_reg(cs, reg, l);
 385 }
 386
 387 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 388 {
 389         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 390                            GPMC_CONFIG1_TIME_PARA_GRAN,
 391                            p->time_para_granularity);
 392         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 393                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 394         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 395                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 396         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 397                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 399                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 400         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 401                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 402                            p->cycle2cyclesamecsen);
 403         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 404                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 405                            p->cycle2cyclediffcsen);
 406 }
 407
 408 #ifdef CONFIG_OMAP_GPMC_DEBUG
 409 /**
 410  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 411  * @cs:      Chip Select Region
 412  * @reg:     GPMC_CS_CONFIGn register offset.
 413  * @st_bit:  Start Bit
 414  * @end_bit: End Bit. Must be >= @st_bit.
 415  * @ma:x     Maximum parameter value (before optional @shift).
 416  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 417  * @name:    DTS node name, w/o "gpmc,"
 418  * @cd:      Clock Domain of timing parameter.
 419  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 420  * @raw:     Raw Format Option.
 421  *           raw format:  gpmc,name = <value>
 422  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 423  *           Where x ns -- y ns result in the same tick value.
 424  *           When @max is exceeded, "invalid" is printed inside comment.
 425  * @noval:   Parameter values equal to 0 are not printed.
 426  * @return:  Specified timing parameter (after optional @shift).
 427  *
 428  */
 429 static int get_gpmc_timing_reg(
 430         /* timing specifiers */
 431         int cs, int reg, int st_bit, int end_bit, int max,
 432         const char *name, const enum gpmc_clk_domain cd,
 433         /* value transform */
 434         int shift,
 435         /* format specifiers */
 436         bool raw, bool noval)
 437 {
 438         u32 l;
 439         int nr_bits;
 440         int mask;
 441         bool invalid;
 442
 443         l = gpmc_cs_read_reg(cs, reg);
 444         nr_bits = end_bit - st_bit + 1;
 445         mask = (1 << nr_bits) - 1;
 446         l = (l >> st_bit) & mask;
 447         if (!max)
 448                 max = mask;
 449         invalid = l > max;
 450         if (shift)
 451                 l = (shift << l);
 452         if (noval && (l == 0))
 453                 return 0;
 454         if (!raw) {
 455                 /* DTS tick format for timings in ns */
 456                 unsigned int time_ns;
 457                 unsigned int time_ns_min = 0;
 458
 459                 if (l)
 460                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 461                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 462                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 463                         name, time_ns, time_ns_min, time_ns, l,
 464                         invalid ? "; invalid " : " ");
 465         } else {
 466                 /* raw format */
 467                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 468                         invalid ? " /* invalid */" : "");
 469         }
 470
 471         return l;
 472 }
 473
 474 #define GPMC_PRINT_CONFIG(cs, config) \
 475         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 476                 gpmc_cs_read_reg(cs, config))
 477 #define GPMC_GET_RAW(reg, st, end, field) \
 478         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 479 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 480         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 481 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 482         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 483 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 484         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 485 #define GPMC_GET_TICKS(reg, st, end, field) \
 486         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 487 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 488         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 489 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 490         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 491
 492 static void gpmc_show_regs(int cs, const char *desc)
 493 {
 494         pr_info("gpmc cs%i %s:\n", cs, desc);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 500         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 501 }
 502
 503 /*
 504  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 505  * see commit c9fb809.
 506  */
 507 static void gpmc_cs_show_timings(int cs, const char *desc)
 508 {
 509         gpmc_show_regs(cs, desc);
 510
 511         pr_info("gpmc cs%i access configuration:\n", cs);
 512         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 513         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 514         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 515                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 516         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 517         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 519         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 520                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 521                                "burst-length");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 526         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 527
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 531
 532         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 533         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 534
 535         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 536         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 537
 538         pr_info("gpmc cs%i timings configuration:\n", cs);
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 540         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 541         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 542
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 544         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 545         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 546         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 547                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 548                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 549                                 "adv-aad-mux-rd-off-ns");
 550                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 551                                 "adv-aad-mux-wr-off-ns");
 552         }
 553
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 556         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 557                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 558                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 559         }
 560         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 561         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 562
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 566
 567         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 568
 569         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 570         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 571
 572         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 573                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 574                               "wait-monitoring-ns", GPMC_CD_CLK);
 575         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 576                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 577                               "clk-activation-ns", GPMC_CD_FCLK);
 578
 579         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 580         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 581 }
 582 #else
 583 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 584 {
 585 }
 586 #endif
 587
 588 /**
 589  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 590  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 591  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 592  *
 593  * @cs:      Chip Select Region.
 594  * @reg:     GPMC_CS_CONFIGn register offset.
 595  * @st_bit:  Start Bit
 596  * @end_bit: End Bit. Must be >= @st_bit.
 597  * @max:     Maximum parameter value.
 598  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 599  * @time:    Timing parameter in ns.
 600  * @cd:      Timing parameter clock domain.
 601  * @name:    Timing parameter name.
 602  * @return:  0 on success, -1 on error.
 603  */
 604 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 605                                int time, enum gpmc_clk_domain cd, const char *name)
 606 {
 607         u32 l;
 608         int ticks, mask, nr_bits;
 609
 610         if (time == 0)
 611                 ticks = 0;
 612         else
 613                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 614         nr_bits = end_bit - st_bit + 1;
 615         mask = (1 << nr_bits) - 1;
 616
 617         if (!max)
 618                 max = mask;
 619
 620         if (ticks > max) {
 621                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 622                        __func__, cs, name, time, ticks, max);
 623
 624                 return -1;
 625         }
 626
 627         l = gpmc_cs_read_reg(cs, reg);
 628 #ifdef CONFIG_OMAP_GPMC_DEBUG
 629         pr_info(
 630                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 631                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 632                         (l >> st_bit) & mask, time);
 633 #endif
 634         l &= ~(mask << st_bit);
 635         l |= ticks << st_bit;
 636         gpmc_cs_write_reg(cs, reg, l);
 637
 638         return 0;
 639 }
 640
 641 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 642         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 643             t->field, (cd), #field) < 0)                       \
 644                 return -1
 645
 646 #define GPMC_SET_ONE(reg, st, end, field) \
 647         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 648
 649 /**
 650  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 651  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 652  * read  --> don't sample bus too early
 653  * write --> data is longer on bus
 654  *
 655  * Formula:
 656  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 657  *                    / waitmonitoring_ticks)
 658  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 659  * div <= 0 check.
 660  *
 661  * @wait_monitoring: WAITMONITORINGTIME in ns.
 662  * @return:          -1 on failure to scale, else proper divider > 0.
 663  */
 664 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 665 {
 666
 667         int div = gpmc_ns_to_ticks(wait_monitoring);
 668
 669         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 670         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 671
 672         if (div > 4)
 673                 return -1;
 674         if (div <= 0)
 675                 div = 1;
 676
 677         return div;
 678
 679 }
 680
 681 /**
 682  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 683  * @sync_clk: GPMC_CLK period in ps.
 684  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 685  *            Else, returns -1.
 686  */
 687 int gpmc_calc_divider(unsigned int sync_clk)
 688 {
 689         int div = gpmc_ps_to_ticks(sync_clk);
 690
 691         if (div > 4)
 692                 return -1;
 693         if (div <= 0)
 694                 div = 1;
 695
 696         return div;
 697 }
 698
 699 /**
 700  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 701  * @cs:     Chip Select Region.
 702  * @t:      GPMC timing parameters.
 703  * @s:      GPMC timing settings.
 704  * @return: 0 on success, -1 on error.
 705  */
 706 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 707                         const struct gpmc_settings *s)
 708 {
 709         int div;
 710         u32 l;
 711
 712         div = gpmc_calc_divider(t->sync_clk);
 713         if (div < 0)
 714                 return div;
 715
 716         /*
 717          * See if we need to change the divider for waitmonitoringtime.
 718          *
 719          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 720          * pure asynchronous accesses, i.e. both read and write asynchronous.
 721          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 722          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 723          *
 724          * This statement must not change div to scale async WAITMONITORINGTIME
 725          * to protect mixed synchronous and asynchronous accesses.
 726          *
 727          * We raise an error later if WAITMONITORINGTIME does not fit.
 728          */
 729         if (!s->sync_read && !s->sync_write &&
 730             (s->wait_on_read || s->wait_on_write)
 731            ) {
 732
 733                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 734                 if (div < 0) {
 735                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 736                                __func__,
 737                                t->wait_monitoring
 738                                );
 739                         return -1;
 740                 }
 741         }
 742
 743         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 744         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 745         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 746
 747         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 748         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 749         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 750         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 751                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 752                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 753                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 754         }
 755
 756         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 757         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 758         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 759                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 760                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 761         }
 762         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 763         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 764
 765         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 766         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 767         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 768
 769         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 770
 771         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 772         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 773
 774         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 775                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 776         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 777                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 778
 779         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 780         l &= ~0x03;
 781         l |= (div - 1);
 782         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 783
 784         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 785                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 786                             wait_monitoring, GPMC_CD_CLK);
 787         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 788                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 789                             clk_activation, GPMC_CD_FCLK);
 790
 791 #ifdef CONFIG_OMAP_GPMC_DEBUG
 792         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 793                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 794 #endif
 795
 796         gpmc_cs_bool_timings(cs, &t->bool_timings);
 797         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 798
 799         return 0;
 800 }
 801
 802 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 803 {
 804         u32 l;
 805         u32 mask;
 806
 807         /*
 808          * Ensure that base address is aligned on a
 809          * boundary equal to or greater than size.
 810          */
 811         if (base & (size - 1))
 812                 return -EINVAL;
 813
 814         base >>= GPMC_CHUNK_SHIFT;
 815         mask = (1 << GPMC_SECTION_SHIFT) - size;
 816         mask >>= GPMC_CHUNK_SHIFT;
 817         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 818
 819         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 820         l &= ~GPMC_CONFIG7_MASK;
 821         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 822         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 823         l |= GPMC_CONFIG7_CSVALID;
 824         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 825
 826         return 0;
 827 }
 828
 829 static void gpmc_cs_enable_mem(int cs)
 830 {
 831         u32 l;
 832
 833         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 834         l |= GPMC_CONFIG7_CSVALID;
 835         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 836 }
 837
 838 static void gpmc_cs_disable_mem(int cs)
 839 {
 840         u32 l;
 841
 842         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 843         l &= ~GPMC_CONFIG7_CSVALID;
 844         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 845 }
 846
 847 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 848 {
 849         u32 l;
 850         u32 mask;
 851
 852         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 853         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 854         mask = (l >> 8) & 0x0f;
 855         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 856 }
 857
 858 static int gpmc_cs_mem_enabled(int cs)
 859 {
 860         u32 l;
 861
 862         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 863         return l & GPMC_CONFIG7_CSVALID;
 864 }
 865
 866 static void gpmc_cs_set_reserved(int cs, int reserved)
 867 {
 868         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 869
 870         gpmc->flags |= GPMC_CS_RESERVED;
 871 }
 872
 873 static bool gpmc_cs_reserved(int cs)
 874 {
 875         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 876
 877         return gpmc->flags & GPMC_CS_RESERVED;
 878 }
 879
 880 static void gpmc_cs_set_name(int cs, const char *name)
 881 {
 882         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 883
 884         gpmc->name = name;
 885 }
 886
 887 static const char *gpmc_cs_get_name(int cs)
 888 {
 889         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 890
 891         return gpmc->name;
 892 }
 893
 894 static unsigned long gpmc_mem_align(unsigned long size)
 895 {
 896         int order;
 897
 898         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 899         order = GPMC_CHUNK_SHIFT - 1;
 900         do {
 901                 size >>= 1;
 902                 order++;
 903         } while (size);
 904         size = 1 << order;
 905         return size;
 906 }
 907
 908 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 909 {
 910         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 911         struct resource *res = &gpmc->mem;
 912         int r;
 913
 914         size = gpmc_mem_align(size);
 915         spin_lock(&gpmc_mem_lock);
 916         res->start = base;
 917         res->end = base + size - 1;
 918         r = request_resource(&gpmc_mem_root, res);
 919         spin_unlock(&gpmc_mem_lock);
 920
 921         return r;
 922 }
 923
 924 static int gpmc_cs_delete_mem(int cs)
 925 {
 926         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 927         struct resource *res = &gpmc->mem;
 928         int r;
 929
 930         spin_lock(&gpmc_mem_lock);
 931         r = release_resource(res);
 932         res->start = 0;
 933         res->end = 0;
 934         spin_unlock(&gpmc_mem_lock);
 935
 936         return r;
 937 }
 938
 939 /**
 940  * gpmc_cs_remap - remaps a chip-select physical base address
 941  * @cs:         chip-select to remap
 942  * @base:       physical base address to re-map chip-select to
 943  *
 944  * Re-maps a chip-select to a new physical base address specified by
 945  * "base". Returns 0 on success and appropriate negative error code
 946  * on failure.
 947  */
 948 static int gpmc_cs_remap(int cs, u32 base)
 949 {
 950         int ret;
 951         u32 old_base, size;
 952
 953         if (cs > gpmc_cs_num) {
 954                 pr_err("%s: requested chip-select is disabled\n", __func__);
 955                 return -ENODEV;
 956         }
 957
 958         /*
 959          * Make sure we ignore any device offsets from the GPMC partition
 960          * allocated for the chip select and that the new base confirms
 961          * to the GPMC 16MB minimum granularity.
 962          */
 963         base &= ~(SZ_16M - 1);
 964
 965         gpmc_cs_get_memconf(cs, &old_base, &size);
 966         if (base == old_base)
 967                 return 0;
 968
 969         ret = gpmc_cs_delete_mem(cs);
 970         if (ret < 0)
 971                 return ret;
 972
 973         ret = gpmc_cs_insert_mem(cs, base, size);
 974         if (ret < 0)
 975                 return ret;
 976
 977         ret = gpmc_cs_set_memconf(cs, base, size);
 978
 979         return ret;
 980 }
 981
 982 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 983 {
 984         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 985         struct resource *res = &gpmc->mem;
 986         int r = -1;
 987
 988         if (cs > gpmc_cs_num) {
 989                 pr_err("%s: requested chip-select is disabled\n", __func__);
 990                 return -ENODEV;
 991         }
 992         size = gpmc_mem_align(size);
 993         if (size > (1 << GPMC_SECTION_SHIFT))
 994                 return -ENOMEM;
 995
 996         spin_lock(&gpmc_mem_lock);
 997         if (gpmc_cs_reserved(cs)) {
 998                 r = -EBUSY;
 999                 goto out;
1000         }
1001         if (gpmc_cs_mem_enabled(cs))
1002                 r = adjust_resource(res, res->start & ~(size - 1), size);
1003         if (r < 0)
1004                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1005                                       size, NULL, NULL);
1006         if (r < 0)
1007                 goto out;
1008
1009         /* Disable CS while changing base address and size mask */
1010         gpmc_cs_disable_mem(cs);
1011
1012         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1013         if (r < 0) {
1014                 release_resource(res);
1015                 goto out;
1016         }
1017
1018         /* Enable CS */
1019         gpmc_cs_enable_mem(cs);
1020         *base = res->start;
1021         gpmc_cs_set_reserved(cs, 1);
1022 out:
1023         spin_unlock(&gpmc_mem_lock);
1024         return r;
1025 }
1026 EXPORT_SYMBOL(gpmc_cs_request);
1027
1028 void gpmc_cs_free(int cs)
1029 {
1030         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1031         struct resource *res = &gpmc->mem;
1032
1033         spin_lock(&gpmc_mem_lock);
1034         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1035                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1036                 BUG();
1037                 spin_unlock(&gpmc_mem_lock);
1038                 return;
1039         }
1040         gpmc_cs_disable_mem(cs);
1041         if (res->flags)
1042                 release_resource(res);
1043         gpmc_cs_set_reserved(cs, 0);
1044         spin_unlock(&gpmc_mem_lock);
1045 }
1046 EXPORT_SYMBOL(gpmc_cs_free);
1047
1048 /**
1049  * gpmc_configure - write request to configure gpmc
1050  * @cmd: command type
1051  * @wval: value to write
1052  * @return status of the operation
1053  */
1054 int gpmc_configure(int cmd, int wval)
1055 {
1056         u32 regval;
1057
1058         switch (cmd) {
1059         case GPMC_ENABLE_IRQ:
1060                 gpmc_write_reg(GPMC_IRQENABLE, wval);
1061                 break;
1062
1063         case GPMC_SET_IRQ_STATUS:
1064                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
1065                 break;
1066
1067         case GPMC_CONFIG_WP:
1068                 regval = gpmc_read_reg(GPMC_CONFIG);
1069                 if (wval)
1070                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1071                 else
1072                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1073                 gpmc_write_reg(GPMC_CONFIG, regval);
1074                 break;
1075
1076         default:
1077                 pr_err("%s: command not supported\n", __func__);
1078                 return -EINVAL;
1079         }
1080
1081         return 0;
1082 }
1083 EXPORT_SYMBOL(gpmc_configure);
1084
1085 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1086 {
1087         int i;
1088
1089         reg->gpmc_status = gpmc_base + GPMC_STATUS;
1090         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1091                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1092         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1093                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1094         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1095                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1096         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1097         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1098         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1099         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1100         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1101         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1102         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1103         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1104
1105         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1106                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1107                                            GPMC_BCH_SIZE * i;
1108                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1109                                            GPMC_BCH_SIZE * i;
1110                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1111                                            GPMC_BCH_SIZE * i;
1112                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1113                                            GPMC_BCH_SIZE * i;
1114                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1115                                            i * GPMC_BCH_SIZE;
1116                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1117                                            i * GPMC_BCH_SIZE;
1118                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1119                                            i * GPMC_BCH_SIZE;
1120         }
1121 }
1122
1123 static bool gpmc_nand_writebuffer_empty(void)
1124 {
1125         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1126                 return true;
1127
1128         return false;
1129 }
1130
1131 static struct gpmc_nand_ops nand_ops = {
1132         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1133 };
1134
1135 /**
1136  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1137  * @regs: the GPMC NAND register map exclusive for NAND use.
1138  * @cs: GPMC chip select number on which the NAND sits. The
1139  *      register map returned will be specific to this chip select.
1140  *
1141  * Returns NULL on error e.g. invalid cs.
1142  */
1143 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1144 {
1145         if (cs >= gpmc_cs_num)
1146                 return NULL;
1147
1148         gpmc_update_nand_reg(reg, cs);
1149
1150         return &nand_ops;
1151 }
1152 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1153
1154 int gpmc_get_client_irq(unsigned irq_config)
1155 {
1156         int i;
1157
1158         if (hweight32(irq_config) > 1)
1159                 return 0;
1160
1161         for (i = 0; i < GPMC_NR_IRQ; i++)
1162                 if (gpmc_client_irq[i].bitmask & irq_config)
1163                         return gpmc_client_irq[i].irq;
1164
1165         return 0;
1166 }
1167
1168 static int gpmc_irq_endis(unsigned irq, bool endis)
1169 {
1170         int i;
1171         u32 regval;
1172
1173         for (i = 0; i < GPMC_NR_IRQ; i++)
1174                 if (irq == gpmc_client_irq[i].irq) {
1175                         regval = gpmc_read_reg(GPMC_IRQENABLE);
1176                         if (endis)
1177                                 regval |= gpmc_client_irq[i].bitmask;
1178                         else
1179                                 regval &= ~gpmc_client_irq[i].bitmask;
1180                         gpmc_write_reg(GPMC_IRQENABLE, regval);
1181                         break;
1182                 }
1183
1184         return 0;
1185 }
1186
1187 static void gpmc_irq_disable(struct irq_data *p)
1188 {
1189         gpmc_irq_endis(p->irq, false);
1190 }
1191
1192 static void gpmc_irq_enable(struct irq_data *p)
1193 {
1194         gpmc_irq_endis(p->irq, true);
1195 }
1196
1197 static void gpmc_irq_noop(struct irq_data *data) { }
1198
1199 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1200
1201 static int gpmc_setup_irq(void)
1202 {
1203         int i;
1204         u32 regval;
1205
1206         if (!gpmc_irq)
1207                 return -EINVAL;
1208
1209         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
1210         if (gpmc_irq_start < 0) {
1211                 pr_err("irq_alloc_descs failed\n");
1212                 return gpmc_irq_start;
1213         }
1214
1215         gpmc_irq_chip.name = "gpmc";
1216         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
1217         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
1218         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
1219         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
1220         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
1221         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
1222         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
1223
1224         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
1225         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
1226
1227         for (i = 0; i < GPMC_NR_IRQ; i++) {
1228                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
1229                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1230                                         &gpmc_irq_chip, handle_simple_irq);
1231                 irq_modify_status(gpmc_client_irq[i].irq, IRQ_NOREQUEST,
1232                                   IRQ_NOAUTOEN);
1233         }
1234
1235         /* Disable interrupts */
1236         gpmc_write_reg(GPMC_IRQENABLE, 0);
1237
1238         /* clear interrupts */
1239         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1240         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1241
1242         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1243 }
1244
1245 static int gpmc_free_irq(void)
1246 {
1247         int i;
1248
1249         if (gpmc_irq)
1250                 free_irq(gpmc_irq, NULL);
1251
1252         for (i = 0; i < GPMC_NR_IRQ; i++) {
1253                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1254                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1255         }
1256
1257         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1258
1259         return 0;
1260 }
1261
1262 static void gpmc_mem_exit(void)
1263 {
1264         int cs;
1265
1266         for (cs = 0; cs < gpmc_cs_num; cs++) {
1267                 if (!gpmc_cs_mem_enabled(cs))
1268                         continue;
1269                 gpmc_cs_delete_mem(cs);
1270         }
1271
1272 }
1273
1274 static void gpmc_mem_init(void)
1275 {
1276         int cs;
1277
1278         /*
1279          * The first 1MB of GPMC address space is typically mapped to
1280          * the internal ROM. Never allocate the first page, to
1281          * facilitate bug detection; even if we didn't boot from ROM.
1282          */
1283         gpmc_mem_root.start = SZ_1M;
1284         gpmc_mem_root.end = GPMC_MEM_END;
1285
1286         /* Reserve all regions that has been set up by bootloader */
1287         for (cs = 0; cs < gpmc_cs_num; cs++) {
1288                 u32 base, size;
1289
1290                 if (!gpmc_cs_mem_enabled(cs))
1291                         continue;
1292                 gpmc_cs_get_memconf(cs, &base, &size);
1293                 if (gpmc_cs_insert_mem(cs, base, size)) {
1294                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1295                                 __func__, cs, base, base + size);
1296                         gpmc_cs_disable_mem(cs);
1297                 }
1298         }
1299 }
1300
1301 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1302 {
1303         u32 temp;
1304         int div;
1305
1306         div = gpmc_calc_divider(sync_clk);
1307         temp = gpmc_ps_to_ticks(time_ps);
1308         temp = (temp + div - 1) / div;
1309         return gpmc_ticks_to_ps(temp * div);
1310 }
1311
1312 /* XXX: can the cycles be avoided ? */
1313 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1314                                        struct gpmc_device_timings *dev_t,
1315                                        bool mux)
1316 {
1317         u32 temp;
1318
1319         /* adv_rd_off */
1320         temp = dev_t->t_avdp_r;
1321         /* XXX: mux check required ? */
1322         if (mux) {
1323                 /* XXX: t_avdp not to be required for sync, only added for tusb
1324                  * this indirectly necessitates requirement of t_avdp_r and
1325                  * t_avdp_w instead of having a single t_avdp
1326                  */
1327                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1328                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1329         }
1330         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1331
1332         /* oe_on */
1333         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1334         if (mux) {
1335                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1336                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1337                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1338         }
1339         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1340
1341         /* access */
1342         /* XXX: any scope for improvement ?, by combining oe_on
1343          * and clk_activation, need to check whether
1344          * access = clk_activation + round to sync clk ?
1345          */
1346         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1347         temp += gpmc_t->clk_activation;
1348         if (dev_t->cyc_oe)
1349                 temp = max_t(u32, temp, gpmc_t->oe_on +
1350                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1351         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1352
1353         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1354         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1355
1356         /* rd_cycle */
1357         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1358         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1359                                                         gpmc_t->access;
1360         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1361         if (dev_t->t_ce_rdyz)
1362                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1363         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1364
1365         return 0;
1366 }
1367
1368 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1369                                         struct gpmc_device_timings *dev_t,
1370                                         bool mux)
1371 {
1372         u32 temp;
1373
1374         /* adv_wr_off */
1375         temp = dev_t->t_avdp_w;
1376         if (mux) {
1377                 temp = max_t(u32, temp,
1378                         gpmc_t->clk_activation + dev_t->t_avdh);
1379                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1380         }
1381         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1382
1383         /* wr_data_mux_bus */
1384         temp = max_t(u32, dev_t->t_weasu,
1385                         gpmc_t->clk_activation + dev_t->t_rdyo);
1386         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1387          * and in that case remember to handle we_on properly
1388          */
1389         if (mux) {
1390                 temp = max_t(u32, temp,
1391                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1392                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1393                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1394         }
1395         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1396
1397         /* we_on */
1398         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1399                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1400         else
1401                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1402
1403         /* wr_access */
1404         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1405         gpmc_t->wr_access = gpmc_t->access;
1406
1407         /* we_off */
1408         temp = gpmc_t->we_on + dev_t->t_wpl;
1409         temp = max_t(u32, temp,
1410                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1411         temp = max_t(u32, temp,
1412                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1413         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1414
1415         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1416                                                         dev_t->t_wph);
1417
1418         /* wr_cycle */
1419         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1420         temp += gpmc_t->wr_access;
1421         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1422         if (dev_t->t_ce_rdyz)
1423                 temp = max_t(u32, temp,
1424                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1425         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1426
1427         return 0;
1428 }
1429
1430 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1431                                         struct gpmc_device_timings *dev_t,
1432                                         bool mux)
1433 {
1434         u32 temp;
1435
1436         /* adv_rd_off */
1437         temp = dev_t->t_avdp_r;
1438         if (mux)
1439                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1440         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1441
1442         /* oe_on */
1443         temp = dev_t->t_oeasu;
1444         if (mux)
1445                 temp = max_t(u32, temp,
1446                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1447         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1448
1449         /* access */
1450         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1451                                 gpmc_t->oe_on + dev_t->t_oe);
1452         temp = max_t(u32, temp,
1453                                 gpmc_t->cs_on + dev_t->t_ce);
1454         temp = max_t(u32, temp,
1455                                 gpmc_t->adv_on + dev_t->t_aa);
1456         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1457
1458         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1459         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1460
1461         /* rd_cycle */
1462         temp = max_t(u32, dev_t->t_rd_cycle,
1463                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1464         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1465         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1466
1467         return 0;
1468 }
1469
1470 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1471                                          struct gpmc_device_timings *dev_t,
1472                                          bool mux)
1473 {
1474         u32 temp;
1475
1476         /* adv_wr_off */
1477         temp = dev_t->t_avdp_w;
1478         if (mux)
1479                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1480         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1481
1482         /* wr_data_mux_bus */
1483         temp = dev_t->t_weasu;
1484         if (mux) {
1485                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1486                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1487                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1488         }
1489         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1490
1491         /* we_on */
1492         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1493                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1494         else
1495                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1496
1497         /* we_off */
1498         temp = gpmc_t->we_on + dev_t->t_wpl;
1499         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1500
1501         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1502                                                         dev_t->t_wph);
1503
1504         /* wr_cycle */
1505         temp = max_t(u32, dev_t->t_wr_cycle,
1506                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1507         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1508
1509         return 0;
1510 }
1511
1512 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1513                         struct gpmc_device_timings *dev_t)
1514 {
1515         u32 temp;
1516
1517         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1518                                                 gpmc_get_fclk_period();
1519
1520         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1521                                         dev_t->t_bacc,
1522                                         gpmc_t->sync_clk);
1523
1524         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1525         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1526
1527         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1528                 return 0;
1529
1530         if (dev_t->ce_xdelay)
1531                 gpmc_t->bool_timings.cs_extra_delay = true;
1532         if (dev_t->avd_xdelay)
1533                 gpmc_t->bool_timings.adv_extra_delay = true;
1534         if (dev_t->oe_xdelay)
1535                 gpmc_t->bool_timings.oe_extra_delay = true;
1536         if (dev_t->we_xdelay)
1537                 gpmc_t->bool_timings.we_extra_delay = true;
1538
1539         return 0;
1540 }
1541
1542 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1543                                     struct gpmc_device_timings *dev_t,
1544                                     bool sync)
1545 {
1546         u32 temp;
1547
1548         /* cs_on */
1549         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1550
1551         /* adv_on */
1552         temp = dev_t->t_avdasu;
1553         if (dev_t->t_ce_avd)
1554                 temp = max_t(u32, temp,
1555                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1556         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1557
1558         if (sync)
1559                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1560
1561         return 0;
1562 }
1563
1564 /* TODO: remove this function once all peripherals are confirmed to
1565  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1566  * has to be modified to handle timings in ps instead of ns
1567 */
1568 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1569 {
1570         t->cs_on /= 1000;
1571         t->cs_rd_off /= 1000;
1572         t->cs_wr_off /= 1000;
1573         t->adv_on /= 1000;
1574         t->adv_rd_off /= 1000;
1575         t->adv_wr_off /= 1000;
1576         t->we_on /= 1000;
1577         t->we_off /= 1000;
1578         t->oe_on /= 1000;
1579         t->oe_off /= 1000;
1580         t->page_burst_access /= 1000;
1581         t->access /= 1000;
1582         t->rd_cycle /= 1000;
1583         t->wr_cycle /= 1000;
1584         t->bus_turnaround /= 1000;
1585         t->cycle2cycle_delay /= 1000;
1586         t->wait_monitoring /= 1000;
1587         t->clk_activation /= 1000;
1588         t->wr_access /= 1000;
1589         t->wr_data_mux_bus /= 1000;
1590 }
1591
1592 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1593                       struct gpmc_settings *gpmc_s,
1594                       struct gpmc_device_timings *dev_t)
1595 {
1596         bool mux = false, sync = false;
1597
1598         if (gpmc_s) {
1599                 mux = gpmc_s->mux_add_data ? true : false;
1600                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1601         }
1602
1603         memset(gpmc_t, 0, sizeof(*gpmc_t));
1604
1605         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1606
1607         if (gpmc_s && gpmc_s->sync_read)
1608                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1609         else
1610                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1611
1612         if (gpmc_s && gpmc_s->sync_write)
1613                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1614         else
1615                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1616
1617         /* TODO: remove, see function definition */
1618         gpmc_convert_ps_to_ns(gpmc_t);
1619
1620         return 0;
1621 }
1622
1623 /**
1624  * gpmc_cs_program_settings - programs non-timing related settings
1625  * @cs:         GPMC chip-select to program
1626  * @p:          pointer to GPMC settings structure
1627  *
1628  * Programs non-timing related settings for a GPMC chip-select, such as
1629  * bus-width, burst configuration, etc. Function should be called once
1630  * for each chip-select that is being used and must be called before
1631  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1632  * register will be initialised to zero by this function. Returns 0 on
1633  * success and appropriate negative error code on failure.
1634  */
1635 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1636 {
1637         u32 config1;
1638
1639         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1640                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1641                 return -EINVAL;
1642         }
1643
1644         /* Address-data multiplexing not supported for NAND devices */
1645         if (p->device_nand && p->mux_add_data) {
1646                 pr_err("%s: invalid configuration!\n", __func__);
1647                 return -EINVAL;
1648         }
1649
1650         if ((p->mux_add_data > GPMC_MUX_AD) ||
1651             ((p->mux_add_data == GPMC_MUX_AAD) &&
1652              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1653                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1654                 return -EINVAL;
1655         }
1656
1657         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1658         if (p->burst_read || p->burst_write) {
1659                 switch (p->burst_len) {
1660                 case GPMC_BURST_4:
1661                 case GPMC_BURST_8:
1662                 case GPMC_BURST_16:
1663                         break;
1664                 default:
1665                         pr_err("%s: invalid page/burst-length (%d)\n",
1666                                __func__, p->burst_len);
1667                         return -EINVAL;
1668                 }
1669         }
1670
1671         if (p->wait_pin > gpmc_nr_waitpins) {
1672                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1673                 return -EINVAL;
1674         }
1675
1676         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1677
1678         if (p->sync_read)
1679                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1680         if (p->sync_write)
1681                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1682         if (p->wait_on_read)
1683                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1684         if (p->wait_on_write)
1685                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1686         if (p->wait_on_read || p->wait_on_write)
1687                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1688         if (p->device_nand)
1689                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1690         if (p->mux_add_data)
1691                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1692         if (p->burst_read)
1693                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1694         if (p->burst_write)
1695                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1696         if (p->burst_read || p->burst_write) {
1697                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1698                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1699         }
1700
1701         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1702
1703         return 0;
1704 }
1705
1706 #ifdef CONFIG_OF
1707 static const struct of_device_id gpmc_dt_ids[] = {
1708         { .compatible = "ti,omap2420-gpmc" },
1709         { .compatible = "ti,omap2430-gpmc" },
1710         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1711         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1712         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1713         { }
1714 };
1715 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1716
1717 /**
1718  * gpmc_read_settings_dt - read gpmc settings from device-tree
1719  * @np:         pointer to device-tree node for a gpmc child device
1720  * @p:          pointer to gpmc settings structure
1721  *
1722  * Reads the GPMC settings for a GPMC child device from device-tree and
1723  * stores them in the GPMC settings structure passed. The GPMC settings
1724  * structure is initialised to zero by this function and so any
1725  * previously stored settings will be cleared.
1726  */
1727 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1728 {
1729         memset(p, 0, sizeof(struct gpmc_settings));
1730
1731         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1732         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1733         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1734         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1735
1736         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1737                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1738                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1739                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1740                 if (!p->burst_read && !p->burst_write)
1741                         pr_warn("%s: page/burst-length set but not used!\n",
1742                                 __func__);
1743         }
1744
1745         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1746                 p->wait_on_read = of_property_read_bool(np,
1747                                                         "gpmc,wait-on-read");
1748                 p->wait_on_write = of_property_read_bool(np,
1749                                                          "gpmc,wait-on-write");
1750                 if (!p->wait_on_read && !p->wait_on_write)
1751                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1752                                  __func__);
1753         }
1754 }
1755
1756 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1757                                                 struct gpmc_timings *gpmc_t)
1758 {
1759         struct gpmc_bool_timings *p;
1760
1761         if (!np || !gpmc_t)
1762                 return;
1763
1764         memset(gpmc_t, 0, sizeof(*gpmc_t));
1765
1766         /* minimum clock period for syncronous mode */
1767         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1768
1769         /* chip select timtings */
1770         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1771         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1772         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1773
1774         /* ADV signal timings */
1775         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1776         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1777         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1778         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1779                              &gpmc_t->adv_aad_mux_on);
1780         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1781                              &gpmc_t->adv_aad_mux_rd_off);
1782         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1783                              &gpmc_t->adv_aad_mux_wr_off);
1784
1785         /* WE signal timings */
1786         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1787         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1788
1789         /* OE signal timings */
1790         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1791         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1792         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1793                              &gpmc_t->oe_aad_mux_on);
1794         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1795                              &gpmc_t->oe_aad_mux_off);
1796
1797         /* access and cycle timings */
1798         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1799                              &gpmc_t->page_burst_access);
1800         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1801         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1802         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1803         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1804                              &gpmc_t->bus_turnaround);
1805         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1806                              &gpmc_t->cycle2cycle_delay);
1807         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1808                              &gpmc_t->wait_monitoring);
1809         of_property_read_u32(np, "gpmc,clk-activation-ns",
1810                              &gpmc_t->clk_activation);
1811
1812         /* only applicable to OMAP3+ */
1813         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1814         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1815                              &gpmc_t->wr_data_mux_bus);
1816
1817         /* bool timing parameters */
1818         p = &gpmc_t->bool_timings;
1819
1820         p->cycle2cyclediffcsen =
1821                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1822         p->cycle2cyclesamecsen =
1823                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1824         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1825         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1826         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1827         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1828         p->time_para_granularity =
1829                 of_property_read_bool(np, "gpmc,time-para-granularity");
1830 }
1831
1832 #if IS_ENABLED(CONFIG_MTD_NAND)
1833
1834 static const char * const nand_xfer_types[] = {
1835         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1836         [NAND_OMAP_POLLED]                      = "polled",
1837         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1838         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1839 };
1840
1841 static int gpmc_probe_nand_child(struct platform_device *pdev,
1842                                  struct device_node *child)
1843 {
1844         u32 val;
1845         const char *s;
1846         struct gpmc_timings gpmc_t;
1847         struct omap_nand_platform_data *gpmc_nand_data;
1848
1849         if (of_property_read_u32(child, "reg", &val) < 0) {
1850                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1851                         child->full_name);
1852                 return -ENODEV;
1853         }
1854
1855         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1856                                       GFP_KERNEL);
1857         if (!gpmc_nand_data)
1858                 return -ENOMEM;
1859
1860         gpmc_nand_data->cs = val;
1861         gpmc_nand_data->of_node = child;
1862
1863         /* Detect availability of ELM module */
1864         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1865         if (gpmc_nand_data->elm_of_node == NULL)
1866                 gpmc_nand_data->elm_of_node =
1867                                         of_parse_phandle(child, "elm_id", 0);
1868
1869         /* select ecc-scheme for NAND */
1870         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1871                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1872                 return -ENODEV;
1873         }
1874
1875         if (!strcmp(s, "sw"))
1876                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1877         else if (!strcmp(s, "ham1") ||
1878                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1879                 gpmc_nand_data->ecc_opt =
1880                                 OMAP_ECC_HAM1_CODE_HW;
1881         else if (!strcmp(s, "bch4"))
1882                 if (gpmc_nand_data->elm_of_node)
1883                         gpmc_nand_data->ecc_opt =
1884                                 OMAP_ECC_BCH4_CODE_HW;
1885                 else
1886                         gpmc_nand_data->ecc_opt =
1887                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1888         else if (!strcmp(s, "bch8"))
1889                 if (gpmc_nand_data->elm_of_node)
1890                         gpmc_nand_data->ecc_opt =
1891                                 OMAP_ECC_BCH8_CODE_HW;
1892                 else
1893                         gpmc_nand_data->ecc_opt =
1894                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1895         else if (!strcmp(s, "bch16"))
1896                 if (gpmc_nand_data->elm_of_node)
1897                         gpmc_nand_data->ecc_opt =
1898                                 OMAP_ECC_BCH16_CODE_HW;
1899                 else
1900                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1901         else
1902                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1903
1904         /* select data transfer mode for NAND controller */
1905         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1906                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1907                         if (!strcasecmp(s, nand_xfer_types[val])) {
1908                                 gpmc_nand_data->xfer_type = val;
1909                                 break;
1910                         }
1911
1912         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1913
1914         val = of_get_nand_bus_width(child);
1915         if (val == 16)
1916                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1917
1918         gpmc_read_timings_dt(child, &gpmc_t);
1919         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1920
1921         return 0;
1922 }
1923 #else
1924 static int gpmc_probe_nand_child(struct platform_device *pdev,
1925                                  struct device_node *child)
1926 {
1927         return 0;
1928 }
1929 #endif
1930
1931 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1932 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1933                                  struct device_node *child)
1934 {
1935         u32 val;
1936         struct omap_onenand_platform_data *gpmc_onenand_data;
1937
1938         if (of_property_read_u32(child, "reg", &val) < 0) {
1939                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1940                         child->full_name);
1941                 return -ENODEV;
1942         }
1943
1944         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1945                                          GFP_KERNEL);
1946         if (!gpmc_onenand_data)
1947                 return -ENOMEM;
1948
1949         gpmc_onenand_data->cs = val;
1950         gpmc_onenand_data->of_node = child;
1951         gpmc_onenand_data->dma_channel = -1;
1952
1953         if (!of_property_read_u32(child, "dma-channel", &val))
1954                 gpmc_onenand_data->dma_channel = val;
1955
1956         gpmc_onenand_init(gpmc_onenand_data);
1957
1958         return 0;
1959 }
1960 #else
1961 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1962                                     struct device_node *child)
1963 {
1964         return 0;
1965 }
1966 #endif
1967
1968 /**
1969  * gpmc_probe_generic_child - configures the gpmc for a child device
1970  * @pdev:       pointer to gpmc platform device
1971  * @child:      pointer to device-tree node for child device
1972  *
1973  * Allocates and configures a GPMC chip-select for a child device.
1974  * Returns 0 on success and appropriate negative error code on failure.
1975  */
1976 static int gpmc_probe_generic_child(struct platform_device *pdev,
1977                                 struct device_node *child)
1978 {
1979         struct gpmc_settings gpmc_s;
1980         struct gpmc_timings gpmc_t;
1981         struct resource res;
1982         unsigned long base;
1983         const char *name;
1984         int ret, cs;
1985         u32 val;
1986
1987         if (of_property_read_u32(child, "reg", &cs) < 0) {
1988                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1989                         child->full_name);
1990                 return -ENODEV;
1991         }
1992
1993         if (of_address_to_resource(child, 0, &res) < 0) {
1994                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1995                         child->full_name);
1996                 return -ENODEV;
1997         }
1998
1999         /*
2000          * Check if we have multiple instances of the same device
2001          * on a single chip select. If so, use the already initialized
2002          * timings.
2003          */
2004         name = gpmc_cs_get_name(cs);
2005         if (name && child->name && of_node_cmp(child->name, name) == 0)
2006                         goto no_timings;
2007
2008         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2009         if (ret < 0) {
2010                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2011                 return ret;
2012         }
2013         gpmc_cs_set_name(cs, child->name);
2014
2015         gpmc_read_settings_dt(child, &gpmc_s);
2016         gpmc_read_timings_dt(child, &gpmc_t);
2017
2018         /*
2019          * For some GPMC devices we still need to rely on the bootloader
2020          * timings because the devices can be connected via FPGA.
2021          * REVISIT: Add timing support from slls644g.pdf.
2022          */
2023         if (!gpmc_t.cs_rd_off) {
2024                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2025                         cs);
2026                 gpmc_cs_show_timings(cs,
2027                                      "please add GPMC bootloader timings to .dts");
2028                 goto no_timings;
2029         }
2030
2031         /* CS must be disabled while making changes to gpmc configuration */
2032         gpmc_cs_disable_mem(cs);
2033
2034         /*
2035          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2036          * location in the gpmc address space. When booting with
2037          * device-tree we want the NOR flash to be mapped to the
2038          * location specified in the device-tree blob. So remap the
2039          * CS to this location. Once DT migration is complete should
2040          * just make gpmc_cs_request() map a specific address.
2041          */
2042         ret = gpmc_cs_remap(cs, res.start);
2043         if (ret < 0) {
2044                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2045                         cs, &res.start);
2046                 goto err;
2047         }
2048
2049         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
2050         if (ret < 0)
2051                 goto err;
2052
2053         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2054         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2055         if (ret < 0)
2056                 goto err;
2057
2058         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2059         if (ret) {
2060                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2061                         child->name);
2062                 goto err;
2063         }
2064
2065         /* Clear limited address i.e. enable A26-A11 */
2066         val = gpmc_read_reg(GPMC_CONFIG);
2067         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2068         gpmc_write_reg(GPMC_CONFIG, val);
2069
2070         /* Enable CS region */
2071         gpmc_cs_enable_mem(cs);
2072
2073 no_timings:
2074
2075         /* create platform device, NULL on error or when disabled */
2076         if (!of_platform_device_create(child, NULL, &pdev->dev))
2077                 goto err_child_fail;
2078
2079         /* is child a common bus? */
2080         if (of_match_node(of_default_bus_match_table, child))
2081                 /* create children and other common bus children */
2082                 if (of_platform_populate(child, of_default_bus_match_table,
2083                                          NULL, &pdev->dev))
2084                         goto err_child_fail;
2085
2086         return 0;
2087
2088 err_child_fail:
2089
2090         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2091         ret = -ENODEV;
2092
2093 err:
2094         gpmc_cs_free(cs);
2095
2096         return ret;
2097 }
2098
2099 static int gpmc_probe_dt(struct platform_device *pdev)
2100 {
2101         int ret;
2102         struct device_node *child;
2103         const struct of_device_id *of_id =
2104                 of_match_device(gpmc_dt_ids, &pdev->dev);
2105
2106         if (!of_id)
2107                 return 0;
2108
2109         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2110                                    &gpmc_cs_num);
2111         if (ret < 0) {
2112                 pr_err("%s: number of chip-selects not defined\n", __func__);
2113                 return ret;
2114         } else if (gpmc_cs_num < 1) {
2115                 pr_err("%s: all chip-selects are disabled\n", __func__);
2116                 return -EINVAL;
2117         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2118                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2119                                          __func__, GPMC_CS_NUM);
2120                 return -EINVAL;
2121         }
2122
2123         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2124                                    &gpmc_nr_waitpins);
2125         if (ret < 0) {
2126                 pr_err("%s: number of wait pins not found!\n", __func__);
2127                 return ret;
2128         }
2129
2130         for_each_available_child_of_node(pdev->dev.of_node, child) {
2131
2132                 if (!child->name)
2133                         continue;
2134
2135                 if (of_node_cmp(child->name, "nand") == 0)
2136                         ret = gpmc_probe_nand_child(pdev, child);
2137                 else if (of_node_cmp(child->name, "onenand") == 0)
2138                         ret = gpmc_probe_onenand_child(pdev, child);
2139                 else
2140                         ret = gpmc_probe_generic_child(pdev, child);
2141         }
2142
2143         return 0;
2144 }
2145 #else
2146 static int gpmc_probe_dt(struct platform_device *pdev)
2147 {
2148         return 0;
2149 }
2150 #endif
2151
2152 static int gpmc_probe(struct platform_device *pdev)
2153 {
2154         int rc;
2155         u32 l;
2156         struct resource *res;
2157
2158         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2159         if (res == NULL)
2160                 return -ENOENT;
2161
2162         phys_base = res->start;
2163         mem_size = resource_size(res);
2164
2165         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2166         if (IS_ERR(gpmc_base))
2167                 return PTR_ERR(gpmc_base);
2168
2169         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2170         if (res == NULL)
2171                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
2172         else
2173                 gpmc_irq = res->start;
2174
2175         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2176         if (IS_ERR(gpmc_l3_clk)) {
2177                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2178                 gpmc_irq = 0;
2179                 return PTR_ERR(gpmc_l3_clk);
2180         }
2181
2182         if (!clk_get_rate(gpmc_l3_clk)) {
2183                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2184                 return -EINVAL;
2185         }
2186
2187         pm_runtime_enable(&pdev->dev);
2188         pm_runtime_get_sync(&pdev->dev);
2189
2190         gpmc_dev = &pdev->dev;
2191
2192         l = gpmc_read_reg(GPMC_REVISION);
2193
2194         /*
2195          * FIXME: Once device-tree migration is complete the below flags
2196          * should be populated based upon the device-tree compatible
2197          * string. For now just use the IP revision. OMAP3+ devices have
2198          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2199          * devices support the addr-addr-data multiplex protocol.
2200          *
2201          * GPMC IP revisions:
2202          * - OMAP24xx                   = 2.0
2203          * - OMAP3xxx                   = 5.0
2204          * - OMAP44xx/54xx/AM335x       = 6.0
2205          */
2206         if (GPMC_REVISION_MAJOR(l) > 0x4)
2207                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2208         if (GPMC_REVISION_MAJOR(l) > 0x5)
2209                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2210         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2211                  GPMC_REVISION_MINOR(l));
2212
2213         gpmc_mem_init();
2214
2215         if (gpmc_setup_irq() < 0)
2216                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
2217
2218         if (!pdev->dev.of_node) {
2219                 gpmc_cs_num      = GPMC_CS_NUM;
2220                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2221         }
2222
2223         rc = gpmc_probe_dt(pdev);
2224         if (rc < 0) {
2225                 pm_runtime_put_sync(&pdev->dev);
2226                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
2227                 return rc;
2228         }
2229
2230         return 0;
2231 }
2232
2233 static int gpmc_remove(struct platform_device *pdev)
2234 {
2235         gpmc_free_irq();
2236         gpmc_mem_exit();
2237         pm_runtime_put_sync(&pdev->dev);
2238         pm_runtime_disable(&pdev->dev);
2239         gpmc_dev = NULL;
2240         return 0;
2241 }
2242
2243 #ifdef CONFIG_PM_SLEEP
2244 static int gpmc_suspend(struct device *dev)
2245 {
2246         omap3_gpmc_save_context();
2247         pm_runtime_put_sync(dev);
2248         return 0;
2249 }
2250
2251 static int gpmc_resume(struct device *dev)
2252 {
2253         pm_runtime_get_sync(dev);
2254         omap3_gpmc_restore_context();
2255         return 0;
2256 }
2257 #endif
2258
2259 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2260
2261 static struct platform_driver gpmc_driver = {
2262         .probe          = gpmc_probe,
2263         .remove         = gpmc_remove,
2264         .driver         = {
2265                 .name   = DEVICE_NAME,
2266                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2267                 .pm     = &gpmc_pm_ops,
2268         },
2269 };
2270
2271 static __init int gpmc_init(void)
2272 {
2273         return platform_driver_register(&gpmc_driver);
2274 }
2275
2276 static __exit void gpmc_exit(void)
2277 {
2278         platform_driver_unregister(&gpmc_driver);
2279
2280 }
2281
2282 postcore_initcall(gpmc_init);
2283 module_exit(gpmc_exit);
2284
2285 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2286 {
2287         int i;
2288         u32 regval;
2289
2290         regval = gpmc_read_reg(GPMC_IRQSTATUS);
2291
2292         if (!regval)
2293                 return IRQ_NONE;
2294
2295         for (i = 0; i < GPMC_NR_IRQ; i++)
2296                 if (regval & gpmc_client_irq[i].bitmask)
2297                         generic_handle_irq(gpmc_client_irq[i].irq);
2298
2299         gpmc_write_reg(GPMC_IRQSTATUS, regval);
2300
2301         return IRQ_HANDLED;
2302 }
2303
2304 static struct omap3_gpmc_regs gpmc_context;
2305
2306 void omap3_gpmc_save_context(void)
2307 {
2308         int i;
2309
2310         if (!gpmc_base)
2311                 return;
2312
2313         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2314         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2315         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2316         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2317         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2318         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2319         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2320         for (i = 0; i < gpmc_cs_num; i++) {
2321                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2322                 if (gpmc_context.cs_context[i].is_valid) {
2323                         gpmc_context.cs_context[i].config1 =
2324                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2325                         gpmc_context.cs_context[i].config2 =
2326                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2327                         gpmc_context.cs_context[i].config3 =
2328                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2329                         gpmc_context.cs_context[i].config4 =
2330                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2331                         gpmc_context.cs_context[i].config5 =
2332                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2333                         gpmc_context.cs_context[i].config6 =
2334                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2335                         gpmc_context.cs_context[i].config7 =
2336                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2337                 }
2338         }
2339 }
2340
2341 void omap3_gpmc_restore_context(void)
2342 {
2343         int i;
2344
2345         if (!gpmc_base)
2346                 return;
2347
2348         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2349         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2350         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2351         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2352         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2353         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2354         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2355         for (i = 0; i < gpmc_cs_num; i++) {
2356                 if (gpmc_context.cs_context[i].is_valid) {
2357                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2358                                 gpmc_context.cs_context[i].config1);
2359                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2360                                 gpmc_context.cs_context[i].config2);
2361                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2362                                 gpmc_context.cs_context[i].config3);
2363                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2364                                 gpmc_context.cs_context[i].config4);
2365                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2366                                 gpmc_context.cs_context[i].config5);
2367                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2368                                 gpmc_context.cs_context[i].config6);
2369                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2370                                 gpmc_context.cs_context[i].config7);
2371                 }
2372         }
2373 }