2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/platform_device.h>
28 #include <linux/of_address.h>
29 #include <linux/of_mtd.h>
30 #include <linux/of_device.h>
31 #include <linux/of_platform.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <linux/platform_data/mtd-onenand-omap2.h>
38 #include <asm/mach-types.h>
40 #define DEVICE_NAME "omap-gpmc"
42 /* GPMC register offsets */
43 #define GPMC_REVISION 0x00
44 #define GPMC_SYSCONFIG 0x10
45 #define GPMC_SYSSTATUS 0x14
46 #define GPMC_IRQSTATUS 0x18
47 #define GPMC_IRQENABLE 0x1c
48 #define GPMC_TIMEOUT_CONTROL 0x40
49 #define GPMC_ERR_ADDRESS 0x44
50 #define GPMC_ERR_TYPE 0x48
51 #define GPMC_CONFIG 0x50
52 #define GPMC_STATUS 0x54
53 #define GPMC_PREFETCH_CONFIG1 0x1e0
54 #define GPMC_PREFETCH_CONFIG2 0x1e4
55 #define GPMC_PREFETCH_CONTROL 0x1ec
56 #define GPMC_PREFETCH_STATUS 0x1f0
57 #define GPMC_ECC_CONFIG 0x1f4
58 #define GPMC_ECC_CONTROL 0x1f8
59 #define GPMC_ECC_SIZE_CONFIG 0x1fc
60 #define GPMC_ECC1_RESULT 0x200
61 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
69 /* GPMC ECC control settings */
70 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
71 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
72 #define GPMC_ECC_CTRL_ECCREG1 0x001
73 #define GPMC_ECC_CTRL_ECCREG2 0x002
74 #define GPMC_ECC_CTRL_ECCREG3 0x003
75 #define GPMC_ECC_CTRL_ECCREG4 0x004
76 #define GPMC_ECC_CTRL_ECCREG5 0x005
77 #define GPMC_ECC_CTRL_ECCREG6 0x006
78 #define GPMC_ECC_CTRL_ECCREG7 0x007
79 #define GPMC_ECC_CTRL_ECCREG8 0x008
80 #define GPMC_ECC_CTRL_ECCREG9 0x009
82 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
84 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
86 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
87 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
88 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
89 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
90 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
91 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
93 #define GPMC_CS0_OFFSET 0x60
94 #define GPMC_CS_SIZE 0x30
95 #define GPMC_BCH_SIZE 0x10
98 * The first 1MB of GPMC address space is typically mapped to
99 * the internal ROM. Never allocate the first page, to
100 * facilitate bug detection; even if we didn't boot from ROM.
101 * As GPMC minimum partition size is 16MB we can only start from
104 #define GPMC_MEM_START 0x1000000
105 #define GPMC_MEM_END 0x3FFFFFFF
107 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
108 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
110 #define CS_NUM_SHIFT 24
111 #define ENABLE_PREFETCH (0x1 << 7)
112 #define DMA_MPU_MODE 2
114 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
115 #define GPMC_REVISION_MINOR(l) (l & 0xf)
117 #define GPMC_HAS_WR_ACCESS 0x1
118 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
119 #define GPMC_HAS_MUX_AAD 0x4
121 #define GPMC_NR_WAITPINS 4
123 #define GPMC_CS_CONFIG1 0x00
124 #define GPMC_CS_CONFIG2 0x04
125 #define GPMC_CS_CONFIG3 0x08
126 #define GPMC_CS_CONFIG4 0x0c
127 #define GPMC_CS_CONFIG5 0x10
128 #define GPMC_CS_CONFIG6 0x14
129 #define GPMC_CS_CONFIG7 0x18
130 #define GPMC_CS_NAND_COMMAND 0x1c
131 #define GPMC_CS_NAND_ADDRESS 0x20
132 #define GPMC_CS_NAND_DATA 0x24
134 /* Control Commands */
135 #define GPMC_CONFIG_RDY_BSY 0x00000001
136 #define GPMC_CONFIG_DEV_SIZE 0x00000002
137 #define GPMC_CONFIG_DEV_TYPE 0x00000003
139 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
140 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
141 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
142 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
143 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
144 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
145 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
146 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
147 /** CLKACTIVATIONTIME Max Ticks */
148 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
149 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
150 /** ATTACHEDDEVICEPAGELENGTH Max Value */
151 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
152 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
153 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
154 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
155 /** WAITMONITORINGTIME Max Ticks */
156 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
157 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
158 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
159 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
160 /** DEVICESIZE Max Value */
161 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
162 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
163 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
164 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
165 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
166 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
167 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
168 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
169 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
170 #define GPMC_CONFIG7_CSVALID (1 << 6)
172 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
173 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
174 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
175 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
176 /* All CONFIG7 bits except reserved bits */
177 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
178 GPMC_CONFIG7_CSVALID_MASK | \
179 GPMC_CONFIG7_MASKADDRESS_MASK)
181 #define GPMC_DEVICETYPE_NOR 0
182 #define GPMC_DEVICETYPE_NAND 2
183 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
184 #define WR_RD_PIN_MONITORING 0x00600000
187 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
188 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
189 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
191 /* XXX: Only NAND irq has been considered,currently these are the only ones used
193 #define GPMC_NR_IRQ 2
195 enum gpmc_clk_domain {
200 struct gpmc_cs_data {
203 #define GPMC_CS_RESERVED (1 << 0)
209 /* Structure to save gpmc cs context */
210 struct gpmc_cs_config {
222 * Structure to save/restore gpmc context
223 * to support core off on OMAP3
225 struct omap3_gpmc_regs {
230 u32 prefetch_config1;
231 u32 prefetch_config2;
232 u32 prefetch_control;
233 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
239 struct irq_chip irq_chip;
242 static struct irq_domain *gpmc_irq_domain;
244 static struct resource gpmc_mem_root;
245 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
246 static DEFINE_SPINLOCK(gpmc_mem_lock);
247 /* Define chip-selects as reserved by default until probe completes */
248 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
249 static unsigned int gpmc_nr_waitpins;
250 static resource_size_t phys_base, mem_size;
251 static unsigned gpmc_capability;
252 static void __iomem *gpmc_base;
254 static struct clk *gpmc_l3_clk;
256 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
258 static void gpmc_write_reg(int idx, u32 val)
260 writel_relaxed(val, gpmc_base + idx);
263 static u32 gpmc_read_reg(int idx)
265 return readl_relaxed(gpmc_base + idx);
268 void gpmc_cs_write_reg(int cs, int idx, u32 val)
270 void __iomem *reg_addr;
272 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
273 writel_relaxed(val, reg_addr);
276 static u32 gpmc_cs_read_reg(int cs, int idx)
278 void __iomem *reg_addr;
280 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
281 return readl_relaxed(reg_addr);
284 /* TODO: Add support for gpmc_fck to clock framework and use it */
285 static unsigned long gpmc_get_fclk_period(void)
287 unsigned long rate = clk_get_rate(gpmc_l3_clk);
290 rate = 1000000000 / rate; /* In picoseconds */
296 * gpmc_get_clk_period - get period of selected clock domain in ps
297 * @cs Chip Select Region.
300 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
301 * prior to calling this function with GPMC_CD_CLK.
303 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
306 unsigned long tick_ps = gpmc_get_fclk_period();
312 /* get current clk divider */
313 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
314 div = (l & 0x03) + 1;
315 /* get GPMC_CLK period */
328 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
329 enum gpmc_clk_domain cd)
331 unsigned long tick_ps;
333 /* Calculate in picosecs to yield more exact results */
334 tick_ps = gpmc_get_clk_period(cs, cd);
336 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
339 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
341 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
344 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
346 unsigned long tick_ps;
348 /* Calculate in picosecs to yield more exact results */
349 tick_ps = gpmc_get_fclk_period();
351 return (time_ps + tick_ps - 1) / tick_ps;
354 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
355 enum gpmc_clk_domain cd)
357 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
360 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
362 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
365 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
367 return ticks * gpmc_get_fclk_period();
370 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
372 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
374 return ticks * gpmc_get_fclk_period();
377 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
381 l = gpmc_cs_read_reg(cs, reg);
386 gpmc_cs_write_reg(cs, reg, l);
389 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
391 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
392 GPMC_CONFIG1_TIME_PARA_GRAN,
393 p->time_para_granularity);
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
395 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
397 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
399 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
400 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
401 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
402 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
403 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
404 p->cycle2cyclesamecsen);
405 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
406 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
407 p->cycle2cyclediffcsen);
410 #ifdef CONFIG_OMAP_GPMC_DEBUG
412 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
413 * @cs: Chip Select Region
414 * @reg: GPMC_CS_CONFIGn register offset.
416 * @end_bit: End Bit. Must be >= @st_bit.
417 * @ma:x Maximum parameter value (before optional @shift).
418 * If 0, maximum is as high as @st_bit and @end_bit allow.
419 * @name: DTS node name, w/o "gpmc,"
420 * @cd: Clock Domain of timing parameter.
421 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
422 * @raw: Raw Format Option.
423 * raw format: gpmc,name = <value>
424 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
425 * Where x ns -- y ns result in the same tick value.
426 * When @max is exceeded, "invalid" is printed inside comment.
427 * @noval: Parameter values equal to 0 are not printed.
428 * @return: Specified timing parameter (after optional @shift).
431 static int get_gpmc_timing_reg(
432 /* timing specifiers */
433 int cs, int reg, int st_bit, int end_bit, int max,
434 const char *name, const enum gpmc_clk_domain cd,
435 /* value transform */
437 /* format specifiers */
438 bool raw, bool noval)
445 l = gpmc_cs_read_reg(cs, reg);
446 nr_bits = end_bit - st_bit + 1;
447 mask = (1 << nr_bits) - 1;
448 l = (l >> st_bit) & mask;
454 if (noval && (l == 0))
457 /* DTS tick format for timings in ns */
458 unsigned int time_ns;
459 unsigned int time_ns_min = 0;
462 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
463 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
464 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
465 name, time_ns, time_ns_min, time_ns, l,
466 invalid ? "; invalid " : " ");
469 pr_info("gpmc,%s = <%u>%s\n", name, l,
470 invalid ? " /* invalid */" : "");
476 #define GPMC_PRINT_CONFIG(cs, config) \
477 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
478 gpmc_cs_read_reg(cs, config))
479 #define GPMC_GET_RAW(reg, st, end, field) \
480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
481 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
483 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
485 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
486 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
487 #define GPMC_GET_TICKS(reg, st, end, field) \
488 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
489 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
490 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
491 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
492 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
494 static void gpmc_show_regs(int cs, const char *desc)
496 pr_info("gpmc cs%i %s:\n", cs, desc);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
502 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
506 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
507 * see commit c9fb809.
509 static void gpmc_cs_show_timings(int cs, const char *desc)
511 gpmc_show_regs(cs, desc);
513 pr_info("gpmc cs%i access configuration:\n", cs);
514 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
515 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
516 GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
517 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
518 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
519 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
521 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
522 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
532 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
538 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
540 pr_info("gpmc cs%i timings configuration:\n", cs);
541 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
547 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
548 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
550 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
551 "adv-aad-mux-rd-off-ns");
552 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
553 "adv-aad-mux-wr-off-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
557 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
558 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
560 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
563 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
567 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
569 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
571 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
572 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
574 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
575 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
576 "wait-monitoring-ns", GPMC_CD_CLK);
577 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
578 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
579 "clk-activation-ns", GPMC_CD_FCLK);
581 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
582 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
585 static inline void gpmc_cs_show_timings(int cs, const char *desc)
591 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
592 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
593 * prior to calling this function with @cd equal to GPMC_CD_CLK.
595 * @cs: Chip Select Region.
596 * @reg: GPMC_CS_CONFIGn register offset.
598 * @end_bit: End Bit. Must be >= @st_bit.
599 * @max: Maximum parameter value.
600 * If 0, maximum is as high as @st_bit and @end_bit allow.
601 * @time: Timing parameter in ns.
602 * @cd: Timing parameter clock domain.
603 * @name: Timing parameter name.
604 * @return: 0 on success, -1 on error.
606 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
607 int time, enum gpmc_clk_domain cd, const char *name)
610 int ticks, mask, nr_bits;
615 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
616 nr_bits = end_bit - st_bit + 1;
617 mask = (1 << nr_bits) - 1;
623 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
624 __func__, cs, name, time, ticks, max);
629 l = gpmc_cs_read_reg(cs, reg);
630 #ifdef CONFIG_OMAP_GPMC_DEBUG
632 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
633 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
634 (l >> st_bit) & mask, time);
636 l &= ~(mask << st_bit);
637 l |= ticks << st_bit;
638 gpmc_cs_write_reg(cs, reg, l);
643 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
644 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
645 t->field, (cd), #field) < 0) \
648 #define GPMC_SET_ONE(reg, st, end, field) \
649 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
652 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
653 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
654 * read --> don't sample bus too early
655 * write --> data is longer on bus
658 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
659 * / waitmonitoring_ticks)
660 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
663 * @wait_monitoring: WAITMONITORINGTIME in ns.
664 * @return: -1 on failure to scale, else proper divider > 0.
666 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
669 int div = gpmc_ns_to_ticks(wait_monitoring);
671 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
672 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
684 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
685 * @sync_clk: GPMC_CLK period in ps.
686 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
689 int gpmc_calc_divider(unsigned int sync_clk)
691 int div = gpmc_ps_to_ticks(sync_clk);
702 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
703 * @cs: Chip Select Region.
704 * @t: GPMC timing parameters.
705 * @s: GPMC timing settings.
706 * @return: 0 on success, -1 on error.
708 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
709 const struct gpmc_settings *s)
714 div = gpmc_calc_divider(t->sync_clk);
719 * See if we need to change the divider for waitmonitoringtime.
721 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
722 * pure asynchronous accesses, i.e. both read and write asynchronous.
723 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
724 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
726 * This statement must not change div to scale async WAITMONITORINGTIME
727 * to protect mixed synchronous and asynchronous accesses.
729 * We raise an error later if WAITMONITORINGTIME does not fit.
731 if (!s->sync_read && !s->sync_write &&
732 (s->wait_on_read || s->wait_on_write)
735 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
737 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
745 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
746 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
747 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
749 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
751 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
752 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
753 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
754 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
755 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
759 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
760 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
762 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
764 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
765 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
767 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
768 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
769 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
771 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
773 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
774 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
776 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
777 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
778 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
779 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
781 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
784 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
786 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
787 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
788 wait_monitoring, GPMC_CD_CLK);
789 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
790 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
791 clk_activation, GPMC_CD_FCLK);
793 #ifdef CONFIG_OMAP_GPMC_DEBUG
794 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
795 cs, (div * gpmc_get_fclk_period()) / 1000, div);
798 gpmc_cs_bool_timings(cs, &t->bool_timings);
799 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
804 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
810 * Ensure that base address is aligned on a
811 * boundary equal to or greater than size.
813 if (base & (size - 1))
816 base >>= GPMC_CHUNK_SHIFT;
817 mask = (1 << GPMC_SECTION_SHIFT) - size;
818 mask >>= GPMC_CHUNK_SHIFT;
819 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
821 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
822 l &= ~GPMC_CONFIG7_MASK;
823 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
824 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
825 l |= GPMC_CONFIG7_CSVALID;
826 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
831 static void gpmc_cs_enable_mem(int cs)
835 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
836 l |= GPMC_CONFIG7_CSVALID;
837 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
840 static void gpmc_cs_disable_mem(int cs)
844 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
845 l &= ~GPMC_CONFIG7_CSVALID;
846 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
849 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
854 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
855 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
856 mask = (l >> 8) & 0x0f;
857 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
860 static int gpmc_cs_mem_enabled(int cs)
864 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
865 return l & GPMC_CONFIG7_CSVALID;
868 static void gpmc_cs_set_reserved(int cs, int reserved)
870 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
872 gpmc->flags |= GPMC_CS_RESERVED;
875 static bool gpmc_cs_reserved(int cs)
877 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
879 return gpmc->flags & GPMC_CS_RESERVED;
882 static void gpmc_cs_set_name(int cs, const char *name)
884 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
889 static const char *gpmc_cs_get_name(int cs)
891 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
896 static unsigned long gpmc_mem_align(unsigned long size)
900 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
901 order = GPMC_CHUNK_SHIFT - 1;
910 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
912 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
913 struct resource *res = &gpmc->mem;
916 size = gpmc_mem_align(size);
917 spin_lock(&gpmc_mem_lock);
919 res->end = base + size - 1;
920 r = request_resource(&gpmc_mem_root, res);
921 spin_unlock(&gpmc_mem_lock);
926 static int gpmc_cs_delete_mem(int cs)
928 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
929 struct resource *res = &gpmc->mem;
932 spin_lock(&gpmc_mem_lock);
933 r = release_resource(res);
936 spin_unlock(&gpmc_mem_lock);
942 * gpmc_cs_remap - remaps a chip-select physical base address
943 * @cs: chip-select to remap
944 * @base: physical base address to re-map chip-select to
946 * Re-maps a chip-select to a new physical base address specified by
947 * "base". Returns 0 on success and appropriate negative error code
950 static int gpmc_cs_remap(int cs, u32 base)
955 if (cs > gpmc_cs_num) {
956 pr_err("%s: requested chip-select is disabled\n", __func__);
961 * Make sure we ignore any device offsets from the GPMC partition
962 * allocated for the chip select and that the new base confirms
963 * to the GPMC 16MB minimum granularity.
965 base &= ~(SZ_16M - 1);
967 gpmc_cs_get_memconf(cs, &old_base, &size);
968 if (base == old_base)
971 ret = gpmc_cs_delete_mem(cs);
975 ret = gpmc_cs_insert_mem(cs, base, size);
979 ret = gpmc_cs_set_memconf(cs, base, size);
984 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
986 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
987 struct resource *res = &gpmc->mem;
990 if (cs > gpmc_cs_num) {
991 pr_err("%s: requested chip-select is disabled\n", __func__);
994 size = gpmc_mem_align(size);
995 if (size > (1 << GPMC_SECTION_SHIFT))
998 spin_lock(&gpmc_mem_lock);
999 if (gpmc_cs_reserved(cs)) {
1003 if (gpmc_cs_mem_enabled(cs))
1004 r = adjust_resource(res, res->start & ~(size - 1), size);
1006 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1011 /* Disable CS while changing base address and size mask */
1012 gpmc_cs_disable_mem(cs);
1014 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1016 release_resource(res);
1021 gpmc_cs_enable_mem(cs);
1023 gpmc_cs_set_reserved(cs, 1);
1025 spin_unlock(&gpmc_mem_lock);
1028 EXPORT_SYMBOL(gpmc_cs_request);
1030 void gpmc_cs_free(int cs)
1032 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1033 struct resource *res = &gpmc->mem;
1035 spin_lock(&gpmc_mem_lock);
1036 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1037 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1039 spin_unlock(&gpmc_mem_lock);
1042 gpmc_cs_disable_mem(cs);
1044 release_resource(res);
1045 gpmc_cs_set_reserved(cs, 0);
1046 spin_unlock(&gpmc_mem_lock);
1048 EXPORT_SYMBOL(gpmc_cs_free);
1051 * gpmc_configure - write request to configure gpmc
1052 * @cmd: command type
1053 * @wval: value to write
1054 * @return status of the operation
1056 int gpmc_configure(int cmd, int wval)
1061 case GPMC_CONFIG_WP:
1062 regval = gpmc_read_reg(GPMC_CONFIG);
1064 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1066 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1067 gpmc_write_reg(GPMC_CONFIG, regval);
1071 pr_err("%s: command not supported\n", __func__);
1077 EXPORT_SYMBOL(gpmc_configure);
1079 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1083 reg->gpmc_status = gpmc_base + GPMC_STATUS;
1084 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1085 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1086 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1087 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1088 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1089 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1090 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1091 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1092 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1093 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1094 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1095 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1096 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1097 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1099 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1100 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1102 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1104 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1106 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1108 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1110 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1112 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1117 static bool gpmc_nand_writebuffer_empty(void)
1119 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1125 static struct gpmc_nand_ops nand_ops = {
1126 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1130 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1131 * @regs: the GPMC NAND register map exclusive for NAND use.
1132 * @cs: GPMC chip select number on which the NAND sits. The
1133 * register map returned will be specific to this chip select.
1135 * Returns NULL on error e.g. invalid cs.
1137 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1139 if (cs >= gpmc_cs_num)
1142 gpmc_update_nand_reg(reg, cs);
1146 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1148 int gpmc_get_client_irq(unsigned irq_config)
1150 if (!gpmc_irq_domain) {
1151 pr_warn("%s called before GPMC IRQ domain available\n",
1156 if (irq_config >= GPMC_NR_IRQ)
1159 return irq_create_mapping(gpmc_irq_domain, irq_config);
1162 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1166 regval = gpmc_read_reg(GPMC_IRQENABLE);
1168 regval |= BIT(hwirq);
1170 regval &= ~BIT(hwirq);
1171 gpmc_write_reg(GPMC_IRQENABLE, regval);
1176 static void gpmc_irq_disable(struct irq_data *p)
1178 gpmc_irq_endis(p->hwirq, false);
1181 static void gpmc_irq_enable(struct irq_data *p)
1183 gpmc_irq_endis(p->hwirq, true);
1186 static void gpmc_irq_noop(struct irq_data *data) { }
1188 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1190 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1193 struct gpmc_device *gpmc = d->host_data;
1195 irq_set_chip_data(virq, gpmc);
1196 irq_set_chip_and_handler(virq, &gpmc->irq_chip, handle_simple_irq);
1197 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1202 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1203 .map = gpmc_irq_map,
1204 .xlate = irq_domain_xlate_twocell,
1207 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1211 struct gpmc_device *gpmc = data;
1213 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1218 for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++) {
1219 if (regval & BIT(hwirq)) {
1220 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1223 "spurious irq detected hwirq %d, virq %d\n",
1227 generic_handle_irq(virq);
1231 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1236 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1241 /* Disable interrupts */
1242 gpmc_write_reg(GPMC_IRQENABLE, 0);
1244 /* clear interrupts */
1245 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1246 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1248 gpmc->irq_chip.name = "gpmc";
1249 gpmc->irq_chip.irq_startup = gpmc_irq_noop_ret;
1250 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1251 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1252 gpmc->irq_chip.irq_shutdown = gpmc_irq_noop;
1253 gpmc->irq_chip.irq_ack = gpmc_irq_noop;
1254 gpmc->irq_chip.irq_mask = gpmc_irq_noop;
1255 gpmc->irq_chip.irq_unmask = gpmc_irq_noop;
1257 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1259 &gpmc_irq_domain_ops,
1261 if (!gpmc_irq_domain) {
1262 dev_err(gpmc->dev, "IRQ domain add failed\n");
1266 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1268 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1270 irq_domain_remove(gpmc_irq_domain);
1271 gpmc_irq_domain = NULL;
1277 static int gpmc_free_irq(struct gpmc_device *gpmc)
1281 free_irq(gpmc->irq, gpmc);
1283 for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++)
1284 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1286 irq_domain_remove(gpmc_irq_domain);
1287 gpmc_irq_domain = NULL;
1292 static void gpmc_mem_exit(void)
1296 for (cs = 0; cs < gpmc_cs_num; cs++) {
1297 if (!gpmc_cs_mem_enabled(cs))
1299 gpmc_cs_delete_mem(cs);
1304 static void gpmc_mem_init(void)
1308 gpmc_mem_root.start = GPMC_MEM_START;
1309 gpmc_mem_root.end = GPMC_MEM_END;
1311 /* Reserve all regions that has been set up by bootloader */
1312 for (cs = 0; cs < gpmc_cs_num; cs++) {
1315 if (!gpmc_cs_mem_enabled(cs))
1317 gpmc_cs_get_memconf(cs, &base, &size);
1318 if (gpmc_cs_insert_mem(cs, base, size)) {
1319 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1320 __func__, cs, base, base + size);
1321 gpmc_cs_disable_mem(cs);
1326 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1331 div = gpmc_calc_divider(sync_clk);
1332 temp = gpmc_ps_to_ticks(time_ps);
1333 temp = (temp + div - 1) / div;
1334 return gpmc_ticks_to_ps(temp * div);
1337 /* XXX: can the cycles be avoided ? */
1338 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1339 struct gpmc_device_timings *dev_t,
1345 temp = dev_t->t_avdp_r;
1346 /* XXX: mux check required ? */
1348 /* XXX: t_avdp not to be required for sync, only added for tusb
1349 * this indirectly necessitates requirement of t_avdp_r and
1350 * t_avdp_w instead of having a single t_avdp
1352 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1353 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1355 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1358 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1360 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1361 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1362 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1364 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1367 /* XXX: any scope for improvement ?, by combining oe_on
1368 * and clk_activation, need to check whether
1369 * access = clk_activation + round to sync clk ?
1371 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1372 temp += gpmc_t->clk_activation;
1374 temp = max_t(u32, temp, gpmc_t->oe_on +
1375 gpmc_ticks_to_ps(dev_t->cyc_oe));
1376 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1378 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1379 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1382 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1383 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1385 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1386 if (dev_t->t_ce_rdyz)
1387 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1388 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1393 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1394 struct gpmc_device_timings *dev_t,
1400 temp = dev_t->t_avdp_w;
1402 temp = max_t(u32, temp,
1403 gpmc_t->clk_activation + dev_t->t_avdh);
1404 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1406 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1408 /* wr_data_mux_bus */
1409 temp = max_t(u32, dev_t->t_weasu,
1410 gpmc_t->clk_activation + dev_t->t_rdyo);
1411 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1412 * and in that case remember to handle we_on properly
1415 temp = max_t(u32, temp,
1416 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1417 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1418 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1420 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1423 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1424 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1426 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1429 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1430 gpmc_t->wr_access = gpmc_t->access;
1433 temp = gpmc_t->we_on + dev_t->t_wpl;
1434 temp = max_t(u32, temp,
1435 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1436 temp = max_t(u32, temp,
1437 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1438 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1440 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1444 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1445 temp += gpmc_t->wr_access;
1446 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1447 if (dev_t->t_ce_rdyz)
1448 temp = max_t(u32, temp,
1449 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1450 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1455 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1456 struct gpmc_device_timings *dev_t,
1462 temp = dev_t->t_avdp_r;
1464 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1465 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1468 temp = dev_t->t_oeasu;
1470 temp = max_t(u32, temp,
1471 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1472 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1475 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1476 gpmc_t->oe_on + dev_t->t_oe);
1477 temp = max_t(u32, temp,
1478 gpmc_t->cs_on + dev_t->t_ce);
1479 temp = max_t(u32, temp,
1480 gpmc_t->adv_on + dev_t->t_aa);
1481 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1483 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1484 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1487 temp = max_t(u32, dev_t->t_rd_cycle,
1488 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1489 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1490 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1495 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1496 struct gpmc_device_timings *dev_t,
1502 temp = dev_t->t_avdp_w;
1504 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1505 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1507 /* wr_data_mux_bus */
1508 temp = dev_t->t_weasu;
1510 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1511 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1512 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1514 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1517 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1518 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1520 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1523 temp = gpmc_t->we_on + dev_t->t_wpl;
1524 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1526 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1530 temp = max_t(u32, dev_t->t_wr_cycle,
1531 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1532 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1537 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1538 struct gpmc_device_timings *dev_t)
1542 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1543 gpmc_get_fclk_period();
1545 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1549 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1550 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1552 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1555 if (dev_t->ce_xdelay)
1556 gpmc_t->bool_timings.cs_extra_delay = true;
1557 if (dev_t->avd_xdelay)
1558 gpmc_t->bool_timings.adv_extra_delay = true;
1559 if (dev_t->oe_xdelay)
1560 gpmc_t->bool_timings.oe_extra_delay = true;
1561 if (dev_t->we_xdelay)
1562 gpmc_t->bool_timings.we_extra_delay = true;
1567 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1568 struct gpmc_device_timings *dev_t,
1574 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1577 temp = dev_t->t_avdasu;
1578 if (dev_t->t_ce_avd)
1579 temp = max_t(u32, temp,
1580 gpmc_t->cs_on + dev_t->t_ce_avd);
1581 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1584 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1589 /* TODO: remove this function once all peripherals are confirmed to
1590 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1591 * has to be modified to handle timings in ps instead of ns
1593 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1596 t->cs_rd_off /= 1000;
1597 t->cs_wr_off /= 1000;
1599 t->adv_rd_off /= 1000;
1600 t->adv_wr_off /= 1000;
1605 t->page_burst_access /= 1000;
1607 t->rd_cycle /= 1000;
1608 t->wr_cycle /= 1000;
1609 t->bus_turnaround /= 1000;
1610 t->cycle2cycle_delay /= 1000;
1611 t->wait_monitoring /= 1000;
1612 t->clk_activation /= 1000;
1613 t->wr_access /= 1000;
1614 t->wr_data_mux_bus /= 1000;
1617 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1618 struct gpmc_settings *gpmc_s,
1619 struct gpmc_device_timings *dev_t)
1621 bool mux = false, sync = false;
1624 mux = gpmc_s->mux_add_data ? true : false;
1625 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1628 memset(gpmc_t, 0, sizeof(*gpmc_t));
1630 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1632 if (gpmc_s && gpmc_s->sync_read)
1633 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1635 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1637 if (gpmc_s && gpmc_s->sync_write)
1638 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1640 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1642 /* TODO: remove, see function definition */
1643 gpmc_convert_ps_to_ns(gpmc_t);
1649 * gpmc_cs_program_settings - programs non-timing related settings
1650 * @cs: GPMC chip-select to program
1651 * @p: pointer to GPMC settings structure
1653 * Programs non-timing related settings for a GPMC chip-select, such as
1654 * bus-width, burst configuration, etc. Function should be called once
1655 * for each chip-select that is being used and must be called before
1656 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1657 * register will be initialised to zero by this function. Returns 0 on
1658 * success and appropriate negative error code on failure.
1660 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1664 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1665 pr_err("%s: invalid width %d!", __func__, p->device_width);
1669 /* Address-data multiplexing not supported for NAND devices */
1670 if (p->device_nand && p->mux_add_data) {
1671 pr_err("%s: invalid configuration!\n", __func__);
1675 if ((p->mux_add_data > GPMC_MUX_AD) ||
1676 ((p->mux_add_data == GPMC_MUX_AAD) &&
1677 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1678 pr_err("%s: invalid multiplex configuration!\n", __func__);
1682 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1683 if (p->burst_read || p->burst_write) {
1684 switch (p->burst_len) {
1690 pr_err("%s: invalid page/burst-length (%d)\n",
1691 __func__, p->burst_len);
1696 if (p->wait_pin > gpmc_nr_waitpins) {
1697 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1701 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1704 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1706 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1707 if (p->wait_on_read)
1708 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1709 if (p->wait_on_write)
1710 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1711 if (p->wait_on_read || p->wait_on_write)
1712 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1714 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1715 if (p->mux_add_data)
1716 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1718 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1720 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1721 if (p->burst_read || p->burst_write) {
1722 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1723 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1726 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1732 static const struct of_device_id gpmc_dt_ids[] = {
1733 { .compatible = "ti,omap2420-gpmc" },
1734 { .compatible = "ti,omap2430-gpmc" },
1735 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1736 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1737 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1740 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1743 * gpmc_read_settings_dt - read gpmc settings from device-tree
1744 * @np: pointer to device-tree node for a gpmc child device
1745 * @p: pointer to gpmc settings structure
1747 * Reads the GPMC settings for a GPMC child device from device-tree and
1748 * stores them in the GPMC settings structure passed. The GPMC settings
1749 * structure is initialised to zero by this function and so any
1750 * previously stored settings will be cleared.
1752 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1754 memset(p, 0, sizeof(struct gpmc_settings));
1756 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1757 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1758 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1759 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1761 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1762 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1763 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1764 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1765 if (!p->burst_read && !p->burst_write)
1766 pr_warn("%s: page/burst-length set but not used!\n",
1770 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1771 p->wait_on_read = of_property_read_bool(np,
1772 "gpmc,wait-on-read");
1773 p->wait_on_write = of_property_read_bool(np,
1774 "gpmc,wait-on-write");
1775 if (!p->wait_on_read && !p->wait_on_write)
1776 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1781 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1782 struct gpmc_timings *gpmc_t)
1784 struct gpmc_bool_timings *p;
1789 memset(gpmc_t, 0, sizeof(*gpmc_t));
1791 /* minimum clock period for syncronous mode */
1792 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1794 /* chip select timtings */
1795 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1796 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1797 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1799 /* ADV signal timings */
1800 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1801 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1802 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1803 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1804 &gpmc_t->adv_aad_mux_on);
1805 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1806 &gpmc_t->adv_aad_mux_rd_off);
1807 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1808 &gpmc_t->adv_aad_mux_wr_off);
1810 /* WE signal timings */
1811 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1812 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1814 /* OE signal timings */
1815 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1816 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1817 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1818 &gpmc_t->oe_aad_mux_on);
1819 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1820 &gpmc_t->oe_aad_mux_off);
1822 /* access and cycle timings */
1823 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1824 &gpmc_t->page_burst_access);
1825 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1826 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1827 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1828 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1829 &gpmc_t->bus_turnaround);
1830 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1831 &gpmc_t->cycle2cycle_delay);
1832 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1833 &gpmc_t->wait_monitoring);
1834 of_property_read_u32(np, "gpmc,clk-activation-ns",
1835 &gpmc_t->clk_activation);
1837 /* only applicable to OMAP3+ */
1838 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1839 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1840 &gpmc_t->wr_data_mux_bus);
1842 /* bool timing parameters */
1843 p = &gpmc_t->bool_timings;
1845 p->cycle2cyclediffcsen =
1846 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1847 p->cycle2cyclesamecsen =
1848 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1849 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1850 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1851 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1852 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1853 p->time_para_granularity =
1854 of_property_read_bool(np, "gpmc,time-para-granularity");
1857 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1858 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1859 struct device_node *child)
1862 struct omap_onenand_platform_data *gpmc_onenand_data;
1864 if (of_property_read_u32(child, "reg", &val) < 0) {
1865 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1870 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1872 if (!gpmc_onenand_data)
1875 gpmc_onenand_data->cs = val;
1876 gpmc_onenand_data->of_node = child;
1877 gpmc_onenand_data->dma_channel = -1;
1879 if (!of_property_read_u32(child, "dma-channel", &val))
1880 gpmc_onenand_data->dma_channel = val;
1882 gpmc_onenand_init(gpmc_onenand_data);
1887 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1888 struct device_node *child)
1895 * gpmc_probe_generic_child - configures the gpmc for a child device
1896 * @pdev: pointer to gpmc platform device
1897 * @child: pointer to device-tree node for child device
1899 * Allocates and configures a GPMC chip-select for a child device.
1900 * Returns 0 on success and appropriate negative error code on failure.
1902 static int gpmc_probe_generic_child(struct platform_device *pdev,
1903 struct device_node *child)
1905 struct gpmc_settings gpmc_s;
1906 struct gpmc_timings gpmc_t;
1907 struct resource res;
1913 if (of_property_read_u32(child, "reg", &cs) < 0) {
1914 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1919 if (of_address_to_resource(child, 0, &res) < 0) {
1920 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1926 * Check if we have multiple instances of the same device
1927 * on a single chip select. If so, use the already initialized
1930 name = gpmc_cs_get_name(cs);
1931 if (name && child->name && of_node_cmp(child->name, name) == 0)
1934 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1936 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1939 gpmc_cs_set_name(cs, child->name);
1941 gpmc_read_settings_dt(child, &gpmc_s);
1942 gpmc_read_timings_dt(child, &gpmc_t);
1945 * For some GPMC devices we still need to rely on the bootloader
1946 * timings because the devices can be connected via FPGA.
1947 * REVISIT: Add timing support from slls644g.pdf.
1949 if (!gpmc_t.cs_rd_off) {
1950 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1952 gpmc_cs_show_timings(cs,
1953 "please add GPMC bootloader timings to .dts");
1957 /* CS must be disabled while making changes to gpmc configuration */
1958 gpmc_cs_disable_mem(cs);
1961 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1962 * location in the gpmc address space. When booting with
1963 * device-tree we want the NOR flash to be mapped to the
1964 * location specified in the device-tree blob. So remap the
1965 * CS to this location. Once DT migration is complete should
1966 * just make gpmc_cs_request() map a specific address.
1968 ret = gpmc_cs_remap(cs, res.start);
1970 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1972 if (res.start < GPMC_MEM_START) {
1973 dev_info(&pdev->dev,
1974 "GPMC CS %d start cannot be lesser than 0x%x\n",
1975 cs, GPMC_MEM_START);
1976 } else if (res.end > GPMC_MEM_END) {
1977 dev_info(&pdev->dev,
1978 "GPMC CS %d end cannot be greater than 0x%x\n",
1984 if (of_node_cmp(child->name, "nand") == 0) {
1985 /* Warn about older DT blobs with no compatible property */
1986 if (!of_property_read_bool(child, "compatible")) {
1987 dev_warn(&pdev->dev,
1988 "Incompatible NAND node: missing compatible");
1994 if (of_device_is_compatible(child, "ti,omap2-nand")) {
1995 /* NAND specific setup */
1996 val = of_get_nand_bus_width(child);
1999 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2002 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2005 dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2011 /* disable write protect */
2012 gpmc_configure(GPMC_CONFIG_WP, 0);
2013 gpmc_s.device_nand = true;
2015 ret = of_property_read_u32(child, "bank-width",
2016 &gpmc_s.device_width);
2021 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2022 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2026 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2028 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2033 /* Clear limited address i.e. enable A26-A11 */
2034 val = gpmc_read_reg(GPMC_CONFIG);
2035 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2036 gpmc_write_reg(GPMC_CONFIG, val);
2038 /* Enable CS region */
2039 gpmc_cs_enable_mem(cs);
2043 /* create platform device, NULL on error or when disabled */
2044 if (!of_platform_device_create(child, NULL, &pdev->dev))
2045 goto err_child_fail;
2047 /* is child a common bus? */
2048 if (of_match_node(of_default_bus_match_table, child))
2049 /* create children and other common bus children */
2050 if (of_platform_populate(child, of_default_bus_match_table,
2052 goto err_child_fail;
2058 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2067 static int gpmc_probe_dt(struct platform_device *pdev)
2070 struct device_node *child;
2071 const struct of_device_id *of_id =
2072 of_match_device(gpmc_dt_ids, &pdev->dev);
2077 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2080 pr_err("%s: number of chip-selects not defined\n", __func__);
2082 } else if (gpmc_cs_num < 1) {
2083 pr_err("%s: all chip-selects are disabled\n", __func__);
2085 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2086 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2087 __func__, GPMC_CS_NUM);
2091 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2094 pr_err("%s: number of wait pins not found!\n", __func__);
2098 for_each_available_child_of_node(pdev->dev.of_node, child) {
2103 if (of_node_cmp(child->name, "onenand") == 0)
2104 ret = gpmc_probe_onenand_child(pdev, child);
2106 ret = gpmc_probe_generic_child(pdev, child);
2112 static int gpmc_probe_dt(struct platform_device *pdev)
2118 static int gpmc_probe(struct platform_device *pdev)
2122 struct resource *res;
2123 struct gpmc_device *gpmc;
2125 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2129 gpmc->dev = &pdev->dev;
2130 platform_set_drvdata(pdev, gpmc);
2132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2136 phys_base = res->start;
2137 mem_size = resource_size(res);
2139 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2140 if (IS_ERR(gpmc_base))
2141 return PTR_ERR(gpmc_base);
2143 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2145 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2149 gpmc->irq = res->start;
2151 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2152 if (IS_ERR(gpmc_l3_clk)) {
2153 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2154 return PTR_ERR(gpmc_l3_clk);
2157 if (!clk_get_rate(gpmc_l3_clk)) {
2158 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2162 pm_runtime_enable(&pdev->dev);
2163 pm_runtime_get_sync(&pdev->dev);
2165 l = gpmc_read_reg(GPMC_REVISION);
2168 * FIXME: Once device-tree migration is complete the below flags
2169 * should be populated based upon the device-tree compatible
2170 * string. For now just use the IP revision. OMAP3+ devices have
2171 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2172 * devices support the addr-addr-data multiplex protocol.
2174 * GPMC IP revisions:
2177 * - OMAP44xx/54xx/AM335x = 6.0
2179 if (GPMC_REVISION_MAJOR(l) > 0x4)
2180 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2181 if (GPMC_REVISION_MAJOR(l) > 0x5)
2182 gpmc_capability |= GPMC_HAS_MUX_AAD;
2183 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2184 GPMC_REVISION_MINOR(l));
2188 rc = gpmc_setup_irq(gpmc);
2190 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2194 if (!pdev->dev.of_node) {
2195 gpmc_cs_num = GPMC_CS_NUM;
2196 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2199 rc = gpmc_probe_dt(pdev);
2201 dev_err(gpmc->dev, "failed to probe DT parameters\n");
2202 gpmc_free_irq(gpmc);
2209 pm_runtime_put_sync(&pdev->dev);
2213 static int gpmc_remove(struct platform_device *pdev)
2215 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2217 gpmc_free_irq(gpmc);
2219 pm_runtime_put_sync(&pdev->dev);
2220 pm_runtime_disable(&pdev->dev);
2225 #ifdef CONFIG_PM_SLEEP
2226 static int gpmc_suspend(struct device *dev)
2228 omap3_gpmc_save_context();
2229 pm_runtime_put_sync(dev);
2233 static int gpmc_resume(struct device *dev)
2235 pm_runtime_get_sync(dev);
2236 omap3_gpmc_restore_context();
2241 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2243 static struct platform_driver gpmc_driver = {
2244 .probe = gpmc_probe,
2245 .remove = gpmc_remove,
2247 .name = DEVICE_NAME,
2248 .of_match_table = of_match_ptr(gpmc_dt_ids),
2253 static __init int gpmc_init(void)
2255 return platform_driver_register(&gpmc_driver);
2258 static __exit void gpmc_exit(void)
2260 platform_driver_unregister(&gpmc_driver);
2264 postcore_initcall(gpmc_init);
2265 module_exit(gpmc_exit);
2267 static struct omap3_gpmc_regs gpmc_context;
2269 void omap3_gpmc_save_context(void)
2276 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2277 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2278 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2279 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2280 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2281 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2282 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2283 for (i = 0; i < gpmc_cs_num; i++) {
2284 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2285 if (gpmc_context.cs_context[i].is_valid) {
2286 gpmc_context.cs_context[i].config1 =
2287 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2288 gpmc_context.cs_context[i].config2 =
2289 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2290 gpmc_context.cs_context[i].config3 =
2291 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2292 gpmc_context.cs_context[i].config4 =
2293 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2294 gpmc_context.cs_context[i].config5 =
2295 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2296 gpmc_context.cs_context[i].config6 =
2297 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2298 gpmc_context.cs_context[i].config7 =
2299 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2304 void omap3_gpmc_restore_context(void)
2311 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2312 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2313 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2314 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2315 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2316 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2317 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2318 for (i = 0; i < gpmc_cs_num; i++) {
2319 if (gpmc_context.cs_context[i].is_valid) {
2320 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2321 gpmc_context.cs_context[i].config1);
2322 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2323 gpmc_context.cs_context[i].config2);
2324 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2325 gpmc_context.cs_context[i].config3);
2326 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2327 gpmc_context.cs_context[i].config4);
2328 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2329 gpmc_context.cs_context[i].config5);
2330 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2331 gpmc_context.cs_context[i].config6);
2332 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2333 gpmc_context.cs_context[i].config7);