drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/sched.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/omap-dma.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_mtd.h>
  28
  29 #include <linux/mtd/nand_bch.h>
  30 #include <linux/platform_data/elm.h>
  31
  32 #include <linux/omap-gpmc.h>
  33 #include <linux/platform_data/mtd-nand-omap2.h>
  34
  35 #define DRIVER_NAME     "omap2-nand"
  36 #define OMAP_NAND_TIMEOUT_MS    5000
  37
  38 #define NAND_Ecc_P1e            (1 << 0)
  39 #define NAND_Ecc_P2e            (1 << 1)
  40 #define NAND_Ecc_P4e            (1 << 2)
  41 #define NAND_Ecc_P8e            (1 << 3)
  42 #define NAND_Ecc_P16e           (1 << 4)
  43 #define NAND_Ecc_P32e           (1 << 5)
  44 #define NAND_Ecc_P64e           (1 << 6)
  45 #define NAND_Ecc_P128e          (1 << 7)
  46 #define NAND_Ecc_P256e          (1 << 8)
  47 #define NAND_Ecc_P512e          (1 << 9)
  48 #define NAND_Ecc_P1024e         (1 << 10)
  49 #define NAND_Ecc_P2048e         (1 << 11)
  50
  51 #define NAND_Ecc_P1o            (1 << 16)
  52 #define NAND_Ecc_P2o            (1 << 17)
  53 #define NAND_Ecc_P4o            (1 << 18)
  54 #define NAND_Ecc_P8o            (1 << 19)
  55 #define NAND_Ecc_P16o           (1 << 20)
  56 #define NAND_Ecc_P32o           (1 << 21)
  57 #define NAND_Ecc_P64o           (1 << 22)
  58 #define NAND_Ecc_P128o          (1 << 23)
  59 #define NAND_Ecc_P256o          (1 << 24)
  60 #define NAND_Ecc_P512o          (1 << 25)
  61 #define NAND_Ecc_P1024o         (1 << 26)
  62 #define NAND_Ecc_P2048o         (1 << 27)
  63
  64 #define TF(value)       (value ? 1 : 0)
  65
  66 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  67 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  68 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  69 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  70 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  71 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  72 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  73 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  74
  75 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  76 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  77 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  78 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  79 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  80 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  81 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  82 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  83
  84 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  85 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  86 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  87 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  88 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  89 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  90 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  91 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  92
  93 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  94 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  95 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  96 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  97 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  98 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  99 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
 100 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
 101
 102 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 103 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 104
 105 #define PREFETCH_CONFIG1_CS_SHIFT       24
 106 #define ECC_CONFIG_CS_SHIFT             1
 107 #define CS_MASK                         0x7
 108 #define ENABLE_PREFETCH                 (0x1 << 7)
 109 #define DMA_MPU_MODE_SHIFT              2
 110 #define ECCSIZE0_SHIFT                  12
 111 #define ECCSIZE1_SHIFT                  22
 112 #define ECC1RESULTSIZE                  0x1
 113 #define ECCCLEAR                        0x100
 114 #define ECC1                            0x1
 115 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 116 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 117 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 118 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 119 #define STATUS_BUFF_EMPTY               0x00000001
 120
 121 #define OMAP24XX_DMA_GPMC               4
 122
 123 #define SECTOR_BYTES            512
 124 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 125 #define BCH4_BIT_PAD            4
 126
 127 /* GPMC ecc engine settings for read */
 128 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
 129 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
 130 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
 131 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
 132 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
 133
 134 /* GPMC ecc engine settings for write */
 135 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
 136 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
 137 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
 138
 139 #define BADBLOCK_MARKER_LENGTH          2
 140
 141 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
 142                                 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
 143                                 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
 144                                 0x07, 0x0e};
 145 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 146         0xac, 0x6b, 0xff, 0x99, 0x7b};
 147 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 148
 149 /* Shared among all NAND instances to synchronize access to the ECC Engine */
 150 static struct nand_hw_control omap_gpmc_controller = {
 151         .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
 152         .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
 153 };
 154
 155 struct omap_nand_info {
 156         struct nand_chip                nand;
 157         struct platform_device          *pdev;
 158
 159         int                             gpmc_cs;
 160         bool                            dev_ready;
 161         enum nand_io                    xfer_type;
 162         int                             devsize;
 163         enum omap_ecc                   ecc_opt;
 164         struct device_node              *elm_of_node;
 165
 166         unsigned long                   phys_base;
 167         struct completion               comp;
 168         struct dma_chan                 *dma;
 169         int                             gpmc_irq_fifo;
 170         int                             gpmc_irq_count;
 171         enum {
 172                 OMAP_NAND_IO_READ = 0,  /* read */
 173                 OMAP_NAND_IO_WRITE,     /* write */
 174         } iomode;
 175         u_char                          *buf;
 176         int                                     buf_len;
 177         /* Interface to GPMC */
 178         struct gpmc_nand_regs           reg;
 179         struct gpmc_nand_ops            *ops;
 180         bool                            flash_bbt;
 181         /* generated at runtime depending on ECC algorithm and layout selected */
 182         struct nand_ecclayout           oobinfo;
 183         /* fields specific for BCHx_HW ECC scheme */
 184         struct device                   *elm_dev;
 185 };
 186
 187 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
 188 {
 189         return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
 190 }
 191
 192 /**
 193  * omap_prefetch_enable - configures and starts prefetch transfer
 194  * @cs: cs (chip select) number
 195  * @fifo_th: fifo threshold to be used for read/ write
 196  * @dma_mode: dma mode enable (1) or disable (0)
 197  * @u32_count: number of bytes to be transferred
 198  * @is_write: prefetch read(0) or write post(1) mode
 199  */
 200 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 201         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 202 {
 203         u32 val;
 204
 205         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 206                 return -1;
 207
 208         if (readl(info->reg.gpmc_prefetch_control))
 209                 return -EBUSY;
 210
 211         /* Set the amount of bytes to be prefetched */
 212         writel(u32_count, info->reg.gpmc_prefetch_config2);
 213
 214         /* Set dma/mpu mode, the prefetch read / post write and
 215          * enable the engine. Set which cs is has requested for.
 216          */
 217         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 218                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 219                 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
 220         writel(val, info->reg.gpmc_prefetch_config1);
 221
 222         /*  Start the prefetch engine */
 223         writel(0x1, info->reg.gpmc_prefetch_control);
 224
 225         return 0;
 226 }
 227
 228 /**
 229  * omap_prefetch_reset - disables and stops the prefetch engine
 230  */
 231 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 232 {
 233         u32 config1;
 234
 235         /* check if the same module/cs is trying to reset */
 236         config1 = readl(info->reg.gpmc_prefetch_config1);
 237         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 238                 return -EINVAL;
 239
 240         /* Stop the PFPW engine */
 241         writel(0x0, info->reg.gpmc_prefetch_control);
 242
 243         /* Reset/disable the PFPW engine */
 244         writel(0x0, info->reg.gpmc_prefetch_config1);
 245
 246         return 0;
 247 }
 248
 249 /**
 250  * omap_hwcontrol - hardware specific access to control-lines
 251  * @mtd: MTD device structure
 252  * @cmd: command to device
 253  * @ctrl:
 254  * NAND_NCE: bit 0 -> don't care
 255  * NAND_CLE: bit 1 -> Command Latch
 256  * NAND_ALE: bit 2 -> Address Latch
 257  *
 258  * NOTE: boards may use different bits for these!!
 259  */
 260 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 261 {
 262         struct omap_nand_info *info = mtd_to_omap(mtd);
 263
 264         if (cmd != NAND_CMD_NONE) {
 265                 if (ctrl & NAND_CLE)
 266                         writeb(cmd, info->reg.gpmc_nand_command);
 267
 268                 else if (ctrl & NAND_ALE)
 269                         writeb(cmd, info->reg.gpmc_nand_address);
 270
 271                 else /* NAND_NCE */
 272                         writeb(cmd, info->reg.gpmc_nand_data);
 273         }
 274 }
 275
 276 /**
 277  * omap_read_buf8 - read data from NAND controller into buffer
 278  * @mtd: MTD device structure
 279  * @buf: buffer to store date
 280  * @len: number of bytes to read
 281  */
 282 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 283 {
 284         struct nand_chip *nand = mtd_to_nand(mtd);
 285
 286         ioread8_rep(nand->IO_ADDR_R, buf, len);
 287 }
 288
 289 /**
 290  * omap_write_buf8 - write buffer to NAND controller
 291  * @mtd: MTD device structure
 292  * @buf: data buffer
 293  * @len: number of bytes to write
 294  */
 295 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 296 {
 297         struct omap_nand_info *info = mtd_to_omap(mtd);
 298         u_char *p = (u_char *)buf;
 299         bool status;
 300
 301         while (len--) {
 302                 iowrite8(*p++, info->nand.IO_ADDR_W);
 303                 /* wait until buffer is available for write */
 304                 do {
 305                         status = info->ops->nand_writebuffer_empty();
 306                 } while (!status);
 307         }
 308 }
 309
 310 /**
 311  * omap_read_buf16 - read data from NAND controller into buffer
 312  * @mtd: MTD device structure
 313  * @buf: buffer to store date
 314  * @len: number of bytes to read
 315  */
 316 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 317 {
 318         struct nand_chip *nand = mtd_to_nand(mtd);
 319
 320         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 321 }
 322
 323 /**
 324  * omap_write_buf16 - write buffer to NAND controller
 325  * @mtd: MTD device structure
 326  * @buf: data buffer
 327  * @len: number of bytes to write
 328  */
 329 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 330 {
 331         struct omap_nand_info *info = mtd_to_omap(mtd);
 332         u16 *p = (u16 *) buf;
 333         bool status;
 334         /* FIXME try bursts of writesw() or DMA ... */
 335         len >>= 1;
 336
 337         while (len--) {
 338                 iowrite16(*p++, info->nand.IO_ADDR_W);
 339                 /* wait until buffer is available for write */
 340                 do {
 341                         status = info->ops->nand_writebuffer_empty();
 342                 } while (!status);
 343         }
 344 }
 345
 346 /**
 347  * omap_read_buf_pref - read data from NAND controller into buffer
 348  * @mtd: MTD device structure
 349  * @buf: buffer to store date
 350  * @len: number of bytes to read
 351  */
 352 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 353 {
 354         struct omap_nand_info *info = mtd_to_omap(mtd);
 355         uint32_t r_count = 0;
 356         int ret = 0;
 357         u32 *p = (u32 *)buf;
 358
 359         /* take care of subpage reads */
 360         if (len % 4) {
 361                 if (info->nand.options & NAND_BUSWIDTH_16)
 362                         omap_read_buf16(mtd, buf, len % 4);
 363                 else
 364                         omap_read_buf8(mtd, buf, len % 4);
 365                 p = (u32 *) (buf + len % 4);
 366                 len -= len % 4;
 367         }
 368
 369         /* configure and start prefetch transfer */
 370         ret = omap_prefetch_enable(info->gpmc_cs,
 371                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 372         if (ret) {
 373                 /* PFPW engine is busy, use cpu copy method */
 374                 if (info->nand.options & NAND_BUSWIDTH_16)
 375                         omap_read_buf16(mtd, (u_char *)p, len);
 376                 else
 377                         omap_read_buf8(mtd, (u_char *)p, len);
 378         } else {
 379                 do {
 380                         r_count = readl(info->reg.gpmc_prefetch_status);
 381                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
 382                         r_count = r_count >> 2;
 383                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 384                         p += r_count;
 385                         len -= r_count << 2;
 386                 } while (len);
 387                 /* disable and stop the PFPW engine */
 388                 omap_prefetch_reset(info->gpmc_cs, info);
 389         }
 390 }
 391
 392 /**
 393  * omap_write_buf_pref - write buffer to NAND controller
 394  * @mtd: MTD device structure
 395  * @buf: data buffer
 396  * @len: number of bytes to write
 397  */
 398 static void omap_write_buf_pref(struct mtd_info *mtd,
 399                                         const u_char *buf, int len)
 400 {
 401         struct omap_nand_info *info = mtd_to_omap(mtd);
 402         uint32_t w_count = 0;
 403         int i = 0, ret = 0;
 404         u16 *p = (u16 *)buf;
 405         unsigned long tim, limit;
 406         u32 val;
 407
 408         /* take care of subpage writes */
 409         if (len % 2 != 0) {
 410                 writeb(*buf, info->nand.IO_ADDR_W);
 411                 p = (u16 *)(buf + 1);
 412                 len--;
 413         }
 414
 415         /*  configure and start prefetch transfer */
 416         ret = omap_prefetch_enable(info->gpmc_cs,
 417                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 418         if (ret) {
 419                 /* PFPW engine is busy, use cpu copy method */
 420                 if (info->nand.options & NAND_BUSWIDTH_16)
 421                         omap_write_buf16(mtd, (u_char *)p, len);
 422                 else
 423                         omap_write_buf8(mtd, (u_char *)p, len);
 424         } else {
 425                 while (len) {
 426                         w_count = readl(info->reg.gpmc_prefetch_status);
 427                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
 428                         w_count = w_count >> 1;
 429                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 430                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 431                 }
 432                 /* wait for data to flushed-out before reset the prefetch */
 433                 tim = 0;
 434                 limit = (loops_per_jiffy *
 435                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 436                 do {
 437                         cpu_relax();
 438                         val = readl(info->reg.gpmc_prefetch_status);
 439                         val = PREFETCH_STATUS_COUNT(val);
 440                 } while (val && (tim++ < limit));
 441
 442                 /* disable and stop the PFPW engine */
 443                 omap_prefetch_reset(info->gpmc_cs, info);
 444         }
 445 }
 446
 447 /*
 448  * omap_nand_dma_callback: callback on the completion of dma transfer
 449  * @data: pointer to completion data structure
 450  */
 451 static void omap_nand_dma_callback(void *data)
 452 {
 453         complete((struct completion *) data);
 454 }
 455
 456 /*
 457  * omap_nand_dma_transfer: configure and start dma transfer
 458  * @mtd: MTD device structure
 459  * @addr: virtual address in RAM of source/destination
 460  * @len: number of data bytes to be transferred
 461  * @is_write: flag for read/write operation
 462  */
 463 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 464                                         unsigned int len, int is_write)
 465 {
 466         struct omap_nand_info *info = mtd_to_omap(mtd);
 467         struct dma_async_tx_descriptor *tx;
 468         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 469                                                         DMA_FROM_DEVICE;
 470         struct scatterlist sg;
 471         unsigned long tim, limit;
 472         unsigned n;
 473         int ret;
 474         u32 val;
 475
 476         if (addr >= high_memory) {
 477                 struct page *p1;
 478
 479                 if (((size_t)addr & PAGE_MASK) !=
 480                         ((size_t)(addr + len - 1) & PAGE_MASK))
 481                         goto out_copy;
 482                 p1 = vmalloc_to_page(addr);
 483                 if (!p1)
 484                         goto out_copy;
 485                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 486         }
 487
 488         sg_init_one(&sg, addr, len);
 489         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 490         if (n == 0) {
 491                 dev_err(&info->pdev->dev,
 492                         "Couldn't DMA map a %d byte buffer\n", len);
 493                 goto out_copy;
 494         }
 495
 496         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 497                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 498                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 499         if (!tx)
 500                 goto out_copy_unmap;
 501
 502         tx->callback = omap_nand_dma_callback;
 503         tx->callback_param = &info->comp;
 504         dmaengine_submit(tx);
 505
 506         /*  configure and start prefetch transfer */
 507         ret = omap_prefetch_enable(info->gpmc_cs,
 508                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 509         if (ret)
 510                 /* PFPW engine is busy, use cpu copy method */
 511                 goto out_copy_unmap;
 512
 513         init_completion(&info->comp);
 514         dma_async_issue_pending(info->dma);
 515
 516         /* setup and start DMA using dma_addr */
 517         wait_for_completion(&info->comp);
 518         tim = 0;
 519         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 520
 521         do {
 522                 cpu_relax();
 523                 val = readl(info->reg.gpmc_prefetch_status);
 524                 val = PREFETCH_STATUS_COUNT(val);
 525         } while (val && (tim++ < limit));
 526
 527         /* disable and stop the PFPW engine */
 528         omap_prefetch_reset(info->gpmc_cs, info);
 529
 530         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 531         return 0;
 532
 533 out_copy_unmap:
 534         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 535 out_copy:
 536         if (info->nand.options & NAND_BUSWIDTH_16)
 537                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 538                         : omap_write_buf16(mtd, (u_char *) addr, len);
 539         else
 540                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 541                         : omap_write_buf8(mtd, (u_char *) addr, len);
 542         return 0;
 543 }
 544
 545 /**
 546  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 547  * @mtd: MTD device structure
 548  * @buf: buffer to store date
 549  * @len: number of bytes to read
 550  */
 551 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 552 {
 553         if (len <= mtd->oobsize)
 554                 omap_read_buf_pref(mtd, buf, len);
 555         else
 556                 /* start transfer in DMA mode */
 557                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 558 }
 559
 560 /**
 561  * omap_write_buf_dma_pref - write buffer to NAND controller
 562  * @mtd: MTD device structure
 563  * @buf: data buffer
 564  * @len: number of bytes to write
 565  */
 566 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 567                                         const u_char *buf, int len)
 568 {
 569         if (len <= mtd->oobsize)
 570                 omap_write_buf_pref(mtd, buf, len);
 571         else
 572                 /* start transfer in DMA mode */
 573                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 574 }
 575
 576 /*
 577  * omap_nand_irq - GPMC irq handler
 578  * @this_irq: gpmc irq number
 579  * @dev: omap_nand_info structure pointer is passed here
 580  */
 581 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 582 {
 583         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 584         u32 bytes;
 585
 586         bytes = readl(info->reg.gpmc_prefetch_status);
 587         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 588         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 589         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 590                 if (this_irq == info->gpmc_irq_count)
 591                         goto done;
 592
 593                 if (info->buf_len && (info->buf_len < bytes))
 594                         bytes = info->buf_len;
 595                 else if (!info->buf_len)
 596                         bytes = 0;
 597                 iowrite32_rep(info->nand.IO_ADDR_W,
 598                                                 (u32 *)info->buf, bytes >> 2);
 599                 info->buf = info->buf + bytes;
 600                 info->buf_len -= bytes;
 601
 602         } else {
 603                 ioread32_rep(info->nand.IO_ADDR_R,
 604                                                 (u32 *)info->buf, bytes >> 2);
 605                 info->buf = info->buf + bytes;
 606
 607                 if (this_irq == info->gpmc_irq_count)
 608                         goto done;
 609         }
 610
 611         return IRQ_HANDLED;
 612
 613 done:
 614         complete(&info->comp);
 615
 616         disable_irq_nosync(info->gpmc_irq_fifo);
 617         disable_irq_nosync(info->gpmc_irq_count);
 618
 619         return IRQ_HANDLED;
 620 }
 621
 622 /*
 623  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 624  * @mtd: MTD device structure
 625  * @buf: buffer to store date
 626  * @len: number of bytes to read
 627  */
 628 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 629 {
 630         struct omap_nand_info *info = mtd_to_omap(mtd);
 631         int ret = 0;
 632
 633         if (len <= mtd->oobsize) {
 634                 omap_read_buf_pref(mtd, buf, len);
 635                 return;
 636         }
 637
 638         info->iomode = OMAP_NAND_IO_READ;
 639         info->buf = buf;
 640         init_completion(&info->comp);
 641
 642         /*  configure and start prefetch transfer */
 643         ret = omap_prefetch_enable(info->gpmc_cs,
 644                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 645         if (ret)
 646                 /* PFPW engine is busy, use cpu copy method */
 647                 goto out_copy;
 648
 649         info->buf_len = len;
 650
 651         enable_irq(info->gpmc_irq_count);
 652         enable_irq(info->gpmc_irq_fifo);
 653
 654         /* waiting for read to complete */
 655         wait_for_completion(&info->comp);
 656
 657         /* disable and stop the PFPW engine */
 658         omap_prefetch_reset(info->gpmc_cs, info);
 659         return;
 660
 661 out_copy:
 662         if (info->nand.options & NAND_BUSWIDTH_16)
 663                 omap_read_buf16(mtd, buf, len);
 664         else
 665                 omap_read_buf8(mtd, buf, len);
 666 }
 667
 668 /*
 669  * omap_write_buf_irq_pref - write buffer to NAND controller
 670  * @mtd: MTD device structure
 671  * @buf: data buffer
 672  * @len: number of bytes to write
 673  */
 674 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 675                                         const u_char *buf, int len)
 676 {
 677         struct omap_nand_info *info = mtd_to_omap(mtd);
 678         int ret = 0;
 679         unsigned long tim, limit;
 680         u32 val;
 681
 682         if (len <= mtd->oobsize) {
 683                 omap_write_buf_pref(mtd, buf, len);
 684                 return;
 685         }
 686
 687         info->iomode = OMAP_NAND_IO_WRITE;
 688         info->buf = (u_char *) buf;
 689         init_completion(&info->comp);
 690
 691         /* configure and start prefetch transfer : size=24 */
 692         ret = omap_prefetch_enable(info->gpmc_cs,
 693                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 694         if (ret)
 695                 /* PFPW engine is busy, use cpu copy method */
 696                 goto out_copy;
 697
 698         info->buf_len = len;
 699
 700         enable_irq(info->gpmc_irq_count);
 701         enable_irq(info->gpmc_irq_fifo);
 702
 703         /* waiting for write to complete */
 704         wait_for_completion(&info->comp);
 705
 706         /* wait for data to flushed-out before reset the prefetch */
 707         tim = 0;
 708         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 709         do {
 710                 val = readl(info->reg.gpmc_prefetch_status);
 711                 val = PREFETCH_STATUS_COUNT(val);
 712                 cpu_relax();
 713         } while (val && (tim++ < limit));
 714
 715         /* disable and stop the PFPW engine */
 716         omap_prefetch_reset(info->gpmc_cs, info);
 717         return;
 718
 719 out_copy:
 720         if (info->nand.options & NAND_BUSWIDTH_16)
 721                 omap_write_buf16(mtd, buf, len);
 722         else
 723                 omap_write_buf8(mtd, buf, len);
 724 }
 725
 726 /**
 727  * gen_true_ecc - This function will generate true ECC value
 728  * @ecc_buf: buffer to store ecc code
 729  *
 730  * This generated true ECC value can be used when correcting
 731  * data read from NAND flash memory core
 732  */
 733 static void gen_true_ecc(u8 *ecc_buf)
 734 {
 735         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 736                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 737
 738         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 739                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 740         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 741                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 742         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 743                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 744 }
 745
 746 /**
 747  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 748  * @ecc_data1:  ecc code from nand spare area
 749  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 750  * @page_data:  page data
 751  *
 752  * This function compares two ECC's and indicates if there is an error.
 753  * If the error can be corrected it will be corrected to the buffer.
 754  * If there is no error, %0 is returned. If there is an error but it
 755  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 756  */
 757 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 758                             u8 *ecc_data2,      /* read from register */
 759                             u8 *page_data)
 760 {
 761         uint    i;
 762         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 763         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 764         u8      ecc_bit[24];
 765         u8      ecc_sum = 0;
 766         u8      find_bit = 0;
 767         uint    find_byte = 0;
 768         int     isEccFF;
 769
 770         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 771
 772         gen_true_ecc(ecc_data1);
 773         gen_true_ecc(ecc_data2);
 774
 775         for (i = 0; i <= 2; i++) {
 776                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 777                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 778         }
 779
 780         for (i = 0; i < 8; i++) {
 781                 tmp0_bit[i]     = *ecc_data1 % 2;
 782                 *ecc_data1      = *ecc_data1 / 2;
 783         }
 784
 785         for (i = 0; i < 8; i++) {
 786                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 787                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 788         }
 789
 790         for (i = 0; i < 8; i++) {
 791                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 792                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 793         }
 794
 795         for (i = 0; i < 8; i++) {
 796                 comp0_bit[i]     = *ecc_data2 % 2;
 797                 *ecc_data2       = *ecc_data2 / 2;
 798         }
 799
 800         for (i = 0; i < 8; i++) {
 801                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 802                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 803         }
 804
 805         for (i = 0; i < 8; i++) {
 806                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 807                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 808         }
 809
 810         for (i = 0; i < 6; i++)
 811                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 812
 813         for (i = 0; i < 8; i++)
 814                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 815
 816         for (i = 0; i < 8; i++)
 817                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 818
 819         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 820         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 821
 822         for (i = 0; i < 24; i++)
 823                 ecc_sum += ecc_bit[i];
 824
 825         switch (ecc_sum) {
 826         case 0:
 827                 /* Not reached because this function is not called if
 828                  *  ECC values are equal
 829                  */
 830                 return 0;
 831
 832         case 1:
 833                 /* Uncorrectable error */
 834                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 835                 return -EBADMSG;
 836
 837         case 11:
 838                 /* UN-Correctable error */
 839                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 840                 return -EBADMSG;
 841
 842         case 12:
 843                 /* Correctable error */
 844                 find_byte = (ecc_bit[23] << 8) +
 845                             (ecc_bit[21] << 7) +
 846                             (ecc_bit[19] << 6) +
 847                             (ecc_bit[17] << 5) +
 848                             (ecc_bit[15] << 4) +
 849                             (ecc_bit[13] << 3) +
 850                             (ecc_bit[11] << 2) +
 851                             (ecc_bit[9]  << 1) +
 852                             ecc_bit[7];
 853
 854                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 855
 856                 pr_debug("Correcting single bit ECC error at offset: "
 857                                 "%d, bit: %d\n", find_byte, find_bit);
 858
 859                 page_data[find_byte] ^= (1 << find_bit);
 860
 861                 return 1;
 862         default:
 863                 if (isEccFF) {
 864                         if (ecc_data2[0] == 0 &&
 865                             ecc_data2[1] == 0 &&
 866                             ecc_data2[2] == 0)
 867                                 return 0;
 868                 }
 869                 pr_debug("UNCORRECTED_ERROR default\n");
 870                 return -EBADMSG;
 871         }
 872 }
 873
 874 /**
 875  * omap_correct_data - Compares the ECC read with HW generated ECC
 876  * @mtd: MTD device structure
 877  * @dat: page data
 878  * @read_ecc: ecc read from nand flash
 879  * @calc_ecc: ecc read from HW ECC registers
 880  *
 881  * Compares the ecc read from nand spare area with ECC registers values
 882  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 883  * detection and correction. If there are no errors, %0 is returned. If
 884  * there were errors and all of the errors were corrected, the number of
 885  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 886  * returned.
 887  */
 888 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 889                                 u_char *read_ecc, u_char *calc_ecc)
 890 {
 891         struct omap_nand_info *info = mtd_to_omap(mtd);
 892         int blockCnt = 0, i = 0, ret = 0;
 893         int stat = 0;
 894
 895         /* Ex NAND_ECC_HW12_2048 */
 896         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 897                         (info->nand.ecc.size  == 2048))
 898                 blockCnt = 4;
 899         else
 900                 blockCnt = 1;
 901
 902         for (i = 0; i < blockCnt; i++) {
 903                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 904                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 905                         if (ret < 0)
 906                                 return ret;
 907                         /* keep track of the number of corrected errors */
 908                         stat += ret;
 909                 }
 910                 read_ecc += 3;
 911                 calc_ecc += 3;
 912                 dat      += 512;
 913         }
 914         return stat;
 915 }
 916
 917 /**
 918  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 919  * @mtd: MTD device structure
 920  * @dat: The pointer to data on which ecc is computed
 921  * @ecc_code: The ecc_code buffer
 922  *
 923  * Using noninverted ECC can be considered ugly since writing a blank
 924  * page ie. padding will clear the ECC bytes. This is no problem as long
 925  * nobody is trying to write data on the seemingly unused page. Reading
 926  * an erased page will produce an ECC mismatch between generated and read
 927  * ECC bytes that has to be dealt with separately.
 928  */
 929 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 930                                 u_char *ecc_code)
 931 {
 932         struct omap_nand_info *info = mtd_to_omap(mtd);
 933         u32 val;
 934
 935         val = readl(info->reg.gpmc_ecc_config);
 936         if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
 937                 return -EINVAL;
 938
 939         /* read ecc result */
 940         val = readl(info->reg.gpmc_ecc1_result);
 941         *ecc_code++ = val;          /* P128e, ..., P1e */
 942         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 943         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 944         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 945
 946         return 0;
 947 }
 948
 949 /**
 950  * omap_enable_hwecc - This function enables the hardware ecc functionality
 951  * @mtd: MTD device structure
 952  * @mode: Read/Write mode
 953  */
 954 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 955 {
 956         struct omap_nand_info *info = mtd_to_omap(mtd);
 957         struct nand_chip *chip = mtd_to_nand(mtd);
 958         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 959         u32 val;
 960
 961         /* clear ecc and enable bits */
 962         val = ECCCLEAR | ECC1;
 963         writel(val, info->reg.gpmc_ecc_control);
 964
 965         /* program ecc and result sizes */
 966         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 967                          ECC1RESULTSIZE);
 968         writel(val, info->reg.gpmc_ecc_size_config);
 969
 970         switch (mode) {
 971         case NAND_ECC_READ:
 972         case NAND_ECC_WRITE:
 973                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 974                 break;
 975         case NAND_ECC_READSYN:
 976                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 977                 break;
 978         default:
 979                 dev_info(&info->pdev->dev,
 980                         "error: unrecognized Mode[%d]!\n", mode);
 981                 break;
 982         }
 983
 984         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 985         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 986         writel(val, info->reg.gpmc_ecc_config);
 987 }
 988
 989 /**
 990  * omap_wait - wait until the command is done
 991  * @mtd: MTD device structure
 992  * @chip: NAND Chip structure
 993  *
 994  * Wait function is called during Program and erase operations and
 995  * the way it is called from MTD layer, we should wait till the NAND
 996  * chip is ready after the programming/erase operation has completed.
 997  *
 998  * Erase can take up to 400ms and program up to 20ms according to
 999  * general NAND and SmartMedia specs
1000  */
1001 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1002 {
1003         struct nand_chip *this = mtd_to_nand(mtd);
1004         struct omap_nand_info *info = mtd_to_omap(mtd);
1005         unsigned long timeo = jiffies;
1006         int status, state = this->state;
1007
1008         if (state == FL_ERASING)
1009                 timeo += msecs_to_jiffies(400);
1010         else
1011                 timeo += msecs_to_jiffies(20);
1012
1013         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1014         while (time_before(jiffies, timeo)) {
1015                 status = readb(info->reg.gpmc_nand_data);
1016                 if (status & NAND_STATUS_READY)
1017                         break;
1018                 cond_resched();
1019         }
1020
1021         status = readb(info->reg.gpmc_nand_data);
1022         return status;
1023 }
1024
1025 /**
1026  * omap_dev_ready - calls the platform specific dev_ready function
1027  * @mtd: MTD device structure
1028  */
1029 static int omap_dev_ready(struct mtd_info *mtd)
1030 {
1031         unsigned int val = 0;
1032         struct omap_nand_info *info = mtd_to_omap(mtd);
1033
1034         val = readl(info->reg.gpmc_status);
1035
1036         if ((val & 0x100) == 0x100) {
1037                 return 1;
1038         } else {
1039                 return 0;
1040         }
1041 }
1042
1043 /**
1044  * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1045  * @mtd: MTD device structure
1046  * @mode: Read/Write mode
1047  *
1048  * When using BCH with SW correction (i.e. no ELM), sector size is set
1049  * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1050  * for both reading and writing with:
1051  * eccsize0 = 0  (no additional protected byte in spare area)
1052  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1053  */
1054 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1055 {
1056         unsigned int bch_type;
1057         unsigned int dev_width, nsectors;
1058         struct omap_nand_info *info = mtd_to_omap(mtd);
1059         enum omap_ecc ecc_opt = info->ecc_opt;
1060         struct nand_chip *chip = mtd_to_nand(mtd);
1061         u32 val, wr_mode;
1062         unsigned int ecc_size1, ecc_size0;
1063
1064         /* GPMC configurations for calculating ECC */
1065         switch (ecc_opt) {
1066         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1067                 bch_type = 0;
1068                 nsectors = 1;
1069                 wr_mode   = BCH_WRAPMODE_6;
1070                 ecc_size0 = BCH_ECC_SIZE0;
1071                 ecc_size1 = BCH_ECC_SIZE1;
1072                 break;
1073         case OMAP_ECC_BCH4_CODE_HW:
1074                 bch_type = 0;
1075                 nsectors = chip->ecc.steps;
1076                 if (mode == NAND_ECC_READ) {
1077                         wr_mode   = BCH_WRAPMODE_1;
1078                         ecc_size0 = BCH4R_ECC_SIZE0;
1079                         ecc_size1 = BCH4R_ECC_SIZE1;
1080                 } else {
1081                         wr_mode   = BCH_WRAPMODE_6;
1082                         ecc_size0 = BCH_ECC_SIZE0;
1083                         ecc_size1 = BCH_ECC_SIZE1;
1084                 }
1085                 break;
1086         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1087                 bch_type = 1;
1088                 nsectors = 1;
1089                 wr_mode   = BCH_WRAPMODE_6;
1090                 ecc_size0 = BCH_ECC_SIZE0;
1091                 ecc_size1 = BCH_ECC_SIZE1;
1092                 break;
1093         case OMAP_ECC_BCH8_CODE_HW:
1094                 bch_type = 1;
1095                 nsectors = chip->ecc.steps;
1096                 if (mode == NAND_ECC_READ) {
1097                         wr_mode   = BCH_WRAPMODE_1;
1098                         ecc_size0 = BCH8R_ECC_SIZE0;
1099                         ecc_size1 = BCH8R_ECC_SIZE1;
1100                 } else {
1101                         wr_mode   = BCH_WRAPMODE_6;
1102                         ecc_size0 = BCH_ECC_SIZE0;
1103                         ecc_size1 = BCH_ECC_SIZE1;
1104                 }
1105                 break;
1106         case OMAP_ECC_BCH16_CODE_HW:
1107                 bch_type = 0x2;
1108                 nsectors = chip->ecc.steps;
1109                 if (mode == NAND_ECC_READ) {
1110                         wr_mode   = 0x01;
1111                         ecc_size0 = 52; /* ECC bits in nibbles per sector */
1112                         ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
1113                 } else {
1114                         wr_mode   = 0x01;
1115                         ecc_size0 = 0;  /* extra bits in nibbles per sector */
1116                         ecc_size1 = 52; /* OOB bits in nibbles per sector */
1117                 }
1118                 break;
1119         default:
1120                 return;
1121         }
1122
1123         writel(ECC1, info->reg.gpmc_ecc_control);
1124
1125         /* Configure ecc size for BCH */
1126         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1127         writel(val, info->reg.gpmc_ecc_size_config);
1128
1129         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1130
1131         /* BCH configuration */
1132         val = ((1                        << 16) | /* enable BCH */
1133                (bch_type                 << 12) | /* BCH4/BCH8/BCH16 */
1134                (wr_mode                  <<  8) | /* wrap mode */
1135                (dev_width                <<  7) | /* bus width */
1136                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1137                (info->gpmc_cs            <<  1) | /* ECC CS */
1138                (0x1));                            /* enable ECC */
1139
1140         writel(val, info->reg.gpmc_ecc_config);
1141
1142         /* Clear ecc and enable bits */
1143         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1144 }
1145
1146 static u8  bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1147 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1148                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
1149
1150 /**
1151  * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1152  * @mtd:        MTD device structure
1153  * @dat:        The pointer to data on which ecc is computed
1154  * @ecc_code:   The ecc_code buffer
1155  *
1156  * Support calculating of BCH4/8 ecc vectors for the page
1157  */
1158 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1159                                         const u_char *dat, u_char *ecc_calc)
1160 {
1161         struct omap_nand_info *info = mtd_to_omap(mtd);
1162         int eccbytes    = info->nand.ecc.bytes;
1163         struct gpmc_nand_regs   *gpmc_regs = &info->reg;
1164         u8 *ecc_code;
1165         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1166         u32 val;
1167         int i, j;
1168
1169         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1170         for (i = 0; i < nsectors; i++) {
1171                 ecc_code = ecc_calc;
1172                 switch (info->ecc_opt) {
1173                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1174                 case OMAP_ECC_BCH8_CODE_HW:
1175                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1176                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1177                         bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1178                         bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1179                         *ecc_code++ = (bch_val4 & 0xFF);
1180                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1181                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1182                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1183                         *ecc_code++ = (bch_val3 & 0xFF);
1184                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1185                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1186                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1187                         *ecc_code++ = (bch_val2 & 0xFF);
1188                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1189                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1190                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1191                         *ecc_code++ = (bch_val1 & 0xFF);
1192                         break;
1193                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1194                 case OMAP_ECC_BCH4_CODE_HW:
1195                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1196                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1197                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1198                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1199                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1200                                 ((bch_val1 >> 28) & 0xF);
1201                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1202                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1203                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1204                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1205                         break;
1206                 case OMAP_ECC_BCH16_CODE_HW:
1207                         val = readl(gpmc_regs->gpmc_bch_result6[i]);
1208                         ecc_code[0]  = ((val >>  8) & 0xFF);
1209                         ecc_code[1]  = ((val >>  0) & 0xFF);
1210                         val = readl(gpmc_regs->gpmc_bch_result5[i]);
1211                         ecc_code[2]  = ((val >> 24) & 0xFF);
1212                         ecc_code[3]  = ((val >> 16) & 0xFF);
1213                         ecc_code[4]  = ((val >>  8) & 0xFF);
1214                         ecc_code[5]  = ((val >>  0) & 0xFF);
1215                         val = readl(gpmc_regs->gpmc_bch_result4[i]);
1216                         ecc_code[6]  = ((val >> 24) & 0xFF);
1217                         ecc_code[7]  = ((val >> 16) & 0xFF);
1218                         ecc_code[8]  = ((val >>  8) & 0xFF);
1219                         ecc_code[9]  = ((val >>  0) & 0xFF);
1220                         val = readl(gpmc_regs->gpmc_bch_result3[i]);
1221                         ecc_code[10] = ((val >> 24) & 0xFF);
1222                         ecc_code[11] = ((val >> 16) & 0xFF);
1223                         ecc_code[12] = ((val >>  8) & 0xFF);
1224                         ecc_code[13] = ((val >>  0) & 0xFF);
1225                         val = readl(gpmc_regs->gpmc_bch_result2[i]);
1226                         ecc_code[14] = ((val >> 24) & 0xFF);
1227                         ecc_code[15] = ((val >> 16) & 0xFF);
1228                         ecc_code[16] = ((val >>  8) & 0xFF);
1229                         ecc_code[17] = ((val >>  0) & 0xFF);
1230                         val = readl(gpmc_regs->gpmc_bch_result1[i]);
1231                         ecc_code[18] = ((val >> 24) & 0xFF);
1232                         ecc_code[19] = ((val >> 16) & 0xFF);
1233                         ecc_code[20] = ((val >>  8) & 0xFF);
1234                         ecc_code[21] = ((val >>  0) & 0xFF);
1235                         val = readl(gpmc_regs->gpmc_bch_result0[i]);
1236                         ecc_code[22] = ((val >> 24) & 0xFF);
1237                         ecc_code[23] = ((val >> 16) & 0xFF);
1238                         ecc_code[24] = ((val >>  8) & 0xFF);
1239                         ecc_code[25] = ((val >>  0) & 0xFF);
1240                         break;
1241                 default:
1242                         return -EINVAL;
1243                 }
1244
1245                 /* ECC scheme specific syndrome customizations */
1246                 switch (info->ecc_opt) {
1247                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1248                         /* Add constant polynomial to remainder, so that
1249                          * ECC of blank pages results in 0x0 on reading back */
1250                         for (j = 0; j < eccbytes; j++)
1251                                 ecc_calc[j] ^= bch4_polynomial[j];
1252                         break;
1253                 case OMAP_ECC_BCH4_CODE_HW:
1254                         /* Set  8th ECC byte as 0x0 for ROM compatibility */
1255                         ecc_calc[eccbytes - 1] = 0x0;
1256                         break;
1257                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1258                         /* Add constant polynomial to remainder, so that
1259                          * ECC of blank pages results in 0x0 on reading back */
1260                         for (j = 0; j < eccbytes; j++)
1261                                 ecc_calc[j] ^= bch8_polynomial[j];
1262                         break;
1263                 case OMAP_ECC_BCH8_CODE_HW:
1264                         /* Set 14th ECC byte as 0x0 for ROM compatibility */
1265                         ecc_calc[eccbytes - 1] = 0x0;
1266                         break;
1267                 case OMAP_ECC_BCH16_CODE_HW:
1268                         break;
1269                 default:
1270                         return -EINVAL;
1271                 }
1272
1273         ecc_calc += eccbytes;
1274         }
1275
1276         return 0;
1277 }
1278
1279 /**
1280  * erased_sector_bitflips - count bit flips
1281  * @data:       data sector buffer
1282  * @oob:        oob buffer
1283  * @info:       omap_nand_info
1284  *
1285  * Check the bit flips in erased page falls below correctable level.
1286  * If falls below, report the page as erased with correctable bit
1287  * flip, else report as uncorrectable page.
1288  */
1289 static int erased_sector_bitflips(u_char *data, u_char *oob,
1290                 struct omap_nand_info *info)
1291 {
1292         int flip_bits = 0, i;
1293
1294         for (i = 0; i < info->nand.ecc.size; i++) {
1295                 flip_bits += hweight8(~data[i]);
1296                 if (flip_bits > info->nand.ecc.strength)
1297                         return 0;
1298         }
1299
1300         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1301                 flip_bits += hweight8(~oob[i]);
1302                 if (flip_bits > info->nand.ecc.strength)
1303                         return 0;
1304         }
1305
1306         /*
1307          * Bit flips falls in correctable level.
1308          * Fill data area with 0xFF
1309          */
1310         if (flip_bits) {
1311                 memset(data, 0xFF, info->nand.ecc.size);
1312                 memset(oob, 0xFF, info->nand.ecc.bytes);
1313         }
1314
1315         return flip_bits;
1316 }
1317
1318 /**
1319  * omap_elm_correct_data - corrects page data area in case error reported
1320  * @mtd:        MTD device structure
1321  * @data:       page data
1322  * @read_ecc:   ecc read from nand flash
1323  * @calc_ecc:   ecc read from HW ECC registers
1324  *
1325  * Calculated ecc vector reported as zero in case of non-error pages.
1326  * In case of non-zero ecc vector, first filter out erased-pages, and
1327  * then process data via ELM to detect bit-flips.
1328  */
1329 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1330                                 u_char *read_ecc, u_char *calc_ecc)
1331 {
1332         struct omap_nand_info *info = mtd_to_omap(mtd);
1333         struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1334         int eccsteps = info->nand.ecc.steps;
1335         int i , j, stat = 0;
1336         int eccflag, actual_eccbytes;
1337         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1338         u_char *ecc_vec = calc_ecc;
1339         u_char *spare_ecc = read_ecc;
1340         u_char *erased_ecc_vec;
1341         u_char *buf;
1342         int bitflip_count;
1343         bool is_error_reported = false;
1344         u32 bit_pos, byte_pos, error_max, pos;
1345         int err;
1346
1347         switch (info->ecc_opt) {
1348         case OMAP_ECC_BCH4_CODE_HW:
1349                 /* omit  7th ECC byte reserved for ROM code compatibility */
1350                 actual_eccbytes = ecc->bytes - 1;
1351                 erased_ecc_vec = bch4_vector;
1352                 break;
1353         case OMAP_ECC_BCH8_CODE_HW:
1354                 /* omit 14th ECC byte reserved for ROM code compatibility */
1355                 actual_eccbytes = ecc->bytes - 1;
1356                 erased_ecc_vec = bch8_vector;
1357                 break;
1358         case OMAP_ECC_BCH16_CODE_HW:
1359                 actual_eccbytes = ecc->bytes;
1360                 erased_ecc_vec = bch16_vector;
1361                 break;
1362         default:
1363                 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1364                 return -EINVAL;
1365         }
1366
1367         /* Initialize elm error vector to zero */
1368         memset(err_vec, 0, sizeof(err_vec));
1369
1370         for (i = 0; i < eccsteps ; i++) {
1371                 eccflag = 0;    /* initialize eccflag */
1372
1373                 /*
1374                  * Check any error reported,
1375                  * In case of error, non zero ecc reported.
1376                  */
1377                 for (j = 0; j < actual_eccbytes; j++) {
1378                         if (calc_ecc[j] != 0) {
1379                                 eccflag = 1; /* non zero ecc, error present */
1380                                 break;
1381                         }
1382                 }
1383
1384                 if (eccflag == 1) {
1385                         if (memcmp(calc_ecc, erased_ecc_vec,
1386                                                 actual_eccbytes) == 0) {
1387                                 /*
1388                                  * calc_ecc[] matches pattern for ECC(all 0xff)
1389                                  * so this is definitely an erased-page
1390                                  */
1391                         } else {
1392                                 buf = &data[info->nand.ecc.size * i];
1393                                 /*
1394                                  * count number of 0-bits in read_buf.
1395                                  * This check can be removed once a similar
1396                                  * check is introduced in generic NAND driver
1397                                  */
1398                                 bitflip_count = erased_sector_bitflips(
1399                                                 buf, read_ecc, info);
1400                                 if (bitflip_count) {
1401                                         /*
1402                                          * number of 0-bits within ECC limits
1403                                          * So this may be an erased-page
1404                                          */
1405                                         stat += bitflip_count;
1406                                 } else {
1407                                         /*
1408                                          * Too many 0-bits. It may be a
1409                                          * - programmed-page, OR
1410                                          * - erased-page with many bit-flips
1411                                          * So this page requires check by ELM
1412                                          */
1413                                         err_vec[i].error_reported = true;
1414                                         is_error_reported = true;
1415                                 }
1416                         }
1417                 }
1418
1419                 /* Update the ecc vector */
1420                 calc_ecc += ecc->bytes;
1421                 read_ecc += ecc->bytes;
1422         }
1423
1424         /* Check if any error reported */
1425         if (!is_error_reported)
1426                 return stat;
1427
1428         /* Decode BCH error using ELM module */
1429         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1430
1431         err = 0;
1432         for (i = 0; i < eccsteps; i++) {
1433                 if (err_vec[i].error_uncorrectable) {
1434                         dev_err(&info->pdev->dev,
1435                                 "uncorrectable bit-flips found\n");
1436                         err = -EBADMSG;
1437                 } else if (err_vec[i].error_reported) {
1438                         for (j = 0; j < err_vec[i].error_count; j++) {
1439                                 switch (info->ecc_opt) {
1440                                 case OMAP_ECC_BCH4_CODE_HW:
1441                                         /* Add 4 bits to take care of padding */
1442                                         pos = err_vec[i].error_loc[j] +
1443                                                 BCH4_BIT_PAD;
1444                                         break;
1445                                 case OMAP_ECC_BCH8_CODE_HW:
1446                                 case OMAP_ECC_BCH16_CODE_HW:
1447                                         pos = err_vec[i].error_loc[j];
1448                                         break;
1449                                 default:
1450                                         return -EINVAL;
1451                                 }
1452                                 error_max = (ecc->size + actual_eccbytes) * 8;
1453                                 /* Calculate bit position of error */
1454                                 bit_pos = pos % 8;
1455
1456                                 /* Calculate byte position of error */
1457                                 byte_pos = (error_max - pos - 1) / 8;
1458
1459                                 if (pos < error_max) {
1460                                         if (byte_pos < 512) {
1461                                                 pr_debug("bitflip@dat[%d]=%x\n",
1462                                                      byte_pos, data[byte_pos]);
1463                                                 data[byte_pos] ^= 1 << bit_pos;
1464                                         } else {
1465                                                 pr_debug("bitflip@oob[%d]=%x\n",
1466                                                         (byte_pos - 512),
1467                                                      spare_ecc[byte_pos - 512]);
1468                                                 spare_ecc[byte_pos - 512] ^=
1469                                                         1 << bit_pos;
1470                                         }
1471                                 } else {
1472                                         dev_err(&info->pdev->dev,
1473                                                 "invalid bit-flip @ %d:%d\n",
1474                                                 byte_pos, bit_pos);
1475                                         err = -EBADMSG;
1476                                 }
1477                         }
1478                 }
1479
1480                 /* Update number of correctable errors */
1481                 stat += err_vec[i].error_count;
1482
1483                 /* Update page data with sector size */
1484                 data += ecc->size;
1485                 spare_ecc += ecc->bytes;
1486         }
1487
1488         return (err) ? err : stat;
1489 }
1490
1491 /**
1492  * omap_write_page_bch - BCH ecc based write page function for entire page
1493  * @mtd:                mtd info structure
1494  * @chip:               nand chip info structure
1495  * @buf:                data buffer
1496  * @oob_required:       must write chip->oob_poi to OOB
1497  * @page:               page
1498  *
1499  * Custom write page method evolved to support multi sector writing in one shot
1500  */
1501 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1502                                const uint8_t *buf, int oob_required, int page)
1503 {
1504         int i;
1505         uint8_t *ecc_calc = chip->buffers->ecccalc;
1506         uint32_t *eccpos = chip->ecc.layout->eccpos;
1507
1508         /* Enable GPMC ecc engine */
1509         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1510
1511         /* Write data */
1512         chip->write_buf(mtd, buf, mtd->writesize);
1513
1514         /* Update ecc vector from GPMC result registers */
1515         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1516
1517         for (i = 0; i < chip->ecc.total; i++)
1518                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1519
1520         /* Write ecc vector to OOB area */
1521         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1522         return 0;
1523 }
1524
1525 /**
1526  * omap_read_page_bch - BCH ecc based page read function for entire page
1527  * @mtd:                mtd info structure
1528  * @chip:               nand chip info structure
1529  * @buf:                buffer to store read data
1530  * @oob_required:       caller requires OOB data read to chip->oob_poi
1531  * @page:               page number to read
1532  *
1533  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1534  * used for error correction.
1535  * Custom method evolved to support ELM error correction & multi sector
1536  * reading. On reading page data area is read along with OOB data with
1537  * ecc engine enabled. ecc vector updated after read of OOB data.
1538  * For non error pages ecc vector reported as zero.
1539  */
1540 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1541                                 uint8_t *buf, int oob_required, int page)
1542 {
1543         uint8_t *ecc_calc = chip->buffers->ecccalc;
1544         uint8_t *ecc_code = chip->buffers->ecccode;
1545         uint32_t *eccpos = chip->ecc.layout->eccpos;
1546         uint8_t *oob = &chip->oob_poi[eccpos[0]];
1547         uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1548         int stat;
1549         unsigned int max_bitflips = 0;
1550
1551         /* Enable GPMC ecc engine */
1552         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1553
1554         /* Read data */
1555         chip->read_buf(mtd, buf, mtd->writesize);
1556
1557         /* Read oob bytes */
1558         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1559         chip->read_buf(mtd, oob, chip->ecc.total);
1560
1561         /* Calculate ecc bytes */
1562         chip->ecc.calculate(mtd, buf, ecc_calc);
1563
1564         memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1565
1566         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1567
1568         if (stat < 0) {
1569                 mtd->ecc_stats.failed++;
1570         } else {
1571                 mtd->ecc_stats.corrected += stat;
1572                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1573         }
1574
1575         return max_bitflips;
1576 }
1577
1578 /**
1579  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1580  * @omap_nand_info: NAND device structure containing platform data
1581  */
1582 static bool is_elm_present(struct omap_nand_info *info,
1583                            struct device_node *elm_node)
1584 {
1585         struct platform_device *pdev;
1586
1587         /* check whether elm-id is passed via DT */
1588         if (!elm_node) {
1589                 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1590                 return false;
1591         }
1592         pdev = of_find_device_by_node(elm_node);
1593         /* check whether ELM device is registered */
1594         if (!pdev) {
1595                 dev_err(&info->pdev->dev, "ELM device not found\n");
1596                 return false;
1597         }
1598         /* ELM module available, now configure it */
1599         info->elm_dev = &pdev->dev;
1600         return true;
1601 }
1602
1603 static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1604                                  struct omap_nand_platform_data *pdata)
1605 {
1606         bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1607
1608         switch (info->ecc_opt) {
1609         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1610         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1611                 ecc_needs_omap_bch = false;
1612                 ecc_needs_bch = true;
1613                 ecc_needs_elm = false;
1614                 break;
1615         case OMAP_ECC_BCH4_CODE_HW:
1616         case OMAP_ECC_BCH8_CODE_HW:
1617         case OMAP_ECC_BCH16_CODE_HW:
1618                 ecc_needs_omap_bch = true;
1619                 ecc_needs_bch = false;
1620                 ecc_needs_elm = true;
1621                 break;
1622         default:
1623                 ecc_needs_omap_bch = false;
1624                 ecc_needs_bch = false;
1625                 ecc_needs_elm = false;
1626                 break;
1627         }
1628
1629         if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1630                 dev_err(&info->pdev->dev,
1631                         "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1632                 return false;
1633         }
1634         if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1635                 dev_err(&info->pdev->dev,
1636                         "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1637                 return false;
1638         }
1639         if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1640                 dev_err(&info->pdev->dev, "ELM not available\n");
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static const char * const nand_xfer_types[] = {
1648         [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1649         [NAND_OMAP_POLLED] = "polled",
1650         [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1651         [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1652 };
1653
1654 static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info)
1655 {
1656         struct device_node *child = dev->of_node;
1657         int i;
1658         const char *s;
1659         u32 cs;
1660
1661         if (of_property_read_u32(child, "reg", &cs) < 0) {
1662                 dev_err(dev, "reg not found in DT\n");
1663                 return -EINVAL;
1664         }
1665
1666         info->gpmc_cs = cs;
1667
1668         /* detect availability of ELM module. Won't be present pre-OMAP4 */
1669         info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1670         if (!info->elm_of_node)
1671                 dev_dbg(dev, "ti,elm-id not in DT\n");
1672
1673         /* select ecc-scheme for NAND */
1674         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1675                 dev_err(dev, "ti,nand-ecc-opt not found\n");
1676                 return -EINVAL;
1677         }
1678
1679         if (!strcmp(s, "sw")) {
1680                 info->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1681         } else if (!strcmp(s, "ham1") ||
1682                    !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) {
1683                 info->ecc_opt = OMAP_ECC_HAM1_CODE_HW;
1684         } else if (!strcmp(s, "bch4")) {
1685                 if (info->elm_of_node)
1686                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW;
1687                 else
1688                         info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1689         } else if (!strcmp(s, "bch8")) {
1690                 if (info->elm_of_node)
1691                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW;
1692                 else
1693                         info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1694         } else if (!strcmp(s, "bch16")) {
1695                 info->ecc_opt = OMAP_ECC_BCH16_CODE_HW;
1696         } else {
1697                 dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n");
1698                 return -EINVAL;
1699         }
1700
1701         /* select data transfer mode */
1702         if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) {
1703                 for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) {
1704                         if (!strcasecmp(s, nand_xfer_types[i])) {
1705                                 info->xfer_type = i;
1706                                 goto next;
1707                         }
1708                 }
1709
1710                 dev_err(dev, "unrecognized value for ti,nand-xfer-type\n");
1711                 return -EINVAL;
1712         }
1713
1714 next:
1715         of_get_nand_on_flash_bbt(child);
1716
1717         if (of_get_nand_bus_width(child) == 16)
1718                 info->devsize = NAND_BUSWIDTH_16;
1719
1720         return 0;
1721 }
1722
1723 static int omap_nand_probe(struct platform_device *pdev)
1724 {
1725         struct omap_nand_info           *info;
1726         struct omap_nand_platform_data  *pdata = NULL;
1727         struct mtd_info                 *mtd;
1728         struct nand_chip                *nand_chip;
1729         struct nand_ecclayout           *ecclayout;
1730         int                             err;
1731         int                             i;
1732         dma_cap_mask_t                  mask;
1733         unsigned                        sig;
1734         unsigned                        oob_index;
1735         struct resource                 *res;
1736         struct device                   *dev = &pdev->dev;
1737
1738         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1739                                 GFP_KERNEL);
1740         if (!info)
1741                 return -ENOMEM;
1742
1743         info->pdev = pdev;
1744
1745         if (dev->of_node) {
1746                 if (omap_get_dt_info(dev, info))
1747                         return -EINVAL;
1748         } else {
1749                 pdata = dev_get_platdata(&pdev->dev);
1750                 if (!pdata) {
1751                         dev_err(&pdev->dev, "platform data missing\n");
1752                         return -EINVAL;
1753                 }
1754
1755                 info->gpmc_cs = pdata->cs;
1756                 info->reg = pdata->reg;
1757                 info->ecc_opt = pdata->ecc_opt;
1758                 info->dev_ready = pdata->dev_ready;
1759                 info->xfer_type = pdata->xfer_type;
1760                 info->devsize = pdata->devsize;
1761                 info->elm_of_node = pdata->elm_of_node;
1762                 info->flash_bbt = pdata->flash_bbt;
1763         }
1764
1765         platform_set_drvdata(pdev, info);
1766         info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
1767         if (!info->ops) {
1768                 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
1769                 return -ENODEV;
1770         }
1771
1772         nand_chip               = &info->nand;
1773         mtd                     = nand_to_mtd(nand_chip);
1774         mtd->dev.parent         = &pdev->dev;
1775         nand_chip->ecc.priv     = NULL;
1776         nand_set_flash_node(nand_chip, dev->of_node);
1777
1778         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1779         nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1780         if (IS_ERR(nand_chip->IO_ADDR_R))
1781                 return PTR_ERR(nand_chip->IO_ADDR_R);
1782
1783         info->phys_base = res->start;
1784
1785         nand_chip->controller = &omap_gpmc_controller;
1786
1787         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1788         nand_chip->cmd_ctrl  = omap_hwcontrol;
1789
1790         /*
1791          * If RDY/BSY line is connected to OMAP then use the omap ready
1792          * function and the generic nand_wait function which reads the status
1793          * register after monitoring the RDY/BSY line. Otherwise use a standard
1794          * chip delay which is slightly more than tR (AC Timing) of the NAND
1795          * device and read status register until you get a failure or success
1796          */
1797         if (info->dev_ready) {
1798                 nand_chip->dev_ready = omap_dev_ready;
1799                 nand_chip->chip_delay = 0;
1800         } else {
1801                 nand_chip->waitfunc = omap_wait;
1802                 nand_chip->chip_delay = 50;
1803         }
1804
1805         if (info->flash_bbt)
1806                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1807         else
1808                 nand_chip->options |= NAND_SKIP_BBTSCAN;
1809
1810         /* scan NAND device connected to chip controller */
1811         nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
1812         if (nand_scan_ident(mtd, 1, NULL)) {
1813                 dev_err(&info->pdev->dev,
1814                         "scan failed, may be bus-width mismatch\n");
1815                 err = -ENXIO;
1816                 goto return_error;
1817         }
1818
1819         /* re-populate low-level callbacks based on xfer modes */
1820         switch (info->xfer_type) {
1821         case NAND_OMAP_PREFETCH_POLLED:
1822                 nand_chip->read_buf   = omap_read_buf_pref;
1823                 nand_chip->write_buf  = omap_write_buf_pref;
1824                 break;
1825
1826         case NAND_OMAP_POLLED:
1827                 /* Use nand_base defaults for {read,write}_buf */
1828                 break;
1829
1830         case NAND_OMAP_PREFETCH_DMA:
1831                 dma_cap_zero(mask);
1832                 dma_cap_set(DMA_SLAVE, mask);
1833                 sig = OMAP24XX_DMA_GPMC;
1834                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1835                 if (!info->dma) {
1836                         dev_err(&pdev->dev, "DMA engine request failed\n");
1837                         err = -ENXIO;
1838                         goto return_error;
1839                 } else {
1840                         struct dma_slave_config cfg;
1841
1842                         memset(&cfg, 0, sizeof(cfg));
1843                         cfg.src_addr = info->phys_base;
1844                         cfg.dst_addr = info->phys_base;
1845                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1846                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1847                         cfg.src_maxburst = 16;
1848                         cfg.dst_maxburst = 16;
1849                         err = dmaengine_slave_config(info->dma, &cfg);
1850                         if (err) {
1851                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1852                                         err);
1853                                 goto return_error;
1854                         }
1855                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1856                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1857                 }
1858                 break;
1859
1860         case NAND_OMAP_PREFETCH_IRQ:
1861                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1862                 if (info->gpmc_irq_fifo <= 0) {
1863                         dev_err(&pdev->dev, "error getting fifo irq\n");
1864                         err = -ENODEV;
1865                         goto return_error;
1866                 }
1867                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1868                                         omap_nand_irq, IRQF_SHARED,
1869                                         "gpmc-nand-fifo", info);
1870                 if (err) {
1871                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1872                                                 info->gpmc_irq_fifo, err);
1873                         info->gpmc_irq_fifo = 0;
1874                         goto return_error;
1875                 }
1876
1877                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1878                 if (info->gpmc_irq_count <= 0) {
1879                         dev_err(&pdev->dev, "error getting count irq\n");
1880                         err = -ENODEV;
1881                         goto return_error;
1882                 }
1883                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1884                                         omap_nand_irq, IRQF_SHARED,
1885                                         "gpmc-nand-count", info);
1886                 if (err) {
1887                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1888                                                 info->gpmc_irq_count, err);
1889                         info->gpmc_irq_count = 0;
1890                         goto return_error;
1891                 }
1892
1893                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1894                 nand_chip->write_buf = omap_write_buf_irq_pref;
1895
1896                 break;
1897
1898         default:
1899                 dev_err(&pdev->dev,
1900                         "xfer_type(%d) not supported!\n", info->xfer_type);
1901                 err = -EINVAL;
1902                 goto return_error;
1903         }
1904
1905         if (!omap2_nand_ecc_check(info, pdata)) {
1906                 err = -EINVAL;
1907                 goto return_error;
1908         }
1909
1910         /*
1911          * Bail out earlier to let NAND_ECC_SOFT code create its own
1912          * ecclayout instead of using ours.
1913          */
1914         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
1915                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1916                 goto scan_tail;
1917         }
1918
1919         /* populate MTD interface based on ECC scheme */
1920         ecclayout               = &info->oobinfo;
1921         nand_chip->ecc.layout   = ecclayout;
1922         switch (info->ecc_opt) {
1923         case OMAP_ECC_HAM1_CODE_HW:
1924                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1925                 nand_chip->ecc.mode             = NAND_ECC_HW;
1926                 nand_chip->ecc.bytes            = 3;
1927                 nand_chip->ecc.size             = 512;
1928                 nand_chip->ecc.strength         = 1;
1929                 nand_chip->ecc.calculate        = omap_calculate_ecc;
1930                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
1931                 nand_chip->ecc.correct          = omap_correct_data;
1932                 /* define ECC layout */
1933                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1934                                                         (mtd->writesize /
1935                                                         nand_chip->ecc.size);
1936                 if (nand_chip->options & NAND_BUSWIDTH_16)
1937                         oob_index               = BADBLOCK_MARKER_LENGTH;
1938                 else
1939                         oob_index               = 1;
1940                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1941                         ecclayout->eccpos[i]    = oob_index;
1942                 /* no reserved-marker in ecclayout for this ecc-scheme */
1943                 ecclayout->oobfree->offset      =
1944                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1945                 break;
1946
1947         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1948                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1949                 nand_chip->ecc.mode             = NAND_ECC_HW;
1950                 nand_chip->ecc.size             = 512;
1951                 nand_chip->ecc.bytes            = 7;
1952                 nand_chip->ecc.strength         = 4;
1953                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1954                 nand_chip->ecc.correct          = nand_bch_correct_data;
1955                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1956                 /* define ECC layout */
1957                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1958                                                         (mtd->writesize /
1959                                                         nand_chip->ecc.size);
1960                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1961                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1962                         ecclayout->eccpos[i] = oob_index;
1963                         if (((i + 1) % nand_chip->ecc.bytes) == 0)
1964                                 oob_index++;
1965                 }
1966                 /* include reserved-marker in ecclayout->oobfree calculation */
1967                 ecclayout->oobfree->offset      = 1 +
1968                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1969                 /* software bch library is used for locating errors */
1970                 nand_chip->ecc.priv             = nand_bch_init(mtd);
1971                 if (!nand_chip->ecc.priv) {
1972                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
1973                         err = -EINVAL;
1974                         goto return_error;
1975                 }
1976                 break;
1977
1978         case OMAP_ECC_BCH4_CODE_HW:
1979                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1980                 nand_chip->ecc.mode             = NAND_ECC_HW;
1981                 nand_chip->ecc.size             = 512;
1982                 /* 14th bit is kept reserved for ROM-code compatibility */
1983                 nand_chip->ecc.bytes            = 7 + 1;
1984                 nand_chip->ecc.strength         = 4;
1985                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1986                 nand_chip->ecc.correct          = omap_elm_correct_data;
1987                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1988                 nand_chip->ecc.read_page        = omap_read_page_bch;
1989                 nand_chip->ecc.write_page       = omap_write_page_bch;
1990                 /* define ECC layout */
1991                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1992                                                         (mtd->writesize /
1993                                                         nand_chip->ecc.size);
1994                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1995                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1996                         ecclayout->eccpos[i]    = oob_index;
1997                 /* reserved marker already included in ecclayout->eccbytes */
1998                 ecclayout->oobfree->offset      =
1999                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2000
2001                 err = elm_config(info->elm_dev, BCH4_ECC,
2002                                  mtd->writesize / nand_chip->ecc.size,
2003                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2004                 if (err < 0)
2005                         goto return_error;
2006                 break;
2007
2008         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
2009                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2010                 nand_chip->ecc.mode             = NAND_ECC_HW;
2011                 nand_chip->ecc.size             = 512;
2012                 nand_chip->ecc.bytes            = 13;
2013                 nand_chip->ecc.strength         = 8;
2014                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2015                 nand_chip->ecc.correct          = nand_bch_correct_data;
2016                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2017                 /* define ECC layout */
2018                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
2019                                                         (mtd->writesize /
2020                                                         nand_chip->ecc.size);
2021                 oob_index                       = BADBLOCK_MARKER_LENGTH;
2022                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
2023                         ecclayout->eccpos[i] = oob_index;
2024                         if (((i + 1) % nand_chip->ecc.bytes) == 0)
2025                                 oob_index++;
2026                 }
2027                 /* include reserved-marker in ecclayout->oobfree calculation */
2028                 ecclayout->oobfree->offset      = 1 +
2029                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2030                 /* software bch library is used for locating errors */
2031                 nand_chip->ecc.priv             = nand_bch_init(mtd);
2032                 if (!nand_chip->ecc.priv) {
2033                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
2034                         err = -EINVAL;
2035                         goto return_error;
2036                 }
2037                 break;
2038
2039         case OMAP_ECC_BCH8_CODE_HW:
2040                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2041                 nand_chip->ecc.mode             = NAND_ECC_HW;
2042                 nand_chip->ecc.size             = 512;
2043                 /* 14th bit is kept reserved for ROM-code compatibility */
2044                 nand_chip->ecc.bytes            = 13 + 1;
2045                 nand_chip->ecc.strength         = 8;
2046                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2047                 nand_chip->ecc.correct          = omap_elm_correct_data;
2048                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2049                 nand_chip->ecc.read_page        = omap_read_page_bch;
2050                 nand_chip->ecc.write_page       = omap_write_page_bch;
2051
2052                 err = elm_config(info->elm_dev, BCH8_ECC,
2053                                  mtd->writesize / nand_chip->ecc.size,
2054                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2055                 if (err < 0)
2056                         goto return_error;
2057
2058                 /* define ECC layout */
2059                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
2060                                                         (mtd->writesize /
2061                                                         nand_chip->ecc.size);
2062                 oob_index                       = BADBLOCK_MARKER_LENGTH;
2063                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
2064                         ecclayout->eccpos[i]    = oob_index;
2065                 /* reserved marker already included in ecclayout->eccbytes */
2066                 ecclayout->oobfree->offset      =
2067                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2068                 break;
2069
2070         case OMAP_ECC_BCH16_CODE_HW:
2071                 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2072                 nand_chip->ecc.mode             = NAND_ECC_HW;
2073                 nand_chip->ecc.size             = 512;
2074                 nand_chip->ecc.bytes            = 26;
2075                 nand_chip->ecc.strength         = 16;
2076                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
2077                 nand_chip->ecc.correct          = omap_elm_correct_data;
2078                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
2079                 nand_chip->ecc.read_page        = omap_read_page_bch;
2080                 nand_chip->ecc.write_page       = omap_write_page_bch;
2081
2082                 err = elm_config(info->elm_dev, BCH16_ECC,
2083                                  mtd->writesize / nand_chip->ecc.size,
2084                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2085                 if (err < 0)
2086                         goto return_error;
2087
2088                 /* define ECC layout */
2089                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
2090                                                         (mtd->writesize /
2091                                                         nand_chip->ecc.size);
2092                 oob_index                       = BADBLOCK_MARKER_LENGTH;
2093                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
2094                         ecclayout->eccpos[i]    = oob_index;
2095                 /* reserved marker already included in ecclayout->eccbytes */
2096                 ecclayout->oobfree->offset      =
2097                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2098                 break;
2099         default:
2100                 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
2101                 err = -EINVAL;
2102                 goto return_error;
2103         }
2104
2105         /* all OOB bytes from oobfree->offset till end off OOB are free */
2106         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2107         /* check if NAND device's OOB is enough to store ECC signatures */
2108         if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2109                 dev_err(&info->pdev->dev,
2110                         "not enough OOB bytes required = %d, available=%d\n",
2111                         ecclayout->eccbytes, mtd->oobsize);
2112                 err = -EINVAL;
2113                 goto return_error;
2114         }
2115
2116 scan_tail:
2117         /* second phase scan */
2118         if (nand_scan_tail(mtd)) {
2119                 err = -ENXIO;
2120                 goto return_error;
2121         }
2122
2123         if (dev->of_node)
2124                 mtd_device_register(mtd, NULL, 0);
2125         else
2126                 mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2127
2128         platform_set_drvdata(pdev, mtd);
2129
2130         return 0;
2131
2132 return_error:
2133         if (info->dma)
2134                 dma_release_channel(info->dma);
2135         if (nand_chip->ecc.priv) {
2136                 nand_bch_free(nand_chip->ecc.priv);
2137                 nand_chip->ecc.priv = NULL;
2138         }
2139         return err;
2140 }
2141
2142 static int omap_nand_remove(struct platform_device *pdev)
2143 {
2144         struct mtd_info *mtd = platform_get_drvdata(pdev);
2145         struct nand_chip *nand_chip = mtd_to_nand(mtd);
2146         struct omap_nand_info *info = mtd_to_omap(mtd);
2147         if (nand_chip->ecc.priv) {
2148                 nand_bch_free(nand_chip->ecc.priv);
2149                 nand_chip->ecc.priv = NULL;
2150         }
2151         if (info->dma)
2152                 dma_release_channel(info->dma);
2153         nand_release(mtd);
2154         return 0;
2155 }
2156
2157 static const struct of_device_id omap_nand_ids[] = {
2158         { .compatible = "ti,omap2-nand", },
2159         {},
2160 };
2161
2162 static struct platform_driver omap_nand_driver = {
2163         .probe          = omap_nand_probe,
2164         .remove         = omap_nand_remove,
2165         .driver         = {
2166                 .name   = DRIVER_NAME,
2167                 .of_match_table = of_match_ptr(omap_nand_ids),
2168         },
2169 };
2170
2171 module_platform_driver(omap_nand_driver);
2172
2173 MODULE_ALIAS("platform:" DRIVER_NAME);
2174 MODULE_LICENSE("GPL");
2175 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");