drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/sched.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/omap-dma.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <linux/mtd/nand_bch.h>
  29 #include <linux/platform_data/elm.h>
  30
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/platform_data/mtd-nand-omap2.h>
  33
  34 #define DRIVER_NAME     "omap2-nand"
  35 #define OMAP_NAND_TIMEOUT_MS    5000
  36
  37 #define NAND_Ecc_P1e            (1 << 0)
  38 #define NAND_Ecc_P2e            (1 << 1)
  39 #define NAND_Ecc_P4e            (1 << 2)
  40 #define NAND_Ecc_P8e            (1 << 3)
  41 #define NAND_Ecc_P16e           (1 << 4)
  42 #define NAND_Ecc_P32e           (1 << 5)
  43 #define NAND_Ecc_P64e           (1 << 6)
  44 #define NAND_Ecc_P128e          (1 << 7)
  45 #define NAND_Ecc_P256e          (1 << 8)
  46 #define NAND_Ecc_P512e          (1 << 9)
  47 #define NAND_Ecc_P1024e         (1 << 10)
  48 #define NAND_Ecc_P2048e         (1 << 11)
  49
  50 #define NAND_Ecc_P1o            (1 << 16)
  51 #define NAND_Ecc_P2o            (1 << 17)
  52 #define NAND_Ecc_P4o            (1 << 18)
  53 #define NAND_Ecc_P8o            (1 << 19)
  54 #define NAND_Ecc_P16o           (1 << 20)
  55 #define NAND_Ecc_P32o           (1 << 21)
  56 #define NAND_Ecc_P64o           (1 << 22)
  57 #define NAND_Ecc_P128o          (1 << 23)
  58 #define NAND_Ecc_P256o          (1 << 24)
  59 #define NAND_Ecc_P512o          (1 << 25)
  60 #define NAND_Ecc_P1024o         (1 << 26)
  61 #define NAND_Ecc_P2048o         (1 << 27)
  62
  63 #define TF(value)       (value ? 1 : 0)
  64
  65 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  66 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  67 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  68 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  69 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  70 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  71 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  72 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  73
  74 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  75 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  76 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  77 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  78 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  79 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  80 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  81 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  82
  83 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  84 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  85 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  86 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  87 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  88 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  89 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  90 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  91
  92 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  93 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  94 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  95 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  96 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  97 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  98 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  99 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
 100
 101 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 102 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 103
 104 #define PREFETCH_CONFIG1_CS_SHIFT       24
 105 #define ECC_CONFIG_CS_SHIFT             1
 106 #define CS_MASK                         0x7
 107 #define ENABLE_PREFETCH                 (0x1 << 7)
 108 #define DMA_MPU_MODE_SHIFT              2
 109 #define ECCSIZE0_SHIFT                  12
 110 #define ECCSIZE1_SHIFT                  22
 111 #define ECC1RESULTSIZE                  0x1
 112 #define ECCCLEAR                        0x100
 113 #define ECC1                            0x1
 114 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 115 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 116 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 117 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 118 #define STATUS_BUFF_EMPTY               0x00000001
 119
 120 #define OMAP24XX_DMA_GPMC               4
 121
 122 #define SECTOR_BYTES            512
 123 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 124 #define BCH4_BIT_PAD            4
 125
 126 /* GPMC ecc engine settings for read */
 127 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
 128 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
 129 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
 130 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
 131 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
 132
 133 /* GPMC ecc engine settings for write */
 134 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
 135 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
 136 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
 137
 138 #define BADBLOCK_MARKER_LENGTH          2
 139
 140 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
 141                                 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
 142                                 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
 143                                 0x07, 0x0e};
 144 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 145         0xac, 0x6b, 0xff, 0x99, 0x7b};
 146 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 147
 148 /* Shared among all NAND instances to synchronize access to the ECC Engine */
 149 static struct nand_hw_control omap_gpmc_controller = {
 150         .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
 151         .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
 152 };
 153
 154 struct omap_nand_info {
 155         struct nand_chip                nand;
 156         struct platform_device          *pdev;
 157
 158         int                             gpmc_cs;
 159         bool                            dev_ready;
 160         enum nand_io                    xfer_type;
 161         int                             devsize;
 162         enum omap_ecc                   ecc_opt;
 163         struct device_node              *elm_of_node;
 164
 165         unsigned long                   phys_base;
 166         struct completion               comp;
 167         struct dma_chan                 *dma;
 168         int                             gpmc_irq_fifo;
 169         int                             gpmc_irq_count;
 170         enum {
 171                 OMAP_NAND_IO_READ = 0,  /* read */
 172                 OMAP_NAND_IO_WRITE,     /* write */
 173         } iomode;
 174         u_char                          *buf;
 175         int                                     buf_len;
 176         /* Interface to GPMC */
 177         struct gpmc_nand_regs           reg;
 178         struct gpmc_nand_ops            *ops;
 179         /* generated at runtime depending on ECC algorithm and layout selected */
 180         struct nand_ecclayout           oobinfo;
 181         /* fields specific for BCHx_HW ECC scheme */
 182         struct device                   *elm_dev;
 183         struct device_node              *of_node;
 184 };
 185
 186 static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd)
 187 {
 188         return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand);
 189 }
 190
 191 /**
 192  * omap_prefetch_enable - configures and starts prefetch transfer
 193  * @cs: cs (chip select) number
 194  * @fifo_th: fifo threshold to be used for read/ write
 195  * @dma_mode: dma mode enable (1) or disable (0)
 196  * @u32_count: number of bytes to be transferred
 197  * @is_write: prefetch read(0) or write post(1) mode
 198  */
 199 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 200         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 201 {
 202         u32 val;
 203
 204         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 205                 return -1;
 206
 207         if (readl(info->reg.gpmc_prefetch_control))
 208                 return -EBUSY;
 209
 210         /* Set the amount of bytes to be prefetched */
 211         writel(u32_count, info->reg.gpmc_prefetch_config2);
 212
 213         /* Set dma/mpu mode, the prefetch read / post write and
 214          * enable the engine. Set which cs is has requested for.
 215          */
 216         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 217                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 218                 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
 219         writel(val, info->reg.gpmc_prefetch_config1);
 220
 221         /*  Start the prefetch engine */
 222         writel(0x1, info->reg.gpmc_prefetch_control);
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * omap_prefetch_reset - disables and stops the prefetch engine
 229  */
 230 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 231 {
 232         u32 config1;
 233
 234         /* check if the same module/cs is trying to reset */
 235         config1 = readl(info->reg.gpmc_prefetch_config1);
 236         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 237                 return -EINVAL;
 238
 239         /* Stop the PFPW engine */
 240         writel(0x0, info->reg.gpmc_prefetch_control);
 241
 242         /* Reset/disable the PFPW engine */
 243         writel(0x0, info->reg.gpmc_prefetch_config1);
 244
 245         return 0;
 246 }
 247
 248 /**
 249  * omap_hwcontrol - hardware specific access to control-lines
 250  * @mtd: MTD device structure
 251  * @cmd: command to device
 252  * @ctrl:
 253  * NAND_NCE: bit 0 -> don't care
 254  * NAND_CLE: bit 1 -> Command Latch
 255  * NAND_ALE: bit 2 -> Address Latch
 256  *
 257  * NOTE: boards may use different bits for these!!
 258  */
 259 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 260 {
 261         struct omap_nand_info *info = mtd_to_omap(mtd);
 262
 263         if (cmd != NAND_CMD_NONE) {
 264                 if (ctrl & NAND_CLE)
 265                         writeb(cmd, info->reg.gpmc_nand_command);
 266
 267                 else if (ctrl & NAND_ALE)
 268                         writeb(cmd, info->reg.gpmc_nand_address);
 269
 270                 else /* NAND_NCE */
 271                         writeb(cmd, info->reg.gpmc_nand_data);
 272         }
 273 }
 274
 275 /**
 276  * omap_read_buf8 - read data from NAND controller into buffer
 277  * @mtd: MTD device structure
 278  * @buf: buffer to store date
 279  * @len: number of bytes to read
 280  */
 281 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 282 {
 283         struct nand_chip *nand = mtd_to_nand(mtd);
 284
 285         ioread8_rep(nand->IO_ADDR_R, buf, len);
 286 }
 287
 288 /**
 289  * omap_write_buf8 - write buffer to NAND controller
 290  * @mtd: MTD device structure
 291  * @buf: data buffer
 292  * @len: number of bytes to write
 293  */
 294 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 295 {
 296         struct omap_nand_info *info = mtd_to_omap(mtd);
 297         u_char *p = (u_char *)buf;
 298         bool status;
 299
 300         while (len--) {
 301                 iowrite8(*p++, info->nand.IO_ADDR_W);
 302                 /* wait until buffer is available for write */
 303                 do {
 304                         status = info->ops->nand_writebuffer_empty();
 305                 } while (!status);
 306         }
 307 }
 308
 309 /**
 310  * omap_read_buf16 - read data from NAND controller into buffer
 311  * @mtd: MTD device structure
 312  * @buf: buffer to store date
 313  * @len: number of bytes to read
 314  */
 315 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 316 {
 317         struct nand_chip *nand = mtd_to_nand(mtd);
 318
 319         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 320 }
 321
 322 /**
 323  * omap_write_buf16 - write buffer to NAND controller
 324  * @mtd: MTD device structure
 325  * @buf: data buffer
 326  * @len: number of bytes to write
 327  */
 328 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 329 {
 330         struct omap_nand_info *info = mtd_to_omap(mtd);
 331         u16 *p = (u16 *) buf;
 332         bool status;
 333         /* FIXME try bursts of writesw() or DMA ... */
 334         len >>= 1;
 335
 336         while (len--) {
 337                 iowrite16(*p++, info->nand.IO_ADDR_W);
 338                 /* wait until buffer is available for write */
 339                 do {
 340                         status = info->ops->nand_writebuffer_empty();
 341                 } while (!status);
 342         }
 343 }
 344
 345 /**
 346  * omap_read_buf_pref - read data from NAND controller into buffer
 347  * @mtd: MTD device structure
 348  * @buf: buffer to store date
 349  * @len: number of bytes to read
 350  */
 351 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 352 {
 353         struct omap_nand_info *info = mtd_to_omap(mtd);
 354         uint32_t r_count = 0;
 355         int ret = 0;
 356         u32 *p = (u32 *)buf;
 357
 358         /* take care of subpage reads */
 359         if (len % 4) {
 360                 if (info->nand.options & NAND_BUSWIDTH_16)
 361                         omap_read_buf16(mtd, buf, len % 4);
 362                 else
 363                         omap_read_buf8(mtd, buf, len % 4);
 364                 p = (u32 *) (buf + len % 4);
 365                 len -= len % 4;
 366         }
 367
 368         /* configure and start prefetch transfer */
 369         ret = omap_prefetch_enable(info->gpmc_cs,
 370                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 371         if (ret) {
 372                 /* PFPW engine is busy, use cpu copy method */
 373                 if (info->nand.options & NAND_BUSWIDTH_16)
 374                         omap_read_buf16(mtd, (u_char *)p, len);
 375                 else
 376                         omap_read_buf8(mtd, (u_char *)p, len);
 377         } else {
 378                 do {
 379                         r_count = readl(info->reg.gpmc_prefetch_status);
 380                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
 381                         r_count = r_count >> 2;
 382                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 383                         p += r_count;
 384                         len -= r_count << 2;
 385                 } while (len);
 386                 /* disable and stop the PFPW engine */
 387                 omap_prefetch_reset(info->gpmc_cs, info);
 388         }
 389 }
 390
 391 /**
 392  * omap_write_buf_pref - write buffer to NAND controller
 393  * @mtd: MTD device structure
 394  * @buf: data buffer
 395  * @len: number of bytes to write
 396  */
 397 static void omap_write_buf_pref(struct mtd_info *mtd,
 398                                         const u_char *buf, int len)
 399 {
 400         struct omap_nand_info *info = mtd_to_omap(mtd);
 401         uint32_t w_count = 0;
 402         int i = 0, ret = 0;
 403         u16 *p = (u16 *)buf;
 404         unsigned long tim, limit;
 405         u32 val;
 406
 407         /* take care of subpage writes */
 408         if (len % 2 != 0) {
 409                 writeb(*buf, info->nand.IO_ADDR_W);
 410                 p = (u16 *)(buf + 1);
 411                 len--;
 412         }
 413
 414         /*  configure and start prefetch transfer */
 415         ret = omap_prefetch_enable(info->gpmc_cs,
 416                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 417         if (ret) {
 418                 /* PFPW engine is busy, use cpu copy method */
 419                 if (info->nand.options & NAND_BUSWIDTH_16)
 420                         omap_write_buf16(mtd, (u_char *)p, len);
 421                 else
 422                         omap_write_buf8(mtd, (u_char *)p, len);
 423         } else {
 424                 while (len) {
 425                         w_count = readl(info->reg.gpmc_prefetch_status);
 426                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
 427                         w_count = w_count >> 1;
 428                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 429                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 430                 }
 431                 /* wait for data to flushed-out before reset the prefetch */
 432                 tim = 0;
 433                 limit = (loops_per_jiffy *
 434                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 435                 do {
 436                         cpu_relax();
 437                         val = readl(info->reg.gpmc_prefetch_status);
 438                         val = PREFETCH_STATUS_COUNT(val);
 439                 } while (val && (tim++ < limit));
 440
 441                 /* disable and stop the PFPW engine */
 442                 omap_prefetch_reset(info->gpmc_cs, info);
 443         }
 444 }
 445
 446 /*
 447  * omap_nand_dma_callback: callback on the completion of dma transfer
 448  * @data: pointer to completion data structure
 449  */
 450 static void omap_nand_dma_callback(void *data)
 451 {
 452         complete((struct completion *) data);
 453 }
 454
 455 /*
 456  * omap_nand_dma_transfer: configure and start dma transfer
 457  * @mtd: MTD device structure
 458  * @addr: virtual address in RAM of source/destination
 459  * @len: number of data bytes to be transferred
 460  * @is_write: flag for read/write operation
 461  */
 462 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 463                                         unsigned int len, int is_write)
 464 {
 465         struct omap_nand_info *info = mtd_to_omap(mtd);
 466         struct dma_async_tx_descriptor *tx;
 467         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 468                                                         DMA_FROM_DEVICE;
 469         struct scatterlist sg;
 470         unsigned long tim, limit;
 471         unsigned n;
 472         int ret;
 473         u32 val;
 474
 475         if (addr >= high_memory) {
 476                 struct page *p1;
 477
 478                 if (((size_t)addr & PAGE_MASK) !=
 479                         ((size_t)(addr + len - 1) & PAGE_MASK))
 480                         goto out_copy;
 481                 p1 = vmalloc_to_page(addr);
 482                 if (!p1)
 483                         goto out_copy;
 484                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 485         }
 486
 487         sg_init_one(&sg, addr, len);
 488         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 489         if (n == 0) {
 490                 dev_err(&info->pdev->dev,
 491                         "Couldn't DMA map a %d byte buffer\n", len);
 492                 goto out_copy;
 493         }
 494
 495         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 496                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 497                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 498         if (!tx)
 499                 goto out_copy_unmap;
 500
 501         tx->callback = omap_nand_dma_callback;
 502         tx->callback_param = &info->comp;
 503         dmaengine_submit(tx);
 504
 505         /*  configure and start prefetch transfer */
 506         ret = omap_prefetch_enable(info->gpmc_cs,
 507                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 508         if (ret)
 509                 /* PFPW engine is busy, use cpu copy method */
 510                 goto out_copy_unmap;
 511
 512         init_completion(&info->comp);
 513         dma_async_issue_pending(info->dma);
 514
 515         /* setup and start DMA using dma_addr */
 516         wait_for_completion(&info->comp);
 517         tim = 0;
 518         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 519
 520         do {
 521                 cpu_relax();
 522                 val = readl(info->reg.gpmc_prefetch_status);
 523                 val = PREFETCH_STATUS_COUNT(val);
 524         } while (val && (tim++ < limit));
 525
 526         /* disable and stop the PFPW engine */
 527         omap_prefetch_reset(info->gpmc_cs, info);
 528
 529         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 530         return 0;
 531
 532 out_copy_unmap:
 533         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 534 out_copy:
 535         if (info->nand.options & NAND_BUSWIDTH_16)
 536                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 537                         : omap_write_buf16(mtd, (u_char *) addr, len);
 538         else
 539                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 540                         : omap_write_buf8(mtd, (u_char *) addr, len);
 541         return 0;
 542 }
 543
 544 /**
 545  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 546  * @mtd: MTD device structure
 547  * @buf: buffer to store date
 548  * @len: number of bytes to read
 549  */
 550 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 551 {
 552         if (len <= mtd->oobsize)
 553                 omap_read_buf_pref(mtd, buf, len);
 554         else
 555                 /* start transfer in DMA mode */
 556                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 557 }
 558
 559 /**
 560  * omap_write_buf_dma_pref - write buffer to NAND controller
 561  * @mtd: MTD device structure
 562  * @buf: data buffer
 563  * @len: number of bytes to write
 564  */
 565 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 566                                         const u_char *buf, int len)
 567 {
 568         if (len <= mtd->oobsize)
 569                 omap_write_buf_pref(mtd, buf, len);
 570         else
 571                 /* start transfer in DMA mode */
 572                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 573 }
 574
 575 /*
 576  * omap_nand_irq - GPMC irq handler
 577  * @this_irq: gpmc irq number
 578  * @dev: omap_nand_info structure pointer is passed here
 579  */
 580 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 581 {
 582         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 583         u32 bytes;
 584
 585         bytes = readl(info->reg.gpmc_prefetch_status);
 586         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 587         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 588         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 589                 if (this_irq == info->gpmc_irq_count)
 590                         goto done;
 591
 592                 if (info->buf_len && (info->buf_len < bytes))
 593                         bytes = info->buf_len;
 594                 else if (!info->buf_len)
 595                         bytes = 0;
 596                 iowrite32_rep(info->nand.IO_ADDR_W,
 597                                                 (u32 *)info->buf, bytes >> 2);
 598                 info->buf = info->buf + bytes;
 599                 info->buf_len -= bytes;
 600
 601         } else {
 602                 ioread32_rep(info->nand.IO_ADDR_R,
 603                                                 (u32 *)info->buf, bytes >> 2);
 604                 info->buf = info->buf + bytes;
 605
 606                 if (this_irq == info->gpmc_irq_count)
 607                         goto done;
 608         }
 609
 610         return IRQ_HANDLED;
 611
 612 done:
 613         complete(&info->comp);
 614
 615         disable_irq_nosync(info->gpmc_irq_fifo);
 616         disable_irq_nosync(info->gpmc_irq_count);
 617
 618         return IRQ_HANDLED;
 619 }
 620
 621 /*
 622  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 623  * @mtd: MTD device structure
 624  * @buf: buffer to store date
 625  * @len: number of bytes to read
 626  */
 627 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 628 {
 629         struct omap_nand_info *info = mtd_to_omap(mtd);
 630         int ret = 0;
 631
 632         if (len <= mtd->oobsize) {
 633                 omap_read_buf_pref(mtd, buf, len);
 634                 return;
 635         }
 636
 637         info->iomode = OMAP_NAND_IO_READ;
 638         info->buf = buf;
 639         init_completion(&info->comp);
 640
 641         /*  configure and start prefetch transfer */
 642         ret = omap_prefetch_enable(info->gpmc_cs,
 643                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 644         if (ret)
 645                 /* PFPW engine is busy, use cpu copy method */
 646                 goto out_copy;
 647
 648         info->buf_len = len;
 649
 650         enable_irq(info->gpmc_irq_count);
 651         enable_irq(info->gpmc_irq_fifo);
 652
 653         /* waiting for read to complete */
 654         wait_for_completion(&info->comp);
 655
 656         /* disable and stop the PFPW engine */
 657         omap_prefetch_reset(info->gpmc_cs, info);
 658         return;
 659
 660 out_copy:
 661         if (info->nand.options & NAND_BUSWIDTH_16)
 662                 omap_read_buf16(mtd, buf, len);
 663         else
 664                 omap_read_buf8(mtd, buf, len);
 665 }
 666
 667 /*
 668  * omap_write_buf_irq_pref - write buffer to NAND controller
 669  * @mtd: MTD device structure
 670  * @buf: data buffer
 671  * @len: number of bytes to write
 672  */
 673 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 674                                         const u_char *buf, int len)
 675 {
 676         struct omap_nand_info *info = mtd_to_omap(mtd);
 677         int ret = 0;
 678         unsigned long tim, limit;
 679         u32 val;
 680
 681         if (len <= mtd->oobsize) {
 682                 omap_write_buf_pref(mtd, buf, len);
 683                 return;
 684         }
 685
 686         info->iomode = OMAP_NAND_IO_WRITE;
 687         info->buf = (u_char *) buf;
 688         init_completion(&info->comp);
 689
 690         /* configure and start prefetch transfer : size=24 */
 691         ret = omap_prefetch_enable(info->gpmc_cs,
 692                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 693         if (ret)
 694                 /* PFPW engine is busy, use cpu copy method */
 695                 goto out_copy;
 696
 697         info->buf_len = len;
 698
 699         enable_irq(info->gpmc_irq_count);
 700         enable_irq(info->gpmc_irq_fifo);
 701
 702         /* waiting for write to complete */
 703         wait_for_completion(&info->comp);
 704
 705         /* wait for data to flushed-out before reset the prefetch */
 706         tim = 0;
 707         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 708         do {
 709                 val = readl(info->reg.gpmc_prefetch_status);
 710                 val = PREFETCH_STATUS_COUNT(val);
 711                 cpu_relax();
 712         } while (val && (tim++ < limit));
 713
 714         /* disable and stop the PFPW engine */
 715         omap_prefetch_reset(info->gpmc_cs, info);
 716         return;
 717
 718 out_copy:
 719         if (info->nand.options & NAND_BUSWIDTH_16)
 720                 omap_write_buf16(mtd, buf, len);
 721         else
 722                 omap_write_buf8(mtd, buf, len);
 723 }
 724
 725 /**
 726  * gen_true_ecc - This function will generate true ECC value
 727  * @ecc_buf: buffer to store ecc code
 728  *
 729  * This generated true ECC value can be used when correcting
 730  * data read from NAND flash memory core
 731  */
 732 static void gen_true_ecc(u8 *ecc_buf)
 733 {
 734         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 735                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 736
 737         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 738                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 739         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 740                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 741         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 742                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 743 }
 744
 745 /**
 746  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 747  * @ecc_data1:  ecc code from nand spare area
 748  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 749  * @page_data:  page data
 750  *
 751  * This function compares two ECC's and indicates if there is an error.
 752  * If the error can be corrected it will be corrected to the buffer.
 753  * If there is no error, %0 is returned. If there is an error but it
 754  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 755  */
 756 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 757                             u8 *ecc_data2,      /* read from register */
 758                             u8 *page_data)
 759 {
 760         uint    i;
 761         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 762         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 763         u8      ecc_bit[24];
 764         u8      ecc_sum = 0;
 765         u8      find_bit = 0;
 766         uint    find_byte = 0;
 767         int     isEccFF;
 768
 769         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 770
 771         gen_true_ecc(ecc_data1);
 772         gen_true_ecc(ecc_data2);
 773
 774         for (i = 0; i <= 2; i++) {
 775                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 776                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 777         }
 778
 779         for (i = 0; i < 8; i++) {
 780                 tmp0_bit[i]     = *ecc_data1 % 2;
 781                 *ecc_data1      = *ecc_data1 / 2;
 782         }
 783
 784         for (i = 0; i < 8; i++) {
 785                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 786                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 787         }
 788
 789         for (i = 0; i < 8; i++) {
 790                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 791                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 792         }
 793
 794         for (i = 0; i < 8; i++) {
 795                 comp0_bit[i]     = *ecc_data2 % 2;
 796                 *ecc_data2       = *ecc_data2 / 2;
 797         }
 798
 799         for (i = 0; i < 8; i++) {
 800                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 801                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 802         }
 803
 804         for (i = 0; i < 8; i++) {
 805                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 806                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 807         }
 808
 809         for (i = 0; i < 6; i++)
 810                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 811
 812         for (i = 0; i < 8; i++)
 813                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 814
 815         for (i = 0; i < 8; i++)
 816                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 817
 818         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 819         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 820
 821         for (i = 0; i < 24; i++)
 822                 ecc_sum += ecc_bit[i];
 823
 824         switch (ecc_sum) {
 825         case 0:
 826                 /* Not reached because this function is not called if
 827                  *  ECC values are equal
 828                  */
 829                 return 0;
 830
 831         case 1:
 832                 /* Uncorrectable error */
 833                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 834                 return -EBADMSG;
 835
 836         case 11:
 837                 /* UN-Correctable error */
 838                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 839                 return -EBADMSG;
 840
 841         case 12:
 842                 /* Correctable error */
 843                 find_byte = (ecc_bit[23] << 8) +
 844                             (ecc_bit[21] << 7) +
 845                             (ecc_bit[19] << 6) +
 846                             (ecc_bit[17] << 5) +
 847                             (ecc_bit[15] << 4) +
 848                             (ecc_bit[13] << 3) +
 849                             (ecc_bit[11] << 2) +
 850                             (ecc_bit[9]  << 1) +
 851                             ecc_bit[7];
 852
 853                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 854
 855                 pr_debug("Correcting single bit ECC error at offset: "
 856                                 "%d, bit: %d\n", find_byte, find_bit);
 857
 858                 page_data[find_byte] ^= (1 << find_bit);
 859
 860                 return 1;
 861         default:
 862                 if (isEccFF) {
 863                         if (ecc_data2[0] == 0 &&
 864                             ecc_data2[1] == 0 &&
 865                             ecc_data2[2] == 0)
 866                                 return 0;
 867                 }
 868                 pr_debug("UNCORRECTED_ERROR default\n");
 869                 return -EBADMSG;
 870         }
 871 }
 872
 873 /**
 874  * omap_correct_data - Compares the ECC read with HW generated ECC
 875  * @mtd: MTD device structure
 876  * @dat: page data
 877  * @read_ecc: ecc read from nand flash
 878  * @calc_ecc: ecc read from HW ECC registers
 879  *
 880  * Compares the ecc read from nand spare area with ECC registers values
 881  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 882  * detection and correction. If there are no errors, %0 is returned. If
 883  * there were errors and all of the errors were corrected, the number of
 884  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 885  * returned.
 886  */
 887 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 888                                 u_char *read_ecc, u_char *calc_ecc)
 889 {
 890         struct omap_nand_info *info = mtd_to_omap(mtd);
 891         int blockCnt = 0, i = 0, ret = 0;
 892         int stat = 0;
 893
 894         /* Ex NAND_ECC_HW12_2048 */
 895         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 896                         (info->nand.ecc.size  == 2048))
 897                 blockCnt = 4;
 898         else
 899                 blockCnt = 1;
 900
 901         for (i = 0; i < blockCnt; i++) {
 902                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 903                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 904                         if (ret < 0)
 905                                 return ret;
 906                         /* keep track of the number of corrected errors */
 907                         stat += ret;
 908                 }
 909                 read_ecc += 3;
 910                 calc_ecc += 3;
 911                 dat      += 512;
 912         }
 913         return stat;
 914 }
 915
 916 /**
 917  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 918  * @mtd: MTD device structure
 919  * @dat: The pointer to data on which ecc is computed
 920  * @ecc_code: The ecc_code buffer
 921  *
 922  * Using noninverted ECC can be considered ugly since writing a blank
 923  * page ie. padding will clear the ECC bytes. This is no problem as long
 924  * nobody is trying to write data on the seemingly unused page. Reading
 925  * an erased page will produce an ECC mismatch between generated and read
 926  * ECC bytes that has to be dealt with separately.
 927  */
 928 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 929                                 u_char *ecc_code)
 930 {
 931         struct omap_nand_info *info = mtd_to_omap(mtd);
 932         u32 val;
 933
 934         val = readl(info->reg.gpmc_ecc_config);
 935         if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
 936                 return -EINVAL;
 937
 938         /* read ecc result */
 939         val = readl(info->reg.gpmc_ecc1_result);
 940         *ecc_code++ = val;          /* P128e, ..., P1e */
 941         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 942         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 943         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 944
 945         return 0;
 946 }
 947
 948 /**
 949  * omap_enable_hwecc - This function enables the hardware ecc functionality
 950  * @mtd: MTD device structure
 951  * @mode: Read/Write mode
 952  */
 953 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 954 {
 955         struct omap_nand_info *info = mtd_to_omap(mtd);
 956         struct nand_chip *chip = mtd_to_nand(mtd);
 957         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 958         u32 val;
 959
 960         /* clear ecc and enable bits */
 961         val = ECCCLEAR | ECC1;
 962         writel(val, info->reg.gpmc_ecc_control);
 963
 964         /* program ecc and result sizes */
 965         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 966                          ECC1RESULTSIZE);
 967         writel(val, info->reg.gpmc_ecc_size_config);
 968
 969         switch (mode) {
 970         case NAND_ECC_READ:
 971         case NAND_ECC_WRITE:
 972                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 973                 break;
 974         case NAND_ECC_READSYN:
 975                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 976                 break;
 977         default:
 978                 dev_info(&info->pdev->dev,
 979                         "error: unrecognized Mode[%d]!\n", mode);
 980                 break;
 981         }
 982
 983         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 984         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 985         writel(val, info->reg.gpmc_ecc_config);
 986 }
 987
 988 /**
 989  * omap_wait - wait until the command is done
 990  * @mtd: MTD device structure
 991  * @chip: NAND Chip structure
 992  *
 993  * Wait function is called during Program and erase operations and
 994  * the way it is called from MTD layer, we should wait till the NAND
 995  * chip is ready after the programming/erase operation has completed.
 996  *
 997  * Erase can take up to 400ms and program up to 20ms according to
 998  * general NAND and SmartMedia specs
 999  */
1000 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1001 {
1002         struct nand_chip *this = mtd_to_nand(mtd);
1003         struct omap_nand_info *info = mtd_to_omap(mtd);
1004         unsigned long timeo = jiffies;
1005         int status, state = this->state;
1006
1007         if (state == FL_ERASING)
1008                 timeo += msecs_to_jiffies(400);
1009         else
1010                 timeo += msecs_to_jiffies(20);
1011
1012         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1013         while (time_before(jiffies, timeo)) {
1014                 status = readb(info->reg.gpmc_nand_data);
1015                 if (status & NAND_STATUS_READY)
1016                         break;
1017                 cond_resched();
1018         }
1019
1020         status = readb(info->reg.gpmc_nand_data);
1021         return status;
1022 }
1023
1024 /**
1025  * omap_dev_ready - calls the platform specific dev_ready function
1026  * @mtd: MTD device structure
1027  */
1028 static int omap_dev_ready(struct mtd_info *mtd)
1029 {
1030         unsigned int val = 0;
1031         struct omap_nand_info *info = mtd_to_omap(mtd);
1032
1033         val = readl(info->reg.gpmc_status);
1034
1035         if ((val & 0x100) == 0x100) {
1036                 return 1;
1037         } else {
1038                 return 0;
1039         }
1040 }
1041
1042 /**
1043  * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1044  * @mtd: MTD device structure
1045  * @mode: Read/Write mode
1046  *
1047  * When using BCH with SW correction (i.e. no ELM), sector size is set
1048  * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1049  * for both reading and writing with:
1050  * eccsize0 = 0  (no additional protected byte in spare area)
1051  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1052  */
1053 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1054 {
1055         unsigned int bch_type;
1056         unsigned int dev_width, nsectors;
1057         struct omap_nand_info *info = mtd_to_omap(mtd);
1058         enum omap_ecc ecc_opt = info->ecc_opt;
1059         struct nand_chip *chip = mtd_to_nand(mtd);
1060         u32 val, wr_mode;
1061         unsigned int ecc_size1, ecc_size0;
1062
1063         /* GPMC configurations for calculating ECC */
1064         switch (ecc_opt) {
1065         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1066                 bch_type = 0;
1067                 nsectors = 1;
1068                 wr_mode   = BCH_WRAPMODE_6;
1069                 ecc_size0 = BCH_ECC_SIZE0;
1070                 ecc_size1 = BCH_ECC_SIZE1;
1071                 break;
1072         case OMAP_ECC_BCH4_CODE_HW:
1073                 bch_type = 0;
1074                 nsectors = chip->ecc.steps;
1075                 if (mode == NAND_ECC_READ) {
1076                         wr_mode   = BCH_WRAPMODE_1;
1077                         ecc_size0 = BCH4R_ECC_SIZE0;
1078                         ecc_size1 = BCH4R_ECC_SIZE1;
1079                 } else {
1080                         wr_mode   = BCH_WRAPMODE_6;
1081                         ecc_size0 = BCH_ECC_SIZE0;
1082                         ecc_size1 = BCH_ECC_SIZE1;
1083                 }
1084                 break;
1085         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1086                 bch_type = 1;
1087                 nsectors = 1;
1088                 wr_mode   = BCH_WRAPMODE_6;
1089                 ecc_size0 = BCH_ECC_SIZE0;
1090                 ecc_size1 = BCH_ECC_SIZE1;
1091                 break;
1092         case OMAP_ECC_BCH8_CODE_HW:
1093                 bch_type = 1;
1094                 nsectors = chip->ecc.steps;
1095                 if (mode == NAND_ECC_READ) {
1096                         wr_mode   = BCH_WRAPMODE_1;
1097                         ecc_size0 = BCH8R_ECC_SIZE0;
1098                         ecc_size1 = BCH8R_ECC_SIZE1;
1099                 } else {
1100                         wr_mode   = BCH_WRAPMODE_6;
1101                         ecc_size0 = BCH_ECC_SIZE0;
1102                         ecc_size1 = BCH_ECC_SIZE1;
1103                 }
1104                 break;
1105         case OMAP_ECC_BCH16_CODE_HW:
1106                 bch_type = 0x2;
1107                 nsectors = chip->ecc.steps;
1108                 if (mode == NAND_ECC_READ) {
1109                         wr_mode   = 0x01;
1110                         ecc_size0 = 52; /* ECC bits in nibbles per sector */
1111                         ecc_size1 = 0;  /* non-ECC bits in nibbles per sector */
1112                 } else {
1113                         wr_mode   = 0x01;
1114                         ecc_size0 = 0;  /* extra bits in nibbles per sector */
1115                         ecc_size1 = 52; /* OOB bits in nibbles per sector */
1116                 }
1117                 break;
1118         default:
1119                 return;
1120         }
1121
1122         writel(ECC1, info->reg.gpmc_ecc_control);
1123
1124         /* Configure ecc size for BCH */
1125         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1126         writel(val, info->reg.gpmc_ecc_size_config);
1127
1128         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1129
1130         /* BCH configuration */
1131         val = ((1                        << 16) | /* enable BCH */
1132                (bch_type                 << 12) | /* BCH4/BCH8/BCH16 */
1133                (wr_mode                  <<  8) | /* wrap mode */
1134                (dev_width                <<  7) | /* bus width */
1135                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1136                (info->gpmc_cs            <<  1) | /* ECC CS */
1137                (0x1));                            /* enable ECC */
1138
1139         writel(val, info->reg.gpmc_ecc_config);
1140
1141         /* Clear ecc and enable bits */
1142         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1143 }
1144
1145 static u8  bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1146 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1147                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
1148
1149 /**
1150  * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1151  * @mtd:        MTD device structure
1152  * @dat:        The pointer to data on which ecc is computed
1153  * @ecc_code:   The ecc_code buffer
1154  *
1155  * Support calculating of BCH4/8 ecc vectors for the page
1156  */
1157 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1158                                         const u_char *dat, u_char *ecc_calc)
1159 {
1160         struct omap_nand_info *info = mtd_to_omap(mtd);
1161         int eccbytes    = info->nand.ecc.bytes;
1162         struct gpmc_nand_regs   *gpmc_regs = &info->reg;
1163         u8 *ecc_code;
1164         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1165         u32 val;
1166         int i, j;
1167
1168         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1169         for (i = 0; i < nsectors; i++) {
1170                 ecc_code = ecc_calc;
1171                 switch (info->ecc_opt) {
1172                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1173                 case OMAP_ECC_BCH8_CODE_HW:
1174                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1175                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1176                         bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1177                         bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1178                         *ecc_code++ = (bch_val4 & 0xFF);
1179                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1180                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1181                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1182                         *ecc_code++ = (bch_val3 & 0xFF);
1183                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1184                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1185                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1186                         *ecc_code++ = (bch_val2 & 0xFF);
1187                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1188                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1189                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1190                         *ecc_code++ = (bch_val1 & 0xFF);
1191                         break;
1192                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1193                 case OMAP_ECC_BCH4_CODE_HW:
1194                         bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1195                         bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1196                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1197                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1198                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1199                                 ((bch_val1 >> 28) & 0xF);
1200                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1201                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1202                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1203                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1204                         break;
1205                 case OMAP_ECC_BCH16_CODE_HW:
1206                         val = readl(gpmc_regs->gpmc_bch_result6[i]);
1207                         ecc_code[0]  = ((val >>  8) & 0xFF);
1208                         ecc_code[1]  = ((val >>  0) & 0xFF);
1209                         val = readl(gpmc_regs->gpmc_bch_result5[i]);
1210                         ecc_code[2]  = ((val >> 24) & 0xFF);
1211                         ecc_code[3]  = ((val >> 16) & 0xFF);
1212                         ecc_code[4]  = ((val >>  8) & 0xFF);
1213                         ecc_code[5]  = ((val >>  0) & 0xFF);
1214                         val = readl(gpmc_regs->gpmc_bch_result4[i]);
1215                         ecc_code[6]  = ((val >> 24) & 0xFF);
1216                         ecc_code[7]  = ((val >> 16) & 0xFF);
1217                         ecc_code[8]  = ((val >>  8) & 0xFF);
1218                         ecc_code[9]  = ((val >>  0) & 0xFF);
1219                         val = readl(gpmc_regs->gpmc_bch_result3[i]);
1220                         ecc_code[10] = ((val >> 24) & 0xFF);
1221                         ecc_code[11] = ((val >> 16) & 0xFF);
1222                         ecc_code[12] = ((val >>  8) & 0xFF);
1223                         ecc_code[13] = ((val >>  0) & 0xFF);
1224                         val = readl(gpmc_regs->gpmc_bch_result2[i]);
1225                         ecc_code[14] = ((val >> 24) & 0xFF);
1226                         ecc_code[15] = ((val >> 16) & 0xFF);
1227                         ecc_code[16] = ((val >>  8) & 0xFF);
1228                         ecc_code[17] = ((val >>  0) & 0xFF);
1229                         val = readl(gpmc_regs->gpmc_bch_result1[i]);
1230                         ecc_code[18] = ((val >> 24) & 0xFF);
1231                         ecc_code[19] = ((val >> 16) & 0xFF);
1232                         ecc_code[20] = ((val >>  8) & 0xFF);
1233                         ecc_code[21] = ((val >>  0) & 0xFF);
1234                         val = readl(gpmc_regs->gpmc_bch_result0[i]);
1235                         ecc_code[22] = ((val >> 24) & 0xFF);
1236                         ecc_code[23] = ((val >> 16) & 0xFF);
1237                         ecc_code[24] = ((val >>  8) & 0xFF);
1238                         ecc_code[25] = ((val >>  0) & 0xFF);
1239                         break;
1240                 default:
1241                         return -EINVAL;
1242                 }
1243
1244                 /* ECC scheme specific syndrome customizations */
1245                 switch (info->ecc_opt) {
1246                 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1247                         /* Add constant polynomial to remainder, so that
1248                          * ECC of blank pages results in 0x0 on reading back */
1249                         for (j = 0; j < eccbytes; j++)
1250                                 ecc_calc[j] ^= bch4_polynomial[j];
1251                         break;
1252                 case OMAP_ECC_BCH4_CODE_HW:
1253                         /* Set  8th ECC byte as 0x0 for ROM compatibility */
1254                         ecc_calc[eccbytes - 1] = 0x0;
1255                         break;
1256                 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1257                         /* Add constant polynomial to remainder, so that
1258                          * ECC of blank pages results in 0x0 on reading back */
1259                         for (j = 0; j < eccbytes; j++)
1260                                 ecc_calc[j] ^= bch8_polynomial[j];
1261                         break;
1262                 case OMAP_ECC_BCH8_CODE_HW:
1263                         /* Set 14th ECC byte as 0x0 for ROM compatibility */
1264                         ecc_calc[eccbytes - 1] = 0x0;
1265                         break;
1266                 case OMAP_ECC_BCH16_CODE_HW:
1267                         break;
1268                 default:
1269                         return -EINVAL;
1270                 }
1271
1272         ecc_calc += eccbytes;
1273         }
1274
1275         return 0;
1276 }
1277
1278 /**
1279  * erased_sector_bitflips - count bit flips
1280  * @data:       data sector buffer
1281  * @oob:        oob buffer
1282  * @info:       omap_nand_info
1283  *
1284  * Check the bit flips in erased page falls below correctable level.
1285  * If falls below, report the page as erased with correctable bit
1286  * flip, else report as uncorrectable page.
1287  */
1288 static int erased_sector_bitflips(u_char *data, u_char *oob,
1289                 struct omap_nand_info *info)
1290 {
1291         int flip_bits = 0, i;
1292
1293         for (i = 0; i < info->nand.ecc.size; i++) {
1294                 flip_bits += hweight8(~data[i]);
1295                 if (flip_bits > info->nand.ecc.strength)
1296                         return 0;
1297         }
1298
1299         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1300                 flip_bits += hweight8(~oob[i]);
1301                 if (flip_bits > info->nand.ecc.strength)
1302                         return 0;
1303         }
1304
1305         /*
1306          * Bit flips falls in correctable level.
1307          * Fill data area with 0xFF
1308          */
1309         if (flip_bits) {
1310                 memset(data, 0xFF, info->nand.ecc.size);
1311                 memset(oob, 0xFF, info->nand.ecc.bytes);
1312         }
1313
1314         return flip_bits;
1315 }
1316
1317 /**
1318  * omap_elm_correct_data - corrects page data area in case error reported
1319  * @mtd:        MTD device structure
1320  * @data:       page data
1321  * @read_ecc:   ecc read from nand flash
1322  * @calc_ecc:   ecc read from HW ECC registers
1323  *
1324  * Calculated ecc vector reported as zero in case of non-error pages.
1325  * In case of non-zero ecc vector, first filter out erased-pages, and
1326  * then process data via ELM to detect bit-flips.
1327  */
1328 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1329                                 u_char *read_ecc, u_char *calc_ecc)
1330 {
1331         struct omap_nand_info *info = mtd_to_omap(mtd);
1332         struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1333         int eccsteps = info->nand.ecc.steps;
1334         int i , j, stat = 0;
1335         int eccflag, actual_eccbytes;
1336         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1337         u_char *ecc_vec = calc_ecc;
1338         u_char *spare_ecc = read_ecc;
1339         u_char *erased_ecc_vec;
1340         u_char *buf;
1341         int bitflip_count;
1342         bool is_error_reported = false;
1343         u32 bit_pos, byte_pos, error_max, pos;
1344         int err;
1345
1346         switch (info->ecc_opt) {
1347         case OMAP_ECC_BCH4_CODE_HW:
1348                 /* omit  7th ECC byte reserved for ROM code compatibility */
1349                 actual_eccbytes = ecc->bytes - 1;
1350                 erased_ecc_vec = bch4_vector;
1351                 break;
1352         case OMAP_ECC_BCH8_CODE_HW:
1353                 /* omit 14th ECC byte reserved for ROM code compatibility */
1354                 actual_eccbytes = ecc->bytes - 1;
1355                 erased_ecc_vec = bch8_vector;
1356                 break;
1357         case OMAP_ECC_BCH16_CODE_HW:
1358                 actual_eccbytes = ecc->bytes;
1359                 erased_ecc_vec = bch16_vector;
1360                 break;
1361         default:
1362                 dev_err(&info->pdev->dev, "invalid driver configuration\n");
1363                 return -EINVAL;
1364         }
1365
1366         /* Initialize elm error vector to zero */
1367         memset(err_vec, 0, sizeof(err_vec));
1368
1369         for (i = 0; i < eccsteps ; i++) {
1370                 eccflag = 0;    /* initialize eccflag */
1371
1372                 /*
1373                  * Check any error reported,
1374                  * In case of error, non zero ecc reported.
1375                  */
1376                 for (j = 0; j < actual_eccbytes; j++) {
1377                         if (calc_ecc[j] != 0) {
1378                                 eccflag = 1; /* non zero ecc, error present */
1379                                 break;
1380                         }
1381                 }
1382
1383                 if (eccflag == 1) {
1384                         if (memcmp(calc_ecc, erased_ecc_vec,
1385                                                 actual_eccbytes) == 0) {
1386                                 /*
1387                                  * calc_ecc[] matches pattern for ECC(all 0xff)
1388                                  * so this is definitely an erased-page
1389                                  */
1390                         } else {
1391                                 buf = &data[info->nand.ecc.size * i];
1392                                 /*
1393                                  * count number of 0-bits in read_buf.
1394                                  * This check can be removed once a similar
1395                                  * check is introduced in generic NAND driver
1396                                  */
1397                                 bitflip_count = erased_sector_bitflips(
1398                                                 buf, read_ecc, info);
1399                                 if (bitflip_count) {
1400                                         /*
1401                                          * number of 0-bits within ECC limits
1402                                          * So this may be an erased-page
1403                                          */
1404                                         stat += bitflip_count;
1405                                 } else {
1406                                         /*
1407                                          * Too many 0-bits. It may be a
1408                                          * - programmed-page, OR
1409                                          * - erased-page with many bit-flips
1410                                          * So this page requires check by ELM
1411                                          */
1412                                         err_vec[i].error_reported = true;
1413                                         is_error_reported = true;
1414                                 }
1415                         }
1416                 }
1417
1418                 /* Update the ecc vector */
1419                 calc_ecc += ecc->bytes;
1420                 read_ecc += ecc->bytes;
1421         }
1422
1423         /* Check if any error reported */
1424         if (!is_error_reported)
1425                 return stat;
1426
1427         /* Decode BCH error using ELM module */
1428         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1429
1430         err = 0;
1431         for (i = 0; i < eccsteps; i++) {
1432                 if (err_vec[i].error_uncorrectable) {
1433                         dev_err(&info->pdev->dev,
1434                                 "uncorrectable bit-flips found\n");
1435                         err = -EBADMSG;
1436                 } else if (err_vec[i].error_reported) {
1437                         for (j = 0; j < err_vec[i].error_count; j++) {
1438                                 switch (info->ecc_opt) {
1439                                 case OMAP_ECC_BCH4_CODE_HW:
1440                                         /* Add 4 bits to take care of padding */
1441                                         pos = err_vec[i].error_loc[j] +
1442                                                 BCH4_BIT_PAD;
1443                                         break;
1444                                 case OMAP_ECC_BCH8_CODE_HW:
1445                                 case OMAP_ECC_BCH16_CODE_HW:
1446                                         pos = err_vec[i].error_loc[j];
1447                                         break;
1448                                 default:
1449                                         return -EINVAL;
1450                                 }
1451                                 error_max = (ecc->size + actual_eccbytes) * 8;
1452                                 /* Calculate bit position of error */
1453                                 bit_pos = pos % 8;
1454
1455                                 /* Calculate byte position of error */
1456                                 byte_pos = (error_max - pos - 1) / 8;
1457
1458                                 if (pos < error_max) {
1459                                         if (byte_pos < 512) {
1460                                                 pr_debug("bitflip@dat[%d]=%x\n",
1461                                                      byte_pos, data[byte_pos]);
1462                                                 data[byte_pos] ^= 1 << bit_pos;
1463                                         } else {
1464                                                 pr_debug("bitflip@oob[%d]=%x\n",
1465                                                         (byte_pos - 512),
1466                                                      spare_ecc[byte_pos - 512]);
1467                                                 spare_ecc[byte_pos - 512] ^=
1468                                                         1 << bit_pos;
1469                                         }
1470                                 } else {
1471                                         dev_err(&info->pdev->dev,
1472                                                 "invalid bit-flip @ %d:%d\n",
1473                                                 byte_pos, bit_pos);
1474                                         err = -EBADMSG;
1475                                 }
1476                         }
1477                 }
1478
1479                 /* Update number of correctable errors */
1480                 stat += err_vec[i].error_count;
1481
1482                 /* Update page data with sector size */
1483                 data += ecc->size;
1484                 spare_ecc += ecc->bytes;
1485         }
1486
1487         return (err) ? err : stat;
1488 }
1489
1490 /**
1491  * omap_write_page_bch - BCH ecc based write page function for entire page
1492  * @mtd:                mtd info structure
1493  * @chip:               nand chip info structure
1494  * @buf:                data buffer
1495  * @oob_required:       must write chip->oob_poi to OOB
1496  * @page:               page
1497  *
1498  * Custom write page method evolved to support multi sector writing in one shot
1499  */
1500 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1501                                const uint8_t *buf, int oob_required, int page)
1502 {
1503         int i;
1504         uint8_t *ecc_calc = chip->buffers->ecccalc;
1505         uint32_t *eccpos = chip->ecc.layout->eccpos;
1506
1507         /* Enable GPMC ecc engine */
1508         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1509
1510         /* Write data */
1511         chip->write_buf(mtd, buf, mtd->writesize);
1512
1513         /* Update ecc vector from GPMC result registers */
1514         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1515
1516         for (i = 0; i < chip->ecc.total; i++)
1517                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1518
1519         /* Write ecc vector to OOB area */
1520         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1521         return 0;
1522 }
1523
1524 /**
1525  * omap_read_page_bch - BCH ecc based page read function for entire page
1526  * @mtd:                mtd info structure
1527  * @chip:               nand chip info structure
1528  * @buf:                buffer to store read data
1529  * @oob_required:       caller requires OOB data read to chip->oob_poi
1530  * @page:               page number to read
1531  *
1532  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1533  * used for error correction.
1534  * Custom method evolved to support ELM error correction & multi sector
1535  * reading. On reading page data area is read along with OOB data with
1536  * ecc engine enabled. ecc vector updated after read of OOB data.
1537  * For non error pages ecc vector reported as zero.
1538  */
1539 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1540                                 uint8_t *buf, int oob_required, int page)
1541 {
1542         uint8_t *ecc_calc = chip->buffers->ecccalc;
1543         uint8_t *ecc_code = chip->buffers->ecccode;
1544         uint32_t *eccpos = chip->ecc.layout->eccpos;
1545         uint8_t *oob = &chip->oob_poi[eccpos[0]];
1546         uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1547         int stat;
1548         unsigned int max_bitflips = 0;
1549
1550         /* Enable GPMC ecc engine */
1551         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1552
1553         /* Read data */
1554         chip->read_buf(mtd, buf, mtd->writesize);
1555
1556         /* Read oob bytes */
1557         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1558         chip->read_buf(mtd, oob, chip->ecc.total);
1559
1560         /* Calculate ecc bytes */
1561         chip->ecc.calculate(mtd, buf, ecc_calc);
1562
1563         memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1564
1565         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1566
1567         if (stat < 0) {
1568                 mtd->ecc_stats.failed++;
1569         } else {
1570                 mtd->ecc_stats.corrected += stat;
1571                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1572         }
1573
1574         return max_bitflips;
1575 }
1576
1577 /**
1578  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1579  * @omap_nand_info: NAND device structure containing platform data
1580  */
1581 static bool is_elm_present(struct omap_nand_info *info,
1582                            struct device_node *elm_node)
1583 {
1584         struct platform_device *pdev;
1585
1586         /* check whether elm-id is passed via DT */
1587         if (!elm_node) {
1588                 dev_err(&info->pdev->dev, "ELM devicetree node not found\n");
1589                 return false;
1590         }
1591         pdev = of_find_device_by_node(elm_node);
1592         /* check whether ELM device is registered */
1593         if (!pdev) {
1594                 dev_err(&info->pdev->dev, "ELM device not found\n");
1595                 return false;
1596         }
1597         /* ELM module available, now configure it */
1598         info->elm_dev = &pdev->dev;
1599         return true;
1600 }
1601
1602 static bool omap2_nand_ecc_check(struct omap_nand_info *info,
1603                                  struct omap_nand_platform_data *pdata)
1604 {
1605         bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm;
1606
1607         switch (info->ecc_opt) {
1608         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1609         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1610                 ecc_needs_omap_bch = false;
1611                 ecc_needs_bch = true;
1612                 ecc_needs_elm = false;
1613                 break;
1614         case OMAP_ECC_BCH4_CODE_HW:
1615         case OMAP_ECC_BCH8_CODE_HW:
1616         case OMAP_ECC_BCH16_CODE_HW:
1617                 ecc_needs_omap_bch = true;
1618                 ecc_needs_bch = false;
1619                 ecc_needs_elm = true;
1620                 break;
1621         default:
1622                 ecc_needs_omap_bch = false;
1623                 ecc_needs_bch = false;
1624                 ecc_needs_elm = false;
1625                 break;
1626         }
1627
1628         if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) {
1629                 dev_err(&info->pdev->dev,
1630                         "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1631                 return false;
1632         }
1633         if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) {
1634                 dev_err(&info->pdev->dev,
1635                         "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1636                 return false;
1637         }
1638         if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) {
1639                 dev_err(&info->pdev->dev, "ELM not available\n");
1640                 return false;
1641         }
1642
1643         return true;
1644 }
1645
1646 static int omap_nand_probe(struct platform_device *pdev)
1647 {
1648         struct omap_nand_info           *info;
1649         struct omap_nand_platform_data  *pdata;
1650         struct mtd_info                 *mtd;
1651         struct nand_chip                *nand_chip;
1652         struct nand_ecclayout           *ecclayout;
1653         int                             err;
1654         int                             i;
1655         dma_cap_mask_t                  mask;
1656         unsigned                        sig;
1657         unsigned                        oob_index;
1658         struct resource                 *res;
1659
1660         pdata = dev_get_platdata(&pdev->dev);
1661         if (pdata == NULL) {
1662                 dev_err(&pdev->dev, "platform data missing\n");
1663                 return -ENODEV;
1664         }
1665
1666         info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1667                                 GFP_KERNEL);
1668         if (!info)
1669                 return -ENOMEM;
1670
1671         platform_set_drvdata(pdev, info);
1672
1673         info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
1674         if (!info->ops) {
1675                 dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
1676                 return -ENODEV;
1677         }
1678         info->pdev              = pdev;
1679         info->gpmc_cs           = pdata->cs;
1680         info->of_node           = pdata->of_node;
1681         info->ecc_opt           = pdata->ecc_opt;
1682         info->dev_ready = pdata->dev_ready;
1683         info->xfer_type = pdata->xfer_type;
1684         info->devsize = pdata->devsize;
1685         info->elm_of_node = pdata->elm_of_node;
1686
1687         nand_chip               = &info->nand;
1688         mtd                     = nand_to_mtd(nand_chip);
1689         mtd->dev.parent         = &pdev->dev;
1690         nand_chip->ecc.priv     = NULL;
1691         nand_set_flash_node(nand_chip, pdata->of_node);
1692
1693         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1694         nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1695         if (IS_ERR(nand_chip->IO_ADDR_R))
1696                 return PTR_ERR(nand_chip->IO_ADDR_R);
1697
1698         info->phys_base = res->start;
1699
1700         nand_chip->controller = &omap_gpmc_controller;
1701
1702         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1703         nand_chip->cmd_ctrl  = omap_hwcontrol;
1704
1705         /*
1706          * If RDY/BSY line is connected to OMAP then use the omap ready
1707          * function and the generic nand_wait function which reads the status
1708          * register after monitoring the RDY/BSY line. Otherwise use a standard
1709          * chip delay which is slightly more than tR (AC Timing) of the NAND
1710          * device and read status register until you get a failure or success
1711          */
1712         if (info->dev_ready) {
1713                 nand_chip->dev_ready = omap_dev_ready;
1714                 nand_chip->chip_delay = 0;
1715         } else {
1716                 nand_chip->waitfunc = omap_wait;
1717                 nand_chip->chip_delay = 50;
1718         }
1719
1720         if (pdata->flash_bbt)
1721                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1722         else
1723                 nand_chip->options |= NAND_SKIP_BBTSCAN;
1724
1725         /* scan NAND device connected to chip controller */
1726         nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
1727         if (nand_scan_ident(mtd, 1, NULL)) {
1728                 dev_err(&info->pdev->dev,
1729                         "scan failed, may be bus-width mismatch\n");
1730                 err = -ENXIO;
1731                 goto return_error;
1732         }
1733
1734         /* re-populate low-level callbacks based on xfer modes */
1735         switch (info->xfer_type) {
1736         case NAND_OMAP_PREFETCH_POLLED:
1737                 nand_chip->read_buf   = omap_read_buf_pref;
1738                 nand_chip->write_buf  = omap_write_buf_pref;
1739                 break;
1740
1741         case NAND_OMAP_POLLED:
1742                 /* Use nand_base defaults for {read,write}_buf */
1743                 break;
1744
1745         case NAND_OMAP_PREFETCH_DMA:
1746                 dma_cap_zero(mask);
1747                 dma_cap_set(DMA_SLAVE, mask);
1748                 sig = OMAP24XX_DMA_GPMC;
1749                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1750                 if (!info->dma) {
1751                         dev_err(&pdev->dev, "DMA engine request failed\n");
1752                         err = -ENXIO;
1753                         goto return_error;
1754                 } else {
1755                         struct dma_slave_config cfg;
1756
1757                         memset(&cfg, 0, sizeof(cfg));
1758                         cfg.src_addr = info->phys_base;
1759                         cfg.dst_addr = info->phys_base;
1760                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1761                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1762                         cfg.src_maxburst = 16;
1763                         cfg.dst_maxburst = 16;
1764                         err = dmaengine_slave_config(info->dma, &cfg);
1765                         if (err) {
1766                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1767                                         err);
1768                                 goto return_error;
1769                         }
1770                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1771                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1772                 }
1773                 break;
1774
1775         case NAND_OMAP_PREFETCH_IRQ:
1776                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1777                 if (info->gpmc_irq_fifo <= 0) {
1778                         dev_err(&pdev->dev, "error getting fifo irq\n");
1779                         err = -ENODEV;
1780                         goto return_error;
1781                 }
1782                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1783                                         omap_nand_irq, IRQF_SHARED,
1784                                         "gpmc-nand-fifo", info);
1785                 if (err) {
1786                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1787                                                 info->gpmc_irq_fifo, err);
1788                         info->gpmc_irq_fifo = 0;
1789                         goto return_error;
1790                 }
1791
1792                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1793                 if (info->gpmc_irq_count <= 0) {
1794                         dev_err(&pdev->dev, "error getting count irq\n");
1795                         err = -ENODEV;
1796                         goto return_error;
1797                 }
1798                 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1799                                         omap_nand_irq, IRQF_SHARED,
1800                                         "gpmc-nand-count", info);
1801                 if (err) {
1802                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1803                                                 info->gpmc_irq_count, err);
1804                         info->gpmc_irq_count = 0;
1805                         goto return_error;
1806                 }
1807
1808                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1809                 nand_chip->write_buf = omap_write_buf_irq_pref;
1810
1811                 break;
1812
1813         default:
1814                 dev_err(&pdev->dev,
1815                         "xfer_type(%d) not supported!\n", info->xfer_type);
1816                 err = -EINVAL;
1817                 goto return_error;
1818         }
1819
1820         if (!omap2_nand_ecc_check(info, pdata)) {
1821                 err = -EINVAL;
1822                 goto return_error;
1823         }
1824
1825         /*
1826          * Bail out earlier to let NAND_ECC_SOFT code create its own
1827          * ecclayout instead of using ours.
1828          */
1829         if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
1830                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1831                 goto scan_tail;
1832         }
1833
1834         /* populate MTD interface based on ECC scheme */
1835         ecclayout               = &info->oobinfo;
1836         nand_chip->ecc.layout   = ecclayout;
1837         switch (info->ecc_opt) {
1838         case OMAP_ECC_HAM1_CODE_HW:
1839                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1840                 nand_chip->ecc.mode             = NAND_ECC_HW;
1841                 nand_chip->ecc.bytes            = 3;
1842                 nand_chip->ecc.size             = 512;
1843                 nand_chip->ecc.strength         = 1;
1844                 nand_chip->ecc.calculate        = omap_calculate_ecc;
1845                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
1846                 nand_chip->ecc.correct          = omap_correct_data;
1847                 /* define ECC layout */
1848                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1849                                                         (mtd->writesize /
1850                                                         nand_chip->ecc.size);
1851                 if (nand_chip->options & NAND_BUSWIDTH_16)
1852                         oob_index               = BADBLOCK_MARKER_LENGTH;
1853                 else
1854                         oob_index               = 1;
1855                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1856                         ecclayout->eccpos[i]    = oob_index;
1857                 /* no reserved-marker in ecclayout for this ecc-scheme */
1858                 ecclayout->oobfree->offset      =
1859                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1860                 break;
1861
1862         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1863                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1864                 nand_chip->ecc.mode             = NAND_ECC_HW;
1865                 nand_chip->ecc.size             = 512;
1866                 nand_chip->ecc.bytes            = 7;
1867                 nand_chip->ecc.strength         = 4;
1868                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1869                 nand_chip->ecc.correct          = nand_bch_correct_data;
1870                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1871                 /* define ECC layout */
1872                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1873                                                         (mtd->writesize /
1874                                                         nand_chip->ecc.size);
1875                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1876                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1877                         ecclayout->eccpos[i] = oob_index;
1878                         if (((i + 1) % nand_chip->ecc.bytes) == 0)
1879                                 oob_index++;
1880                 }
1881                 /* include reserved-marker in ecclayout->oobfree calculation */
1882                 ecclayout->oobfree->offset      = 1 +
1883                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1884                 /* software bch library is used for locating errors */
1885                 nand_chip->ecc.priv             = nand_bch_init(mtd);
1886                 if (!nand_chip->ecc.priv) {
1887                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
1888                         err = -EINVAL;
1889                         goto return_error;
1890                 }
1891                 break;
1892
1893         case OMAP_ECC_BCH4_CODE_HW:
1894                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1895                 nand_chip->ecc.mode             = NAND_ECC_HW;
1896                 nand_chip->ecc.size             = 512;
1897                 /* 14th bit is kept reserved for ROM-code compatibility */
1898                 nand_chip->ecc.bytes            = 7 + 1;
1899                 nand_chip->ecc.strength         = 4;
1900                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1901                 nand_chip->ecc.correct          = omap_elm_correct_data;
1902                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1903                 nand_chip->ecc.read_page        = omap_read_page_bch;
1904                 nand_chip->ecc.write_page       = omap_write_page_bch;
1905                 /* define ECC layout */
1906                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1907                                                         (mtd->writesize /
1908                                                         nand_chip->ecc.size);
1909                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1910                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1911                         ecclayout->eccpos[i]    = oob_index;
1912                 /* reserved marker already included in ecclayout->eccbytes */
1913                 ecclayout->oobfree->offset      =
1914                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1915
1916                 err = elm_config(info->elm_dev, BCH4_ECC,
1917                                  mtd->writesize / nand_chip->ecc.size,
1918                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
1919                 if (err < 0)
1920                         goto return_error;
1921                 break;
1922
1923         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1924                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1925                 nand_chip->ecc.mode             = NAND_ECC_HW;
1926                 nand_chip->ecc.size             = 512;
1927                 nand_chip->ecc.bytes            = 13;
1928                 nand_chip->ecc.strength         = 8;
1929                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1930                 nand_chip->ecc.correct          = nand_bch_correct_data;
1931                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1932                 /* define ECC layout */
1933                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1934                                                         (mtd->writesize /
1935                                                         nand_chip->ecc.size);
1936                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1937                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1938                         ecclayout->eccpos[i] = oob_index;
1939                         if (((i + 1) % nand_chip->ecc.bytes) == 0)
1940                                 oob_index++;
1941                 }
1942                 /* include reserved-marker in ecclayout->oobfree calculation */
1943                 ecclayout->oobfree->offset      = 1 +
1944                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1945                 /* software bch library is used for locating errors */
1946                 nand_chip->ecc.priv             = nand_bch_init(mtd);
1947                 if (!nand_chip->ecc.priv) {
1948                         dev_err(&info->pdev->dev, "unable to use BCH library\n");
1949                         err = -EINVAL;
1950                         goto return_error;
1951                 }
1952                 break;
1953
1954         case OMAP_ECC_BCH8_CODE_HW:
1955                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1956                 nand_chip->ecc.mode             = NAND_ECC_HW;
1957                 nand_chip->ecc.size             = 512;
1958                 /* 14th bit is kept reserved for ROM-code compatibility */
1959                 nand_chip->ecc.bytes            = 13 + 1;
1960                 nand_chip->ecc.strength         = 8;
1961                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1962                 nand_chip->ecc.correct          = omap_elm_correct_data;
1963                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1964                 nand_chip->ecc.read_page        = omap_read_page_bch;
1965                 nand_chip->ecc.write_page       = omap_write_page_bch;
1966
1967                 err = elm_config(info->elm_dev, BCH8_ECC,
1968                                  mtd->writesize / nand_chip->ecc.size,
1969                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
1970                 if (err < 0)
1971                         goto return_error;
1972
1973                 /* define ECC layout */
1974                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1975                                                         (mtd->writesize /
1976                                                         nand_chip->ecc.size);
1977                 oob_index                       = BADBLOCK_MARKER_LENGTH;
1978                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1979                         ecclayout->eccpos[i]    = oob_index;
1980                 /* reserved marker already included in ecclayout->eccbytes */
1981                 ecclayout->oobfree->offset      =
1982                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1983                 break;
1984
1985         case OMAP_ECC_BCH16_CODE_HW:
1986                 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
1987                 nand_chip->ecc.mode             = NAND_ECC_HW;
1988                 nand_chip->ecc.size             = 512;
1989                 nand_chip->ecc.bytes            = 26;
1990                 nand_chip->ecc.strength         = 16;
1991                 nand_chip->ecc.hwctl            = omap_enable_hwecc_bch;
1992                 nand_chip->ecc.correct          = omap_elm_correct_data;
1993                 nand_chip->ecc.calculate        = omap_calculate_ecc_bch;
1994                 nand_chip->ecc.read_page        = omap_read_page_bch;
1995                 nand_chip->ecc.write_page       = omap_write_page_bch;
1996
1997                 err = elm_config(info->elm_dev, BCH16_ECC,
1998                                  mtd->writesize / nand_chip->ecc.size,
1999                                  nand_chip->ecc.size, nand_chip->ecc.bytes);
2000                 if (err < 0)
2001                         goto return_error;
2002
2003                 /* define ECC layout */
2004                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
2005                                                         (mtd->writesize /
2006                                                         nand_chip->ecc.size);
2007                 oob_index                       = BADBLOCK_MARKER_LENGTH;
2008                 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
2009                         ecclayout->eccpos[i]    = oob_index;
2010                 /* reserved marker already included in ecclayout->eccbytes */
2011                 ecclayout->oobfree->offset      =
2012                                 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2013                 break;
2014         default:
2015                 dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n");
2016                 err = -EINVAL;
2017                 goto return_error;
2018         }
2019
2020         /* all OOB bytes from oobfree->offset till end off OOB are free */
2021         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2022         /* check if NAND device's OOB is enough to store ECC signatures */
2023         if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2024                 dev_err(&info->pdev->dev,
2025                         "not enough OOB bytes required = %d, available=%d\n",
2026                         ecclayout->eccbytes, mtd->oobsize);
2027                 err = -EINVAL;
2028                 goto return_error;
2029         }
2030
2031 scan_tail:
2032         /* second phase scan */
2033         if (nand_scan_tail(mtd)) {
2034                 err = -ENXIO;
2035                 goto return_error;
2036         }
2037
2038         mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
2039
2040         platform_set_drvdata(pdev, mtd);
2041
2042         return 0;
2043
2044 return_error:
2045         if (info->dma)
2046                 dma_release_channel(info->dma);
2047         if (nand_chip->ecc.priv) {
2048                 nand_bch_free(nand_chip->ecc.priv);
2049                 nand_chip->ecc.priv = NULL;
2050         }
2051         return err;
2052 }
2053
2054 static int omap_nand_remove(struct platform_device *pdev)
2055 {
2056         struct mtd_info *mtd = platform_get_drvdata(pdev);
2057         struct nand_chip *nand_chip = mtd_to_nand(mtd);
2058         struct omap_nand_info *info = mtd_to_omap(mtd);
2059         if (nand_chip->ecc.priv) {
2060                 nand_bch_free(nand_chip->ecc.priv);
2061                 nand_chip->ecc.priv = NULL;
2062         }
2063         if (info->dma)
2064                 dma_release_channel(info->dma);
2065         nand_release(mtd);
2066         return 0;
2067 }
2068
2069 static struct platform_driver omap_nand_driver = {
2070         .probe          = omap_nand_probe,
2071         .remove         = omap_nand_remove,
2072         .driver         = {
2073                 .name   = DRIVER_NAME,
2074         },
2075 };
2076
2077 module_platform_driver(omap_nand_driver);
2078
2079 MODULE_ALIAS("platform:" DRIVER_NAME);
2080 MODULE_LICENSE("GPL");
2081 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");