drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  76                                              void __iomem *d, u32 value)
  77 {
  78         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  79 }
  80
  81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  82                                             void __iomem *d)
  83 {
  84         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  85 }
  86
  87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  88                                     void __iomem *d,
  89                                     dma_addr_t addr)
  90 {
  91         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  92
  93         /* Register writes to GISB bus can take couple hundred nanoseconds
  94          * and are done for each packet, save these expensive writes unless
  95          * the platform is explicitly configured for 64-bits/LPAE.
  96          */
  97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  98         if (priv->hw_params->flags & GENET_HAS_40BITS)
  99                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 100 #endif
 101 }
 102
 103 /* Combined address + length/status setter */
 104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 105                                void __iomem *d, dma_addr_t addr, u32 val)
 106 {
 107         dmadesc_set_length_status(priv, d, val);
 108         dmadesc_set_addr(priv, d, addr);
 109 }
 110
 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 112                                           void __iomem *d)
 113 {
 114         dma_addr_t addr;
 115
 116         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 117
 118         /* Register writes to GISB bus can take couple hundred nanoseconds
 119          * and are done for each packet, save these expensive writes unless
 120          * the platform is explicitly configured for 64-bits/LPAE.
 121          */
 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 123         if (priv->hw_params->flags & GENET_HAS_40BITS)
 124                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 125 #endif
 126         return addr;
 127 }
 128
 129 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 130
 131 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 132                                 NETIF_MSG_LINK)
 133
 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 135 {
 136         if (GENET_IS_V1(priv))
 137                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 138         else
 139                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 140 }
 141
 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 143 {
 144         if (GENET_IS_V1(priv))
 145                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 146         else
 147                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 148 }
 149
 150 /* These macros are defined to deal with register map change
 151  * between GENET1.1 and GENET2. Only those currently being used
 152  * by driver are defined.
 153  */
 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 155 {
 156         if (GENET_IS_V1(priv))
 157                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 158         else
 159                 return __raw_readl(priv->base +
 160                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 161 }
 162
 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 164 {
 165         if (GENET_IS_V1(priv))
 166                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 167         else
 168                 __raw_writel(val, priv->base +
 169                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 170 }
 171
 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 173 {
 174         if (GENET_IS_V1(priv))
 175                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 176         else
 177                 return __raw_readl(priv->base +
 178                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 179 }
 180
 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 182 {
 183         if (GENET_IS_V1(priv))
 184                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 185         else
 186                 __raw_writel(val, priv->base +
 187                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 188 }
 189
 190 /* RX/TX DMA register accessors */
 191 enum dma_reg {
 192         DMA_RING_CFG = 0,
 193         DMA_CTRL,
 194         DMA_STATUS,
 195         DMA_SCB_BURST_SIZE,
 196         DMA_ARB_CTRL,
 197         DMA_PRIORITY_0,
 198         DMA_PRIORITY_1,
 199         DMA_PRIORITY_2,
 200         DMA_INDEX2RING_0,
 201         DMA_INDEX2RING_1,
 202         DMA_INDEX2RING_2,
 203         DMA_INDEX2RING_3,
 204         DMA_INDEX2RING_4,
 205         DMA_INDEX2RING_5,
 206         DMA_INDEX2RING_6,
 207         DMA_INDEX2RING_7,
 208         DMA_RING0_TIMEOUT,
 209         DMA_RING1_TIMEOUT,
 210         DMA_RING2_TIMEOUT,
 211         DMA_RING3_TIMEOUT,
 212         DMA_RING4_TIMEOUT,
 213         DMA_RING5_TIMEOUT,
 214         DMA_RING6_TIMEOUT,
 215         DMA_RING7_TIMEOUT,
 216         DMA_RING8_TIMEOUT,
 217         DMA_RING9_TIMEOUT,
 218         DMA_RING10_TIMEOUT,
 219         DMA_RING11_TIMEOUT,
 220         DMA_RING12_TIMEOUT,
 221         DMA_RING13_TIMEOUT,
 222         DMA_RING14_TIMEOUT,
 223         DMA_RING15_TIMEOUT,
 224         DMA_RING16_TIMEOUT,
 225 };
 226
 227 static const u8 bcmgenet_dma_regs_v3plus[] = {
 228         [DMA_RING_CFG]          = 0x00,
 229         [DMA_CTRL]              = 0x04,
 230         [DMA_STATUS]            = 0x08,
 231         [DMA_SCB_BURST_SIZE]    = 0x0C,
 232         [DMA_ARB_CTRL]          = 0x2C,
 233         [DMA_PRIORITY_0]        = 0x30,
 234         [DMA_PRIORITY_1]        = 0x34,
 235         [DMA_PRIORITY_2]        = 0x38,
 236         [DMA_RING0_TIMEOUT]     = 0x2C,
 237         [DMA_RING1_TIMEOUT]     = 0x30,
 238         [DMA_RING2_TIMEOUT]     = 0x34,
 239         [DMA_RING3_TIMEOUT]     = 0x38,
 240         [DMA_RING4_TIMEOUT]     = 0x3c,
 241         [DMA_RING5_TIMEOUT]     = 0x40,
 242         [DMA_RING6_TIMEOUT]     = 0x44,
 243         [DMA_RING7_TIMEOUT]     = 0x48,
 244         [DMA_RING8_TIMEOUT]     = 0x4c,
 245         [DMA_RING9_TIMEOUT]     = 0x50,
 246         [DMA_RING10_TIMEOUT]    = 0x54,
 247         [DMA_RING11_TIMEOUT]    = 0x58,
 248         [DMA_RING12_TIMEOUT]    = 0x5c,
 249         [DMA_RING13_TIMEOUT]    = 0x60,
 250         [DMA_RING14_TIMEOUT]    = 0x64,
 251         [DMA_RING15_TIMEOUT]    = 0x68,
 252         [DMA_RING16_TIMEOUT]    = 0x6C,
 253         [DMA_INDEX2RING_0]      = 0x70,
 254         [DMA_INDEX2RING_1]      = 0x74,
 255         [DMA_INDEX2RING_2]      = 0x78,
 256         [DMA_INDEX2RING_3]      = 0x7C,
 257         [DMA_INDEX2RING_4]      = 0x80,
 258         [DMA_INDEX2RING_5]      = 0x84,
 259         [DMA_INDEX2RING_6]      = 0x88,
 260         [DMA_INDEX2RING_7]      = 0x8C,
 261 };
 262
 263 static const u8 bcmgenet_dma_regs_v2[] = {
 264         [DMA_RING_CFG]          = 0x00,
 265         [DMA_CTRL]              = 0x04,
 266         [DMA_STATUS]            = 0x08,
 267         [DMA_SCB_BURST_SIZE]    = 0x0C,
 268         [DMA_ARB_CTRL]          = 0x30,
 269         [DMA_PRIORITY_0]        = 0x34,
 270         [DMA_PRIORITY_1]        = 0x38,
 271         [DMA_PRIORITY_2]        = 0x3C,
 272         [DMA_RING0_TIMEOUT]     = 0x2C,
 273         [DMA_RING1_TIMEOUT]     = 0x30,
 274         [DMA_RING2_TIMEOUT]     = 0x34,
 275         [DMA_RING3_TIMEOUT]     = 0x38,
 276         [DMA_RING4_TIMEOUT]     = 0x3c,
 277         [DMA_RING5_TIMEOUT]     = 0x40,
 278         [DMA_RING6_TIMEOUT]     = 0x44,
 279         [DMA_RING7_TIMEOUT]     = 0x48,
 280         [DMA_RING8_TIMEOUT]     = 0x4c,
 281         [DMA_RING9_TIMEOUT]     = 0x50,
 282         [DMA_RING10_TIMEOUT]    = 0x54,
 283         [DMA_RING11_TIMEOUT]    = 0x58,
 284         [DMA_RING12_TIMEOUT]    = 0x5c,
 285         [DMA_RING13_TIMEOUT]    = 0x60,
 286         [DMA_RING14_TIMEOUT]    = 0x64,
 287         [DMA_RING15_TIMEOUT]    = 0x68,
 288         [DMA_RING16_TIMEOUT]    = 0x6C,
 289 };
 290
 291 static const u8 bcmgenet_dma_regs_v1[] = {
 292         [DMA_CTRL]              = 0x00,
 293         [DMA_STATUS]            = 0x04,
 294         [DMA_SCB_BURST_SIZE]    = 0x0C,
 295         [DMA_ARB_CTRL]          = 0x30,
 296         [DMA_PRIORITY_0]        = 0x34,
 297         [DMA_PRIORITY_1]        = 0x38,
 298         [DMA_PRIORITY_2]        = 0x3C,
 299         [DMA_RING0_TIMEOUT]     = 0x2C,
 300         [DMA_RING1_TIMEOUT]     = 0x30,
 301         [DMA_RING2_TIMEOUT]     = 0x34,
 302         [DMA_RING3_TIMEOUT]     = 0x38,
 303         [DMA_RING4_TIMEOUT]     = 0x3c,
 304         [DMA_RING5_TIMEOUT]     = 0x40,
 305         [DMA_RING6_TIMEOUT]     = 0x44,
 306         [DMA_RING7_TIMEOUT]     = 0x48,
 307         [DMA_RING8_TIMEOUT]     = 0x4c,
 308         [DMA_RING9_TIMEOUT]     = 0x50,
 309         [DMA_RING10_TIMEOUT]    = 0x54,
 310         [DMA_RING11_TIMEOUT]    = 0x58,
 311         [DMA_RING12_TIMEOUT]    = 0x5c,
 312         [DMA_RING13_TIMEOUT]    = 0x60,
 313         [DMA_RING14_TIMEOUT]    = 0x64,
 314         [DMA_RING15_TIMEOUT]    = 0x68,
 315         [DMA_RING16_TIMEOUT]    = 0x6C,
 316 };
 317
 318 /* Set at runtime once bcmgenet version is known */
 319 static const u8 *bcmgenet_dma_regs;
 320
 321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 322 {
 323         return netdev_priv(dev_get_drvdata(dev));
 324 }
 325
 326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 327                                       enum dma_reg r)
 328 {
 329         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 330                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 331 }
 332
 333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 334                                         u32 val, enum dma_reg r)
 335 {
 336         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 337                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 338 }
 339
 340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 341                                       enum dma_reg r)
 342 {
 343         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 344                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 345 }
 346
 347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 348                                         u32 val, enum dma_reg r)
 349 {
 350         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 351                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 352 }
 353
 354 /* RDMA/TDMA ring registers and accessors
 355  * we merge the common fields and just prefix with T/D the registers
 356  * having different meaning depending on the direction
 357  */
 358 enum dma_ring_reg {
 359         TDMA_READ_PTR = 0,
 360         RDMA_WRITE_PTR = TDMA_READ_PTR,
 361         TDMA_READ_PTR_HI,
 362         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 363         TDMA_CONS_INDEX,
 364         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 365         TDMA_PROD_INDEX,
 366         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 367         DMA_RING_BUF_SIZE,
 368         DMA_START_ADDR,
 369         DMA_START_ADDR_HI,
 370         DMA_END_ADDR,
 371         DMA_END_ADDR_HI,
 372         DMA_MBUF_DONE_THRESH,
 373         TDMA_FLOW_PERIOD,
 374         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 375         TDMA_WRITE_PTR,
 376         RDMA_READ_PTR = TDMA_WRITE_PTR,
 377         TDMA_WRITE_PTR_HI,
 378         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 379 };
 380
 381 /* GENET v4 supports 40-bits pointer addressing
 382  * for obvious reasons the LO and HI word parts
 383  * are contiguous, but this offsets the other
 384  * registers.
 385  */
 386 static const u8 genet_dma_ring_regs_v4[] = {
 387         [TDMA_READ_PTR]                 = 0x00,
 388         [TDMA_READ_PTR_HI]              = 0x04,
 389         [TDMA_CONS_INDEX]               = 0x08,
 390         [TDMA_PROD_INDEX]               = 0x0C,
 391         [DMA_RING_BUF_SIZE]             = 0x10,
 392         [DMA_START_ADDR]                = 0x14,
 393         [DMA_START_ADDR_HI]             = 0x18,
 394         [DMA_END_ADDR]                  = 0x1C,
 395         [DMA_END_ADDR_HI]               = 0x20,
 396         [DMA_MBUF_DONE_THRESH]          = 0x24,
 397         [TDMA_FLOW_PERIOD]              = 0x28,
 398         [TDMA_WRITE_PTR]                = 0x2C,
 399         [TDMA_WRITE_PTR_HI]             = 0x30,
 400 };
 401
 402 static const u8 genet_dma_ring_regs_v123[] = {
 403         [TDMA_READ_PTR]                 = 0x00,
 404         [TDMA_CONS_INDEX]               = 0x04,
 405         [TDMA_PROD_INDEX]               = 0x08,
 406         [DMA_RING_BUF_SIZE]             = 0x0C,
 407         [DMA_START_ADDR]                = 0x10,
 408         [DMA_END_ADDR]                  = 0x14,
 409         [DMA_MBUF_DONE_THRESH]          = 0x18,
 410         [TDMA_FLOW_PERIOD]              = 0x1C,
 411         [TDMA_WRITE_PTR]                = 0x20,
 412 };
 413
 414 /* Set at runtime once GENET version is known */
 415 static const u8 *genet_dma_ring_regs;
 416
 417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 418                                            unsigned int ring,
 419                                            enum dma_ring_reg r)
 420 {
 421         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 422                         (DMA_RING_SIZE * ring) +
 423                         genet_dma_ring_regs[r]);
 424 }
 425
 426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 427                                              unsigned int ring, u32 val,
 428                                              enum dma_ring_reg r)
 429 {
 430         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 431                         (DMA_RING_SIZE * ring) +
 432                         genet_dma_ring_regs[r]);
 433 }
 434
 435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 436                                            unsigned int ring,
 437                                            enum dma_ring_reg r)
 438 {
 439         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 440                         (DMA_RING_SIZE * ring) +
 441                         genet_dma_ring_regs[r]);
 442 }
 443
 444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 445                                              unsigned int ring, u32 val,
 446                                              enum dma_ring_reg r)
 447 {
 448         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 449                         (DMA_RING_SIZE * ring) +
 450                         genet_dma_ring_regs[r]);
 451 }
 452
 453 static int bcmgenet_get_settings(struct net_device *dev,
 454                                  struct ethtool_cmd *cmd)
 455 {
 456         struct bcmgenet_priv *priv = netdev_priv(dev);
 457
 458         if (!netif_running(dev))
 459                 return -EINVAL;
 460
 461         if (!priv->phydev)
 462                 return -ENODEV;
 463
 464         return phy_ethtool_gset(priv->phydev, cmd);
 465 }
 466
 467 static int bcmgenet_set_settings(struct net_device *dev,
 468                                  struct ethtool_cmd *cmd)
 469 {
 470         struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472         if (!netif_running(dev))
 473                 return -EINVAL;
 474
 475         if (!priv->phydev)
 476                 return -ENODEV;
 477
 478         return phy_ethtool_sset(priv->phydev, cmd);
 479 }
 480
 481 static int bcmgenet_set_rx_csum(struct net_device *dev,
 482                                 netdev_features_t wanted)
 483 {
 484         struct bcmgenet_priv *priv = netdev_priv(dev);
 485         u32 rbuf_chk_ctrl;
 486         bool rx_csum_en;
 487
 488         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 489
 490         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 491
 492         /* enable rx checksumming */
 493         if (rx_csum_en)
 494                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 495         else
 496                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 497         priv->desc_rxchk_en = rx_csum_en;
 498
 499         /* If UniMAC forwards CRC, we need to skip over it to get
 500          * a valid CHK bit to be set in the per-packet status word
 501         */
 502         if (rx_csum_en && priv->crc_fwd_en)
 503                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 504         else
 505                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 506
 507         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 508
 509         return 0;
 510 }
 511
 512 static int bcmgenet_set_tx_csum(struct net_device *dev,
 513                                 netdev_features_t wanted)
 514 {
 515         struct bcmgenet_priv *priv = netdev_priv(dev);
 516         bool desc_64b_en;
 517         u32 tbuf_ctrl, rbuf_ctrl;
 518
 519         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 520         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 521
 522         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 523
 524         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 525         if (desc_64b_en) {
 526                 tbuf_ctrl |= RBUF_64B_EN;
 527                 rbuf_ctrl |= RBUF_64B_EN;
 528         } else {
 529                 tbuf_ctrl &= ~RBUF_64B_EN;
 530                 rbuf_ctrl &= ~RBUF_64B_EN;
 531         }
 532         priv->desc_64b_en = desc_64b_en;
 533
 534         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 535         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 536
 537         return 0;
 538 }
 539
 540 static int bcmgenet_set_features(struct net_device *dev,
 541                                  netdev_features_t features)
 542 {
 543         netdev_features_t changed = features ^ dev->features;
 544         netdev_features_t wanted = dev->wanted_features;
 545         int ret = 0;
 546
 547         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 548                 ret = bcmgenet_set_tx_csum(dev, wanted);
 549         if (changed & (NETIF_F_RXCSUM))
 550                 ret = bcmgenet_set_rx_csum(dev, wanted);
 551
 552         return ret;
 553 }
 554
 555 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 556 {
 557         struct bcmgenet_priv *priv = netdev_priv(dev);
 558
 559         return priv->msg_enable;
 560 }
 561
 562 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 563 {
 564         struct bcmgenet_priv *priv = netdev_priv(dev);
 565
 566         priv->msg_enable = level;
 567 }
 568
 569 static int bcmgenet_get_coalesce(struct net_device *dev,
 570                                  struct ethtool_coalesce *ec)
 571 {
 572         struct bcmgenet_priv *priv = netdev_priv(dev);
 573
 574         ec->tx_max_coalesced_frames =
 575                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 576                                          DMA_MBUF_DONE_THRESH);
 577         ec->rx_max_coalesced_frames =
 578                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 579                                          DMA_MBUF_DONE_THRESH);
 580         ec->rx_coalesce_usecs =
 581                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 582
 583         return 0;
 584 }
 585
 586 static int bcmgenet_set_coalesce(struct net_device *dev,
 587                                  struct ethtool_coalesce *ec)
 588 {
 589         struct bcmgenet_priv *priv = netdev_priv(dev);
 590         unsigned int i;
 591         u32 reg;
 592
 593         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 594          * divided by 1024, which yields roughly 8.192us, our maximum value
 595          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 596          */
 597         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 598             ec->tx_max_coalesced_frames == 0 ||
 599             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 600             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 601                 return -EINVAL;
 602
 603         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 604                 return -EINVAL;
 605
 606         /* GENET TDMA hardware does not support a configurable timeout, but will
 607          * always generate an interrupt either after MBDONE packets have been
 608          * transmitted, or when the ring is emtpy.
 609          */
 610         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 611             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 612                 return -EOPNOTSUPP;
 613
 614         /* Program all TX queues with the same values, as there is no
 615          * ethtool knob to do coalescing on a per-queue basis
 616          */
 617         for (i = 0; i < priv->hw_params->tx_queues; i++)
 618                 bcmgenet_tdma_ring_writel(priv, i,
 619                                           ec->tx_max_coalesced_frames,
 620                                           DMA_MBUF_DONE_THRESH);
 621         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 622                                   ec->tx_max_coalesced_frames,
 623                                   DMA_MBUF_DONE_THRESH);
 624
 625         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 626                 bcmgenet_rdma_ring_writel(priv, i,
 627                                           ec->rx_max_coalesced_frames,
 628                                           DMA_MBUF_DONE_THRESH);
 629
 630                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 631                 reg &= ~DMA_TIMEOUT_MASK;
 632                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 633                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 634         }
 635
 636         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 637                                   ec->rx_max_coalesced_frames,
 638                                   DMA_MBUF_DONE_THRESH);
 639
 640         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 641         reg &= ~DMA_TIMEOUT_MASK;
 642         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 643         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 644
 645         return 0;
 646 }
 647
 648 /* standard ethtool support functions. */
 649 enum bcmgenet_stat_type {
 650         BCMGENET_STAT_NETDEV = -1,
 651         BCMGENET_STAT_MIB_RX,
 652         BCMGENET_STAT_MIB_TX,
 653         BCMGENET_STAT_RUNT,
 654         BCMGENET_STAT_MISC,
 655         BCMGENET_STAT_SOFT,
 656 };
 657
 658 struct bcmgenet_stats {
 659         char stat_string[ETH_GSTRING_LEN];
 660         int stat_sizeof;
 661         int stat_offset;
 662         enum bcmgenet_stat_type type;
 663         /* reg offset from UMAC base for misc counters */
 664         u16 reg_offset;
 665 };
 666
 667 #define STAT_NETDEV(m) { \
 668         .stat_string = __stringify(m), \
 669         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 670         .stat_offset = offsetof(struct net_device_stats, m), \
 671         .type = BCMGENET_STAT_NETDEV, \
 672 }
 673
 674 #define STAT_GENET_MIB(str, m, _type) { \
 675         .stat_string = str, \
 676         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 677         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 678         .type = _type, \
 679 }
 680
 681 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 682 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 683 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 684 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 685
 686 #define STAT_GENET_MISC(str, m, offset) { \
 687         .stat_string = str, \
 688         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 689         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 690         .type = BCMGENET_STAT_MISC, \
 691         .reg_offset = offset, \
 692 }
 693
 694
 695 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 696  * between the end of TX stats and the beginning of the RX RUNT
 697  */
 698 #define BCMGENET_STAT_OFFSET    0xc
 699
 700 /* Hardware counters must be kept in sync because the order/offset
 701  * is important here (order in structure declaration = order in hardware)
 702  */
 703 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 704         /* general stats */
 705         STAT_NETDEV(rx_packets),
 706         STAT_NETDEV(tx_packets),
 707         STAT_NETDEV(rx_bytes),
 708         STAT_NETDEV(tx_bytes),
 709         STAT_NETDEV(rx_errors),
 710         STAT_NETDEV(tx_errors),
 711         STAT_NETDEV(rx_dropped),
 712         STAT_NETDEV(tx_dropped),
 713         STAT_NETDEV(multicast),
 714         /* UniMAC RSV counters */
 715         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 716         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 717         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 718         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 719         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 720         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 721         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 722         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 723         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 724         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 725         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 726         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 727         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 728         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 729         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 730         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 731         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 732         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 733         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 734         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 735         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 736         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 737         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 738         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 739         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 740         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 741         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 742         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 743         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 744         /* UniMAC TSV counters */
 745         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 746         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 747         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 748         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 749         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 750         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 751         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 752         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 753         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 754         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 755         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 756         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 757         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 758         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 759         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 760         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 761         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 762         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 763         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 764         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 765         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 766         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 767         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 768         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 769         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 770         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 771         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 772         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 773         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 774         /* UniMAC RUNT counters */
 775         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 776         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 777         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 778         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 779         /* Misc UniMAC counters */
 780         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 781                         UMAC_RBUF_OVFL_CNT),
 782         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 783         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 784         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 785         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 786         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 787 };
 788
 789 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 790
 791 static void bcmgenet_get_drvinfo(struct net_device *dev,
 792                                  struct ethtool_drvinfo *info)
 793 {
 794         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 795         strlcpy(info->version, "v2.0", sizeof(info->version));
 796         info->n_stats = BCMGENET_STATS_LEN;
 797 }
 798
 799 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 800 {
 801         switch (string_set) {
 802         case ETH_SS_STATS:
 803                 return BCMGENET_STATS_LEN;
 804         default:
 805                 return -EOPNOTSUPP;
 806         }
 807 }
 808
 809 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 810                                  u8 *data)
 811 {
 812         int i;
 813
 814         switch (stringset) {
 815         case ETH_SS_STATS:
 816                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 817                         memcpy(data + i * ETH_GSTRING_LEN,
 818                                bcmgenet_gstrings_stats[i].stat_string,
 819                                ETH_GSTRING_LEN);
 820                 }
 821                 break;
 822         }
 823 }
 824
 825 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 826 {
 827         int i, j = 0;
 828
 829         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 830                 const struct bcmgenet_stats *s;
 831                 u8 offset = 0;
 832                 u32 val = 0;
 833                 char *p;
 834
 835                 s = &bcmgenet_gstrings_stats[i];
 836                 switch (s->type) {
 837                 case BCMGENET_STAT_NETDEV:
 838                 case BCMGENET_STAT_SOFT:
 839                         continue;
 840                 case BCMGENET_STAT_MIB_RX:
 841                 case BCMGENET_STAT_MIB_TX:
 842                 case BCMGENET_STAT_RUNT:
 843                         if (s->type != BCMGENET_STAT_MIB_RX)
 844                                 offset = BCMGENET_STAT_OFFSET;
 845                         val = bcmgenet_umac_readl(priv,
 846                                                   UMAC_MIB_START + j + offset);
 847                         break;
 848                 case BCMGENET_STAT_MISC:
 849                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 850                         /* clear if overflowed */
 851                         if (val == ~0)
 852                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 853                         break;
 854                 }
 855
 856                 j += s->stat_sizeof;
 857                 p = (char *)priv + s->stat_offset;
 858                 *(u32 *)p = val;
 859         }
 860 }
 861
 862 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 863                                        struct ethtool_stats *stats,
 864                                        u64 *data)
 865 {
 866         struct bcmgenet_priv *priv = netdev_priv(dev);
 867         int i;
 868
 869         if (netif_running(dev))
 870                 bcmgenet_update_mib_counters(priv);
 871
 872         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 873                 const struct bcmgenet_stats *s;
 874                 char *p;
 875
 876                 s = &bcmgenet_gstrings_stats[i];
 877                 if (s->type == BCMGENET_STAT_NETDEV)
 878                         p = (char *)&dev->stats;
 879                 else
 880                         p = (char *)priv;
 881                 p += s->stat_offset;
 882                 data[i] = *(u32 *)p;
 883         }
 884 }
 885
 886 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 887 {
 888         struct bcmgenet_priv *priv = netdev_priv(dev);
 889         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 890         u32 reg;
 891
 892         if (enable && !priv->clk_eee_enabled) {
 893                 clk_prepare_enable(priv->clk_eee);
 894                 priv->clk_eee_enabled = true;
 895         }
 896
 897         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 898         if (enable)
 899                 reg |= EEE_EN;
 900         else
 901                 reg &= ~EEE_EN;
 902         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 903
 904         /* Enable EEE and switch to a 27Mhz clock automatically */
 905         reg = __raw_readl(priv->base + off);
 906         if (enable)
 907                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 908         else
 909                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 910         __raw_writel(reg, priv->base + off);
 911
 912         /* Do the same for thing for RBUF */
 913         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 914         if (enable)
 915                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 916         else
 917                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 918         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 919
 920         if (!enable && priv->clk_eee_enabled) {
 921                 clk_disable_unprepare(priv->clk_eee);
 922                 priv->clk_eee_enabled = false;
 923         }
 924
 925         priv->eee.eee_enabled = enable;
 926         priv->eee.eee_active = enable;
 927 }
 928
 929 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 930 {
 931         struct bcmgenet_priv *priv = netdev_priv(dev);
 932         struct ethtool_eee *p = &priv->eee;
 933
 934         if (GENET_IS_V1(priv))
 935                 return -EOPNOTSUPP;
 936
 937         e->eee_enabled = p->eee_enabled;
 938         e->eee_active = p->eee_active;
 939         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 940
 941         return phy_ethtool_get_eee(priv->phydev, e);
 942 }
 943
 944 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 945 {
 946         struct bcmgenet_priv *priv = netdev_priv(dev);
 947         struct ethtool_eee *p = &priv->eee;
 948         int ret = 0;
 949
 950         if (GENET_IS_V1(priv))
 951                 return -EOPNOTSUPP;
 952
 953         p->eee_enabled = e->eee_enabled;
 954
 955         if (!p->eee_enabled) {
 956                 bcmgenet_eee_enable_set(dev, false);
 957         } else {
 958                 ret = phy_init_eee(priv->phydev, 0);
 959                 if (ret) {
 960                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 961                         return ret;
 962                 }
 963
 964                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 965                 bcmgenet_eee_enable_set(dev, true);
 966         }
 967
 968         return phy_ethtool_set_eee(priv->phydev, e);
 969 }
 970
 971 static int bcmgenet_nway_reset(struct net_device *dev)
 972 {
 973         struct bcmgenet_priv *priv = netdev_priv(dev);
 974
 975         return genphy_restart_aneg(priv->phydev);
 976 }
 977
 978 /* standard ethtool support functions. */
 979 static struct ethtool_ops bcmgenet_ethtool_ops = {
 980         .get_strings            = bcmgenet_get_strings,
 981         .get_sset_count         = bcmgenet_get_sset_count,
 982         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 983         .get_settings           = bcmgenet_get_settings,
 984         .set_settings           = bcmgenet_set_settings,
 985         .get_drvinfo            = bcmgenet_get_drvinfo,
 986         .get_link               = ethtool_op_get_link,
 987         .get_msglevel           = bcmgenet_get_msglevel,
 988         .set_msglevel           = bcmgenet_set_msglevel,
 989         .get_wol                = bcmgenet_get_wol,
 990         .set_wol                = bcmgenet_set_wol,
 991         .get_eee                = bcmgenet_get_eee,
 992         .set_eee                = bcmgenet_set_eee,
 993         .nway_reset             = bcmgenet_nway_reset,
 994         .get_coalesce           = bcmgenet_get_coalesce,
 995         .set_coalesce           = bcmgenet_set_coalesce,
 996 };
 997
 998 /* Power down the unimac, based on mode. */
 999 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1000                                 enum bcmgenet_power_mode mode)
1001 {
1002         int ret = 0;
1003         u32 reg;
1004
1005         switch (mode) {
1006         case GENET_POWER_CABLE_SENSE:
1007                 phy_detach(priv->phydev);
1008                 break;
1009
1010         case GENET_POWER_WOL_MAGIC:
1011                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1012                 break;
1013
1014         case GENET_POWER_PASSIVE:
1015                 /* Power down LED */
1016                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1017                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1018                         reg |= (EXT_PWR_DOWN_PHY |
1019                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1020                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1021
1022                         bcmgenet_phy_power_set(priv->dev, false);
1023                 }
1024                 break;
1025         default:
1026                 break;
1027         }
1028
1029         return 0;
1030 }
1031
1032 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1033                               enum bcmgenet_power_mode mode)
1034 {
1035         u32 reg;
1036
1037         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1038                 return;
1039
1040         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1041
1042         switch (mode) {
1043         case GENET_POWER_PASSIVE:
1044                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1045                                 EXT_PWR_DOWN_BIAS);
1046                 /* fallthrough */
1047         case GENET_POWER_CABLE_SENSE:
1048                 /* enable APD */
1049                 reg |= EXT_PWR_DN_EN_LD;
1050                 break;
1051         case GENET_POWER_WOL_MAGIC:
1052                 bcmgenet_wol_power_up_cfg(priv, mode);
1053                 return;
1054         default:
1055                 break;
1056         }
1057
1058         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1059         if (mode == GENET_POWER_PASSIVE)
1060                 bcmgenet_phy_power_set(priv->dev, true);
1061 }
1062
1063 /* ioctl handle special commands that are not present in ethtool. */
1064 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1065 {
1066         struct bcmgenet_priv *priv = netdev_priv(dev);
1067         int val = 0;
1068
1069         if (!netif_running(dev))
1070                 return -EINVAL;
1071
1072         switch (cmd) {
1073         case SIOCGMIIPHY:
1074         case SIOCGMIIREG:
1075         case SIOCSMIIREG:
1076                 if (!priv->phydev)
1077                         val = -ENODEV;
1078                 else
1079                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
1080                 break;
1081
1082         default:
1083                 val = -EINVAL;
1084                 break;
1085         }
1086
1087         return val;
1088 }
1089
1090 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1091                                          struct bcmgenet_tx_ring *ring)
1092 {
1093         struct enet_cb *tx_cb_ptr;
1094
1095         tx_cb_ptr = ring->cbs;
1096         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1097
1098         /* Advancing local write pointer */
1099         if (ring->write_ptr == ring->end_ptr)
1100                 ring->write_ptr = ring->cb_ptr;
1101         else
1102                 ring->write_ptr++;
1103
1104         return tx_cb_ptr;
1105 }
1106
1107 /* Simple helper to free a control block's resources */
1108 static void bcmgenet_free_cb(struct enet_cb *cb)
1109 {
1110         dev_kfree_skb_any(cb->skb);
1111         cb->skb = NULL;
1112         dma_unmap_addr_set(cb, dma_addr, 0);
1113 }
1114
1115 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1116 {
1117         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1118                                  INTRL2_CPU_MASK_SET);
1119 }
1120
1121 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1122 {
1123         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1124                                  INTRL2_CPU_MASK_CLEAR);
1125 }
1126
1127 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1128 {
1129         bcmgenet_intrl2_1_writel(ring->priv,
1130                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1131                                  INTRL2_CPU_MASK_SET);
1132 }
1133
1134 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1135 {
1136         bcmgenet_intrl2_1_writel(ring->priv,
1137                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1138                                  INTRL2_CPU_MASK_CLEAR);
1139 }
1140
1141 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1142 {
1143         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1144                                  INTRL2_CPU_MASK_SET);
1145 }
1146
1147 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1148 {
1149         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1150                                  INTRL2_CPU_MASK_CLEAR);
1151 }
1152
1153 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1154 {
1155         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1156                                  INTRL2_CPU_MASK_CLEAR);
1157 }
1158
1159 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1160 {
1161         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1162                                  INTRL2_CPU_MASK_SET);
1163 }
1164
1165 /* Unlocked version of the reclaim routine */
1166 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1167                                           struct bcmgenet_tx_ring *ring)
1168 {
1169         struct bcmgenet_priv *priv = netdev_priv(dev);
1170         struct enet_cb *tx_cb_ptr;
1171         struct netdev_queue *txq;
1172         unsigned int pkts_compl = 0;
1173         unsigned int c_index;
1174         unsigned int txbds_ready;
1175         unsigned int txbds_processed = 0;
1176
1177         /* Compute how many buffers are transmitted since last xmit call */
1178         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1179         c_index &= DMA_C_INDEX_MASK;
1180
1181         if (likely(c_index >= ring->c_index))
1182                 txbds_ready = c_index - ring->c_index;
1183         else
1184                 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1185
1186         netif_dbg(priv, tx_done, dev,
1187                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1188                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1189
1190         /* Reclaim transmitted buffers */
1191         while (txbds_processed < txbds_ready) {
1192                 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1193                 if (tx_cb_ptr->skb) {
1194                         pkts_compl++;
1195                         dev->stats.tx_packets++;
1196                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1197                         dma_unmap_single(&dev->dev,
1198                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1199                                          tx_cb_ptr->skb->len,
1200                                          DMA_TO_DEVICE);
1201                         bcmgenet_free_cb(tx_cb_ptr);
1202                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1203                         dev->stats.tx_bytes +=
1204                                 dma_unmap_len(tx_cb_ptr, dma_len);
1205                         dma_unmap_page(&dev->dev,
1206                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1207                                        dma_unmap_len(tx_cb_ptr, dma_len),
1208                                        DMA_TO_DEVICE);
1209                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1210                 }
1211
1212                 txbds_processed++;
1213                 if (likely(ring->clean_ptr < ring->end_ptr))
1214                         ring->clean_ptr++;
1215                 else
1216                         ring->clean_ptr = ring->cb_ptr;
1217         }
1218
1219         ring->free_bds += txbds_processed;
1220         ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1221
1222         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1223                 txq = netdev_get_tx_queue(dev, ring->queue);
1224                 if (netif_tx_queue_stopped(txq))
1225                         netif_tx_wake_queue(txq);
1226         }
1227
1228         return pkts_compl;
1229 }
1230
1231 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1232                                 struct bcmgenet_tx_ring *ring)
1233 {
1234         unsigned int released;
1235         unsigned long flags;
1236
1237         spin_lock_irqsave(&ring->lock, flags);
1238         released = __bcmgenet_tx_reclaim(dev, ring);
1239         spin_unlock_irqrestore(&ring->lock, flags);
1240
1241         return released;
1242 }
1243
1244 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1245 {
1246         struct bcmgenet_tx_ring *ring =
1247                 container_of(napi, struct bcmgenet_tx_ring, napi);
1248         unsigned int work_done = 0;
1249
1250         work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1251
1252         if (work_done == 0) {
1253                 napi_complete(napi);
1254                 ring->int_enable(ring);
1255
1256                 return 0;
1257         }
1258
1259         return budget;
1260 }
1261
1262 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1263 {
1264         struct bcmgenet_priv *priv = netdev_priv(dev);
1265         int i;
1266
1267         if (netif_is_multiqueue(dev)) {
1268                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1269                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1270         }
1271
1272         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1273 }
1274
1275 /* Transmits a single SKB (either head of a fragment or a single SKB)
1276  * caller must hold priv->lock
1277  */
1278 static int bcmgenet_xmit_single(struct net_device *dev,
1279                                 struct sk_buff *skb,
1280                                 u16 dma_desc_flags,
1281                                 struct bcmgenet_tx_ring *ring)
1282 {
1283         struct bcmgenet_priv *priv = netdev_priv(dev);
1284         struct device *kdev = &priv->pdev->dev;
1285         struct enet_cb *tx_cb_ptr;
1286         unsigned int skb_len;
1287         dma_addr_t mapping;
1288         u32 length_status;
1289         int ret;
1290
1291         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1292
1293         if (unlikely(!tx_cb_ptr))
1294                 BUG();
1295
1296         tx_cb_ptr->skb = skb;
1297
1298         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1299
1300         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1301         ret = dma_mapping_error(kdev, mapping);
1302         if (ret) {
1303                 priv->mib.tx_dma_failed++;
1304                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1305                 dev_kfree_skb(skb);
1306                 return ret;
1307         }
1308
1309         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1310         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1311         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1312                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1313                         DMA_TX_APPEND_CRC;
1314
1315         if (skb->ip_summed == CHECKSUM_PARTIAL)
1316                 length_status |= DMA_TX_DO_CSUM;
1317
1318         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1319
1320         return 0;
1321 }
1322
1323 /* Transmit a SKB fragment */
1324 static int bcmgenet_xmit_frag(struct net_device *dev,
1325                               skb_frag_t *frag,
1326                               u16 dma_desc_flags,
1327                               struct bcmgenet_tx_ring *ring)
1328 {
1329         struct bcmgenet_priv *priv = netdev_priv(dev);
1330         struct device *kdev = &priv->pdev->dev;
1331         struct enet_cb *tx_cb_ptr;
1332         dma_addr_t mapping;
1333         int ret;
1334
1335         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1336
1337         if (unlikely(!tx_cb_ptr))
1338                 BUG();
1339         tx_cb_ptr->skb = NULL;
1340
1341         mapping = skb_frag_dma_map(kdev, frag, 0,
1342                                    skb_frag_size(frag), DMA_TO_DEVICE);
1343         ret = dma_mapping_error(kdev, mapping);
1344         if (ret) {
1345                 priv->mib.tx_dma_failed++;
1346                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1347                           __func__);
1348                 return ret;
1349         }
1350
1351         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1352         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1353
1354         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1355                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1356                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1357
1358         return 0;
1359 }
1360
1361 /* Reallocate the SKB to put enough headroom in front of it and insert
1362  * the transmit checksum offsets in the descriptors
1363  */
1364 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1365                                             struct sk_buff *skb)
1366 {
1367         struct status_64 *status = NULL;
1368         struct sk_buff *new_skb;
1369         u16 offset;
1370         u8 ip_proto;
1371         u16 ip_ver;
1372         u32 tx_csum_info;
1373
1374         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1375                 /* If 64 byte status block enabled, must make sure skb has
1376                  * enough headroom for us to insert 64B status block.
1377                  */
1378                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1379                 dev_kfree_skb(skb);
1380                 if (!new_skb) {
1381                         dev->stats.tx_dropped++;
1382                         return NULL;
1383                 }
1384                 skb = new_skb;
1385         }
1386
1387         skb_push(skb, sizeof(*status));
1388         status = (struct status_64 *)skb->data;
1389
1390         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1391                 ip_ver = htons(skb->protocol);
1392                 switch (ip_ver) {
1393                 case ETH_P_IP:
1394                         ip_proto = ip_hdr(skb)->protocol;
1395                         break;
1396                 case ETH_P_IPV6:
1397                         ip_proto = ipv6_hdr(skb)->nexthdr;
1398                         break;
1399                 default:
1400                         return skb;
1401                 }
1402
1403                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1404                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1405                                 (offset + skb->csum_offset);
1406
1407                 /* Set the length valid bit for TCP and UDP and just set
1408                  * the special UDP flag for IPv4, else just set to 0.
1409                  */
1410                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1411                         tx_csum_info |= STATUS_TX_CSUM_LV;
1412                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1413                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1414                 } else {
1415                         tx_csum_info = 0;
1416                 }
1417
1418                 status->tx_csum_info = tx_csum_info;
1419         }
1420
1421         return skb;
1422 }
1423
1424 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1425 {
1426         struct bcmgenet_priv *priv = netdev_priv(dev);
1427         struct bcmgenet_tx_ring *ring = NULL;
1428         struct netdev_queue *txq;
1429         unsigned long flags = 0;
1430         int nr_frags, index;
1431         u16 dma_desc_flags;
1432         int ret;
1433         int i;
1434
1435         index = skb_get_queue_mapping(skb);
1436         /* Mapping strategy:
1437          * queue_mapping = 0, unclassified, packet xmited through ring16
1438          * queue_mapping = 1, goes to ring 0. (highest priority queue
1439          * queue_mapping = 2, goes to ring 1.
1440          * queue_mapping = 3, goes to ring 2.
1441          * queue_mapping = 4, goes to ring 3.
1442          */
1443         if (index == 0)
1444                 index = DESC_INDEX;
1445         else
1446                 index -= 1;
1447
1448         nr_frags = skb_shinfo(skb)->nr_frags;
1449         ring = &priv->tx_rings[index];
1450         txq = netdev_get_tx_queue(dev, ring->queue);
1451
1452         spin_lock_irqsave(&ring->lock, flags);
1453         if (ring->free_bds <= nr_frags + 1) {
1454                 netif_tx_stop_queue(txq);
1455                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1456                            __func__, index, ring->queue);
1457                 ret = NETDEV_TX_BUSY;
1458                 goto out;
1459         }
1460
1461         if (skb_padto(skb, ETH_ZLEN)) {
1462                 ret = NETDEV_TX_OK;
1463                 goto out;
1464         }
1465
1466         /* set the SKB transmit checksum */
1467         if (priv->desc_64b_en) {
1468                 skb = bcmgenet_put_tx_csum(dev, skb);
1469                 if (!skb) {
1470                         ret = NETDEV_TX_OK;
1471                         goto out;
1472                 }
1473         }
1474
1475         dma_desc_flags = DMA_SOP;
1476         if (nr_frags == 0)
1477                 dma_desc_flags |= DMA_EOP;
1478
1479         /* Transmit single SKB or head of fragment list */
1480         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1481         if (ret) {
1482                 ret = NETDEV_TX_OK;
1483                 goto out;
1484         }
1485
1486         /* xmit fragment */
1487         for (i = 0; i < nr_frags; i++) {
1488                 ret = bcmgenet_xmit_frag(dev,
1489                                          &skb_shinfo(skb)->frags[i],
1490                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1491                                          ring);
1492                 if (ret) {
1493                         ret = NETDEV_TX_OK;
1494                         goto out;
1495                 }
1496         }
1497
1498         skb_tx_timestamp(skb);
1499
1500         /* Decrement total BD count and advance our write pointer */
1501         ring->free_bds -= nr_frags + 1;
1502         ring->prod_index += nr_frags + 1;
1503         ring->prod_index &= DMA_P_INDEX_MASK;
1504
1505         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1506                 netif_tx_stop_queue(txq);
1507
1508         if (!skb->xmit_more || netif_xmit_stopped(txq))
1509                 /* Packets are ready, update producer index */
1510                 bcmgenet_tdma_ring_writel(priv, ring->index,
1511                                           ring->prod_index, TDMA_PROD_INDEX);
1512 out:
1513         spin_unlock_irqrestore(&ring->lock, flags);
1514
1515         return ret;
1516 }
1517
1518 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1519                                           struct enet_cb *cb)
1520 {
1521         struct device *kdev = &priv->pdev->dev;
1522         struct sk_buff *skb;
1523         struct sk_buff *rx_skb;
1524         dma_addr_t mapping;
1525
1526         /* Allocate a new Rx skb */
1527         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1528         if (!skb) {
1529                 priv->mib.alloc_rx_buff_failed++;
1530                 netif_err(priv, rx_err, priv->dev,
1531                           "%s: Rx skb allocation failed\n", __func__);
1532                 return NULL;
1533         }
1534
1535         /* DMA-map the new Rx skb */
1536         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1537                                  DMA_FROM_DEVICE);
1538         if (dma_mapping_error(kdev, mapping)) {
1539                 priv->mib.rx_dma_failed++;
1540                 dev_kfree_skb_any(skb);
1541                 netif_err(priv, rx_err, priv->dev,
1542                           "%s: Rx skb DMA mapping failed\n", __func__);
1543                 return NULL;
1544         }
1545
1546         /* Grab the current Rx skb from the ring and DMA-unmap it */
1547         rx_skb = cb->skb;
1548         if (likely(rx_skb))
1549                 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1550                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1551
1552         /* Put the new Rx skb on the ring */
1553         cb->skb = skb;
1554         dma_unmap_addr_set(cb, dma_addr, mapping);
1555         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1556
1557         /* Return the current Rx skb to caller */
1558         return rx_skb;
1559 }
1560
1561 /* bcmgenet_desc_rx - descriptor based rx process.
1562  * this could be called from bottom half, or from NAPI polling method.
1563  */
1564 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1565                                      unsigned int budget)
1566 {
1567         struct bcmgenet_priv *priv = ring->priv;
1568         struct net_device *dev = priv->dev;
1569         struct enet_cb *cb;
1570         struct sk_buff *skb;
1571         u32 dma_length_status;
1572         unsigned long dma_flag;
1573         int len;
1574         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1575         unsigned int p_index;
1576         unsigned int discards;
1577         unsigned int chksum_ok = 0;
1578
1579         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1580
1581         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1582                    DMA_P_INDEX_DISCARD_CNT_MASK;
1583         if (discards > ring->old_discards) {
1584                 discards = discards - ring->old_discards;
1585                 dev->stats.rx_missed_errors += discards;
1586                 dev->stats.rx_errors += discards;
1587                 ring->old_discards += discards;
1588
1589                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1590                 if (ring->old_discards >= 0xC000) {
1591                         ring->old_discards = 0;
1592                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1593                                                   RDMA_PROD_INDEX);
1594                 }
1595         }
1596
1597         p_index &= DMA_P_INDEX_MASK;
1598
1599         if (likely(p_index >= ring->c_index))
1600                 rxpkttoprocess = p_index - ring->c_index;
1601         else
1602                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1603                                  p_index;
1604
1605         netif_dbg(priv, rx_status, dev,
1606                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1607
1608         while ((rxpktprocessed < rxpkttoprocess) &&
1609                (rxpktprocessed < budget)) {
1610                 cb = &priv->rx_cbs[ring->read_ptr];
1611                 skb = bcmgenet_rx_refill(priv, cb);
1612
1613                 if (unlikely(!skb)) {
1614                         dev->stats.rx_dropped++;
1615                         goto next;
1616                 }
1617
1618                 if (!priv->desc_64b_en) {
1619                         dma_length_status =
1620                                 dmadesc_get_length_status(priv, cb->bd_addr);
1621                 } else {
1622                         struct status_64 *status;
1623
1624                         status = (struct status_64 *)skb->data;
1625                         dma_length_status = status->length_status;
1626                 }
1627
1628                 /* DMA flags and length are still valid no matter how
1629                  * we got the Receive Status Vector (64B RSB or register)
1630                  */
1631                 dma_flag = dma_length_status & 0xffff;
1632                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1633
1634                 netif_dbg(priv, rx_status, dev,
1635                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1636                           __func__, p_index, ring->c_index,
1637                           ring->read_ptr, dma_length_status);
1638
1639                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1640                         netif_err(priv, rx_status, dev,
1641                                   "dropping fragmented packet!\n");
1642                         dev->stats.rx_errors++;
1643                         dev_kfree_skb_any(skb);
1644                         goto next;
1645                 }
1646
1647                 /* report errors */
1648                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1649                                                 DMA_RX_OV |
1650                                                 DMA_RX_NO |
1651                                                 DMA_RX_LG |
1652                                                 DMA_RX_RXER))) {
1653                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1654                                   (unsigned int)dma_flag);
1655                         if (dma_flag & DMA_RX_CRC_ERROR)
1656                                 dev->stats.rx_crc_errors++;
1657                         if (dma_flag & DMA_RX_OV)
1658                                 dev->stats.rx_over_errors++;
1659                         if (dma_flag & DMA_RX_NO)
1660                                 dev->stats.rx_frame_errors++;
1661                         if (dma_flag & DMA_RX_LG)
1662                                 dev->stats.rx_length_errors++;
1663                         dev->stats.rx_errors++;
1664                         dev_kfree_skb_any(skb);
1665                         goto next;
1666                 } /* error packet */
1667
1668                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1669                              priv->desc_rxchk_en;
1670
1671                 skb_put(skb, len);
1672                 if (priv->desc_64b_en) {
1673                         skb_pull(skb, 64);
1674                         len -= 64;
1675                 }
1676
1677                 if (likely(chksum_ok))
1678                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1679
1680                 /* remove hardware 2bytes added for IP alignment */
1681                 skb_pull(skb, 2);
1682                 len -= 2;
1683
1684                 if (priv->crc_fwd_en) {
1685                         skb_trim(skb, len - ETH_FCS_LEN);
1686                         len -= ETH_FCS_LEN;
1687                 }
1688
1689                 /*Finish setting up the received SKB and send it to the kernel*/
1690                 skb->protocol = eth_type_trans(skb, priv->dev);
1691                 dev->stats.rx_packets++;
1692                 dev->stats.rx_bytes += len;
1693                 if (dma_flag & DMA_RX_MULT)
1694                         dev->stats.multicast++;
1695
1696                 /* Notify kernel */
1697                 napi_gro_receive(&ring->napi, skb);
1698                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1699
1700 next:
1701                 rxpktprocessed++;
1702                 if (likely(ring->read_ptr < ring->end_ptr))
1703                         ring->read_ptr++;
1704                 else
1705                         ring->read_ptr = ring->cb_ptr;
1706
1707                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1708                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1709         }
1710
1711         return rxpktprocessed;
1712 }
1713
1714 /* Rx NAPI polling method */
1715 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1716 {
1717         struct bcmgenet_rx_ring *ring = container_of(napi,
1718                         struct bcmgenet_rx_ring, napi);
1719         unsigned int work_done;
1720
1721         work_done = bcmgenet_desc_rx(ring, budget);
1722
1723         if (work_done < budget) {
1724                 napi_complete(napi);
1725                 ring->int_enable(ring);
1726         }
1727
1728         return work_done;
1729 }
1730
1731 /* Assign skb to RX DMA descriptor. */
1732 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1733                                      struct bcmgenet_rx_ring *ring)
1734 {
1735         struct enet_cb *cb;
1736         struct sk_buff *skb;
1737         int i;
1738
1739         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1740
1741         /* loop here for each buffer needing assign */
1742         for (i = 0; i < ring->size; i++) {
1743                 cb = ring->cbs + i;
1744                 skb = bcmgenet_rx_refill(priv, cb);
1745                 if (skb)
1746                         dev_kfree_skb_any(skb);
1747                 if (!cb->skb)
1748                         return -ENOMEM;
1749         }
1750
1751         return 0;
1752 }
1753
1754 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1755 {
1756         struct enet_cb *cb;
1757         int i;
1758
1759         for (i = 0; i < priv->num_rx_bds; i++) {
1760                 cb = &priv->rx_cbs[i];
1761
1762                 if (dma_unmap_addr(cb, dma_addr)) {
1763                         dma_unmap_single(&priv->dev->dev,
1764                                          dma_unmap_addr(cb, dma_addr),
1765                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1766                         dma_unmap_addr_set(cb, dma_addr, 0);
1767                 }
1768
1769                 if (cb->skb)
1770                         bcmgenet_free_cb(cb);
1771         }
1772 }
1773
1774 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1775 {
1776         u32 reg;
1777
1778         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1779         if (enable)
1780                 reg |= mask;
1781         else
1782                 reg &= ~mask;
1783         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1784
1785         /* UniMAC stops on a packet boundary, wait for a full-size packet
1786          * to be processed
1787          */
1788         if (enable == 0)
1789                 usleep_range(1000, 2000);
1790 }
1791
1792 static int reset_umac(struct bcmgenet_priv *priv)
1793 {
1794         struct device *kdev = &priv->pdev->dev;
1795         unsigned int timeout = 0;
1796         u32 reg;
1797
1798         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1799         bcmgenet_rbuf_ctrl_set(priv, 0);
1800         udelay(10);
1801
1802         /* disable MAC while updating its registers */
1803         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1804
1805         /* issue soft reset, wait for it to complete */
1806         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1807         while (timeout++ < 1000) {
1808                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1809                 if (!(reg & CMD_SW_RESET))
1810                         return 0;
1811
1812                 udelay(1);
1813         }
1814
1815         if (timeout == 1000) {
1816                 dev_err(kdev,
1817                         "timeout waiting for MAC to come out of reset\n");
1818                 return -ETIMEDOUT;
1819         }
1820
1821         return 0;
1822 }
1823
1824 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1825 {
1826         /* Mask all interrupts.*/
1827         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1828         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1829         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1830         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1831         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1832         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1833 }
1834
1835 static int init_umac(struct bcmgenet_priv *priv)
1836 {
1837         struct device *kdev = &priv->pdev->dev;
1838         int ret;
1839         u32 reg;
1840         u32 int0_enable = 0;
1841         u32 int1_enable = 0;
1842         int i;
1843
1844         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1845
1846         ret = reset_umac(priv);
1847         if (ret)
1848                 return ret;
1849
1850         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1851         /* clear tx/rx counter */
1852         bcmgenet_umac_writel(priv,
1853                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1854                              UMAC_MIB_CTRL);
1855         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1856
1857         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1858
1859         /* init rx registers, enable ip header optimization */
1860         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1861         reg |= RBUF_ALIGN_2B;
1862         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1863
1864         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1865                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1866
1867         bcmgenet_intr_disable(priv);
1868
1869         /* Enable Rx default queue 16 interrupts */
1870         int0_enable |= UMAC_IRQ_RXDMA_DONE;
1871
1872         /* Enable Tx default queue 16 interrupts */
1873         int0_enable |= UMAC_IRQ_TXDMA_DONE;
1874
1875         /* Monitor cable plug/unplugged event for internal PHY */
1876         if (priv->internal_phy) {
1877                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1878         } else if (priv->ext_phy) {
1879                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1880         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1881                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1882                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1883
1884                 reg = bcmgenet_bp_mc_get(priv);
1885                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1886
1887                 /* bp_mask: back pressure mask */
1888                 if (netif_is_multiqueue(priv->dev))
1889                         reg |= priv->hw_params->bp_in_mask;
1890                 else
1891                         reg &= ~priv->hw_params->bp_in_mask;
1892                 bcmgenet_bp_mc_set(priv, reg);
1893         }
1894
1895         /* Enable MDIO interrupts on GENET v3+ */
1896         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1897                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1898
1899         /* Enable Rx priority queue interrupts */
1900         for (i = 0; i < priv->hw_params->rx_queues; ++i)
1901                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1902
1903         /* Enable Tx priority queue interrupts */
1904         for (i = 0; i < priv->hw_params->tx_queues; ++i)
1905                 int1_enable |= (1 << i);
1906
1907         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1908         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1909
1910         /* Enable rx/tx engine.*/
1911         dev_dbg(kdev, "done init umac\n");
1912
1913         return 0;
1914 }
1915
1916 /* Initialize a Tx ring along with corresponding hardware registers */
1917 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1918                                   unsigned int index, unsigned int size,
1919                                   unsigned int start_ptr, unsigned int end_ptr)
1920 {
1921         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1922         u32 words_per_bd = WORDS_PER_BD(priv);
1923         u32 flow_period_val = 0;
1924
1925         spin_lock_init(&ring->lock);
1926         ring->priv = priv;
1927         ring->index = index;
1928         if (index == DESC_INDEX) {
1929                 ring->queue = 0;
1930                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1931                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1932         } else {
1933                 ring->queue = index + 1;
1934                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1935                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1936         }
1937         ring->cbs = priv->tx_cbs + start_ptr;
1938         ring->size = size;
1939         ring->clean_ptr = start_ptr;
1940         ring->c_index = 0;
1941         ring->free_bds = size;
1942         ring->write_ptr = start_ptr;
1943         ring->cb_ptr = start_ptr;
1944         ring->end_ptr = end_ptr - 1;
1945         ring->prod_index = 0;
1946
1947         /* Set flow period for ring != 16 */
1948         if (index != DESC_INDEX)
1949                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1950
1951         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1952         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1953         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1954         /* Disable rate control for now */
1955         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1956                                   TDMA_FLOW_PERIOD);
1957         bcmgenet_tdma_ring_writel(priv, index,
1958                                   ((size << DMA_RING_SIZE_SHIFT) |
1959                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1960
1961         /* Set start and end address, read and write pointers */
1962         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1963                                   DMA_START_ADDR);
1964         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1965                                   TDMA_READ_PTR);
1966         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1967                                   TDMA_WRITE_PTR);
1968         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1969                                   DMA_END_ADDR);
1970 }
1971
1972 /* Initialize a RDMA ring */
1973 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1974                                  unsigned int index, unsigned int size,
1975                                  unsigned int start_ptr, unsigned int end_ptr)
1976 {
1977         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1978         u32 words_per_bd = WORDS_PER_BD(priv);
1979         int ret;
1980
1981         ring->priv = priv;
1982         ring->index = index;
1983         if (index == DESC_INDEX) {
1984                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1985                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1986         } else {
1987                 ring->int_enable = bcmgenet_rx_ring_int_enable;
1988                 ring->int_disable = bcmgenet_rx_ring_int_disable;
1989         }
1990         ring->cbs = priv->rx_cbs + start_ptr;
1991         ring->size = size;
1992         ring->c_index = 0;
1993         ring->read_ptr = start_ptr;
1994         ring->cb_ptr = start_ptr;
1995         ring->end_ptr = end_ptr - 1;
1996
1997         ret = bcmgenet_alloc_rx_buffers(priv, ring);
1998         if (ret)
1999                 return ret;
2000
2001         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2002         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2003         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2004         bcmgenet_rdma_ring_writel(priv, index,
2005                                   ((size << DMA_RING_SIZE_SHIFT) |
2006                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2007         bcmgenet_rdma_ring_writel(priv, index,
2008                                   (DMA_FC_THRESH_LO <<
2009                                    DMA_XOFF_THRESHOLD_SHIFT) |
2010                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2011
2012         /* Set start and end address, read and write pointers */
2013         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2014                                   DMA_START_ADDR);
2015         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2016                                   RDMA_READ_PTR);
2017         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2018                                   RDMA_WRITE_PTR);
2019         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2020                                   DMA_END_ADDR);
2021
2022         return ret;
2023 }
2024
2025 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2026 {
2027         unsigned int i;
2028         struct bcmgenet_tx_ring *ring;
2029
2030         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2031                 ring = &priv->tx_rings[i];
2032                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2033         }
2034
2035         ring = &priv->tx_rings[DESC_INDEX];
2036         netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2037 }
2038
2039 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2040 {
2041         unsigned int i;
2042         struct bcmgenet_tx_ring *ring;
2043
2044         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2045                 ring = &priv->tx_rings[i];
2046                 napi_enable(&ring->napi);
2047         }
2048
2049         ring = &priv->tx_rings[DESC_INDEX];
2050         napi_enable(&ring->napi);
2051 }
2052
2053 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2054 {
2055         unsigned int i;
2056         struct bcmgenet_tx_ring *ring;
2057
2058         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2059                 ring = &priv->tx_rings[i];
2060                 napi_disable(&ring->napi);
2061         }
2062
2063         ring = &priv->tx_rings[DESC_INDEX];
2064         napi_disable(&ring->napi);
2065 }
2066
2067 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2068 {
2069         unsigned int i;
2070         struct bcmgenet_tx_ring *ring;
2071
2072         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2073                 ring = &priv->tx_rings[i];
2074                 netif_napi_del(&ring->napi);
2075         }
2076
2077         ring = &priv->tx_rings[DESC_INDEX];
2078         netif_napi_del(&ring->napi);
2079 }
2080
2081 /* Initialize Tx queues
2082  *
2083  * Queues 0-3 are priority-based, each one has 32 descriptors,
2084  * with queue 0 being the highest priority queue.
2085  *
2086  * Queue 16 is the default Tx queue with
2087  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2088  *
2089  * The transmit control block pool is then partitioned as follows:
2090  * - Tx queue 0 uses tx_cbs[0..31]
2091  * - Tx queue 1 uses tx_cbs[32..63]
2092  * - Tx queue 2 uses tx_cbs[64..95]
2093  * - Tx queue 3 uses tx_cbs[96..127]
2094  * - Tx queue 16 uses tx_cbs[128..255]
2095  */
2096 static void bcmgenet_init_tx_queues(struct net_device *dev)
2097 {
2098         struct bcmgenet_priv *priv = netdev_priv(dev);
2099         u32 i, dma_enable;
2100         u32 dma_ctrl, ring_cfg;
2101         u32 dma_priority[3] = {0, 0, 0};
2102
2103         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2104         dma_enable = dma_ctrl & DMA_EN;
2105         dma_ctrl &= ~DMA_EN;
2106         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2107
2108         dma_ctrl = 0;
2109         ring_cfg = 0;
2110
2111         /* Enable strict priority arbiter mode */
2112         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2113
2114         /* Initialize Tx priority queues */
2115         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2116                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2117                                       i * priv->hw_params->tx_bds_per_q,
2118                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2119                 ring_cfg |= (1 << i);
2120                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2121                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2122                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2123         }
2124
2125         /* Initialize Tx default queue 16 */
2126         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2127                               priv->hw_params->tx_queues *
2128                               priv->hw_params->tx_bds_per_q,
2129                               TOTAL_DESC);
2130         ring_cfg |= (1 << DESC_INDEX);
2131         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2132         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2133                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2134                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2135
2136         /* Set Tx queue priorities */
2137         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2138         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2139         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2140
2141         /* Initialize Tx NAPI */
2142         bcmgenet_init_tx_napi(priv);
2143
2144         /* Enable Tx queues */
2145         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2146
2147         /* Enable Tx DMA */
2148         if (dma_enable)
2149                 dma_ctrl |= DMA_EN;
2150         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2151 }
2152
2153 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2154 {
2155         unsigned int i;
2156         struct bcmgenet_rx_ring *ring;
2157
2158         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2159                 ring = &priv->rx_rings[i];
2160                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2161         }
2162
2163         ring = &priv->rx_rings[DESC_INDEX];
2164         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2165 }
2166
2167 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2168 {
2169         unsigned int i;
2170         struct bcmgenet_rx_ring *ring;
2171
2172         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2173                 ring = &priv->rx_rings[i];
2174                 napi_enable(&ring->napi);
2175         }
2176
2177         ring = &priv->rx_rings[DESC_INDEX];
2178         napi_enable(&ring->napi);
2179 }
2180
2181 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2182 {
2183         unsigned int i;
2184         struct bcmgenet_rx_ring *ring;
2185
2186         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2187                 ring = &priv->rx_rings[i];
2188                 napi_disable(&ring->napi);
2189         }
2190
2191         ring = &priv->rx_rings[DESC_INDEX];
2192         napi_disable(&ring->napi);
2193 }
2194
2195 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2196 {
2197         unsigned int i;
2198         struct bcmgenet_rx_ring *ring;
2199
2200         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2201                 ring = &priv->rx_rings[i];
2202                 netif_napi_del(&ring->napi);
2203         }
2204
2205         ring = &priv->rx_rings[DESC_INDEX];
2206         netif_napi_del(&ring->napi);
2207 }
2208
2209 /* Initialize Rx queues
2210  *
2211  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2212  * used to direct traffic to these queues.
2213  *
2214  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2215  */
2216 static int bcmgenet_init_rx_queues(struct net_device *dev)
2217 {
2218         struct bcmgenet_priv *priv = netdev_priv(dev);
2219         u32 i;
2220         u32 dma_enable;
2221         u32 dma_ctrl;
2222         u32 ring_cfg;
2223         int ret;
2224
2225         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2226         dma_enable = dma_ctrl & DMA_EN;
2227         dma_ctrl &= ~DMA_EN;
2228         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2229
2230         dma_ctrl = 0;
2231         ring_cfg = 0;
2232
2233         /* Initialize Rx priority queues */
2234         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2235                 ret = bcmgenet_init_rx_ring(priv, i,
2236                                             priv->hw_params->rx_bds_per_q,
2237                                             i * priv->hw_params->rx_bds_per_q,
2238                                             (i + 1) *
2239                                             priv->hw_params->rx_bds_per_q);
2240                 if (ret)
2241                         return ret;
2242
2243                 ring_cfg |= (1 << i);
2244                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2245         }
2246
2247         /* Initialize Rx default queue 16 */
2248         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2249                                     priv->hw_params->rx_queues *
2250                                     priv->hw_params->rx_bds_per_q,
2251                                     TOTAL_DESC);
2252         if (ret)
2253                 return ret;
2254
2255         ring_cfg |= (1 << DESC_INDEX);
2256         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2257
2258         /* Initialize Rx NAPI */
2259         bcmgenet_init_rx_napi(priv);
2260
2261         /* Enable rings */
2262         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2263
2264         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2265         if (dma_enable)
2266                 dma_ctrl |= DMA_EN;
2267         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2268
2269         return 0;
2270 }
2271
2272 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2273 {
2274         int ret = 0;
2275         int timeout = 0;
2276         u32 reg;
2277         u32 dma_ctrl;
2278         int i;
2279
2280         /* Disable TDMA to stop add more frames in TX DMA */
2281         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2282         reg &= ~DMA_EN;
2283         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2284
2285         /* Check TDMA status register to confirm TDMA is disabled */
2286         while (timeout++ < DMA_TIMEOUT_VAL) {
2287                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2288                 if (reg & DMA_DISABLED)
2289                         break;
2290
2291                 udelay(1);
2292         }
2293
2294         if (timeout == DMA_TIMEOUT_VAL) {
2295                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2296                 ret = -ETIMEDOUT;
2297         }
2298
2299         /* Wait 10ms for packet drain in both tx and rx dma */
2300         usleep_range(10000, 20000);
2301
2302         /* Disable RDMA */
2303         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2304         reg &= ~DMA_EN;
2305         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2306
2307         timeout = 0;
2308         /* Check RDMA status register to confirm RDMA is disabled */
2309         while (timeout++ < DMA_TIMEOUT_VAL) {
2310                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2311                 if (reg & DMA_DISABLED)
2312                         break;
2313
2314                 udelay(1);
2315         }
2316
2317         if (timeout == DMA_TIMEOUT_VAL) {
2318                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2319                 ret = -ETIMEDOUT;
2320         }
2321
2322         dma_ctrl = 0;
2323         for (i = 0; i < priv->hw_params->rx_queues; i++)
2324                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2325         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2326         reg &= ~dma_ctrl;
2327         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2328
2329         dma_ctrl = 0;
2330         for (i = 0; i < priv->hw_params->tx_queues; i++)
2331                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2332         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2333         reg &= ~dma_ctrl;
2334         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2335
2336         return ret;
2337 }
2338
2339 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2340 {
2341         int i;
2342
2343         bcmgenet_fini_rx_napi(priv);
2344         bcmgenet_fini_tx_napi(priv);
2345
2346         /* disable DMA */
2347         bcmgenet_dma_teardown(priv);
2348
2349         for (i = 0; i < priv->num_tx_bds; i++) {
2350                 if (priv->tx_cbs[i].skb != NULL) {
2351                         dev_kfree_skb(priv->tx_cbs[i].skb);
2352                         priv->tx_cbs[i].skb = NULL;
2353                 }
2354         }
2355
2356         bcmgenet_free_rx_buffers(priv);
2357         kfree(priv->rx_cbs);
2358         kfree(priv->tx_cbs);
2359 }
2360
2361 /* init_edma: Initialize DMA control register */
2362 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2363 {
2364         int ret;
2365         unsigned int i;
2366         struct enet_cb *cb;
2367
2368         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2369
2370         /* Initialize common Rx ring structures */
2371         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2372         priv->num_rx_bds = TOTAL_DESC;
2373         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2374                                GFP_KERNEL);
2375         if (!priv->rx_cbs)
2376                 return -ENOMEM;
2377
2378         for (i = 0; i < priv->num_rx_bds; i++) {
2379                 cb = priv->rx_cbs + i;
2380                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2381         }
2382
2383         /* Initialize common TX ring structures */
2384         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2385         priv->num_tx_bds = TOTAL_DESC;
2386         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2387                                GFP_KERNEL);
2388         if (!priv->tx_cbs) {
2389                 kfree(priv->rx_cbs);
2390                 return -ENOMEM;
2391         }
2392
2393         for (i = 0; i < priv->num_tx_bds; i++) {
2394                 cb = priv->tx_cbs + i;
2395                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2396         }
2397
2398         /* Init rDma */
2399         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2400
2401         /* Initialize Rx queues */
2402         ret = bcmgenet_init_rx_queues(priv->dev);
2403         if (ret) {
2404                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2405                 bcmgenet_free_rx_buffers(priv);
2406                 kfree(priv->rx_cbs);
2407                 kfree(priv->tx_cbs);
2408                 return ret;
2409         }
2410
2411         /* Init tDma */
2412         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2413
2414         /* Initialize Tx queues */
2415         bcmgenet_init_tx_queues(priv->dev);
2416
2417         return 0;
2418 }
2419
2420 /* Interrupt bottom half */
2421 static void bcmgenet_irq_task(struct work_struct *work)
2422 {
2423         struct bcmgenet_priv *priv = container_of(
2424                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2425
2426         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2427
2428         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2429                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2430                 netif_dbg(priv, wol, priv->dev,
2431                           "magic packet detected, waking up\n");
2432                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2433         }
2434
2435         /* Link UP/DOWN event */
2436         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2437             (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
2438                 phy_mac_interrupt(priv->phydev,
2439                                   !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2440                 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2441         }
2442 }
2443
2444 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2445 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2446 {
2447         struct bcmgenet_priv *priv = dev_id;
2448         struct bcmgenet_rx_ring *rx_ring;
2449         struct bcmgenet_tx_ring *tx_ring;
2450         unsigned int index;
2451
2452         /* Save irq status for bottom-half processing. */
2453         priv->irq1_stat =
2454                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2455                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2456
2457         /* clear interrupts */
2458         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2459
2460         netif_dbg(priv, intr, priv->dev,
2461                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2462
2463         /* Check Rx priority queue interrupts */
2464         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2465                 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2466                         continue;
2467
2468                 rx_ring = &priv->rx_rings[index];
2469
2470                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2471                         rx_ring->int_disable(rx_ring);
2472                         __napi_schedule(&rx_ring->napi);
2473                 }
2474         }
2475
2476         /* Check Tx priority queue interrupts */
2477         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2478                 if (!(priv->irq1_stat & BIT(index)))
2479                         continue;
2480
2481                 tx_ring = &priv->tx_rings[index];
2482
2483                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2484                         tx_ring->int_disable(tx_ring);
2485                         __napi_schedule(&tx_ring->napi);
2486                 }
2487         }
2488
2489         return IRQ_HANDLED;
2490 }
2491
2492 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2493 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2494 {
2495         struct bcmgenet_priv *priv = dev_id;
2496         struct bcmgenet_rx_ring *rx_ring;
2497         struct bcmgenet_tx_ring *tx_ring;
2498
2499         /* Save irq status for bottom-half processing. */
2500         priv->irq0_stat =
2501                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2502                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2503
2504         /* clear interrupts */
2505         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2506
2507         netif_dbg(priv, intr, priv->dev,
2508                   "IRQ=0x%x\n", priv->irq0_stat);
2509
2510         if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2511                 rx_ring = &priv->rx_rings[DESC_INDEX];
2512
2513                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2514                         rx_ring->int_disable(rx_ring);
2515                         __napi_schedule(&rx_ring->napi);
2516                 }
2517         }
2518
2519         if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2520                 tx_ring = &priv->tx_rings[DESC_INDEX];
2521
2522                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2523                         tx_ring->int_disable(tx_ring);
2524                         __napi_schedule(&tx_ring->napi);
2525                 }
2526         }
2527
2528         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2529                                 UMAC_IRQ_PHY_DET_F |
2530                                 UMAC_IRQ_LINK_EVENT |
2531                                 UMAC_IRQ_HFB_SM |
2532                                 UMAC_IRQ_HFB_MM |
2533                                 UMAC_IRQ_MPD_R)) {
2534                 /* all other interested interrupts handled in bottom half */
2535                 schedule_work(&priv->bcmgenet_irq_work);
2536         }
2537
2538         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2539             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2540                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2541                 wake_up(&priv->wq);
2542         }
2543
2544         return IRQ_HANDLED;
2545 }
2546
2547 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2548 {
2549         struct bcmgenet_priv *priv = dev_id;
2550
2551         pm_wakeup_event(&priv->pdev->dev, 0);
2552
2553         return IRQ_HANDLED;
2554 }
2555
2556 #ifdef CONFIG_NET_POLL_CONTROLLER
2557 static void bcmgenet_poll_controller(struct net_device *dev)
2558 {
2559         struct bcmgenet_priv *priv = netdev_priv(dev);
2560
2561         /* Invoke the main RX/TX interrupt handler */
2562         disable_irq(priv->irq0);
2563         bcmgenet_isr0(priv->irq0, priv);
2564         enable_irq(priv->irq0);
2565
2566         /* And the interrupt handler for RX/TX priority queues */
2567         disable_irq(priv->irq1);
2568         bcmgenet_isr1(priv->irq1, priv);
2569         enable_irq(priv->irq1);
2570 }
2571 #endif
2572
2573 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2574 {
2575         u32 reg;
2576
2577         reg = bcmgenet_rbuf_ctrl_get(priv);
2578         reg |= BIT(1);
2579         bcmgenet_rbuf_ctrl_set(priv, reg);
2580         udelay(10);
2581
2582         reg &= ~BIT(1);
2583         bcmgenet_rbuf_ctrl_set(priv, reg);
2584         udelay(10);
2585 }
2586
2587 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2588                                  unsigned char *addr)
2589 {
2590         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2591                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2592         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2593 }
2594
2595 /* Returns a reusable dma control register value */
2596 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2597 {
2598         u32 reg;
2599         u32 dma_ctrl;
2600
2601         /* disable DMA */
2602         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2603         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2604         reg &= ~dma_ctrl;
2605         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2606
2607         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2608         reg &= ~dma_ctrl;
2609         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2610
2611         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2612         udelay(10);
2613         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2614
2615         return dma_ctrl;
2616 }
2617
2618 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2619 {
2620         u32 reg;
2621
2622         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2623         reg |= dma_ctrl;
2624         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2625
2626         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2627         reg |= dma_ctrl;
2628         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2629 }
2630
2631 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2632                                            u32 f_index)
2633 {
2634         u32 offset;
2635         u32 reg;
2636
2637         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2638         reg = bcmgenet_hfb_reg_readl(priv, offset);
2639         return !!(reg & (1 << (f_index % 32)));
2640 }
2641
2642 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2643 {
2644         u32 offset;
2645         u32 reg;
2646
2647         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2648         reg = bcmgenet_hfb_reg_readl(priv, offset);
2649         reg |= (1 << (f_index % 32));
2650         bcmgenet_hfb_reg_writel(priv, reg, offset);
2651 }
2652
2653 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2654                                                      u32 f_index, u32 rx_queue)
2655 {
2656         u32 offset;
2657         u32 reg;
2658
2659         offset = f_index / 8;
2660         reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2661         reg &= ~(0xF << (4 * (f_index % 8)));
2662         reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2663         bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2664 }
2665
2666 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2667                                            u32 f_index, u32 f_length)
2668 {
2669         u32 offset;
2670         u32 reg;
2671
2672         offset = HFB_FLT_LEN_V3PLUS +
2673                  ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2674                  sizeof(u32);
2675         reg = bcmgenet_hfb_reg_readl(priv, offset);
2676         reg &= ~(0xFF << (8 * (f_index % 4)));
2677         reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2678         bcmgenet_hfb_reg_writel(priv, reg, offset);
2679 }
2680
2681 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2682 {
2683         u32 f_index;
2684
2685         for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2686                 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2687                         return f_index;
2688
2689         return -ENOMEM;
2690 }
2691
2692 /* bcmgenet_hfb_add_filter
2693  *
2694  * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2695  * desired Rx queue.
2696  *
2697  * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2698  * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2699  *
2700  * bits 31:20 - unused
2701  * bit  19    - nibble 0 match enable
2702  * bit  18    - nibble 1 match enable
2703  * bit  17    - nibble 2 match enable
2704  * bit  16    - nibble 3 match enable
2705  * bits 15:12 - nibble 0 data
2706  * bits 11:8  - nibble 1 data
2707  * bits 7:4   - nibble 2 data
2708  * bits 3:0   - nibble 3 data
2709  *
2710  * Example:
2711  * In order to match:
2712  * - Ethernet frame type = 0x0800 (IP)
2713  * - IP version field = 4
2714  * - IP protocol field = 0x11 (UDP)
2715  *
2716  * The following filter is needed:
2717  * u32 hfb_filter_ipv4_udp[] = {
2718  *   Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2719  *   Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2720  *   Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2721  * };
2722  *
2723  * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2724  * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2725  *                         ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2726  */
2727 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2728                             u32 f_length, u32 rx_queue)
2729 {
2730         int f_index;
2731         u32 i;
2732
2733         f_index = bcmgenet_hfb_find_unused_filter(priv);
2734         if (f_index < 0)
2735                 return -ENOMEM;
2736
2737         if (f_length > priv->hw_params->hfb_filter_size)
2738                 return -EINVAL;
2739
2740         for (i = 0; i < f_length; i++)
2741                 bcmgenet_hfb_writel(priv, f_data[i],
2742                         (f_index * priv->hw_params->hfb_filter_size + i) *
2743                         sizeof(u32));
2744
2745         bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2746         bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2747         bcmgenet_hfb_enable_filter(priv, f_index);
2748         bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2749
2750         return 0;
2751 }
2752
2753 /* bcmgenet_hfb_clear
2754  *
2755  * Clear Hardware Filter Block and disable all filtering.
2756  */
2757 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2758 {
2759         u32 i;
2760
2761         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2762         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2763         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2764
2765         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2766                 bcmgenet_rdma_writel(priv, 0x0, i);
2767
2768         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2769                 bcmgenet_hfb_reg_writel(priv, 0x0,
2770                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2771
2772         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2773                         priv->hw_params->hfb_filter_size; i++)
2774                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2775 }
2776
2777 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2778 {
2779         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2780                 return;
2781
2782         bcmgenet_hfb_clear(priv);
2783 }
2784
2785 static void bcmgenet_netif_start(struct net_device *dev)
2786 {
2787         struct bcmgenet_priv *priv = netdev_priv(dev);
2788
2789         /* Start the network engine */
2790         bcmgenet_enable_rx_napi(priv);
2791         bcmgenet_enable_tx_napi(priv);
2792
2793         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2794
2795         netif_tx_start_all_queues(dev);
2796
2797         phy_start(priv->phydev);
2798 }
2799
2800 static int bcmgenet_open(struct net_device *dev)
2801 {
2802         struct bcmgenet_priv *priv = netdev_priv(dev);
2803         unsigned long dma_ctrl;
2804         u32 reg;
2805         int ret;
2806
2807         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2808
2809         /* Turn on the clock */
2810         clk_prepare_enable(priv->clk);
2811
2812         /* If this is an internal GPHY, power it back on now, before UniMAC is
2813          * brought out of reset as absolutely no UniMAC activity is allowed
2814          */
2815         if (priv->internal_phy)
2816                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2817
2818         /* take MAC out of reset */
2819         bcmgenet_umac_reset(priv);
2820
2821         ret = init_umac(priv);
2822         if (ret)
2823                 goto err_clk_disable;
2824
2825         /* disable ethernet MAC while updating its registers */
2826         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2827
2828         /* Make sure we reflect the value of CRC_CMD_FWD */
2829         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2830         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2831
2832         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2833
2834         if (priv->internal_phy) {
2835                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2836                 reg |= EXT_ENERGY_DET_MASK;
2837                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2838         }
2839
2840         /* Disable RX/TX DMA and flush TX queues */
2841         dma_ctrl = bcmgenet_dma_disable(priv);
2842
2843         /* Reinitialize TDMA and RDMA and SW housekeeping */
2844         ret = bcmgenet_init_dma(priv);
2845         if (ret) {
2846                 netdev_err(dev, "failed to initialize DMA\n");
2847                 goto err_clk_disable;
2848         }
2849
2850         /* Always enable ring 16 - descriptor ring */
2851         bcmgenet_enable_dma(priv, dma_ctrl);
2852
2853         /* HFB init */
2854         bcmgenet_hfb_init(priv);
2855
2856         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2857                           dev->name, priv);
2858         if (ret < 0) {
2859                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2860                 goto err_fini_dma;
2861         }
2862
2863         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2864                           dev->name, priv);
2865         if (ret < 0) {
2866                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2867                 goto err_irq0;
2868         }
2869
2870         ret = bcmgenet_mii_probe(dev);
2871         if (ret) {
2872                 netdev_err(dev, "failed to connect to PHY\n");
2873                 goto err_irq1;
2874         }
2875
2876         bcmgenet_netif_start(dev);
2877
2878         return 0;
2879
2880 err_irq1:
2881         free_irq(priv->irq1, priv);
2882 err_irq0:
2883         free_irq(priv->irq0, priv);
2884 err_fini_dma:
2885         bcmgenet_fini_dma(priv);
2886 err_clk_disable:
2887         clk_disable_unprepare(priv->clk);
2888         return ret;
2889 }
2890
2891 static void bcmgenet_netif_stop(struct net_device *dev)
2892 {
2893         struct bcmgenet_priv *priv = netdev_priv(dev);
2894
2895         netif_tx_stop_all_queues(dev);
2896         phy_stop(priv->phydev);
2897         bcmgenet_intr_disable(priv);
2898         bcmgenet_disable_rx_napi(priv);
2899         bcmgenet_disable_tx_napi(priv);
2900
2901         /* Wait for pending work items to complete. Since interrupts are
2902          * disabled no new work will be scheduled.
2903          */
2904         cancel_work_sync(&priv->bcmgenet_irq_work);
2905
2906         priv->old_link = -1;
2907         priv->old_speed = -1;
2908         priv->old_duplex = -1;
2909         priv->old_pause = -1;
2910 }
2911
2912 static int bcmgenet_close(struct net_device *dev)
2913 {
2914         struct bcmgenet_priv *priv = netdev_priv(dev);
2915         int ret;
2916
2917         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2918
2919         bcmgenet_netif_stop(dev);
2920
2921         /* Really kill the PHY state machine and disconnect from it */
2922         phy_disconnect(priv->phydev);
2923
2924         /* Disable MAC receive */
2925         umac_enable_set(priv, CMD_RX_EN, false);
2926
2927         ret = bcmgenet_dma_teardown(priv);
2928         if (ret)
2929                 return ret;
2930
2931         /* Disable MAC transmit. TX DMA disabled have to done before this */
2932         umac_enable_set(priv, CMD_TX_EN, false);
2933
2934         /* tx reclaim */
2935         bcmgenet_tx_reclaim_all(dev);
2936         bcmgenet_fini_dma(priv);
2937
2938         free_irq(priv->irq0, priv);
2939         free_irq(priv->irq1, priv);
2940
2941         if (priv->internal_phy)
2942                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2943
2944         clk_disable_unprepare(priv->clk);
2945
2946         return ret;
2947 }
2948
2949 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2950 {
2951         struct bcmgenet_priv *priv = ring->priv;
2952         u32 p_index, c_index, intsts, intmsk;
2953         struct netdev_queue *txq;
2954         unsigned int free_bds;
2955         unsigned long flags;
2956         bool txq_stopped;
2957
2958         if (!netif_msg_tx_err(priv))
2959                 return;
2960
2961         txq = netdev_get_tx_queue(priv->dev, ring->queue);
2962
2963         spin_lock_irqsave(&ring->lock, flags);
2964         if (ring->index == DESC_INDEX) {
2965                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2966                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2967         } else {
2968                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2969                 intmsk = 1 << ring->index;
2970         }
2971         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2972         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2973         txq_stopped = netif_tx_queue_stopped(txq);
2974         free_bds = ring->free_bds;
2975         spin_unlock_irqrestore(&ring->lock, flags);
2976
2977         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2978                   "TX queue status: %s, interrupts: %s\n"
2979                   "(sw)free_bds: %d (sw)size: %d\n"
2980                   "(sw)p_index: %d (hw)p_index: %d\n"
2981                   "(sw)c_index: %d (hw)c_index: %d\n"
2982                   "(sw)clean_p: %d (sw)write_p: %d\n"
2983                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2984                   ring->index, ring->queue,
2985                   txq_stopped ? "stopped" : "active",
2986                   intsts & intmsk ? "enabled" : "disabled",
2987                   free_bds, ring->size,
2988                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
2989                   ring->c_index, c_index & DMA_C_INDEX_MASK,
2990                   ring->clean_ptr, ring->write_ptr,
2991                   ring->cb_ptr, ring->end_ptr);
2992 }
2993
2994 static void bcmgenet_timeout(struct net_device *dev)
2995 {
2996         struct bcmgenet_priv *priv = netdev_priv(dev);
2997         u32 int0_enable = 0;
2998         u32 int1_enable = 0;
2999         unsigned int q;
3000
3001         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3002
3003         for (q = 0; q < priv->hw_params->tx_queues; q++)
3004                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3005         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3006
3007         bcmgenet_tx_reclaim_all(dev);
3008
3009         for (q = 0; q < priv->hw_params->tx_queues; q++)
3010                 int1_enable |= (1 << q);
3011
3012         int0_enable = UMAC_IRQ_TXDMA_DONE;
3013
3014         /* Re-enable TX interrupts if disabled */
3015         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3016         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3017
3018         dev->trans_start = jiffies;
3019
3020         dev->stats.tx_errors++;
3021
3022         netif_tx_wake_all_queues(dev);
3023 }
3024
3025 #define MAX_MC_COUNT    16
3026
3027 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3028                                          unsigned char *addr,
3029                                          int *i,
3030                                          int *mc)
3031 {
3032         u32 reg;
3033
3034         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3035                              UMAC_MDF_ADDR + (*i * 4));
3036         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3037                              addr[4] << 8 | addr[5],
3038                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3039         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3040         reg |= (1 << (MAX_MC_COUNT - *mc));
3041         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3042         *i += 2;
3043         (*mc)++;
3044 }
3045
3046 static void bcmgenet_set_rx_mode(struct net_device *dev)
3047 {
3048         struct bcmgenet_priv *priv = netdev_priv(dev);
3049         struct netdev_hw_addr *ha;
3050         int i, mc;
3051         u32 reg;
3052
3053         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3054
3055         /* Promiscuous mode */
3056         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3057         if (dev->flags & IFF_PROMISC) {
3058                 reg |= CMD_PROMISC;
3059                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3060                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3061                 return;
3062         } else {
3063                 reg &= ~CMD_PROMISC;
3064                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3065         }
3066
3067         /* UniMac doesn't support ALLMULTI */
3068         if (dev->flags & IFF_ALLMULTI) {
3069                 netdev_warn(dev, "ALLMULTI is not supported\n");
3070                 return;
3071         }
3072
3073         /* update MDF filter */
3074         i = 0;
3075         mc = 0;
3076         /* Broadcast */
3077         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3078         /* my own address.*/
3079         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3080         /* Unicast list*/
3081         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3082                 return;
3083
3084         if (!netdev_uc_empty(dev))
3085                 netdev_for_each_uc_addr(ha, dev)
3086                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3087         /* Multicast */
3088         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3089                 return;
3090
3091         netdev_for_each_mc_addr(ha, dev)
3092                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3093 }
3094
3095 /* Set the hardware MAC address. */
3096 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3097 {
3098         struct sockaddr *addr = p;
3099
3100         /* Setting the MAC address at the hardware level is not possible
3101          * without disabling the UniMAC RX/TX enable bits.
3102          */
3103         if (netif_running(dev))
3104                 return -EBUSY;
3105
3106         ether_addr_copy(dev->dev_addr, addr->sa_data);
3107
3108         return 0;
3109 }
3110
3111 static const struct net_device_ops bcmgenet_netdev_ops = {
3112         .ndo_open               = bcmgenet_open,
3113         .ndo_stop               = bcmgenet_close,
3114         .ndo_start_xmit         = bcmgenet_xmit,
3115         .ndo_tx_timeout         = bcmgenet_timeout,
3116         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3117         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3118         .ndo_do_ioctl           = bcmgenet_ioctl,
3119         .ndo_set_features       = bcmgenet_set_features,
3120 #ifdef CONFIG_NET_POLL_CONTROLLER
3121         .ndo_poll_controller    = bcmgenet_poll_controller,
3122 #endif
3123 };
3124
3125 /* Array of GENET hardware parameters/characteristics */
3126 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3127         [GENET_V1] = {
3128                 .tx_queues = 0,
3129                 .tx_bds_per_q = 0,
3130                 .rx_queues = 0,
3131                 .rx_bds_per_q = 0,
3132                 .bp_in_en_shift = 16,
3133                 .bp_in_mask = 0xffff,
3134                 .hfb_filter_cnt = 16,
3135                 .qtag_mask = 0x1F,
3136                 .hfb_offset = 0x1000,
3137                 .rdma_offset = 0x2000,
3138                 .tdma_offset = 0x3000,
3139                 .words_per_bd = 2,
3140         },
3141         [GENET_V2] = {
3142                 .tx_queues = 4,
3143                 .tx_bds_per_q = 32,
3144                 .rx_queues = 0,
3145                 .rx_bds_per_q = 0,
3146                 .bp_in_en_shift = 16,
3147                 .bp_in_mask = 0xffff,
3148                 .hfb_filter_cnt = 16,
3149                 .qtag_mask = 0x1F,
3150                 .tbuf_offset = 0x0600,
3151                 .hfb_offset = 0x1000,
3152                 .hfb_reg_offset = 0x2000,
3153                 .rdma_offset = 0x3000,
3154                 .tdma_offset = 0x4000,
3155                 .words_per_bd = 2,
3156                 .flags = GENET_HAS_EXT,
3157         },
3158         [GENET_V3] = {
3159                 .tx_queues = 4,
3160                 .tx_bds_per_q = 32,
3161                 .rx_queues = 0,
3162                 .rx_bds_per_q = 0,
3163                 .bp_in_en_shift = 17,
3164                 .bp_in_mask = 0x1ffff,
3165                 .hfb_filter_cnt = 48,
3166                 .hfb_filter_size = 128,
3167                 .qtag_mask = 0x3F,
3168                 .tbuf_offset = 0x0600,
3169                 .hfb_offset = 0x8000,
3170                 .hfb_reg_offset = 0xfc00,
3171                 .rdma_offset = 0x10000,
3172                 .tdma_offset = 0x11000,
3173                 .words_per_bd = 2,
3174                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3175                          GENET_HAS_MOCA_LINK_DET,
3176         },
3177         [GENET_V4] = {
3178                 .tx_queues = 4,
3179                 .tx_bds_per_q = 32,
3180                 .rx_queues = 0,
3181                 .rx_bds_per_q = 0,
3182                 .bp_in_en_shift = 17,
3183                 .bp_in_mask = 0x1ffff,
3184                 .hfb_filter_cnt = 48,
3185                 .hfb_filter_size = 128,
3186                 .qtag_mask = 0x3F,
3187                 .tbuf_offset = 0x0600,
3188                 .hfb_offset = 0x8000,
3189                 .hfb_reg_offset = 0xfc00,
3190                 .rdma_offset = 0x2000,
3191                 .tdma_offset = 0x4000,
3192                 .words_per_bd = 3,
3193                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3194                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3195         },
3196 };
3197
3198 /* Infer hardware parameters from the detected GENET version */
3199 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3200 {
3201         struct bcmgenet_hw_params *params;
3202         u32 reg;
3203         u8 major;
3204         u16 gphy_rev;
3205
3206         if (GENET_IS_V4(priv)) {
3207                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3208                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3209                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3210                 priv->version = GENET_V4;
3211         } else if (GENET_IS_V3(priv)) {
3212                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3213                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3214                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3215                 priv->version = GENET_V3;
3216         } else if (GENET_IS_V2(priv)) {
3217                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3218                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3219                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3220                 priv->version = GENET_V2;
3221         } else if (GENET_IS_V1(priv)) {
3222                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3223                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3224                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3225                 priv->version = GENET_V1;
3226         }
3227
3228         /* enum genet_version starts at 1 */
3229         priv->hw_params = &bcmgenet_hw_params[priv->version];
3230         params = priv->hw_params;
3231
3232         /* Read GENET HW version */
3233         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3234         major = (reg >> 24 & 0x0f);
3235         if (major == 5)
3236                 major = 4;
3237         else if (major == 0)
3238                 major = 1;
3239         if (major != priv->version) {
3240                 dev_err(&priv->pdev->dev,
3241                         "GENET version mismatch, got: %d, configured for: %d\n",
3242                         major, priv->version);
3243         }
3244
3245         /* Print the GENET core version */
3246         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3247                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3248
3249         /* Store the integrated PHY revision for the MDIO probing function
3250          * to pass this information to the PHY driver. The PHY driver expects
3251          * to find the PHY major revision in bits 15:8 while the GENET register
3252          * stores that information in bits 7:0, account for that.
3253          *
3254          * On newer chips, starting with PHY revision G0, a new scheme is
3255          * deployed similar to the Starfighter 2 switch with GPHY major
3256          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3257          * is reserved as well as special value 0x01ff, we have a small
3258          * heuristic to check for the new GPHY revision and re-arrange things
3259          * so the GPHY driver is happy.
3260          */
3261         gphy_rev = reg & 0xffff;
3262
3263         /* This is the good old scheme, just GPHY major, no minor nor patch */
3264         if ((gphy_rev & 0xf0) != 0)
3265                 priv->gphy_rev = gphy_rev << 8;
3266
3267         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3268         else if ((gphy_rev & 0xff00) != 0)
3269                 priv->gphy_rev = gphy_rev;
3270
3271         /* This is reserved so should require special treatment */
3272         else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3273                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3274                 return;
3275         }
3276
3277 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3278         if (!(params->flags & GENET_HAS_40BITS))
3279                 pr_warn("GENET does not support 40-bits PA\n");
3280 #endif
3281
3282         pr_debug("Configuration for version: %d\n"
3283                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3284                 "BP << en: %2d, BP msk: 0x%05x\n"
3285                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3286                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3287                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3288                 "Words/BD: %d\n",
3289                 priv->version,
3290                 params->tx_queues, params->tx_bds_per_q,
3291                 params->rx_queues, params->rx_bds_per_q,
3292                 params->bp_in_en_shift, params->bp_in_mask,
3293                 params->hfb_filter_cnt, params->qtag_mask,
3294                 params->tbuf_offset, params->hfb_offset,
3295                 params->hfb_reg_offset,
3296                 params->rdma_offset, params->tdma_offset,
3297                 params->words_per_bd);
3298 }
3299
3300 static const struct of_device_id bcmgenet_match[] = {
3301         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3302         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3303         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3304         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3305         { },
3306 };
3307 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3308
3309 static int bcmgenet_probe(struct platform_device *pdev)
3310 {
3311         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3312         struct device_node *dn = pdev->dev.of_node;
3313         const struct of_device_id *of_id = NULL;
3314         struct bcmgenet_priv *priv;
3315         struct net_device *dev;
3316         const void *macaddr;
3317         struct resource *r;
3318         int err = -EIO;
3319
3320         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3321         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3322                                  GENET_MAX_MQ_CNT + 1);
3323         if (!dev) {
3324                 dev_err(&pdev->dev, "can't allocate net device\n");
3325                 return -ENOMEM;
3326         }
3327
3328         if (dn) {
3329                 of_id = of_match_node(bcmgenet_match, dn);
3330                 if (!of_id)
3331                         return -EINVAL;
3332         }
3333
3334         priv = netdev_priv(dev);
3335         priv->irq0 = platform_get_irq(pdev, 0);
3336         priv->irq1 = platform_get_irq(pdev, 1);
3337         priv->wol_irq = platform_get_irq(pdev, 2);
3338         if (!priv->irq0 || !priv->irq1) {
3339                 dev_err(&pdev->dev, "can't find IRQs\n");
3340                 err = -EINVAL;
3341                 goto err;
3342         }
3343
3344         if (dn) {
3345                 macaddr = of_get_mac_address(dn);
3346                 if (!macaddr) {
3347                         dev_err(&pdev->dev, "can't find MAC address\n");
3348                         err = -EINVAL;
3349                         goto err;
3350                 }
3351         } else {
3352                 macaddr = pd->mac_address;
3353         }
3354
3355         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3356         priv->base = devm_ioremap_resource(&pdev->dev, r);
3357         if (IS_ERR(priv->base)) {
3358                 err = PTR_ERR(priv->base);
3359                 goto err;
3360         }
3361
3362         SET_NETDEV_DEV(dev, &pdev->dev);
3363         dev_set_drvdata(&pdev->dev, dev);
3364         ether_addr_copy(dev->dev_addr, macaddr);
3365         dev->watchdog_timeo = 2 * HZ;
3366         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3367         dev->netdev_ops = &bcmgenet_netdev_ops;
3368
3369         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3370
3371         /* Set hardware features */
3372         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3373                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3374
3375         /* Request the WOL interrupt and advertise suspend if available */
3376         priv->wol_irq_disabled = true;
3377         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3378                                dev->name, priv);
3379         if (!err)
3380                 device_set_wakeup_capable(&pdev->dev, 1);
3381
3382         /* Set the needed headroom to account for any possible
3383          * features enabling/disabling at runtime
3384          */
3385         dev->needed_headroom += 64;
3386
3387         netdev_boot_setup_check(dev);
3388
3389         priv->dev = dev;
3390         priv->pdev = pdev;
3391         if (of_id)
3392                 priv->version = (enum bcmgenet_version)of_id->data;
3393         else
3394                 priv->version = pd->genet_version;
3395
3396         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3397         if (IS_ERR(priv->clk)) {
3398                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3399                 priv->clk = NULL;
3400         }
3401
3402         clk_prepare_enable(priv->clk);
3403
3404         bcmgenet_set_hw_params(priv);
3405
3406         /* Mii wait queue */
3407         init_waitqueue_head(&priv->wq);
3408         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3409         priv->rx_buf_len = RX_BUF_LENGTH;
3410         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3411
3412         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3413         if (IS_ERR(priv->clk_wol)) {
3414                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3415                 priv->clk_wol = NULL;
3416         }
3417
3418         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3419         if (IS_ERR(priv->clk_eee)) {
3420                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3421                 priv->clk_eee = NULL;
3422         }
3423
3424         err = reset_umac(priv);
3425         if (err)
3426                 goto err_clk_disable;
3427
3428         err = bcmgenet_mii_init(dev);
3429         if (err)
3430                 goto err_clk_disable;
3431
3432         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3433          * just the ring 16 descriptor based TX
3434          */
3435         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3436         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3437
3438         /* libphy will determine the link state */
3439         netif_carrier_off(dev);
3440
3441         /* Turn off the main clock, WOL clock is handled separately */
3442         clk_disable_unprepare(priv->clk);
3443
3444         err = register_netdev(dev);
3445         if (err)
3446                 goto err;
3447
3448         return err;
3449
3450 err_clk_disable:
3451         clk_disable_unprepare(priv->clk);
3452 err:
3453         free_netdev(dev);
3454         return err;
3455 }
3456
3457 static int bcmgenet_remove(struct platform_device *pdev)
3458 {
3459         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3460
3461         dev_set_drvdata(&pdev->dev, NULL);
3462         unregister_netdev(priv->dev);
3463         bcmgenet_mii_exit(priv->dev);
3464         free_netdev(priv->dev);
3465
3466         return 0;
3467 }
3468
3469 #ifdef CONFIG_PM_SLEEP
3470 static int bcmgenet_suspend(struct device *d)
3471 {
3472         struct net_device *dev = dev_get_drvdata(d);
3473         struct bcmgenet_priv *priv = netdev_priv(dev);
3474         int ret;
3475
3476         if (!netif_running(dev))
3477                 return 0;
3478
3479         bcmgenet_netif_stop(dev);
3480
3481         phy_suspend(priv->phydev);
3482
3483         netif_device_detach(dev);
3484
3485         /* Disable MAC receive */
3486         umac_enable_set(priv, CMD_RX_EN, false);
3487
3488         ret = bcmgenet_dma_teardown(priv);
3489         if (ret)
3490                 return ret;
3491
3492         /* Disable MAC transmit. TX DMA disabled have to done before this */
3493         umac_enable_set(priv, CMD_TX_EN, false);
3494
3495         /* tx reclaim */
3496         bcmgenet_tx_reclaim_all(dev);
3497         bcmgenet_fini_dma(priv);
3498
3499         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3500         if (device_may_wakeup(d) && priv->wolopts) {
3501                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3502                 clk_prepare_enable(priv->clk_wol);
3503         } else if (priv->internal_phy) {
3504                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3505         }
3506
3507         /* Turn off the clocks */
3508         clk_disable_unprepare(priv->clk);
3509
3510         return ret;
3511 }
3512
3513 static int bcmgenet_resume(struct device *d)
3514 {
3515         struct net_device *dev = dev_get_drvdata(d);
3516         struct bcmgenet_priv *priv = netdev_priv(dev);
3517         unsigned long dma_ctrl;
3518         int ret;
3519         u32 reg;
3520
3521         if (!netif_running(dev))
3522                 return 0;
3523
3524         /* Turn on the clock */
3525         ret = clk_prepare_enable(priv->clk);
3526         if (ret)
3527                 return ret;
3528
3529         /* If this is an internal GPHY, power it back on now, before UniMAC is
3530          * brought out of reset as absolutely no UniMAC activity is allowed
3531          */
3532         if (priv->internal_phy)
3533                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3534
3535         bcmgenet_umac_reset(priv);
3536
3537         ret = init_umac(priv);
3538         if (ret)
3539                 goto out_clk_disable;
3540
3541         /* From WOL-enabled suspend, switch to regular clock */
3542         if (priv->wolopts)
3543                 clk_disable_unprepare(priv->clk_wol);
3544
3545         phy_init_hw(priv->phydev);
3546         /* Speed settings must be restored */
3547         bcmgenet_mii_config(priv->dev);
3548
3549         /* disable ethernet MAC while updating its registers */
3550         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3551
3552         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3553
3554         if (priv->internal_phy) {
3555                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3556                 reg |= EXT_ENERGY_DET_MASK;
3557                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3558         }
3559
3560         if (priv->wolopts)
3561                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3562
3563         /* Disable RX/TX DMA and flush TX queues */
3564         dma_ctrl = bcmgenet_dma_disable(priv);
3565
3566         /* Reinitialize TDMA and RDMA and SW housekeeping */
3567         ret = bcmgenet_init_dma(priv);
3568         if (ret) {
3569                 netdev_err(dev, "failed to initialize DMA\n");
3570                 goto out_clk_disable;
3571         }
3572
3573         /* Always enable ring 16 - descriptor ring */
3574         bcmgenet_enable_dma(priv, dma_ctrl);
3575
3576         netif_device_attach(dev);
3577
3578         phy_resume(priv->phydev);
3579
3580         if (priv->eee.eee_enabled)
3581                 bcmgenet_eee_enable_set(dev, true);
3582
3583         bcmgenet_netif_start(dev);
3584
3585         return 0;
3586
3587 out_clk_disable:
3588         clk_disable_unprepare(priv->clk);
3589         return ret;
3590 }
3591 #endif /* CONFIG_PM_SLEEP */
3592
3593 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3594
3595 static struct platform_driver bcmgenet_driver = {
3596         .probe  = bcmgenet_probe,
3597         .remove = bcmgenet_remove,
3598         .driver = {
3599                 .name   = "bcmgenet",
3600                 .of_match_table = bcmgenet_match,
3601                 .pm     = &bcmgenet_pm_ops,
3602         },
3603 };
3604 module_platform_driver(bcmgenet_driver);
3605
3606 MODULE_AUTHOR("Broadcom Corporation");
3607 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3608 MODULE_ALIAS("platform:bcmgenet");
3609 MODULE_LICENSE("GPL");