drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  76                                              void __iomem *d, u32 value)
  77 {
  78         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  79 }
  80
  81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  82                                             void __iomem *d)
  83 {
  84         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  85 }
  86
  87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  88                                     void __iomem *d,
  89                                     dma_addr_t addr)
  90 {
  91         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  92
  93         /* Register writes to GISB bus can take couple hundred nanoseconds
  94          * and are done for each packet, save these expensive writes unless
  95          * the platform is explicitly configured for 64-bits/LPAE.
  96          */
  97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  98         if (priv->hw_params->flags & GENET_HAS_40BITS)
  99                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 100 #endif
 101 }
 102
 103 /* Combined address + length/status setter */
 104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 105                                void __iomem *d, dma_addr_t addr, u32 val)
 106 {
 107         dmadesc_set_length_status(priv, d, val);
 108         dmadesc_set_addr(priv, d, addr);
 109 }
 110
 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 112                                           void __iomem *d)
 113 {
 114         dma_addr_t addr;
 115
 116         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 117
 118         /* Register writes to GISB bus can take couple hundred nanoseconds
 119          * and are done for each packet, save these expensive writes unless
 120          * the platform is explicitly configured for 64-bits/LPAE.
 121          */
 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 123         if (priv->hw_params->flags & GENET_HAS_40BITS)
 124                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 125 #endif
 126         return addr;
 127 }
 128
 129 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 130
 131 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 132                                 NETIF_MSG_LINK)
 133
 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 135 {
 136         if (GENET_IS_V1(priv))
 137                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 138         else
 139                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 140 }
 141
 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 143 {
 144         if (GENET_IS_V1(priv))
 145                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 146         else
 147                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 148 }
 149
 150 /* These macros are defined to deal with register map change
 151  * between GENET1.1 and GENET2. Only those currently being used
 152  * by driver are defined.
 153  */
 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 155 {
 156         if (GENET_IS_V1(priv))
 157                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 158         else
 159                 return __raw_readl(priv->base +
 160                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 161 }
 162
 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 164 {
 165         if (GENET_IS_V1(priv))
 166                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 167         else
 168                 __raw_writel(val, priv->base +
 169                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 170 }
 171
 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 173 {
 174         if (GENET_IS_V1(priv))
 175                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 176         else
 177                 return __raw_readl(priv->base +
 178                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 179 }
 180
 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 182 {
 183         if (GENET_IS_V1(priv))
 184                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 185         else
 186                 __raw_writel(val, priv->base +
 187                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 188 }
 189
 190 /* RX/TX DMA register accessors */
 191 enum dma_reg {
 192         DMA_RING_CFG = 0,
 193         DMA_CTRL,
 194         DMA_STATUS,
 195         DMA_SCB_BURST_SIZE,
 196         DMA_ARB_CTRL,
 197         DMA_PRIORITY_0,
 198         DMA_PRIORITY_1,
 199         DMA_PRIORITY_2,
 200         DMA_INDEX2RING_0,
 201         DMA_INDEX2RING_1,
 202         DMA_INDEX2RING_2,
 203         DMA_INDEX2RING_3,
 204         DMA_INDEX2RING_4,
 205         DMA_INDEX2RING_5,
 206         DMA_INDEX2RING_6,
 207         DMA_INDEX2RING_7,
 208         DMA_RING0_TIMEOUT,
 209         DMA_RING1_TIMEOUT,
 210         DMA_RING2_TIMEOUT,
 211         DMA_RING3_TIMEOUT,
 212         DMA_RING4_TIMEOUT,
 213         DMA_RING5_TIMEOUT,
 214         DMA_RING6_TIMEOUT,
 215         DMA_RING7_TIMEOUT,
 216         DMA_RING8_TIMEOUT,
 217         DMA_RING9_TIMEOUT,
 218         DMA_RING10_TIMEOUT,
 219         DMA_RING11_TIMEOUT,
 220         DMA_RING12_TIMEOUT,
 221         DMA_RING13_TIMEOUT,
 222         DMA_RING14_TIMEOUT,
 223         DMA_RING15_TIMEOUT,
 224         DMA_RING16_TIMEOUT,
 225 };
 226
 227 static const u8 bcmgenet_dma_regs_v3plus[] = {
 228         [DMA_RING_CFG]          = 0x00,
 229         [DMA_CTRL]              = 0x04,
 230         [DMA_STATUS]            = 0x08,
 231         [DMA_SCB_BURST_SIZE]    = 0x0C,
 232         [DMA_ARB_CTRL]          = 0x2C,
 233         [DMA_PRIORITY_0]        = 0x30,
 234         [DMA_PRIORITY_1]        = 0x34,
 235         [DMA_PRIORITY_2]        = 0x38,
 236         [DMA_RING0_TIMEOUT]     = 0x2C,
 237         [DMA_RING1_TIMEOUT]     = 0x30,
 238         [DMA_RING2_TIMEOUT]     = 0x34,
 239         [DMA_RING3_TIMEOUT]     = 0x38,
 240         [DMA_RING4_TIMEOUT]     = 0x3c,
 241         [DMA_RING5_TIMEOUT]     = 0x40,
 242         [DMA_RING6_TIMEOUT]     = 0x44,
 243         [DMA_RING7_TIMEOUT]     = 0x48,
 244         [DMA_RING8_TIMEOUT]     = 0x4c,
 245         [DMA_RING9_TIMEOUT]     = 0x50,
 246         [DMA_RING10_TIMEOUT]    = 0x54,
 247         [DMA_RING11_TIMEOUT]    = 0x58,
 248         [DMA_RING12_TIMEOUT]    = 0x5c,
 249         [DMA_RING13_TIMEOUT]    = 0x60,
 250         [DMA_RING14_TIMEOUT]    = 0x64,
 251         [DMA_RING15_TIMEOUT]    = 0x68,
 252         [DMA_RING16_TIMEOUT]    = 0x6C,
 253         [DMA_INDEX2RING_0]      = 0x70,
 254         [DMA_INDEX2RING_1]      = 0x74,
 255         [DMA_INDEX2RING_2]      = 0x78,
 256         [DMA_INDEX2RING_3]      = 0x7C,
 257         [DMA_INDEX2RING_4]      = 0x80,
 258         [DMA_INDEX2RING_5]      = 0x84,
 259         [DMA_INDEX2RING_6]      = 0x88,
 260         [DMA_INDEX2RING_7]      = 0x8C,
 261 };
 262
 263 static const u8 bcmgenet_dma_regs_v2[] = {
 264         [DMA_RING_CFG]          = 0x00,
 265         [DMA_CTRL]              = 0x04,
 266         [DMA_STATUS]            = 0x08,
 267         [DMA_SCB_BURST_SIZE]    = 0x0C,
 268         [DMA_ARB_CTRL]          = 0x30,
 269         [DMA_PRIORITY_0]        = 0x34,
 270         [DMA_PRIORITY_1]        = 0x38,
 271         [DMA_PRIORITY_2]        = 0x3C,
 272         [DMA_RING0_TIMEOUT]     = 0x2C,
 273         [DMA_RING1_TIMEOUT]     = 0x30,
 274         [DMA_RING2_TIMEOUT]     = 0x34,
 275         [DMA_RING3_TIMEOUT]     = 0x38,
 276         [DMA_RING4_TIMEOUT]     = 0x3c,
 277         [DMA_RING5_TIMEOUT]     = 0x40,
 278         [DMA_RING6_TIMEOUT]     = 0x44,
 279         [DMA_RING7_TIMEOUT]     = 0x48,
 280         [DMA_RING8_TIMEOUT]     = 0x4c,
 281         [DMA_RING9_TIMEOUT]     = 0x50,
 282         [DMA_RING10_TIMEOUT]    = 0x54,
 283         [DMA_RING11_TIMEOUT]    = 0x58,
 284         [DMA_RING12_TIMEOUT]    = 0x5c,
 285         [DMA_RING13_TIMEOUT]    = 0x60,
 286         [DMA_RING14_TIMEOUT]    = 0x64,
 287         [DMA_RING15_TIMEOUT]    = 0x68,
 288         [DMA_RING16_TIMEOUT]    = 0x6C,
 289 };
 290
 291 static const u8 bcmgenet_dma_regs_v1[] = {
 292         [DMA_CTRL]              = 0x00,
 293         [DMA_STATUS]            = 0x04,
 294         [DMA_SCB_BURST_SIZE]    = 0x0C,
 295         [DMA_ARB_CTRL]          = 0x30,
 296         [DMA_PRIORITY_0]        = 0x34,
 297         [DMA_PRIORITY_1]        = 0x38,
 298         [DMA_PRIORITY_2]        = 0x3C,
 299         [DMA_RING0_TIMEOUT]     = 0x2C,
 300         [DMA_RING1_TIMEOUT]     = 0x30,
 301         [DMA_RING2_TIMEOUT]     = 0x34,
 302         [DMA_RING3_TIMEOUT]     = 0x38,
 303         [DMA_RING4_TIMEOUT]     = 0x3c,
 304         [DMA_RING5_TIMEOUT]     = 0x40,
 305         [DMA_RING6_TIMEOUT]     = 0x44,
 306         [DMA_RING7_TIMEOUT]     = 0x48,
 307         [DMA_RING8_TIMEOUT]     = 0x4c,
 308         [DMA_RING9_TIMEOUT]     = 0x50,
 309         [DMA_RING10_TIMEOUT]    = 0x54,
 310         [DMA_RING11_TIMEOUT]    = 0x58,
 311         [DMA_RING12_TIMEOUT]    = 0x5c,
 312         [DMA_RING13_TIMEOUT]    = 0x60,
 313         [DMA_RING14_TIMEOUT]    = 0x64,
 314         [DMA_RING15_TIMEOUT]    = 0x68,
 315         [DMA_RING16_TIMEOUT]    = 0x6C,
 316 };
 317
 318 /* Set at runtime once bcmgenet version is known */
 319 static const u8 *bcmgenet_dma_regs;
 320
 321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 322 {
 323         return netdev_priv(dev_get_drvdata(dev));
 324 }
 325
 326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 327                                       enum dma_reg r)
 328 {
 329         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 330                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 331 }
 332
 333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 334                                         u32 val, enum dma_reg r)
 335 {
 336         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 337                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 338 }
 339
 340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 341                                       enum dma_reg r)
 342 {
 343         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 344                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 345 }
 346
 347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 348                                         u32 val, enum dma_reg r)
 349 {
 350         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 351                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 352 }
 353
 354 /* RDMA/TDMA ring registers and accessors
 355  * we merge the common fields and just prefix with T/D the registers
 356  * having different meaning depending on the direction
 357  */
 358 enum dma_ring_reg {
 359         TDMA_READ_PTR = 0,
 360         RDMA_WRITE_PTR = TDMA_READ_PTR,
 361         TDMA_READ_PTR_HI,
 362         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 363         TDMA_CONS_INDEX,
 364         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 365         TDMA_PROD_INDEX,
 366         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 367         DMA_RING_BUF_SIZE,
 368         DMA_START_ADDR,
 369         DMA_START_ADDR_HI,
 370         DMA_END_ADDR,
 371         DMA_END_ADDR_HI,
 372         DMA_MBUF_DONE_THRESH,
 373         TDMA_FLOW_PERIOD,
 374         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 375         TDMA_WRITE_PTR,
 376         RDMA_READ_PTR = TDMA_WRITE_PTR,
 377         TDMA_WRITE_PTR_HI,
 378         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 379 };
 380
 381 /* GENET v4 supports 40-bits pointer addressing
 382  * for obvious reasons the LO and HI word parts
 383  * are contiguous, but this offsets the other
 384  * registers.
 385  */
 386 static const u8 genet_dma_ring_regs_v4[] = {
 387         [TDMA_READ_PTR]                 = 0x00,
 388         [TDMA_READ_PTR_HI]              = 0x04,
 389         [TDMA_CONS_INDEX]               = 0x08,
 390         [TDMA_PROD_INDEX]               = 0x0C,
 391         [DMA_RING_BUF_SIZE]             = 0x10,
 392         [DMA_START_ADDR]                = 0x14,
 393         [DMA_START_ADDR_HI]             = 0x18,
 394         [DMA_END_ADDR]                  = 0x1C,
 395         [DMA_END_ADDR_HI]               = 0x20,
 396         [DMA_MBUF_DONE_THRESH]          = 0x24,
 397         [TDMA_FLOW_PERIOD]              = 0x28,
 398         [TDMA_WRITE_PTR]                = 0x2C,
 399         [TDMA_WRITE_PTR_HI]             = 0x30,
 400 };
 401
 402 static const u8 genet_dma_ring_regs_v123[] = {
 403         [TDMA_READ_PTR]                 = 0x00,
 404         [TDMA_CONS_INDEX]               = 0x04,
 405         [TDMA_PROD_INDEX]               = 0x08,
 406         [DMA_RING_BUF_SIZE]             = 0x0C,
 407         [DMA_START_ADDR]                = 0x10,
 408         [DMA_END_ADDR]                  = 0x14,
 409         [DMA_MBUF_DONE_THRESH]          = 0x18,
 410         [TDMA_FLOW_PERIOD]              = 0x1C,
 411         [TDMA_WRITE_PTR]                = 0x20,
 412 };
 413
 414 /* Set at runtime once GENET version is known */
 415 static const u8 *genet_dma_ring_regs;
 416
 417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 418                                            unsigned int ring,
 419                                            enum dma_ring_reg r)
 420 {
 421         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 422                         (DMA_RING_SIZE * ring) +
 423                         genet_dma_ring_regs[r]);
 424 }
 425
 426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 427                                              unsigned int ring, u32 val,
 428                                              enum dma_ring_reg r)
 429 {
 430         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 431                         (DMA_RING_SIZE * ring) +
 432                         genet_dma_ring_regs[r]);
 433 }
 434
 435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 436                                            unsigned int ring,
 437                                            enum dma_ring_reg r)
 438 {
 439         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 440                         (DMA_RING_SIZE * ring) +
 441                         genet_dma_ring_regs[r]);
 442 }
 443
 444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 445                                              unsigned int ring, u32 val,
 446                                              enum dma_ring_reg r)
 447 {
 448         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 449                         (DMA_RING_SIZE * ring) +
 450                         genet_dma_ring_regs[r]);
 451 }
 452
 453 static int bcmgenet_get_settings(struct net_device *dev,
 454                                  struct ethtool_cmd *cmd)
 455 {
 456         struct bcmgenet_priv *priv = netdev_priv(dev);
 457
 458         if (!netif_running(dev))
 459                 return -EINVAL;
 460
 461         if (!priv->phydev)
 462                 return -ENODEV;
 463
 464         return phy_ethtool_gset(priv->phydev, cmd);
 465 }
 466
 467 static int bcmgenet_set_settings(struct net_device *dev,
 468                                  struct ethtool_cmd *cmd)
 469 {
 470         struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472         if (!netif_running(dev))
 473                 return -EINVAL;
 474
 475         if (!priv->phydev)
 476                 return -ENODEV;
 477
 478         return phy_ethtool_sset(priv->phydev, cmd);
 479 }
 480
 481 static int bcmgenet_set_rx_csum(struct net_device *dev,
 482                                 netdev_features_t wanted)
 483 {
 484         struct bcmgenet_priv *priv = netdev_priv(dev);
 485         u32 rbuf_chk_ctrl;
 486         bool rx_csum_en;
 487
 488         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 489
 490         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 491
 492         /* enable rx checksumming */
 493         if (rx_csum_en)
 494                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 495         else
 496                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 497         priv->desc_rxchk_en = rx_csum_en;
 498
 499         /* If UniMAC forwards CRC, we need to skip over it to get
 500          * a valid CHK bit to be set in the per-packet status word
 501         */
 502         if (rx_csum_en && priv->crc_fwd_en)
 503                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 504         else
 505                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 506
 507         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 508
 509         return 0;
 510 }
 511
 512 static int bcmgenet_set_tx_csum(struct net_device *dev,
 513                                 netdev_features_t wanted)
 514 {
 515         struct bcmgenet_priv *priv = netdev_priv(dev);
 516         bool desc_64b_en;
 517         u32 tbuf_ctrl, rbuf_ctrl;
 518
 519         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 520         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 521
 522         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 523
 524         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 525         if (desc_64b_en) {
 526                 tbuf_ctrl |= RBUF_64B_EN;
 527                 rbuf_ctrl |= RBUF_64B_EN;
 528         } else {
 529                 tbuf_ctrl &= ~RBUF_64B_EN;
 530                 rbuf_ctrl &= ~RBUF_64B_EN;
 531         }
 532         priv->desc_64b_en = desc_64b_en;
 533
 534         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 535         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 536
 537         return 0;
 538 }
 539
 540 static int bcmgenet_set_features(struct net_device *dev,
 541                                  netdev_features_t features)
 542 {
 543         netdev_features_t changed = features ^ dev->features;
 544         netdev_features_t wanted = dev->wanted_features;
 545         int ret = 0;
 546
 547         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 548                 ret = bcmgenet_set_tx_csum(dev, wanted);
 549         if (changed & (NETIF_F_RXCSUM))
 550                 ret = bcmgenet_set_rx_csum(dev, wanted);
 551
 552         return ret;
 553 }
 554
 555 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 556 {
 557         struct bcmgenet_priv *priv = netdev_priv(dev);
 558
 559         return priv->msg_enable;
 560 }
 561
 562 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 563 {
 564         struct bcmgenet_priv *priv = netdev_priv(dev);
 565
 566         priv->msg_enable = level;
 567 }
 568
 569 static int bcmgenet_get_coalesce(struct net_device *dev,
 570                                  struct ethtool_coalesce *ec)
 571 {
 572         struct bcmgenet_priv *priv = netdev_priv(dev);
 573
 574         ec->tx_max_coalesced_frames =
 575                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 576                                          DMA_MBUF_DONE_THRESH);
 577         ec->rx_max_coalesced_frames =
 578                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 579                                          DMA_MBUF_DONE_THRESH);
 580         ec->rx_coalesce_usecs =
 581                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 582
 583         return 0;
 584 }
 585
 586 static int bcmgenet_set_coalesce(struct net_device *dev,
 587                                  struct ethtool_coalesce *ec)
 588 {
 589         struct bcmgenet_priv *priv = netdev_priv(dev);
 590         unsigned int i;
 591         u32 reg;
 592
 593         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 594          * divided by 1024, which yields roughly 8.192us, our maximum value
 595          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 596          */
 597         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 598             ec->tx_max_coalesced_frames == 0 ||
 599             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 600             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 601                 return -EINVAL;
 602
 603         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 604                 return -EINVAL;
 605
 606         /* GENET TDMA hardware does not support a configurable timeout, but will
 607          * always generate an interrupt either after MBDONE packets have been
 608          * transmitted, or when the ring is emtpy.
 609          */
 610         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 611             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 612                 return -EOPNOTSUPP;
 613
 614         /* Program all TX queues with the same values, as there is no
 615          * ethtool knob to do coalescing on a per-queue basis
 616          */
 617         for (i = 0; i < priv->hw_params->tx_queues; i++)
 618                 bcmgenet_tdma_ring_writel(priv, i,
 619                                           ec->tx_max_coalesced_frames,
 620                                           DMA_MBUF_DONE_THRESH);
 621         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 622                                   ec->tx_max_coalesced_frames,
 623                                   DMA_MBUF_DONE_THRESH);
 624
 625         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 626                 bcmgenet_rdma_ring_writel(priv, i,
 627                                           ec->rx_max_coalesced_frames,
 628                                           DMA_MBUF_DONE_THRESH);
 629
 630                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 631                 reg &= ~DMA_TIMEOUT_MASK;
 632                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 633                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 634         }
 635
 636         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 637                                   ec->rx_max_coalesced_frames,
 638                                   DMA_MBUF_DONE_THRESH);
 639
 640         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 641         reg &= ~DMA_TIMEOUT_MASK;
 642         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 643         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 644
 645         return 0;
 646 }
 647
 648 /* standard ethtool support functions. */
 649 enum bcmgenet_stat_type {
 650         BCMGENET_STAT_NETDEV = -1,
 651         BCMGENET_STAT_MIB_RX,
 652         BCMGENET_STAT_MIB_TX,
 653         BCMGENET_STAT_RUNT,
 654         BCMGENET_STAT_MISC,
 655         BCMGENET_STAT_SOFT,
 656 };
 657
 658 struct bcmgenet_stats {
 659         char stat_string[ETH_GSTRING_LEN];
 660         int stat_sizeof;
 661         int stat_offset;
 662         enum bcmgenet_stat_type type;
 663         /* reg offset from UMAC base for misc counters */
 664         u16 reg_offset;
 665 };
 666
 667 #define STAT_NETDEV(m) { \
 668         .stat_string = __stringify(m), \
 669         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 670         .stat_offset = offsetof(struct net_device_stats, m), \
 671         .type = BCMGENET_STAT_NETDEV, \
 672 }
 673
 674 #define STAT_GENET_MIB(str, m, _type) { \
 675         .stat_string = str, \
 676         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 677         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 678         .type = _type, \
 679 }
 680
 681 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 682 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 683 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 684 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 685
 686 #define STAT_GENET_MISC(str, m, offset) { \
 687         .stat_string = str, \
 688         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 689         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 690         .type = BCMGENET_STAT_MISC, \
 691         .reg_offset = offset, \
 692 }
 693
 694
 695 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 696  * between the end of TX stats and the beginning of the RX RUNT
 697  */
 698 #define BCMGENET_STAT_OFFSET    0xc
 699
 700 /* Hardware counters must be kept in sync because the order/offset
 701  * is important here (order in structure declaration = order in hardware)
 702  */
 703 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 704         /* general stats */
 705         STAT_NETDEV(rx_packets),
 706         STAT_NETDEV(tx_packets),
 707         STAT_NETDEV(rx_bytes),
 708         STAT_NETDEV(tx_bytes),
 709         STAT_NETDEV(rx_errors),
 710         STAT_NETDEV(tx_errors),
 711         STAT_NETDEV(rx_dropped),
 712         STAT_NETDEV(tx_dropped),
 713         STAT_NETDEV(multicast),
 714         /* UniMAC RSV counters */
 715         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 716         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 717         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 718         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 719         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 720         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 721         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 722         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 723         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 724         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 725         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 726         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 727         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 728         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 729         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 730         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 731         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 732         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 733         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 734         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 735         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 736         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 737         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 738         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 739         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 740         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 741         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 742         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 743         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 744         /* UniMAC TSV counters */
 745         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 746         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 747         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 748         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 749         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 750         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 751         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 752         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 753         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 754         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 755         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 756         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 757         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 758         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 759         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 760         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 761         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 762         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 763         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 764         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 765         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 766         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 767         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 768         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 769         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 770         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 771         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 772         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 773         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 774         /* UniMAC RUNT counters */
 775         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 776         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 777         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 778         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 779         /* Misc UniMAC counters */
 780         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 781                         UMAC_RBUF_OVFL_CNT),
 782         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 783         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 784         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 785         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 786         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 787 };
 788
 789 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 790
 791 static void bcmgenet_get_drvinfo(struct net_device *dev,
 792                                  struct ethtool_drvinfo *info)
 793 {
 794         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 795         strlcpy(info->version, "v2.0", sizeof(info->version));
 796 }
 797
 798 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 799 {
 800         switch (string_set) {
 801         case ETH_SS_STATS:
 802                 return BCMGENET_STATS_LEN;
 803         default:
 804                 return -EOPNOTSUPP;
 805         }
 806 }
 807
 808 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 809                                  u8 *data)
 810 {
 811         int i;
 812
 813         switch (stringset) {
 814         case ETH_SS_STATS:
 815                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 816                         memcpy(data + i * ETH_GSTRING_LEN,
 817                                bcmgenet_gstrings_stats[i].stat_string,
 818                                ETH_GSTRING_LEN);
 819                 }
 820                 break;
 821         }
 822 }
 823
 824 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 825 {
 826         int i, j = 0;
 827
 828         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 829                 const struct bcmgenet_stats *s;
 830                 u8 offset = 0;
 831                 u32 val = 0;
 832                 char *p;
 833
 834                 s = &bcmgenet_gstrings_stats[i];
 835                 switch (s->type) {
 836                 case BCMGENET_STAT_NETDEV:
 837                 case BCMGENET_STAT_SOFT:
 838                         continue;
 839                 case BCMGENET_STAT_MIB_RX:
 840                 case BCMGENET_STAT_MIB_TX:
 841                 case BCMGENET_STAT_RUNT:
 842                         if (s->type != BCMGENET_STAT_MIB_RX)
 843                                 offset = BCMGENET_STAT_OFFSET;
 844                         val = bcmgenet_umac_readl(priv,
 845                                                   UMAC_MIB_START + j + offset);
 846                         break;
 847                 case BCMGENET_STAT_MISC:
 848                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 849                         /* clear if overflowed */
 850                         if (val == ~0)
 851                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 852                         break;
 853                 }
 854
 855                 j += s->stat_sizeof;
 856                 p = (char *)priv + s->stat_offset;
 857                 *(u32 *)p = val;
 858         }
 859 }
 860
 861 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 862                                        struct ethtool_stats *stats,
 863                                        u64 *data)
 864 {
 865         struct bcmgenet_priv *priv = netdev_priv(dev);
 866         int i;
 867
 868         if (netif_running(dev))
 869                 bcmgenet_update_mib_counters(priv);
 870
 871         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 872                 const struct bcmgenet_stats *s;
 873                 char *p;
 874
 875                 s = &bcmgenet_gstrings_stats[i];
 876                 if (s->type == BCMGENET_STAT_NETDEV)
 877                         p = (char *)&dev->stats;
 878                 else
 879                         p = (char *)priv;
 880                 p += s->stat_offset;
 881                 data[i] = *(u32 *)p;
 882         }
 883 }
 884
 885 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 886 {
 887         struct bcmgenet_priv *priv = netdev_priv(dev);
 888         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 889         u32 reg;
 890
 891         if (enable && !priv->clk_eee_enabled) {
 892                 clk_prepare_enable(priv->clk_eee);
 893                 priv->clk_eee_enabled = true;
 894         }
 895
 896         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 897         if (enable)
 898                 reg |= EEE_EN;
 899         else
 900                 reg &= ~EEE_EN;
 901         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 902
 903         /* Enable EEE and switch to a 27Mhz clock automatically */
 904         reg = __raw_readl(priv->base + off);
 905         if (enable)
 906                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 907         else
 908                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 909         __raw_writel(reg, priv->base + off);
 910
 911         /* Do the same for thing for RBUF */
 912         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 913         if (enable)
 914                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 915         else
 916                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 917         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 918
 919         if (!enable && priv->clk_eee_enabled) {
 920                 clk_disable_unprepare(priv->clk_eee);
 921                 priv->clk_eee_enabled = false;
 922         }
 923
 924         priv->eee.eee_enabled = enable;
 925         priv->eee.eee_active = enable;
 926 }
 927
 928 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 929 {
 930         struct bcmgenet_priv *priv = netdev_priv(dev);
 931         struct ethtool_eee *p = &priv->eee;
 932
 933         if (GENET_IS_V1(priv))
 934                 return -EOPNOTSUPP;
 935
 936         e->eee_enabled = p->eee_enabled;
 937         e->eee_active = p->eee_active;
 938         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 939
 940         return phy_ethtool_get_eee(priv->phydev, e);
 941 }
 942
 943 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 944 {
 945         struct bcmgenet_priv *priv = netdev_priv(dev);
 946         struct ethtool_eee *p = &priv->eee;
 947         int ret = 0;
 948
 949         if (GENET_IS_V1(priv))
 950                 return -EOPNOTSUPP;
 951
 952         p->eee_enabled = e->eee_enabled;
 953
 954         if (!p->eee_enabled) {
 955                 bcmgenet_eee_enable_set(dev, false);
 956         } else {
 957                 ret = phy_init_eee(priv->phydev, 0);
 958                 if (ret) {
 959                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 960                         return ret;
 961                 }
 962
 963                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 964                 bcmgenet_eee_enable_set(dev, true);
 965         }
 966
 967         return phy_ethtool_set_eee(priv->phydev, e);
 968 }
 969
 970 static int bcmgenet_nway_reset(struct net_device *dev)
 971 {
 972         struct bcmgenet_priv *priv = netdev_priv(dev);
 973
 974         return genphy_restart_aneg(priv->phydev);
 975 }
 976
 977 /* standard ethtool support functions. */
 978 static struct ethtool_ops bcmgenet_ethtool_ops = {
 979         .get_strings            = bcmgenet_get_strings,
 980         .get_sset_count         = bcmgenet_get_sset_count,
 981         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 982         .get_settings           = bcmgenet_get_settings,
 983         .set_settings           = bcmgenet_set_settings,
 984         .get_drvinfo            = bcmgenet_get_drvinfo,
 985         .get_link               = ethtool_op_get_link,
 986         .get_msglevel           = bcmgenet_get_msglevel,
 987         .set_msglevel           = bcmgenet_set_msglevel,
 988         .get_wol                = bcmgenet_get_wol,
 989         .set_wol                = bcmgenet_set_wol,
 990         .get_eee                = bcmgenet_get_eee,
 991         .set_eee                = bcmgenet_set_eee,
 992         .nway_reset             = bcmgenet_nway_reset,
 993         .get_coalesce           = bcmgenet_get_coalesce,
 994         .set_coalesce           = bcmgenet_set_coalesce,
 995 };
 996
 997 /* Power down the unimac, based on mode. */
 998 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
 999                                 enum bcmgenet_power_mode mode)
1000 {
1001         int ret = 0;
1002         u32 reg;
1003
1004         switch (mode) {
1005         case GENET_POWER_CABLE_SENSE:
1006                 phy_detach(priv->phydev);
1007                 break;
1008
1009         case GENET_POWER_WOL_MAGIC:
1010                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1011                 break;
1012
1013         case GENET_POWER_PASSIVE:
1014                 /* Power down LED */
1015                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1016                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1017                         reg |= (EXT_PWR_DOWN_PHY |
1018                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1019                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1020
1021                         bcmgenet_phy_power_set(priv->dev, false);
1022                 }
1023                 break;
1024         default:
1025                 break;
1026         }
1027
1028         return 0;
1029 }
1030
1031 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1032                               enum bcmgenet_power_mode mode)
1033 {
1034         u32 reg;
1035
1036         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1037                 return;
1038
1039         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1040
1041         switch (mode) {
1042         case GENET_POWER_PASSIVE:
1043                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1044                                 EXT_PWR_DOWN_BIAS);
1045                 /* fallthrough */
1046         case GENET_POWER_CABLE_SENSE:
1047                 /* enable APD */
1048                 reg |= EXT_PWR_DN_EN_LD;
1049                 break;
1050         case GENET_POWER_WOL_MAGIC:
1051                 bcmgenet_wol_power_up_cfg(priv, mode);
1052                 return;
1053         default:
1054                 break;
1055         }
1056
1057         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1058         if (mode == GENET_POWER_PASSIVE)
1059                 bcmgenet_phy_power_set(priv->dev, true);
1060 }
1061
1062 /* ioctl handle special commands that are not present in ethtool. */
1063 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1064 {
1065         struct bcmgenet_priv *priv = netdev_priv(dev);
1066         int val = 0;
1067
1068         if (!netif_running(dev))
1069                 return -EINVAL;
1070
1071         switch (cmd) {
1072         case SIOCGMIIPHY:
1073         case SIOCGMIIREG:
1074         case SIOCSMIIREG:
1075                 if (!priv->phydev)
1076                         val = -ENODEV;
1077                 else
1078                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
1079                 break;
1080
1081         default:
1082                 val = -EINVAL;
1083                 break;
1084         }
1085
1086         return val;
1087 }
1088
1089 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1090                                          struct bcmgenet_tx_ring *ring)
1091 {
1092         struct enet_cb *tx_cb_ptr;
1093
1094         tx_cb_ptr = ring->cbs;
1095         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1096
1097         /* Advancing local write pointer */
1098         if (ring->write_ptr == ring->end_ptr)
1099                 ring->write_ptr = ring->cb_ptr;
1100         else
1101                 ring->write_ptr++;
1102
1103         return tx_cb_ptr;
1104 }
1105
1106 /* Simple helper to free a control block's resources */
1107 static void bcmgenet_free_cb(struct enet_cb *cb)
1108 {
1109         dev_kfree_skb_any(cb->skb);
1110         cb->skb = NULL;
1111         dma_unmap_addr_set(cb, dma_addr, 0);
1112 }
1113
1114 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1115 {
1116         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1117                                  INTRL2_CPU_MASK_SET);
1118 }
1119
1120 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1121 {
1122         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1123                                  INTRL2_CPU_MASK_CLEAR);
1124 }
1125
1126 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1127 {
1128         bcmgenet_intrl2_1_writel(ring->priv,
1129                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1130                                  INTRL2_CPU_MASK_SET);
1131 }
1132
1133 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1134 {
1135         bcmgenet_intrl2_1_writel(ring->priv,
1136                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1137                                  INTRL2_CPU_MASK_CLEAR);
1138 }
1139
1140 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1141 {
1142         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1143                                  INTRL2_CPU_MASK_SET);
1144 }
1145
1146 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1147 {
1148         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1149                                  INTRL2_CPU_MASK_CLEAR);
1150 }
1151
1152 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1153 {
1154         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1155                                  INTRL2_CPU_MASK_CLEAR);
1156 }
1157
1158 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1159 {
1160         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1161                                  INTRL2_CPU_MASK_SET);
1162 }
1163
1164 /* Unlocked version of the reclaim routine */
1165 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1166                                           struct bcmgenet_tx_ring *ring)
1167 {
1168         struct bcmgenet_priv *priv = netdev_priv(dev);
1169         struct enet_cb *tx_cb_ptr;
1170         struct netdev_queue *txq;
1171         unsigned int pkts_compl = 0;
1172         unsigned int c_index;
1173         unsigned int txbds_ready;
1174         unsigned int txbds_processed = 0;
1175
1176         /* Compute how many buffers are transmitted since last xmit call */
1177         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1178         c_index &= DMA_C_INDEX_MASK;
1179
1180         if (likely(c_index >= ring->c_index))
1181                 txbds_ready = c_index - ring->c_index;
1182         else
1183                 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1184
1185         netif_dbg(priv, tx_done, dev,
1186                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1187                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1188
1189         /* Reclaim transmitted buffers */
1190         while (txbds_processed < txbds_ready) {
1191                 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1192                 if (tx_cb_ptr->skb) {
1193                         pkts_compl++;
1194                         dev->stats.tx_packets++;
1195                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1196                         dma_unmap_single(&dev->dev,
1197                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1198                                          tx_cb_ptr->skb->len,
1199                                          DMA_TO_DEVICE);
1200                         bcmgenet_free_cb(tx_cb_ptr);
1201                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1202                         dev->stats.tx_bytes +=
1203                                 dma_unmap_len(tx_cb_ptr, dma_len);
1204                         dma_unmap_page(&dev->dev,
1205                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1206                                        dma_unmap_len(tx_cb_ptr, dma_len),
1207                                        DMA_TO_DEVICE);
1208                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1209                 }
1210
1211                 txbds_processed++;
1212                 if (likely(ring->clean_ptr < ring->end_ptr))
1213                         ring->clean_ptr++;
1214                 else
1215                         ring->clean_ptr = ring->cb_ptr;
1216         }
1217
1218         ring->free_bds += txbds_processed;
1219         ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1220
1221         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1222                 txq = netdev_get_tx_queue(dev, ring->queue);
1223                 if (netif_tx_queue_stopped(txq))
1224                         netif_tx_wake_queue(txq);
1225         }
1226
1227         return pkts_compl;
1228 }
1229
1230 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1231                                 struct bcmgenet_tx_ring *ring)
1232 {
1233         unsigned int released;
1234         unsigned long flags;
1235
1236         spin_lock_irqsave(&ring->lock, flags);
1237         released = __bcmgenet_tx_reclaim(dev, ring);
1238         spin_unlock_irqrestore(&ring->lock, flags);
1239
1240         return released;
1241 }
1242
1243 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1244 {
1245         struct bcmgenet_tx_ring *ring =
1246                 container_of(napi, struct bcmgenet_tx_ring, napi);
1247         unsigned int work_done = 0;
1248
1249         work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1250
1251         if (work_done == 0) {
1252                 napi_complete(napi);
1253                 ring->int_enable(ring);
1254
1255                 return 0;
1256         }
1257
1258         return budget;
1259 }
1260
1261 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1262 {
1263         struct bcmgenet_priv *priv = netdev_priv(dev);
1264         int i;
1265
1266         if (netif_is_multiqueue(dev)) {
1267                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1268                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1269         }
1270
1271         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1272 }
1273
1274 /* Transmits a single SKB (either head of a fragment or a single SKB)
1275  * caller must hold priv->lock
1276  */
1277 static int bcmgenet_xmit_single(struct net_device *dev,
1278                                 struct sk_buff *skb,
1279                                 u16 dma_desc_flags,
1280                                 struct bcmgenet_tx_ring *ring)
1281 {
1282         struct bcmgenet_priv *priv = netdev_priv(dev);
1283         struct device *kdev = &priv->pdev->dev;
1284         struct enet_cb *tx_cb_ptr;
1285         unsigned int skb_len;
1286         dma_addr_t mapping;
1287         u32 length_status;
1288         int ret;
1289
1290         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1291
1292         if (unlikely(!tx_cb_ptr))
1293                 BUG();
1294
1295         tx_cb_ptr->skb = skb;
1296
1297         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1298
1299         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1300         ret = dma_mapping_error(kdev, mapping);
1301         if (ret) {
1302                 priv->mib.tx_dma_failed++;
1303                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1304                 dev_kfree_skb(skb);
1305                 return ret;
1306         }
1307
1308         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1309         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1310         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1311                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1312                         DMA_TX_APPEND_CRC;
1313
1314         if (skb->ip_summed == CHECKSUM_PARTIAL)
1315                 length_status |= DMA_TX_DO_CSUM;
1316
1317         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1318
1319         return 0;
1320 }
1321
1322 /* Transmit a SKB fragment */
1323 static int bcmgenet_xmit_frag(struct net_device *dev,
1324                               skb_frag_t *frag,
1325                               u16 dma_desc_flags,
1326                               struct bcmgenet_tx_ring *ring)
1327 {
1328         struct bcmgenet_priv *priv = netdev_priv(dev);
1329         struct device *kdev = &priv->pdev->dev;
1330         struct enet_cb *tx_cb_ptr;
1331         dma_addr_t mapping;
1332         int ret;
1333
1334         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1335
1336         if (unlikely(!tx_cb_ptr))
1337                 BUG();
1338         tx_cb_ptr->skb = NULL;
1339
1340         mapping = skb_frag_dma_map(kdev, frag, 0,
1341                                    skb_frag_size(frag), DMA_TO_DEVICE);
1342         ret = dma_mapping_error(kdev, mapping);
1343         if (ret) {
1344                 priv->mib.tx_dma_failed++;
1345                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1346                           __func__);
1347                 return ret;
1348         }
1349
1350         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1351         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1352
1353         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1354                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1355                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1356
1357         return 0;
1358 }
1359
1360 /* Reallocate the SKB to put enough headroom in front of it and insert
1361  * the transmit checksum offsets in the descriptors
1362  */
1363 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1364                                             struct sk_buff *skb)
1365 {
1366         struct status_64 *status = NULL;
1367         struct sk_buff *new_skb;
1368         u16 offset;
1369         u8 ip_proto;
1370         u16 ip_ver;
1371         u32 tx_csum_info;
1372
1373         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1374                 /* If 64 byte status block enabled, must make sure skb has
1375                  * enough headroom for us to insert 64B status block.
1376                  */
1377                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1378                 dev_kfree_skb(skb);
1379                 if (!new_skb) {
1380                         dev->stats.tx_dropped++;
1381                         return NULL;
1382                 }
1383                 skb = new_skb;
1384         }
1385
1386         skb_push(skb, sizeof(*status));
1387         status = (struct status_64 *)skb->data;
1388
1389         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1390                 ip_ver = htons(skb->protocol);
1391                 switch (ip_ver) {
1392                 case ETH_P_IP:
1393                         ip_proto = ip_hdr(skb)->protocol;
1394                         break;
1395                 case ETH_P_IPV6:
1396                         ip_proto = ipv6_hdr(skb)->nexthdr;
1397                         break;
1398                 default:
1399                         return skb;
1400                 }
1401
1402                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1403                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1404                                 (offset + skb->csum_offset);
1405
1406                 /* Set the length valid bit for TCP and UDP and just set
1407                  * the special UDP flag for IPv4, else just set to 0.
1408                  */
1409                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1410                         tx_csum_info |= STATUS_TX_CSUM_LV;
1411                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1412                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1413                 } else {
1414                         tx_csum_info = 0;
1415                 }
1416
1417                 status->tx_csum_info = tx_csum_info;
1418         }
1419
1420         return skb;
1421 }
1422
1423 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1424 {
1425         struct bcmgenet_priv *priv = netdev_priv(dev);
1426         struct bcmgenet_tx_ring *ring = NULL;
1427         struct netdev_queue *txq;
1428         unsigned long flags = 0;
1429         int nr_frags, index;
1430         u16 dma_desc_flags;
1431         int ret;
1432         int i;
1433
1434         index = skb_get_queue_mapping(skb);
1435         /* Mapping strategy:
1436          * queue_mapping = 0, unclassified, packet xmited through ring16
1437          * queue_mapping = 1, goes to ring 0. (highest priority queue
1438          * queue_mapping = 2, goes to ring 1.
1439          * queue_mapping = 3, goes to ring 2.
1440          * queue_mapping = 4, goes to ring 3.
1441          */
1442         if (index == 0)
1443                 index = DESC_INDEX;
1444         else
1445                 index -= 1;
1446
1447         nr_frags = skb_shinfo(skb)->nr_frags;
1448         ring = &priv->tx_rings[index];
1449         txq = netdev_get_tx_queue(dev, ring->queue);
1450
1451         spin_lock_irqsave(&ring->lock, flags);
1452         if (ring->free_bds <= nr_frags + 1) {
1453                 netif_tx_stop_queue(txq);
1454                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1455                            __func__, index, ring->queue);
1456                 ret = NETDEV_TX_BUSY;
1457                 goto out;
1458         }
1459
1460         if (skb_padto(skb, ETH_ZLEN)) {
1461                 ret = NETDEV_TX_OK;
1462                 goto out;
1463         }
1464
1465         /* set the SKB transmit checksum */
1466         if (priv->desc_64b_en) {
1467                 skb = bcmgenet_put_tx_csum(dev, skb);
1468                 if (!skb) {
1469                         ret = NETDEV_TX_OK;
1470                         goto out;
1471                 }
1472         }
1473
1474         dma_desc_flags = DMA_SOP;
1475         if (nr_frags == 0)
1476                 dma_desc_flags |= DMA_EOP;
1477
1478         /* Transmit single SKB or head of fragment list */
1479         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1480         if (ret) {
1481                 ret = NETDEV_TX_OK;
1482                 goto out;
1483         }
1484
1485         /* xmit fragment */
1486         for (i = 0; i < nr_frags; i++) {
1487                 ret = bcmgenet_xmit_frag(dev,
1488                                          &skb_shinfo(skb)->frags[i],
1489                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1490                                          ring);
1491                 if (ret) {
1492                         ret = NETDEV_TX_OK;
1493                         goto out;
1494                 }
1495         }
1496
1497         skb_tx_timestamp(skb);
1498
1499         /* Decrement total BD count and advance our write pointer */
1500         ring->free_bds -= nr_frags + 1;
1501         ring->prod_index += nr_frags + 1;
1502         ring->prod_index &= DMA_P_INDEX_MASK;
1503
1504         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1505                 netif_tx_stop_queue(txq);
1506
1507         if (!skb->xmit_more || netif_xmit_stopped(txq))
1508                 /* Packets are ready, update producer index */
1509                 bcmgenet_tdma_ring_writel(priv, ring->index,
1510                                           ring->prod_index, TDMA_PROD_INDEX);
1511 out:
1512         spin_unlock_irqrestore(&ring->lock, flags);
1513
1514         return ret;
1515 }
1516
1517 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1518                                           struct enet_cb *cb)
1519 {
1520         struct device *kdev = &priv->pdev->dev;
1521         struct sk_buff *skb;
1522         struct sk_buff *rx_skb;
1523         dma_addr_t mapping;
1524
1525         /* Allocate a new Rx skb */
1526         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1527         if (!skb) {
1528                 priv->mib.alloc_rx_buff_failed++;
1529                 netif_err(priv, rx_err, priv->dev,
1530                           "%s: Rx skb allocation failed\n", __func__);
1531                 return NULL;
1532         }
1533
1534         /* DMA-map the new Rx skb */
1535         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1536                                  DMA_FROM_DEVICE);
1537         if (dma_mapping_error(kdev, mapping)) {
1538                 priv->mib.rx_dma_failed++;
1539                 dev_kfree_skb_any(skb);
1540                 netif_err(priv, rx_err, priv->dev,
1541                           "%s: Rx skb DMA mapping failed\n", __func__);
1542                 return NULL;
1543         }
1544
1545         /* Grab the current Rx skb from the ring and DMA-unmap it */
1546         rx_skb = cb->skb;
1547         if (likely(rx_skb))
1548                 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1549                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1550
1551         /* Put the new Rx skb on the ring */
1552         cb->skb = skb;
1553         dma_unmap_addr_set(cb, dma_addr, mapping);
1554         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1555
1556         /* Return the current Rx skb to caller */
1557         return rx_skb;
1558 }
1559
1560 /* bcmgenet_desc_rx - descriptor based rx process.
1561  * this could be called from bottom half, or from NAPI polling method.
1562  */
1563 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1564                                      unsigned int budget)
1565 {
1566         struct bcmgenet_priv *priv = ring->priv;
1567         struct net_device *dev = priv->dev;
1568         struct enet_cb *cb;
1569         struct sk_buff *skb;
1570         u32 dma_length_status;
1571         unsigned long dma_flag;
1572         int len;
1573         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1574         unsigned int p_index;
1575         unsigned int discards;
1576         unsigned int chksum_ok = 0;
1577
1578         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1579
1580         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1581                    DMA_P_INDEX_DISCARD_CNT_MASK;
1582         if (discards > ring->old_discards) {
1583                 discards = discards - ring->old_discards;
1584                 dev->stats.rx_missed_errors += discards;
1585                 dev->stats.rx_errors += discards;
1586                 ring->old_discards += discards;
1587
1588                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1589                 if (ring->old_discards >= 0xC000) {
1590                         ring->old_discards = 0;
1591                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1592                                                   RDMA_PROD_INDEX);
1593                 }
1594         }
1595
1596         p_index &= DMA_P_INDEX_MASK;
1597
1598         if (likely(p_index >= ring->c_index))
1599                 rxpkttoprocess = p_index - ring->c_index;
1600         else
1601                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1602                                  p_index;
1603
1604         netif_dbg(priv, rx_status, dev,
1605                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1606
1607         while ((rxpktprocessed < rxpkttoprocess) &&
1608                (rxpktprocessed < budget)) {
1609                 cb = &priv->rx_cbs[ring->read_ptr];
1610                 skb = bcmgenet_rx_refill(priv, cb);
1611
1612                 if (unlikely(!skb)) {
1613                         dev->stats.rx_dropped++;
1614                         goto next;
1615                 }
1616
1617                 if (!priv->desc_64b_en) {
1618                         dma_length_status =
1619                                 dmadesc_get_length_status(priv, cb->bd_addr);
1620                 } else {
1621                         struct status_64 *status;
1622
1623                         status = (struct status_64 *)skb->data;
1624                         dma_length_status = status->length_status;
1625                 }
1626
1627                 /* DMA flags and length are still valid no matter how
1628                  * we got the Receive Status Vector (64B RSB or register)
1629                  */
1630                 dma_flag = dma_length_status & 0xffff;
1631                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1632
1633                 netif_dbg(priv, rx_status, dev,
1634                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1635                           __func__, p_index, ring->c_index,
1636                           ring->read_ptr, dma_length_status);
1637
1638                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1639                         netif_err(priv, rx_status, dev,
1640                                   "dropping fragmented packet!\n");
1641                         dev->stats.rx_errors++;
1642                         dev_kfree_skb_any(skb);
1643                         goto next;
1644                 }
1645
1646                 /* report errors */
1647                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1648                                                 DMA_RX_OV |
1649                                                 DMA_RX_NO |
1650                                                 DMA_RX_LG |
1651                                                 DMA_RX_RXER))) {
1652                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1653                                   (unsigned int)dma_flag);
1654                         if (dma_flag & DMA_RX_CRC_ERROR)
1655                                 dev->stats.rx_crc_errors++;
1656                         if (dma_flag & DMA_RX_OV)
1657                                 dev->stats.rx_over_errors++;
1658                         if (dma_flag & DMA_RX_NO)
1659                                 dev->stats.rx_frame_errors++;
1660                         if (dma_flag & DMA_RX_LG)
1661                                 dev->stats.rx_length_errors++;
1662                         dev->stats.rx_errors++;
1663                         dev_kfree_skb_any(skb);
1664                         goto next;
1665                 } /* error packet */
1666
1667                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1668                              priv->desc_rxchk_en;
1669
1670                 skb_put(skb, len);
1671                 if (priv->desc_64b_en) {
1672                         skb_pull(skb, 64);
1673                         len -= 64;
1674                 }
1675
1676                 if (likely(chksum_ok))
1677                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1678
1679                 /* remove hardware 2bytes added for IP alignment */
1680                 skb_pull(skb, 2);
1681                 len -= 2;
1682
1683                 if (priv->crc_fwd_en) {
1684                         skb_trim(skb, len - ETH_FCS_LEN);
1685                         len -= ETH_FCS_LEN;
1686                 }
1687
1688                 /*Finish setting up the received SKB and send it to the kernel*/
1689                 skb->protocol = eth_type_trans(skb, priv->dev);
1690                 dev->stats.rx_packets++;
1691                 dev->stats.rx_bytes += len;
1692                 if (dma_flag & DMA_RX_MULT)
1693                         dev->stats.multicast++;
1694
1695                 /* Notify kernel */
1696                 napi_gro_receive(&ring->napi, skb);
1697                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1698
1699 next:
1700                 rxpktprocessed++;
1701                 if (likely(ring->read_ptr < ring->end_ptr))
1702                         ring->read_ptr++;
1703                 else
1704                         ring->read_ptr = ring->cb_ptr;
1705
1706                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1707                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1708         }
1709
1710         return rxpktprocessed;
1711 }
1712
1713 /* Rx NAPI polling method */
1714 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1715 {
1716         struct bcmgenet_rx_ring *ring = container_of(napi,
1717                         struct bcmgenet_rx_ring, napi);
1718         unsigned int work_done;
1719
1720         work_done = bcmgenet_desc_rx(ring, budget);
1721
1722         if (work_done < budget) {
1723                 napi_complete(napi);
1724                 ring->int_enable(ring);
1725         }
1726
1727         return work_done;
1728 }
1729
1730 /* Assign skb to RX DMA descriptor. */
1731 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1732                                      struct bcmgenet_rx_ring *ring)
1733 {
1734         struct enet_cb *cb;
1735         struct sk_buff *skb;
1736         int i;
1737
1738         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1739
1740         /* loop here for each buffer needing assign */
1741         for (i = 0; i < ring->size; i++) {
1742                 cb = ring->cbs + i;
1743                 skb = bcmgenet_rx_refill(priv, cb);
1744                 if (skb)
1745                         dev_kfree_skb_any(skb);
1746                 if (!cb->skb)
1747                         return -ENOMEM;
1748         }
1749
1750         return 0;
1751 }
1752
1753 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1754 {
1755         struct enet_cb *cb;
1756         int i;
1757
1758         for (i = 0; i < priv->num_rx_bds; i++) {
1759                 cb = &priv->rx_cbs[i];
1760
1761                 if (dma_unmap_addr(cb, dma_addr)) {
1762                         dma_unmap_single(&priv->dev->dev,
1763                                          dma_unmap_addr(cb, dma_addr),
1764                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1765                         dma_unmap_addr_set(cb, dma_addr, 0);
1766                 }
1767
1768                 if (cb->skb)
1769                         bcmgenet_free_cb(cb);
1770         }
1771 }
1772
1773 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1774 {
1775         u32 reg;
1776
1777         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1778         if (enable)
1779                 reg |= mask;
1780         else
1781                 reg &= ~mask;
1782         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1783
1784         /* UniMAC stops on a packet boundary, wait for a full-size packet
1785          * to be processed
1786          */
1787         if (enable == 0)
1788                 usleep_range(1000, 2000);
1789 }
1790
1791 static int reset_umac(struct bcmgenet_priv *priv)
1792 {
1793         struct device *kdev = &priv->pdev->dev;
1794         unsigned int timeout = 0;
1795         u32 reg;
1796
1797         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1798         bcmgenet_rbuf_ctrl_set(priv, 0);
1799         udelay(10);
1800
1801         /* disable MAC while updating its registers */
1802         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1803
1804         /* issue soft reset, wait for it to complete */
1805         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1806         while (timeout++ < 1000) {
1807                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1808                 if (!(reg & CMD_SW_RESET))
1809                         return 0;
1810
1811                 udelay(1);
1812         }
1813
1814         if (timeout == 1000) {
1815                 dev_err(kdev,
1816                         "timeout waiting for MAC to come out of reset\n");
1817                 return -ETIMEDOUT;
1818         }
1819
1820         return 0;
1821 }
1822
1823 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1824 {
1825         /* Mask all interrupts.*/
1826         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1827         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1828         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1829         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1830         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1831         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1832 }
1833
1834 static int init_umac(struct bcmgenet_priv *priv)
1835 {
1836         struct device *kdev = &priv->pdev->dev;
1837         int ret;
1838         u32 reg;
1839         u32 int0_enable = 0;
1840         u32 int1_enable = 0;
1841         int i;
1842
1843         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1844
1845         ret = reset_umac(priv);
1846         if (ret)
1847                 return ret;
1848
1849         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1850         /* clear tx/rx counter */
1851         bcmgenet_umac_writel(priv,
1852                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1853                              UMAC_MIB_CTRL);
1854         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1855
1856         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1857
1858         /* init rx registers, enable ip header optimization */
1859         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1860         reg |= RBUF_ALIGN_2B;
1861         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1862
1863         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1864                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1865
1866         bcmgenet_intr_disable(priv);
1867
1868         /* Enable Rx default queue 16 interrupts */
1869         int0_enable |= UMAC_IRQ_RXDMA_DONE;
1870
1871         /* Enable Tx default queue 16 interrupts */
1872         int0_enable |= UMAC_IRQ_TXDMA_DONE;
1873
1874         /* Monitor cable plug/unplugged event for internal PHY */
1875         if (priv->internal_phy) {
1876                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1877         } else if (priv->ext_phy) {
1878                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1879         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1880                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1881                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1882
1883                 reg = bcmgenet_bp_mc_get(priv);
1884                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1885
1886                 /* bp_mask: back pressure mask */
1887                 if (netif_is_multiqueue(priv->dev))
1888                         reg |= priv->hw_params->bp_in_mask;
1889                 else
1890                         reg &= ~priv->hw_params->bp_in_mask;
1891                 bcmgenet_bp_mc_set(priv, reg);
1892         }
1893
1894         /* Enable MDIO interrupts on GENET v3+ */
1895         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1896                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1897
1898         /* Enable Rx priority queue interrupts */
1899         for (i = 0; i < priv->hw_params->rx_queues; ++i)
1900                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1901
1902         /* Enable Tx priority queue interrupts */
1903         for (i = 0; i < priv->hw_params->tx_queues; ++i)
1904                 int1_enable |= (1 << i);
1905
1906         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1907         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1908
1909         /* Enable rx/tx engine.*/
1910         dev_dbg(kdev, "done init umac\n");
1911
1912         return 0;
1913 }
1914
1915 /* Initialize a Tx ring along with corresponding hardware registers */
1916 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1917                                   unsigned int index, unsigned int size,
1918                                   unsigned int start_ptr, unsigned int end_ptr)
1919 {
1920         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1921         u32 words_per_bd = WORDS_PER_BD(priv);
1922         u32 flow_period_val = 0;
1923
1924         spin_lock_init(&ring->lock);
1925         ring->priv = priv;
1926         ring->index = index;
1927         if (index == DESC_INDEX) {
1928                 ring->queue = 0;
1929                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1930                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1931         } else {
1932                 ring->queue = index + 1;
1933                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1934                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1935         }
1936         ring->cbs = priv->tx_cbs + start_ptr;
1937         ring->size = size;
1938         ring->clean_ptr = start_ptr;
1939         ring->c_index = 0;
1940         ring->free_bds = size;
1941         ring->write_ptr = start_ptr;
1942         ring->cb_ptr = start_ptr;
1943         ring->end_ptr = end_ptr - 1;
1944         ring->prod_index = 0;
1945
1946         /* Set flow period for ring != 16 */
1947         if (index != DESC_INDEX)
1948                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1949
1950         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1951         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1952         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1953         /* Disable rate control for now */
1954         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1955                                   TDMA_FLOW_PERIOD);
1956         bcmgenet_tdma_ring_writel(priv, index,
1957                                   ((size << DMA_RING_SIZE_SHIFT) |
1958                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1959
1960         /* Set start and end address, read and write pointers */
1961         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1962                                   DMA_START_ADDR);
1963         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1964                                   TDMA_READ_PTR);
1965         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1966                                   TDMA_WRITE_PTR);
1967         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1968                                   DMA_END_ADDR);
1969 }
1970
1971 /* Initialize a RDMA ring */
1972 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1973                                  unsigned int index, unsigned int size,
1974                                  unsigned int start_ptr, unsigned int end_ptr)
1975 {
1976         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1977         u32 words_per_bd = WORDS_PER_BD(priv);
1978         int ret;
1979
1980         ring->priv = priv;
1981         ring->index = index;
1982         if (index == DESC_INDEX) {
1983                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1984                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1985         } else {
1986                 ring->int_enable = bcmgenet_rx_ring_int_enable;
1987                 ring->int_disable = bcmgenet_rx_ring_int_disable;
1988         }
1989         ring->cbs = priv->rx_cbs + start_ptr;
1990         ring->size = size;
1991         ring->c_index = 0;
1992         ring->read_ptr = start_ptr;
1993         ring->cb_ptr = start_ptr;
1994         ring->end_ptr = end_ptr - 1;
1995
1996         ret = bcmgenet_alloc_rx_buffers(priv, ring);
1997         if (ret)
1998                 return ret;
1999
2000         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2001         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2002         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2003         bcmgenet_rdma_ring_writel(priv, index,
2004                                   ((size << DMA_RING_SIZE_SHIFT) |
2005                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2006         bcmgenet_rdma_ring_writel(priv, index,
2007                                   (DMA_FC_THRESH_LO <<
2008                                    DMA_XOFF_THRESHOLD_SHIFT) |
2009                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2010
2011         /* Set start and end address, read and write pointers */
2012         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2013                                   DMA_START_ADDR);
2014         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2015                                   RDMA_READ_PTR);
2016         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2017                                   RDMA_WRITE_PTR);
2018         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2019                                   DMA_END_ADDR);
2020
2021         return ret;
2022 }
2023
2024 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2025 {
2026         unsigned int i;
2027         struct bcmgenet_tx_ring *ring;
2028
2029         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2030                 ring = &priv->tx_rings[i];
2031                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2032         }
2033
2034         ring = &priv->tx_rings[DESC_INDEX];
2035         netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2036 }
2037
2038 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2039 {
2040         unsigned int i;
2041         struct bcmgenet_tx_ring *ring;
2042
2043         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2044                 ring = &priv->tx_rings[i];
2045                 napi_enable(&ring->napi);
2046         }
2047
2048         ring = &priv->tx_rings[DESC_INDEX];
2049         napi_enable(&ring->napi);
2050 }
2051
2052 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2053 {
2054         unsigned int i;
2055         struct bcmgenet_tx_ring *ring;
2056
2057         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2058                 ring = &priv->tx_rings[i];
2059                 napi_disable(&ring->napi);
2060         }
2061
2062         ring = &priv->tx_rings[DESC_INDEX];
2063         napi_disable(&ring->napi);
2064 }
2065
2066 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2067 {
2068         unsigned int i;
2069         struct bcmgenet_tx_ring *ring;
2070
2071         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2072                 ring = &priv->tx_rings[i];
2073                 netif_napi_del(&ring->napi);
2074         }
2075
2076         ring = &priv->tx_rings[DESC_INDEX];
2077         netif_napi_del(&ring->napi);
2078 }
2079
2080 /* Initialize Tx queues
2081  *
2082  * Queues 0-3 are priority-based, each one has 32 descriptors,
2083  * with queue 0 being the highest priority queue.
2084  *
2085  * Queue 16 is the default Tx queue with
2086  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2087  *
2088  * The transmit control block pool is then partitioned as follows:
2089  * - Tx queue 0 uses tx_cbs[0..31]
2090  * - Tx queue 1 uses tx_cbs[32..63]
2091  * - Tx queue 2 uses tx_cbs[64..95]
2092  * - Tx queue 3 uses tx_cbs[96..127]
2093  * - Tx queue 16 uses tx_cbs[128..255]
2094  */
2095 static void bcmgenet_init_tx_queues(struct net_device *dev)
2096 {
2097         struct bcmgenet_priv *priv = netdev_priv(dev);
2098         u32 i, dma_enable;
2099         u32 dma_ctrl, ring_cfg;
2100         u32 dma_priority[3] = {0, 0, 0};
2101
2102         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2103         dma_enable = dma_ctrl & DMA_EN;
2104         dma_ctrl &= ~DMA_EN;
2105         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2106
2107         dma_ctrl = 0;
2108         ring_cfg = 0;
2109
2110         /* Enable strict priority arbiter mode */
2111         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2112
2113         /* Initialize Tx priority queues */
2114         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2115                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2116                                       i * priv->hw_params->tx_bds_per_q,
2117                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2118                 ring_cfg |= (1 << i);
2119                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2120                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2121                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2122         }
2123
2124         /* Initialize Tx default queue 16 */
2125         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2126                               priv->hw_params->tx_queues *
2127                               priv->hw_params->tx_bds_per_q,
2128                               TOTAL_DESC);
2129         ring_cfg |= (1 << DESC_INDEX);
2130         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2131         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2132                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2133                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2134
2135         /* Set Tx queue priorities */
2136         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2137         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2138         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2139
2140         /* Initialize Tx NAPI */
2141         bcmgenet_init_tx_napi(priv);
2142
2143         /* Enable Tx queues */
2144         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2145
2146         /* Enable Tx DMA */
2147         if (dma_enable)
2148                 dma_ctrl |= DMA_EN;
2149         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2150 }
2151
2152 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2153 {
2154         unsigned int i;
2155         struct bcmgenet_rx_ring *ring;
2156
2157         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2158                 ring = &priv->rx_rings[i];
2159                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2160         }
2161
2162         ring = &priv->rx_rings[DESC_INDEX];
2163         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2164 }
2165
2166 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2167 {
2168         unsigned int i;
2169         struct bcmgenet_rx_ring *ring;
2170
2171         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2172                 ring = &priv->rx_rings[i];
2173                 napi_enable(&ring->napi);
2174         }
2175
2176         ring = &priv->rx_rings[DESC_INDEX];
2177         napi_enable(&ring->napi);
2178 }
2179
2180 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2181 {
2182         unsigned int i;
2183         struct bcmgenet_rx_ring *ring;
2184
2185         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2186                 ring = &priv->rx_rings[i];
2187                 napi_disable(&ring->napi);
2188         }
2189
2190         ring = &priv->rx_rings[DESC_INDEX];
2191         napi_disable(&ring->napi);
2192 }
2193
2194 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2195 {
2196         unsigned int i;
2197         struct bcmgenet_rx_ring *ring;
2198
2199         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2200                 ring = &priv->rx_rings[i];
2201                 netif_napi_del(&ring->napi);
2202         }
2203
2204         ring = &priv->rx_rings[DESC_INDEX];
2205         netif_napi_del(&ring->napi);
2206 }
2207
2208 /* Initialize Rx queues
2209  *
2210  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2211  * used to direct traffic to these queues.
2212  *
2213  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2214  */
2215 static int bcmgenet_init_rx_queues(struct net_device *dev)
2216 {
2217         struct bcmgenet_priv *priv = netdev_priv(dev);
2218         u32 i;
2219         u32 dma_enable;
2220         u32 dma_ctrl;
2221         u32 ring_cfg;
2222         int ret;
2223
2224         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2225         dma_enable = dma_ctrl & DMA_EN;
2226         dma_ctrl &= ~DMA_EN;
2227         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2228
2229         dma_ctrl = 0;
2230         ring_cfg = 0;
2231
2232         /* Initialize Rx priority queues */
2233         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2234                 ret = bcmgenet_init_rx_ring(priv, i,
2235                                             priv->hw_params->rx_bds_per_q,
2236                                             i * priv->hw_params->rx_bds_per_q,
2237                                             (i + 1) *
2238                                             priv->hw_params->rx_bds_per_q);
2239                 if (ret)
2240                         return ret;
2241
2242                 ring_cfg |= (1 << i);
2243                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2244         }
2245
2246         /* Initialize Rx default queue 16 */
2247         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2248                                     priv->hw_params->rx_queues *
2249                                     priv->hw_params->rx_bds_per_q,
2250                                     TOTAL_DESC);
2251         if (ret)
2252                 return ret;
2253
2254         ring_cfg |= (1 << DESC_INDEX);
2255         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2256
2257         /* Initialize Rx NAPI */
2258         bcmgenet_init_rx_napi(priv);
2259
2260         /* Enable rings */
2261         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2262
2263         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2264         if (dma_enable)
2265                 dma_ctrl |= DMA_EN;
2266         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2267
2268         return 0;
2269 }
2270
2271 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2272 {
2273         int ret = 0;
2274         int timeout = 0;
2275         u32 reg;
2276         u32 dma_ctrl;
2277         int i;
2278
2279         /* Disable TDMA to stop add more frames in TX DMA */
2280         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2281         reg &= ~DMA_EN;
2282         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2283
2284         /* Check TDMA status register to confirm TDMA is disabled */
2285         while (timeout++ < DMA_TIMEOUT_VAL) {
2286                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2287                 if (reg & DMA_DISABLED)
2288                         break;
2289
2290                 udelay(1);
2291         }
2292
2293         if (timeout == DMA_TIMEOUT_VAL) {
2294                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2295                 ret = -ETIMEDOUT;
2296         }
2297
2298         /* Wait 10ms for packet drain in both tx and rx dma */
2299         usleep_range(10000, 20000);
2300
2301         /* Disable RDMA */
2302         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2303         reg &= ~DMA_EN;
2304         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2305
2306         timeout = 0;
2307         /* Check RDMA status register to confirm RDMA is disabled */
2308         while (timeout++ < DMA_TIMEOUT_VAL) {
2309                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2310                 if (reg & DMA_DISABLED)
2311                         break;
2312
2313                 udelay(1);
2314         }
2315
2316         if (timeout == DMA_TIMEOUT_VAL) {
2317                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2318                 ret = -ETIMEDOUT;
2319         }
2320
2321         dma_ctrl = 0;
2322         for (i = 0; i < priv->hw_params->rx_queues; i++)
2323                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2324         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2325         reg &= ~dma_ctrl;
2326         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2327
2328         dma_ctrl = 0;
2329         for (i = 0; i < priv->hw_params->tx_queues; i++)
2330                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2331         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2332         reg &= ~dma_ctrl;
2333         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2334
2335         return ret;
2336 }
2337
2338 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2339 {
2340         int i;
2341
2342         bcmgenet_fini_rx_napi(priv);
2343         bcmgenet_fini_tx_napi(priv);
2344
2345         /* disable DMA */
2346         bcmgenet_dma_teardown(priv);
2347
2348         for (i = 0; i < priv->num_tx_bds; i++) {
2349                 if (priv->tx_cbs[i].skb != NULL) {
2350                         dev_kfree_skb(priv->tx_cbs[i].skb);
2351                         priv->tx_cbs[i].skb = NULL;
2352                 }
2353         }
2354
2355         bcmgenet_free_rx_buffers(priv);
2356         kfree(priv->rx_cbs);
2357         kfree(priv->tx_cbs);
2358 }
2359
2360 /* init_edma: Initialize DMA control register */
2361 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2362 {
2363         int ret;
2364         unsigned int i;
2365         struct enet_cb *cb;
2366
2367         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2368
2369         /* Initialize common Rx ring structures */
2370         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2371         priv->num_rx_bds = TOTAL_DESC;
2372         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2373                                GFP_KERNEL);
2374         if (!priv->rx_cbs)
2375                 return -ENOMEM;
2376
2377         for (i = 0; i < priv->num_rx_bds; i++) {
2378                 cb = priv->rx_cbs + i;
2379                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2380         }
2381
2382         /* Initialize common TX ring structures */
2383         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2384         priv->num_tx_bds = TOTAL_DESC;
2385         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2386                                GFP_KERNEL);
2387         if (!priv->tx_cbs) {
2388                 kfree(priv->rx_cbs);
2389                 return -ENOMEM;
2390         }
2391
2392         for (i = 0; i < priv->num_tx_bds; i++) {
2393                 cb = priv->tx_cbs + i;
2394                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2395         }
2396
2397         /* Init rDma */
2398         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2399
2400         /* Initialize Rx queues */
2401         ret = bcmgenet_init_rx_queues(priv->dev);
2402         if (ret) {
2403                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2404                 bcmgenet_free_rx_buffers(priv);
2405                 kfree(priv->rx_cbs);
2406                 kfree(priv->tx_cbs);
2407                 return ret;
2408         }
2409
2410         /* Init tDma */
2411         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2412
2413         /* Initialize Tx queues */
2414         bcmgenet_init_tx_queues(priv->dev);
2415
2416         return 0;
2417 }
2418
2419 /* Interrupt bottom half */
2420 static void bcmgenet_irq_task(struct work_struct *work)
2421 {
2422         struct bcmgenet_priv *priv = container_of(
2423                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2424
2425         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2426
2427         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2428                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2429                 netif_dbg(priv, wol, priv->dev,
2430                           "magic packet detected, waking up\n");
2431                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2432         }
2433
2434         /* Link UP/DOWN event */
2435         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2436             (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
2437                 phy_mac_interrupt(priv->phydev,
2438                                   !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2439                 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2440         }
2441 }
2442
2443 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2444 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2445 {
2446         struct bcmgenet_priv *priv = dev_id;
2447         struct bcmgenet_rx_ring *rx_ring;
2448         struct bcmgenet_tx_ring *tx_ring;
2449         unsigned int index;
2450
2451         /* Save irq status for bottom-half processing. */
2452         priv->irq1_stat =
2453                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2454                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2455
2456         /* clear interrupts */
2457         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2458
2459         netif_dbg(priv, intr, priv->dev,
2460                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2461
2462         /* Check Rx priority queue interrupts */
2463         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2464                 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2465                         continue;
2466
2467                 rx_ring = &priv->rx_rings[index];
2468
2469                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2470                         rx_ring->int_disable(rx_ring);
2471                         __napi_schedule(&rx_ring->napi);
2472                 }
2473         }
2474
2475         /* Check Tx priority queue interrupts */
2476         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2477                 if (!(priv->irq1_stat & BIT(index)))
2478                         continue;
2479
2480                 tx_ring = &priv->tx_rings[index];
2481
2482                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2483                         tx_ring->int_disable(tx_ring);
2484                         __napi_schedule(&tx_ring->napi);
2485                 }
2486         }
2487
2488         return IRQ_HANDLED;
2489 }
2490
2491 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2492 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2493 {
2494         struct bcmgenet_priv *priv = dev_id;
2495         struct bcmgenet_rx_ring *rx_ring;
2496         struct bcmgenet_tx_ring *tx_ring;
2497
2498         /* Save irq status for bottom-half processing. */
2499         priv->irq0_stat =
2500                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2501                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2502
2503         /* clear interrupts */
2504         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2505
2506         netif_dbg(priv, intr, priv->dev,
2507                   "IRQ=0x%x\n", priv->irq0_stat);
2508
2509         if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2510                 rx_ring = &priv->rx_rings[DESC_INDEX];
2511
2512                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2513                         rx_ring->int_disable(rx_ring);
2514                         __napi_schedule(&rx_ring->napi);
2515                 }
2516         }
2517
2518         if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2519                 tx_ring = &priv->tx_rings[DESC_INDEX];
2520
2521                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2522                         tx_ring->int_disable(tx_ring);
2523                         __napi_schedule(&tx_ring->napi);
2524                 }
2525         }
2526
2527         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2528                                 UMAC_IRQ_PHY_DET_F |
2529                                 UMAC_IRQ_LINK_EVENT |
2530                                 UMAC_IRQ_HFB_SM |
2531                                 UMAC_IRQ_HFB_MM |
2532                                 UMAC_IRQ_MPD_R)) {
2533                 /* all other interested interrupts handled in bottom half */
2534                 schedule_work(&priv->bcmgenet_irq_work);
2535         }
2536
2537         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2538             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2539                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2540                 wake_up(&priv->wq);
2541         }
2542
2543         return IRQ_HANDLED;
2544 }
2545
2546 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2547 {
2548         struct bcmgenet_priv *priv = dev_id;
2549
2550         pm_wakeup_event(&priv->pdev->dev, 0);
2551
2552         return IRQ_HANDLED;
2553 }
2554
2555 #ifdef CONFIG_NET_POLL_CONTROLLER
2556 static void bcmgenet_poll_controller(struct net_device *dev)
2557 {
2558         struct bcmgenet_priv *priv = netdev_priv(dev);
2559
2560         /* Invoke the main RX/TX interrupt handler */
2561         disable_irq(priv->irq0);
2562         bcmgenet_isr0(priv->irq0, priv);
2563         enable_irq(priv->irq0);
2564
2565         /* And the interrupt handler for RX/TX priority queues */
2566         disable_irq(priv->irq1);
2567         bcmgenet_isr1(priv->irq1, priv);
2568         enable_irq(priv->irq1);
2569 }
2570 #endif
2571
2572 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2573 {
2574         u32 reg;
2575
2576         reg = bcmgenet_rbuf_ctrl_get(priv);
2577         reg |= BIT(1);
2578         bcmgenet_rbuf_ctrl_set(priv, reg);
2579         udelay(10);
2580
2581         reg &= ~BIT(1);
2582         bcmgenet_rbuf_ctrl_set(priv, reg);
2583         udelay(10);
2584 }
2585
2586 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2587                                  unsigned char *addr)
2588 {
2589         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2590                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2591         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2592 }
2593
2594 /* Returns a reusable dma control register value */
2595 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2596 {
2597         u32 reg;
2598         u32 dma_ctrl;
2599
2600         /* disable DMA */
2601         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2602         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2603         reg &= ~dma_ctrl;
2604         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2605
2606         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2607         reg &= ~dma_ctrl;
2608         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2609
2610         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2611         udelay(10);
2612         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2613
2614         return dma_ctrl;
2615 }
2616
2617 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2618 {
2619         u32 reg;
2620
2621         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2622         reg |= dma_ctrl;
2623         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2624
2625         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2626         reg |= dma_ctrl;
2627         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2628 }
2629
2630 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2631                                            u32 f_index)
2632 {
2633         u32 offset;
2634         u32 reg;
2635
2636         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2637         reg = bcmgenet_hfb_reg_readl(priv, offset);
2638         return !!(reg & (1 << (f_index % 32)));
2639 }
2640
2641 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2642 {
2643         u32 offset;
2644         u32 reg;
2645
2646         offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2647         reg = bcmgenet_hfb_reg_readl(priv, offset);
2648         reg |= (1 << (f_index % 32));
2649         bcmgenet_hfb_reg_writel(priv, reg, offset);
2650 }
2651
2652 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2653                                                      u32 f_index, u32 rx_queue)
2654 {
2655         u32 offset;
2656         u32 reg;
2657
2658         offset = f_index / 8;
2659         reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2660         reg &= ~(0xF << (4 * (f_index % 8)));
2661         reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2662         bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2663 }
2664
2665 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2666                                            u32 f_index, u32 f_length)
2667 {
2668         u32 offset;
2669         u32 reg;
2670
2671         offset = HFB_FLT_LEN_V3PLUS +
2672                  ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2673                  sizeof(u32);
2674         reg = bcmgenet_hfb_reg_readl(priv, offset);
2675         reg &= ~(0xFF << (8 * (f_index % 4)));
2676         reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2677         bcmgenet_hfb_reg_writel(priv, reg, offset);
2678 }
2679
2680 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2681 {
2682         u32 f_index;
2683
2684         for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2685                 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2686                         return f_index;
2687
2688         return -ENOMEM;
2689 }
2690
2691 /* bcmgenet_hfb_add_filter
2692  *
2693  * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2694  * desired Rx queue.
2695  *
2696  * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2697  * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2698  *
2699  * bits 31:20 - unused
2700  * bit  19    - nibble 0 match enable
2701  * bit  18    - nibble 1 match enable
2702  * bit  17    - nibble 2 match enable
2703  * bit  16    - nibble 3 match enable
2704  * bits 15:12 - nibble 0 data
2705  * bits 11:8  - nibble 1 data
2706  * bits 7:4   - nibble 2 data
2707  * bits 3:0   - nibble 3 data
2708  *
2709  * Example:
2710  * In order to match:
2711  * - Ethernet frame type = 0x0800 (IP)
2712  * - IP version field = 4
2713  * - IP protocol field = 0x11 (UDP)
2714  *
2715  * The following filter is needed:
2716  * u32 hfb_filter_ipv4_udp[] = {
2717  *   Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2718  *   Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2719  *   Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2720  * };
2721  *
2722  * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2723  * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2724  *                         ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2725  */
2726 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2727                             u32 f_length, u32 rx_queue)
2728 {
2729         int f_index;
2730         u32 i;
2731
2732         f_index = bcmgenet_hfb_find_unused_filter(priv);
2733         if (f_index < 0)
2734                 return -ENOMEM;
2735
2736         if (f_length > priv->hw_params->hfb_filter_size)
2737                 return -EINVAL;
2738
2739         for (i = 0; i < f_length; i++)
2740                 bcmgenet_hfb_writel(priv, f_data[i],
2741                         (f_index * priv->hw_params->hfb_filter_size + i) *
2742                         sizeof(u32));
2743
2744         bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2745         bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2746         bcmgenet_hfb_enable_filter(priv, f_index);
2747         bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2748
2749         return 0;
2750 }
2751
2752 /* bcmgenet_hfb_clear
2753  *
2754  * Clear Hardware Filter Block and disable all filtering.
2755  */
2756 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2757 {
2758         u32 i;
2759
2760         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2761         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2762         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2763
2764         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2765                 bcmgenet_rdma_writel(priv, 0x0, i);
2766
2767         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2768                 bcmgenet_hfb_reg_writel(priv, 0x0,
2769                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2770
2771         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2772                         priv->hw_params->hfb_filter_size; i++)
2773                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2774 }
2775
2776 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2777 {
2778         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2779                 return;
2780
2781         bcmgenet_hfb_clear(priv);
2782 }
2783
2784 static void bcmgenet_netif_start(struct net_device *dev)
2785 {
2786         struct bcmgenet_priv *priv = netdev_priv(dev);
2787
2788         /* Start the network engine */
2789         bcmgenet_enable_rx_napi(priv);
2790         bcmgenet_enable_tx_napi(priv);
2791
2792         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2793
2794         netif_tx_start_all_queues(dev);
2795
2796         phy_start(priv->phydev);
2797 }
2798
2799 static int bcmgenet_open(struct net_device *dev)
2800 {
2801         struct bcmgenet_priv *priv = netdev_priv(dev);
2802         unsigned long dma_ctrl;
2803         u32 reg;
2804         int ret;
2805
2806         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2807
2808         /* Turn on the clock */
2809         clk_prepare_enable(priv->clk);
2810
2811         /* If this is an internal GPHY, power it back on now, before UniMAC is
2812          * brought out of reset as absolutely no UniMAC activity is allowed
2813          */
2814         if (priv->internal_phy)
2815                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2816
2817         /* take MAC out of reset */
2818         bcmgenet_umac_reset(priv);
2819
2820         ret = init_umac(priv);
2821         if (ret)
2822                 goto err_clk_disable;
2823
2824         /* disable ethernet MAC while updating its registers */
2825         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2826
2827         /* Make sure we reflect the value of CRC_CMD_FWD */
2828         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2829         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2830
2831         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2832
2833         if (priv->internal_phy) {
2834                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2835                 reg |= EXT_ENERGY_DET_MASK;
2836                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2837         }
2838
2839         /* Disable RX/TX DMA and flush TX queues */
2840         dma_ctrl = bcmgenet_dma_disable(priv);
2841
2842         /* Reinitialize TDMA and RDMA and SW housekeeping */
2843         ret = bcmgenet_init_dma(priv);
2844         if (ret) {
2845                 netdev_err(dev, "failed to initialize DMA\n");
2846                 goto err_clk_disable;
2847         }
2848
2849         /* Always enable ring 16 - descriptor ring */
2850         bcmgenet_enable_dma(priv, dma_ctrl);
2851
2852         /* HFB init */
2853         bcmgenet_hfb_init(priv);
2854
2855         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2856                           dev->name, priv);
2857         if (ret < 0) {
2858                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2859                 goto err_fini_dma;
2860         }
2861
2862         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2863                           dev->name, priv);
2864         if (ret < 0) {
2865                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2866                 goto err_irq0;
2867         }
2868
2869         ret = bcmgenet_mii_probe(dev);
2870         if (ret) {
2871                 netdev_err(dev, "failed to connect to PHY\n");
2872                 goto err_irq1;
2873         }
2874
2875         bcmgenet_netif_start(dev);
2876
2877         return 0;
2878
2879 err_irq1:
2880         free_irq(priv->irq1, priv);
2881 err_irq0:
2882         free_irq(priv->irq0, priv);
2883 err_fini_dma:
2884         bcmgenet_fini_dma(priv);
2885 err_clk_disable:
2886         clk_disable_unprepare(priv->clk);
2887         return ret;
2888 }
2889
2890 static void bcmgenet_netif_stop(struct net_device *dev)
2891 {
2892         struct bcmgenet_priv *priv = netdev_priv(dev);
2893
2894         netif_tx_stop_all_queues(dev);
2895         phy_stop(priv->phydev);
2896         bcmgenet_intr_disable(priv);
2897         bcmgenet_disable_rx_napi(priv);
2898         bcmgenet_disable_tx_napi(priv);
2899
2900         /* Wait for pending work items to complete. Since interrupts are
2901          * disabled no new work will be scheduled.
2902          */
2903         cancel_work_sync(&priv->bcmgenet_irq_work);
2904
2905         priv->old_link = -1;
2906         priv->old_speed = -1;
2907         priv->old_duplex = -1;
2908         priv->old_pause = -1;
2909 }
2910
2911 static int bcmgenet_close(struct net_device *dev)
2912 {
2913         struct bcmgenet_priv *priv = netdev_priv(dev);
2914         int ret;
2915
2916         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2917
2918         bcmgenet_netif_stop(dev);
2919
2920         /* Really kill the PHY state machine and disconnect from it */
2921         phy_disconnect(priv->phydev);
2922
2923         /* Disable MAC receive */
2924         umac_enable_set(priv, CMD_RX_EN, false);
2925
2926         ret = bcmgenet_dma_teardown(priv);
2927         if (ret)
2928                 return ret;
2929
2930         /* Disable MAC transmit. TX DMA disabled have to done before this */
2931         umac_enable_set(priv, CMD_TX_EN, false);
2932
2933         /* tx reclaim */
2934         bcmgenet_tx_reclaim_all(dev);
2935         bcmgenet_fini_dma(priv);
2936
2937         free_irq(priv->irq0, priv);
2938         free_irq(priv->irq1, priv);
2939
2940         if (priv->internal_phy)
2941                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2942
2943         clk_disable_unprepare(priv->clk);
2944
2945         return ret;
2946 }
2947
2948 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2949 {
2950         struct bcmgenet_priv *priv = ring->priv;
2951         u32 p_index, c_index, intsts, intmsk;
2952         struct netdev_queue *txq;
2953         unsigned int free_bds;
2954         unsigned long flags;
2955         bool txq_stopped;
2956
2957         if (!netif_msg_tx_err(priv))
2958                 return;
2959
2960         txq = netdev_get_tx_queue(priv->dev, ring->queue);
2961
2962         spin_lock_irqsave(&ring->lock, flags);
2963         if (ring->index == DESC_INDEX) {
2964                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2965                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2966         } else {
2967                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2968                 intmsk = 1 << ring->index;
2969         }
2970         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2971         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2972         txq_stopped = netif_tx_queue_stopped(txq);
2973         free_bds = ring->free_bds;
2974         spin_unlock_irqrestore(&ring->lock, flags);
2975
2976         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2977                   "TX queue status: %s, interrupts: %s\n"
2978                   "(sw)free_bds: %d (sw)size: %d\n"
2979                   "(sw)p_index: %d (hw)p_index: %d\n"
2980                   "(sw)c_index: %d (hw)c_index: %d\n"
2981                   "(sw)clean_p: %d (sw)write_p: %d\n"
2982                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2983                   ring->index, ring->queue,
2984                   txq_stopped ? "stopped" : "active",
2985                   intsts & intmsk ? "enabled" : "disabled",
2986                   free_bds, ring->size,
2987                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
2988                   ring->c_index, c_index & DMA_C_INDEX_MASK,
2989                   ring->clean_ptr, ring->write_ptr,
2990                   ring->cb_ptr, ring->end_ptr);
2991 }
2992
2993 static void bcmgenet_timeout(struct net_device *dev)
2994 {
2995         struct bcmgenet_priv *priv = netdev_priv(dev);
2996         u32 int0_enable = 0;
2997         u32 int1_enable = 0;
2998         unsigned int q;
2999
3000         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3001
3002         for (q = 0; q < priv->hw_params->tx_queues; q++)
3003                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3004         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3005
3006         bcmgenet_tx_reclaim_all(dev);
3007
3008         for (q = 0; q < priv->hw_params->tx_queues; q++)
3009                 int1_enable |= (1 << q);
3010
3011         int0_enable = UMAC_IRQ_TXDMA_DONE;
3012
3013         /* Re-enable TX interrupts if disabled */
3014         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3015         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3016
3017         dev->trans_start = jiffies;
3018
3019         dev->stats.tx_errors++;
3020
3021         netif_tx_wake_all_queues(dev);
3022 }
3023
3024 #define MAX_MC_COUNT    16
3025
3026 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3027                                          unsigned char *addr,
3028                                          int *i,
3029                                          int *mc)
3030 {
3031         u32 reg;
3032
3033         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3034                              UMAC_MDF_ADDR + (*i * 4));
3035         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3036                              addr[4] << 8 | addr[5],
3037                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3038         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3039         reg |= (1 << (MAX_MC_COUNT - *mc));
3040         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3041         *i += 2;
3042         (*mc)++;
3043 }
3044
3045 static void bcmgenet_set_rx_mode(struct net_device *dev)
3046 {
3047         struct bcmgenet_priv *priv = netdev_priv(dev);
3048         struct netdev_hw_addr *ha;
3049         int i, mc;
3050         u32 reg;
3051
3052         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3053
3054         /* Promiscuous mode */
3055         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3056         if (dev->flags & IFF_PROMISC) {
3057                 reg |= CMD_PROMISC;
3058                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3059                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3060                 return;
3061         } else {
3062                 reg &= ~CMD_PROMISC;
3063                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3064         }
3065
3066         /* UniMac doesn't support ALLMULTI */
3067         if (dev->flags & IFF_ALLMULTI) {
3068                 netdev_warn(dev, "ALLMULTI is not supported\n");
3069                 return;
3070         }
3071
3072         /* update MDF filter */
3073         i = 0;
3074         mc = 0;
3075         /* Broadcast */
3076         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3077         /* my own address.*/
3078         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3079         /* Unicast list*/
3080         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3081                 return;
3082
3083         if (!netdev_uc_empty(dev))
3084                 netdev_for_each_uc_addr(ha, dev)
3085                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3086         /* Multicast */
3087         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3088                 return;
3089
3090         netdev_for_each_mc_addr(ha, dev)
3091                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3092 }
3093
3094 /* Set the hardware MAC address. */
3095 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3096 {
3097         struct sockaddr *addr = p;
3098
3099         /* Setting the MAC address at the hardware level is not possible
3100          * without disabling the UniMAC RX/TX enable bits.
3101          */
3102         if (netif_running(dev))
3103                 return -EBUSY;
3104
3105         ether_addr_copy(dev->dev_addr, addr->sa_data);
3106
3107         return 0;
3108 }
3109
3110 static const struct net_device_ops bcmgenet_netdev_ops = {
3111         .ndo_open               = bcmgenet_open,
3112         .ndo_stop               = bcmgenet_close,
3113         .ndo_start_xmit         = bcmgenet_xmit,
3114         .ndo_tx_timeout         = bcmgenet_timeout,
3115         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3116         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3117         .ndo_do_ioctl           = bcmgenet_ioctl,
3118         .ndo_set_features       = bcmgenet_set_features,
3119 #ifdef CONFIG_NET_POLL_CONTROLLER
3120         .ndo_poll_controller    = bcmgenet_poll_controller,
3121 #endif
3122 };
3123
3124 /* Array of GENET hardware parameters/characteristics */
3125 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3126         [GENET_V1] = {
3127                 .tx_queues = 0,
3128                 .tx_bds_per_q = 0,
3129                 .rx_queues = 0,
3130                 .rx_bds_per_q = 0,
3131                 .bp_in_en_shift = 16,
3132                 .bp_in_mask = 0xffff,
3133                 .hfb_filter_cnt = 16,
3134                 .qtag_mask = 0x1F,
3135                 .hfb_offset = 0x1000,
3136                 .rdma_offset = 0x2000,
3137                 .tdma_offset = 0x3000,
3138                 .words_per_bd = 2,
3139         },
3140         [GENET_V2] = {
3141                 .tx_queues = 4,
3142                 .tx_bds_per_q = 32,
3143                 .rx_queues = 0,
3144                 .rx_bds_per_q = 0,
3145                 .bp_in_en_shift = 16,
3146                 .bp_in_mask = 0xffff,
3147                 .hfb_filter_cnt = 16,
3148                 .qtag_mask = 0x1F,
3149                 .tbuf_offset = 0x0600,
3150                 .hfb_offset = 0x1000,
3151                 .hfb_reg_offset = 0x2000,
3152                 .rdma_offset = 0x3000,
3153                 .tdma_offset = 0x4000,
3154                 .words_per_bd = 2,
3155                 .flags = GENET_HAS_EXT,
3156         },
3157         [GENET_V3] = {
3158                 .tx_queues = 4,
3159                 .tx_bds_per_q = 32,
3160                 .rx_queues = 0,
3161                 .rx_bds_per_q = 0,
3162                 .bp_in_en_shift = 17,
3163                 .bp_in_mask = 0x1ffff,
3164                 .hfb_filter_cnt = 48,
3165                 .hfb_filter_size = 128,
3166                 .qtag_mask = 0x3F,
3167                 .tbuf_offset = 0x0600,
3168                 .hfb_offset = 0x8000,
3169                 .hfb_reg_offset = 0xfc00,
3170                 .rdma_offset = 0x10000,
3171                 .tdma_offset = 0x11000,
3172                 .words_per_bd = 2,
3173                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3174                          GENET_HAS_MOCA_LINK_DET,
3175         },
3176         [GENET_V4] = {
3177                 .tx_queues = 4,
3178                 .tx_bds_per_q = 32,
3179                 .rx_queues = 0,
3180                 .rx_bds_per_q = 0,
3181                 .bp_in_en_shift = 17,
3182                 .bp_in_mask = 0x1ffff,
3183                 .hfb_filter_cnt = 48,
3184                 .hfb_filter_size = 128,
3185                 .qtag_mask = 0x3F,
3186                 .tbuf_offset = 0x0600,
3187                 .hfb_offset = 0x8000,
3188                 .hfb_reg_offset = 0xfc00,
3189                 .rdma_offset = 0x2000,
3190                 .tdma_offset = 0x4000,
3191                 .words_per_bd = 3,
3192                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3193                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3194         },
3195 };
3196
3197 /* Infer hardware parameters from the detected GENET version */
3198 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3199 {
3200         struct bcmgenet_hw_params *params;
3201         u32 reg;
3202         u8 major;
3203         u16 gphy_rev;
3204
3205         if (GENET_IS_V4(priv)) {
3206                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3207                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3208                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3209                 priv->version = GENET_V4;
3210         } else if (GENET_IS_V3(priv)) {
3211                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3212                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3213                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3214                 priv->version = GENET_V3;
3215         } else if (GENET_IS_V2(priv)) {
3216                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3217                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3218                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3219                 priv->version = GENET_V2;
3220         } else if (GENET_IS_V1(priv)) {
3221                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3222                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3223                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3224                 priv->version = GENET_V1;
3225         }
3226
3227         /* enum genet_version starts at 1 */
3228         priv->hw_params = &bcmgenet_hw_params[priv->version];
3229         params = priv->hw_params;
3230
3231         /* Read GENET HW version */
3232         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3233         major = (reg >> 24 & 0x0f);
3234         if (major == 5)
3235                 major = 4;
3236         else if (major == 0)
3237                 major = 1;
3238         if (major != priv->version) {
3239                 dev_err(&priv->pdev->dev,
3240                         "GENET version mismatch, got: %d, configured for: %d\n",
3241                         major, priv->version);
3242         }
3243
3244         /* Print the GENET core version */
3245         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3246                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3247
3248         /* Store the integrated PHY revision for the MDIO probing function
3249          * to pass this information to the PHY driver. The PHY driver expects
3250          * to find the PHY major revision in bits 15:8 while the GENET register
3251          * stores that information in bits 7:0, account for that.
3252          *
3253          * On newer chips, starting with PHY revision G0, a new scheme is
3254          * deployed similar to the Starfighter 2 switch with GPHY major
3255          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3256          * is reserved as well as special value 0x01ff, we have a small
3257          * heuristic to check for the new GPHY revision and re-arrange things
3258          * so the GPHY driver is happy.
3259          */
3260         gphy_rev = reg & 0xffff;
3261
3262         /* This is the good old scheme, just GPHY major, no minor nor patch */
3263         if ((gphy_rev & 0xf0) != 0)
3264                 priv->gphy_rev = gphy_rev << 8;
3265
3266         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3267         else if ((gphy_rev & 0xff00) != 0)
3268                 priv->gphy_rev = gphy_rev;
3269
3270         /* This is reserved so should require special treatment */
3271         else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3272                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3273                 return;
3274         }
3275
3276 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3277         if (!(params->flags & GENET_HAS_40BITS))
3278                 pr_warn("GENET does not support 40-bits PA\n");
3279 #endif
3280
3281         pr_debug("Configuration for version: %d\n"
3282                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3283                 "BP << en: %2d, BP msk: 0x%05x\n"
3284                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3285                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3286                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3287                 "Words/BD: %d\n",
3288                 priv->version,
3289                 params->tx_queues, params->tx_bds_per_q,
3290                 params->rx_queues, params->rx_bds_per_q,
3291                 params->bp_in_en_shift, params->bp_in_mask,
3292                 params->hfb_filter_cnt, params->qtag_mask,
3293                 params->tbuf_offset, params->hfb_offset,
3294                 params->hfb_reg_offset,
3295                 params->rdma_offset, params->tdma_offset,
3296                 params->words_per_bd);
3297 }
3298
3299 static const struct of_device_id bcmgenet_match[] = {
3300         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3301         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3302         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3303         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3304         { },
3305 };
3306 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3307
3308 static int bcmgenet_probe(struct platform_device *pdev)
3309 {
3310         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3311         struct device_node *dn = pdev->dev.of_node;
3312         const struct of_device_id *of_id = NULL;
3313         struct bcmgenet_priv *priv;
3314         struct net_device *dev;
3315         const void *macaddr;
3316         struct resource *r;
3317         int err = -EIO;
3318
3319         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3320         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3321                                  GENET_MAX_MQ_CNT + 1);
3322         if (!dev) {
3323                 dev_err(&pdev->dev, "can't allocate net device\n");
3324                 return -ENOMEM;
3325         }
3326
3327         if (dn) {
3328                 of_id = of_match_node(bcmgenet_match, dn);
3329                 if (!of_id)
3330                         return -EINVAL;
3331         }
3332
3333         priv = netdev_priv(dev);
3334         priv->irq0 = platform_get_irq(pdev, 0);
3335         priv->irq1 = platform_get_irq(pdev, 1);
3336         priv->wol_irq = platform_get_irq(pdev, 2);
3337         if (!priv->irq0 || !priv->irq1) {
3338                 dev_err(&pdev->dev, "can't find IRQs\n");
3339                 err = -EINVAL;
3340                 goto err;
3341         }
3342
3343         if (dn) {
3344                 macaddr = of_get_mac_address(dn);
3345                 if (!macaddr) {
3346                         dev_err(&pdev->dev, "can't find MAC address\n");
3347                         err = -EINVAL;
3348                         goto err;
3349                 }
3350         } else {
3351                 macaddr = pd->mac_address;
3352         }
3353
3354         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3355         priv->base = devm_ioremap_resource(&pdev->dev, r);
3356         if (IS_ERR(priv->base)) {
3357                 err = PTR_ERR(priv->base);
3358                 goto err;
3359         }
3360
3361         SET_NETDEV_DEV(dev, &pdev->dev);
3362         dev_set_drvdata(&pdev->dev, dev);
3363         ether_addr_copy(dev->dev_addr, macaddr);
3364         dev->watchdog_timeo = 2 * HZ;
3365         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3366         dev->netdev_ops = &bcmgenet_netdev_ops;
3367
3368         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3369
3370         /* Set hardware features */
3371         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3372                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3373
3374         /* Request the WOL interrupt and advertise suspend if available */
3375         priv->wol_irq_disabled = true;
3376         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3377                                dev->name, priv);
3378         if (!err)
3379                 device_set_wakeup_capable(&pdev->dev, 1);
3380
3381         /* Set the needed headroom to account for any possible
3382          * features enabling/disabling at runtime
3383          */
3384         dev->needed_headroom += 64;
3385
3386         netdev_boot_setup_check(dev);
3387
3388         priv->dev = dev;
3389         priv->pdev = pdev;
3390         if (of_id)
3391                 priv->version = (enum bcmgenet_version)of_id->data;
3392         else
3393                 priv->version = pd->genet_version;
3394
3395         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3396         if (IS_ERR(priv->clk)) {
3397                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3398                 priv->clk = NULL;
3399         }
3400
3401         clk_prepare_enable(priv->clk);
3402
3403         bcmgenet_set_hw_params(priv);
3404
3405         /* Mii wait queue */
3406         init_waitqueue_head(&priv->wq);
3407         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3408         priv->rx_buf_len = RX_BUF_LENGTH;
3409         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3410
3411         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3412         if (IS_ERR(priv->clk_wol)) {
3413                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3414                 priv->clk_wol = NULL;
3415         }
3416
3417         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3418         if (IS_ERR(priv->clk_eee)) {
3419                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3420                 priv->clk_eee = NULL;
3421         }
3422
3423         err = reset_umac(priv);
3424         if (err)
3425                 goto err_clk_disable;
3426
3427         err = bcmgenet_mii_init(dev);
3428         if (err)
3429                 goto err_clk_disable;
3430
3431         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3432          * just the ring 16 descriptor based TX
3433          */
3434         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3435         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3436
3437         /* libphy will determine the link state */
3438         netif_carrier_off(dev);
3439
3440         /* Turn off the main clock, WOL clock is handled separately */
3441         clk_disable_unprepare(priv->clk);
3442
3443         err = register_netdev(dev);
3444         if (err)
3445                 goto err;
3446
3447         return err;
3448
3449 err_clk_disable:
3450         clk_disable_unprepare(priv->clk);
3451 err:
3452         free_netdev(dev);
3453         return err;
3454 }
3455
3456 static int bcmgenet_remove(struct platform_device *pdev)
3457 {
3458         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3459
3460         dev_set_drvdata(&pdev->dev, NULL);
3461         unregister_netdev(priv->dev);
3462         bcmgenet_mii_exit(priv->dev);
3463         free_netdev(priv->dev);
3464
3465         return 0;
3466 }
3467
3468 #ifdef CONFIG_PM_SLEEP
3469 static int bcmgenet_suspend(struct device *d)
3470 {
3471         struct net_device *dev = dev_get_drvdata(d);
3472         struct bcmgenet_priv *priv = netdev_priv(dev);
3473         int ret;
3474
3475         if (!netif_running(dev))
3476                 return 0;
3477
3478         bcmgenet_netif_stop(dev);
3479
3480         phy_suspend(priv->phydev);
3481
3482         netif_device_detach(dev);
3483
3484         /* Disable MAC receive */
3485         umac_enable_set(priv, CMD_RX_EN, false);
3486
3487         ret = bcmgenet_dma_teardown(priv);
3488         if (ret)
3489                 return ret;
3490
3491         /* Disable MAC transmit. TX DMA disabled have to done before this */
3492         umac_enable_set(priv, CMD_TX_EN, false);
3493
3494         /* tx reclaim */
3495         bcmgenet_tx_reclaim_all(dev);
3496         bcmgenet_fini_dma(priv);
3497
3498         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3499         if (device_may_wakeup(d) && priv->wolopts) {
3500                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3501                 clk_prepare_enable(priv->clk_wol);
3502         } else if (priv->internal_phy) {
3503                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3504         }
3505
3506         /* Turn off the clocks */
3507         clk_disable_unprepare(priv->clk);
3508
3509         return ret;
3510 }
3511
3512 static int bcmgenet_resume(struct device *d)
3513 {
3514         struct net_device *dev = dev_get_drvdata(d);
3515         struct bcmgenet_priv *priv = netdev_priv(dev);
3516         unsigned long dma_ctrl;
3517         int ret;
3518         u32 reg;
3519
3520         if (!netif_running(dev))
3521                 return 0;
3522
3523         /* Turn on the clock */
3524         ret = clk_prepare_enable(priv->clk);
3525         if (ret)
3526                 return ret;
3527
3528         /* If this is an internal GPHY, power it back on now, before UniMAC is
3529          * brought out of reset as absolutely no UniMAC activity is allowed
3530          */
3531         if (priv->internal_phy)
3532                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3533
3534         bcmgenet_umac_reset(priv);
3535
3536         ret = init_umac(priv);
3537         if (ret)
3538                 goto out_clk_disable;
3539
3540         /* From WOL-enabled suspend, switch to regular clock */
3541         if (priv->wolopts)
3542                 clk_disable_unprepare(priv->clk_wol);
3543
3544         phy_init_hw(priv->phydev);
3545         /* Speed settings must be restored */
3546         bcmgenet_mii_config(priv->dev);
3547
3548         /* disable ethernet MAC while updating its registers */
3549         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3550
3551         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3552
3553         if (priv->internal_phy) {
3554                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3555                 reg |= EXT_ENERGY_DET_MASK;
3556                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3557         }
3558
3559         if (priv->wolopts)
3560                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3561
3562         /* Disable RX/TX DMA and flush TX queues */
3563         dma_ctrl = bcmgenet_dma_disable(priv);
3564
3565         /* Reinitialize TDMA and RDMA and SW housekeeping */
3566         ret = bcmgenet_init_dma(priv);
3567         if (ret) {
3568                 netdev_err(dev, "failed to initialize DMA\n");
3569                 goto out_clk_disable;
3570         }
3571
3572         /* Always enable ring 16 - descriptor ring */
3573         bcmgenet_enable_dma(priv, dma_ctrl);
3574
3575         netif_device_attach(dev);
3576
3577         phy_resume(priv->phydev);
3578
3579         if (priv->eee.eee_enabled)
3580                 bcmgenet_eee_enable_set(dev, true);
3581
3582         bcmgenet_netif_start(dev);
3583
3584         return 0;
3585
3586 out_clk_disable:
3587         clk_disable_unprepare(priv->clk);
3588         return ret;
3589 }
3590 #endif /* CONFIG_PM_SLEEP */
3591
3592 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3593
3594 static struct platform_driver bcmgenet_driver = {
3595         .probe  = bcmgenet_probe,
3596         .remove = bcmgenet_remove,
3597         .driver = {
3598                 .name   = "bcmgenet",
3599                 .of_match_table = bcmgenet_match,
3600                 .pm     = &bcmgenet_pm_ops,
3601         },
3602 };
3603 module_platform_driver(bcmgenet_driver);
3604
3605 MODULE_AUTHOR("Broadcom Corporation");
3606 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3607 MODULE_ALIAS("platform:bcmgenet");
3608 MODULE_LICENSE("GPL");