drivers/net/ethernet/brocade/bna/bnad.c

   1 /*
   2  * Linux network driver for QLogic BR-series Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
  15  * Copyright (c) 2014-2015 QLogic Corporation
  16  * All rights reserved
  17  * www.qlogic.com
  18  */
  19 #include <linux/bitops.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/skbuff.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/in.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/if_vlan.h>
  26 #include <linux/if_ether.h>
  27 #include <linux/ip.h>
  28 #include <linux/prefetch.h>
  29 #include <linux/module.h>
  30
  31 #include "bnad.h"
  32 #include "bna.h"
  33 #include "cna.h"
  34
  35 static DEFINE_MUTEX(bnad_fwimg_mutex);
  36
  37 /*
  38  * Module params
  39  */
  40 static uint bnad_msix_disable;
  41 module_param(bnad_msix_disable, uint, 0444);
  42 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
  43
  44 static uint bnad_ioc_auto_recover = 1;
  45 module_param(bnad_ioc_auto_recover, uint, 0444);
  46 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
  47
  48 static uint bna_debugfs_enable = 1;
  49 module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
  50 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
  51                  " Range[false:0|true:1]");
  52
  53 /*
  54  * Global variables
  55  */
  56 static u32 bnad_rxqs_per_cq = 2;
  57 static u32 bna_id;
  58 static struct mutex bnad_list_mutex;
  59 static LIST_HEAD(bnad_list);
  60 static const u8 bnad_bcast_addr[] __aligned(2) =
  61         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  62
  63 /*
  64  * Local MACROS
  65  */
  66 #define BNAD_GET_MBOX_IRQ(_bnad)                                \
  67         (((_bnad)->cfg_flags & BNAD_CF_MSIX) ?                  \
  68          ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
  69          ((_bnad)->pcidev->irq))
  70
  71 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size)        \
  72 do {                                                            \
  73         (_res_info)->res_type = BNA_RES_T_MEM;                  \
  74         (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA;   \
  75         (_res_info)->res_u.mem_info.num = (_num);               \
  76         (_res_info)->res_u.mem_info.len = (_size);              \
  77 } while (0)
  78
  79 static void
  80 bnad_add_to_list(struct bnad *bnad)
  81 {
  82         mutex_lock(&bnad_list_mutex);
  83         list_add_tail(&bnad->list_entry, &bnad_list);
  84         bnad->id = bna_id++;
  85         mutex_unlock(&bnad_list_mutex);
  86 }
  87
  88 static void
  89 bnad_remove_from_list(struct bnad *bnad)
  90 {
  91         mutex_lock(&bnad_list_mutex);
  92         list_del(&bnad->list_entry);
  93         mutex_unlock(&bnad_list_mutex);
  94 }
  95
  96 /*
  97  * Reinitialize completions in CQ, once Rx is taken down
  98  */
  99 static void
 100 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
 101 {
 102         struct bna_cq_entry *cmpl;
 103         int i;
 104
 105         for (i = 0; i < ccb->q_depth; i++) {
 106                 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i];
 107                 cmpl->valid = 0;
 108         }
 109 }
 110
 111 /* Tx Datapath functions */
 112
 113
 114 /* Caller should ensure that the entry at unmap_q[index] is valid */
 115 static u32
 116 bnad_tx_buff_unmap(struct bnad *bnad,
 117                               struct bnad_tx_unmap *unmap_q,
 118                               u32 q_depth, u32 index)
 119 {
 120         struct bnad_tx_unmap *unmap;
 121         struct sk_buff *skb;
 122         int vector, nvecs;
 123
 124         unmap = &unmap_q[index];
 125         nvecs = unmap->nvecs;
 126
 127         skb = unmap->skb;
 128         unmap->skb = NULL;
 129         unmap->nvecs = 0;
 130         dma_unmap_single(&bnad->pcidev->dev,
 131                 dma_unmap_addr(&unmap->vectors[0], dma_addr),
 132                 skb_headlen(skb), DMA_TO_DEVICE);
 133         dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0);
 134         nvecs--;
 135
 136         vector = 0;
 137         while (nvecs) {
 138                 vector++;
 139                 if (vector == BFI_TX_MAX_VECTORS_PER_WI) {
 140                         vector = 0;
 141                         BNA_QE_INDX_INC(index, q_depth);
 142                         unmap = &unmap_q[index];
 143                 }
 144
 145                 dma_unmap_page(&bnad->pcidev->dev,
 146                         dma_unmap_addr(&unmap->vectors[vector], dma_addr),
 147                         dma_unmap_len(&unmap->vectors[vector], dma_len),
 148                         DMA_TO_DEVICE);
 149                 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0);
 150                 nvecs--;
 151         }
 152
 153         BNA_QE_INDX_INC(index, q_depth);
 154
 155         return index;
 156 }
 157
 158 /*
 159  * Frees all pending Tx Bufs
 160  * At this point no activity is expected on the Q,
 161  * so DMA unmap & freeing is fine.
 162  */
 163 static void
 164 bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
 165 {
 166         struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
 167         struct sk_buff *skb;
 168         int i;
 169
 170         for (i = 0; i < tcb->q_depth; i++) {
 171                 skb = unmap_q[i].skb;
 172                 if (!skb)
 173                         continue;
 174                 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i);
 175
 176                 dev_kfree_skb_any(skb);
 177         }
 178 }
 179
 180 /*
 181  * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
 182  * Can be called in a) Interrupt context
 183  *                  b) Sending context
 184  */
 185 static u32
 186 bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb)
 187 {
 188         u32 sent_packets = 0, sent_bytes = 0;
 189         u32 wis, unmap_wis, hw_cons, cons, q_depth;
 190         struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
 191         struct bnad_tx_unmap *unmap;
 192         struct sk_buff *skb;
 193
 194         /* Just return if TX is stopped */
 195         if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
 196                 return 0;
 197
 198         hw_cons = *(tcb->hw_consumer_index);
 199         cons = tcb->consumer_index;
 200         q_depth = tcb->q_depth;
 201
 202         wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth);
 203         BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
 204
 205         while (wis) {
 206                 unmap = &unmap_q[cons];
 207
 208                 skb = unmap->skb;
 209
 210                 sent_packets++;
 211                 sent_bytes += skb->len;
 212
 213                 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs);
 214                 wis -= unmap_wis;
 215
 216                 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons);
 217                 dev_kfree_skb_any(skb);
 218         }
 219
 220         /* Update consumer pointers. */
 221         tcb->consumer_index = hw_cons;
 222
 223         tcb->txq->tx_packets += sent_packets;
 224         tcb->txq->tx_bytes += sent_bytes;
 225
 226         return sent_packets;
 227 }
 228
 229 static u32
 230 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
 231 {
 232         struct net_device *netdev = bnad->netdev;
 233         u32 sent = 0;
 234
 235         if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
 236                 return 0;
 237
 238         sent = bnad_txcmpl_process(bnad, tcb);
 239         if (sent) {
 240                 if (netif_queue_stopped(netdev) &&
 241                     netif_carrier_ok(netdev) &&
 242                     BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
 243                                     BNAD_NETIF_WAKE_THRESHOLD) {
 244                         if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
 245                                 netif_wake_queue(netdev);
 246                                 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
 247                         }
 248                 }
 249         }
 250
 251         if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
 252                 bna_ib_ack(tcb->i_dbell, sent);
 253
 254         smp_mb__before_atomic();
 255         clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
 256
 257         return sent;
 258 }
 259
 260 /* MSIX Tx Completion Handler */
 261 static irqreturn_t
 262 bnad_msix_tx(int irq, void *data)
 263 {
 264         struct bna_tcb *tcb = (struct bna_tcb *)data;
 265         struct bnad *bnad = tcb->bnad;
 266
 267         bnad_tx_complete(bnad, tcb);
 268
 269         return IRQ_HANDLED;
 270 }
 271
 272 static inline void
 273 bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb)
 274 {
 275         struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
 276
 277         unmap_q->reuse_pi = -1;
 278         unmap_q->alloc_order = -1;
 279         unmap_q->map_size = 0;
 280         unmap_q->type = BNAD_RXBUF_NONE;
 281 }
 282
 283 /* Default is page-based allocation. Multi-buffer support - TBD */
 284 static int
 285 bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
 286 {
 287         struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
 288         int order;
 289
 290         bnad_rxq_alloc_uninit(bnad, rcb);
 291
 292         order = get_order(rcb->rxq->buffer_size);
 293
 294         unmap_q->type = BNAD_RXBUF_PAGE;
 295
 296         if (bna_is_small_rxq(rcb->id)) {
 297                 unmap_q->alloc_order = 0;
 298                 unmap_q->map_size = rcb->rxq->buffer_size;
 299         } else {
 300                 if (rcb->rxq->multi_buffer) {
 301                         unmap_q->alloc_order = 0;
 302                         unmap_q->map_size = rcb->rxq->buffer_size;
 303                         unmap_q->type = BNAD_RXBUF_MULTI_BUFF;
 304                 } else {
 305                         unmap_q->alloc_order = order;
 306                         unmap_q->map_size =
 307                                 (rcb->rxq->buffer_size > 2048) ?
 308                                 PAGE_SIZE << order : 2048;
 309                 }
 310         }
 311
 312         BUG_ON(((PAGE_SIZE << order) % unmap_q->map_size));
 313
 314         return 0;
 315 }
 316
 317 static inline void
 318 bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap)
 319 {
 320         if (!unmap->page)
 321                 return;
 322
 323         dma_unmap_page(&bnad->pcidev->dev,
 324                         dma_unmap_addr(&unmap->vector, dma_addr),
 325                         unmap->vector.len, DMA_FROM_DEVICE);
 326         put_page(unmap->page);
 327         unmap->page = NULL;
 328         dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
 329         unmap->vector.len = 0;
 330 }
 331
 332 static inline void
 333 bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap)
 334 {
 335         if (!unmap->skb)
 336                 return;
 337
 338         dma_unmap_single(&bnad->pcidev->dev,
 339                         dma_unmap_addr(&unmap->vector, dma_addr),
 340                         unmap->vector.len, DMA_FROM_DEVICE);
 341         dev_kfree_skb_any(unmap->skb);
 342         unmap->skb = NULL;
 343         dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
 344         unmap->vector.len = 0;
 345 }
 346
 347 static void
 348 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
 349 {
 350         struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
 351         int i;
 352
 353         for (i = 0; i < rcb->q_depth; i++) {
 354                 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i];
 355
 356                 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
 357                         bnad_rxq_cleanup_skb(bnad, unmap);
 358                 else
 359                         bnad_rxq_cleanup_page(bnad, unmap);
 360         }
 361         bnad_rxq_alloc_uninit(bnad, rcb);
 362 }
 363
 364 static u32
 365 bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
 366 {
 367         u32 alloced, prod, q_depth;
 368         struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
 369         struct bnad_rx_unmap *unmap, *prev;
 370         struct bna_rxq_entry *rxent;
 371         struct page *page;
 372         u32 page_offset, alloc_size;
 373         dma_addr_t dma_addr;
 374
 375         prod = rcb->producer_index;
 376         q_depth = rcb->q_depth;
 377
 378         alloc_size = PAGE_SIZE << unmap_q->alloc_order;
 379         alloced = 0;
 380
 381         while (nalloc--) {
 382                 unmap = &unmap_q->unmap[prod];
 383
 384                 if (unmap_q->reuse_pi < 0) {
 385                         page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
 386                                         unmap_q->alloc_order);
 387                         page_offset = 0;
 388                 } else {
 389                         prev = &unmap_q->unmap[unmap_q->reuse_pi];
 390                         page = prev->page;
 391                         page_offset = prev->page_offset + unmap_q->map_size;
 392                         get_page(page);
 393                 }
 394
 395                 if (unlikely(!page)) {
 396                         BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
 397                         rcb->rxq->rxbuf_alloc_failed++;
 398                         goto finishing;
 399                 }
 400
 401                 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset,
 402                                 unmap_q->map_size, DMA_FROM_DEVICE);
 403
 404                 unmap->page = page;
 405                 unmap->page_offset = page_offset;
 406                 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
 407                 unmap->vector.len = unmap_q->map_size;
 408                 page_offset += unmap_q->map_size;
 409
 410                 if (page_offset < alloc_size)
 411                         unmap_q->reuse_pi = prod;
 412                 else
 413                         unmap_q->reuse_pi = -1;
 414
 415                 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
 416                 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
 417                 BNA_QE_INDX_INC(prod, q_depth);
 418                 alloced++;
 419         }
 420
 421 finishing:
 422         if (likely(alloced)) {
 423                 rcb->producer_index = prod;
 424                 smp_mb();
 425                 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
 426                         bna_rxq_prod_indx_doorbell(rcb);
 427         }
 428
 429         return alloced;
 430 }
 431
 432 static u32
 433 bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
 434 {
 435         u32 alloced, prod, q_depth, buff_sz;
 436         struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
 437         struct bnad_rx_unmap *unmap;
 438         struct bna_rxq_entry *rxent;
 439         struct sk_buff *skb;
 440         dma_addr_t dma_addr;
 441
 442         buff_sz = rcb->rxq->buffer_size;
 443         prod = rcb->producer_index;
 444         q_depth = rcb->q_depth;
 445
 446         alloced = 0;
 447         while (nalloc--) {
 448                 unmap = &unmap_q->unmap[prod];
 449
 450                 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz);
 451
 452                 if (unlikely(!skb)) {
 453                         BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
 454                         rcb->rxq->rxbuf_alloc_failed++;
 455                         goto finishing;
 456                 }
 457                 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
 458                                           buff_sz, DMA_FROM_DEVICE);
 459
 460                 unmap->skb = skb;
 461                 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
 462                 unmap->vector.len = buff_sz;
 463
 464                 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
 465                 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
 466                 BNA_QE_INDX_INC(prod, q_depth);
 467                 alloced++;
 468         }
 469
 470 finishing:
 471         if (likely(alloced)) {
 472                 rcb->producer_index = prod;
 473                 smp_mb();
 474                 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
 475                         bna_rxq_prod_indx_doorbell(rcb);
 476         }
 477
 478         return alloced;
 479 }
 480
 481 static inline void
 482 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
 483 {
 484         struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
 485         u32 to_alloc;
 486
 487         to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth);
 488         if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT))
 489                 return;
 490
 491         if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
 492                 bnad_rxq_refill_skb(bnad, rcb, to_alloc);
 493         else
 494                 bnad_rxq_refill_page(bnad, rcb, to_alloc);
 495 }
 496
 497 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
 498                                         BNA_CQ_EF_IPV6 | \
 499                                         BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
 500                                         BNA_CQ_EF_L4_CKSUM_OK)
 501
 502 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
 503                                 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
 504 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \
 505                                 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
 506 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
 507                                 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
 508 #define flags_udp6 (BNA_CQ_EF_IPV6 | \
 509                                 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
 510
 511 static void
 512 bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb,
 513                     u32 sop_ci, u32 nvecs)
 514 {
 515         struct bnad_rx_unmap_q *unmap_q;
 516         struct bnad_rx_unmap *unmap;
 517         u32 ci, vec;
 518
 519         unmap_q = rcb->unmap_q;
 520         for (vec = 0, ci = sop_ci; vec < nvecs; vec++) {
 521                 unmap = &unmap_q->unmap[ci];
 522                 BNA_QE_INDX_INC(ci, rcb->q_depth);
 523
 524                 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
 525                         bnad_rxq_cleanup_skb(bnad, unmap);
 526                 else
 527                         bnad_rxq_cleanup_page(bnad, unmap);
 528         }
 529 }
 530
 531 static void
 532 bnad_cq_setup_skb_frags(struct bna_rcb *rcb, struct sk_buff *skb,
 533                         u32 sop_ci, u32 nvecs, u32 last_fraglen)
 534 {
 535         struct bnad *bnad;
 536         u32 ci, vec, len, totlen = 0;
 537         struct bnad_rx_unmap_q *unmap_q;
 538         struct bnad_rx_unmap *unmap;
 539
 540         unmap_q = rcb->unmap_q;
 541         bnad = rcb->bnad;
 542
 543         /* prefetch header */
 544         prefetch(page_address(unmap_q->unmap[sop_ci].page) +
 545                         unmap_q->unmap[sop_ci].page_offset);
 546
 547         for (vec = 1, ci = sop_ci; vec <= nvecs; vec++) {
 548                 unmap = &unmap_q->unmap[ci];
 549                 BNA_QE_INDX_INC(ci, rcb->q_depth);
 550
 551                 dma_unmap_page(&bnad->pcidev->dev,
 552                                 dma_unmap_addr(&unmap->vector, dma_addr),
 553                                 unmap->vector.len, DMA_FROM_DEVICE);
 554
 555                 len = (vec == nvecs) ?
 556                         last_fraglen : unmap->vector.len;
 557                 skb->truesize += unmap->vector.len;
 558                 totlen += len;
 559
 560                 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 561                                 unmap->page, unmap->page_offset, len);
 562
 563                 unmap->page = NULL;
 564                 unmap->vector.len = 0;
 565         }
 566
 567         skb->len += totlen;
 568         skb->data_len += totlen;
 569 }
 570
 571 static inline void
 572 bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb,
 573                   struct bnad_rx_unmap *unmap, u32 len)
 574 {
 575         prefetch(skb->data);
 576
 577         dma_unmap_single(&bnad->pcidev->dev,
 578                         dma_unmap_addr(&unmap->vector, dma_addr),
 579                         unmap->vector.len, DMA_FROM_DEVICE);
 580
 581         skb_put(skb, len);
 582         skb->protocol = eth_type_trans(skb, bnad->netdev);
 583
 584         unmap->skb = NULL;
 585         unmap->vector.len = 0;
 586 }
 587
 588 static u32
 589 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
 590 {
 591         struct bna_cq_entry *cq, *cmpl, *next_cmpl;
 592         struct bna_rcb *rcb = NULL;
 593         struct bnad_rx_unmap_q *unmap_q;
 594         struct bnad_rx_unmap *unmap = NULL;
 595         struct sk_buff *skb = NULL;
 596         struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
 597         struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl;
 598         u32 packets = 0, len = 0, totlen = 0;
 599         u32 pi, vec, sop_ci = 0, nvecs = 0;
 600         u32 flags, masked_flags;
 601
 602         prefetch(bnad->netdev);
 603
 604         cq = ccb->sw_q;
 605
 606         while (packets < budget) {
 607                 cmpl = &cq[ccb->producer_index];
 608                 if (!cmpl->valid)
 609                         break;
 610                 /* The 'valid' field is set by the adapter, only after writing
 611                  * the other fields of completion entry. Hence, do not load
 612                  * other fields of completion entry *before* the 'valid' is
 613                  * loaded. Adding the rmb() here prevents the compiler and/or
 614                  * CPU from reordering the reads which would potentially result
 615                  * in reading stale values in completion entry.
 616                  */
 617                 rmb();
 618
 619                 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
 620
 621                 if (bna_is_small_rxq(cmpl->rxq_id))
 622                         rcb = ccb->rcb[1];
 623                 else
 624                         rcb = ccb->rcb[0];
 625
 626                 unmap_q = rcb->unmap_q;
 627
 628                 /* start of packet ci */
 629                 sop_ci = rcb->consumer_index;
 630
 631                 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) {
 632                         unmap = &unmap_q->unmap[sop_ci];
 633                         skb = unmap->skb;
 634                 } else {
 635                         skb = napi_get_frags(&rx_ctrl->napi);
 636                         if (unlikely(!skb))
 637                                 break;
 638                 }
 639                 prefetch(skb);
 640
 641                 flags = ntohl(cmpl->flags);
 642                 len = ntohs(cmpl->length);
 643                 totlen = len;
 644                 nvecs = 1;
 645
 646                 /* Check all the completions for this frame.
 647                  * busy-wait doesn't help much, break here.
 648                  */
 649                 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) &&
 650                     (flags & BNA_CQ_EF_EOP) == 0) {
 651                         pi = ccb->producer_index;
 652                         do {
 653                                 BNA_QE_INDX_INC(pi, ccb->q_depth);
 654                                 next_cmpl = &cq[pi];
 655
 656                                 if (!next_cmpl->valid)
 657                                         break;
 658                                 /* The 'valid' field is set by the adapter, only
 659                                  * after writing the other fields of completion
 660                                  * entry. Hence, do not load other fields of
 661                                  * completion entry *before* the 'valid' is
 662                                  * loaded. Adding the rmb() here prevents the
 663                                  * compiler and/or CPU from reordering the reads
 664                                  * which would potentially result in reading
 665                                  * stale values in completion entry.
 666                                  */
 667                                 rmb();
 668
 669                                 len = ntohs(next_cmpl->length);
 670                                 flags = ntohl(next_cmpl->flags);
 671
 672                                 nvecs++;
 673                                 totlen += len;
 674                         } while ((flags & BNA_CQ_EF_EOP) == 0);
 675
 676                         if (!next_cmpl->valid)
 677                                 break;
 678                 }
 679
 680                 /* TODO: BNA_CQ_EF_LOCAL ? */
 681                 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
 682                                                 BNA_CQ_EF_FCS_ERROR |
 683                                                 BNA_CQ_EF_TOO_LONG))) {
 684                         bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs);
 685                         rcb->rxq->rx_packets_with_error++;
 686
 687                         goto next;
 688                 }
 689
 690                 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
 691                         bnad_cq_setup_skb(bnad, skb, unmap, len);
 692                 else
 693                         bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
 694
 695                 packets++;
 696                 rcb->rxq->rx_packets++;
 697                 rcb->rxq->rx_bytes += totlen;
 698                 ccb->bytes_per_intr += totlen;
 699
 700                 masked_flags = flags & flags_cksum_prot_mask;
 701
 702                 if (likely
 703                     ((bnad->netdev->features & NETIF_F_RXCSUM) &&
 704                      ((masked_flags == flags_tcp4) ||
 705                       (masked_flags == flags_udp4) ||
 706                       (masked_flags == flags_tcp6) ||
 707                       (masked_flags == flags_udp6))))
 708                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 709                 else
 710                         skb_checksum_none_assert(skb);
 711
 712                 if ((flags & BNA_CQ_EF_VLAN) &&
 713                     (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX))
 714                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag));
 715
 716                 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
 717                         netif_receive_skb(skb);
 718                 else
 719                         napi_gro_frags(&rx_ctrl->napi);
 720
 721 next:
 722                 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth);
 723                 for (vec = 0; vec < nvecs; vec++) {
 724                         cmpl = &cq[ccb->producer_index];
 725                         cmpl->valid = 0;
 726                         BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
 727                 }
 728         }
 729
 730         napi_gro_flush(&rx_ctrl->napi, false);
 731         if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
 732                 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
 733
 734         bnad_rxq_post(bnad, ccb->rcb[0]);
 735         if (ccb->rcb[1])
 736                 bnad_rxq_post(bnad, ccb->rcb[1]);
 737
 738         return packets;
 739 }
 740
 741 static void
 742 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
 743 {
 744         struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
 745         struct napi_struct *napi = &rx_ctrl->napi;
 746
 747         if (likely(napi_schedule_prep(napi))) {
 748                 __napi_schedule(napi);
 749                 rx_ctrl->rx_schedule++;
 750         }
 751 }
 752
 753 /* MSIX Rx Path Handler */
 754 static irqreturn_t
 755 bnad_msix_rx(int irq, void *data)
 756 {
 757         struct bna_ccb *ccb = (struct bna_ccb *)data;
 758
 759         if (ccb) {
 760                 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
 761                 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
 762         }
 763
 764         return IRQ_HANDLED;
 765 }
 766
 767 /* Interrupt handlers */
 768
 769 /* Mbox Interrupt Handlers */
 770 static irqreturn_t
 771 bnad_msix_mbox_handler(int irq, void *data)
 772 {
 773         u32 intr_status;
 774         unsigned long flags;
 775         struct bnad *bnad = (struct bnad *)data;
 776
 777         spin_lock_irqsave(&bnad->bna_lock, flags);
 778         if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
 779                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
 780                 return IRQ_HANDLED;
 781         }
 782
 783         bna_intr_status_get(&bnad->bna, intr_status);
 784
 785         if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
 786                 bna_mbox_handler(&bnad->bna, intr_status);
 787
 788         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 789
 790         return IRQ_HANDLED;
 791 }
 792
 793 static irqreturn_t
 794 bnad_isr(int irq, void *data)
 795 {
 796         int i, j;
 797         u32 intr_status;
 798         unsigned long flags;
 799         struct bnad *bnad = (struct bnad *)data;
 800         struct bnad_rx_info *rx_info;
 801         struct bnad_rx_ctrl *rx_ctrl;
 802         struct bna_tcb *tcb = NULL;
 803
 804         spin_lock_irqsave(&bnad->bna_lock, flags);
 805         if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
 806                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
 807                 return IRQ_NONE;
 808         }
 809
 810         bna_intr_status_get(&bnad->bna, intr_status);
 811
 812         if (unlikely(!intr_status)) {
 813                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
 814                 return IRQ_NONE;
 815         }
 816
 817         if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
 818                 bna_mbox_handler(&bnad->bna, intr_status);
 819
 820         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 821
 822         if (!BNA_IS_INTX_DATA_INTR(intr_status))
 823                 return IRQ_HANDLED;
 824
 825         /* Process data interrupts */
 826         /* Tx processing */
 827         for (i = 0; i < bnad->num_tx; i++) {
 828                 for (j = 0; j < bnad->num_txq_per_tx; j++) {
 829                         tcb = bnad->tx_info[i].tcb[j];
 830                         if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
 831                                 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
 832                 }
 833         }
 834         /* Rx processing */
 835         for (i = 0; i < bnad->num_rx; i++) {
 836                 rx_info = &bnad->rx_info[i];
 837                 if (!rx_info->rx)
 838                         continue;
 839                 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
 840                         rx_ctrl = &rx_info->rx_ctrl[j];
 841                         if (rx_ctrl->ccb)
 842                                 bnad_netif_rx_schedule_poll(bnad,
 843                                                             rx_ctrl->ccb);
 844                 }
 845         }
 846         return IRQ_HANDLED;
 847 }
 848
 849 /*
 850  * Called in interrupt / callback context
 851  * with bna_lock held, so cfg_flags access is OK
 852  */
 853 static void
 854 bnad_enable_mbox_irq(struct bnad *bnad)
 855 {
 856         clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
 857
 858         BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
 859 }
 860
 861 /*
 862  * Called with bnad->bna_lock held b'cos of
 863  * bnad->cfg_flags access.
 864  */
 865 static void
 866 bnad_disable_mbox_irq(struct bnad *bnad)
 867 {
 868         set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
 869
 870         BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
 871 }
 872
 873 static void
 874 bnad_set_netdev_perm_addr(struct bnad *bnad)
 875 {
 876         struct net_device *netdev = bnad->netdev;
 877
 878         ether_addr_copy(netdev->perm_addr, bnad->perm_addr);
 879         if (is_zero_ether_addr(netdev->dev_addr))
 880                 ether_addr_copy(netdev->dev_addr, bnad->perm_addr);
 881 }
 882
 883 /* Control Path Handlers */
 884
 885 /* Callbacks */
 886 void
 887 bnad_cb_mbox_intr_enable(struct bnad *bnad)
 888 {
 889         bnad_enable_mbox_irq(bnad);
 890 }
 891
 892 void
 893 bnad_cb_mbox_intr_disable(struct bnad *bnad)
 894 {
 895         bnad_disable_mbox_irq(bnad);
 896 }
 897
 898 void
 899 bnad_cb_ioceth_ready(struct bnad *bnad)
 900 {
 901         bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
 902         complete(&bnad->bnad_completions.ioc_comp);
 903 }
 904
 905 void
 906 bnad_cb_ioceth_failed(struct bnad *bnad)
 907 {
 908         bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
 909         complete(&bnad->bnad_completions.ioc_comp);
 910 }
 911
 912 void
 913 bnad_cb_ioceth_disabled(struct bnad *bnad)
 914 {
 915         bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
 916         complete(&bnad->bnad_completions.ioc_comp);
 917 }
 918
 919 static void
 920 bnad_cb_enet_disabled(void *arg)
 921 {
 922         struct bnad *bnad = (struct bnad *)arg;
 923
 924         netif_carrier_off(bnad->netdev);
 925         complete(&bnad->bnad_completions.enet_comp);
 926 }
 927
 928 void
 929 bnad_cb_ethport_link_status(struct bnad *bnad,
 930                         enum bna_link_status link_status)
 931 {
 932         bool link_up = false;
 933
 934         link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
 935
 936         if (link_status == BNA_CEE_UP) {
 937                 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
 938                         BNAD_UPDATE_CTR(bnad, cee_toggle);
 939                 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
 940         } else {
 941                 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
 942                         BNAD_UPDATE_CTR(bnad, cee_toggle);
 943                 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
 944         }
 945
 946         if (link_up) {
 947                 if (!netif_carrier_ok(bnad->netdev)) {
 948                         uint tx_id, tcb_id;
 949                         printk(KERN_WARNING "bna: %s link up\n",
 950                                 bnad->netdev->name);
 951                         netif_carrier_on(bnad->netdev);
 952                         BNAD_UPDATE_CTR(bnad, link_toggle);
 953                         for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
 954                                 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
 955                                       tcb_id++) {
 956                                         struct bna_tcb *tcb =
 957                                         bnad->tx_info[tx_id].tcb[tcb_id];
 958                                         u32 txq_id;
 959                                         if (!tcb)
 960                                                 continue;
 961
 962                                         txq_id = tcb->id;
 963
 964                                         if (test_bit(BNAD_TXQ_TX_STARTED,
 965                                                      &tcb->flags)) {
 966                                                 /*
 967                                                  * Force an immediate
 968                                                  * Transmit Schedule */
 969                                                 printk(KERN_INFO "bna: %s %d "
 970                                                       "TXQ_STARTED\n",
 971                                                        bnad->netdev->name,
 972                                                        txq_id);
 973                                                 netif_wake_subqueue(
 974                                                                 bnad->netdev,
 975                                                                 txq_id);
 976                                                 BNAD_UPDATE_CTR(bnad,
 977                                                         netif_queue_wakeup);
 978                                         } else {
 979                                                 netif_stop_subqueue(
 980                                                                 bnad->netdev,
 981                                                                 txq_id);
 982                                                 BNAD_UPDATE_CTR(bnad,
 983                                                         netif_queue_stop);
 984                                         }
 985                                 }
 986                         }
 987                 }
 988         } else {
 989                 if (netif_carrier_ok(bnad->netdev)) {
 990                         printk(KERN_WARNING "bna: %s link down\n",
 991                                 bnad->netdev->name);
 992                         netif_carrier_off(bnad->netdev);
 993                         BNAD_UPDATE_CTR(bnad, link_toggle);
 994                 }
 995         }
 996 }
 997
 998 static void
 999 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
1000 {
1001         struct bnad *bnad = (struct bnad *)arg;
1002
1003         complete(&bnad->bnad_completions.tx_comp);
1004 }
1005
1006 static void
1007 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
1008 {
1009         struct bnad_tx_info *tx_info =
1010                         (struct bnad_tx_info *)tcb->txq->tx->priv;
1011
1012         tcb->priv = tcb;
1013         tx_info->tcb[tcb->id] = tcb;
1014 }
1015
1016 static void
1017 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
1018 {
1019         struct bnad_tx_info *tx_info =
1020                         (struct bnad_tx_info *)tcb->txq->tx->priv;
1021
1022         tx_info->tcb[tcb->id] = NULL;
1023         tcb->priv = NULL;
1024 }
1025
1026 static void
1027 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
1028 {
1029         struct bnad_rx_info *rx_info =
1030                         (struct bnad_rx_info *)ccb->cq->rx->priv;
1031
1032         rx_info->rx_ctrl[ccb->id].ccb = ccb;
1033         ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
1034 }
1035
1036 static void
1037 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
1038 {
1039         struct bnad_rx_info *rx_info =
1040                         (struct bnad_rx_info *)ccb->cq->rx->priv;
1041
1042         rx_info->rx_ctrl[ccb->id].ccb = NULL;
1043 }
1044
1045 static void
1046 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
1047 {
1048         struct bnad_tx_info *tx_info =
1049                         (struct bnad_tx_info *)tx->priv;
1050         struct bna_tcb *tcb;
1051         u32 txq_id;
1052         int i;
1053
1054         for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1055                 tcb = tx_info->tcb[i];
1056                 if (!tcb)
1057                         continue;
1058                 txq_id = tcb->id;
1059                 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1060                 netif_stop_subqueue(bnad->netdev, txq_id);
1061                 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
1062                         bnad->netdev->name, txq_id);
1063         }
1064 }
1065
1066 static void
1067 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
1068 {
1069         struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1070         struct bna_tcb *tcb;
1071         u32 txq_id;
1072         int i;
1073
1074         for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1075                 tcb = tx_info->tcb[i];
1076                 if (!tcb)
1077                         continue;
1078                 txq_id = tcb->id;
1079
1080                 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
1081                 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1082                 BUG_ON(*(tcb->hw_consumer_index) != 0);
1083
1084                 if (netif_carrier_ok(bnad->netdev)) {
1085                         printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
1086                                 bnad->netdev->name, txq_id);
1087                         netif_wake_subqueue(bnad->netdev, txq_id);
1088                         BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
1089                 }
1090         }
1091
1092         /*
1093          * Workaround for first ioceth enable failure & we
1094          * get a 0 MAC address. We try to get the MAC address
1095          * again here.
1096          */
1097         if (is_zero_ether_addr(bnad->perm_addr)) {
1098                 bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr);
1099                 bnad_set_netdev_perm_addr(bnad);
1100         }
1101 }
1102
1103 /*
1104  * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1105  */
1106 static void
1107 bnad_tx_cleanup(struct delayed_work *work)
1108 {
1109         struct bnad_tx_info *tx_info =
1110                 container_of(work, struct bnad_tx_info, tx_cleanup_work);
1111         struct bnad *bnad = NULL;
1112         struct bna_tcb *tcb;
1113         unsigned long flags;
1114         u32 i, pending = 0;
1115
1116         for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1117                 tcb = tx_info->tcb[i];
1118                 if (!tcb)
1119                         continue;
1120
1121                 bnad = tcb->bnad;
1122
1123                 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
1124                         pending++;
1125                         continue;
1126                 }
1127
1128                 bnad_txq_cleanup(bnad, tcb);
1129
1130                 smp_mb__before_atomic();
1131                 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
1132         }
1133
1134         if (pending) {
1135                 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
1136                         msecs_to_jiffies(1));
1137                 return;
1138         }
1139
1140         spin_lock_irqsave(&bnad->bna_lock, flags);
1141         bna_tx_cleanup_complete(tx_info->tx);
1142         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1143 }
1144
1145 static void
1146 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
1147 {
1148         struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1149         struct bna_tcb *tcb;
1150         int i;
1151
1152         for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1153                 tcb = tx_info->tcb[i];
1154                 if (!tcb)
1155                         continue;
1156         }
1157
1158         queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
1159 }
1160
1161 static void
1162 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
1163 {
1164         struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1165         struct bna_ccb *ccb;
1166         struct bnad_rx_ctrl *rx_ctrl;
1167         int i;
1168
1169         for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1170                 rx_ctrl = &rx_info->rx_ctrl[i];
1171                 ccb = rx_ctrl->ccb;
1172                 if (!ccb)
1173                         continue;
1174
1175                 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1176
1177                 if (ccb->rcb[1])
1178                         clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1179         }
1180 }
1181
1182 /*
1183  * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1184  */
1185 static void
1186 bnad_rx_cleanup(void *work)
1187 {
1188         struct bnad_rx_info *rx_info =
1189                 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1190         struct bnad_rx_ctrl *rx_ctrl;
1191         struct bnad *bnad = NULL;
1192         unsigned long flags;
1193         u32 i;
1194
1195         for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1196                 rx_ctrl = &rx_info->rx_ctrl[i];
1197
1198                 if (!rx_ctrl->ccb)
1199                         continue;
1200
1201                 bnad = rx_ctrl->ccb->bnad;
1202
1203                 /*
1204                  * Wait till the poll handler has exited
1205                  * and nothing can be scheduled anymore
1206                  */
1207                 napi_disable(&rx_ctrl->napi);
1208
1209                 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
1210                 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
1211                 if (rx_ctrl->ccb->rcb[1])
1212                         bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
1213         }
1214
1215         spin_lock_irqsave(&bnad->bna_lock, flags);
1216         bna_rx_cleanup_complete(rx_info->rx);
1217         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1218 }
1219
1220 static void
1221 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
1222 {
1223         struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1224         struct bna_ccb *ccb;
1225         struct bnad_rx_ctrl *rx_ctrl;
1226         int i;
1227
1228         for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1229                 rx_ctrl = &rx_info->rx_ctrl[i];
1230                 ccb = rx_ctrl->ccb;
1231                 if (!ccb)
1232                         continue;
1233
1234                 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1235
1236                 if (ccb->rcb[1])
1237                         clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
1238         }
1239
1240         queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
1241 }
1242
1243 static void
1244 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
1245 {
1246         struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1247         struct bna_ccb *ccb;
1248         struct bna_rcb *rcb;
1249         struct bnad_rx_ctrl *rx_ctrl;
1250         int i, j;
1251
1252         for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1253                 rx_ctrl = &rx_info->rx_ctrl[i];
1254                 ccb = rx_ctrl->ccb;
1255                 if (!ccb)
1256                         continue;
1257
1258                 napi_enable(&rx_ctrl->napi);
1259
1260                 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1261                         rcb = ccb->rcb[j];
1262                         if (!rcb)
1263                                 continue;
1264
1265                         bnad_rxq_alloc_init(bnad, rcb);
1266                         set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1267                         set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
1268                         bnad_rxq_post(bnad, rcb);
1269                 }
1270         }
1271 }
1272
1273 static void
1274 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
1275 {
1276         struct bnad *bnad = (struct bnad *)arg;
1277
1278         complete(&bnad->bnad_completions.rx_comp);
1279 }
1280
1281 static void
1282 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
1283 {
1284         bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
1285         complete(&bnad->bnad_completions.mcast_comp);
1286 }
1287
1288 void
1289 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1290                        struct bna_stats *stats)
1291 {
1292         if (status == BNA_CB_SUCCESS)
1293                 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1294
1295         if (!netif_running(bnad->netdev) ||
1296                 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1297                 return;
1298
1299         mod_timer(&bnad->stats_timer,
1300                   jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1301 }
1302
1303 static void
1304 bnad_cb_enet_mtu_set(struct bnad *bnad)
1305 {
1306         bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1307         complete(&bnad->bnad_completions.mtu_comp);
1308 }
1309
1310 void
1311 bnad_cb_completion(void *arg, enum bfa_status status)
1312 {
1313         struct bnad_iocmd_comp *iocmd_comp =
1314                         (struct bnad_iocmd_comp *)arg;
1315
1316         iocmd_comp->comp_status = (u32) status;
1317         complete(&iocmd_comp->comp);
1318 }
1319
1320 /* Resource allocation, free functions */
1321
1322 static void
1323 bnad_mem_free(struct bnad *bnad,
1324               struct bna_mem_info *mem_info)
1325 {
1326         int i;
1327         dma_addr_t dma_pa;
1328
1329         if (mem_info->mdl == NULL)
1330                 return;
1331
1332         for (i = 0; i < mem_info->num; i++) {
1333                 if (mem_info->mdl[i].kva != NULL) {
1334                         if (mem_info->mem_type == BNA_MEM_T_DMA) {
1335                                 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1336                                                 dma_pa);
1337                                 dma_free_coherent(&bnad->pcidev->dev,
1338                                                   mem_info->mdl[i].len,
1339                                                   mem_info->mdl[i].kva, dma_pa);
1340                         } else
1341                                 kfree(mem_info->mdl[i].kva);
1342                 }
1343         }
1344         kfree(mem_info->mdl);
1345         mem_info->mdl = NULL;
1346 }
1347
1348 static int
1349 bnad_mem_alloc(struct bnad *bnad,
1350                struct bna_mem_info *mem_info)
1351 {
1352         int i;
1353         dma_addr_t dma_pa;
1354
1355         if ((mem_info->num == 0) || (mem_info->len == 0)) {
1356                 mem_info->mdl = NULL;
1357                 return 0;
1358         }
1359
1360         mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1361                                 GFP_KERNEL);
1362         if (mem_info->mdl == NULL)
1363                 return -ENOMEM;
1364
1365         if (mem_info->mem_type == BNA_MEM_T_DMA) {
1366                 for (i = 0; i < mem_info->num; i++) {
1367                         mem_info->mdl[i].len = mem_info->len;
1368                         mem_info->mdl[i].kva =
1369                                 dma_alloc_coherent(&bnad->pcidev->dev,
1370                                                    mem_info->len, &dma_pa,
1371                                                    GFP_KERNEL);
1372                         if (mem_info->mdl[i].kva == NULL)
1373                                 goto err_return;
1374
1375                         BNA_SET_DMA_ADDR(dma_pa,
1376                                          &(mem_info->mdl[i].dma));
1377                 }
1378         } else {
1379                 for (i = 0; i < mem_info->num; i++) {
1380                         mem_info->mdl[i].len = mem_info->len;
1381                         mem_info->mdl[i].kva = kzalloc(mem_info->len,
1382                                                         GFP_KERNEL);
1383                         if (mem_info->mdl[i].kva == NULL)
1384                                 goto err_return;
1385                 }
1386         }
1387
1388         return 0;
1389
1390 err_return:
1391         bnad_mem_free(bnad, mem_info);
1392         return -ENOMEM;
1393 }
1394
1395 /* Free IRQ for Mailbox */
1396 static void
1397 bnad_mbox_irq_free(struct bnad *bnad)
1398 {
1399         int irq;
1400         unsigned long flags;
1401
1402         spin_lock_irqsave(&bnad->bna_lock, flags);
1403         bnad_disable_mbox_irq(bnad);
1404         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1405
1406         irq = BNAD_GET_MBOX_IRQ(bnad);
1407         free_irq(irq, bnad);
1408 }
1409
1410 /*
1411  * Allocates IRQ for Mailbox, but keep it disabled
1412  * This will be enabled once we get the mbox enable callback
1413  * from bna
1414  */
1415 static int
1416 bnad_mbox_irq_alloc(struct bnad *bnad)
1417 {
1418         int             err = 0;
1419         unsigned long   irq_flags, flags;
1420         u32     irq;
1421         irq_handler_t   irq_handler;
1422
1423         spin_lock_irqsave(&bnad->bna_lock, flags);
1424         if (bnad->cfg_flags & BNAD_CF_MSIX) {
1425                 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1426                 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
1427                 irq_flags = 0;
1428         } else {
1429                 irq_handler = (irq_handler_t)bnad_isr;
1430                 irq = bnad->pcidev->irq;
1431                 irq_flags = IRQF_SHARED;
1432         }
1433
1434         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1435         sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1436
1437         /*
1438          * Set the Mbox IRQ disable flag, so that the IRQ handler
1439          * called from request_irq() for SHARED IRQs do not execute
1440          */
1441         set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1442
1443         BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1444
1445         err = request_irq(irq, irq_handler, irq_flags,
1446                           bnad->mbox_irq_name, bnad);
1447
1448         return err;
1449 }
1450
1451 static void
1452 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1453 {
1454         kfree(intr_info->idl);
1455         intr_info->idl = NULL;
1456 }
1457
1458 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1459 static int
1460 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1461                     u32 txrx_id, struct bna_intr_info *intr_info)
1462 {
1463         int i, vector_start = 0;
1464         u32 cfg_flags;
1465         unsigned long flags;
1466
1467         spin_lock_irqsave(&bnad->bna_lock, flags);
1468         cfg_flags = bnad->cfg_flags;
1469         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1470
1471         if (cfg_flags & BNAD_CF_MSIX) {
1472                 intr_info->intr_type = BNA_INTR_T_MSIX;
1473                 intr_info->idl = kcalloc(intr_info->num,
1474                                         sizeof(struct bna_intr_descr),
1475                                         GFP_KERNEL);
1476                 if (!intr_info->idl)
1477                         return -ENOMEM;
1478
1479                 switch (src) {
1480                 case BNAD_INTR_TX:
1481                         vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
1482                         break;
1483
1484                 case BNAD_INTR_RX:
1485                         vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1486                                         (bnad->num_tx * bnad->num_txq_per_tx) +
1487                                         txrx_id;
1488                         break;
1489
1490                 default:
1491                         BUG();
1492                 }
1493
1494                 for (i = 0; i < intr_info->num; i++)
1495                         intr_info->idl[i].vector = vector_start + i;
1496         } else {
1497                 intr_info->intr_type = BNA_INTR_T_INTX;
1498                 intr_info->num = 1;
1499                 intr_info->idl = kcalloc(intr_info->num,
1500                                         sizeof(struct bna_intr_descr),
1501                                         GFP_KERNEL);
1502                 if (!intr_info->idl)
1503                         return -ENOMEM;
1504
1505                 switch (src) {
1506                 case BNAD_INTR_TX:
1507                         intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
1508                         break;
1509
1510                 case BNAD_INTR_RX:
1511                         intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
1512                         break;
1513                 }
1514         }
1515         return 0;
1516 }
1517
1518 /* NOTE: Should be called for MSIX only
1519  * Unregisters Tx MSIX vector(s) from the kernel
1520  */
1521 static void
1522 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1523                         int num_txqs)
1524 {
1525         int i;
1526         int vector_num;
1527
1528         for (i = 0; i < num_txqs; i++) {
1529                 if (tx_info->tcb[i] == NULL)
1530                         continue;
1531
1532                 vector_num = tx_info->tcb[i]->intr_vector;
1533                 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1534         }
1535 }
1536
1537 /* NOTE: Should be called for MSIX only
1538  * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1539  */
1540 static int
1541 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1542                         u32 tx_id, int num_txqs)
1543 {
1544         int i;
1545         int err;
1546         int vector_num;
1547
1548         for (i = 0; i < num_txqs; i++) {
1549                 vector_num = tx_info->tcb[i]->intr_vector;
1550                 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1551                                 tx_id + tx_info->tcb[i]->id);
1552                 err = request_irq(bnad->msix_table[vector_num].vector,
1553                                   (irq_handler_t)bnad_msix_tx, 0,
1554                                   tx_info->tcb[i]->name,
1555                                   tx_info->tcb[i]);
1556                 if (err)
1557                         goto err_return;
1558         }
1559
1560         return 0;
1561
1562 err_return:
1563         if (i > 0)
1564                 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1565         return -1;
1566 }
1567
1568 /* NOTE: Should be called for MSIX only
1569  * Unregisters Rx MSIX vector(s) from the kernel
1570  */
1571 static void
1572 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1573                         int num_rxps)
1574 {
1575         int i;
1576         int vector_num;
1577
1578         for (i = 0; i < num_rxps; i++) {
1579                 if (rx_info->rx_ctrl[i].ccb == NULL)
1580                         continue;
1581
1582                 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1583                 free_irq(bnad->msix_table[vector_num].vector,
1584                          rx_info->rx_ctrl[i].ccb);
1585         }
1586 }
1587
1588 /* NOTE: Should be called for MSIX only
1589  * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1590  */
1591 static int
1592 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1593                         u32 rx_id, int num_rxps)
1594 {
1595         int i;
1596         int err;
1597         int vector_num;
1598
1599         for (i = 0; i < num_rxps; i++) {
1600                 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1601                 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1602                         bnad->netdev->name,
1603                         rx_id + rx_info->rx_ctrl[i].ccb->id);
1604                 err = request_irq(bnad->msix_table[vector_num].vector,
1605                                   (irq_handler_t)bnad_msix_rx, 0,
1606                                   rx_info->rx_ctrl[i].ccb->name,
1607                                   rx_info->rx_ctrl[i].ccb);
1608                 if (err)
1609                         goto err_return;
1610         }
1611
1612         return 0;
1613
1614 err_return:
1615         if (i > 0)
1616                 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1617         return -1;
1618 }
1619
1620 /* Free Tx object Resources */
1621 static void
1622 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1623 {
1624         int i;
1625
1626         for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1627                 if (res_info[i].res_type == BNA_RES_T_MEM)
1628                         bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1629                 else if (res_info[i].res_type == BNA_RES_T_INTR)
1630                         bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1631         }
1632 }
1633
1634 /* Allocates memory and interrupt resources for Tx object */
1635 static int
1636 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1637                   u32 tx_id)
1638 {
1639         int i, err = 0;
1640
1641         for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1642                 if (res_info[i].res_type == BNA_RES_T_MEM)
1643                         err = bnad_mem_alloc(bnad,
1644                                         &res_info[i].res_u.mem_info);
1645                 else if (res_info[i].res_type == BNA_RES_T_INTR)
1646                         err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1647                                         &res_info[i].res_u.intr_info);
1648                 if (err)
1649                         goto err_return;
1650         }
1651         return 0;
1652
1653 err_return:
1654         bnad_tx_res_free(bnad, res_info);
1655         return err;
1656 }
1657
1658 /* Free Rx object Resources */
1659 static void
1660 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1661 {
1662         int i;
1663
1664         for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1665                 if (res_info[i].res_type == BNA_RES_T_MEM)
1666                         bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1667                 else if (res_info[i].res_type == BNA_RES_T_INTR)
1668                         bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1669         }
1670 }
1671
1672 /* Allocates memory and interrupt resources for Rx object */
1673 static int
1674 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1675                   uint rx_id)
1676 {
1677         int i, err = 0;
1678
1679         /* All memory needs to be allocated before setup_ccbs */
1680         for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1681                 if (res_info[i].res_type == BNA_RES_T_MEM)
1682                         err = bnad_mem_alloc(bnad,
1683                                         &res_info[i].res_u.mem_info);
1684                 else if (res_info[i].res_type == BNA_RES_T_INTR)
1685                         err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1686                                         &res_info[i].res_u.intr_info);
1687                 if (err)
1688                         goto err_return;
1689         }
1690         return 0;
1691
1692 err_return:
1693         bnad_rx_res_free(bnad, res_info);
1694         return err;
1695 }
1696
1697 /* Timer callbacks */
1698 /* a) IOC timer */
1699 static void
1700 bnad_ioc_timeout(unsigned long data)
1701 {
1702         struct bnad *bnad = (struct bnad *)data;
1703         unsigned long flags;
1704
1705         spin_lock_irqsave(&bnad->bna_lock, flags);
1706         bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc);
1707         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1708 }
1709
1710 static void
1711 bnad_ioc_hb_check(unsigned long data)
1712 {
1713         struct bnad *bnad = (struct bnad *)data;
1714         unsigned long flags;
1715
1716         spin_lock_irqsave(&bnad->bna_lock, flags);
1717         bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc);
1718         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1719 }
1720
1721 static void
1722 bnad_iocpf_timeout(unsigned long data)
1723 {
1724         struct bnad *bnad = (struct bnad *)data;
1725         unsigned long flags;
1726
1727         spin_lock_irqsave(&bnad->bna_lock, flags);
1728         bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc);
1729         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1730 }
1731
1732 static void
1733 bnad_iocpf_sem_timeout(unsigned long data)
1734 {
1735         struct bnad *bnad = (struct bnad *)data;
1736         unsigned long flags;
1737
1738         spin_lock_irqsave(&bnad->bna_lock, flags);
1739         bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc);
1740         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1741 }
1742
1743 /*
1744  * All timer routines use bnad->bna_lock to protect against
1745  * the following race, which may occur in case of no locking:
1746  *      Time    CPU m   CPU n
1747  *      0       1 = test_bit
1748  *      1                       clear_bit
1749  *      2                       del_timer_sync
1750  *      3       mod_timer
1751  */
1752
1753 /* b) Dynamic Interrupt Moderation Timer */
1754 static void
1755 bnad_dim_timeout(unsigned long data)
1756 {
1757         struct bnad *bnad = (struct bnad *)data;
1758         struct bnad_rx_info *rx_info;
1759         struct bnad_rx_ctrl *rx_ctrl;
1760         int i, j;
1761         unsigned long flags;
1762
1763         if (!netif_carrier_ok(bnad->netdev))
1764                 return;
1765
1766         spin_lock_irqsave(&bnad->bna_lock, flags);
1767         for (i = 0; i < bnad->num_rx; i++) {
1768                 rx_info = &bnad->rx_info[i];
1769                 if (!rx_info->rx)
1770                         continue;
1771                 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1772                         rx_ctrl = &rx_info->rx_ctrl[j];
1773                         if (!rx_ctrl->ccb)
1774                                 continue;
1775                         bna_rx_dim_update(rx_ctrl->ccb);
1776                 }
1777         }
1778
1779         /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1780         if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1781                 mod_timer(&bnad->dim_timer,
1782                           jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1783         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1784 }
1785
1786 /* c)  Statistics Timer */
1787 static void
1788 bnad_stats_timeout(unsigned long data)
1789 {
1790         struct bnad *bnad = (struct bnad *)data;
1791         unsigned long flags;
1792
1793         if (!netif_running(bnad->netdev) ||
1794                 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1795                 return;
1796
1797         spin_lock_irqsave(&bnad->bna_lock, flags);
1798         bna_hw_stats_get(&bnad->bna);
1799         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1800 }
1801
1802 /*
1803  * Set up timer for DIM
1804  * Called with bnad->bna_lock held
1805  */
1806 void
1807 bnad_dim_timer_start(struct bnad *bnad)
1808 {
1809         if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1810             !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1811                 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1812                             (unsigned long)bnad);
1813                 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1814                 mod_timer(&bnad->dim_timer,
1815                           jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1816         }
1817 }
1818
1819 /*
1820  * Set up timer for statistics
1821  * Called with mutex_lock(&bnad->conf_mutex) held
1822  */
1823 static void
1824 bnad_stats_timer_start(struct bnad *bnad)
1825 {
1826         unsigned long flags;
1827
1828         spin_lock_irqsave(&bnad->bna_lock, flags);
1829         if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1830                 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1831                             (unsigned long)bnad);
1832                 mod_timer(&bnad->stats_timer,
1833                           jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1834         }
1835         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1836 }
1837
1838 /*
1839  * Stops the stats timer
1840  * Called with mutex_lock(&bnad->conf_mutex) held
1841  */
1842 static void
1843 bnad_stats_timer_stop(struct bnad *bnad)
1844 {
1845         int to_del = 0;
1846         unsigned long flags;
1847
1848         spin_lock_irqsave(&bnad->bna_lock, flags);
1849         if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1850                 to_del = 1;
1851         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1852         if (to_del)
1853                 del_timer_sync(&bnad->stats_timer);
1854 }
1855
1856 /* Utilities */
1857
1858 static void
1859 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1860 {
1861         int i = 1; /* Index 0 has broadcast address */
1862         struct netdev_hw_addr *mc_addr;
1863
1864         netdev_for_each_mc_addr(mc_addr, netdev) {
1865                 ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]);
1866                 i++;
1867         }
1868 }
1869
1870 static int
1871 bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1872 {
1873         struct bnad_rx_ctrl *rx_ctrl =
1874                 container_of(napi, struct bnad_rx_ctrl, napi);
1875         struct bnad *bnad = rx_ctrl->bnad;
1876         int rcvd = 0;
1877
1878         rx_ctrl->rx_poll_ctr++;
1879
1880         if (!netif_carrier_ok(bnad->netdev))
1881                 goto poll_exit;
1882
1883         rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
1884         if (rcvd >= budget)
1885                 return rcvd;
1886
1887 poll_exit:
1888         napi_complete(napi);
1889
1890         rx_ctrl->rx_complete++;
1891
1892         if (rx_ctrl->ccb)
1893                 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1894
1895         return rcvd;
1896 }
1897
1898 #define BNAD_NAPI_POLL_QUOTA            64
1899 static void
1900 bnad_napi_add(struct bnad *bnad, u32 rx_id)
1901 {
1902         struct bnad_rx_ctrl *rx_ctrl;
1903         int i;
1904
1905         /* Initialize & enable NAPI */
1906         for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1907                 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1908                 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1909                                bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1910         }
1911 }
1912
1913 static void
1914 bnad_napi_delete(struct bnad *bnad, u32 rx_id)
1915 {
1916         int i;
1917
1918         /* First disable and then clean up */
1919         for (i = 0; i < bnad->num_rxp_per_rx; i++)
1920                 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1921 }
1922
1923 /* Should be held with conf_lock held */
1924 void
1925 bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
1926 {
1927         struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1928         struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1929         unsigned long flags;
1930
1931         if (!tx_info->tx)
1932                 return;
1933
1934         init_completion(&bnad->bnad_completions.tx_comp);
1935         spin_lock_irqsave(&bnad->bna_lock, flags);
1936         bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1937         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1938         wait_for_completion(&bnad->bnad_completions.tx_comp);
1939
1940         if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1941                 bnad_tx_msix_unregister(bnad, tx_info,
1942                         bnad->num_txq_per_tx);
1943
1944         spin_lock_irqsave(&bnad->bna_lock, flags);
1945         bna_tx_destroy(tx_info->tx);
1946         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1947
1948         tx_info->tx = NULL;
1949         tx_info->tx_id = 0;
1950
1951         bnad_tx_res_free(bnad, res_info);
1952 }
1953
1954 /* Should be held with conf_lock held */
1955 int
1956 bnad_setup_tx(struct bnad *bnad, u32 tx_id)
1957 {
1958         int err;
1959         struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1960         struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1961         struct bna_intr_info *intr_info =
1962                         &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1963         struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1964         static const struct bna_tx_event_cbfn tx_cbfn = {
1965                 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1966                 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1967                 .tx_stall_cbfn = bnad_cb_tx_stall,
1968                 .tx_resume_cbfn = bnad_cb_tx_resume,
1969                 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1970         };
1971
1972         struct bna_tx *tx;
1973         unsigned long flags;
1974
1975         tx_info->tx_id = tx_id;
1976
1977         /* Initialize the Tx object configuration */
1978         tx_config->num_txq = bnad->num_txq_per_tx;
1979         tx_config->txq_depth = bnad->txq_depth;
1980         tx_config->tx_type = BNA_TX_T_REGULAR;
1981         tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
1982
1983         /* Get BNA's resource requirement for one tx object */
1984         spin_lock_irqsave(&bnad->bna_lock, flags);
1985         bna_tx_res_req(bnad->num_txq_per_tx,
1986                 bnad->txq_depth, res_info);
1987         spin_unlock_irqrestore(&bnad->bna_lock, flags);
1988
1989         /* Fill Unmap Q memory requirements */
1990         BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1991                         bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) *
1992                         bnad->txq_depth));
1993
1994         /* Allocate resources */
1995         err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1996         if (err)
1997                 return err;
1998
1999         /* Ask BNA to create one Tx object, supplying required resources */
2000         spin_lock_irqsave(&bnad->bna_lock, flags);
2001         tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
2002                         tx_info);
2003         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2004         if (!tx) {
2005                 err = -ENOMEM;
2006                 goto err_return;
2007         }
2008         tx_info->tx = tx;
2009
2010         INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
2011                         (work_func_t)bnad_tx_cleanup);
2012
2013         /* Register ISR for the Tx object */
2014         if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2015                 err = bnad_tx_msix_register(bnad, tx_info,
2016                         tx_id, bnad->num_txq_per_tx);
2017                 if (err)
2018                         goto cleanup_tx;
2019         }
2020
2021         spin_lock_irqsave(&bnad->bna_lock, flags);
2022         bna_tx_enable(tx);
2023         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2024
2025         return 0;
2026
2027 cleanup_tx:
2028         spin_lock_irqsave(&bnad->bna_lock, flags);
2029         bna_tx_destroy(tx_info->tx);
2030         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2031         tx_info->tx = NULL;
2032         tx_info->tx_id = 0;
2033 err_return:
2034         bnad_tx_res_free(bnad, res_info);
2035         return err;
2036 }
2037
2038 /* Setup the rx config for bna_rx_create */
2039 /* bnad decides the configuration */
2040 static void
2041 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
2042 {
2043         memset(rx_config, 0, sizeof(*rx_config));
2044         rx_config->rx_type = BNA_RX_T_REGULAR;
2045         rx_config->num_paths = bnad->num_rxp_per_rx;
2046         rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
2047
2048         if (bnad->num_rxp_per_rx > 1) {
2049                 rx_config->rss_status = BNA_STATUS_T_ENABLED;
2050                 rx_config->rss_config.hash_type =
2051                                 (BFI_ENET_RSS_IPV6 |
2052                                  BFI_ENET_RSS_IPV6_TCP |
2053                                  BFI_ENET_RSS_IPV4 |
2054                                  BFI_ENET_RSS_IPV4_TCP);
2055                 rx_config->rss_config.hash_mask =
2056                                 bnad->num_rxp_per_rx - 1;
2057                 netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key,
2058                         sizeof(rx_config->rss_config.toeplitz_hash_key));
2059         } else {
2060                 rx_config->rss_status = BNA_STATUS_T_DISABLED;
2061                 memset(&rx_config->rss_config, 0,
2062                        sizeof(rx_config->rss_config));
2063         }
2064
2065         rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu);
2066         rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED;
2067
2068         /* BNA_RXP_SINGLE - one data-buffer queue
2069          * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2070          * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2071          */
2072         /* TODO: configurable param for queue type */
2073         rx_config->rxp_type = BNA_RXP_SLR;
2074
2075         if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
2076             rx_config->frame_size > 4096) {
2077                 /* though size_routing_enable is set in SLR,
2078                  * small packets may get routed to same rxq.
2079                  * set buf_size to 2048 instead of PAGE_SIZE.
2080                  */
2081                 rx_config->q0_buf_size = 2048;
2082                 /* this should be in multiples of 2 */
2083                 rx_config->q0_num_vecs = 4;
2084                 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs;
2085                 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED;
2086         } else {
2087                 rx_config->q0_buf_size = rx_config->frame_size;
2088                 rx_config->q0_num_vecs = 1;
2089                 rx_config->q0_depth = bnad->rxq_depth;
2090         }
2091
2092         /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2093         if (rx_config->rxp_type == BNA_RXP_SLR) {
2094                 rx_config->q1_depth = bnad->rxq_depth;
2095                 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE;
2096         }
2097
2098         rx_config->vlan_strip_status =
2099                 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ?
2100                 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
2101 }
2102
2103 static void
2104 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
2105 {
2106         struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2107         int i;
2108
2109         for (i = 0; i < bnad->num_rxp_per_rx; i++)
2110                 rx_info->rx_ctrl[i].bnad = bnad;
2111 }
2112
2113 /* Called with mutex_lock(&bnad->conf_mutex) held */
2114 static u32
2115 bnad_reinit_rx(struct bnad *bnad)
2116 {
2117         struct net_device *netdev = bnad->netdev;
2118         u32 err = 0, current_err = 0;
2119         u32 rx_id = 0, count = 0;
2120         unsigned long flags;
2121
2122         /* destroy and create new rx objects */
2123         for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2124                 if (!bnad->rx_info[rx_id].rx)
2125                         continue;
2126                 bnad_destroy_rx(bnad, rx_id);
2127         }
2128
2129         spin_lock_irqsave(&bnad->bna_lock, flags);
2130         bna_enet_mtu_set(&bnad->bna.enet,
2131                          BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2132         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2133
2134         for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2135                 count++;
2136                 current_err = bnad_setup_rx(bnad, rx_id);
2137                 if (current_err && !err) {
2138                         err = current_err;
2139                         pr_err("RXQ:%u setup failed\n", rx_id);
2140                 }
2141         }
2142
2143         /* restore rx configuration */
2144         if (bnad->rx_info[0].rx && !err) {
2145                 bnad_restore_vlans(bnad, 0);
2146                 bnad_enable_default_bcast(bnad);
2147                 spin_lock_irqsave(&bnad->bna_lock, flags);
2148                 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2149                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2150                 bnad_set_rx_mode(netdev);
2151         }
2152
2153         return count;
2154 }
2155
2156 /* Called with bnad_conf_lock() held */
2157 void
2158 bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
2159 {
2160         struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2161         struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2162         struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2163         unsigned long flags;
2164         int to_del = 0;
2165
2166         if (!rx_info->rx)
2167                 return;
2168
2169         if (0 == rx_id) {
2170                 spin_lock_irqsave(&bnad->bna_lock, flags);
2171                 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
2172                     test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
2173                         clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
2174                         to_del = 1;
2175                 }
2176                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2177                 if (to_del)
2178                         del_timer_sync(&bnad->dim_timer);
2179         }
2180
2181         init_completion(&bnad->bnad_completions.rx_comp);
2182         spin_lock_irqsave(&bnad->bna_lock, flags);
2183         bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
2184         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2185         wait_for_completion(&bnad->bnad_completions.rx_comp);
2186
2187         if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
2188                 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
2189
2190         bnad_napi_delete(bnad, rx_id);
2191
2192         spin_lock_irqsave(&bnad->bna_lock, flags);
2193         bna_rx_destroy(rx_info->rx);
2194
2195         rx_info->rx = NULL;
2196         rx_info->rx_id = 0;
2197         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2198
2199         bnad_rx_res_free(bnad, res_info);
2200 }
2201
2202 /* Called with mutex_lock(&bnad->conf_mutex) held */
2203 int
2204 bnad_setup_rx(struct bnad *bnad, u32 rx_id)
2205 {
2206         int err;
2207         struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2208         struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2209         struct bna_intr_info *intr_info =
2210                         &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2211         struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2212         static const struct bna_rx_event_cbfn rx_cbfn = {
2213                 .rcb_setup_cbfn = NULL,
2214                 .rcb_destroy_cbfn = NULL,
2215                 .ccb_setup_cbfn = bnad_cb_ccb_setup,
2216                 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
2217                 .rx_stall_cbfn = bnad_cb_rx_stall,
2218                 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
2219                 .rx_post_cbfn = bnad_cb_rx_post,
2220         };
2221         struct bna_rx *rx;
2222         unsigned long flags;
2223
2224         rx_info->rx_id = rx_id;
2225
2226         /* Initialize the Rx object configuration */
2227         bnad_init_rx_config(bnad, rx_config);
2228
2229         /* Get BNA's resource requirement for one Rx object */
2230         spin_lock_irqsave(&bnad->bna_lock, flags);
2231         bna_rx_res_req(rx_config, res_info);
2232         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2233
2234         /* Fill Unmap Q memory requirements */
2235         BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ],
2236                                  rx_config->num_paths,
2237                         (rx_config->q0_depth *
2238                          sizeof(struct bnad_rx_unmap)) +
2239                          sizeof(struct bnad_rx_unmap_q));
2240
2241         if (rx_config->rxp_type != BNA_RXP_SINGLE) {
2242                 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ],
2243                                          rx_config->num_paths,
2244                                 (rx_config->q1_depth *
2245                                  sizeof(struct bnad_rx_unmap) +
2246                                  sizeof(struct bnad_rx_unmap_q)));
2247         }
2248         /* Allocate resource */
2249         err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2250         if (err)
2251                 return err;
2252
2253         bnad_rx_ctrl_init(bnad, rx_id);
2254
2255         /* Ask BNA to create one Rx object, supplying required resources */
2256         spin_lock_irqsave(&bnad->bna_lock, flags);
2257         rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2258                         rx_info);
2259         if (!rx) {
2260                 err = -ENOMEM;
2261                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2262                 goto err_return;
2263         }
2264         rx_info->rx = rx;
2265         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2266
2267         INIT_WORK(&rx_info->rx_cleanup_work,
2268                         (work_func_t)(bnad_rx_cleanup));
2269
2270         /*
2271          * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2272          * so that IRQ handler cannot schedule NAPI at this point.
2273          */
2274         bnad_napi_add(bnad, rx_id);
2275
2276         /* Register ISR for the Rx object */
2277         if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2278                 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2279                                                 rx_config->num_paths);
2280                 if (err)
2281                         goto err_return;
2282         }
2283
2284         spin_lock_irqsave(&bnad->bna_lock, flags);
2285         if (0 == rx_id) {
2286                 /* Set up Dynamic Interrupt Moderation Vector */
2287                 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2288                         bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2289
2290                 /* Enable VLAN filtering only on the default Rx */
2291                 bna_rx_vlanfilter_enable(rx);
2292
2293                 /* Start the DIM timer */
2294                 bnad_dim_timer_start(bnad);
2295         }
2296
2297         bna_rx_enable(rx);
2298         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2299
2300         return 0;
2301
2302 err_return:
2303         bnad_destroy_rx(bnad, rx_id);
2304         return err;
2305 }
2306
2307 /* Called with conf_lock & bnad->bna_lock held */
2308 void
2309 bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2310 {
2311         struct bnad_tx_info *tx_info;
2312
2313         tx_info = &bnad->tx_info[0];
2314         if (!tx_info->tx)
2315                 return;
2316
2317         bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2318 }
2319
2320 /* Called with conf_lock & bnad->bna_lock held */
2321 void
2322 bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2323 {
2324         struct bnad_rx_info *rx_info;
2325         int     i;
2326
2327         for (i = 0; i < bnad->num_rx; i++) {
2328                 rx_info = &bnad->rx_info[i];
2329                 if (!rx_info->rx)
2330                         continue;
2331                 bna_rx_coalescing_timeo_set(rx_info->rx,
2332                                 bnad->rx_coalescing_timeo);
2333         }
2334 }
2335
2336 /*
2337  * Called with bnad->bna_lock held
2338  */
2339 int
2340 bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2341 {
2342         int ret;
2343
2344         if (!is_valid_ether_addr(mac_addr))
2345                 return -EADDRNOTAVAIL;
2346
2347         /* If datapath is down, pretend everything went through */
2348         if (!bnad->rx_info[0].rx)
2349                 return 0;
2350
2351         ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr);
2352         if (ret != BNA_CB_SUCCESS)
2353                 return -EADDRNOTAVAIL;
2354
2355         return 0;
2356 }
2357
2358 /* Should be called with conf_lock held */
2359 int
2360 bnad_enable_default_bcast(struct bnad *bnad)
2361 {
2362         struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2363         int ret;
2364         unsigned long flags;
2365
2366         init_completion(&bnad->bnad_completions.mcast_comp);
2367
2368         spin_lock_irqsave(&bnad->bna_lock, flags);
2369         ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2370                                 bnad_cb_rx_mcast_add);
2371         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2372
2373         if (ret == BNA_CB_SUCCESS)
2374                 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2375         else
2376                 return -ENODEV;
2377
2378         if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2379                 return -ENODEV;
2380
2381         return 0;
2382 }
2383
2384 /* Called with mutex_lock(&bnad->conf_mutex) held */
2385 void
2386 bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2387 {
2388         u16 vid;
2389         unsigned long flags;
2390
2391         for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
2392                 spin_lock_irqsave(&bnad->bna_lock, flags);
2393                 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
2394                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2395         }
2396 }
2397
2398 /* Statistics utilities */
2399 void
2400 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2401 {
2402         int i, j;
2403
2404         for (i = 0; i < bnad->num_rx; i++) {
2405                 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2406                         if (bnad->rx_info[i].rx_ctrl[j].ccb) {
2407                                 stats->rx_packets += bnad->rx_info[i].
2408                                 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
2409                                 stats->rx_bytes += bnad->rx_info[i].
2410                                         rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2411                                 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2412                                         bnad->rx_info[i].rx_ctrl[j].ccb->
2413                                         rcb[1]->rxq) {
2414                                         stats->rx_packets +=
2415                                                 bnad->rx_info[i].rx_ctrl[j].
2416                                                 ccb->rcb[1]->rxq->rx_packets;
2417                                         stats->rx_bytes +=
2418                                                 bnad->rx_info[i].rx_ctrl[j].
2419                                                 ccb->rcb[1]->rxq->rx_bytes;
2420                                 }
2421                         }
2422                 }
2423         }
2424         for (i = 0; i < bnad->num_tx; i++) {
2425                 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2426                         if (bnad->tx_info[i].tcb[j]) {
2427                                 stats->tx_packets +=
2428                                 bnad->tx_info[i].tcb[j]->txq->tx_packets;
2429                                 stats->tx_bytes +=
2430                                         bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2431                         }
2432                 }
2433         }
2434 }
2435
2436 /*
2437  * Must be called with the bna_lock held.
2438  */
2439 void
2440 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2441 {
2442         struct bfi_enet_stats_mac *mac_stats;
2443         u32 bmap;
2444         int i;
2445
2446         mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
2447         stats->rx_errors =
2448                 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2449                 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2450                 mac_stats->rx_undersize;
2451         stats->tx_errors = mac_stats->tx_fcs_error +
2452                                         mac_stats->tx_undersize;
2453         stats->rx_dropped = mac_stats->rx_drop;
2454         stats->tx_dropped = mac_stats->tx_drop;
2455         stats->multicast = mac_stats->rx_multicast;
2456         stats->collisions = mac_stats->tx_total_collision;
2457
2458         stats->rx_length_errors = mac_stats->rx_frame_length_error;
2459
2460         /* receive ring buffer overflow  ?? */
2461
2462         stats->rx_crc_errors = mac_stats->rx_fcs_error;
2463         stats->rx_frame_errors = mac_stats->rx_alignment_error;
2464         /* recv'r fifo overrun */
2465         bmap = bna_rx_rid_mask(&bnad->bna);
2466         for (i = 0; bmap; i++) {
2467                 if (bmap & 1) {
2468                         stats->rx_fifo_errors +=
2469                                 bnad->stats.bna_stats->
2470                                         hw_stats.rxf_stats[i].frame_drops;
2471                         break;
2472                 }
2473                 bmap >>= 1;
2474         }
2475 }
2476
2477 static void
2478 bnad_mbox_irq_sync(struct bnad *bnad)
2479 {
2480         u32 irq;
2481         unsigned long flags;
2482
2483         spin_lock_irqsave(&bnad->bna_lock, flags);
2484         if (bnad->cfg_flags & BNAD_CF_MSIX)
2485                 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
2486         else
2487                 irq = bnad->pcidev->irq;
2488         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2489
2490         synchronize_irq(irq);
2491 }
2492
2493 /* Utility used by bnad_start_xmit, for doing TSO */
2494 static int
2495 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2496 {
2497         int err;
2498
2499         err = skb_cow_head(skb, 0);
2500         if (err < 0) {
2501                 BNAD_UPDATE_CTR(bnad, tso_err);
2502                 return err;
2503         }
2504
2505         /*
2506          * For TSO, the TCP checksum field is seeded with pseudo-header sum
2507          * excluding the length field.
2508          */
2509         if (vlan_get_protocol(skb) == htons(ETH_P_IP)) {
2510                 struct iphdr *iph = ip_hdr(skb);
2511
2512                 /* Do we really need these? */
2513                 iph->tot_len = 0;
2514                 iph->check = 0;
2515
2516                 tcp_hdr(skb)->check =
2517                         ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2518                                            IPPROTO_TCP, 0);
2519                 BNAD_UPDATE_CTR(bnad, tso4);
2520         } else {
2521                 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2522
2523                 ipv6h->payload_len = 0;
2524                 tcp_hdr(skb)->check =
2525                         ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2526                                          IPPROTO_TCP, 0);
2527                 BNAD_UPDATE_CTR(bnad, tso6);
2528         }
2529
2530         return 0;
2531 }
2532
2533 /*
2534  * Initialize Q numbers depending on Rx Paths
2535  * Called with bnad->bna_lock held, because of cfg_flags
2536  * access.
2537  */
2538 static void
2539 bnad_q_num_init(struct bnad *bnad)
2540 {
2541         int rxps;
2542
2543         rxps = min((uint)num_online_cpus(),
2544                         (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
2545
2546         if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2547                 rxps = 1;       /* INTx */
2548
2549         bnad->num_rx = 1;
2550         bnad->num_tx = 1;
2551         bnad->num_rxp_per_rx = rxps;
2552         bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2553 }
2554
2555 /*
2556  * Adjusts the Q numbers, given a number of msix vectors
2557  * Give preference to RSS as opposed to Tx priority Queues,
2558  * in such a case, just use 1 Tx Q
2559  * Called with bnad->bna_lock held b'cos of cfg_flags access
2560  */
2561 static void
2562 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
2563 {
2564         bnad->num_txq_per_tx = 1;
2565         if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx)  +
2566              bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2567             (bnad->cfg_flags & BNAD_CF_MSIX)) {
2568                 bnad->num_rxp_per_rx = msix_vectors -
2569                         (bnad->num_tx * bnad->num_txq_per_tx) -
2570                         BNAD_MAILBOX_MSIX_VECTORS;
2571         } else
2572                 bnad->num_rxp_per_rx = 1;
2573 }
2574
2575 /* Enable / disable ioceth */
2576 static int
2577 bnad_ioceth_disable(struct bnad *bnad)
2578 {
2579         unsigned long flags;
2580         int err = 0;
2581
2582         spin_lock_irqsave(&bnad->bna_lock, flags);
2583         init_completion(&bnad->bnad_completions.ioc_comp);
2584         bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
2585         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2586
2587         wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2588                 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2589
2590         err = bnad->bnad_completions.ioc_comp_status;
2591         return err;
2592 }
2593
2594 static int
2595 bnad_ioceth_enable(struct bnad *bnad)
2596 {
2597         int err = 0;
2598         unsigned long flags;
2599
2600         spin_lock_irqsave(&bnad->bna_lock, flags);
2601         init_completion(&bnad->bnad_completions.ioc_comp);
2602         bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2603         bna_ioceth_enable(&bnad->bna.ioceth);
2604         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2605
2606         wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2607                 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2608
2609         err = bnad->bnad_completions.ioc_comp_status;
2610
2611         return err;
2612 }
2613
2614 /* Free BNA resources */
2615 static void
2616 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2617                 u32 res_val_max)
2618 {
2619         int i;
2620
2621         for (i = 0; i < res_val_max; i++)
2622                 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2623 }
2624
2625 /* Allocates memory and interrupt resources for BNA */
2626 static int
2627 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2628                 u32 res_val_max)
2629 {
2630         int i, err;
2631
2632         for (i = 0; i < res_val_max; i++) {
2633                 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2634                 if (err)
2635                         goto err_return;
2636         }
2637         return 0;
2638
2639 err_return:
2640         bnad_res_free(bnad, res_info, res_val_max);
2641         return err;
2642 }
2643
2644 /* Interrupt enable / disable */
2645 static void
2646 bnad_enable_msix(struct bnad *bnad)
2647 {
2648         int i, ret;
2649         unsigned long flags;
2650
2651         spin_lock_irqsave(&bnad->bna_lock, flags);
2652         if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2653                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2654                 return;
2655         }
2656         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2657
2658         if (bnad->msix_table)
2659                 return;
2660
2661         bnad->msix_table =
2662                 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2663
2664         if (!bnad->msix_table)
2665                 goto intx_mode;
2666
2667         for (i = 0; i < bnad->msix_num; i++)
2668                 bnad->msix_table[i].entry = i;
2669
2670         ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table,
2671                                     1, bnad->msix_num);
2672         if (ret < 0) {
2673                 goto intx_mode;
2674         } else if (ret < bnad->msix_num) {
2675                 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2676                         ret, bnad->msix_num);
2677
2678                 spin_lock_irqsave(&bnad->bna_lock, flags);
2679                 /* ret = #of vectors that we got */
2680                 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2681                         (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
2682                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2683
2684                 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
2685                          BNAD_MAILBOX_MSIX_VECTORS;
2686
2687                 if (bnad->msix_num > ret) {
2688                         pci_disable_msix(bnad->pcidev);
2689                         goto intx_mode;
2690                 }
2691         }
2692
2693         pci_intx(bnad->pcidev, 0);
2694
2695         return;
2696
2697 intx_mode:
2698         pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
2699
2700         kfree(bnad->msix_table);
2701         bnad->msix_table = NULL;
2702         bnad->msix_num = 0;
2703         spin_lock_irqsave(&bnad->bna_lock, flags);
2704         bnad->cfg_flags &= ~BNAD_CF_MSIX;
2705         bnad_q_num_init(bnad);
2706         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2707 }
2708
2709 static void
2710 bnad_disable_msix(struct bnad *bnad)
2711 {
2712         u32 cfg_flags;
2713         unsigned long flags;
2714
2715         spin_lock_irqsave(&bnad->bna_lock, flags);
2716         cfg_flags = bnad->cfg_flags;
2717         if (bnad->cfg_flags & BNAD_CF_MSIX)
2718                 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2719         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2720
2721         if (cfg_flags & BNAD_CF_MSIX) {
2722                 pci_disable_msix(bnad->pcidev);
2723                 kfree(bnad->msix_table);
2724                 bnad->msix_table = NULL;
2725         }
2726 }
2727
2728 /* Netdev entry points */
2729 static int
2730 bnad_open(struct net_device *netdev)
2731 {
2732         int err;
2733         struct bnad *bnad = netdev_priv(netdev);
2734         struct bna_pause_config pause_config;
2735         unsigned long flags;
2736
2737         mutex_lock(&bnad->conf_mutex);
2738
2739         /* Tx */
2740         err = bnad_setup_tx(bnad, 0);
2741         if (err)
2742                 goto err_return;
2743
2744         /* Rx */
2745         err = bnad_setup_rx(bnad, 0);
2746         if (err)
2747                 goto cleanup_tx;
2748
2749         /* Port */
2750         pause_config.tx_pause = 0;
2751         pause_config.rx_pause = 0;
2752
2753         spin_lock_irqsave(&bnad->bna_lock, flags);
2754         bna_enet_mtu_set(&bnad->bna.enet,
2755                          BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2756         bna_enet_pause_config(&bnad->bna.enet, &pause_config);
2757         bna_enet_enable(&bnad->bna.enet);
2758         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2759
2760         /* Enable broadcast */
2761         bnad_enable_default_bcast(bnad);
2762
2763         /* Restore VLANs, if any */
2764         bnad_restore_vlans(bnad, 0);
2765
2766         /* Set the UCAST address */
2767         spin_lock_irqsave(&bnad->bna_lock, flags);
2768         bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2769         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2770
2771         /* Start the stats timer */
2772         bnad_stats_timer_start(bnad);
2773
2774         mutex_unlock(&bnad->conf_mutex);
2775
2776         return 0;
2777
2778 cleanup_tx:
2779         bnad_destroy_tx(bnad, 0);
2780
2781 err_return:
2782         mutex_unlock(&bnad->conf_mutex);
2783         return err;
2784 }
2785
2786 static int
2787 bnad_stop(struct net_device *netdev)
2788 {
2789         struct bnad *bnad = netdev_priv(netdev);
2790         unsigned long flags;
2791
2792         mutex_lock(&bnad->conf_mutex);
2793
2794         /* Stop the stats timer */
2795         bnad_stats_timer_stop(bnad);
2796
2797         init_completion(&bnad->bnad_completions.enet_comp);
2798
2799         spin_lock_irqsave(&bnad->bna_lock, flags);
2800         bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2801                         bnad_cb_enet_disabled);
2802         spin_unlock_irqrestore(&bnad->bna_lock, flags);
2803
2804         wait_for_completion(&bnad->bnad_completions.enet_comp);
2805
2806         bnad_destroy_tx(bnad, 0);
2807         bnad_destroy_rx(bnad, 0);
2808
2809         /* Synchronize mailbox IRQ */
2810         bnad_mbox_irq_sync(bnad);
2811
2812         mutex_unlock(&bnad->conf_mutex);
2813
2814         return 0;
2815 }
2816
2817 /* TX */
2818 /* Returns 0 for success */
2819 static int
2820 bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb,
2821                     struct sk_buff *skb, struct bna_txq_entry *txqent)
2822 {
2823         u16 flags = 0;
2824         u32 gso_size;
2825         u16 vlan_tag = 0;
2826
2827         if (skb_vlan_tag_present(skb)) {
2828                 vlan_tag = (u16)skb_vlan_tag_get(skb);
2829                 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2830         }
2831         if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2832                 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT)
2833                                 | (vlan_tag & 0x1fff);
2834                 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2835         }
2836         txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2837
2838         if (skb_is_gso(skb)) {
2839                 gso_size = skb_shinfo(skb)->gso_size;
2840                 if (unlikely(gso_size > bnad->netdev->mtu)) {
2841                         BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
2842                         return -EINVAL;
2843                 }
2844                 if (unlikely((gso_size + skb_transport_offset(skb) +
2845                               tcp_hdrlen(skb)) >= skb->len)) {
2846                         txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
2847                         txqent->hdr.wi.lso_mss = 0;
2848                         BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2849                 } else {
2850                         txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO);
2851                         txqent->hdr.wi.lso_mss = htons(gso_size);
2852                 }
2853
2854                 if (bnad_tso_prepare(bnad, skb)) {
2855                         BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
2856                         return -EINVAL;
2857                 }
2858
2859                 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2860                 txqent->hdr.wi.l4_hdr_size_n_offset =
2861                         htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2862                         tcp_hdrlen(skb) >> 2, skb_transport_offset(skb)));
2863         } else  {
2864                 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
2865                 txqent->hdr.wi.lso_mss = 0;
2866
2867                 if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) {
2868                         BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
2869                         return -EINVAL;
2870                 }
2871
2872                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2873                         __be16 net_proto = vlan_get_protocol(skb);
2874                         u8 proto = 0;
2875
2876                         if (net_proto == htons(ETH_P_IP))
2877                                 proto = ip_hdr(skb)->protocol;
2878 #ifdef NETIF_F_IPV6_CSUM
2879                         else if (net_proto == htons(ETH_P_IPV6)) {
2880                                 /* nexthdr may not be TCP immediately. */
2881                                 proto = ipv6_hdr(skb)->nexthdr;
2882                         }
2883 #endif
2884                         if (proto == IPPROTO_TCP) {
2885                                 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2886                                 txqent->hdr.wi.l4_hdr_size_n_offset =
2887                                         htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2888                                               (0, skb_transport_offset(skb)));
2889
2890                                 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2891
2892                                 if (unlikely(skb_headlen(skb) <
2893                                             skb_transport_offset(skb) +
2894                                     tcp_hdrlen(skb))) {
2895                                         BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
2896                                         return -EINVAL;
2897                                 }
2898                         } else if (proto == IPPROTO_UDP) {
2899                                 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2900                                 txqent->hdr.wi.l4_hdr_size_n_offset =
2901                                         htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2902                                               (0, skb_transport_offset(skb)));
2903
2904                                 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2905                                 if (unlikely(skb_headlen(skb) <
2906                                             skb_transport_offset(skb) +
2907                                     sizeof(struct udphdr))) {
2908                                         BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
2909                                         return -EINVAL;
2910                                 }
2911                         } else {
2912
2913                                 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
2914                                 return -EINVAL;
2915                         }
2916                 } else
2917                         txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2918         }
2919
2920         txqent->hdr.wi.flags = htons(flags);
2921         txqent->hdr.wi.frame_length = htonl(skb->len);
2922
2923         return 0;
2924 }
2925
2926 /*
2927  * bnad_start_xmit : Netdev entry point for Transmit
2928  *                   Called under lock held by net_device
2929  */
2930 static netdev_tx_t
2931 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2932 {
2933         struct bnad *bnad = netdev_priv(netdev);
2934         u32 txq_id = 0;
2935         struct bna_tcb *tcb = NULL;
2936         struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap;
2937         u32             prod, q_depth, vect_id;
2938         u32             wis, vectors, len;
2939         int             i;
2940         dma_addr_t              dma_addr;
2941         struct bna_txq_entry *txqent;
2942
2943         len = skb_headlen(skb);
2944
2945         /* Sanity checks for the skb */
2946
2947         if (unlikely(skb->len <= ETH_HLEN)) {
2948                 dev_kfree_skb_any(skb);
2949                 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2950                 return NETDEV_TX_OK;
2951         }
2952         if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) {
2953                 dev_kfree_skb_any(skb);
2954                 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2955                 return NETDEV_TX_OK;
2956         }
2957         if (unlikely(len == 0)) {
2958                 dev_kfree_skb_any(skb);
2959                 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2960                 return NETDEV_TX_OK;
2961         }
2962
2963         tcb = bnad->tx_info[0].tcb[txq_id];
2964
2965         /*
2966          * Takes care of the Tx that is scheduled between clearing the flag
2967          * and the netif_tx_stop_all_queues() call.
2968          */
2969         if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
2970                 dev_kfree_skb_any(skb);
2971                 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2972                 return NETDEV_TX_OK;
2973         }
2974
2975         q_depth = tcb->q_depth;
2976         prod = tcb->producer_index;
2977         unmap_q = tcb->unmap_q;
2978
2979         vectors = 1 + skb_shinfo(skb)->nr_frags;
2980         wis = BNA_TXQ_WI_NEEDED(vectors);       /* 4 vectors per work item */
2981
2982         if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
2983                 dev_kfree_skb_any(skb);
2984                 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2985                 return NETDEV_TX_OK;
2986         }
2987
2988         /* Check for available TxQ resources */
2989         if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2990                 if ((*tcb->hw_consumer_index != tcb->consumer_index) &&
2991                     !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2992                         u32 sent;
2993                         sent = bnad_txcmpl_process(bnad, tcb);
2994                         if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2995                                 bna_ib_ack(tcb->i_dbell, sent);
2996                         smp_mb__before_atomic();
2997                         clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2998                 } else {
2999                         netif_stop_queue(netdev);
3000                         BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3001                 }
3002
3003                 smp_mb();
3004                 /*
3005                  * Check again to deal with race condition between
3006                  * netif_stop_queue here, and netif_wake_queue in
3007                  * interrupt handler which is not inside netif tx lock.
3008                  */
3009                 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
3010                         BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3011                         return NETDEV_TX_BUSY;
3012                 } else {
3013                         netif_wake_queue(netdev);
3014                         BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
3015                 }
3016         }
3017
3018         txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3019         head_unmap = &unmap_q[prod];
3020
3021         /* Program the opcode, flags, frame_len, num_vectors in WI */
3022         if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) {
3023                 dev_kfree_skb_any(skb);
3024                 return NETDEV_TX_OK;
3025         }
3026         txqent->hdr.wi.reserved = 0;
3027         txqent->hdr.wi.num_vectors = vectors;
3028
3029         head_unmap->skb = skb;
3030         head_unmap->nvecs = 0;
3031
3032         /* Program the vectors */
3033         unmap = head_unmap;
3034         dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
3035                                   len, DMA_TO_DEVICE);
3036         BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
3037         txqent->vector[0].length = htons(len);
3038         dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr);
3039         head_unmap->nvecs++;
3040
3041         for (i = 0, vect_id = 0; i < vectors - 1; i++) {
3042                 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
3043                 u32             size = skb_frag_size(frag);
3044
3045                 if (unlikely(size == 0)) {
3046                         /* Undo the changes starting at tcb->producer_index */
3047                         bnad_tx_buff_unmap(bnad, unmap_q, q_depth,
3048                                 tcb->producer_index);
3049                         dev_kfree_skb_any(skb);
3050                         BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
3051                         return NETDEV_TX_OK;
3052                 }
3053
3054                 len += size;
3055
3056                 vect_id++;
3057                 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
3058                         vect_id = 0;
3059                         BNA_QE_INDX_INC(prod, q_depth);
3060                         txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3061                         txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
3062                         unmap = &unmap_q[prod];
3063                 }
3064
3065                 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
3066                                             0, size, DMA_TO_DEVICE);
3067                 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size);
3068                 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
3069                 txqent->vector[vect_id].length = htons(size);
3070                 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr,
3071                                    dma_addr);
3072                 head_unmap->nvecs++;
3073         }
3074
3075         if (unlikely(len != skb->len)) {
3076                 /* Undo the changes starting at tcb->producer_index */
3077                 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index);
3078                 dev_kfree_skb_any(skb);
3079                 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
3080                 return NETDEV_TX_OK;
3081         }
3082
3083         BNA_QE_INDX_INC(prod, q_depth);
3084         tcb->producer_index = prod;
3085
3086         smp_mb();
3087
3088         if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3089                 return NETDEV_TX_OK;
3090
3091         skb_tx_timestamp(skb);
3092
3093         bna_txq_prod_indx_doorbell(tcb);
3094         smp_mb();
3095
3096         return NETDEV_TX_OK;
3097 }
3098
3099 /*
3100  * Used spin_lock to synchronize reading of stats structures, which
3101  * is written by BNA under the same lock.
3102  */
3103 static struct rtnl_link_stats64 *
3104 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
3105 {
3106         struct bnad *bnad = netdev_priv(netdev);
3107         unsigned long flags;
3108
3109         spin_lock_irqsave(&bnad->bna_lock, flags);
3110
3111         bnad_netdev_qstats_fill(bnad, stats);
3112         bnad_netdev_hwstats_fill(bnad, stats);
3113
3114         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3115
3116         return stats;
3117 }
3118
3119 static void
3120 bnad_set_rx_ucast_fltr(struct bnad *bnad)
3121 {
3122         struct net_device *netdev = bnad->netdev;
3123         int uc_count = netdev_uc_count(netdev);
3124         enum bna_cb_status ret;
3125         u8 *mac_list;
3126         struct netdev_hw_addr *ha;
3127         int entry;
3128
3129         if (netdev_uc_empty(bnad->netdev)) {
3130                 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
3131                 return;
3132         }
3133
3134         if (uc_count > bna_attr(&bnad->bna)->num_ucmac)
3135                 goto mode_default;
3136
3137         mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC);
3138         if (mac_list == NULL)
3139                 goto mode_default;
3140
3141         entry = 0;
3142         netdev_for_each_uc_addr(ha, netdev) {
3143                 ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]);
3144                 entry++;
3145         }
3146
3147         ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list);
3148         kfree(mac_list);
3149
3150         if (ret != BNA_CB_SUCCESS)
3151                 goto mode_default;
3152
3153         return;
3154
3155         /* ucast packets not in UCAM are routed to default function */
3156 mode_default:
3157         bnad->cfg_flags |= BNAD_CF_DEFAULT;
3158         bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
3159 }
3160
3161 static void
3162 bnad_set_rx_mcast_fltr(struct bnad *bnad)
3163 {
3164         struct net_device *netdev = bnad->netdev;
3165         int mc_count = netdev_mc_count(netdev);
3166         enum bna_cb_status ret;
3167         u8 *mac_list;
3168
3169         if (netdev->flags & IFF_ALLMULTI)
3170                 goto mode_allmulti;
3171
3172         if (netdev_mc_empty(netdev))
3173                 return;
3174
3175         if (mc_count > bna_attr(&bnad->bna)->num_mcmac)
3176                 goto mode_allmulti;
3177
3178         mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC);
3179
3180         if (mac_list == NULL)
3181                 goto mode_allmulti;
3182
3183         ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]);
3184
3185         /* copy rest of the MCAST addresses */
3186         bnad_netdev_mc_list_get(netdev, mac_list);
3187         ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list);
3188         kfree(mac_list);
3189
3190         if (ret != BNA_CB_SUCCESS)
3191                 goto mode_allmulti;
3192
3193         return;
3194
3195 mode_allmulti:
3196         bnad->cfg_flags |= BNAD_CF_ALLMULTI;
3197         bna_rx_mcast_delall(bnad->rx_info[0].rx);
3198 }
3199
3200 void
3201 bnad_set_rx_mode(struct net_device *netdev)
3202 {
3203         struct bnad *bnad = netdev_priv(netdev);
3204         enum bna_rxmode new_mode, mode_mask;
3205         unsigned long flags;
3206
3207         spin_lock_irqsave(&bnad->bna_lock, flags);
3208
3209         if (bnad->rx_info[0].rx == NULL) {
3210                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3211                 return;
3212         }
3213
3214         /* clear bnad flags to update it with new settings */
3215         bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT |
3216                         BNAD_CF_ALLMULTI);
3217
3218         new_mode = 0;
3219         if (netdev->flags & IFF_PROMISC) {
3220                 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT;
3221                 bnad->cfg_flags |= BNAD_CF_PROMISC;
3222         } else {
3223                 bnad_set_rx_mcast_fltr(bnad);
3224
3225                 if (bnad->cfg_flags & BNAD_CF_ALLMULTI)
3226                         new_mode |= BNA_RXMODE_ALLMULTI;
3227
3228                 bnad_set_rx_ucast_fltr(bnad);
3229
3230                 if (bnad->cfg_flags & BNAD_CF_DEFAULT)
3231                         new_mode |= BNA_RXMODE_DEFAULT;
3232         }
3233
3234         mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
3235                         BNA_RXMODE_ALLMULTI;
3236         bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask);
3237
3238         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3239 }
3240
3241 /*
3242  * bna_lock is used to sync writes to netdev->addr
3243  * conf_lock cannot be used since this call may be made
3244  * in a non-blocking context.
3245  */
3246 static int
3247 bnad_set_mac_address(struct net_device *netdev, void *addr)
3248 {
3249         int err;
3250         struct bnad *bnad = netdev_priv(netdev);
3251         struct sockaddr *sa = (struct sockaddr *)addr;
3252         unsigned long flags;
3253
3254         spin_lock_irqsave(&bnad->bna_lock, flags);
3255
3256         err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
3257         if (!err)
3258                 ether_addr_copy(netdev->dev_addr, sa->sa_data);
3259
3260         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3261
3262         return err;
3263 }
3264
3265 static int
3266 bnad_mtu_set(struct bnad *bnad, int frame_size)
3267 {
3268         unsigned long flags;
3269
3270         init_completion(&bnad->bnad_completions.mtu_comp);
3271
3272         spin_lock_irqsave(&bnad->bna_lock, flags);
3273         bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set);
3274         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3275
3276         wait_for_completion(&bnad->bnad_completions.mtu_comp);
3277
3278         return bnad->bnad_completions.mtu_comp_status;
3279 }
3280
3281 static int
3282 bnad_change_mtu(struct net_device *netdev, int new_mtu)
3283 {
3284         int err, mtu;
3285         struct bnad *bnad = netdev_priv(netdev);
3286         u32 rx_count = 0, frame, new_frame;
3287
3288         if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3289                 return -EINVAL;
3290
3291         mutex_lock(&bnad->conf_mutex);
3292
3293         mtu = netdev->mtu;
3294         netdev->mtu = new_mtu;
3295
3296         frame = BNAD_FRAME_SIZE(mtu);
3297         new_frame = BNAD_FRAME_SIZE(new_mtu);
3298
3299         /* check if multi-buffer needs to be enabled */
3300         if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
3301             netif_running(bnad->netdev)) {
3302                 /* only when transition is over 4K */
3303                 if ((frame <= 4096 && new_frame > 4096) ||
3304                     (frame > 4096 && new_frame <= 4096))
3305                         rx_count = bnad_reinit_rx(bnad);
3306         }
3307
3308         /* rx_count > 0 - new rx created
3309          *      - Linux set err = 0 and return
3310          */
3311         err = bnad_mtu_set(bnad, new_frame);
3312         if (err)
3313                 err = -EBUSY;
3314
3315         mutex_unlock(&bnad->conf_mutex);
3316         return err;
3317 }
3318
3319 static int
3320 bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
3321 {
3322         struct bnad *bnad = netdev_priv(netdev);
3323         unsigned long flags;
3324
3325         if (!bnad->rx_info[0].rx)
3326                 return 0;
3327
3328         mutex_lock(&bnad->conf_mutex);
3329
3330         spin_lock_irqsave(&bnad->bna_lock, flags);
3331         bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
3332         set_bit(vid, bnad->active_vlans);
3333         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3334
3335         mutex_unlock(&bnad->conf_mutex);
3336
3337         return 0;
3338 }
3339
3340 static int
3341 bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
3342 {
3343         struct bnad *bnad = netdev_priv(netdev);
3344         unsigned long flags;
3345
3346         if (!bnad->rx_info[0].rx)
3347                 return 0;
3348
3349         mutex_lock(&bnad->conf_mutex);
3350
3351         spin_lock_irqsave(&bnad->bna_lock, flags);
3352         clear_bit(vid, bnad->active_vlans);
3353         bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3354         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3355
3356         mutex_unlock(&bnad->conf_mutex);
3357
3358         return 0;
3359 }
3360
3361 static int bnad_set_features(struct net_device *dev, netdev_features_t features)
3362 {
3363         struct bnad *bnad = netdev_priv(dev);
3364         netdev_features_t changed = features ^ dev->features;
3365
3366         if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) {
3367                 unsigned long flags;
3368
3369                 spin_lock_irqsave(&bnad->bna_lock, flags);
3370
3371                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3372                         bna_rx_vlan_strip_enable(bnad->rx_info[0].rx);
3373                 else
3374                         bna_rx_vlan_strip_disable(bnad->rx_info[0].rx);
3375
3376                 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3377         }
3378
3379         return 0;
3380 }
3381
3382 #ifdef CONFIG_NET_POLL_CONTROLLER
3383 static void
3384 bnad_netpoll(struct net_device *netdev)
3385 {
3386         struct bnad *bnad = netdev_priv(netdev);
3387         struct bnad_rx_info *rx_info;
3388         struct bnad_rx_ctrl *rx_ctrl;
3389         u32 curr_mask;
3390         int i, j;
3391
3392         if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3393                 bna_intx_disable(&bnad->bna, curr_mask);
3394                 bnad_isr(bnad->pcidev->irq, netdev);
3395                 bna_intx_enable(&bnad->bna, curr_mask);
3396         } else {
3397                 /*
3398                  * Tx processing may happen in sending context, so no need
3399                  * to explicitly process completions here
3400                  */
3401
3402                 /* Rx processing */
3403                 for (i = 0; i < bnad->num_rx; i++) {
3404                         rx_info = &bnad->rx_info[i];
3405                         if (!rx_info->rx)
3406                                 continue;
3407                         for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3408                                 rx_ctrl = &rx_info->rx_ctrl[j];
3409                                 if (rx_ctrl->ccb)
3410                                         bnad_netif_rx_schedule_poll(bnad,
3411                                                             rx_ctrl->ccb);
3412                         }
3413                 }
3414         }
3415 }
3416 #endif
3417
3418 static const struct net_device_ops bnad_netdev_ops = {
3419         .ndo_open               = bnad_open,
3420         .ndo_stop               = bnad_stop,
3421         .ndo_start_xmit         = bnad_start_xmit,
3422         .ndo_get_stats64                = bnad_get_stats64,
3423         .ndo_set_rx_mode        = bnad_set_rx_mode,
3424         .ndo_validate_addr      = eth_validate_addr,
3425         .ndo_set_mac_address    = bnad_set_mac_address,
3426         .ndo_change_mtu         = bnad_change_mtu,
3427         .ndo_vlan_rx_add_vid    = bnad_vlan_rx_add_vid,
3428         .ndo_vlan_rx_kill_vid   = bnad_vlan_rx_kill_vid,
3429         .ndo_set_features       = bnad_set_features,
3430 #ifdef CONFIG_NET_POLL_CONTROLLER
3431         .ndo_poll_controller    = bnad_netpoll
3432 #endif
3433 };
3434
3435 static void
3436 bnad_netdev_init(struct bnad *bnad, bool using_dac)
3437 {
3438         struct net_device *netdev = bnad->netdev;
3439
3440         netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3441                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3442                 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX |
3443                 NETIF_F_HW_VLAN_CTAG_RX;
3444
3445         netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3446                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3447                 NETIF_F_TSO | NETIF_F_TSO6;
3448
3449         netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3450
3451         if (using_dac)
3452                 netdev->features |= NETIF_F_HIGHDMA;
3453
3454         netdev->mem_start = bnad->mmio_start;
3455         netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3456
3457         netdev->netdev_ops = &bnad_netdev_ops;
3458         bnad_set_ethtool_ops(netdev);
3459 }
3460
3461 /*
3462  * 1. Initialize the bnad structure
3463  * 2. Setup netdev pointer in pci_dev
3464  * 3. Initialize no. of TxQ & CQs & MSIX vectors
3465  * 4. Initialize work queue.
3466  */
3467 static int
3468 bnad_init(struct bnad *bnad,
3469           struct pci_dev *pdev, struct net_device *netdev)
3470 {
3471         unsigned long flags;
3472
3473         SET_NETDEV_DEV(netdev, &pdev->dev);
3474         pci_set_drvdata(pdev, netdev);
3475
3476         bnad->netdev = netdev;
3477         bnad->pcidev = pdev;
3478         bnad->mmio_start = pci_resource_start(pdev, 0);
3479         bnad->mmio_len = pci_resource_len(pdev, 0);
3480         bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3481         if (!bnad->bar0) {
3482                 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3483                 return -ENOMEM;
3484         }
3485         pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3486                (unsigned long long) bnad->mmio_len);
3487
3488         spin_lock_irqsave(&bnad->bna_lock, flags);
3489         if (!bnad_msix_disable)
3490                 bnad->cfg_flags = BNAD_CF_MSIX;
3491
3492         bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3493
3494         bnad_q_num_init(bnad);
3495         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3496
3497         bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3498                 (bnad->num_rx * bnad->num_rxp_per_rx) +
3499                          BNAD_MAILBOX_MSIX_VECTORS;
3500
3501         bnad->txq_depth = BNAD_TXQ_DEPTH;
3502         bnad->rxq_depth = BNAD_RXQ_DEPTH;
3503
3504         bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3505         bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3506
3507         sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3508         bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
3509         if (!bnad->work_q) {
3510                 iounmap(bnad->bar0);
3511                 return -ENOMEM;
3512         }
3513
3514         return 0;
3515 }
3516
3517 /*
3518  * Must be called after bnad_pci_uninit()
3519  * so that iounmap() and pci_set_drvdata(NULL)
3520  * happens only after PCI uninitialization.
3521  */
3522 static void
3523 bnad_uninit(struct bnad *bnad)
3524 {
3525         if (bnad->work_q) {
3526                 flush_workqueue(bnad->work_q);
3527                 destroy_workqueue(bnad->work_q);
3528                 bnad->work_q = NULL;
3529         }
3530
3531         if (bnad->bar0)
3532                 iounmap(bnad->bar0);
3533 }
3534
3535 /*
3536  * Initialize locks
3537         a) Per ioceth mutes used for serializing configuration
3538            changes from OS interface
3539         b) spin lock used to protect bna state machine
3540  */
3541 static void
3542 bnad_lock_init(struct bnad *bnad)
3543 {
3544         spin_lock_init(&bnad->bna_lock);
3545         mutex_init(&bnad->conf_mutex);
3546         mutex_init(&bnad_list_mutex);
3547 }
3548
3549 static void
3550 bnad_lock_uninit(struct bnad *bnad)
3551 {
3552         mutex_destroy(&bnad->conf_mutex);
3553         mutex_destroy(&bnad_list_mutex);
3554 }
3555
3556 /* PCI Initialization */
3557 static int
3558 bnad_pci_init(struct bnad *bnad,
3559               struct pci_dev *pdev, bool *using_dac)
3560 {
3561         int err;
3562
3563         err = pci_enable_device(pdev);
3564         if (err)
3565                 return err;
3566         err = pci_request_regions(pdev, BNAD_NAME);
3567         if (err)
3568                 goto disable_device;
3569         if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
3570                 *using_dac = true;
3571         } else {
3572                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3573                 if (err)
3574                         goto release_regions;
3575                 *using_dac = false;
3576         }
3577         pci_set_master(pdev);
3578         return 0;
3579
3580 release_regions:
3581         pci_release_regions(pdev);
3582 disable_device:
3583         pci_disable_device(pdev);
3584
3585         return err;
3586 }
3587
3588 static void
3589 bnad_pci_uninit(struct pci_dev *pdev)
3590 {
3591         pci_release_regions(pdev);
3592         pci_disable_device(pdev);
3593 }
3594
3595 static int
3596 bnad_pci_probe(struct pci_dev *pdev,
3597                 const struct pci_device_id *pcidev_id)
3598 {
3599         bool    using_dac;
3600         int     err;
3601         struct bnad *bnad;
3602         struct bna *bna;
3603         struct net_device *netdev;
3604         struct bfa_pcidev pcidev_info;
3605         unsigned long flags;
3606
3607         pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3608                pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3609
3610         mutex_lock(&bnad_fwimg_mutex);
3611         if (!cna_get_firmware_buf(pdev)) {
3612                 mutex_unlock(&bnad_fwimg_mutex);
3613                 pr_warn("Failed to load Firmware Image!\n");
3614                 return -ENODEV;
3615         }
3616         mutex_unlock(&bnad_fwimg_mutex);
3617
3618         /*
3619          * Allocates sizeof(struct net_device + struct bnad)
3620          * bnad = netdev->priv
3621          */
3622         netdev = alloc_etherdev(sizeof(struct bnad));
3623         if (!netdev) {
3624                 err = -ENOMEM;
3625                 return err;
3626         }
3627         bnad = netdev_priv(netdev);
3628         bnad_lock_init(bnad);
3629         bnad_add_to_list(bnad);
3630
3631         mutex_lock(&bnad->conf_mutex);
3632         /*
3633          * PCI initialization
3634          *      Output : using_dac = 1 for 64 bit DMA
3635          *                         = 0 for 32 bit DMA
3636          */
3637         using_dac = false;
3638         err = bnad_pci_init(bnad, pdev, &using_dac);
3639         if (err)
3640                 goto unlock_mutex;
3641
3642         /*
3643          * Initialize bnad structure
3644          * Setup relation between pci_dev & netdev
3645          */
3646         err = bnad_init(bnad, pdev, netdev);
3647         if (err)
3648                 goto pci_uninit;
3649
3650         /* Initialize netdev structure, set up ethtool ops */
3651         bnad_netdev_init(bnad, using_dac);
3652
3653         /* Set link to down state */
3654         netif_carrier_off(netdev);
3655
3656         /* Setup the debugfs node for this bfad */
3657         if (bna_debugfs_enable)
3658                 bnad_debugfs_init(bnad);
3659
3660         /* Get resource requirement form bna */
3661         spin_lock_irqsave(&bnad->bna_lock, flags);
3662         bna_res_req(&bnad->res_info[0]);
3663         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3664
3665         /* Allocate resources from bna */
3666         err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3667         if (err)
3668                 goto drv_uninit;
3669
3670         bna = &bnad->bna;
3671
3672         /* Setup pcidev_info for bna_init() */
3673         pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3674         pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3675         pcidev_info.device_id = bnad->pcidev->device;
3676         pcidev_info.pci_bar_kva = bnad->bar0;
3677
3678         spin_lock_irqsave(&bnad->bna_lock, flags);
3679         bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3680         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3681
3682         bnad->stats.bna_stats = &bna->stats;
3683
3684         bnad_enable_msix(bnad);
3685         err = bnad_mbox_irq_alloc(bnad);
3686         if (err)
3687                 goto res_free;
3688
3689         /* Set up timers */
3690         setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
3691                                 ((unsigned long)bnad));
3692         setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
3693                                 ((unsigned long)bnad));
3694         setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
3695                                 ((unsigned long)bnad));
3696         setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
3697                                 ((unsigned long)bnad));
3698
3699         /*
3700          * Start the chip
3701          * If the call back comes with error, we bail out.
3702          * This is a catastrophic error.
3703          */
3704         err = bnad_ioceth_enable(bnad);
3705         if (err) {
3706                 pr_err("BNA: Initialization failed err=%d\n",
3707                        err);
3708                 goto probe_success;
3709         }
3710
3711         spin_lock_irqsave(&bnad->bna_lock, flags);
3712         if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3713                 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3714                 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3715                         bna_attr(bna)->num_rxp - 1);
3716                 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3717                         bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3718                         err = -EIO;
3719         }
3720         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3721         if (err)
3722                 goto disable_ioceth;
3723
3724         spin_lock_irqsave(&bnad->bna_lock, flags);
3725         bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3726         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3727
3728         err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3729         if (err) {
3730                 err = -EIO;
3731                 goto disable_ioceth;
3732         }
3733
3734         spin_lock_irqsave(&bnad->bna_lock, flags);
3735         bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3736         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3737
3738         /* Get the burnt-in mac */
3739         spin_lock_irqsave(&bnad->bna_lock, flags);
3740         bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr);
3741         bnad_set_netdev_perm_addr(bnad);
3742         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3743
3744         mutex_unlock(&bnad->conf_mutex);
3745
3746         /* Finally, reguister with net_device layer */
3747         err = register_netdev(netdev);
3748         if (err) {
3749                 pr_err("BNA : Registering with netdev failed\n");
3750                 goto probe_uninit;
3751         }
3752         set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
3753
3754         return 0;
3755
3756 probe_success:
3757         mutex_unlock(&bnad->conf_mutex);
3758         return 0;
3759
3760 probe_uninit:
3761         mutex_lock(&bnad->conf_mutex);
3762         bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3763 disable_ioceth:
3764         bnad_ioceth_disable(bnad);
3765         del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3766         del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3767         del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3768         spin_lock_irqsave(&bnad->bna_lock, flags);
3769         bna_uninit(bna);
3770         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3771         bnad_mbox_irq_free(bnad);
3772         bnad_disable_msix(bnad);
3773 res_free:
3774         bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3775 drv_uninit:
3776         /* Remove the debugfs node for this bnad */
3777         kfree(bnad->regdata);
3778         bnad_debugfs_uninit(bnad);
3779         bnad_uninit(bnad);
3780 pci_uninit:
3781         bnad_pci_uninit(pdev);
3782 unlock_mutex:
3783         mutex_unlock(&bnad->conf_mutex);
3784         bnad_remove_from_list(bnad);
3785         bnad_lock_uninit(bnad);
3786         free_netdev(netdev);
3787         return err;
3788 }
3789
3790 static void
3791 bnad_pci_remove(struct pci_dev *pdev)
3792 {
3793         struct net_device *netdev = pci_get_drvdata(pdev);
3794         struct bnad *bnad;
3795         struct bna *bna;
3796         unsigned long flags;
3797
3798         if (!netdev)
3799                 return;
3800
3801         pr_info("%s bnad_pci_remove\n", netdev->name);
3802         bnad = netdev_priv(netdev);
3803         bna = &bnad->bna;
3804
3805         if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3806                 unregister_netdev(netdev);
3807
3808         mutex_lock(&bnad->conf_mutex);
3809         bnad_ioceth_disable(bnad);
3810         del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3811         del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3812         del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3813         spin_lock_irqsave(&bnad->bna_lock, flags);
3814         bna_uninit(bna);
3815         spin_unlock_irqrestore(&bnad->bna_lock, flags);
3816
3817         bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3818         bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3819         bnad_mbox_irq_free(bnad);
3820         bnad_disable_msix(bnad);
3821         bnad_pci_uninit(pdev);
3822         mutex_unlock(&bnad->conf_mutex);
3823         bnad_remove_from_list(bnad);
3824         bnad_lock_uninit(bnad);
3825         /* Remove the debugfs node for this bnad */
3826         kfree(bnad->regdata);
3827         bnad_debugfs_uninit(bnad);
3828         bnad_uninit(bnad);
3829         free_netdev(netdev);
3830 }
3831
3832 static const struct pci_device_id bnad_pci_id_table[] = {
3833         {
3834                 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3835                         PCI_DEVICE_ID_BROCADE_CT),
3836                 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3837                 .class_mask =  0xffff00
3838         },
3839         {
3840                 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3841                         BFA_PCI_DEVICE_ID_CT2),
3842                 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3843                 .class_mask =  0xffff00
3844         },
3845         {0,  },
3846 };
3847
3848 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3849
3850 static struct pci_driver bnad_pci_driver = {
3851         .name = BNAD_NAME,
3852         .id_table = bnad_pci_id_table,
3853         .probe = bnad_pci_probe,
3854         .remove = bnad_pci_remove,
3855 };
3856
3857 static int __init
3858 bnad_module_init(void)
3859 {
3860         int err;
3861
3862         pr_info("QLogic BR-series 10G Ethernet driver - version: %s\n",
3863                         BNAD_VERSION);
3864
3865         bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
3866
3867         err = pci_register_driver(&bnad_pci_driver);
3868         if (err < 0) {
3869                 pr_err("bna : PCI registration failed in module init "
3870                        "(%d)\n", err);
3871                 return err;
3872         }
3873
3874         return 0;
3875 }
3876
3877 static void __exit
3878 bnad_module_exit(void)
3879 {
3880         pci_unregister_driver(&bnad_pci_driver);
3881         release_firmware(bfi_fw);
3882 }
3883
3884 module_init(bnad_module_init);
3885 module_exit(bnad_module_exit);
3886
3887 MODULE_AUTHOR("Brocade");
3888 MODULE_LICENSE("GPL");
3889 MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver");
3890 MODULE_VERSION(BNAD_VERSION);
3891 MODULE_FIRMWARE(CNA_FW_FILE_CT);
3892 MODULE_FIRMWARE(CNA_FW_FILE_CT2);