drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45
  46 #include <asm/io.h>
  47
  48 #include "mlx4.h"
  49 #include "fw.h"
  50
  51 #define CMD_POLL_TOKEN 0xffff
  52 #define INBOX_MASK      0xffffffffffffff00ULL
  53
  54 #define CMD_CHAN_VER 1
  55 #define CMD_CHAN_IF_REV 1
  56
  57 enum {
  58         /* command completed successfully: */
  59         CMD_STAT_OK             = 0x00,
  60         /* Internal error (such as a bus error) occurred while processing command: */
  61         CMD_STAT_INTERNAL_ERR   = 0x01,
  62         /* Operation/command not supported or opcode modifier not supported: */
  63         CMD_STAT_BAD_OP         = 0x02,
  64         /* Parameter not supported or parameter out of range: */
  65         CMD_STAT_BAD_PARAM      = 0x03,
  66         /* System not enabled or bad system state: */
  67         CMD_STAT_BAD_SYS_STATE  = 0x04,
  68         /* Attempt to access reserved or unallocaterd resource: */
  69         CMD_STAT_BAD_RESOURCE   = 0x05,
  70         /* Requested resource is currently executing a command, or is otherwise busy: */
  71         CMD_STAT_RESOURCE_BUSY  = 0x06,
  72         /* Required capability exceeds device limits: */
  73         CMD_STAT_EXCEED_LIM     = 0x08,
  74         /* Resource is not in the appropriate state or ownership: */
  75         CMD_STAT_BAD_RES_STATE  = 0x09,
  76         /* Index out of range: */
  77         CMD_STAT_BAD_INDEX      = 0x0a,
  78         /* FW image corrupted: */
  79         CMD_STAT_BAD_NVMEM      = 0x0b,
  80         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  81         CMD_STAT_ICM_ERROR      = 0x0c,
  82         /* Attempt to modify a QP/EE which is not in the presumed state: */
  83         CMD_STAT_BAD_QP_STATE   = 0x10,
  84         /* Bad segment parameters (Address/Size): */
  85         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  86         /* Memory Region has Memory Windows bound to: */
  87         CMD_STAT_REG_BOUND      = 0x21,
  88         /* HCA local attached memory not present: */
  89         CMD_STAT_LAM_NOT_PRE    = 0x22,
  90         /* Bad management packet (silently discarded): */
  91         CMD_STAT_BAD_PKT        = 0x30,
  92         /* More outstanding CQEs in CQ than new CQ size: */
  93         CMD_STAT_BAD_SIZE       = 0x40,
  94         /* Multi Function device support required: */
  95         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  96 };
  97
  98 enum {
  99         HCR_IN_PARAM_OFFSET     = 0x00,
 100         HCR_IN_MODIFIER_OFFSET  = 0x08,
 101         HCR_OUT_PARAM_OFFSET    = 0x0c,
 102         HCR_TOKEN_OFFSET        = 0x14,
 103         HCR_STATUS_OFFSET       = 0x18,
 104
 105         HCR_OPMOD_SHIFT         = 12,
 106         HCR_T_BIT               = 21,
 107         HCR_E_BIT               = 22,
 108         HCR_GO_BIT              = 23
 109 };
 110
 111 enum {
 112         GO_BIT_TIMEOUT_MSECS    = 10000
 113 };
 114
 115 enum mlx4_vlan_transition {
 116         MLX4_VLAN_TRANSITION_VST_VST = 0,
 117         MLX4_VLAN_TRANSITION_VST_VGT = 1,
 118         MLX4_VLAN_TRANSITION_VGT_VST = 2,
 119         MLX4_VLAN_TRANSITION_VGT_VGT = 3,
 120 };
 121
 122
 123 struct mlx4_cmd_context {
 124         struct completion       done;
 125         int                     result;
 126         int                     next;
 127         u64                     out_param;
 128         u16                     token;
 129         u8                      fw_status;
 130 };
 131
 132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 133                                     struct mlx4_vhcr_cmd *in_vhcr);
 134
 135 static int mlx4_status_to_errno(u8 status)
 136 {
 137         static const int trans_table[] = {
 138                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 139                 [CMD_STAT_BAD_OP]         = -EPERM,
 140                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 141                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 142                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 143                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 144                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 145                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 146                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 147                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 148                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 149                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 150                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 151                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 152                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 153                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 154                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 155                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 156         };
 157
 158         if (status >= ARRAY_SIZE(trans_table) ||
 159             (status != CMD_STAT_OK && trans_table[status] == 0))
 160                 return -EIO;
 161
 162         return trans_table[status];
 163 }
 164
 165 static u8 mlx4_errno_to_status(int errno)
 166 {
 167         switch (errno) {
 168         case -EPERM:
 169                 return CMD_STAT_BAD_OP;
 170         case -EINVAL:
 171                 return CMD_STAT_BAD_PARAM;
 172         case -ENXIO:
 173                 return CMD_STAT_BAD_SYS_STATE;
 174         case -EBUSY:
 175                 return CMD_STAT_RESOURCE_BUSY;
 176         case -ENOMEM:
 177                 return CMD_STAT_EXCEED_LIM;
 178         case -ENFILE:
 179                 return CMD_STAT_ICM_ERROR;
 180         default:
 181                 return CMD_STAT_INTERNAL_ERR;
 182         }
 183 }
 184
 185 static int comm_pending(struct mlx4_dev *dev)
 186 {
 187         struct mlx4_priv *priv = mlx4_priv(dev);
 188         u32 status = readl(&priv->mfunc.comm->slave_read);
 189
 190         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 191 }
 192
 193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 194 {
 195         struct mlx4_priv *priv = mlx4_priv(dev);
 196         u32 val;
 197
 198         priv->cmd.comm_toggle ^= 1;
 199         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 200         __raw_writel((__force u32) cpu_to_be32(val),
 201                      &priv->mfunc.comm->slave_write);
 202         mmiowb();
 203 }
 204
 205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 206                        unsigned long timeout)
 207 {
 208         struct mlx4_priv *priv = mlx4_priv(dev);
 209         unsigned long end;
 210         int err = 0;
 211         int ret_from_pending = 0;
 212
 213         /* First, verify that the master reports correct status */
 214         if (comm_pending(dev)) {
 215                 mlx4_warn(dev, "Communication channel is not idle."
 216                           "my toggle is %d (cmd:0x%x)\n",
 217                           priv->cmd.comm_toggle, cmd);
 218                 return -EAGAIN;
 219         }
 220
 221         /* Write command */
 222         down(&priv->cmd.poll_sem);
 223         mlx4_comm_cmd_post(dev, cmd, param);
 224
 225         end = msecs_to_jiffies(timeout) + jiffies;
 226         while (comm_pending(dev) && time_before(jiffies, end))
 227                 cond_resched();
 228         ret_from_pending = comm_pending(dev);
 229         if (ret_from_pending) {
 230                 /* check if the slave is trying to boot in the middle of
 231                  * FLR process. The only non-zero result in the RESET command
 232                  * is MLX4_DELAY_RESET_SLAVE*/
 233                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 234                         err = MLX4_DELAY_RESET_SLAVE;
 235                 } else {
 236                         mlx4_warn(dev, "Communication channel timed out\n");
 237                         err = -ETIMEDOUT;
 238                 }
 239         }
 240
 241         up(&priv->cmd.poll_sem);
 242         return err;
 243 }
 244
 245 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
 246                               u16 param, unsigned long timeout)
 247 {
 248         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 249         struct mlx4_cmd_context *context;
 250         unsigned long end;
 251         int err = 0;
 252
 253         down(&cmd->event_sem);
 254
 255         spin_lock(&cmd->context_lock);
 256         BUG_ON(cmd->free_head < 0);
 257         context = &cmd->context[cmd->free_head];
 258         context->token += cmd->token_mask + 1;
 259         cmd->free_head = context->next;
 260         spin_unlock(&cmd->context_lock);
 261
 262         init_completion(&context->done);
 263
 264         mlx4_comm_cmd_post(dev, op, param);
 265
 266         if (!wait_for_completion_timeout(&context->done,
 267                                          msecs_to_jiffies(timeout))) {
 268                 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
 269                           op);
 270                 err = -EBUSY;
 271                 goto out;
 272         }
 273
 274         err = context->result;
 275         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 276                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 277                          op, context->fw_status);
 278                 goto out;
 279         }
 280
 281 out:
 282         /* wait for comm channel ready
 283          * this is necessary for prevention the race
 284          * when switching between event to polling mode
 285          */
 286         end = msecs_to_jiffies(timeout) + jiffies;
 287         while (comm_pending(dev) && time_before(jiffies, end))
 288                 cond_resched();
 289
 290         spin_lock(&cmd->context_lock);
 291         context->next = cmd->free_head;
 292         cmd->free_head = context - cmd->context;
 293         spin_unlock(&cmd->context_lock);
 294
 295         up(&cmd->event_sem);
 296         return err;
 297 }
 298
 299 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 300                   unsigned long timeout)
 301 {
 302         if (mlx4_priv(dev)->cmd.use_events)
 303                 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
 304         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 305 }
 306
 307 static int cmd_pending(struct mlx4_dev *dev)
 308 {
 309         u32 status;
 310
 311         if (pci_channel_offline(dev->pdev))
 312                 return -EIO;
 313
 314         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 315
 316         return (status & swab32(1 << HCR_GO_BIT)) ||
 317                 (mlx4_priv(dev)->cmd.toggle ==
 318                  !!(status & swab32(1 << HCR_T_BIT)));
 319 }
 320
 321 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 322                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 323                          int event)
 324 {
 325         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 326         u32 __iomem *hcr = cmd->hcr;
 327         int ret = -EAGAIN;
 328         unsigned long end;
 329
 330         mutex_lock(&cmd->hcr_mutex);
 331
 332         if (pci_channel_offline(dev->pdev)) {
 333                 /*
 334                  * Device is going through error recovery
 335                  * and cannot accept commands.
 336                  */
 337                 ret = -EIO;
 338                 goto out;
 339         }
 340
 341         end = jiffies;
 342         if (event)
 343                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 344
 345         while (cmd_pending(dev)) {
 346                 if (pci_channel_offline(dev->pdev)) {
 347                         /*
 348                          * Device is going through error recovery
 349                          * and cannot accept commands.
 350                          */
 351                         ret = -EIO;
 352                         goto out;
 353                 }
 354
 355                 if (time_after_eq(jiffies, end)) {
 356                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 357                         goto out;
 358                 }
 359                 cond_resched();
 360         }
 361
 362         /*
 363          * We use writel (instead of something like memcpy_toio)
 364          * because writes of less than 32 bits to the HCR don't work
 365          * (and some architectures such as ia64 implement memcpy_toio
 366          * in terms of writeb).
 367          */
 368         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 369         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 370         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 371         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 372         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 373         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 374
 375         /* __raw_writel may not order writes. */
 376         wmb();
 377
 378         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 379                                                (cmd->toggle << HCR_T_BIT)       |
 380                                                (event ? (1 << HCR_E_BIT) : 0)   |
 381                                                (op_modifier << HCR_OPMOD_SHIFT) |
 382                                                op), hcr + 6);
 383
 384         /*
 385          * Make sure that our HCR writes don't get mixed in with
 386          * writes from another CPU starting a FW command.
 387          */
 388         mmiowb();
 389
 390         cmd->toggle = cmd->toggle ^ 1;
 391
 392         ret = 0;
 393
 394 out:
 395         mutex_unlock(&cmd->hcr_mutex);
 396         return ret;
 397 }
 398
 399 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 400                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 401                           u16 op, unsigned long timeout)
 402 {
 403         struct mlx4_priv *priv = mlx4_priv(dev);
 404         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 405         int ret;
 406
 407         mutex_lock(&priv->cmd.slave_cmd_mutex);
 408
 409         vhcr->in_param = cpu_to_be64(in_param);
 410         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 411         vhcr->in_modifier = cpu_to_be32(in_modifier);
 412         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 413         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 414         vhcr->status = 0;
 415         vhcr->flags = !!(priv->cmd.use_events) << 6;
 416
 417         if (mlx4_is_master(dev)) {
 418                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 419                 if (!ret) {
 420                         if (out_is_imm) {
 421                                 if (out_param)
 422                                         *out_param =
 423                                                 be64_to_cpu(vhcr->out_param);
 424                                 else {
 425                                         mlx4_err(dev, "response expected while"
 426                                                  "output mailbox is NULL for "
 427                                                  "command 0x%x\n", op);
 428                                         vhcr->status = CMD_STAT_BAD_PARAM;
 429                                 }
 430                         }
 431                         ret = mlx4_status_to_errno(vhcr->status);
 432                 }
 433         } else {
 434                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
 435                                     MLX4_COMM_TIME + timeout);
 436                 if (!ret) {
 437                         if (out_is_imm) {
 438                                 if (out_param)
 439                                         *out_param =
 440                                                 be64_to_cpu(vhcr->out_param);
 441                                 else {
 442                                         mlx4_err(dev, "response expected while"
 443                                                  "output mailbox is NULL for "
 444                                                  "command 0x%x\n", op);
 445                                         vhcr->status = CMD_STAT_BAD_PARAM;
 446                                 }
 447                         }
 448                         ret = mlx4_status_to_errno(vhcr->status);
 449                 } else
 450                         mlx4_err(dev, "failed execution of VHCR_POST command"
 451                                  "opcode 0x%x\n", op);
 452         }
 453
 454         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 455         return ret;
 456 }
 457
 458 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 459                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 460                          u16 op, unsigned long timeout)
 461 {
 462         struct mlx4_priv *priv = mlx4_priv(dev);
 463         void __iomem *hcr = priv->cmd.hcr;
 464         int err = 0;
 465         unsigned long end;
 466         u32 stat;
 467
 468         down(&priv->cmd.poll_sem);
 469
 470         if (pci_channel_offline(dev->pdev)) {
 471                 /*
 472                  * Device is going through error recovery
 473                  * and cannot accept commands.
 474                  */
 475                 err = -EIO;
 476                 goto out;
 477         }
 478
 479         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 480                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 481         if (err)
 482                 goto out;
 483
 484         end = msecs_to_jiffies(timeout) + jiffies;
 485         while (cmd_pending(dev) && time_before(jiffies, end)) {
 486                 if (pci_channel_offline(dev->pdev)) {
 487                         /*
 488                          * Device is going through error recovery
 489                          * and cannot accept commands.
 490                          */
 491                         err = -EIO;
 492                         goto out;
 493                 }
 494
 495                 cond_resched();
 496         }
 497
 498         if (cmd_pending(dev)) {
 499                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 500                           op);
 501                 err = -ETIMEDOUT;
 502                 goto out;
 503         }
 504
 505         if (out_is_imm)
 506                 *out_param =
 507                         (u64) be32_to_cpu((__force __be32)
 508                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 509                         (u64) be32_to_cpu((__force __be32)
 510                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 511         stat = be32_to_cpu((__force __be32)
 512                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 513         err = mlx4_status_to_errno(stat);
 514         if (err)
 515                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 516                          op, stat);
 517
 518 out:
 519         up(&priv->cmd.poll_sem);
 520         return err;
 521 }
 522
 523 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 524 {
 525         struct mlx4_priv *priv = mlx4_priv(dev);
 526         struct mlx4_cmd_context *context =
 527                 &priv->cmd.context[token & priv->cmd.token_mask];
 528
 529         /* previously timed out command completing at long last */
 530         if (token != context->token)
 531                 return;
 532
 533         context->fw_status = status;
 534         context->result    = mlx4_status_to_errno(status);
 535         context->out_param = out_param;
 536
 537         complete(&context->done);
 538 }
 539
 540 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 541                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 542                          u16 op, unsigned long timeout)
 543 {
 544         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 545         struct mlx4_cmd_context *context;
 546         int err = 0;
 547
 548         down(&cmd->event_sem);
 549
 550         spin_lock(&cmd->context_lock);
 551         BUG_ON(cmd->free_head < 0);
 552         context = &cmd->context[cmd->free_head];
 553         context->token += cmd->token_mask + 1;
 554         cmd->free_head = context->next;
 555         spin_unlock(&cmd->context_lock);
 556
 557         init_completion(&context->done);
 558
 559         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 560                       in_modifier, op_modifier, op, context->token, 1);
 561
 562         if (!wait_for_completion_timeout(&context->done,
 563                                          msecs_to_jiffies(timeout))) {
 564                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 565                           op);
 566                 err = -EBUSY;
 567                 goto out;
 568         }
 569
 570         err = context->result;
 571         if (err) {
 572                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 573                          op, context->fw_status);
 574                 goto out;
 575         }
 576
 577         if (out_is_imm)
 578                 *out_param = context->out_param;
 579
 580 out:
 581         spin_lock(&cmd->context_lock);
 582         context->next = cmd->free_head;
 583         cmd->free_head = context - cmd->context;
 584         spin_unlock(&cmd->context_lock);
 585
 586         up(&cmd->event_sem);
 587         return err;
 588 }
 589
 590 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 591                int out_is_imm, u32 in_modifier, u8 op_modifier,
 592                u16 op, unsigned long timeout, int native)
 593 {
 594         if (pci_channel_offline(dev->pdev))
 595                 return -EIO;
 596
 597         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 598                 if (mlx4_priv(dev)->cmd.use_events)
 599                         return mlx4_cmd_wait(dev, in_param, out_param,
 600                                              out_is_imm, in_modifier,
 601                                              op_modifier, op, timeout);
 602                 else
 603                         return mlx4_cmd_poll(dev, in_param, out_param,
 604                                              out_is_imm, in_modifier,
 605                                              op_modifier, op, timeout);
 606         }
 607         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 608                               in_modifier, op_modifier, op, timeout);
 609 }
 610 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 611
 612
 613 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 614 {
 615         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 616                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 617 }
 618
 619 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 620                            int slave, u64 slave_addr,
 621                            int size, int is_read)
 622 {
 623         u64 in_param;
 624         u64 out_param;
 625
 626         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 627             (slave & ~0x7f) | (size & 0xff)) {
 628                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
 629                               "master_addr:0x%llx slave_id:%d size:%d\n",
 630                               slave_addr, master_addr, slave, size);
 631                 return -EINVAL;
 632         }
 633
 634         if (is_read) {
 635                 in_param = (u64) slave | slave_addr;
 636                 out_param = (u64) dev->caps.function | master_addr;
 637         } else {
 638                 in_param = (u64) dev->caps.function | master_addr;
 639                 out_param = (u64) slave | slave_addr;
 640         }
 641
 642         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 643                             MLX4_CMD_ACCESS_MEM,
 644                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 645 }
 646
 647 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 648                                struct mlx4_cmd_mailbox *inbox,
 649                                struct mlx4_cmd_mailbox *outbox)
 650 {
 651         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 652         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 653         int err;
 654         int i;
 655
 656         if (index & 0x1f)
 657                 return -EINVAL;
 658
 659         in_mad->attr_mod = cpu_to_be32(index / 32);
 660
 661         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 662                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 663                            MLX4_CMD_NATIVE);
 664         if (err)
 665                 return err;
 666
 667         for (i = 0; i < 32; ++i)
 668                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 669
 670         return err;
 671 }
 672
 673 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 674                                struct mlx4_cmd_mailbox *inbox,
 675                                struct mlx4_cmd_mailbox *outbox)
 676 {
 677         int i;
 678         int err;
 679
 680         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 681                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 682                 if (err)
 683                         return err;
 684         }
 685
 686         return 0;
 687 }
 688 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 689 #define PORT_STATE_OFFSET 32
 690
 691 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 692 {
 693         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 694                 return IB_PORT_ACTIVE;
 695         else
 696                 return IB_PORT_DOWN;
 697 }
 698
 699 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 700                                 struct mlx4_vhcr *vhcr,
 701                                 struct mlx4_cmd_mailbox *inbox,
 702                                 struct mlx4_cmd_mailbox *outbox,
 703                                 struct mlx4_cmd_info *cmd)
 704 {
 705         struct ib_smp *smp = inbox->buf;
 706         u32 index;
 707         u8 port;
 708         u8 opcode_modifier;
 709         u16 *table;
 710         int err;
 711         int vidx, pidx;
 712         int network_view;
 713         struct mlx4_priv *priv = mlx4_priv(dev);
 714         struct ib_smp *outsmp = outbox->buf;
 715         __be16 *outtab = (__be16 *)(outsmp->data);
 716         __be32 slave_cap_mask;
 717         __be64 slave_node_guid;
 718
 719         port = vhcr->in_modifier;
 720
 721         /* network-view bit is for driver use only, and should not be passed to FW */
 722         opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
 723         network_view = !!(vhcr->op_modifier & 0x8);
 724
 725         if (smp->base_version == 1 &&
 726             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 727             smp->class_version == 1) {
 728                 /* host view is paravirtualized */
 729                 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
 730                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 731                                 index = be32_to_cpu(smp->attr_mod);
 732                                 if (port < 1 || port > dev->caps.num_ports)
 733                                         return -EINVAL;
 734                                 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
 735                                 if (!table)
 736                                         return -ENOMEM;
 737                                 /* need to get the full pkey table because the paravirtualized
 738                                  * pkeys may be scattered among several pkey blocks.
 739                                  */
 740                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 741                                 if (!err) {
 742                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 743                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 744                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 745                                         }
 746                                 }
 747                                 kfree(table);
 748                                 return err;
 749                         }
 750                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 751                                 /*get the slave specific caps:*/
 752                                 /*do the command */
 753                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 754                                             vhcr->in_modifier, opcode_modifier,
 755                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 756                                 /* modify the response for slaves */
 757                                 if (!err && slave != mlx4_master_func_num(dev)) {
 758                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 759
 760                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 761                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 762                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 763                                 }
 764                                 return err;
 765                         }
 766                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 767                                 /* compute slave's gid block */
 768                                 smp->attr_mod = cpu_to_be32(slave / 8);
 769                                 /* execute cmd */
 770                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 771                                              vhcr->in_modifier, opcode_modifier,
 772                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 773                                 if (!err) {
 774                                         /* if needed, move slave gid to index 0 */
 775                                         if (slave % 8)
 776                                                 memcpy(outsmp->data,
 777                                                        outsmp->data + (slave % 8) * 8, 8);
 778                                         /* delete all other gids */
 779                                         memset(outsmp->data + 8, 0, 56);
 780                                 }
 781                                 return err;
 782                         }
 783                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 784                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 785                                              vhcr->in_modifier, opcode_modifier,
 786                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 787                                 if (!err) {
 788                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 789                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 790                                 }
 791                                 return err;
 792                         }
 793                 }
 794         }
 795
 796         /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
 797          * These are the MADs used by ib verbs (such as ib_query_gids).
 798          */
 799         if (slave != mlx4_master_func_num(dev) &&
 800             !mlx4_vf_smi_enabled(dev, slave, port)) {
 801                 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 802                       smp->method == IB_MGMT_METHOD_GET) || network_view) {
 803                         mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
 804                                  slave, smp->method, smp->mgmt_class,
 805                                  network_view ? "Network" : "Host",
 806                                  be16_to_cpu(smp->attr_id));
 807                         return -EPERM;
 808                 }
 809         }
 810
 811         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 812                                     vhcr->in_modifier, opcode_modifier,
 813                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 814 }
 815
 816 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
 817                      struct mlx4_vhcr *vhcr,
 818                      struct mlx4_cmd_mailbox *inbox,
 819                      struct mlx4_cmd_mailbox *outbox,
 820                      struct mlx4_cmd_info *cmd)
 821 {
 822         return -EPERM;
 823 }
 824
 825 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 826                      struct mlx4_vhcr *vhcr,
 827                      struct mlx4_cmd_mailbox *inbox,
 828                      struct mlx4_cmd_mailbox *outbox,
 829                      struct mlx4_cmd_info *cmd)
 830 {
 831         u64 in_param;
 832         u64 out_param;
 833         int err;
 834
 835         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
 836         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
 837         if (cmd->encode_slave_id) {
 838                 in_param &= 0xffffffffffffff00ll;
 839                 in_param |= slave;
 840         }
 841
 842         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
 843                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
 844                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 845
 846         if (cmd->out_is_imm)
 847                 vhcr->out_param = out_param;
 848
 849         return err;
 850 }
 851
 852 static struct mlx4_cmd_info cmd_info[] = {
 853         {
 854                 .opcode = MLX4_CMD_QUERY_FW,
 855                 .has_inbox = false,
 856                 .has_outbox = true,
 857                 .out_is_imm = false,
 858                 .encode_slave_id = false,
 859                 .verify = NULL,
 860                 .wrapper = mlx4_QUERY_FW_wrapper
 861         },
 862         {
 863                 .opcode = MLX4_CMD_QUERY_HCA,
 864                 .has_inbox = false,
 865                 .has_outbox = true,
 866                 .out_is_imm = false,
 867                 .encode_slave_id = false,
 868                 .verify = NULL,
 869                 .wrapper = NULL
 870         },
 871         {
 872                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
 873                 .has_inbox = false,
 874                 .has_outbox = true,
 875                 .out_is_imm = false,
 876                 .encode_slave_id = false,
 877                 .verify = NULL,
 878                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
 879         },
 880         {
 881                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
 882                 .has_inbox = false,
 883                 .has_outbox = true,
 884                 .out_is_imm = false,
 885                 .encode_slave_id = false,
 886                 .verify = NULL,
 887                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
 888         },
 889         {
 890                 .opcode = MLX4_CMD_QUERY_ADAPTER,
 891                 .has_inbox = false,
 892                 .has_outbox = true,
 893                 .out_is_imm = false,
 894                 .encode_slave_id = false,
 895                 .verify = NULL,
 896                 .wrapper = NULL
 897         },
 898         {
 899                 .opcode = MLX4_CMD_INIT_PORT,
 900                 .has_inbox = false,
 901                 .has_outbox = false,
 902                 .out_is_imm = false,
 903                 .encode_slave_id = false,
 904                 .verify = NULL,
 905                 .wrapper = mlx4_INIT_PORT_wrapper
 906         },
 907         {
 908                 .opcode = MLX4_CMD_CLOSE_PORT,
 909                 .has_inbox = false,
 910                 .has_outbox = false,
 911                 .out_is_imm  = false,
 912                 .encode_slave_id = false,
 913                 .verify = NULL,
 914                 .wrapper = mlx4_CLOSE_PORT_wrapper
 915         },
 916         {
 917                 .opcode = MLX4_CMD_QUERY_PORT,
 918                 .has_inbox = false,
 919                 .has_outbox = true,
 920                 .out_is_imm = false,
 921                 .encode_slave_id = false,
 922                 .verify = NULL,
 923                 .wrapper = mlx4_QUERY_PORT_wrapper
 924         },
 925         {
 926                 .opcode = MLX4_CMD_SET_PORT,
 927                 .has_inbox = true,
 928                 .has_outbox = false,
 929                 .out_is_imm = false,
 930                 .encode_slave_id = false,
 931                 .verify = NULL,
 932                 .wrapper = mlx4_SET_PORT_wrapper
 933         },
 934         {
 935                 .opcode = MLX4_CMD_MAP_EQ,
 936                 .has_inbox = false,
 937                 .has_outbox = false,
 938                 .out_is_imm = false,
 939                 .encode_slave_id = false,
 940                 .verify = NULL,
 941                 .wrapper = mlx4_MAP_EQ_wrapper
 942         },
 943         {
 944                 .opcode = MLX4_CMD_SW2HW_EQ,
 945                 .has_inbox = true,
 946                 .has_outbox = false,
 947                 .out_is_imm = false,
 948                 .encode_slave_id = true,
 949                 .verify = NULL,
 950                 .wrapper = mlx4_SW2HW_EQ_wrapper
 951         },
 952         {
 953                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
 954                 .has_inbox = false,
 955                 .has_outbox = false,
 956                 .out_is_imm = false,
 957                 .encode_slave_id = false,
 958                 .verify = NULL,
 959                 .wrapper = NULL
 960         },
 961         {
 962                 .opcode = MLX4_CMD_NOP,
 963                 .has_inbox = false,
 964                 .has_outbox = false,
 965                 .out_is_imm = false,
 966                 .encode_slave_id = false,
 967                 .verify = NULL,
 968                 .wrapper = NULL
 969         },
 970         {
 971                 .opcode = MLX4_CMD_CONFIG_DEV,
 972                 .has_inbox = false,
 973                 .has_outbox = false,
 974                 .out_is_imm = false,
 975                 .encode_slave_id = false,
 976                 .verify = NULL,
 977                 .wrapper = mlx4_CMD_EPERM_wrapper
 978         },
 979         {
 980                 .opcode = MLX4_CMD_ALLOC_RES,
 981                 .has_inbox = false,
 982                 .has_outbox = false,
 983                 .out_is_imm = true,
 984                 .encode_slave_id = false,
 985                 .verify = NULL,
 986                 .wrapper = mlx4_ALLOC_RES_wrapper
 987         },
 988         {
 989                 .opcode = MLX4_CMD_FREE_RES,
 990                 .has_inbox = false,
 991                 .has_outbox = false,
 992                 .out_is_imm = false,
 993                 .encode_slave_id = false,
 994                 .verify = NULL,
 995                 .wrapper = mlx4_FREE_RES_wrapper
 996         },
 997         {
 998                 .opcode = MLX4_CMD_SW2HW_MPT,
 999                 .has_inbox = true,
1000                 .has_outbox = false,
1001                 .out_is_imm = false,
1002                 .encode_slave_id = true,
1003                 .verify = NULL,
1004                 .wrapper = mlx4_SW2HW_MPT_wrapper
1005         },
1006         {
1007                 .opcode = MLX4_CMD_QUERY_MPT,
1008                 .has_inbox = false,
1009                 .has_outbox = true,
1010                 .out_is_imm = false,
1011                 .encode_slave_id = false,
1012                 .verify = NULL,
1013                 .wrapper = mlx4_QUERY_MPT_wrapper
1014         },
1015         {
1016                 .opcode = MLX4_CMD_HW2SW_MPT,
1017                 .has_inbox = false,
1018                 .has_outbox = false,
1019                 .out_is_imm = false,
1020                 .encode_slave_id = false,
1021                 .verify = NULL,
1022                 .wrapper = mlx4_HW2SW_MPT_wrapper
1023         },
1024         {
1025                 .opcode = MLX4_CMD_READ_MTT,
1026                 .has_inbox = false,
1027                 .has_outbox = true,
1028                 .out_is_imm = false,
1029                 .encode_slave_id = false,
1030                 .verify = NULL,
1031                 .wrapper = NULL
1032         },
1033         {
1034                 .opcode = MLX4_CMD_WRITE_MTT,
1035                 .has_inbox = true,
1036                 .has_outbox = false,
1037                 .out_is_imm = false,
1038                 .encode_slave_id = false,
1039                 .verify = NULL,
1040                 .wrapper = mlx4_WRITE_MTT_wrapper
1041         },
1042         {
1043                 .opcode = MLX4_CMD_SYNC_TPT,
1044                 .has_inbox = true,
1045                 .has_outbox = false,
1046                 .out_is_imm = false,
1047                 .encode_slave_id = false,
1048                 .verify = NULL,
1049                 .wrapper = NULL
1050         },
1051         {
1052                 .opcode = MLX4_CMD_HW2SW_EQ,
1053                 .has_inbox = false,
1054                 .has_outbox = true,
1055                 .out_is_imm = false,
1056                 .encode_slave_id = true,
1057                 .verify = NULL,
1058                 .wrapper = mlx4_HW2SW_EQ_wrapper
1059         },
1060         {
1061                 .opcode = MLX4_CMD_QUERY_EQ,
1062                 .has_inbox = false,
1063                 .has_outbox = true,
1064                 .out_is_imm = false,
1065                 .encode_slave_id = true,
1066                 .verify = NULL,
1067                 .wrapper = mlx4_QUERY_EQ_wrapper
1068         },
1069         {
1070                 .opcode = MLX4_CMD_SW2HW_CQ,
1071                 .has_inbox = true,
1072                 .has_outbox = false,
1073                 .out_is_imm = false,
1074                 .encode_slave_id = true,
1075                 .verify = NULL,
1076                 .wrapper = mlx4_SW2HW_CQ_wrapper
1077         },
1078         {
1079                 .opcode = MLX4_CMD_HW2SW_CQ,
1080                 .has_inbox = false,
1081                 .has_outbox = false,
1082                 .out_is_imm = false,
1083                 .encode_slave_id = false,
1084                 .verify = NULL,
1085                 .wrapper = mlx4_HW2SW_CQ_wrapper
1086         },
1087         {
1088                 .opcode = MLX4_CMD_QUERY_CQ,
1089                 .has_inbox = false,
1090                 .has_outbox = true,
1091                 .out_is_imm = false,
1092                 .encode_slave_id = false,
1093                 .verify = NULL,
1094                 .wrapper = mlx4_QUERY_CQ_wrapper
1095         },
1096         {
1097                 .opcode = MLX4_CMD_MODIFY_CQ,
1098                 .has_inbox = true,
1099                 .has_outbox = false,
1100                 .out_is_imm = true,
1101                 .encode_slave_id = false,
1102                 .verify = NULL,
1103                 .wrapper = mlx4_MODIFY_CQ_wrapper
1104         },
1105         {
1106                 .opcode = MLX4_CMD_SW2HW_SRQ,
1107                 .has_inbox = true,
1108                 .has_outbox = false,
1109                 .out_is_imm = false,
1110                 .encode_slave_id = true,
1111                 .verify = NULL,
1112                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1113         },
1114         {
1115                 .opcode = MLX4_CMD_HW2SW_SRQ,
1116                 .has_inbox = false,
1117                 .has_outbox = false,
1118                 .out_is_imm = false,
1119                 .encode_slave_id = false,
1120                 .verify = NULL,
1121                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1122         },
1123         {
1124                 .opcode = MLX4_CMD_QUERY_SRQ,
1125                 .has_inbox = false,
1126                 .has_outbox = true,
1127                 .out_is_imm = false,
1128                 .encode_slave_id = false,
1129                 .verify = NULL,
1130                 .wrapper = mlx4_QUERY_SRQ_wrapper
1131         },
1132         {
1133                 .opcode = MLX4_CMD_ARM_SRQ,
1134                 .has_inbox = false,
1135                 .has_outbox = false,
1136                 .out_is_imm = false,
1137                 .encode_slave_id = false,
1138                 .verify = NULL,
1139                 .wrapper = mlx4_ARM_SRQ_wrapper
1140         },
1141         {
1142                 .opcode = MLX4_CMD_RST2INIT_QP,
1143                 .has_inbox = true,
1144                 .has_outbox = false,
1145                 .out_is_imm = false,
1146                 .encode_slave_id = true,
1147                 .verify = NULL,
1148                 .wrapper = mlx4_RST2INIT_QP_wrapper
1149         },
1150         {
1151                 .opcode = MLX4_CMD_INIT2INIT_QP,
1152                 .has_inbox = true,
1153                 .has_outbox = false,
1154                 .out_is_imm = false,
1155                 .encode_slave_id = false,
1156                 .verify = NULL,
1157                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1158         },
1159         {
1160                 .opcode = MLX4_CMD_INIT2RTR_QP,
1161                 .has_inbox = true,
1162                 .has_outbox = false,
1163                 .out_is_imm = false,
1164                 .encode_slave_id = false,
1165                 .verify = NULL,
1166                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1167         },
1168         {
1169                 .opcode = MLX4_CMD_RTR2RTS_QP,
1170                 .has_inbox = true,
1171                 .has_outbox = false,
1172                 .out_is_imm = false,
1173                 .encode_slave_id = false,
1174                 .verify = NULL,
1175                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1176         },
1177         {
1178                 .opcode = MLX4_CMD_RTS2RTS_QP,
1179                 .has_inbox = true,
1180                 .has_outbox = false,
1181                 .out_is_imm = false,
1182                 .encode_slave_id = false,
1183                 .verify = NULL,
1184                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1185         },
1186         {
1187                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1188                 .has_inbox = true,
1189                 .has_outbox = false,
1190                 .out_is_imm = false,
1191                 .encode_slave_id = false,
1192                 .verify = NULL,
1193                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1194         },
1195         {
1196                 .opcode = MLX4_CMD_2ERR_QP,
1197                 .has_inbox = false,
1198                 .has_outbox = false,
1199                 .out_is_imm = false,
1200                 .encode_slave_id = false,
1201                 .verify = NULL,
1202                 .wrapper = mlx4_GEN_QP_wrapper
1203         },
1204         {
1205                 .opcode = MLX4_CMD_RTS2SQD_QP,
1206                 .has_inbox = false,
1207                 .has_outbox = false,
1208                 .out_is_imm = false,
1209                 .encode_slave_id = false,
1210                 .verify = NULL,
1211                 .wrapper = mlx4_GEN_QP_wrapper
1212         },
1213         {
1214                 .opcode = MLX4_CMD_SQD2SQD_QP,
1215                 .has_inbox = true,
1216                 .has_outbox = false,
1217                 .out_is_imm = false,
1218                 .encode_slave_id = false,
1219                 .verify = NULL,
1220                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1221         },
1222         {
1223                 .opcode = MLX4_CMD_SQD2RTS_QP,
1224                 .has_inbox = true,
1225                 .has_outbox = false,
1226                 .out_is_imm = false,
1227                 .encode_slave_id = false,
1228                 .verify = NULL,
1229                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1230         },
1231         {
1232                 .opcode = MLX4_CMD_2RST_QP,
1233                 .has_inbox = false,
1234                 .has_outbox = false,
1235                 .out_is_imm = false,
1236                 .encode_slave_id = false,
1237                 .verify = NULL,
1238                 .wrapper = mlx4_2RST_QP_wrapper
1239         },
1240         {
1241                 .opcode = MLX4_CMD_QUERY_QP,
1242                 .has_inbox = false,
1243                 .has_outbox = true,
1244                 .out_is_imm = false,
1245                 .encode_slave_id = false,
1246                 .verify = NULL,
1247                 .wrapper = mlx4_GEN_QP_wrapper
1248         },
1249         {
1250                 .opcode = MLX4_CMD_SUSPEND_QP,
1251                 .has_inbox = false,
1252                 .has_outbox = false,
1253                 .out_is_imm = false,
1254                 .encode_slave_id = false,
1255                 .verify = NULL,
1256                 .wrapper = mlx4_GEN_QP_wrapper
1257         },
1258         {
1259                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1260                 .has_inbox = false,
1261                 .has_outbox = false,
1262                 .out_is_imm = false,
1263                 .encode_slave_id = false,
1264                 .verify = NULL,
1265                 .wrapper = mlx4_GEN_QP_wrapper
1266         },
1267         {
1268                 .opcode = MLX4_CMD_UPDATE_QP,
1269                 .has_inbox = false,
1270                 .has_outbox = false,
1271                 .out_is_imm = false,
1272                 .encode_slave_id = false,
1273                 .verify = NULL,
1274                 .wrapper = mlx4_CMD_EPERM_wrapper
1275         },
1276         {
1277                 .opcode = MLX4_CMD_GET_OP_REQ,
1278                 .has_inbox = false,
1279                 .has_outbox = false,
1280                 .out_is_imm = false,
1281                 .encode_slave_id = false,
1282                 .verify = NULL,
1283                 .wrapper = mlx4_CMD_EPERM_wrapper,
1284         },
1285         {
1286                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1287                 .has_inbox = false,
1288                 .has_outbox = false,
1289                 .out_is_imm = false,
1290                 .encode_slave_id = false,
1291                 .verify = NULL, /* XXX verify: only demux can do this */
1292                 .wrapper = NULL
1293         },
1294         {
1295                 .opcode = MLX4_CMD_MAD_IFC,
1296                 .has_inbox = true,
1297                 .has_outbox = true,
1298                 .out_is_imm = false,
1299                 .encode_slave_id = false,
1300                 .verify = NULL,
1301                 .wrapper = mlx4_MAD_IFC_wrapper
1302         },
1303         {
1304                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1305                 .has_inbox = false,
1306                 .has_outbox = true,
1307                 .out_is_imm = false,
1308                 .encode_slave_id = false,
1309                 .verify = NULL,
1310                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1311         },
1312         /* Native multicast commands are not available for guests */
1313         {
1314                 .opcode = MLX4_CMD_QP_ATTACH,
1315                 .has_inbox = true,
1316                 .has_outbox = false,
1317                 .out_is_imm = false,
1318                 .encode_slave_id = false,
1319                 .verify = NULL,
1320                 .wrapper = mlx4_QP_ATTACH_wrapper
1321         },
1322         {
1323                 .opcode = MLX4_CMD_PROMISC,
1324                 .has_inbox = false,
1325                 .has_outbox = false,
1326                 .out_is_imm = false,
1327                 .encode_slave_id = false,
1328                 .verify = NULL,
1329                 .wrapper = mlx4_PROMISC_wrapper
1330         },
1331         /* Ethernet specific commands */
1332         {
1333                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1334                 .has_inbox = true,
1335                 .has_outbox = false,
1336                 .out_is_imm = false,
1337                 .encode_slave_id = false,
1338                 .verify = NULL,
1339                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1340         },
1341         {
1342                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1343                 .has_inbox = false,
1344                 .has_outbox = false,
1345                 .out_is_imm = false,
1346                 .encode_slave_id = false,
1347                 .verify = NULL,
1348                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1349         },
1350         {
1351                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1352                 .has_inbox = false,
1353                 .has_outbox = true,
1354                 .out_is_imm = false,
1355                 .encode_slave_id = false,
1356                 .verify = NULL,
1357                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1358         },
1359         {
1360                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1361                 .has_inbox = false,
1362                 .has_outbox = false,
1363                 .out_is_imm = false,
1364                 .encode_slave_id = false,
1365                 .verify = NULL,
1366                 .wrapper = NULL
1367         },
1368         /* flow steering commands */
1369         {
1370                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1371                 .has_inbox = true,
1372                 .has_outbox = false,
1373                 .out_is_imm = true,
1374                 .encode_slave_id = false,
1375                 .verify = NULL,
1376                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1377         },
1378         {
1379                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1380                 .has_inbox = false,
1381                 .has_outbox = false,
1382                 .out_is_imm = false,
1383                 .encode_slave_id = false,
1384                 .verify = NULL,
1385                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1386         },
1387         {
1388                 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1389                 .has_inbox = false,
1390                 .has_outbox = false,
1391                 .out_is_imm = false,
1392                 .encode_slave_id = false,
1393                 .verify = NULL,
1394                 .wrapper = mlx4_CMD_EPERM_wrapper
1395         },
1396 };
1397
1398 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1399                                     struct mlx4_vhcr_cmd *in_vhcr)
1400 {
1401         struct mlx4_priv *priv = mlx4_priv(dev);
1402         struct mlx4_cmd_info *cmd = NULL;
1403         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1404         struct mlx4_vhcr *vhcr;
1405         struct mlx4_cmd_mailbox *inbox = NULL;
1406         struct mlx4_cmd_mailbox *outbox = NULL;
1407         u64 in_param;
1408         u64 out_param;
1409         int ret = 0;
1410         int i;
1411         int err = 0;
1412
1413         /* Create sw representation of Virtual HCR */
1414         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1415         if (!vhcr)
1416                 return -ENOMEM;
1417
1418         /* DMA in the vHCR */
1419         if (!in_vhcr) {
1420                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1421                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1422                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1423                                             MLX4_ACCESS_MEM_ALIGN), 1);
1424                 if (ret) {
1425                         mlx4_err(dev, "%s:Failed reading vhcr"
1426                                  "ret: 0x%x\n", __func__, ret);
1427                         kfree(vhcr);
1428                         return ret;
1429                 }
1430         }
1431
1432         /* Fill SW VHCR fields */
1433         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1434         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1435         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1436         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1437         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1438         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1439         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1440
1441         /* Lookup command */
1442         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1443                 if (vhcr->op == cmd_info[i].opcode) {
1444                         cmd = &cmd_info[i];
1445                         break;
1446                 }
1447         }
1448         if (!cmd) {
1449                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1450                          vhcr->op, slave);
1451                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1452                 goto out_status;
1453         }
1454
1455         /* Read inbox */
1456         if (cmd->has_inbox) {
1457                 vhcr->in_param &= INBOX_MASK;
1458                 inbox = mlx4_alloc_cmd_mailbox(dev);
1459                 if (IS_ERR(inbox)) {
1460                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1461                         inbox = NULL;
1462                         goto out_status;
1463                 }
1464
1465                 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1466                                     vhcr->in_param,
1467                                     MLX4_MAILBOX_SIZE, 1)) {
1468                         mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1469                                  __func__, cmd->opcode);
1470                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1471                         goto out_status;
1472                 }
1473         }
1474
1475         /* Apply permission and bound checks if applicable */
1476         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1477                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1478                           "checks for resource_id:%d\n", vhcr->op, slave,
1479                           vhcr->in_modifier);
1480                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1481                 goto out_status;
1482         }
1483
1484         /* Allocate outbox */
1485         if (cmd->has_outbox) {
1486                 outbox = mlx4_alloc_cmd_mailbox(dev);
1487                 if (IS_ERR(outbox)) {
1488                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1489                         outbox = NULL;
1490                         goto out_status;
1491                 }
1492         }
1493
1494         /* Execute the command! */
1495         if (cmd->wrapper) {
1496                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1497                                    cmd);
1498                 if (cmd->out_is_imm)
1499                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1500         } else {
1501                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1502                         vhcr->in_param;
1503                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1504                         vhcr->out_param;
1505                 err = __mlx4_cmd(dev, in_param, &out_param,
1506                                  cmd->out_is_imm, vhcr->in_modifier,
1507                                  vhcr->op_modifier, vhcr->op,
1508                                  MLX4_CMD_TIME_CLASS_A,
1509                                  MLX4_CMD_NATIVE);
1510
1511                 if (cmd->out_is_imm) {
1512                         vhcr->out_param = out_param;
1513                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1514                 }
1515         }
1516
1517         if (err) {
1518                 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1519                           " error:%d, status %d\n",
1520                           vhcr->op, slave, vhcr->errno, err);
1521                 vhcr_cmd->status = mlx4_errno_to_status(err);
1522                 goto out_status;
1523         }
1524
1525
1526         /* Write outbox if command completed successfully */
1527         if (cmd->has_outbox && !vhcr_cmd->status) {
1528                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1529                                       vhcr->out_param,
1530                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1531                 if (ret) {
1532                         /* If we failed to write back the outbox after the
1533                          *command was successfully executed, we must fail this
1534                          * slave, as it is now in undefined state */
1535                         mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1536                         goto out;
1537                 }
1538         }
1539
1540 out_status:
1541         /* DMA back vhcr result */
1542         if (!in_vhcr) {
1543                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1544                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1545                                       ALIGN(sizeof(struct mlx4_vhcr),
1546                                             MLX4_ACCESS_MEM_ALIGN),
1547                                       MLX4_CMD_WRAPPED);
1548                 if (ret)
1549                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1550                                  __func__);
1551                 else if (vhcr->e_bit &&
1552                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1553                                 mlx4_warn(dev, "Failed to generate command completion "
1554                                           "eqe for slave %d\n", slave);
1555         }
1556
1557 out:
1558         kfree(vhcr);
1559         mlx4_free_cmd_mailbox(dev, inbox);
1560         mlx4_free_cmd_mailbox(dev, outbox);
1561         return ret;
1562 }
1563
1564 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1565                                             int slave, int port)
1566 {
1567         struct mlx4_vport_oper_state *vp_oper;
1568         struct mlx4_vport_state *vp_admin;
1569         struct mlx4_vf_immed_vlan_work *work;
1570         struct mlx4_dev *dev = &(priv->dev);
1571         int err;
1572         int admin_vlan_ix = NO_INDX;
1573
1574         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1575         vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1576
1577         if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1578             vp_oper->state.default_qos == vp_admin->default_qos &&
1579             vp_oper->state.link_state == vp_admin->link_state)
1580                 return 0;
1581
1582         if (!(priv->mfunc.master.slave_state[slave].active &&
1583               dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1584                 /* even if the UPDATE_QP command isn't supported, we still want
1585                  * to set this VF link according to the admin directive
1586                  */
1587                 vp_oper->state.link_state = vp_admin->link_state;
1588                 return -1;
1589         }
1590
1591         mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1592                  slave, port);
1593         mlx4_dbg(dev, "vlan %d QoS %d link down %d\n", vp_admin->default_vlan,
1594                  vp_admin->default_qos, vp_admin->link_state);
1595
1596         work = kzalloc(sizeof(*work), GFP_KERNEL);
1597         if (!work)
1598                 return -ENOMEM;
1599
1600         if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1601                 if (MLX4_VGT != vp_admin->default_vlan) {
1602                         err = __mlx4_register_vlan(&priv->dev, port,
1603                                                    vp_admin->default_vlan,
1604                                                    &admin_vlan_ix);
1605                         if (err) {
1606                                 kfree(work);
1607                                 mlx4_warn((&priv->dev),
1608                                           "No vlan resources slave %d, port %d\n",
1609                                           slave, port);
1610                                 return err;
1611                         }
1612                 } else {
1613                         admin_vlan_ix = NO_INDX;
1614                 }
1615                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1616                 mlx4_dbg((&(priv->dev)),
1617                          "alloc vlan %d idx  %d slave %d port %d\n",
1618                          (int)(vp_admin->default_vlan),
1619                          admin_vlan_ix, slave, port);
1620         }
1621
1622         /* save original vlan ix and vlan id */
1623         work->orig_vlan_id = vp_oper->state.default_vlan;
1624         work->orig_vlan_ix = vp_oper->vlan_idx;
1625
1626         /* handle new qos */
1627         if (vp_oper->state.default_qos != vp_admin->default_qos)
1628                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1629
1630         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1631                 vp_oper->vlan_idx = admin_vlan_ix;
1632
1633         vp_oper->state.default_vlan = vp_admin->default_vlan;
1634         vp_oper->state.default_qos = vp_admin->default_qos;
1635         vp_oper->state.link_state = vp_admin->link_state;
1636
1637         if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1638                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1639
1640         /* iterate over QPs owned by this slave, using UPDATE_QP */
1641         work->port = port;
1642         work->slave = slave;
1643         work->qos = vp_oper->state.default_qos;
1644         work->vlan_id = vp_oper->state.default_vlan;
1645         work->vlan_ix = vp_oper->vlan_idx;
1646         work->priv = priv;
1647         INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1648         queue_work(priv->mfunc.master.comm_wq, &work->work);
1649
1650         return 0;
1651 }
1652
1653
1654 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1655 {
1656         int port, err;
1657         struct mlx4_vport_state *vp_admin;
1658         struct mlx4_vport_oper_state *vp_oper;
1659         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1660                         &priv->dev, slave);
1661         int min_port = find_first_bit(actv_ports.ports,
1662                                       priv->dev.caps.num_ports) + 1;
1663         int max_port = min_port - 1 +
1664                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1665
1666         for (port = min_port; port <= max_port; port++) {
1667                 if (!test_bit(port - 1, actv_ports.ports))
1668                         continue;
1669                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1670                         priv->mfunc.master.vf_admin[slave].enable_smi[port];
1671                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1672                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1673                 vp_oper->state = *vp_admin;
1674                 if (MLX4_VGT != vp_admin->default_vlan) {
1675                         err = __mlx4_register_vlan(&priv->dev, port,
1676                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
1677                         if (err) {
1678                                 vp_oper->vlan_idx = NO_INDX;
1679                                 mlx4_warn((&priv->dev),
1680                                           "No vlan resorces slave %d, port %d\n",
1681                                           slave, port);
1682                                 return err;
1683                         }
1684                         mlx4_dbg((&(priv->dev)), "alloc vlan %d idx  %d slave %d port %d\n",
1685                                  (int)(vp_oper->state.default_vlan),
1686                                  vp_oper->vlan_idx, slave, port);
1687                 }
1688                 if (vp_admin->spoofchk) {
1689                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1690                                                                port,
1691                                                                vp_admin->mac);
1692                         if (0 > vp_oper->mac_idx) {
1693                                 err = vp_oper->mac_idx;
1694                                 vp_oper->mac_idx = NO_INDX;
1695                                 mlx4_warn((&priv->dev),
1696                                           "No mac resorces slave %d, port %d\n",
1697                                           slave, port);
1698                                 return err;
1699                         }
1700                         mlx4_dbg((&(priv->dev)), "alloc mac %llx idx  %d slave %d port %d\n",
1701                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1702                 }
1703         }
1704         return 0;
1705 }
1706
1707 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1708 {
1709         int port;
1710         struct mlx4_vport_oper_state *vp_oper;
1711         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1712                         &priv->dev, slave);
1713         int min_port = find_first_bit(actv_ports.ports,
1714                                       priv->dev.caps.num_ports) + 1;
1715         int max_port = min_port - 1 +
1716                 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1717
1718
1719         for (port = min_port; port <= max_port; port++) {
1720                 if (!test_bit(port - 1, actv_ports.ports))
1721                         continue;
1722                 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1723                         MLX4_VF_SMI_DISABLED;
1724                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1725                 if (NO_INDX != vp_oper->vlan_idx) {
1726                         __mlx4_unregister_vlan(&priv->dev,
1727                                                port, vp_oper->state.default_vlan);
1728                         vp_oper->vlan_idx = NO_INDX;
1729                 }
1730                 if (NO_INDX != vp_oper->mac_idx) {
1731                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
1732                         vp_oper->mac_idx = NO_INDX;
1733                 }
1734         }
1735         return;
1736 }
1737
1738 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1739                                u16 param, u8 toggle)
1740 {
1741         struct mlx4_priv *priv = mlx4_priv(dev);
1742         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1743         u32 reply;
1744         u8 is_going_down = 0;
1745         int i;
1746         unsigned long flags;
1747
1748         slave_state[slave].comm_toggle ^= 1;
1749         reply = (u32) slave_state[slave].comm_toggle << 31;
1750         if (toggle != slave_state[slave].comm_toggle) {
1751                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1752                           "STATE COMPROMISIED ***\n", toggle, slave);
1753                 goto reset_slave;
1754         }
1755         if (cmd == MLX4_COMM_CMD_RESET) {
1756                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1757                 slave_state[slave].active = false;
1758                 slave_state[slave].old_vlan_api = false;
1759                 mlx4_master_deactivate_admin_state(priv, slave);
1760                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1761                                 slave_state[slave].event_eq[i].eqn = -1;
1762                                 slave_state[slave].event_eq[i].token = 0;
1763                 }
1764                 /*check if we are in the middle of FLR process,
1765                 if so return "retry" status to the slave*/
1766                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1767                         goto inform_slave_state;
1768
1769                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1770
1771                 /* write the version in the event field */
1772                 reply |= mlx4_comm_get_version();
1773
1774                 goto reset_slave;
1775         }
1776         /*command from slave in the middle of FLR*/
1777         if (cmd != MLX4_COMM_CMD_RESET &&
1778             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1779                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1780                           "in the middle of FLR\n", slave, cmd);
1781                 return;
1782         }
1783
1784         switch (cmd) {
1785         case MLX4_COMM_CMD_VHCR0:
1786                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1787                         goto reset_slave;
1788                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1789                 priv->mfunc.master.slave_state[slave].cookie = 0;
1790                 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1791                 break;
1792         case MLX4_COMM_CMD_VHCR1:
1793                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1794                         goto reset_slave;
1795                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1796                 break;
1797         case MLX4_COMM_CMD_VHCR2:
1798                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1799                         goto reset_slave;
1800                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1801                 break;
1802         case MLX4_COMM_CMD_VHCR_EN:
1803                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1804                         goto reset_slave;
1805                 slave_state[slave].vhcr_dma |= param;
1806                 if (mlx4_master_activate_admin_state(priv, slave))
1807                                 goto reset_slave;
1808                 slave_state[slave].active = true;
1809                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1810                 break;
1811         case MLX4_COMM_CMD_VHCR_POST:
1812                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1813                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1814                         goto reset_slave;
1815
1816                 mutex_lock(&priv->cmd.slave_cmd_mutex);
1817                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1818                         mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1819                                  " resetting slave.\n", slave);
1820                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1821                         goto reset_slave;
1822                 }
1823                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1824                 break;
1825         default:
1826                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1827                 goto reset_slave;
1828         }
1829         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1830         if (!slave_state[slave].is_slave_going_down)
1831                 slave_state[slave].last_cmd = cmd;
1832         else
1833                 is_going_down = 1;
1834         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1835         if (is_going_down) {
1836                 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1837                           " executing from slave:%d\n",
1838                           cmd, slave);
1839                 return;
1840         }
1841         __raw_writel((__force u32) cpu_to_be32(reply),
1842                      &priv->mfunc.comm[slave].slave_read);
1843         mmiowb();
1844
1845         return;
1846
1847 reset_slave:
1848         /* cleanup any slave resources */
1849         mlx4_delete_all_resources_for_slave(dev, slave);
1850         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1851         if (!slave_state[slave].is_slave_going_down)
1852                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1853         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1854         /*with slave in the middle of flr, no need to clean resources again.*/
1855 inform_slave_state:
1856         memset(&slave_state[slave].event_eq, 0,
1857                sizeof(struct mlx4_slave_event_eq_info));
1858         __raw_writel((__force u32) cpu_to_be32(reply),
1859                      &priv->mfunc.comm[slave].slave_read);
1860         wmb();
1861 }
1862
1863 /* master command processing */
1864 void mlx4_master_comm_channel(struct work_struct *work)
1865 {
1866         struct mlx4_mfunc_master_ctx *master =
1867                 container_of(work,
1868                              struct mlx4_mfunc_master_ctx,
1869                              comm_work);
1870         struct mlx4_mfunc *mfunc =
1871                 container_of(master, struct mlx4_mfunc, master);
1872         struct mlx4_priv *priv =
1873                 container_of(mfunc, struct mlx4_priv, mfunc);
1874         struct mlx4_dev *dev = &priv->dev;
1875         __be32 *bit_vec;
1876         u32 comm_cmd;
1877         u32 vec;
1878         int i, j, slave;
1879         int toggle;
1880         int served = 0;
1881         int reported = 0;
1882         u32 slt;
1883
1884         bit_vec = master->comm_arm_bit_vector;
1885         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1886                 vec = be32_to_cpu(bit_vec[i]);
1887                 for (j = 0; j < 32; j++) {
1888                         if (!(vec & (1 << j)))
1889                                 continue;
1890                         ++reported;
1891                         slave = (i * 32) + j;
1892                         comm_cmd = swab32(readl(
1893                                           &mfunc->comm[slave].slave_write));
1894                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
1895                                      >> 31;
1896                         toggle = comm_cmd >> 31;
1897                         if (toggle != slt) {
1898                                 if (master->slave_state[slave].comm_toggle
1899                                     != slt) {
1900                                         printk(KERN_INFO "slave %d out of sync."
1901                                                " read toggle %d, state toggle %d. "
1902                                                "Resynching.\n", slave, slt,
1903                                                master->slave_state[slave].comm_toggle);
1904                                         master->slave_state[slave].comm_toggle =
1905                                                 slt;
1906                                 }
1907                                 mlx4_master_do_cmd(dev, slave,
1908                                                    comm_cmd >> 16 & 0xff,
1909                                                    comm_cmd & 0xffff, toggle);
1910                                 ++served;
1911                         }
1912                 }
1913         }
1914
1915         if (reported && reported != served)
1916                 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1917                           " but %d were served\n",
1918                           reported, served);
1919
1920         if (mlx4_ARM_COMM_CHANNEL(dev))
1921                 mlx4_warn(dev, "Failed to arm comm channel events\n");
1922 }
1923
1924 static int sync_toggles(struct mlx4_dev *dev)
1925 {
1926         struct mlx4_priv *priv = mlx4_priv(dev);
1927         int wr_toggle;
1928         int rd_toggle;
1929         unsigned long end;
1930
1931         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1932         end = jiffies + msecs_to_jiffies(5000);
1933
1934         while (time_before(jiffies, end)) {
1935                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1936                 if (rd_toggle == wr_toggle) {
1937                         priv->cmd.comm_toggle = rd_toggle;
1938                         return 0;
1939                 }
1940
1941                 cond_resched();
1942         }
1943
1944         /*
1945          * we could reach here if for example the previous VM using this
1946          * function misbehaved and left the channel with unsynced state. We
1947          * should fix this here and give this VM a chance to use a properly
1948          * synced channel
1949          */
1950         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1951         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1952         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1953         priv->cmd.comm_toggle = 0;
1954
1955         return 0;
1956 }
1957
1958 int mlx4_multi_func_init(struct mlx4_dev *dev)
1959 {
1960         struct mlx4_priv *priv = mlx4_priv(dev);
1961         struct mlx4_slave_state *s_state;
1962         int i, j, err, port;
1963
1964         if (mlx4_is_master(dev))
1965                 priv->mfunc.comm =
1966                 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1967                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1968         else
1969                 priv->mfunc.comm =
1970                 ioremap(pci_resource_start(dev->pdev, 2) +
1971                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1972         if (!priv->mfunc.comm) {
1973                 mlx4_err(dev, "Couldn't map communication vector.\n");
1974                 goto err_vhcr;
1975         }
1976
1977         if (mlx4_is_master(dev)) {
1978                 priv->mfunc.master.slave_state =
1979                         kzalloc(dev->num_slaves *
1980                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1981                 if (!priv->mfunc.master.slave_state)
1982                         goto err_comm;
1983
1984                 priv->mfunc.master.vf_admin =
1985                         kzalloc(dev->num_slaves *
1986                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1987                 if (!priv->mfunc.master.vf_admin)
1988                         goto err_comm_admin;
1989
1990                 priv->mfunc.master.vf_oper =
1991                         kzalloc(dev->num_slaves *
1992                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1993                 if (!priv->mfunc.master.vf_oper)
1994                         goto err_comm_oper;
1995
1996                 for (i = 0; i < dev->num_slaves; ++i) {
1997                         s_state = &priv->mfunc.master.slave_state[i];
1998                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
1999                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2000                                 s_state->event_eq[j].eqn = -1;
2001                         __raw_writel((__force u32) 0,
2002                                      &priv->mfunc.comm[i].slave_write);
2003                         __raw_writel((__force u32) 0,
2004                                      &priv->mfunc.comm[i].slave_read);
2005                         mmiowb();
2006                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2007                                 s_state->vlan_filter[port] =
2008                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
2009                                                 GFP_KERNEL);
2010                                 if (!s_state->vlan_filter[port]) {
2011                                         if (--port)
2012                                                 kfree(s_state->vlan_filter[port]);
2013                                         goto err_slaves;
2014                                 }
2015                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2016                                 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
2017                                 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
2018                                 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2019                                 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
2020                         }
2021                         spin_lock_init(&s_state->lock);
2022                 }
2023
2024                 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2025                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2026                 INIT_WORK(&priv->mfunc.master.comm_work,
2027                           mlx4_master_comm_channel);
2028                 INIT_WORK(&priv->mfunc.master.slave_event_work,
2029                           mlx4_gen_slave_eqe);
2030                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2031                           mlx4_master_handle_slave_flr);
2032                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2033                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2034                 priv->mfunc.master.comm_wq =
2035                         create_singlethread_workqueue("mlx4_comm");
2036                 if (!priv->mfunc.master.comm_wq)
2037                         goto err_slaves;
2038
2039                 if (mlx4_init_resource_tracker(dev))
2040                         goto err_thread;
2041
2042                 err = mlx4_ARM_COMM_CHANNEL(dev);
2043                 if (err) {
2044                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2045                                  err);
2046                         goto err_resource;
2047                 }
2048
2049         } else {
2050                 err = sync_toggles(dev);
2051                 if (err) {
2052                         mlx4_err(dev, "Couldn't sync toggles\n");
2053                         goto err_comm;
2054                 }
2055         }
2056         return 0;
2057
2058 err_resource:
2059         mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
2060 err_thread:
2061         flush_workqueue(priv->mfunc.master.comm_wq);
2062         destroy_workqueue(priv->mfunc.master.comm_wq);
2063 err_slaves:
2064         while (--i) {
2065                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2066                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2067         }
2068         kfree(priv->mfunc.master.vf_oper);
2069 err_comm_oper:
2070         kfree(priv->mfunc.master.vf_admin);
2071 err_comm_admin:
2072         kfree(priv->mfunc.master.slave_state);
2073 err_comm:
2074         iounmap(priv->mfunc.comm);
2075 err_vhcr:
2076         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2077                                              priv->mfunc.vhcr,
2078                                              priv->mfunc.vhcr_dma);
2079         priv->mfunc.vhcr = NULL;
2080         return -ENOMEM;
2081 }
2082
2083 int mlx4_cmd_init(struct mlx4_dev *dev)
2084 {
2085         struct mlx4_priv *priv = mlx4_priv(dev);
2086
2087         mutex_init(&priv->cmd.hcr_mutex);
2088         mutex_init(&priv->cmd.slave_cmd_mutex);
2089         sema_init(&priv->cmd.poll_sem, 1);
2090         priv->cmd.use_events = 0;
2091         priv->cmd.toggle     = 1;
2092
2093         priv->cmd.hcr = NULL;
2094         priv->mfunc.vhcr = NULL;
2095
2096         if (!mlx4_is_slave(dev)) {
2097                 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2098                                         MLX4_HCR_BASE, MLX4_HCR_SIZE);
2099                 if (!priv->cmd.hcr) {
2100                         mlx4_err(dev, "Couldn't map command register.\n");
2101                         return -ENOMEM;
2102                 }
2103         }
2104
2105         if (mlx4_is_mfunc(dev)) {
2106                 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2107                                                       &priv->mfunc.vhcr_dma,
2108                                                       GFP_KERNEL);
2109                 if (!priv->mfunc.vhcr)
2110                         goto err_hcr;
2111         }
2112
2113         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2114                                          MLX4_MAILBOX_SIZE,
2115                                          MLX4_MAILBOX_SIZE, 0);
2116         if (!priv->cmd.pool)
2117                 goto err_vhcr;
2118
2119         return 0;
2120
2121 err_vhcr:
2122         if (mlx4_is_mfunc(dev))
2123                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2124                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2125         priv->mfunc.vhcr = NULL;
2126
2127 err_hcr:
2128         if (!mlx4_is_slave(dev))
2129                 iounmap(priv->cmd.hcr);
2130         return -ENOMEM;
2131 }
2132
2133 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2134 {
2135         struct mlx4_priv *priv = mlx4_priv(dev);
2136         int i, port;
2137
2138         if (mlx4_is_master(dev)) {
2139                 flush_workqueue(priv->mfunc.master.comm_wq);
2140                 destroy_workqueue(priv->mfunc.master.comm_wq);
2141                 for (i = 0; i < dev->num_slaves; i++) {
2142                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
2143                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2144                 }
2145                 kfree(priv->mfunc.master.slave_state);
2146                 kfree(priv->mfunc.master.vf_admin);
2147                 kfree(priv->mfunc.master.vf_oper);
2148         }
2149
2150         iounmap(priv->mfunc.comm);
2151 }
2152
2153 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2154 {
2155         struct mlx4_priv *priv = mlx4_priv(dev);
2156
2157         pci_pool_destroy(priv->cmd.pool);
2158
2159         if (!mlx4_is_slave(dev))
2160                 iounmap(priv->cmd.hcr);
2161         if (mlx4_is_mfunc(dev))
2162                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2163                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2164         priv->mfunc.vhcr = NULL;
2165 }
2166
2167 /*
2168  * Switch to using events to issue FW commands (can only be called
2169  * after event queue for command events has been initialized).
2170  */
2171 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2172 {
2173         struct mlx4_priv *priv = mlx4_priv(dev);
2174         int i;
2175         int err = 0;
2176
2177         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2178                                    sizeof (struct mlx4_cmd_context),
2179                                    GFP_KERNEL);
2180         if (!priv->cmd.context)
2181                 return -ENOMEM;
2182
2183         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2184                 priv->cmd.context[i].token = i;
2185                 priv->cmd.context[i].next  = i + 1;
2186         }
2187
2188         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2189         priv->cmd.free_head = 0;
2190
2191         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2192         spin_lock_init(&priv->cmd.context_lock);
2193
2194         for (priv->cmd.token_mask = 1;
2195              priv->cmd.token_mask < priv->cmd.max_cmds;
2196              priv->cmd.token_mask <<= 1)
2197                 ; /* nothing */
2198         --priv->cmd.token_mask;
2199
2200         down(&priv->cmd.poll_sem);
2201         priv->cmd.use_events = 1;
2202
2203         return err;
2204 }
2205
2206 /*
2207  * Switch back to polling (used when shutting down the device)
2208  */
2209 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2210 {
2211         struct mlx4_priv *priv = mlx4_priv(dev);
2212         int i;
2213
2214         priv->cmd.use_events = 0;
2215
2216         for (i = 0; i < priv->cmd.max_cmds; ++i)
2217                 down(&priv->cmd.event_sem);
2218
2219         kfree(priv->cmd.context);
2220
2221         up(&priv->cmd.poll_sem);
2222 }
2223
2224 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2225 {
2226         struct mlx4_cmd_mailbox *mailbox;
2227
2228         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2229         if (!mailbox)
2230                 return ERR_PTR(-ENOMEM);
2231
2232         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2233                                       &mailbox->dma);
2234         if (!mailbox->buf) {
2235                 kfree(mailbox);
2236                 return ERR_PTR(-ENOMEM);
2237         }
2238
2239         memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2240
2241         return mailbox;
2242 }
2243 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2244
2245 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2246                            struct mlx4_cmd_mailbox *mailbox)
2247 {
2248         if (!mailbox)
2249                 return;
2250
2251         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2252         kfree(mailbox);
2253 }
2254 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2255
2256 u32 mlx4_comm_get_version(void)
2257 {
2258          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2259 }
2260
2261 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2262 {
2263         if ((vf < 0) || (vf >= dev->num_vfs)) {
2264                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2265                 return -EINVAL;
2266         }
2267
2268         return vf+1;
2269 }
2270
2271 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2272 {
2273         if (slave < 1 || slave > dev->num_vfs) {
2274                 mlx4_err(dev,
2275                          "Bad slave number:%d (number of activated slaves: %lu)\n",
2276                          slave, dev->num_slaves);
2277                 return -EINVAL;
2278         }
2279         return slave - 1;
2280 }
2281
2282 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2283 {
2284         struct mlx4_active_ports actv_ports;
2285         int vf;
2286
2287         bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2288
2289         if (slave == 0) {
2290                 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2291                 return actv_ports;
2292         }
2293
2294         vf = mlx4_get_vf_indx(dev, slave);
2295         if (vf < 0)
2296                 return actv_ports;
2297
2298         bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2299                    min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2300                    dev->caps.num_ports));
2301
2302         return actv_ports;
2303 }
2304 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2305
2306 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2307 {
2308         unsigned n;
2309         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2310         unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2311
2312         if (port <= 0 || port > m)
2313                 return -EINVAL;
2314
2315         n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2316         if (port <= n)
2317                 port = n + 1;
2318
2319         return port;
2320 }
2321 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2322
2323 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2324 {
2325         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2326         if (test_bit(port - 1, actv_ports.ports))
2327                 return port -
2328                         find_first_bit(actv_ports.ports, dev->caps.num_ports);
2329
2330         return -1;
2331 }
2332 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2333
2334 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2335                                                    int port)
2336 {
2337         unsigned i;
2338         struct mlx4_slaves_pport slaves_pport;
2339
2340         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2341
2342         if (port <= 0 || port > dev->caps.num_ports)
2343                 return slaves_pport;
2344
2345         for (i = 0; i < dev->num_vfs + 1; i++) {
2346                 struct mlx4_active_ports actv_ports =
2347                         mlx4_get_active_ports(dev, i);
2348                 if (test_bit(port - 1, actv_ports.ports))
2349                         set_bit(i, slaves_pport.slaves);
2350         }
2351
2352         return slaves_pport;
2353 }
2354 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2355
2356 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2357                 struct mlx4_dev *dev,
2358                 const struct mlx4_active_ports *crit_ports)
2359 {
2360         unsigned i;
2361         struct mlx4_slaves_pport slaves_pport;
2362
2363         bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2364
2365         for (i = 0; i < dev->num_vfs + 1; i++) {
2366                 struct mlx4_active_ports actv_ports =
2367                         mlx4_get_active_ports(dev, i);
2368                 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2369                                  dev->caps.num_ports))
2370                         set_bit(i, slaves_pport.slaves);
2371         }
2372
2373         return slaves_pport;
2374 }
2375 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2376
2377 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2378 {
2379         struct mlx4_priv *priv = mlx4_priv(dev);
2380         struct mlx4_vport_state *s_info;
2381         int slave;
2382
2383         if (!mlx4_is_master(dev))
2384                 return -EPROTONOSUPPORT;
2385
2386         slave = mlx4_get_slave_indx(dev, vf);
2387         if (slave < 0)
2388                 return -EINVAL;
2389
2390         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2391         s_info->mac = mac;
2392         mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2393                   vf, port, s_info->mac);
2394         return 0;
2395 }
2396 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2397
2398
2399 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2400 {
2401         struct mlx4_priv *priv = mlx4_priv(dev);
2402         struct mlx4_vport_state *vf_admin;
2403         int slave;
2404
2405         if ((!mlx4_is_master(dev)) ||
2406             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2407                 return -EPROTONOSUPPORT;
2408
2409         if ((vlan > 4095) || (qos > 7))
2410                 return -EINVAL;
2411
2412         slave = mlx4_get_slave_indx(dev, vf);
2413         if (slave < 0)
2414                 return -EINVAL;
2415
2416         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2417
2418         if ((0 == vlan) && (0 == qos))
2419                 vf_admin->default_vlan = MLX4_VGT;
2420         else
2421                 vf_admin->default_vlan = vlan;
2422         vf_admin->default_qos = qos;
2423
2424         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2425                 mlx4_info(dev,
2426                           "updating vf %d port %d config will take effect on next VF restart\n",
2427                           vf, port);
2428         return 0;
2429 }
2430 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2431
2432  /* mlx4_get_slave_default_vlan -
2433  * return true if VST ( default vlan)
2434  * if VST, will return vlan & qos (if not NULL)
2435  */
2436 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2437                                  u16 *vlan, u8 *qos)
2438 {
2439         struct mlx4_vport_oper_state *vp_oper;
2440         struct mlx4_priv *priv;
2441
2442         priv = mlx4_priv(dev);
2443         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2444
2445         if (MLX4_VGT != vp_oper->state.default_vlan) {
2446                 if (vlan)
2447                         *vlan = vp_oper->state.default_vlan;
2448                 if (qos)
2449                         *qos = vp_oper->state.default_qos;
2450                 return true;
2451         }
2452         return false;
2453 }
2454 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2455
2456 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2457 {
2458         struct mlx4_priv *priv = mlx4_priv(dev);
2459         struct mlx4_vport_state *s_info;
2460         int slave;
2461
2462         if ((!mlx4_is_master(dev)) ||
2463             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2464                 return -EPROTONOSUPPORT;
2465
2466         slave = mlx4_get_slave_indx(dev, vf);
2467         if (slave < 0)
2468                 return -EINVAL;
2469
2470         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2471         s_info->spoofchk = setting;
2472
2473         return 0;
2474 }
2475 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2476
2477 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2478 {
2479         struct mlx4_priv *priv = mlx4_priv(dev);
2480         struct mlx4_vport_state *s_info;
2481         int slave;
2482
2483         if (!mlx4_is_master(dev))
2484                 return -EPROTONOSUPPORT;
2485
2486         slave = mlx4_get_slave_indx(dev, vf);
2487         if (slave < 0)
2488                 return -EINVAL;
2489
2490         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2491         ivf->vf = vf;
2492
2493         /* need to convert it to a func */
2494         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2495         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2496         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2497         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2498         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2499         ivf->mac[5] = ((s_info->mac)  & 0xff);
2500
2501         ivf->vlan       = s_info->default_vlan;
2502         ivf->qos        = s_info->default_qos;
2503         ivf->tx_rate    = s_info->tx_rate;
2504         ivf->spoofchk   = s_info->spoofchk;
2505         ivf->linkstate  = s_info->link_state;
2506
2507         return 0;
2508 }
2509 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2510
2511 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2512 {
2513         struct mlx4_priv *priv = mlx4_priv(dev);
2514         struct mlx4_vport_state *s_info;
2515         int slave;
2516         u8 link_stat_event;
2517
2518         slave = mlx4_get_slave_indx(dev, vf);
2519         if (slave < 0)
2520                 return -EINVAL;
2521
2522         switch (link_state) {
2523         case IFLA_VF_LINK_STATE_AUTO:
2524                 /* get current link state */
2525                 if (!priv->sense.do_sense_port[port])
2526                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2527                 else
2528                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2529             break;
2530
2531         case IFLA_VF_LINK_STATE_ENABLE:
2532                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2533             break;
2534
2535         case IFLA_VF_LINK_STATE_DISABLE:
2536                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2537             break;
2538
2539         default:
2540                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2541                           link_state, slave, port);
2542                 return -EINVAL;
2543         };
2544         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2545         s_info->link_state = link_state;
2546
2547         /* send event */
2548         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2549
2550         if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2551                 mlx4_dbg(dev,
2552                          "updating vf %d port %d no link state HW enforcment\n",
2553                          vf, port);
2554         return 0;
2555 }
2556 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
2557
2558 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2559 {
2560         struct mlx4_priv *priv = mlx4_priv(dev);
2561
2562         if (slave < 1 || slave >= dev->num_slaves ||
2563             port < 1 || port > MLX4_MAX_PORTS)
2564                 return 0;
2565
2566         return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2567                 MLX4_VF_SMI_ENABLED;
2568 }
2569 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);