drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/semaphore.h>
  43
  44 #include <asm/io.h>
  45
  46 #include "mlx4.h"
  47 #include "fw.h"
  48
  49 #define CMD_POLL_TOKEN 0xffff
  50 #define INBOX_MASK      0xffffffffffffff00ULL
  51
  52 #define CMD_CHAN_VER 1
  53 #define CMD_CHAN_IF_REV 1
  54
  55 enum {
  56         /* command completed successfully: */
  57         CMD_STAT_OK             = 0x00,
  58         /* Internal error (such as a bus error) occurred while processing command: */
  59         CMD_STAT_INTERNAL_ERR   = 0x01,
  60         /* Operation/command not supported or opcode modifier not supported: */
  61         CMD_STAT_BAD_OP         = 0x02,
  62         /* Parameter not supported or parameter out of range: */
  63         CMD_STAT_BAD_PARAM      = 0x03,
  64         /* System not enabled or bad system state: */
  65         CMD_STAT_BAD_SYS_STATE  = 0x04,
  66         /* Attempt to access reserved or unallocaterd resource: */
  67         CMD_STAT_BAD_RESOURCE   = 0x05,
  68         /* Requested resource is currently executing a command, or is otherwise busy: */
  69         CMD_STAT_RESOURCE_BUSY  = 0x06,
  70         /* Required capability exceeds device limits: */
  71         CMD_STAT_EXCEED_LIM     = 0x08,
  72         /* Resource is not in the appropriate state or ownership: */
  73         CMD_STAT_BAD_RES_STATE  = 0x09,
  74         /* Index out of range: */
  75         CMD_STAT_BAD_INDEX      = 0x0a,
  76         /* FW image corrupted: */
  77         CMD_STAT_BAD_NVMEM      = 0x0b,
  78         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  79         CMD_STAT_ICM_ERROR      = 0x0c,
  80         /* Attempt to modify a QP/EE which is not in the presumed state: */
  81         CMD_STAT_BAD_QP_STATE   = 0x10,
  82         /* Bad segment parameters (Address/Size): */
  83         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  84         /* Memory Region has Memory Windows bound to: */
  85         CMD_STAT_REG_BOUND      = 0x21,
  86         /* HCA local attached memory not present: */
  87         CMD_STAT_LAM_NOT_PRE    = 0x22,
  88         /* Bad management packet (silently discarded): */
  89         CMD_STAT_BAD_PKT        = 0x30,
  90         /* More outstanding CQEs in CQ than new CQ size: */
  91         CMD_STAT_BAD_SIZE       = 0x40,
  92         /* Multi Function device support required: */
  93         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  94 };
  95
  96 enum {
  97         HCR_IN_PARAM_OFFSET     = 0x00,
  98         HCR_IN_MODIFIER_OFFSET  = 0x08,
  99         HCR_OUT_PARAM_OFFSET    = 0x0c,
 100         HCR_TOKEN_OFFSET        = 0x14,
 101         HCR_STATUS_OFFSET       = 0x18,
 102
 103         HCR_OPMOD_SHIFT         = 12,
 104         HCR_T_BIT               = 21,
 105         HCR_E_BIT               = 22,
 106         HCR_GO_BIT              = 23
 107 };
 108
 109 enum {
 110         GO_BIT_TIMEOUT_MSECS    = 10000
 111 };
 112
 113 struct mlx4_cmd_context {
 114         struct completion       done;
 115         int                     result;
 116         int                     next;
 117         u64                     out_param;
 118         u16                     token;
 119         u8                      fw_status;
 120 };
 121
 122 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 123                                     struct mlx4_vhcr_cmd *in_vhcr);
 124
 125 static int mlx4_status_to_errno(u8 status)
 126 {
 127         static const int trans_table[] = {
 128                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 129                 [CMD_STAT_BAD_OP]         = -EPERM,
 130                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 131                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 132                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 133                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 134                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 135                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 136                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 137                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 138                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 139                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 140                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 141                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 142                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 143                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 144                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 145                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 146         };
 147
 148         if (status >= ARRAY_SIZE(trans_table) ||
 149             (status != CMD_STAT_OK && trans_table[status] == 0))
 150                 return -EIO;
 151
 152         return trans_table[status];
 153 }
 154
 155 static u8 mlx4_errno_to_status(int errno)
 156 {
 157         switch (errno) {
 158         case -EPERM:
 159                 return CMD_STAT_BAD_OP;
 160         case -EINVAL:
 161                 return CMD_STAT_BAD_PARAM;
 162         case -ENXIO:
 163                 return CMD_STAT_BAD_SYS_STATE;
 164         case -EBUSY:
 165                 return CMD_STAT_RESOURCE_BUSY;
 166         case -ENOMEM:
 167                 return CMD_STAT_EXCEED_LIM;
 168         case -ENFILE:
 169                 return CMD_STAT_ICM_ERROR;
 170         default:
 171                 return CMD_STAT_INTERNAL_ERR;
 172         }
 173 }
 174
 175 static int comm_pending(struct mlx4_dev *dev)
 176 {
 177         struct mlx4_priv *priv = mlx4_priv(dev);
 178         u32 status = readl(&priv->mfunc.comm->slave_read);
 179
 180         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 181 }
 182
 183 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 184 {
 185         struct mlx4_priv *priv = mlx4_priv(dev);
 186         u32 val;
 187
 188         priv->cmd.comm_toggle ^= 1;
 189         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 190         __raw_writel((__force u32) cpu_to_be32(val),
 191                      &priv->mfunc.comm->slave_write);
 192         mmiowb();
 193 }
 194
 195 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 196                        unsigned long timeout)
 197 {
 198         struct mlx4_priv *priv = mlx4_priv(dev);
 199         unsigned long end;
 200         int err = 0;
 201         int ret_from_pending = 0;
 202
 203         /* First, verify that the master reports correct status */
 204         if (comm_pending(dev)) {
 205                 mlx4_warn(dev, "Communication channel is not idle."
 206                           "my toggle is %d (cmd:0x%x)\n",
 207                           priv->cmd.comm_toggle, cmd);
 208                 return -EAGAIN;
 209         }
 210
 211         /* Write command */
 212         down(&priv->cmd.poll_sem);
 213         mlx4_comm_cmd_post(dev, cmd, param);
 214
 215         end = msecs_to_jiffies(timeout) + jiffies;
 216         while (comm_pending(dev) && time_before(jiffies, end))
 217                 cond_resched();
 218         ret_from_pending = comm_pending(dev);
 219         if (ret_from_pending) {
 220                 /* check if the slave is trying to boot in the middle of
 221                  * FLR process. The only non-zero result in the RESET command
 222                  * is MLX4_DELAY_RESET_SLAVE*/
 223                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 224                         mlx4_warn(dev, "Got slave FLRed from Communication"
 225                                   " channel (ret:0x%x)\n", ret_from_pending);
 226                         err = MLX4_DELAY_RESET_SLAVE;
 227                 } else {
 228                         mlx4_warn(dev, "Communication channel timed out\n");
 229                         err = -ETIMEDOUT;
 230                 }
 231         }
 232
 233         up(&priv->cmd.poll_sem);
 234         return err;
 235 }
 236
 237 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
 238                               u16 param, unsigned long timeout)
 239 {
 240         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 241         struct mlx4_cmd_context *context;
 242         int err = 0;
 243
 244         down(&cmd->event_sem);
 245
 246         spin_lock(&cmd->context_lock);
 247         BUG_ON(cmd->free_head < 0);
 248         context = &cmd->context[cmd->free_head];
 249         context->token += cmd->token_mask + 1;
 250         cmd->free_head = context->next;
 251         spin_unlock(&cmd->context_lock);
 252
 253         init_completion(&context->done);
 254
 255         mlx4_comm_cmd_post(dev, op, param);
 256
 257         if (!wait_for_completion_timeout(&context->done,
 258                                          msecs_to_jiffies(timeout))) {
 259                 err = -EBUSY;
 260                 goto out;
 261         }
 262
 263         err = context->result;
 264         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 265                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 266                          op, context->fw_status);
 267                 goto out;
 268         }
 269
 270 out:
 271         spin_lock(&cmd->context_lock);
 272         context->next = cmd->free_head;
 273         cmd->free_head = context - cmd->context;
 274         spin_unlock(&cmd->context_lock);
 275
 276         up(&cmd->event_sem);
 277         return err;
 278 }
 279
 280 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 281                   unsigned long timeout)
 282 {
 283         if (mlx4_priv(dev)->cmd.use_events)
 284                 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
 285         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 286 }
 287
 288 static int cmd_pending(struct mlx4_dev *dev)
 289 {
 290         u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 291
 292         return (status & swab32(1 << HCR_GO_BIT)) ||
 293                 (mlx4_priv(dev)->cmd.toggle ==
 294                  !!(status & swab32(1 << HCR_T_BIT)));
 295 }
 296
 297 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 298                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 299                          int event)
 300 {
 301         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 302         u32 __iomem *hcr = cmd->hcr;
 303         int ret = -EAGAIN;
 304         unsigned long end;
 305
 306         mutex_lock(&cmd->hcr_mutex);
 307
 308         end = jiffies;
 309         if (event)
 310                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 311
 312         while (cmd_pending(dev)) {
 313                 if (time_after_eq(jiffies, end)) {
 314                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 315                         goto out;
 316                 }
 317                 cond_resched();
 318         }
 319
 320         /*
 321          * We use writel (instead of something like memcpy_toio)
 322          * because writes of less than 32 bits to the HCR don't work
 323          * (and some architectures such as ia64 implement memcpy_toio
 324          * in terms of writeb).
 325          */
 326         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 327         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 328         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 329         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 330         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 331         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 332
 333         /* __raw_writel may not order writes. */
 334         wmb();
 335
 336         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 337                                                (cmd->toggle << HCR_T_BIT)       |
 338                                                (event ? (1 << HCR_E_BIT) : 0)   |
 339                                                (op_modifier << HCR_OPMOD_SHIFT) |
 340                                                op), hcr + 6);
 341
 342         /*
 343          * Make sure that our HCR writes don't get mixed in with
 344          * writes from another CPU starting a FW command.
 345          */
 346         mmiowb();
 347
 348         cmd->toggle = cmd->toggle ^ 1;
 349
 350         ret = 0;
 351
 352 out:
 353         mutex_unlock(&cmd->hcr_mutex);
 354         return ret;
 355 }
 356
 357 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 358                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 359                           u16 op, unsigned long timeout)
 360 {
 361         struct mlx4_priv *priv = mlx4_priv(dev);
 362         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 363         int ret;
 364
 365         down(&priv->cmd.slave_sem);
 366         vhcr->in_param = cpu_to_be64(in_param);
 367         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 368         vhcr->in_modifier = cpu_to_be32(in_modifier);
 369         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 370         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 371         vhcr->status = 0;
 372         vhcr->flags = !!(priv->cmd.use_events) << 6;
 373         if (mlx4_is_master(dev)) {
 374                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 375                 if (!ret) {
 376                         if (out_is_imm) {
 377                                 if (out_param)
 378                                         *out_param =
 379                                                 be64_to_cpu(vhcr->out_param);
 380                                 else {
 381                                         mlx4_err(dev, "response expected while"
 382                                                  "output mailbox is NULL for "
 383                                                  "command 0x%x\n", op);
 384                                         vhcr->status = CMD_STAT_BAD_PARAM;
 385                                 }
 386                         }
 387                         ret = mlx4_status_to_errno(vhcr->status);
 388                 }
 389         } else {
 390                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
 391                                     MLX4_COMM_TIME + timeout);
 392                 if (!ret) {
 393                         if (out_is_imm) {
 394                                 if (out_param)
 395                                         *out_param =
 396                                                 be64_to_cpu(vhcr->out_param);
 397                                 else {
 398                                         mlx4_err(dev, "response expected while"
 399                                                  "output mailbox is NULL for "
 400                                                  "command 0x%x\n", op);
 401                                         vhcr->status = CMD_STAT_BAD_PARAM;
 402                                 }
 403                         }
 404                         ret = mlx4_status_to_errno(vhcr->status);
 405                 } else
 406                         mlx4_err(dev, "failed execution of VHCR_POST command"
 407                                  "opcode 0x%x\n", op);
 408         }
 409         up(&priv->cmd.slave_sem);
 410         return ret;
 411 }
 412
 413 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 414                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 415                          u16 op, unsigned long timeout)
 416 {
 417         struct mlx4_priv *priv = mlx4_priv(dev);
 418         void __iomem *hcr = priv->cmd.hcr;
 419         int err = 0;
 420         unsigned long end;
 421         u32 stat;
 422
 423         down(&priv->cmd.poll_sem);
 424
 425         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 426                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 427         if (err)
 428                 goto out;
 429
 430         end = msecs_to_jiffies(timeout) + jiffies;
 431         while (cmd_pending(dev) && time_before(jiffies, end))
 432                 cond_resched();
 433
 434         if (cmd_pending(dev)) {
 435                 err = -ETIMEDOUT;
 436                 goto out;
 437         }
 438
 439         if (out_is_imm)
 440                 *out_param =
 441                         (u64) be32_to_cpu((__force __be32)
 442                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 443                         (u64) be32_to_cpu((__force __be32)
 444                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 445         stat = be32_to_cpu((__force __be32)
 446                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 447         err = mlx4_status_to_errno(stat);
 448         if (err)
 449                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 450                          op, stat);
 451
 452 out:
 453         up(&priv->cmd.poll_sem);
 454         return err;
 455 }
 456
 457 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 458 {
 459         struct mlx4_priv *priv = mlx4_priv(dev);
 460         struct mlx4_cmd_context *context =
 461                 &priv->cmd.context[token & priv->cmd.token_mask];
 462
 463         /* previously timed out command completing at long last */
 464         if (token != context->token)
 465                 return;
 466
 467         context->fw_status = status;
 468         context->result    = mlx4_status_to_errno(status);
 469         context->out_param = out_param;
 470
 471         complete(&context->done);
 472 }
 473
 474 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 475                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 476                          u16 op, unsigned long timeout)
 477 {
 478         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 479         struct mlx4_cmd_context *context;
 480         int err = 0;
 481
 482         down(&cmd->event_sem);
 483
 484         spin_lock(&cmd->context_lock);
 485         BUG_ON(cmd->free_head < 0);
 486         context = &cmd->context[cmd->free_head];
 487         context->token += cmd->token_mask + 1;
 488         cmd->free_head = context->next;
 489         spin_unlock(&cmd->context_lock);
 490
 491         init_completion(&context->done);
 492
 493         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 494                       in_modifier, op_modifier, op, context->token, 1);
 495
 496         if (!wait_for_completion_timeout(&context->done,
 497                                          msecs_to_jiffies(timeout))) {
 498                 err = -EBUSY;
 499                 goto out;
 500         }
 501
 502         err = context->result;
 503         if (err) {
 504                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 505                          op, context->fw_status);
 506                 goto out;
 507         }
 508
 509         if (out_is_imm)
 510                 *out_param = context->out_param;
 511
 512 out:
 513         spin_lock(&cmd->context_lock);
 514         context->next = cmd->free_head;
 515         cmd->free_head = context - cmd->context;
 516         spin_unlock(&cmd->context_lock);
 517
 518         up(&cmd->event_sem);
 519         return err;
 520 }
 521
 522 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 523                int out_is_imm, u32 in_modifier, u8 op_modifier,
 524                u16 op, unsigned long timeout, int native)
 525 {
 526         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 527                 if (mlx4_priv(dev)->cmd.use_events)
 528                         return mlx4_cmd_wait(dev, in_param, out_param,
 529                                              out_is_imm, in_modifier,
 530                                              op_modifier, op, timeout);
 531                 else
 532                         return mlx4_cmd_poll(dev, in_param, out_param,
 533                                              out_is_imm, in_modifier,
 534                                              op_modifier, op, timeout);
 535         }
 536         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 537                               in_modifier, op_modifier, op, timeout);
 538 }
 539 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 540
 541
 542 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 543 {
 544         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 545                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 546 }
 547
 548 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 549                            int slave, u64 slave_addr,
 550                            int size, int is_read)
 551 {
 552         u64 in_param;
 553         u64 out_param;
 554
 555         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 556             (slave & ~0x7f) | (size & 0xff)) {
 557                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
 558                               "master_addr:0x%llx slave_id:%d size:%d\n",
 559                               slave_addr, master_addr, slave, size);
 560                 return -EINVAL;
 561         }
 562
 563         if (is_read) {
 564                 in_param = (u64) slave | slave_addr;
 565                 out_param = (u64) dev->caps.function | master_addr;
 566         } else {
 567                 in_param = (u64) dev->caps.function | master_addr;
 568                 out_param = (u64) slave | slave_addr;
 569         }
 570
 571         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 572                             MLX4_CMD_ACCESS_MEM,
 573                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 574 }
 575
 576 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 577                      struct mlx4_vhcr *vhcr,
 578                      struct mlx4_cmd_mailbox *inbox,
 579                      struct mlx4_cmd_mailbox *outbox,
 580                      struct mlx4_cmd_info *cmd)
 581 {
 582         u64 in_param;
 583         u64 out_param;
 584         int err;
 585
 586         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
 587         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
 588         if (cmd->encode_slave_id) {
 589                 in_param &= 0xffffffffffffff00ll;
 590                 in_param |= slave;
 591         }
 592
 593         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
 594                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
 595                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 596
 597         if (cmd->out_is_imm)
 598                 vhcr->out_param = out_param;
 599
 600         return err;
 601 }
 602
 603 static struct mlx4_cmd_info cmd_info[] = {
 604         {
 605                 .opcode = MLX4_CMD_QUERY_FW,
 606                 .has_inbox = false,
 607                 .has_outbox = true,
 608                 .out_is_imm = false,
 609                 .encode_slave_id = false,
 610                 .verify = NULL,
 611                 .wrapper = NULL
 612         },
 613         {
 614                 .opcode = MLX4_CMD_QUERY_HCA,
 615                 .has_inbox = false,
 616                 .has_outbox = true,
 617                 .out_is_imm = false,
 618                 .encode_slave_id = false,
 619                 .verify = NULL,
 620                 .wrapper = NULL
 621         },
 622         {
 623                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
 624                 .has_inbox = false,
 625                 .has_outbox = true,
 626                 .out_is_imm = false,
 627                 .encode_slave_id = false,
 628                 .verify = NULL,
 629                 .wrapper = NULL
 630         },
 631         {
 632                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
 633                 .has_inbox = false,
 634                 .has_outbox = true,
 635                 .out_is_imm = false,
 636                 .encode_slave_id = false,
 637                 .verify = NULL,
 638                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
 639         },
 640         {
 641                 .opcode = MLX4_CMD_QUERY_ADAPTER,
 642                 .has_inbox = false,
 643                 .has_outbox = true,
 644                 .out_is_imm = false,
 645                 .encode_slave_id = false,
 646                 .verify = NULL,
 647                 .wrapper = NULL
 648         },
 649         {
 650                 .opcode = MLX4_CMD_INIT_PORT,
 651                 .has_inbox = false,
 652                 .has_outbox = false,
 653                 .out_is_imm = false,
 654                 .encode_slave_id = false,
 655                 .verify = NULL,
 656                 .wrapper = mlx4_INIT_PORT_wrapper
 657         },
 658         {
 659                 .opcode = MLX4_CMD_CLOSE_PORT,
 660                 .has_inbox = false,
 661                 .has_outbox = false,
 662                 .out_is_imm  = false,
 663                 .encode_slave_id = false,
 664                 .verify = NULL,
 665                 .wrapper = mlx4_CLOSE_PORT_wrapper
 666         },
 667         {
 668                 .opcode = MLX4_CMD_QUERY_PORT,
 669                 .has_inbox = false,
 670                 .has_outbox = true,
 671                 .out_is_imm = false,
 672                 .encode_slave_id = false,
 673                 .verify = NULL,
 674                 .wrapper = mlx4_QUERY_PORT_wrapper
 675         },
 676         {
 677                 .opcode = MLX4_CMD_SET_PORT,
 678                 .has_inbox = true,
 679                 .has_outbox = false,
 680                 .out_is_imm = false,
 681                 .encode_slave_id = false,
 682                 .verify = NULL,
 683                 .wrapper = mlx4_SET_PORT_wrapper
 684         },
 685         {
 686                 .opcode = MLX4_CMD_MAP_EQ,
 687                 .has_inbox = false,
 688                 .has_outbox = false,
 689                 .out_is_imm = false,
 690                 .encode_slave_id = false,
 691                 .verify = NULL,
 692                 .wrapper = mlx4_MAP_EQ_wrapper
 693         },
 694         {
 695                 .opcode = MLX4_CMD_SW2HW_EQ,
 696                 .has_inbox = true,
 697                 .has_outbox = false,
 698                 .out_is_imm = false,
 699                 .encode_slave_id = true,
 700                 .verify = NULL,
 701                 .wrapper = mlx4_SW2HW_EQ_wrapper
 702         },
 703         {
 704                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
 705                 .has_inbox = false,
 706                 .has_outbox = false,
 707                 .out_is_imm = false,
 708                 .encode_slave_id = false,
 709                 .verify = NULL,
 710                 .wrapper = NULL
 711         },
 712         {
 713                 .opcode = MLX4_CMD_NOP,
 714                 .has_inbox = false,
 715                 .has_outbox = false,
 716                 .out_is_imm = false,
 717                 .encode_slave_id = false,
 718                 .verify = NULL,
 719                 .wrapper = NULL
 720         },
 721         {
 722                 .opcode = MLX4_CMD_ALLOC_RES,
 723                 .has_inbox = false,
 724                 .has_outbox = false,
 725                 .out_is_imm = true,
 726                 .encode_slave_id = false,
 727                 .verify = NULL,
 728                 .wrapper = mlx4_ALLOC_RES_wrapper
 729         },
 730         {
 731                 .opcode = MLX4_CMD_FREE_RES,
 732                 .has_inbox = false,
 733                 .has_outbox = false,
 734                 .out_is_imm = false,
 735                 .encode_slave_id = false,
 736                 .verify = NULL,
 737                 .wrapper = mlx4_FREE_RES_wrapper
 738         },
 739         {
 740                 .opcode = MLX4_CMD_SW2HW_MPT,
 741                 .has_inbox = true,
 742                 .has_outbox = false,
 743                 .out_is_imm = false,
 744                 .encode_slave_id = true,
 745                 .verify = NULL,
 746                 .wrapper = mlx4_SW2HW_MPT_wrapper
 747         },
 748         {
 749                 .opcode = MLX4_CMD_QUERY_MPT,
 750                 .has_inbox = false,
 751                 .has_outbox = true,
 752                 .out_is_imm = false,
 753                 .encode_slave_id = false,
 754                 .verify = NULL,
 755                 .wrapper = mlx4_QUERY_MPT_wrapper
 756         },
 757         {
 758                 .opcode = MLX4_CMD_HW2SW_MPT,
 759                 .has_inbox = false,
 760                 .has_outbox = false,
 761                 .out_is_imm = false,
 762                 .encode_slave_id = false,
 763                 .verify = NULL,
 764                 .wrapper = mlx4_HW2SW_MPT_wrapper
 765         },
 766         {
 767                 .opcode = MLX4_CMD_READ_MTT,
 768                 .has_inbox = false,
 769                 .has_outbox = true,
 770                 .out_is_imm = false,
 771                 .encode_slave_id = false,
 772                 .verify = NULL,
 773                 .wrapper = NULL
 774         },
 775         {
 776                 .opcode = MLX4_CMD_WRITE_MTT,
 777                 .has_inbox = true,
 778                 .has_outbox = false,
 779                 .out_is_imm = false,
 780                 .encode_slave_id = false,
 781                 .verify = NULL,
 782                 .wrapper = mlx4_WRITE_MTT_wrapper
 783         },
 784         {
 785                 .opcode = MLX4_CMD_SYNC_TPT,
 786                 .has_inbox = true,
 787                 .has_outbox = false,
 788                 .out_is_imm = false,
 789                 .encode_slave_id = false,
 790                 .verify = NULL,
 791                 .wrapper = NULL
 792         },
 793         {
 794                 .opcode = MLX4_CMD_HW2SW_EQ,
 795                 .has_inbox = false,
 796                 .has_outbox = true,
 797                 .out_is_imm = false,
 798                 .encode_slave_id = true,
 799                 .verify = NULL,
 800                 .wrapper = mlx4_HW2SW_EQ_wrapper
 801         },
 802         {
 803                 .opcode = MLX4_CMD_QUERY_EQ,
 804                 .has_inbox = false,
 805                 .has_outbox = true,
 806                 .out_is_imm = false,
 807                 .encode_slave_id = true,
 808                 .verify = NULL,
 809                 .wrapper = mlx4_QUERY_EQ_wrapper
 810         },
 811         {
 812                 .opcode = MLX4_CMD_SW2HW_CQ,
 813                 .has_inbox = true,
 814                 .has_outbox = false,
 815                 .out_is_imm = false,
 816                 .encode_slave_id = true,
 817                 .verify = NULL,
 818                 .wrapper = mlx4_SW2HW_CQ_wrapper
 819         },
 820         {
 821                 .opcode = MLX4_CMD_HW2SW_CQ,
 822                 .has_inbox = false,
 823                 .has_outbox = false,
 824                 .out_is_imm = false,
 825                 .encode_slave_id = false,
 826                 .verify = NULL,
 827                 .wrapper = mlx4_HW2SW_CQ_wrapper
 828         },
 829         {
 830                 .opcode = MLX4_CMD_QUERY_CQ,
 831                 .has_inbox = false,
 832                 .has_outbox = true,
 833                 .out_is_imm = false,
 834                 .encode_slave_id = false,
 835                 .verify = NULL,
 836                 .wrapper = mlx4_QUERY_CQ_wrapper
 837         },
 838         {
 839                 .opcode = MLX4_CMD_MODIFY_CQ,
 840                 .has_inbox = true,
 841                 .has_outbox = false,
 842                 .out_is_imm = true,
 843                 .encode_slave_id = false,
 844                 .verify = NULL,
 845                 .wrapper = mlx4_MODIFY_CQ_wrapper
 846         },
 847         {
 848                 .opcode = MLX4_CMD_SW2HW_SRQ,
 849                 .has_inbox = true,
 850                 .has_outbox = false,
 851                 .out_is_imm = false,
 852                 .encode_slave_id = true,
 853                 .verify = NULL,
 854                 .wrapper = mlx4_SW2HW_SRQ_wrapper
 855         },
 856         {
 857                 .opcode = MLX4_CMD_HW2SW_SRQ,
 858                 .has_inbox = false,
 859                 .has_outbox = false,
 860                 .out_is_imm = false,
 861                 .encode_slave_id = false,
 862                 .verify = NULL,
 863                 .wrapper = mlx4_HW2SW_SRQ_wrapper
 864         },
 865         {
 866                 .opcode = MLX4_CMD_QUERY_SRQ,
 867                 .has_inbox = false,
 868                 .has_outbox = true,
 869                 .out_is_imm = false,
 870                 .encode_slave_id = false,
 871                 .verify = NULL,
 872                 .wrapper = mlx4_QUERY_SRQ_wrapper
 873         },
 874         {
 875                 .opcode = MLX4_CMD_ARM_SRQ,
 876                 .has_inbox = false,
 877                 .has_outbox = false,
 878                 .out_is_imm = false,
 879                 .encode_slave_id = false,
 880                 .verify = NULL,
 881                 .wrapper = mlx4_ARM_SRQ_wrapper
 882         },
 883         {
 884                 .opcode = MLX4_CMD_RST2INIT_QP,
 885                 .has_inbox = true,
 886                 .has_outbox = false,
 887                 .out_is_imm = false,
 888                 .encode_slave_id = true,
 889                 .verify = NULL,
 890                 .wrapper = mlx4_RST2INIT_QP_wrapper
 891         },
 892         {
 893                 .opcode = MLX4_CMD_INIT2INIT_QP,
 894                 .has_inbox = true,
 895                 .has_outbox = false,
 896                 .out_is_imm = false,
 897                 .encode_slave_id = false,
 898                 .verify = NULL,
 899                 .wrapper = mlx4_GEN_QP_wrapper
 900         },
 901         {
 902                 .opcode = MLX4_CMD_INIT2RTR_QP,
 903                 .has_inbox = true,
 904                 .has_outbox = false,
 905                 .out_is_imm = false,
 906                 .encode_slave_id = false,
 907                 .verify = NULL,
 908                 .wrapper = mlx4_INIT2RTR_QP_wrapper
 909         },
 910         {
 911                 .opcode = MLX4_CMD_RTR2RTS_QP,
 912                 .has_inbox = true,
 913                 .has_outbox = false,
 914                 .out_is_imm = false,
 915                 .encode_slave_id = false,
 916                 .verify = NULL,
 917                 .wrapper = mlx4_GEN_QP_wrapper
 918         },
 919         {
 920                 .opcode = MLX4_CMD_RTS2RTS_QP,
 921                 .has_inbox = true,
 922                 .has_outbox = false,
 923                 .out_is_imm = false,
 924                 .encode_slave_id = false,
 925                 .verify = NULL,
 926                 .wrapper = mlx4_GEN_QP_wrapper
 927         },
 928         {
 929                 .opcode = MLX4_CMD_SQERR2RTS_QP,
 930                 .has_inbox = true,
 931                 .has_outbox = false,
 932                 .out_is_imm = false,
 933                 .encode_slave_id = false,
 934                 .verify = NULL,
 935                 .wrapper = mlx4_GEN_QP_wrapper
 936         },
 937         {
 938                 .opcode = MLX4_CMD_2ERR_QP,
 939                 .has_inbox = false,
 940                 .has_outbox = false,
 941                 .out_is_imm = false,
 942                 .encode_slave_id = false,
 943                 .verify = NULL,
 944                 .wrapper = mlx4_GEN_QP_wrapper
 945         },
 946         {
 947                 .opcode = MLX4_CMD_RTS2SQD_QP,
 948                 .has_inbox = false,
 949                 .has_outbox = false,
 950                 .out_is_imm = false,
 951                 .encode_slave_id = false,
 952                 .verify = NULL,
 953                 .wrapper = mlx4_GEN_QP_wrapper
 954         },
 955         {
 956                 .opcode = MLX4_CMD_SQD2SQD_QP,
 957                 .has_inbox = true,
 958                 .has_outbox = false,
 959                 .out_is_imm = false,
 960                 .encode_slave_id = false,
 961                 .verify = NULL,
 962                 .wrapper = mlx4_GEN_QP_wrapper
 963         },
 964         {
 965                 .opcode = MLX4_CMD_SQD2RTS_QP,
 966                 .has_inbox = true,
 967                 .has_outbox = false,
 968                 .out_is_imm = false,
 969                 .encode_slave_id = false,
 970                 .verify = NULL,
 971                 .wrapper = mlx4_GEN_QP_wrapper
 972         },
 973         {
 974                 .opcode = MLX4_CMD_2RST_QP,
 975                 .has_inbox = false,
 976                 .has_outbox = false,
 977                 .out_is_imm = false,
 978                 .encode_slave_id = false,
 979                 .verify = NULL,
 980                 .wrapper = mlx4_2RST_QP_wrapper
 981         },
 982         {
 983                 .opcode = MLX4_CMD_QUERY_QP,
 984                 .has_inbox = false,
 985                 .has_outbox = true,
 986                 .out_is_imm = false,
 987                 .encode_slave_id = false,
 988                 .verify = NULL,
 989                 .wrapper = mlx4_GEN_QP_wrapper
 990         },
 991         {
 992                 .opcode = MLX4_CMD_SUSPEND_QP,
 993                 .has_inbox = false,
 994                 .has_outbox = false,
 995                 .out_is_imm = false,
 996                 .encode_slave_id = false,
 997                 .verify = NULL,
 998                 .wrapper = mlx4_GEN_QP_wrapper
 999         },
1000         {
1001                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1002                 .has_inbox = false,
1003                 .has_outbox = false,
1004                 .out_is_imm = false,
1005                 .encode_slave_id = false,
1006                 .verify = NULL,
1007                 .wrapper = mlx4_GEN_QP_wrapper
1008         },
1009         {
1010                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1011                 .has_inbox = false,
1012                 .has_outbox = true,
1013                 .out_is_imm = false,
1014                 .encode_slave_id = false,
1015                 .verify = NULL,
1016                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1017         },
1018         /* Native multicast commands are not available for guests */
1019         {
1020                 .opcode = MLX4_CMD_QP_ATTACH,
1021                 .has_inbox = true,
1022                 .has_outbox = false,
1023                 .out_is_imm = false,
1024                 .encode_slave_id = false,
1025                 .verify = NULL,
1026                 .wrapper = mlx4_QP_ATTACH_wrapper
1027         },
1028         {
1029                 .opcode = MLX4_CMD_PROMISC,
1030                 .has_inbox = false,
1031                 .has_outbox = false,
1032                 .out_is_imm = false,
1033                 .encode_slave_id = false,
1034                 .verify = NULL,
1035                 .wrapper = mlx4_PROMISC_wrapper
1036         },
1037         /* Ethernet specific commands */
1038         {
1039                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1040                 .has_inbox = true,
1041                 .has_outbox = false,
1042                 .out_is_imm = false,
1043                 .encode_slave_id = false,
1044                 .verify = NULL,
1045                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1046         },
1047         {
1048                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1049                 .has_inbox = false,
1050                 .has_outbox = false,
1051                 .out_is_imm = false,
1052                 .encode_slave_id = false,
1053                 .verify = NULL,
1054                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1055         },
1056         {
1057                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1058                 .has_inbox = false,
1059                 .has_outbox = true,
1060                 .out_is_imm = false,
1061                 .encode_slave_id = false,
1062                 .verify = NULL,
1063                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1064         },
1065         {
1066                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1067                 .has_inbox = false,
1068                 .has_outbox = false,
1069                 .out_is_imm = false,
1070                 .encode_slave_id = false,
1071                 .verify = NULL,
1072                 .wrapper = NULL
1073         },
1074 };
1075
1076 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1077                                     struct mlx4_vhcr_cmd *in_vhcr)
1078 {
1079         struct mlx4_priv *priv = mlx4_priv(dev);
1080         struct mlx4_cmd_info *cmd = NULL;
1081         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1082         struct mlx4_vhcr *vhcr;
1083         struct mlx4_cmd_mailbox *inbox = NULL;
1084         struct mlx4_cmd_mailbox *outbox = NULL;
1085         u64 in_param;
1086         u64 out_param;
1087         int ret = 0;
1088         int i;
1089         int err = 0;
1090
1091         /* Create sw representation of Virtual HCR */
1092         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1093         if (!vhcr)
1094                 return -ENOMEM;
1095
1096         /* DMA in the vHCR */
1097         if (!in_vhcr) {
1098                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1099                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1100                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1101                                             MLX4_ACCESS_MEM_ALIGN), 1);
1102                 if (ret) {
1103                         mlx4_err(dev, "%s:Failed reading vhcr"
1104                                  "ret: 0x%x\n", __func__, ret);
1105                         kfree(vhcr);
1106                         return ret;
1107                 }
1108         }
1109
1110         /* Fill SW VHCR fields */
1111         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1112         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1113         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1114         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1115         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1116         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1117         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1118
1119         /* Lookup command */
1120         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1121                 if (vhcr->op == cmd_info[i].opcode) {
1122                         cmd = &cmd_info[i];
1123                         break;
1124                 }
1125         }
1126         if (!cmd) {
1127                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1128                          vhcr->op, slave);
1129                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1130                 goto out_status;
1131         }
1132
1133         /* Read inbox */
1134         if (cmd->has_inbox) {
1135                 vhcr->in_param &= INBOX_MASK;
1136                 inbox = mlx4_alloc_cmd_mailbox(dev);
1137                 if (IS_ERR(inbox)) {
1138                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1139                         inbox = NULL;
1140                         goto out_status;
1141                 }
1142
1143                 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1144                                     vhcr->in_param,
1145                                     MLX4_MAILBOX_SIZE, 1)) {
1146                         mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1147                                  __func__, cmd->opcode);
1148                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1149                         goto out_status;
1150                 }
1151         }
1152
1153         /* Apply permission and bound checks if applicable */
1154         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1155                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1156                           "checks for resource_id:%d\n", vhcr->op, slave,
1157                           vhcr->in_modifier);
1158                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1159                 goto out_status;
1160         }
1161
1162         /* Allocate outbox */
1163         if (cmd->has_outbox) {
1164                 outbox = mlx4_alloc_cmd_mailbox(dev);
1165                 if (IS_ERR(outbox)) {
1166                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1167                         outbox = NULL;
1168                         goto out_status;
1169                 }
1170         }
1171
1172         /* Execute the command! */
1173         if (cmd->wrapper) {
1174                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1175                                    cmd);
1176                 if (cmd->out_is_imm)
1177                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1178         } else {
1179                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1180                         vhcr->in_param;
1181                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1182                         vhcr->out_param;
1183                 err = __mlx4_cmd(dev, in_param, &out_param,
1184                                  cmd->out_is_imm, vhcr->in_modifier,
1185                                  vhcr->op_modifier, vhcr->op,
1186                                  MLX4_CMD_TIME_CLASS_A,
1187                                  MLX4_CMD_NATIVE);
1188
1189                 if (cmd->out_is_imm) {
1190                         vhcr->out_param = out_param;
1191                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1192                 }
1193         }
1194
1195         if (err) {
1196                 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1197                           " error:%d, status %d\n",
1198                           vhcr->op, slave, vhcr->errno, err);
1199                 vhcr_cmd->status = mlx4_errno_to_status(err);
1200                 goto out_status;
1201         }
1202
1203
1204         /* Write outbox if command completed successfully */
1205         if (cmd->has_outbox && !vhcr_cmd->status) {
1206                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1207                                       vhcr->out_param,
1208                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1209                 if (ret) {
1210                         /* If we failed to write back the outbox after the
1211                          *command was successfully executed, we must fail this
1212                          * slave, as it is now in undefined state */
1213                         mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1214                         goto out;
1215                 }
1216         }
1217
1218 out_status:
1219         /* DMA back vhcr result */
1220         if (!in_vhcr) {
1221                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1222                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1223                                       ALIGN(sizeof(struct mlx4_vhcr),
1224                                             MLX4_ACCESS_MEM_ALIGN),
1225                                       MLX4_CMD_WRAPPED);
1226                 if (ret)
1227                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1228                                  __func__);
1229                 else if (vhcr->e_bit &&
1230                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1231                                 mlx4_warn(dev, "Failed to generate command completion "
1232                                           "eqe for slave %d\n", slave);
1233         }
1234
1235 out:
1236         kfree(vhcr);
1237         mlx4_free_cmd_mailbox(dev, inbox);
1238         mlx4_free_cmd_mailbox(dev, outbox);
1239         return ret;
1240 }
1241
1242 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1243                                u16 param, u8 toggle)
1244 {
1245         struct mlx4_priv *priv = mlx4_priv(dev);
1246         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1247         u32 reply;
1248         u32 slave_status = 0;
1249         u8 is_going_down = 0;
1250         int i;
1251
1252         slave_state[slave].comm_toggle ^= 1;
1253         reply = (u32) slave_state[slave].comm_toggle << 31;
1254         if (toggle != slave_state[slave].comm_toggle) {
1255                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1256                           "STATE COMPROMISIED ***\n", toggle, slave);
1257                 goto reset_slave;
1258         }
1259         if (cmd == MLX4_COMM_CMD_RESET) {
1260                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1261                 slave_state[slave].active = false;
1262                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1263                                 slave_state[slave].event_eq[i].eqn = -1;
1264                                 slave_state[slave].event_eq[i].token = 0;
1265                 }
1266                 /*check if we are in the middle of FLR process,
1267                 if so return "retry" status to the slave*/
1268                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1269                         slave_status = MLX4_DELAY_RESET_SLAVE;
1270                         goto inform_slave_state;
1271                 }
1272
1273                 /* write the version in the event field */
1274                 reply |= mlx4_comm_get_version();
1275
1276                 goto reset_slave;
1277         }
1278         /*command from slave in the middle of FLR*/
1279         if (cmd != MLX4_COMM_CMD_RESET &&
1280             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1281                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1282                           "in the middle of FLR\n", slave, cmd);
1283                 return;
1284         }
1285
1286         switch (cmd) {
1287         case MLX4_COMM_CMD_VHCR0:
1288                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1289                         goto reset_slave;
1290                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1291                 priv->mfunc.master.slave_state[slave].cookie = 0;
1292                 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1293                 break;
1294         case MLX4_COMM_CMD_VHCR1:
1295                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1296                         goto reset_slave;
1297                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1298                 break;
1299         case MLX4_COMM_CMD_VHCR2:
1300                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1301                         goto reset_slave;
1302                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1303                 break;
1304         case MLX4_COMM_CMD_VHCR_EN:
1305                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1306                         goto reset_slave;
1307                 slave_state[slave].vhcr_dma |= param;
1308                 slave_state[slave].active = true;
1309                 break;
1310         case MLX4_COMM_CMD_VHCR_POST:
1311                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1312                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1313                         goto reset_slave;
1314                 down(&priv->cmd.slave_sem);
1315                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1316                         mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1317                                  " reseting slave.\n", slave);
1318                         up(&priv->cmd.slave_sem);
1319                         goto reset_slave;
1320                 }
1321                 up(&priv->cmd.slave_sem);
1322                 break;
1323         default:
1324                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1325                 goto reset_slave;
1326         }
1327         spin_lock(&priv->mfunc.master.slave_state_lock);
1328         if (!slave_state[slave].is_slave_going_down)
1329                 slave_state[slave].last_cmd = cmd;
1330         else
1331                 is_going_down = 1;
1332         spin_unlock(&priv->mfunc.master.slave_state_lock);
1333         if (is_going_down) {
1334                 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1335                           " executing from slave:%d\n",
1336                           cmd, slave);
1337                 return;
1338         }
1339         __raw_writel((__force u32) cpu_to_be32(reply),
1340                      &priv->mfunc.comm[slave].slave_read);
1341         mmiowb();
1342
1343         return;
1344
1345 reset_slave:
1346         /* cleanup any slave resources */
1347         mlx4_delete_all_resources_for_slave(dev, slave);
1348         spin_lock(&priv->mfunc.master.slave_state_lock);
1349         if (!slave_state[slave].is_slave_going_down)
1350                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1351         spin_unlock(&priv->mfunc.master.slave_state_lock);
1352         /*with slave in the middle of flr, no need to clean resources again.*/
1353 inform_slave_state:
1354         memset(&slave_state[slave].event_eq, 0,
1355                sizeof(struct mlx4_slave_event_eq_info));
1356         __raw_writel((__force u32) cpu_to_be32(reply),
1357                      &priv->mfunc.comm[slave].slave_read);
1358         wmb();
1359 }
1360
1361 /* master command processing */
1362 void mlx4_master_comm_channel(struct work_struct *work)
1363 {
1364         struct mlx4_mfunc_master_ctx *master =
1365                 container_of(work,
1366                              struct mlx4_mfunc_master_ctx,
1367                              comm_work);
1368         struct mlx4_mfunc *mfunc =
1369                 container_of(master, struct mlx4_mfunc, master);
1370         struct mlx4_priv *priv =
1371                 container_of(mfunc, struct mlx4_priv, mfunc);
1372         struct mlx4_dev *dev = &priv->dev;
1373         __be32 *bit_vec;
1374         u32 comm_cmd;
1375         u32 vec;
1376         int i, j, slave;
1377         int toggle;
1378         int served = 0;
1379         int reported = 0;
1380         u32 slt;
1381
1382         bit_vec = master->comm_arm_bit_vector;
1383         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1384                 vec = be32_to_cpu(bit_vec[i]);
1385                 for (j = 0; j < 32; j++) {
1386                         if (!(vec & (1 << j)))
1387                                 continue;
1388                         ++reported;
1389                         slave = (i * 32) + j;
1390                         comm_cmd = swab32(readl(
1391                                           &mfunc->comm[slave].slave_write));
1392                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
1393                                      >> 31;
1394                         toggle = comm_cmd >> 31;
1395                         if (toggle != slt) {
1396                                 if (master->slave_state[slave].comm_toggle
1397                                     != slt) {
1398                                         printk(KERN_INFO "slave %d out of sync."
1399                                                " read toggle %d, state toggle %d. "
1400                                                "Resynching.\n", slave, slt,
1401                                                master->slave_state[slave].comm_toggle);
1402                                         master->slave_state[slave].comm_toggle =
1403                                                 slt;
1404                                 }
1405                                 mlx4_master_do_cmd(dev, slave,
1406                                                    comm_cmd >> 16 & 0xff,
1407                                                    comm_cmd & 0xffff, toggle);
1408                                 ++served;
1409                         }
1410                 }
1411         }
1412
1413         if (reported && reported != served)
1414                 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1415                           " but %d were served\n",
1416                           reported, served);
1417
1418         if (mlx4_ARM_COMM_CHANNEL(dev))
1419                 mlx4_warn(dev, "Failed to arm comm channel events\n");
1420 }
1421
1422 static int sync_toggles(struct mlx4_dev *dev)
1423 {
1424         struct mlx4_priv *priv = mlx4_priv(dev);
1425         int wr_toggle;
1426         int rd_toggle;
1427         unsigned long end;
1428
1429         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1430         end = jiffies + msecs_to_jiffies(5000);
1431
1432         while (time_before(jiffies, end)) {
1433                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1434                 if (rd_toggle == wr_toggle) {
1435                         priv->cmd.comm_toggle = rd_toggle;
1436                         return 0;
1437                 }
1438
1439                 cond_resched();
1440         }
1441
1442         /*
1443          * we could reach here if for example the previous VM using this
1444          * function misbehaved and left the channel with unsynced state. We
1445          * should fix this here and give this VM a chance to use a properly
1446          * synced channel
1447          */
1448         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1449         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1450         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1451         priv->cmd.comm_toggle = 0;
1452
1453         return 0;
1454 }
1455
1456 int mlx4_multi_func_init(struct mlx4_dev *dev)
1457 {
1458         struct mlx4_priv *priv = mlx4_priv(dev);
1459         struct mlx4_slave_state *s_state;
1460         int i, j, err, port;
1461
1462         priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1463                                             &priv->mfunc.vhcr_dma,
1464                                             GFP_KERNEL);
1465         if (!priv->mfunc.vhcr) {
1466                 mlx4_err(dev, "Couldn't allocate vhcr.\n");
1467                 return -ENOMEM;
1468         }
1469
1470         if (mlx4_is_master(dev))
1471                 priv->mfunc.comm =
1472                 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1473                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1474         else
1475                 priv->mfunc.comm =
1476                 ioremap(pci_resource_start(dev->pdev, 2) +
1477                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1478         if (!priv->mfunc.comm) {
1479                 mlx4_err(dev, "Couldn't map communication vector.\n");
1480                 goto err_vhcr;
1481         }
1482
1483         if (mlx4_is_master(dev)) {
1484                 priv->mfunc.master.slave_state =
1485                         kzalloc(dev->num_slaves *
1486                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1487                 if (!priv->mfunc.master.slave_state)
1488                         goto err_comm;
1489
1490                 for (i = 0; i < dev->num_slaves; ++i) {
1491                         s_state = &priv->mfunc.master.slave_state[i];
1492                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
1493                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1494                                 s_state->event_eq[j].eqn = -1;
1495                         __raw_writel((__force u32) 0,
1496                                      &priv->mfunc.comm[i].slave_write);
1497                         __raw_writel((__force u32) 0,
1498                                      &priv->mfunc.comm[i].slave_read);
1499                         mmiowb();
1500                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1501                                 s_state->vlan_filter[port] =
1502                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
1503                                                 GFP_KERNEL);
1504                                 if (!s_state->vlan_filter[port]) {
1505                                         if (--port)
1506                                                 kfree(s_state->vlan_filter[port]);
1507                                         goto err_slaves;
1508                                 }
1509                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1510                         }
1511                         spin_lock_init(&s_state->lock);
1512                 }
1513
1514                 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
1515                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1516                 INIT_WORK(&priv->mfunc.master.comm_work,
1517                           mlx4_master_comm_channel);
1518                 INIT_WORK(&priv->mfunc.master.slave_event_work,
1519                           mlx4_gen_slave_eqe);
1520                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1521                           mlx4_master_handle_slave_flr);
1522                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1523                 priv->mfunc.master.comm_wq =
1524                         create_singlethread_workqueue("mlx4_comm");
1525                 if (!priv->mfunc.master.comm_wq)
1526                         goto err_slaves;
1527
1528                 if (mlx4_init_resource_tracker(dev))
1529                         goto err_thread;
1530
1531                 sema_init(&priv->cmd.slave_sem, 1);
1532                 err = mlx4_ARM_COMM_CHANNEL(dev);
1533                 if (err) {
1534                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1535                                  err);
1536                         goto err_resource;
1537                 }
1538
1539         } else {
1540                 err = sync_toggles(dev);
1541                 if (err) {
1542                         mlx4_err(dev, "Couldn't sync toggles\n");
1543                         goto err_comm;
1544                 }
1545
1546                 sema_init(&priv->cmd.slave_sem, 1);
1547         }
1548         return 0;
1549
1550 err_resource:
1551         mlx4_free_resource_tracker(dev);
1552 err_thread:
1553         flush_workqueue(priv->mfunc.master.comm_wq);
1554         destroy_workqueue(priv->mfunc.master.comm_wq);
1555 err_slaves:
1556         while (--i) {
1557                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1558                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1559         }
1560         kfree(priv->mfunc.master.slave_state);
1561 err_comm:
1562         iounmap(priv->mfunc.comm);
1563 err_vhcr:
1564         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1565                                              priv->mfunc.vhcr,
1566                                              priv->mfunc.vhcr_dma);
1567         priv->mfunc.vhcr = NULL;
1568         return -ENOMEM;
1569 }
1570
1571 int mlx4_cmd_init(struct mlx4_dev *dev)
1572 {
1573         struct mlx4_priv *priv = mlx4_priv(dev);
1574
1575         mutex_init(&priv->cmd.hcr_mutex);
1576         sema_init(&priv->cmd.poll_sem, 1);
1577         priv->cmd.use_events = 0;
1578         priv->cmd.toggle     = 1;
1579
1580         priv->cmd.hcr = NULL;
1581         priv->mfunc.vhcr = NULL;
1582
1583         if (!mlx4_is_slave(dev)) {
1584                 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1585                                         MLX4_HCR_BASE, MLX4_HCR_SIZE);
1586                 if (!priv->cmd.hcr) {
1587                         mlx4_err(dev, "Couldn't map command register.\n");
1588                         return -ENOMEM;
1589                 }
1590         }
1591
1592         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1593                                          MLX4_MAILBOX_SIZE,
1594                                          MLX4_MAILBOX_SIZE, 0);
1595         if (!priv->cmd.pool)
1596                 goto err_hcr;
1597
1598         return 0;
1599
1600 err_hcr:
1601         if (!mlx4_is_slave(dev))
1602                 iounmap(priv->cmd.hcr);
1603         return -ENOMEM;
1604 }
1605
1606 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1607 {
1608         struct mlx4_priv *priv = mlx4_priv(dev);
1609         int i, port;
1610
1611         if (mlx4_is_master(dev)) {
1612                 flush_workqueue(priv->mfunc.master.comm_wq);
1613                 destroy_workqueue(priv->mfunc.master.comm_wq);
1614                 for (i = 0; i < dev->num_slaves; i++) {
1615                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
1616                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1617                 }
1618                 kfree(priv->mfunc.master.slave_state);
1619                 iounmap(priv->mfunc.comm);
1620                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1621                                                      priv->mfunc.vhcr,
1622                                                      priv->mfunc.vhcr_dma);
1623                 priv->mfunc.vhcr = NULL;
1624         }
1625 }
1626
1627 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1628 {
1629         struct mlx4_priv *priv = mlx4_priv(dev);
1630
1631         pci_pool_destroy(priv->cmd.pool);
1632
1633         if (!mlx4_is_slave(dev))
1634                 iounmap(priv->cmd.hcr);
1635 }
1636
1637 /*
1638  * Switch to using events to issue FW commands (can only be called
1639  * after event queue for command events has been initialized).
1640  */
1641 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1642 {
1643         struct mlx4_priv *priv = mlx4_priv(dev);
1644         int i;
1645         int err = 0;
1646
1647         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1648                                    sizeof (struct mlx4_cmd_context),
1649                                    GFP_KERNEL);
1650         if (!priv->cmd.context)
1651                 return -ENOMEM;
1652
1653         for (i = 0; i < priv->cmd.max_cmds; ++i) {
1654                 priv->cmd.context[i].token = i;
1655                 priv->cmd.context[i].next  = i + 1;
1656         }
1657
1658         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
1659         priv->cmd.free_head = 0;
1660
1661         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
1662         spin_lock_init(&priv->cmd.context_lock);
1663
1664         for (priv->cmd.token_mask = 1;
1665              priv->cmd.token_mask < priv->cmd.max_cmds;
1666              priv->cmd.token_mask <<= 1)
1667                 ; /* nothing */
1668         --priv->cmd.token_mask;
1669
1670         down(&priv->cmd.poll_sem);
1671         priv->cmd.use_events = 1;
1672
1673         return err;
1674 }
1675
1676 /*
1677  * Switch back to polling (used when shutting down the device)
1678  */
1679 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
1680 {
1681         struct mlx4_priv *priv = mlx4_priv(dev);
1682         int i;
1683
1684         priv->cmd.use_events = 0;
1685
1686         for (i = 0; i < priv->cmd.max_cmds; ++i)
1687                 down(&priv->cmd.event_sem);
1688
1689         kfree(priv->cmd.context);
1690
1691         up(&priv->cmd.poll_sem);
1692 }
1693
1694 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
1695 {
1696         struct mlx4_cmd_mailbox *mailbox;
1697
1698         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
1699         if (!mailbox)
1700                 return ERR_PTR(-ENOMEM);
1701
1702         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
1703                                       &mailbox->dma);
1704         if (!mailbox->buf) {
1705                 kfree(mailbox);
1706                 return ERR_PTR(-ENOMEM);
1707         }
1708
1709         return mailbox;
1710 }
1711 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
1712
1713 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
1714                            struct mlx4_cmd_mailbox *mailbox)
1715 {
1716         if (!mailbox)
1717                 return;
1718
1719         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
1720         kfree(mailbox);
1721 }
1722 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
1723
1724 u32 mlx4_comm_get_version(void)
1725 {
1726          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
1727 }