drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45
  46 #include <asm/io.h>
  47
  48 #include "mlx4.h"
  49 #include "fw.h"
  50
  51 #define CMD_POLL_TOKEN 0xffff
  52 #define INBOX_MASK      0xffffffffffffff00ULL
  53
  54 #define CMD_CHAN_VER 1
  55 #define CMD_CHAN_IF_REV 1
  56
  57 enum {
  58         /* command completed successfully: */
  59         CMD_STAT_OK             = 0x00,
  60         /* Internal error (such as a bus error) occurred while processing command: */
  61         CMD_STAT_INTERNAL_ERR   = 0x01,
  62         /* Operation/command not supported or opcode modifier not supported: */
  63         CMD_STAT_BAD_OP         = 0x02,
  64         /* Parameter not supported or parameter out of range: */
  65         CMD_STAT_BAD_PARAM      = 0x03,
  66         /* System not enabled or bad system state: */
  67         CMD_STAT_BAD_SYS_STATE  = 0x04,
  68         /* Attempt to access reserved or unallocaterd resource: */
  69         CMD_STAT_BAD_RESOURCE   = 0x05,
  70         /* Requested resource is currently executing a command, or is otherwise busy: */
  71         CMD_STAT_RESOURCE_BUSY  = 0x06,
  72         /* Required capability exceeds device limits: */
  73         CMD_STAT_EXCEED_LIM     = 0x08,
  74         /* Resource is not in the appropriate state or ownership: */
  75         CMD_STAT_BAD_RES_STATE  = 0x09,
  76         /* Index out of range: */
  77         CMD_STAT_BAD_INDEX      = 0x0a,
  78         /* FW image corrupted: */
  79         CMD_STAT_BAD_NVMEM      = 0x0b,
  80         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  81         CMD_STAT_ICM_ERROR      = 0x0c,
  82         /* Attempt to modify a QP/EE which is not in the presumed state: */
  83         CMD_STAT_BAD_QP_STATE   = 0x10,
  84         /* Bad segment parameters (Address/Size): */
  85         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  86         /* Memory Region has Memory Windows bound to: */
  87         CMD_STAT_REG_BOUND      = 0x21,
  88         /* HCA local attached memory not present: */
  89         CMD_STAT_LAM_NOT_PRE    = 0x22,
  90         /* Bad management packet (silently discarded): */
  91         CMD_STAT_BAD_PKT        = 0x30,
  92         /* More outstanding CQEs in CQ than new CQ size: */
  93         CMD_STAT_BAD_SIZE       = 0x40,
  94         /* Multi Function device support required: */
  95         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  96 };
  97
  98 enum {
  99         HCR_IN_PARAM_OFFSET     = 0x00,
 100         HCR_IN_MODIFIER_OFFSET  = 0x08,
 101         HCR_OUT_PARAM_OFFSET    = 0x0c,
 102         HCR_TOKEN_OFFSET        = 0x14,
 103         HCR_STATUS_OFFSET       = 0x18,
 104
 105         HCR_OPMOD_SHIFT         = 12,
 106         HCR_T_BIT               = 21,
 107         HCR_E_BIT               = 22,
 108         HCR_GO_BIT              = 23
 109 };
 110
 111 enum {
 112         GO_BIT_TIMEOUT_MSECS    = 10000
 113 };
 114
 115 enum mlx4_vlan_transition {
 116         MLX4_VLAN_TRANSITION_VST_VST = 0,
 117         MLX4_VLAN_TRANSITION_VST_VGT = 1,
 118         MLX4_VLAN_TRANSITION_VGT_VST = 2,
 119         MLX4_VLAN_TRANSITION_VGT_VGT = 3,
 120 };
 121
 122
 123 struct mlx4_cmd_context {
 124         struct completion       done;
 125         int                     result;
 126         int                     next;
 127         u64                     out_param;
 128         u16                     token;
 129         u8                      fw_status;
 130 };
 131
 132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 133                                     struct mlx4_vhcr_cmd *in_vhcr);
 134
 135 static int mlx4_status_to_errno(u8 status)
 136 {
 137         static const int trans_table[] = {
 138                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 139                 [CMD_STAT_BAD_OP]         = -EPERM,
 140                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 141                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 142                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 143                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 144                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 145                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 146                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 147                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 148                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 149                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 150                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 151                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 152                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 153                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 154                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 155                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 156         };
 157
 158         if (status >= ARRAY_SIZE(trans_table) ||
 159             (status != CMD_STAT_OK && trans_table[status] == 0))
 160                 return -EIO;
 161
 162         return trans_table[status];
 163 }
 164
 165 static u8 mlx4_errno_to_status(int errno)
 166 {
 167         switch (errno) {
 168         case -EPERM:
 169                 return CMD_STAT_BAD_OP;
 170         case -EINVAL:
 171                 return CMD_STAT_BAD_PARAM;
 172         case -ENXIO:
 173                 return CMD_STAT_BAD_SYS_STATE;
 174         case -EBUSY:
 175                 return CMD_STAT_RESOURCE_BUSY;
 176         case -ENOMEM:
 177                 return CMD_STAT_EXCEED_LIM;
 178         case -ENFILE:
 179                 return CMD_STAT_ICM_ERROR;
 180         default:
 181                 return CMD_STAT_INTERNAL_ERR;
 182         }
 183 }
 184
 185 static int comm_pending(struct mlx4_dev *dev)
 186 {
 187         struct mlx4_priv *priv = mlx4_priv(dev);
 188         u32 status = readl(&priv->mfunc.comm->slave_read);
 189
 190         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 191 }
 192
 193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 194 {
 195         struct mlx4_priv *priv = mlx4_priv(dev);
 196         u32 val;
 197
 198         priv->cmd.comm_toggle ^= 1;
 199         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 200         __raw_writel((__force u32) cpu_to_be32(val),
 201                      &priv->mfunc.comm->slave_write);
 202         mmiowb();
 203 }
 204
 205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 206                        unsigned long timeout)
 207 {
 208         struct mlx4_priv *priv = mlx4_priv(dev);
 209         unsigned long end;
 210         int err = 0;
 211         int ret_from_pending = 0;
 212
 213         /* First, verify that the master reports correct status */
 214         if (comm_pending(dev)) {
 215                 mlx4_warn(dev, "Communication channel is not idle."
 216                           "my toggle is %d (cmd:0x%x)\n",
 217                           priv->cmd.comm_toggle, cmd);
 218                 return -EAGAIN;
 219         }
 220
 221         /* Write command */
 222         down(&priv->cmd.poll_sem);
 223         mlx4_comm_cmd_post(dev, cmd, param);
 224
 225         end = msecs_to_jiffies(timeout) + jiffies;
 226         while (comm_pending(dev) && time_before(jiffies, end))
 227                 cond_resched();
 228         ret_from_pending = comm_pending(dev);
 229         if (ret_from_pending) {
 230                 /* check if the slave is trying to boot in the middle of
 231                  * FLR process. The only non-zero result in the RESET command
 232                  * is MLX4_DELAY_RESET_SLAVE*/
 233                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 234                         err = MLX4_DELAY_RESET_SLAVE;
 235                 } else {
 236                         mlx4_warn(dev, "Communication channel timed out\n");
 237                         err = -ETIMEDOUT;
 238                 }
 239         }
 240
 241         up(&priv->cmd.poll_sem);
 242         return err;
 243 }
 244
 245 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
 246                               u16 param, unsigned long timeout)
 247 {
 248         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 249         struct mlx4_cmd_context *context;
 250         unsigned long end;
 251         int err = 0;
 252
 253         down(&cmd->event_sem);
 254
 255         spin_lock(&cmd->context_lock);
 256         BUG_ON(cmd->free_head < 0);
 257         context = &cmd->context[cmd->free_head];
 258         context->token += cmd->token_mask + 1;
 259         cmd->free_head = context->next;
 260         spin_unlock(&cmd->context_lock);
 261
 262         init_completion(&context->done);
 263
 264         mlx4_comm_cmd_post(dev, op, param);
 265
 266         if (!wait_for_completion_timeout(&context->done,
 267                                          msecs_to_jiffies(timeout))) {
 268                 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
 269                           op);
 270                 err = -EBUSY;
 271                 goto out;
 272         }
 273
 274         err = context->result;
 275         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 276                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 277                          op, context->fw_status);
 278                 goto out;
 279         }
 280
 281 out:
 282         /* wait for comm channel ready
 283          * this is necessary for prevention the race
 284          * when switching between event to polling mode
 285          */
 286         end = msecs_to_jiffies(timeout) + jiffies;
 287         while (comm_pending(dev) && time_before(jiffies, end))
 288                 cond_resched();
 289
 290         spin_lock(&cmd->context_lock);
 291         context->next = cmd->free_head;
 292         cmd->free_head = context - cmd->context;
 293         spin_unlock(&cmd->context_lock);
 294
 295         up(&cmd->event_sem);
 296         return err;
 297 }
 298
 299 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 300                   unsigned long timeout)
 301 {
 302         if (mlx4_priv(dev)->cmd.use_events)
 303                 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
 304         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 305 }
 306
 307 static int cmd_pending(struct mlx4_dev *dev)
 308 {
 309         u32 status;
 310
 311         if (pci_channel_offline(dev->pdev))
 312                 return -EIO;
 313
 314         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 315
 316         return (status & swab32(1 << HCR_GO_BIT)) ||
 317                 (mlx4_priv(dev)->cmd.toggle ==
 318                  !!(status & swab32(1 << HCR_T_BIT)));
 319 }
 320
 321 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 322                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 323                          int event)
 324 {
 325         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 326         u32 __iomem *hcr = cmd->hcr;
 327         int ret = -EAGAIN;
 328         unsigned long end;
 329
 330         mutex_lock(&cmd->hcr_mutex);
 331
 332         if (pci_channel_offline(dev->pdev)) {
 333                 /*
 334                  * Device is going through error recovery
 335                  * and cannot accept commands.
 336                  */
 337                 ret = -EIO;
 338                 goto out;
 339         }
 340
 341         end = jiffies;
 342         if (event)
 343                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 344
 345         while (cmd_pending(dev)) {
 346                 if (pci_channel_offline(dev->pdev)) {
 347                         /*
 348                          * Device is going through error recovery
 349                          * and cannot accept commands.
 350                          */
 351                         ret = -EIO;
 352                         goto out;
 353                 }
 354
 355                 if (time_after_eq(jiffies, end)) {
 356                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 357                         goto out;
 358                 }
 359                 cond_resched();
 360         }
 361
 362         /*
 363          * We use writel (instead of something like memcpy_toio)
 364          * because writes of less than 32 bits to the HCR don't work
 365          * (and some architectures such as ia64 implement memcpy_toio
 366          * in terms of writeb).
 367          */
 368         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 369         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 370         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 371         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 372         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 373         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 374
 375         /* __raw_writel may not order writes. */
 376         wmb();
 377
 378         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 379                                                (cmd->toggle << HCR_T_BIT)       |
 380                                                (event ? (1 << HCR_E_BIT) : 0)   |
 381                                                (op_modifier << HCR_OPMOD_SHIFT) |
 382                                                op), hcr + 6);
 383
 384         /*
 385          * Make sure that our HCR writes don't get mixed in with
 386          * writes from another CPU starting a FW command.
 387          */
 388         mmiowb();
 389
 390         cmd->toggle = cmd->toggle ^ 1;
 391
 392         ret = 0;
 393
 394 out:
 395         mutex_unlock(&cmd->hcr_mutex);
 396         return ret;
 397 }
 398
 399 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 400                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 401                           u16 op, unsigned long timeout)
 402 {
 403         struct mlx4_priv *priv = mlx4_priv(dev);
 404         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 405         int ret;
 406
 407         mutex_lock(&priv->cmd.slave_cmd_mutex);
 408
 409         vhcr->in_param = cpu_to_be64(in_param);
 410         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 411         vhcr->in_modifier = cpu_to_be32(in_modifier);
 412         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 413         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 414         vhcr->status = 0;
 415         vhcr->flags = !!(priv->cmd.use_events) << 6;
 416
 417         if (mlx4_is_master(dev)) {
 418                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 419                 if (!ret) {
 420                         if (out_is_imm) {
 421                                 if (out_param)
 422                                         *out_param =
 423                                                 be64_to_cpu(vhcr->out_param);
 424                                 else {
 425                                         mlx4_err(dev, "response expected while"
 426                                                  "output mailbox is NULL for "
 427                                                  "command 0x%x\n", op);
 428                                         vhcr->status = CMD_STAT_BAD_PARAM;
 429                                 }
 430                         }
 431                         ret = mlx4_status_to_errno(vhcr->status);
 432                 }
 433         } else {
 434                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
 435                                     MLX4_COMM_TIME + timeout);
 436                 if (!ret) {
 437                         if (out_is_imm) {
 438                                 if (out_param)
 439                                         *out_param =
 440                                                 be64_to_cpu(vhcr->out_param);
 441                                 else {
 442                                         mlx4_err(dev, "response expected while"
 443                                                  "output mailbox is NULL for "
 444                                                  "command 0x%x\n", op);
 445                                         vhcr->status = CMD_STAT_BAD_PARAM;
 446                                 }
 447                         }
 448                         ret = mlx4_status_to_errno(vhcr->status);
 449                 } else
 450                         mlx4_err(dev, "failed execution of VHCR_POST command"
 451                                  "opcode 0x%x\n", op);
 452         }
 453
 454         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 455         return ret;
 456 }
 457
 458 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 459                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 460                          u16 op, unsigned long timeout)
 461 {
 462         struct mlx4_priv *priv = mlx4_priv(dev);
 463         void __iomem *hcr = priv->cmd.hcr;
 464         int err = 0;
 465         unsigned long end;
 466         u32 stat;
 467
 468         down(&priv->cmd.poll_sem);
 469
 470         if (pci_channel_offline(dev->pdev)) {
 471                 /*
 472                  * Device is going through error recovery
 473                  * and cannot accept commands.
 474                  */
 475                 err = -EIO;
 476                 goto out;
 477         }
 478
 479         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 480                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 481         if (err)
 482                 goto out;
 483
 484         end = msecs_to_jiffies(timeout) + jiffies;
 485         while (cmd_pending(dev) && time_before(jiffies, end)) {
 486                 if (pci_channel_offline(dev->pdev)) {
 487                         /*
 488                          * Device is going through error recovery
 489                          * and cannot accept commands.
 490                          */
 491                         err = -EIO;
 492                         goto out;
 493                 }
 494
 495                 cond_resched();
 496         }
 497
 498         if (cmd_pending(dev)) {
 499                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 500                           op);
 501                 err = -ETIMEDOUT;
 502                 goto out;
 503         }
 504
 505         if (out_is_imm)
 506                 *out_param =
 507                         (u64) be32_to_cpu((__force __be32)
 508                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 509                         (u64) be32_to_cpu((__force __be32)
 510                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 511         stat = be32_to_cpu((__force __be32)
 512                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 513         err = mlx4_status_to_errno(stat);
 514         if (err)
 515                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 516                          op, stat);
 517
 518 out:
 519         up(&priv->cmd.poll_sem);
 520         return err;
 521 }
 522
 523 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 524 {
 525         struct mlx4_priv *priv = mlx4_priv(dev);
 526         struct mlx4_cmd_context *context =
 527                 &priv->cmd.context[token & priv->cmd.token_mask];
 528
 529         /* previously timed out command completing at long last */
 530         if (token != context->token)
 531                 return;
 532
 533         context->fw_status = status;
 534         context->result    = mlx4_status_to_errno(status);
 535         context->out_param = out_param;
 536
 537         complete(&context->done);
 538 }
 539
 540 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 541                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 542                          u16 op, unsigned long timeout)
 543 {
 544         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 545         struct mlx4_cmd_context *context;
 546         int err = 0;
 547
 548         down(&cmd->event_sem);
 549
 550         spin_lock(&cmd->context_lock);
 551         BUG_ON(cmd->free_head < 0);
 552         context = &cmd->context[cmd->free_head];
 553         context->token += cmd->token_mask + 1;
 554         cmd->free_head = context->next;
 555         spin_unlock(&cmd->context_lock);
 556
 557         init_completion(&context->done);
 558
 559         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 560                       in_modifier, op_modifier, op, context->token, 1);
 561
 562         if (!wait_for_completion_timeout(&context->done,
 563                                          msecs_to_jiffies(timeout))) {
 564                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 565                           op);
 566                 err = -EBUSY;
 567                 goto out;
 568         }
 569
 570         err = context->result;
 571         if (err) {
 572                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 573                          op, context->fw_status);
 574                 goto out;
 575         }
 576
 577         if (out_is_imm)
 578                 *out_param = context->out_param;
 579
 580 out:
 581         spin_lock(&cmd->context_lock);
 582         context->next = cmd->free_head;
 583         cmd->free_head = context - cmd->context;
 584         spin_unlock(&cmd->context_lock);
 585
 586         up(&cmd->event_sem);
 587         return err;
 588 }
 589
 590 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 591                int out_is_imm, u32 in_modifier, u8 op_modifier,
 592                u16 op, unsigned long timeout, int native)
 593 {
 594         if (pci_channel_offline(dev->pdev))
 595                 return -EIO;
 596
 597         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 598                 if (mlx4_priv(dev)->cmd.use_events)
 599                         return mlx4_cmd_wait(dev, in_param, out_param,
 600                                              out_is_imm, in_modifier,
 601                                              op_modifier, op, timeout);
 602                 else
 603                         return mlx4_cmd_poll(dev, in_param, out_param,
 604                                              out_is_imm, in_modifier,
 605                                              op_modifier, op, timeout);
 606         }
 607         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 608                               in_modifier, op_modifier, op, timeout);
 609 }
 610 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 611
 612
 613 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 614 {
 615         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 616                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 617 }
 618
 619 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 620                            int slave, u64 slave_addr,
 621                            int size, int is_read)
 622 {
 623         u64 in_param;
 624         u64 out_param;
 625
 626         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 627             (slave & ~0x7f) | (size & 0xff)) {
 628                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
 629                               "master_addr:0x%llx slave_id:%d size:%d\n",
 630                               slave_addr, master_addr, slave, size);
 631                 return -EINVAL;
 632         }
 633
 634         if (is_read) {
 635                 in_param = (u64) slave | slave_addr;
 636                 out_param = (u64) dev->caps.function | master_addr;
 637         } else {
 638                 in_param = (u64) dev->caps.function | master_addr;
 639                 out_param = (u64) slave | slave_addr;
 640         }
 641
 642         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 643                             MLX4_CMD_ACCESS_MEM,
 644                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 645 }
 646
 647 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 648                                struct mlx4_cmd_mailbox *inbox,
 649                                struct mlx4_cmd_mailbox *outbox)
 650 {
 651         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 652         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 653         int err;
 654         int i;
 655
 656         if (index & 0x1f)
 657                 return -EINVAL;
 658
 659         in_mad->attr_mod = cpu_to_be32(index / 32);
 660
 661         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 662                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 663                            MLX4_CMD_NATIVE);
 664         if (err)
 665                 return err;
 666
 667         for (i = 0; i < 32; ++i)
 668                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 669
 670         return err;
 671 }
 672
 673 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 674                                struct mlx4_cmd_mailbox *inbox,
 675                                struct mlx4_cmd_mailbox *outbox)
 676 {
 677         int i;
 678         int err;
 679
 680         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 681                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 682                 if (err)
 683                         return err;
 684         }
 685
 686         return 0;
 687 }
 688 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 689 #define PORT_STATE_OFFSET 32
 690
 691 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 692 {
 693         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 694                 return IB_PORT_ACTIVE;
 695         else
 696                 return IB_PORT_DOWN;
 697 }
 698
 699 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 700                                 struct mlx4_vhcr *vhcr,
 701                                 struct mlx4_cmd_mailbox *inbox,
 702                                 struct mlx4_cmd_mailbox *outbox,
 703                                 struct mlx4_cmd_info *cmd)
 704 {
 705         struct ib_smp *smp = inbox->buf;
 706         u32 index;
 707         u8 port;
 708         u16 *table;
 709         int err;
 710         int vidx, pidx;
 711         struct mlx4_priv *priv = mlx4_priv(dev);
 712         struct ib_smp *outsmp = outbox->buf;
 713         __be16 *outtab = (__be16 *)(outsmp->data);
 714         __be32 slave_cap_mask;
 715         __be64 slave_node_guid;
 716         port = vhcr->in_modifier;
 717
 718         if (smp->base_version == 1 &&
 719             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 720             smp->class_version == 1) {
 721                 if (smp->method == IB_MGMT_METHOD_GET) {
 722                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 723                                 index = be32_to_cpu(smp->attr_mod);
 724                                 if (port < 1 || port > dev->caps.num_ports)
 725                                         return -EINVAL;
 726                                 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
 727                                 if (!table)
 728                                         return -ENOMEM;
 729                                 /* need to get the full pkey table because the paravirtualized
 730                                  * pkeys may be scattered among several pkey blocks.
 731                                  */
 732                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 733                                 if (!err) {
 734                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 735                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 736                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 737                                         }
 738                                 }
 739                                 kfree(table);
 740                                 return err;
 741                         }
 742                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 743                                 /*get the slave specific caps:*/
 744                                 /*do the command */
 745                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 746                                             vhcr->in_modifier, vhcr->op_modifier,
 747                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 748                                 /* modify the response for slaves */
 749                                 if (!err && slave != mlx4_master_func_num(dev)) {
 750                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 751
 752                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 753                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 754                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 755                                 }
 756                                 return err;
 757                         }
 758                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 759                                 /* compute slave's gid block */
 760                                 smp->attr_mod = cpu_to_be32(slave / 8);
 761                                 /* execute cmd */
 762                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 763                                              vhcr->in_modifier, vhcr->op_modifier,
 764                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 765                                 if (!err) {
 766                                         /* if needed, move slave gid to index 0 */
 767                                         if (slave % 8)
 768                                                 memcpy(outsmp->data,
 769                                                        outsmp->data + (slave % 8) * 8, 8);
 770                                         /* delete all other gids */
 771                                         memset(outsmp->data + 8, 0, 56);
 772                                 }
 773                                 return err;
 774                         }
 775                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 776                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 777                                              vhcr->in_modifier, vhcr->op_modifier,
 778                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 779                                 if (!err) {
 780                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 781                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 782                                 }
 783                                 return err;
 784                         }
 785                 }
 786         }
 787         if (slave != mlx4_master_func_num(dev) &&
 788             ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
 789              (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 790               smp->method == IB_MGMT_METHOD_SET))) {
 791                 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
 792                          "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
 793                          slave, smp->method, smp->mgmt_class,
 794                          be16_to_cpu(smp->attr_id));
 795                 return -EPERM;
 796         }
 797         /*default:*/
 798         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 799                                     vhcr->in_modifier, vhcr->op_modifier,
 800                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 801 }
 802
 803 int MLX4_CMD_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
 804                      struct mlx4_vhcr *vhcr,
 805                      struct mlx4_cmd_mailbox *inbox,
 806                      struct mlx4_cmd_mailbox *outbox,
 807                      struct mlx4_cmd_info *cmd)
 808 {
 809         return -EPERM;
 810 }
 811
 812 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 813                      struct mlx4_vhcr *vhcr,
 814                      struct mlx4_cmd_mailbox *inbox,
 815                      struct mlx4_cmd_mailbox *outbox,
 816                      struct mlx4_cmd_info *cmd)
 817 {
 818         u64 in_param;
 819         u64 out_param;
 820         int err;
 821
 822         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
 823         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
 824         if (cmd->encode_slave_id) {
 825                 in_param &= 0xffffffffffffff00ll;
 826                 in_param |= slave;
 827         }
 828
 829         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
 830                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
 831                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 832
 833         if (cmd->out_is_imm)
 834                 vhcr->out_param = out_param;
 835
 836         return err;
 837 }
 838
 839 static struct mlx4_cmd_info cmd_info[] = {
 840         {
 841                 .opcode = MLX4_CMD_QUERY_FW,
 842                 .has_inbox = false,
 843                 .has_outbox = true,
 844                 .out_is_imm = false,
 845                 .encode_slave_id = false,
 846                 .verify = NULL,
 847                 .wrapper = mlx4_QUERY_FW_wrapper
 848         },
 849         {
 850                 .opcode = MLX4_CMD_QUERY_HCA,
 851                 .has_inbox = false,
 852                 .has_outbox = true,
 853                 .out_is_imm = false,
 854                 .encode_slave_id = false,
 855                 .verify = NULL,
 856                 .wrapper = NULL
 857         },
 858         {
 859                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
 860                 .has_inbox = false,
 861                 .has_outbox = true,
 862                 .out_is_imm = false,
 863                 .encode_slave_id = false,
 864                 .verify = NULL,
 865                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
 866         },
 867         {
 868                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
 869                 .has_inbox = false,
 870                 .has_outbox = true,
 871                 .out_is_imm = false,
 872                 .encode_slave_id = false,
 873                 .verify = NULL,
 874                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
 875         },
 876         {
 877                 .opcode = MLX4_CMD_QUERY_ADAPTER,
 878                 .has_inbox = false,
 879                 .has_outbox = true,
 880                 .out_is_imm = false,
 881                 .encode_slave_id = false,
 882                 .verify = NULL,
 883                 .wrapper = NULL
 884         },
 885         {
 886                 .opcode = MLX4_CMD_INIT_PORT,
 887                 .has_inbox = false,
 888                 .has_outbox = false,
 889                 .out_is_imm = false,
 890                 .encode_slave_id = false,
 891                 .verify = NULL,
 892                 .wrapper = mlx4_INIT_PORT_wrapper
 893         },
 894         {
 895                 .opcode = MLX4_CMD_CLOSE_PORT,
 896                 .has_inbox = false,
 897                 .has_outbox = false,
 898                 .out_is_imm  = false,
 899                 .encode_slave_id = false,
 900                 .verify = NULL,
 901                 .wrapper = mlx4_CLOSE_PORT_wrapper
 902         },
 903         {
 904                 .opcode = MLX4_CMD_QUERY_PORT,
 905                 .has_inbox = false,
 906                 .has_outbox = true,
 907                 .out_is_imm = false,
 908                 .encode_slave_id = false,
 909                 .verify = NULL,
 910                 .wrapper = mlx4_QUERY_PORT_wrapper
 911         },
 912         {
 913                 .opcode = MLX4_CMD_SET_PORT,
 914                 .has_inbox = true,
 915                 .has_outbox = false,
 916                 .out_is_imm = false,
 917                 .encode_slave_id = false,
 918                 .verify = NULL,
 919                 .wrapper = mlx4_SET_PORT_wrapper
 920         },
 921         {
 922                 .opcode = MLX4_CMD_MAP_EQ,
 923                 .has_inbox = false,
 924                 .has_outbox = false,
 925                 .out_is_imm = false,
 926                 .encode_slave_id = false,
 927                 .verify = NULL,
 928                 .wrapper = mlx4_MAP_EQ_wrapper
 929         },
 930         {
 931                 .opcode = MLX4_CMD_SW2HW_EQ,
 932                 .has_inbox = true,
 933                 .has_outbox = false,
 934                 .out_is_imm = false,
 935                 .encode_slave_id = true,
 936                 .verify = NULL,
 937                 .wrapper = mlx4_SW2HW_EQ_wrapper
 938         },
 939         {
 940                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
 941                 .has_inbox = false,
 942                 .has_outbox = false,
 943                 .out_is_imm = false,
 944                 .encode_slave_id = false,
 945                 .verify = NULL,
 946                 .wrapper = NULL
 947         },
 948         {
 949                 .opcode = MLX4_CMD_NOP,
 950                 .has_inbox = false,
 951                 .has_outbox = false,
 952                 .out_is_imm = false,
 953                 .encode_slave_id = false,
 954                 .verify = NULL,
 955                 .wrapper = NULL
 956         },
 957         {
 958                 .opcode = MLX4_CMD_ALLOC_RES,
 959                 .has_inbox = false,
 960                 .has_outbox = false,
 961                 .out_is_imm = true,
 962                 .encode_slave_id = false,
 963                 .verify = NULL,
 964                 .wrapper = mlx4_ALLOC_RES_wrapper
 965         },
 966         {
 967                 .opcode = MLX4_CMD_FREE_RES,
 968                 .has_inbox = false,
 969                 .has_outbox = false,
 970                 .out_is_imm = false,
 971                 .encode_slave_id = false,
 972                 .verify = NULL,
 973                 .wrapper = mlx4_FREE_RES_wrapper
 974         },
 975         {
 976                 .opcode = MLX4_CMD_SW2HW_MPT,
 977                 .has_inbox = true,
 978                 .has_outbox = false,
 979                 .out_is_imm = false,
 980                 .encode_slave_id = true,
 981                 .verify = NULL,
 982                 .wrapper = mlx4_SW2HW_MPT_wrapper
 983         },
 984         {
 985                 .opcode = MLX4_CMD_QUERY_MPT,
 986                 .has_inbox = false,
 987                 .has_outbox = true,
 988                 .out_is_imm = false,
 989                 .encode_slave_id = false,
 990                 .verify = NULL,
 991                 .wrapper = mlx4_QUERY_MPT_wrapper
 992         },
 993         {
 994                 .opcode = MLX4_CMD_HW2SW_MPT,
 995                 .has_inbox = false,
 996                 .has_outbox = false,
 997                 .out_is_imm = false,
 998                 .encode_slave_id = false,
 999                 .verify = NULL,
1000                 .wrapper = mlx4_HW2SW_MPT_wrapper
1001         },
1002         {
1003                 .opcode = MLX4_CMD_READ_MTT,
1004                 .has_inbox = false,
1005                 .has_outbox = true,
1006                 .out_is_imm = false,
1007                 .encode_slave_id = false,
1008                 .verify = NULL,
1009                 .wrapper = NULL
1010         },
1011         {
1012                 .opcode = MLX4_CMD_WRITE_MTT,
1013                 .has_inbox = true,
1014                 .has_outbox = false,
1015                 .out_is_imm = false,
1016                 .encode_slave_id = false,
1017                 .verify = NULL,
1018                 .wrapper = mlx4_WRITE_MTT_wrapper
1019         },
1020         {
1021                 .opcode = MLX4_CMD_SYNC_TPT,
1022                 .has_inbox = true,
1023                 .has_outbox = false,
1024                 .out_is_imm = false,
1025                 .encode_slave_id = false,
1026                 .verify = NULL,
1027                 .wrapper = NULL
1028         },
1029         {
1030                 .opcode = MLX4_CMD_HW2SW_EQ,
1031                 .has_inbox = false,
1032                 .has_outbox = true,
1033                 .out_is_imm = false,
1034                 .encode_slave_id = true,
1035                 .verify = NULL,
1036                 .wrapper = mlx4_HW2SW_EQ_wrapper
1037         },
1038         {
1039                 .opcode = MLX4_CMD_QUERY_EQ,
1040                 .has_inbox = false,
1041                 .has_outbox = true,
1042                 .out_is_imm = false,
1043                 .encode_slave_id = true,
1044                 .verify = NULL,
1045                 .wrapper = mlx4_QUERY_EQ_wrapper
1046         },
1047         {
1048                 .opcode = MLX4_CMD_SW2HW_CQ,
1049                 .has_inbox = true,
1050                 .has_outbox = false,
1051                 .out_is_imm = false,
1052                 .encode_slave_id = true,
1053                 .verify = NULL,
1054                 .wrapper = mlx4_SW2HW_CQ_wrapper
1055         },
1056         {
1057                 .opcode = MLX4_CMD_HW2SW_CQ,
1058                 .has_inbox = false,
1059                 .has_outbox = false,
1060                 .out_is_imm = false,
1061                 .encode_slave_id = false,
1062                 .verify = NULL,
1063                 .wrapper = mlx4_HW2SW_CQ_wrapper
1064         },
1065         {
1066                 .opcode = MLX4_CMD_QUERY_CQ,
1067                 .has_inbox = false,
1068                 .has_outbox = true,
1069                 .out_is_imm = false,
1070                 .encode_slave_id = false,
1071                 .verify = NULL,
1072                 .wrapper = mlx4_QUERY_CQ_wrapper
1073         },
1074         {
1075                 .opcode = MLX4_CMD_MODIFY_CQ,
1076                 .has_inbox = true,
1077                 .has_outbox = false,
1078                 .out_is_imm = true,
1079                 .encode_slave_id = false,
1080                 .verify = NULL,
1081                 .wrapper = mlx4_MODIFY_CQ_wrapper
1082         },
1083         {
1084                 .opcode = MLX4_CMD_SW2HW_SRQ,
1085                 .has_inbox = true,
1086                 .has_outbox = false,
1087                 .out_is_imm = false,
1088                 .encode_slave_id = true,
1089                 .verify = NULL,
1090                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1091         },
1092         {
1093                 .opcode = MLX4_CMD_HW2SW_SRQ,
1094                 .has_inbox = false,
1095                 .has_outbox = false,
1096                 .out_is_imm = false,
1097                 .encode_slave_id = false,
1098                 .verify = NULL,
1099                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1100         },
1101         {
1102                 .opcode = MLX4_CMD_QUERY_SRQ,
1103                 .has_inbox = false,
1104                 .has_outbox = true,
1105                 .out_is_imm = false,
1106                 .encode_slave_id = false,
1107                 .verify = NULL,
1108                 .wrapper = mlx4_QUERY_SRQ_wrapper
1109         },
1110         {
1111                 .opcode = MLX4_CMD_ARM_SRQ,
1112                 .has_inbox = false,
1113                 .has_outbox = false,
1114                 .out_is_imm = false,
1115                 .encode_slave_id = false,
1116                 .verify = NULL,
1117                 .wrapper = mlx4_ARM_SRQ_wrapper
1118         },
1119         {
1120                 .opcode = MLX4_CMD_RST2INIT_QP,
1121                 .has_inbox = true,
1122                 .has_outbox = false,
1123                 .out_is_imm = false,
1124                 .encode_slave_id = true,
1125                 .verify = NULL,
1126                 .wrapper = mlx4_RST2INIT_QP_wrapper
1127         },
1128         {
1129                 .opcode = MLX4_CMD_INIT2INIT_QP,
1130                 .has_inbox = true,
1131                 .has_outbox = false,
1132                 .out_is_imm = false,
1133                 .encode_slave_id = false,
1134                 .verify = NULL,
1135                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1136         },
1137         {
1138                 .opcode = MLX4_CMD_INIT2RTR_QP,
1139                 .has_inbox = true,
1140                 .has_outbox = false,
1141                 .out_is_imm = false,
1142                 .encode_slave_id = false,
1143                 .verify = NULL,
1144                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1145         },
1146         {
1147                 .opcode = MLX4_CMD_RTR2RTS_QP,
1148                 .has_inbox = true,
1149                 .has_outbox = false,
1150                 .out_is_imm = false,
1151                 .encode_slave_id = false,
1152                 .verify = NULL,
1153                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1154         },
1155         {
1156                 .opcode = MLX4_CMD_RTS2RTS_QP,
1157                 .has_inbox = true,
1158                 .has_outbox = false,
1159                 .out_is_imm = false,
1160                 .encode_slave_id = false,
1161                 .verify = NULL,
1162                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1163         },
1164         {
1165                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1166                 .has_inbox = true,
1167                 .has_outbox = false,
1168                 .out_is_imm = false,
1169                 .encode_slave_id = false,
1170                 .verify = NULL,
1171                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1172         },
1173         {
1174                 .opcode = MLX4_CMD_2ERR_QP,
1175                 .has_inbox = false,
1176                 .has_outbox = false,
1177                 .out_is_imm = false,
1178                 .encode_slave_id = false,
1179                 .verify = NULL,
1180                 .wrapper = mlx4_GEN_QP_wrapper
1181         },
1182         {
1183                 .opcode = MLX4_CMD_RTS2SQD_QP,
1184                 .has_inbox = false,
1185                 .has_outbox = false,
1186                 .out_is_imm = false,
1187                 .encode_slave_id = false,
1188                 .verify = NULL,
1189                 .wrapper = mlx4_GEN_QP_wrapper
1190         },
1191         {
1192                 .opcode = MLX4_CMD_SQD2SQD_QP,
1193                 .has_inbox = true,
1194                 .has_outbox = false,
1195                 .out_is_imm = false,
1196                 .encode_slave_id = false,
1197                 .verify = NULL,
1198                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1199         },
1200         {
1201                 .opcode = MLX4_CMD_SQD2RTS_QP,
1202                 .has_inbox = true,
1203                 .has_outbox = false,
1204                 .out_is_imm = false,
1205                 .encode_slave_id = false,
1206                 .verify = NULL,
1207                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1208         },
1209         {
1210                 .opcode = MLX4_CMD_2RST_QP,
1211                 .has_inbox = false,
1212                 .has_outbox = false,
1213                 .out_is_imm = false,
1214                 .encode_slave_id = false,
1215                 .verify = NULL,
1216                 .wrapper = mlx4_2RST_QP_wrapper
1217         },
1218         {
1219                 .opcode = MLX4_CMD_QUERY_QP,
1220                 .has_inbox = false,
1221                 .has_outbox = true,
1222                 .out_is_imm = false,
1223                 .encode_slave_id = false,
1224                 .verify = NULL,
1225                 .wrapper = mlx4_GEN_QP_wrapper
1226         },
1227         {
1228                 .opcode = MLX4_CMD_SUSPEND_QP,
1229                 .has_inbox = false,
1230                 .has_outbox = false,
1231                 .out_is_imm = false,
1232                 .encode_slave_id = false,
1233                 .verify = NULL,
1234                 .wrapper = mlx4_GEN_QP_wrapper
1235         },
1236         {
1237                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1238                 .has_inbox = false,
1239                 .has_outbox = false,
1240                 .out_is_imm = false,
1241                 .encode_slave_id = false,
1242                 .verify = NULL,
1243                 .wrapper = mlx4_GEN_QP_wrapper
1244         },
1245         {
1246                 .opcode = MLX4_CMD_UPDATE_QP,
1247                 .has_inbox = false,
1248                 .has_outbox = false,
1249                 .out_is_imm = false,
1250                 .encode_slave_id = false,
1251                 .verify = NULL,
1252                 .wrapper = MLX4_CMD_UPDATE_QP_wrapper
1253         },
1254         {
1255                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1256                 .has_inbox = false,
1257                 .has_outbox = false,
1258                 .out_is_imm = false,
1259                 .encode_slave_id = false,
1260                 .verify = NULL, /* XXX verify: only demux can do this */
1261                 .wrapper = NULL
1262         },
1263         {
1264                 .opcode = MLX4_CMD_MAD_IFC,
1265                 .has_inbox = true,
1266                 .has_outbox = true,
1267                 .out_is_imm = false,
1268                 .encode_slave_id = false,
1269                 .verify = NULL,
1270                 .wrapper = mlx4_MAD_IFC_wrapper
1271         },
1272         {
1273                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1274                 .has_inbox = false,
1275                 .has_outbox = true,
1276                 .out_is_imm = false,
1277                 .encode_slave_id = false,
1278                 .verify = NULL,
1279                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1280         },
1281         /* Native multicast commands are not available for guests */
1282         {
1283                 .opcode = MLX4_CMD_QP_ATTACH,
1284                 .has_inbox = true,
1285                 .has_outbox = false,
1286                 .out_is_imm = false,
1287                 .encode_slave_id = false,
1288                 .verify = NULL,
1289                 .wrapper = mlx4_QP_ATTACH_wrapper
1290         },
1291         {
1292                 .opcode = MLX4_CMD_PROMISC,
1293                 .has_inbox = false,
1294                 .has_outbox = false,
1295                 .out_is_imm = false,
1296                 .encode_slave_id = false,
1297                 .verify = NULL,
1298                 .wrapper = mlx4_PROMISC_wrapper
1299         },
1300         /* Ethernet specific commands */
1301         {
1302                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1303                 .has_inbox = true,
1304                 .has_outbox = false,
1305                 .out_is_imm = false,
1306                 .encode_slave_id = false,
1307                 .verify = NULL,
1308                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1309         },
1310         {
1311                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1312                 .has_inbox = false,
1313                 .has_outbox = false,
1314                 .out_is_imm = false,
1315                 .encode_slave_id = false,
1316                 .verify = NULL,
1317                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1318         },
1319         {
1320                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1321                 .has_inbox = false,
1322                 .has_outbox = true,
1323                 .out_is_imm = false,
1324                 .encode_slave_id = false,
1325                 .verify = NULL,
1326                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1327         },
1328         {
1329                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1330                 .has_inbox = false,
1331                 .has_outbox = false,
1332                 .out_is_imm = false,
1333                 .encode_slave_id = false,
1334                 .verify = NULL,
1335                 .wrapper = NULL
1336         },
1337         /* flow steering commands */
1338         {
1339                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1340                 .has_inbox = true,
1341                 .has_outbox = false,
1342                 .out_is_imm = true,
1343                 .encode_slave_id = false,
1344                 .verify = NULL,
1345                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1346         },
1347         {
1348                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1349                 .has_inbox = false,
1350                 .has_outbox = false,
1351                 .out_is_imm = false,
1352                 .encode_slave_id = false,
1353                 .verify = NULL,
1354                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1355         },
1356 };
1357
1358 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1359                                     struct mlx4_vhcr_cmd *in_vhcr)
1360 {
1361         struct mlx4_priv *priv = mlx4_priv(dev);
1362         struct mlx4_cmd_info *cmd = NULL;
1363         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1364         struct mlx4_vhcr *vhcr;
1365         struct mlx4_cmd_mailbox *inbox = NULL;
1366         struct mlx4_cmd_mailbox *outbox = NULL;
1367         u64 in_param;
1368         u64 out_param;
1369         int ret = 0;
1370         int i;
1371         int err = 0;
1372
1373         /* Create sw representation of Virtual HCR */
1374         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1375         if (!vhcr)
1376                 return -ENOMEM;
1377
1378         /* DMA in the vHCR */
1379         if (!in_vhcr) {
1380                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1381                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1382                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1383                                             MLX4_ACCESS_MEM_ALIGN), 1);
1384                 if (ret) {
1385                         mlx4_err(dev, "%s:Failed reading vhcr"
1386                                  "ret: 0x%x\n", __func__, ret);
1387                         kfree(vhcr);
1388                         return ret;
1389                 }
1390         }
1391
1392         /* Fill SW VHCR fields */
1393         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1394         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1395         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1396         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1397         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1398         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1399         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1400
1401         /* Lookup command */
1402         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1403                 if (vhcr->op == cmd_info[i].opcode) {
1404                         cmd = &cmd_info[i];
1405                         break;
1406                 }
1407         }
1408         if (!cmd) {
1409                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1410                          vhcr->op, slave);
1411                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1412                 goto out_status;
1413         }
1414
1415         /* Read inbox */
1416         if (cmd->has_inbox) {
1417                 vhcr->in_param &= INBOX_MASK;
1418                 inbox = mlx4_alloc_cmd_mailbox(dev);
1419                 if (IS_ERR(inbox)) {
1420                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1421                         inbox = NULL;
1422                         goto out_status;
1423                 }
1424
1425                 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1426                                     vhcr->in_param,
1427                                     MLX4_MAILBOX_SIZE, 1)) {
1428                         mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1429                                  __func__, cmd->opcode);
1430                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1431                         goto out_status;
1432                 }
1433         }
1434
1435         /* Apply permission and bound checks if applicable */
1436         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1437                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1438                           "checks for resource_id:%d\n", vhcr->op, slave,
1439                           vhcr->in_modifier);
1440                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1441                 goto out_status;
1442         }
1443
1444         /* Allocate outbox */
1445         if (cmd->has_outbox) {
1446                 outbox = mlx4_alloc_cmd_mailbox(dev);
1447                 if (IS_ERR(outbox)) {
1448                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1449                         outbox = NULL;
1450                         goto out_status;
1451                 }
1452         }
1453
1454         /* Execute the command! */
1455         if (cmd->wrapper) {
1456                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1457                                    cmd);
1458                 if (cmd->out_is_imm)
1459                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1460         } else {
1461                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1462                         vhcr->in_param;
1463                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1464                         vhcr->out_param;
1465                 err = __mlx4_cmd(dev, in_param, &out_param,
1466                                  cmd->out_is_imm, vhcr->in_modifier,
1467                                  vhcr->op_modifier, vhcr->op,
1468                                  MLX4_CMD_TIME_CLASS_A,
1469                                  MLX4_CMD_NATIVE);
1470
1471                 if (cmd->out_is_imm) {
1472                         vhcr->out_param = out_param;
1473                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1474                 }
1475         }
1476
1477         if (err) {
1478                 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1479                           " error:%d, status %d\n",
1480                           vhcr->op, slave, vhcr->errno, err);
1481                 vhcr_cmd->status = mlx4_errno_to_status(err);
1482                 goto out_status;
1483         }
1484
1485
1486         /* Write outbox if command completed successfully */
1487         if (cmd->has_outbox && !vhcr_cmd->status) {
1488                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1489                                       vhcr->out_param,
1490                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1491                 if (ret) {
1492                         /* If we failed to write back the outbox after the
1493                          *command was successfully executed, we must fail this
1494                          * slave, as it is now in undefined state */
1495                         mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1496                         goto out;
1497                 }
1498         }
1499
1500 out_status:
1501         /* DMA back vhcr result */
1502         if (!in_vhcr) {
1503                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1504                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1505                                       ALIGN(sizeof(struct mlx4_vhcr),
1506                                             MLX4_ACCESS_MEM_ALIGN),
1507                                       MLX4_CMD_WRAPPED);
1508                 if (ret)
1509                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1510                                  __func__);
1511                 else if (vhcr->e_bit &&
1512                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1513                                 mlx4_warn(dev, "Failed to generate command completion "
1514                                           "eqe for slave %d\n", slave);
1515         }
1516
1517 out:
1518         kfree(vhcr);
1519         mlx4_free_cmd_mailbox(dev, inbox);
1520         mlx4_free_cmd_mailbox(dev, outbox);
1521         return ret;
1522 }
1523
1524
1525 int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1526                                             int slave, int port)
1527 {
1528         struct mlx4_vport_oper_state *vp_oper;
1529         struct mlx4_vport_state *vp_admin;
1530         struct mlx4_vf_immed_vlan_work *work;
1531         int err;
1532         int admin_vlan_ix = NO_INDX;
1533
1534         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1535         vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1536
1537         if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1538             vp_oper->state.default_qos == vp_admin->default_qos)
1539                 return 0;
1540
1541         work = kzalloc(sizeof(*work), GFP_KERNEL);
1542         if (!work)
1543                 return -ENOMEM;
1544
1545         if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1546                 err = __mlx4_register_vlan(&priv->dev, port,
1547                                            vp_admin->default_vlan,
1548                                            &admin_vlan_ix);
1549                 if (err) {
1550                         mlx4_warn((&priv->dev),
1551                                   "No vlan resources slave %d, port %d\n",
1552                                   slave, port);
1553                         return err;
1554                 }
1555                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1556                 mlx4_dbg((&(priv->dev)),
1557                          "alloc vlan %d idx  %d slave %d port %d\n",
1558                          (int)(vp_admin->default_vlan),
1559                          admin_vlan_ix, slave, port);
1560         }
1561
1562         /* save original vlan ix and vlan id */
1563         work->orig_vlan_id = vp_oper->state.default_vlan;
1564         work->orig_vlan_ix = vp_oper->vlan_idx;
1565
1566         /* handle new qos */
1567         if (vp_oper->state.default_qos != vp_admin->default_qos)
1568                 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1569
1570         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1571                 vp_oper->vlan_idx = admin_vlan_ix;
1572
1573         vp_oper->state.default_vlan = vp_admin->default_vlan;
1574         vp_oper->state.default_qos = vp_admin->default_qos;
1575
1576         /* iterate over QPs owned by this slave, using UPDATE_QP */
1577         work->port = port;
1578         work->slave = slave;
1579         work->qos = vp_oper->state.default_qos;
1580         work->vlan_id = vp_oper->state.default_vlan;
1581         work->vlan_ix = vp_oper->vlan_idx;
1582         work->priv = priv;
1583         INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1584         queue_work(priv->mfunc.master.comm_wq, &work->work);
1585
1586         return 0;
1587 }
1588
1589
1590 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1591 {
1592         int port, err;
1593         struct mlx4_vport_state *vp_admin;
1594         struct mlx4_vport_oper_state *vp_oper;
1595
1596         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1597                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1598                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1599                 vp_oper->state = *vp_admin;
1600                 if (MLX4_VGT != vp_admin->default_vlan) {
1601                         err = __mlx4_register_vlan(&priv->dev, port,
1602                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
1603                         if (err) {
1604                                 vp_oper->vlan_idx = NO_INDX;
1605                                 mlx4_warn((&priv->dev),
1606                                           "No vlan resorces slave %d, port %d\n",
1607                                           slave, port);
1608                                 return err;
1609                         }
1610                         mlx4_dbg((&(priv->dev)), "alloc vlan %d idx  %d slave %d port %d\n",
1611                                  (int)(vp_oper->state.default_vlan),
1612                                  vp_oper->vlan_idx, slave, port);
1613                 }
1614                 if (vp_admin->spoofchk) {
1615                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1616                                                                port,
1617                                                                vp_admin->mac);
1618                         if (0 > vp_oper->mac_idx) {
1619                                 err = vp_oper->mac_idx;
1620                                 vp_oper->mac_idx = NO_INDX;
1621                                 mlx4_warn((&priv->dev),
1622                                           "No mac resorces slave %d, port %d\n",
1623                                           slave, port);
1624                                 return err;
1625                         }
1626                         mlx4_dbg((&(priv->dev)), "alloc mac %llx idx  %d slave %d port %d\n",
1627                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1628                 }
1629         }
1630         return 0;
1631 }
1632
1633 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1634 {
1635         int port;
1636         struct mlx4_vport_oper_state *vp_oper;
1637
1638         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1639                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1640                 if (NO_INDX != vp_oper->vlan_idx) {
1641                         __mlx4_unregister_vlan(&priv->dev,
1642                                                port, vp_oper->vlan_idx);
1643                         vp_oper->vlan_idx = NO_INDX;
1644                 }
1645                 if (NO_INDX != vp_oper->mac_idx) {
1646                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->mac_idx);
1647                         vp_oper->mac_idx = NO_INDX;
1648                 }
1649         }
1650         return;
1651 }
1652
1653 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1654                                u16 param, u8 toggle)
1655 {
1656         struct mlx4_priv *priv = mlx4_priv(dev);
1657         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1658         u32 reply;
1659         u8 is_going_down = 0;
1660         int i;
1661         unsigned long flags;
1662
1663         slave_state[slave].comm_toggle ^= 1;
1664         reply = (u32) slave_state[slave].comm_toggle << 31;
1665         if (toggle != slave_state[slave].comm_toggle) {
1666                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1667                           "STATE COMPROMISIED ***\n", toggle, slave);
1668                 goto reset_slave;
1669         }
1670         if (cmd == MLX4_COMM_CMD_RESET) {
1671                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1672                 slave_state[slave].active = false;
1673                 mlx4_master_deactivate_admin_state(priv, slave);
1674                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1675                                 slave_state[slave].event_eq[i].eqn = -1;
1676                                 slave_state[slave].event_eq[i].token = 0;
1677                 }
1678                 /*check if we are in the middle of FLR process,
1679                 if so return "retry" status to the slave*/
1680                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1681                         goto inform_slave_state;
1682
1683                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1684
1685                 /* write the version in the event field */
1686                 reply |= mlx4_comm_get_version();
1687
1688                 goto reset_slave;
1689         }
1690         /*command from slave in the middle of FLR*/
1691         if (cmd != MLX4_COMM_CMD_RESET &&
1692             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1693                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1694                           "in the middle of FLR\n", slave, cmd);
1695                 return;
1696         }
1697
1698         switch (cmd) {
1699         case MLX4_COMM_CMD_VHCR0:
1700                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1701                         goto reset_slave;
1702                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1703                 priv->mfunc.master.slave_state[slave].cookie = 0;
1704                 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1705                 break;
1706         case MLX4_COMM_CMD_VHCR1:
1707                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1708                         goto reset_slave;
1709                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1710                 break;
1711         case MLX4_COMM_CMD_VHCR2:
1712                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1713                         goto reset_slave;
1714                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1715                 break;
1716         case MLX4_COMM_CMD_VHCR_EN:
1717                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1718                         goto reset_slave;
1719                 slave_state[slave].vhcr_dma |= param;
1720                 if (mlx4_master_activate_admin_state(priv, slave))
1721                                 goto reset_slave;
1722                 slave_state[slave].active = true;
1723                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1724                 break;
1725         case MLX4_COMM_CMD_VHCR_POST:
1726                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1727                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1728                         goto reset_slave;
1729
1730                 mutex_lock(&priv->cmd.slave_cmd_mutex);
1731                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1732                         mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1733                                  " resetting slave.\n", slave);
1734                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1735                         goto reset_slave;
1736                 }
1737                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1738                 break;
1739         default:
1740                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1741                 goto reset_slave;
1742         }
1743         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1744         if (!slave_state[slave].is_slave_going_down)
1745                 slave_state[slave].last_cmd = cmd;
1746         else
1747                 is_going_down = 1;
1748         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1749         if (is_going_down) {
1750                 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1751                           " executing from slave:%d\n",
1752                           cmd, slave);
1753                 return;
1754         }
1755         __raw_writel((__force u32) cpu_to_be32(reply),
1756                      &priv->mfunc.comm[slave].slave_read);
1757         mmiowb();
1758
1759         return;
1760
1761 reset_slave:
1762         /* cleanup any slave resources */
1763         mlx4_delete_all_resources_for_slave(dev, slave);
1764         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1765         if (!slave_state[slave].is_slave_going_down)
1766                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1767         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1768         /*with slave in the middle of flr, no need to clean resources again.*/
1769 inform_slave_state:
1770         memset(&slave_state[slave].event_eq, 0,
1771                sizeof(struct mlx4_slave_event_eq_info));
1772         __raw_writel((__force u32) cpu_to_be32(reply),
1773                      &priv->mfunc.comm[slave].slave_read);
1774         wmb();
1775 }
1776
1777 /* master command processing */
1778 void mlx4_master_comm_channel(struct work_struct *work)
1779 {
1780         struct mlx4_mfunc_master_ctx *master =
1781                 container_of(work,
1782                              struct mlx4_mfunc_master_ctx,
1783                              comm_work);
1784         struct mlx4_mfunc *mfunc =
1785                 container_of(master, struct mlx4_mfunc, master);
1786         struct mlx4_priv *priv =
1787                 container_of(mfunc, struct mlx4_priv, mfunc);
1788         struct mlx4_dev *dev = &priv->dev;
1789         __be32 *bit_vec;
1790         u32 comm_cmd;
1791         u32 vec;
1792         int i, j, slave;
1793         int toggle;
1794         int served = 0;
1795         int reported = 0;
1796         u32 slt;
1797
1798         bit_vec = master->comm_arm_bit_vector;
1799         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1800                 vec = be32_to_cpu(bit_vec[i]);
1801                 for (j = 0; j < 32; j++) {
1802                         if (!(vec & (1 << j)))
1803                                 continue;
1804                         ++reported;
1805                         slave = (i * 32) + j;
1806                         comm_cmd = swab32(readl(
1807                                           &mfunc->comm[slave].slave_write));
1808                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
1809                                      >> 31;
1810                         toggle = comm_cmd >> 31;
1811                         if (toggle != slt) {
1812                                 if (master->slave_state[slave].comm_toggle
1813                                     != slt) {
1814                                         printk(KERN_INFO "slave %d out of sync."
1815                                                " read toggle %d, state toggle %d. "
1816                                                "Resynching.\n", slave, slt,
1817                                                master->slave_state[slave].comm_toggle);
1818                                         master->slave_state[slave].comm_toggle =
1819                                                 slt;
1820                                 }
1821                                 mlx4_master_do_cmd(dev, slave,
1822                                                    comm_cmd >> 16 & 0xff,
1823                                                    comm_cmd & 0xffff, toggle);
1824                                 ++served;
1825                         }
1826                 }
1827         }
1828
1829         if (reported && reported != served)
1830                 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1831                           " but %d were served\n",
1832                           reported, served);
1833
1834         if (mlx4_ARM_COMM_CHANNEL(dev))
1835                 mlx4_warn(dev, "Failed to arm comm channel events\n");
1836 }
1837
1838 static int sync_toggles(struct mlx4_dev *dev)
1839 {
1840         struct mlx4_priv *priv = mlx4_priv(dev);
1841         int wr_toggle;
1842         int rd_toggle;
1843         unsigned long end;
1844
1845         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1846         end = jiffies + msecs_to_jiffies(5000);
1847
1848         while (time_before(jiffies, end)) {
1849                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1850                 if (rd_toggle == wr_toggle) {
1851                         priv->cmd.comm_toggle = rd_toggle;
1852                         return 0;
1853                 }
1854
1855                 cond_resched();
1856         }
1857
1858         /*
1859          * we could reach here if for example the previous VM using this
1860          * function misbehaved and left the channel with unsynced state. We
1861          * should fix this here and give this VM a chance to use a properly
1862          * synced channel
1863          */
1864         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1865         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1866         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1867         priv->cmd.comm_toggle = 0;
1868
1869         return 0;
1870 }
1871
1872 int mlx4_multi_func_init(struct mlx4_dev *dev)
1873 {
1874         struct mlx4_priv *priv = mlx4_priv(dev);
1875         struct mlx4_slave_state *s_state;
1876         int i, j, err, port;
1877
1878         if (mlx4_is_master(dev))
1879                 priv->mfunc.comm =
1880                 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1881                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1882         else
1883                 priv->mfunc.comm =
1884                 ioremap(pci_resource_start(dev->pdev, 2) +
1885                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1886         if (!priv->mfunc.comm) {
1887                 mlx4_err(dev, "Couldn't map communication vector.\n");
1888                 goto err_vhcr;
1889         }
1890
1891         if (mlx4_is_master(dev)) {
1892                 priv->mfunc.master.slave_state =
1893                         kzalloc(dev->num_slaves *
1894                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1895                 if (!priv->mfunc.master.slave_state)
1896                         goto err_comm;
1897
1898                 priv->mfunc.master.vf_admin =
1899                         kzalloc(dev->num_slaves *
1900                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1901                 if (!priv->mfunc.master.vf_admin)
1902                         goto err_comm_admin;
1903
1904                 priv->mfunc.master.vf_oper =
1905                         kzalloc(dev->num_slaves *
1906                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1907                 if (!priv->mfunc.master.vf_oper)
1908                         goto err_comm_oper;
1909
1910                 for (i = 0; i < dev->num_slaves; ++i) {
1911                         s_state = &priv->mfunc.master.slave_state[i];
1912                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
1913                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1914                                 s_state->event_eq[j].eqn = -1;
1915                         __raw_writel((__force u32) 0,
1916                                      &priv->mfunc.comm[i].slave_write);
1917                         __raw_writel((__force u32) 0,
1918                                      &priv->mfunc.comm[i].slave_read);
1919                         mmiowb();
1920                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1921                                 s_state->vlan_filter[port] =
1922                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
1923                                                 GFP_KERNEL);
1924                                 if (!s_state->vlan_filter[port]) {
1925                                         if (--port)
1926                                                 kfree(s_state->vlan_filter[port]);
1927                                         goto err_slaves;
1928                                 }
1929                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1930                                 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
1931                                 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
1932                                 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1933                                 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
1934                         }
1935                         spin_lock_init(&s_state->lock);
1936                 }
1937
1938                 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1939                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1940                 INIT_WORK(&priv->mfunc.master.comm_work,
1941                           mlx4_master_comm_channel);
1942                 INIT_WORK(&priv->mfunc.master.slave_event_work,
1943                           mlx4_gen_slave_eqe);
1944                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1945                           mlx4_master_handle_slave_flr);
1946                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1947                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1948                 priv->mfunc.master.comm_wq =
1949                         create_singlethread_workqueue("mlx4_comm");
1950                 if (!priv->mfunc.master.comm_wq)
1951                         goto err_slaves;
1952
1953                 if (mlx4_init_resource_tracker(dev))
1954                         goto err_thread;
1955
1956                 err = mlx4_ARM_COMM_CHANNEL(dev);
1957                 if (err) {
1958                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1959                                  err);
1960                         goto err_resource;
1961                 }
1962
1963         } else {
1964                 err = sync_toggles(dev);
1965                 if (err) {
1966                         mlx4_err(dev, "Couldn't sync toggles\n");
1967                         goto err_comm;
1968                 }
1969         }
1970         return 0;
1971
1972 err_resource:
1973         mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1974 err_thread:
1975         flush_workqueue(priv->mfunc.master.comm_wq);
1976         destroy_workqueue(priv->mfunc.master.comm_wq);
1977 err_slaves:
1978         while (--i) {
1979                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1980                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1981         }
1982         kfree(priv->mfunc.master.vf_oper);
1983 err_comm_oper:
1984         kfree(priv->mfunc.master.vf_admin);
1985 err_comm_admin:
1986         kfree(priv->mfunc.master.slave_state);
1987 err_comm:
1988         iounmap(priv->mfunc.comm);
1989 err_vhcr:
1990         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1991                                              priv->mfunc.vhcr,
1992                                              priv->mfunc.vhcr_dma);
1993         priv->mfunc.vhcr = NULL;
1994         return -ENOMEM;
1995 }
1996
1997 int mlx4_cmd_init(struct mlx4_dev *dev)
1998 {
1999         struct mlx4_priv *priv = mlx4_priv(dev);
2000
2001         mutex_init(&priv->cmd.hcr_mutex);
2002         mutex_init(&priv->cmd.slave_cmd_mutex);
2003         sema_init(&priv->cmd.poll_sem, 1);
2004         priv->cmd.use_events = 0;
2005         priv->cmd.toggle     = 1;
2006
2007         priv->cmd.hcr = NULL;
2008         priv->mfunc.vhcr = NULL;
2009
2010         if (!mlx4_is_slave(dev)) {
2011                 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2012                                         MLX4_HCR_BASE, MLX4_HCR_SIZE);
2013                 if (!priv->cmd.hcr) {
2014                         mlx4_err(dev, "Couldn't map command register.\n");
2015                         return -ENOMEM;
2016                 }
2017         }
2018
2019         if (mlx4_is_mfunc(dev)) {
2020                 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2021                                                       &priv->mfunc.vhcr_dma,
2022                                                       GFP_KERNEL);
2023                 if (!priv->mfunc.vhcr)
2024                         goto err_hcr;
2025         }
2026
2027         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2028                                          MLX4_MAILBOX_SIZE,
2029                                          MLX4_MAILBOX_SIZE, 0);
2030         if (!priv->cmd.pool)
2031                 goto err_vhcr;
2032
2033         return 0;
2034
2035 err_vhcr:
2036         if (mlx4_is_mfunc(dev))
2037                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2038                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2039         priv->mfunc.vhcr = NULL;
2040
2041 err_hcr:
2042         if (!mlx4_is_slave(dev))
2043                 iounmap(priv->cmd.hcr);
2044         return -ENOMEM;
2045 }
2046
2047 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2048 {
2049         struct mlx4_priv *priv = mlx4_priv(dev);
2050         int i, port;
2051
2052         if (mlx4_is_master(dev)) {
2053                 flush_workqueue(priv->mfunc.master.comm_wq);
2054                 destroy_workqueue(priv->mfunc.master.comm_wq);
2055                 for (i = 0; i < dev->num_slaves; i++) {
2056                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
2057                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2058                 }
2059                 kfree(priv->mfunc.master.slave_state);
2060                 kfree(priv->mfunc.master.vf_admin);
2061                 kfree(priv->mfunc.master.vf_oper);
2062         }
2063
2064         iounmap(priv->mfunc.comm);
2065 }
2066
2067 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2068 {
2069         struct mlx4_priv *priv = mlx4_priv(dev);
2070
2071         pci_pool_destroy(priv->cmd.pool);
2072
2073         if (!mlx4_is_slave(dev))
2074                 iounmap(priv->cmd.hcr);
2075         if (mlx4_is_mfunc(dev))
2076                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2077                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2078         priv->mfunc.vhcr = NULL;
2079 }
2080
2081 /*
2082  * Switch to using events to issue FW commands (can only be called
2083  * after event queue for command events has been initialized).
2084  */
2085 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2086 {
2087         struct mlx4_priv *priv = mlx4_priv(dev);
2088         int i;
2089         int err = 0;
2090
2091         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2092                                    sizeof (struct mlx4_cmd_context),
2093                                    GFP_KERNEL);
2094         if (!priv->cmd.context)
2095                 return -ENOMEM;
2096
2097         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2098                 priv->cmd.context[i].token = i;
2099                 priv->cmd.context[i].next  = i + 1;
2100         }
2101
2102         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2103         priv->cmd.free_head = 0;
2104
2105         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2106         spin_lock_init(&priv->cmd.context_lock);
2107
2108         for (priv->cmd.token_mask = 1;
2109              priv->cmd.token_mask < priv->cmd.max_cmds;
2110              priv->cmd.token_mask <<= 1)
2111                 ; /* nothing */
2112         --priv->cmd.token_mask;
2113
2114         down(&priv->cmd.poll_sem);
2115         priv->cmd.use_events = 1;
2116
2117         return err;
2118 }
2119
2120 /*
2121  * Switch back to polling (used when shutting down the device)
2122  */
2123 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2124 {
2125         struct mlx4_priv *priv = mlx4_priv(dev);
2126         int i;
2127
2128         priv->cmd.use_events = 0;
2129
2130         for (i = 0; i < priv->cmd.max_cmds; ++i)
2131                 down(&priv->cmd.event_sem);
2132
2133         kfree(priv->cmd.context);
2134
2135         up(&priv->cmd.poll_sem);
2136 }
2137
2138 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2139 {
2140         struct mlx4_cmd_mailbox *mailbox;
2141
2142         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2143         if (!mailbox)
2144                 return ERR_PTR(-ENOMEM);
2145
2146         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2147                                       &mailbox->dma);
2148         if (!mailbox->buf) {
2149                 kfree(mailbox);
2150                 return ERR_PTR(-ENOMEM);
2151         }
2152
2153         return mailbox;
2154 }
2155 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2156
2157 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2158                            struct mlx4_cmd_mailbox *mailbox)
2159 {
2160         if (!mailbox)
2161                 return;
2162
2163         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2164         kfree(mailbox);
2165 }
2166 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2167
2168 u32 mlx4_comm_get_version(void)
2169 {
2170          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2171 }
2172
2173 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2174 {
2175         if ((vf < 0) || (vf >= dev->num_vfs)) {
2176                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2177                 return -EINVAL;
2178         }
2179
2180         return vf+1;
2181 }
2182
2183 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2184 {
2185         struct mlx4_priv *priv = mlx4_priv(dev);
2186         struct mlx4_vport_state *s_info;
2187         int slave;
2188
2189         if (!mlx4_is_master(dev))
2190                 return -EPROTONOSUPPORT;
2191
2192         slave = mlx4_get_slave_indx(dev, vf);
2193         if (slave < 0)
2194                 return -EINVAL;
2195
2196         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2197         s_info->mac = mac;
2198         mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2199                   vf, port, s_info->mac);
2200         return 0;
2201 }
2202 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2203
2204 static int calculate_transition(u16 oper_vlan, u16 admin_vlan)
2205 {
2206         return (2 * (oper_vlan == MLX4_VGT) + (admin_vlan == MLX4_VGT));
2207 }
2208
2209 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2210 {
2211         struct mlx4_priv *priv = mlx4_priv(dev);
2212         struct mlx4_vport_oper_state *vf_oper;
2213         struct mlx4_vport_state *vf_admin;
2214         int slave;
2215         enum mlx4_vlan_transition vlan_trans;
2216
2217         if ((!mlx4_is_master(dev)) ||
2218             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2219                 return -EPROTONOSUPPORT;
2220
2221         if ((vlan > 4095) || (qos > 7))
2222                 return -EINVAL;
2223
2224         slave = mlx4_get_slave_indx(dev, vf);
2225         if (slave < 0)
2226                 return -EINVAL;
2227
2228         vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2229         vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2230
2231         if ((0 == vlan) && (0 == qos))
2232                 vf_admin->default_vlan = MLX4_VGT;
2233         else
2234                 vf_admin->default_vlan = vlan;
2235         vf_admin->default_qos = qos;
2236
2237         vlan_trans = calculate_transition(vf_oper->state.default_vlan,
2238                                           vf_admin->default_vlan);
2239
2240         if (priv->mfunc.master.slave_state[slave].active &&
2241             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP &&
2242             vlan_trans == MLX4_VLAN_TRANSITION_VST_VST) {
2243                 mlx4_info(dev, "updating vf %d port %d config params immediately\n",
2244                           vf, port);
2245                 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
2246         }
2247         return 0;
2248 }
2249 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2250
2251 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2252 {
2253         struct mlx4_priv *priv = mlx4_priv(dev);
2254         struct mlx4_vport_state *s_info;
2255         int slave;
2256
2257         if ((!mlx4_is_master(dev)) ||
2258             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2259                 return -EPROTONOSUPPORT;
2260
2261         slave = mlx4_get_slave_indx(dev, vf);
2262         if (slave < 0)
2263                 return -EINVAL;
2264
2265         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2266         s_info->spoofchk = setting;
2267
2268         return 0;
2269 }
2270 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2271
2272 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2273 {
2274         struct mlx4_priv *priv = mlx4_priv(dev);
2275         struct mlx4_vport_state *s_info;
2276         int slave;
2277
2278         if (!mlx4_is_master(dev))
2279                 return -EPROTONOSUPPORT;
2280
2281         slave = mlx4_get_slave_indx(dev, vf);
2282         if (slave < 0)
2283                 return -EINVAL;
2284
2285         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2286         ivf->vf = vf;
2287
2288         /* need to convert it to a func */
2289         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2290         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2291         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2292         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2293         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2294         ivf->mac[5] = ((s_info->mac)  & 0xff);
2295
2296         ivf->vlan       = s_info->default_vlan;
2297         ivf->qos        = s_info->default_qos;
2298         ivf->tx_rate    = s_info->tx_rate;
2299         ivf->spoofchk   = s_info->spoofchk;
2300         ivf->linkstate  = s_info->link_state;
2301
2302         return 0;
2303 }
2304 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2305
2306 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2307 {
2308         struct mlx4_priv *priv = mlx4_priv(dev);
2309         struct mlx4_vport_state *s_info;
2310         struct mlx4_vport_oper_state *vp_oper;
2311         int slave;
2312         u8 link_stat_event;
2313
2314         slave = mlx4_get_slave_indx(dev, vf);
2315         if (slave < 0)
2316                 return -EINVAL;
2317
2318         switch (link_state) {
2319         case IFLA_VF_LINK_STATE_AUTO:
2320                 /* get current link state */
2321                 if (!priv->sense.do_sense_port[port])
2322                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2323                 else
2324                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2325             break;
2326
2327         case IFLA_VF_LINK_STATE_ENABLE:
2328                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2329             break;
2330
2331         case IFLA_VF_LINK_STATE_DISABLE:
2332                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2333             break;
2334
2335         default:
2336                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2337                           link_state, slave, port);
2338                 return -EINVAL;
2339         };
2340         /* update the admin & oper state on the link state */
2341         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2342         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2343         s_info->link_state = link_state;
2344         vp_oper->state.link_state = link_state;
2345
2346         /* send event */
2347         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2348         return 0;
2349 }
2350 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);