drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/semaphore.h>
  43 #include <rdma/ib_smi.h>
  44
  45 #include <asm/io.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49
  50 #define CMD_POLL_TOKEN 0xffff
  51 #define INBOX_MASK      0xffffffffffffff00ULL
  52
  53 #define CMD_CHAN_VER 1
  54 #define CMD_CHAN_IF_REV 1
  55
  56 enum {
  57         /* command completed successfully: */
  58         CMD_STAT_OK             = 0x00,
  59         /* Internal error (such as a bus error) occurred while processing command: */
  60         CMD_STAT_INTERNAL_ERR   = 0x01,
  61         /* Operation/command not supported or opcode modifier not supported: */
  62         CMD_STAT_BAD_OP         = 0x02,
  63         /* Parameter not supported or parameter out of range: */
  64         CMD_STAT_BAD_PARAM      = 0x03,
  65         /* System not enabled or bad system state: */
  66         CMD_STAT_BAD_SYS_STATE  = 0x04,
  67         /* Attempt to access reserved or unallocaterd resource: */
  68         CMD_STAT_BAD_RESOURCE   = 0x05,
  69         /* Requested resource is currently executing a command, or is otherwise busy: */
  70         CMD_STAT_RESOURCE_BUSY  = 0x06,
  71         /* Required capability exceeds device limits: */
  72         CMD_STAT_EXCEED_LIM     = 0x08,
  73         /* Resource is not in the appropriate state or ownership: */
  74         CMD_STAT_BAD_RES_STATE  = 0x09,
  75         /* Index out of range: */
  76         CMD_STAT_BAD_INDEX      = 0x0a,
  77         /* FW image corrupted: */
  78         CMD_STAT_BAD_NVMEM      = 0x0b,
  79         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  80         CMD_STAT_ICM_ERROR      = 0x0c,
  81         /* Attempt to modify a QP/EE which is not in the presumed state: */
  82         CMD_STAT_BAD_QP_STATE   = 0x10,
  83         /* Bad segment parameters (Address/Size): */
  84         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  85         /* Memory Region has Memory Windows bound to: */
  86         CMD_STAT_REG_BOUND      = 0x21,
  87         /* HCA local attached memory not present: */
  88         CMD_STAT_LAM_NOT_PRE    = 0x22,
  89         /* Bad management packet (silently discarded): */
  90         CMD_STAT_BAD_PKT        = 0x30,
  91         /* More outstanding CQEs in CQ than new CQ size: */
  92         CMD_STAT_BAD_SIZE       = 0x40,
  93         /* Multi Function device support required: */
  94         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  95 };
  96
  97 enum {
  98         HCR_IN_PARAM_OFFSET     = 0x00,
  99         HCR_IN_MODIFIER_OFFSET  = 0x08,
 100         HCR_OUT_PARAM_OFFSET    = 0x0c,
 101         HCR_TOKEN_OFFSET        = 0x14,
 102         HCR_STATUS_OFFSET       = 0x18,
 103
 104         HCR_OPMOD_SHIFT         = 12,
 105         HCR_T_BIT               = 21,
 106         HCR_E_BIT               = 22,
 107         HCR_GO_BIT              = 23
 108 };
 109
 110 enum {
 111         GO_BIT_TIMEOUT_MSECS    = 10000
 112 };
 113
 114 struct mlx4_cmd_context {
 115         struct completion       done;
 116         int                     result;
 117         int                     next;
 118         u64                     out_param;
 119         u16                     token;
 120         u8                      fw_status;
 121 };
 122
 123 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 124                                     struct mlx4_vhcr_cmd *in_vhcr);
 125
 126 static int mlx4_status_to_errno(u8 status)
 127 {
 128         static const int trans_table[] = {
 129                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 130                 [CMD_STAT_BAD_OP]         = -EPERM,
 131                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 132                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 133                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 134                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 135                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 136                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 137                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 138                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 139                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 140                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 141                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 142                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 143                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 144                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 145                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 146                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 147         };
 148
 149         if (status >= ARRAY_SIZE(trans_table) ||
 150             (status != CMD_STAT_OK && trans_table[status] == 0))
 151                 return -EIO;
 152
 153         return trans_table[status];
 154 }
 155
 156 static u8 mlx4_errno_to_status(int errno)
 157 {
 158         switch (errno) {
 159         case -EPERM:
 160                 return CMD_STAT_BAD_OP;
 161         case -EINVAL:
 162                 return CMD_STAT_BAD_PARAM;
 163         case -ENXIO:
 164                 return CMD_STAT_BAD_SYS_STATE;
 165         case -EBUSY:
 166                 return CMD_STAT_RESOURCE_BUSY;
 167         case -ENOMEM:
 168                 return CMD_STAT_EXCEED_LIM;
 169         case -ENFILE:
 170                 return CMD_STAT_ICM_ERROR;
 171         default:
 172                 return CMD_STAT_INTERNAL_ERR;
 173         }
 174 }
 175
 176 static int comm_pending(struct mlx4_dev *dev)
 177 {
 178         struct mlx4_priv *priv = mlx4_priv(dev);
 179         u32 status = readl(&priv->mfunc.comm->slave_read);
 180
 181         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 182 }
 183
 184 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 185 {
 186         struct mlx4_priv *priv = mlx4_priv(dev);
 187         u32 val;
 188
 189         priv->cmd.comm_toggle ^= 1;
 190         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 191         __raw_writel((__force u32) cpu_to_be32(val),
 192                      &priv->mfunc.comm->slave_write);
 193         mmiowb();
 194 }
 195
 196 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 197                        unsigned long timeout)
 198 {
 199         struct mlx4_priv *priv = mlx4_priv(dev);
 200         unsigned long end;
 201         int err = 0;
 202         int ret_from_pending = 0;
 203
 204         /* First, verify that the master reports correct status */
 205         if (comm_pending(dev)) {
 206                 mlx4_warn(dev, "Communication channel is not idle."
 207                           "my toggle is %d (cmd:0x%x)\n",
 208                           priv->cmd.comm_toggle, cmd);
 209                 return -EAGAIN;
 210         }
 211
 212         /* Write command */
 213         down(&priv->cmd.poll_sem);
 214         mlx4_comm_cmd_post(dev, cmd, param);
 215
 216         end = msecs_to_jiffies(timeout) + jiffies;
 217         while (comm_pending(dev) && time_before(jiffies, end))
 218                 cond_resched();
 219         ret_from_pending = comm_pending(dev);
 220         if (ret_from_pending) {
 221                 /* check if the slave is trying to boot in the middle of
 222                  * FLR process. The only non-zero result in the RESET command
 223                  * is MLX4_DELAY_RESET_SLAVE*/
 224                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 225                         mlx4_warn(dev, "Got slave FLRed from Communication"
 226                                   " channel (ret:0x%x)\n", ret_from_pending);
 227                         err = MLX4_DELAY_RESET_SLAVE;
 228                 } else {
 229                         mlx4_warn(dev, "Communication channel timed out\n");
 230                         err = -ETIMEDOUT;
 231                 }
 232         }
 233
 234         up(&priv->cmd.poll_sem);
 235         return err;
 236 }
 237
 238 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
 239                               u16 param, unsigned long timeout)
 240 {
 241         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 242         struct mlx4_cmd_context *context;
 243         unsigned long end;
 244         int err = 0;
 245
 246         down(&cmd->event_sem);
 247
 248         spin_lock(&cmd->context_lock);
 249         BUG_ON(cmd->free_head < 0);
 250         context = &cmd->context[cmd->free_head];
 251         context->token += cmd->token_mask + 1;
 252         cmd->free_head = context->next;
 253         spin_unlock(&cmd->context_lock);
 254
 255         init_completion(&context->done);
 256
 257         mlx4_comm_cmd_post(dev, op, param);
 258
 259         if (!wait_for_completion_timeout(&context->done,
 260                                          msecs_to_jiffies(timeout))) {
 261                 err = -EBUSY;
 262                 goto out;
 263         }
 264
 265         err = context->result;
 266         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 267                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 268                          op, context->fw_status);
 269                 goto out;
 270         }
 271
 272 out:
 273         /* wait for comm channel ready
 274          * this is necessary for prevention the race
 275          * when switching between event to polling mode
 276          */
 277         end = msecs_to_jiffies(timeout) + jiffies;
 278         while (comm_pending(dev) && time_before(jiffies, end))
 279                 cond_resched();
 280
 281         spin_lock(&cmd->context_lock);
 282         context->next = cmd->free_head;
 283         cmd->free_head = context - cmd->context;
 284         spin_unlock(&cmd->context_lock);
 285
 286         up(&cmd->event_sem);
 287         return err;
 288 }
 289
 290 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 291                   unsigned long timeout)
 292 {
 293         if (mlx4_priv(dev)->cmd.use_events)
 294                 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
 295         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 296 }
 297
 298 static int cmd_pending(struct mlx4_dev *dev)
 299 {
 300         u32 status;
 301
 302         if (pci_channel_offline(dev->pdev))
 303                 return -EIO;
 304
 305         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 306
 307         return (status & swab32(1 << HCR_GO_BIT)) ||
 308                 (mlx4_priv(dev)->cmd.toggle ==
 309                  !!(status & swab32(1 << HCR_T_BIT)));
 310 }
 311
 312 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 313                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 314                          int event)
 315 {
 316         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 317         u32 __iomem *hcr = cmd->hcr;
 318         int ret = -EAGAIN;
 319         unsigned long end;
 320
 321         mutex_lock(&cmd->hcr_mutex);
 322
 323         if (pci_channel_offline(dev->pdev)) {
 324                 /*
 325                  * Device is going through error recovery
 326                  * and cannot accept commands.
 327                  */
 328                 ret = -EIO;
 329                 goto out;
 330         }
 331
 332         end = jiffies;
 333         if (event)
 334                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 335
 336         while (cmd_pending(dev)) {
 337                 if (pci_channel_offline(dev->pdev)) {
 338                         /*
 339                          * Device is going through error recovery
 340                          * and cannot accept commands.
 341                          */
 342                         ret = -EIO;
 343                         goto out;
 344                 }
 345
 346                 if (time_after_eq(jiffies, end)) {
 347                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 348                         goto out;
 349                 }
 350                 cond_resched();
 351         }
 352
 353         /*
 354          * We use writel (instead of something like memcpy_toio)
 355          * because writes of less than 32 bits to the HCR don't work
 356          * (and some architectures such as ia64 implement memcpy_toio
 357          * in terms of writeb).
 358          */
 359         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 360         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 361         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 362         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 363         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 364         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 365
 366         /* __raw_writel may not order writes. */
 367         wmb();
 368
 369         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 370                                                (cmd->toggle << HCR_T_BIT)       |
 371                                                (event ? (1 << HCR_E_BIT) : 0)   |
 372                                                (op_modifier << HCR_OPMOD_SHIFT) |
 373                                                op), hcr + 6);
 374
 375         /*
 376          * Make sure that our HCR writes don't get mixed in with
 377          * writes from another CPU starting a FW command.
 378          */
 379         mmiowb();
 380
 381         cmd->toggle = cmd->toggle ^ 1;
 382
 383         ret = 0;
 384
 385 out:
 386         mutex_unlock(&cmd->hcr_mutex);
 387         return ret;
 388 }
 389
 390 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 391                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 392                           u16 op, unsigned long timeout)
 393 {
 394         struct mlx4_priv *priv = mlx4_priv(dev);
 395         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 396         int ret;
 397
 398         down(&priv->cmd.slave_sem);
 399         vhcr->in_param = cpu_to_be64(in_param);
 400         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 401         vhcr->in_modifier = cpu_to_be32(in_modifier);
 402         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 403         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 404         vhcr->status = 0;
 405         vhcr->flags = !!(priv->cmd.use_events) << 6;
 406         if (mlx4_is_master(dev)) {
 407                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 408                 if (!ret) {
 409                         if (out_is_imm) {
 410                                 if (out_param)
 411                                         *out_param =
 412                                                 be64_to_cpu(vhcr->out_param);
 413                                 else {
 414                                         mlx4_err(dev, "response expected while"
 415                                                  "output mailbox is NULL for "
 416                                                  "command 0x%x\n", op);
 417                                         vhcr->status = CMD_STAT_BAD_PARAM;
 418                                 }
 419                         }
 420                         ret = mlx4_status_to_errno(vhcr->status);
 421                 }
 422         } else {
 423                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
 424                                     MLX4_COMM_TIME + timeout);
 425                 if (!ret) {
 426                         if (out_is_imm) {
 427                                 if (out_param)
 428                                         *out_param =
 429                                                 be64_to_cpu(vhcr->out_param);
 430                                 else {
 431                                         mlx4_err(dev, "response expected while"
 432                                                  "output mailbox is NULL for "
 433                                                  "command 0x%x\n", op);
 434                                         vhcr->status = CMD_STAT_BAD_PARAM;
 435                                 }
 436                         }
 437                         ret = mlx4_status_to_errno(vhcr->status);
 438                 } else
 439                         mlx4_err(dev, "failed execution of VHCR_POST command"
 440                                  "opcode 0x%x\n", op);
 441         }
 442         up(&priv->cmd.slave_sem);
 443         return ret;
 444 }
 445
 446 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 447                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 448                          u16 op, unsigned long timeout)
 449 {
 450         struct mlx4_priv *priv = mlx4_priv(dev);
 451         void __iomem *hcr = priv->cmd.hcr;
 452         int err = 0;
 453         unsigned long end;
 454         u32 stat;
 455
 456         down(&priv->cmd.poll_sem);
 457
 458         if (pci_channel_offline(dev->pdev)) {
 459                 /*
 460                  * Device is going through error recovery
 461                  * and cannot accept commands.
 462                  */
 463                 err = -EIO;
 464                 goto out;
 465         }
 466
 467         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 468                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 469         if (err)
 470                 goto out;
 471
 472         end = msecs_to_jiffies(timeout) + jiffies;
 473         while (cmd_pending(dev) && time_before(jiffies, end)) {
 474                 if (pci_channel_offline(dev->pdev)) {
 475                         /*
 476                          * Device is going through error recovery
 477                          * and cannot accept commands.
 478                          */
 479                         err = -EIO;
 480                         goto out;
 481                 }
 482
 483                 cond_resched();
 484         }
 485
 486         if (cmd_pending(dev)) {
 487                 err = -ETIMEDOUT;
 488                 goto out;
 489         }
 490
 491         if (out_is_imm)
 492                 *out_param =
 493                         (u64) be32_to_cpu((__force __be32)
 494                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 495                         (u64) be32_to_cpu((__force __be32)
 496                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 497         stat = be32_to_cpu((__force __be32)
 498                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 499         err = mlx4_status_to_errno(stat);
 500         if (err)
 501                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 502                          op, stat);
 503
 504 out:
 505         up(&priv->cmd.poll_sem);
 506         return err;
 507 }
 508
 509 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 510 {
 511         struct mlx4_priv *priv = mlx4_priv(dev);
 512         struct mlx4_cmd_context *context =
 513                 &priv->cmd.context[token & priv->cmd.token_mask];
 514
 515         /* previously timed out command completing at long last */
 516         if (token != context->token)
 517                 return;
 518
 519         context->fw_status = status;
 520         context->result    = mlx4_status_to_errno(status);
 521         context->out_param = out_param;
 522
 523         complete(&context->done);
 524 }
 525
 526 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 527                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 528                          u16 op, unsigned long timeout)
 529 {
 530         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 531         struct mlx4_cmd_context *context;
 532         int err = 0;
 533
 534         down(&cmd->event_sem);
 535
 536         spin_lock(&cmd->context_lock);
 537         BUG_ON(cmd->free_head < 0);
 538         context = &cmd->context[cmd->free_head];
 539         context->token += cmd->token_mask + 1;
 540         cmd->free_head = context->next;
 541         spin_unlock(&cmd->context_lock);
 542
 543         init_completion(&context->done);
 544
 545         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 546                       in_modifier, op_modifier, op, context->token, 1);
 547
 548         if (!wait_for_completion_timeout(&context->done,
 549                                          msecs_to_jiffies(timeout))) {
 550                 err = -EBUSY;
 551                 goto out;
 552         }
 553
 554         err = context->result;
 555         if (err) {
 556                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 557                          op, context->fw_status);
 558                 goto out;
 559         }
 560
 561         if (out_is_imm)
 562                 *out_param = context->out_param;
 563
 564 out:
 565         spin_lock(&cmd->context_lock);
 566         context->next = cmd->free_head;
 567         cmd->free_head = context - cmd->context;
 568         spin_unlock(&cmd->context_lock);
 569
 570         up(&cmd->event_sem);
 571         return err;
 572 }
 573
 574 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 575                int out_is_imm, u32 in_modifier, u8 op_modifier,
 576                u16 op, unsigned long timeout, int native)
 577 {
 578         if (pci_channel_offline(dev->pdev))
 579                 return -EIO;
 580
 581         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 582                 if (mlx4_priv(dev)->cmd.use_events)
 583                         return mlx4_cmd_wait(dev, in_param, out_param,
 584                                              out_is_imm, in_modifier,
 585                                              op_modifier, op, timeout);
 586                 else
 587                         return mlx4_cmd_poll(dev, in_param, out_param,
 588                                              out_is_imm, in_modifier,
 589                                              op_modifier, op, timeout);
 590         }
 591         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 592                               in_modifier, op_modifier, op, timeout);
 593 }
 594 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 595
 596
 597 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 598 {
 599         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 600                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 601 }
 602
 603 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 604                            int slave, u64 slave_addr,
 605                            int size, int is_read)
 606 {
 607         u64 in_param;
 608         u64 out_param;
 609
 610         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 611             (slave & ~0x7f) | (size & 0xff)) {
 612                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
 613                               "master_addr:0x%llx slave_id:%d size:%d\n",
 614                               slave_addr, master_addr, slave, size);
 615                 return -EINVAL;
 616         }
 617
 618         if (is_read) {
 619                 in_param = (u64) slave | slave_addr;
 620                 out_param = (u64) dev->caps.function | master_addr;
 621         } else {
 622                 in_param = (u64) dev->caps.function | master_addr;
 623                 out_param = (u64) slave | slave_addr;
 624         }
 625
 626         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 627                             MLX4_CMD_ACCESS_MEM,
 628                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 629 }
 630
 631 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 632                                struct mlx4_cmd_mailbox *inbox,
 633                                struct mlx4_cmd_mailbox *outbox)
 634 {
 635         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 636         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 637         int err;
 638         int i;
 639
 640         if (index & 0x1f)
 641                 return -EINVAL;
 642
 643         in_mad->attr_mod = cpu_to_be32(index / 32);
 644
 645         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 646                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 647                            MLX4_CMD_NATIVE);
 648         if (err)
 649                 return err;
 650
 651         for (i = 0; i < 32; ++i)
 652                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 653
 654         return err;
 655 }
 656
 657 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 658                                struct mlx4_cmd_mailbox *inbox,
 659                                struct mlx4_cmd_mailbox *outbox)
 660 {
 661         int i;
 662         int err;
 663
 664         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 665                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 666                 if (err)
 667                         return err;
 668         }
 669
 670         return 0;
 671 }
 672 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 673 #define PORT_STATE_OFFSET 32
 674
 675 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 676 {
 677         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 678                 return IB_PORT_ACTIVE;
 679         else
 680                 return IB_PORT_DOWN;
 681 }
 682
 683 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 684                                 struct mlx4_vhcr *vhcr,
 685                                 struct mlx4_cmd_mailbox *inbox,
 686                                 struct mlx4_cmd_mailbox *outbox,
 687                                 struct mlx4_cmd_info *cmd)
 688 {
 689         struct ib_smp *smp = inbox->buf;
 690         u32 index;
 691         u8 port;
 692         u16 *table;
 693         int err;
 694         int vidx, pidx;
 695         struct mlx4_priv *priv = mlx4_priv(dev);
 696         struct ib_smp *outsmp = outbox->buf;
 697         __be16 *outtab = (__be16 *)(outsmp->data);
 698         __be32 slave_cap_mask;
 699         __be64 slave_node_guid;
 700         port = vhcr->in_modifier;
 701
 702         if (smp->base_version == 1 &&
 703             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 704             smp->class_version == 1) {
 705                 if (smp->method == IB_MGMT_METHOD_GET) {
 706                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 707                                 index = be32_to_cpu(smp->attr_mod);
 708                                 if (port < 1 || port > dev->caps.num_ports)
 709                                         return -EINVAL;
 710                                 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
 711                                 if (!table)
 712                                         return -ENOMEM;
 713                                 /* need to get the full pkey table because the paravirtualized
 714                                  * pkeys may be scattered among several pkey blocks.
 715                                  */
 716                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 717                                 if (!err) {
 718                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 719                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 720                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 721                                         }
 722                                 }
 723                                 kfree(table);
 724                                 return err;
 725                         }
 726                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 727                                 /*get the slave specific caps:*/
 728                                 /*do the command */
 729                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 730                                             vhcr->in_modifier, vhcr->op_modifier,
 731                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 732                                 /* modify the response for slaves */
 733                                 if (!err && slave != mlx4_master_func_num(dev)) {
 734                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 735
 736                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 737                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 738                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 739                                 }
 740                                 return err;
 741                         }
 742                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 743                                 /* compute slave's gid block */
 744                                 smp->attr_mod = cpu_to_be32(slave / 8);
 745                                 /* execute cmd */
 746                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 747                                              vhcr->in_modifier, vhcr->op_modifier,
 748                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 749                                 if (!err) {
 750                                         /* if needed, move slave gid to index 0 */
 751                                         if (slave % 8)
 752                                                 memcpy(outsmp->data,
 753                                                        outsmp->data + (slave % 8) * 8, 8);
 754                                         /* delete all other gids */
 755                                         memset(outsmp->data + 8, 0, 56);
 756                                 }
 757                                 return err;
 758                         }
 759                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 760                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 761                                              vhcr->in_modifier, vhcr->op_modifier,
 762                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 763                                 if (!err) {
 764                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 765                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 766                                 }
 767                                 return err;
 768                         }
 769                 }
 770         }
 771         if (slave != mlx4_master_func_num(dev) &&
 772             ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
 773              (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 774               smp->method == IB_MGMT_METHOD_SET))) {
 775                 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
 776                          "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
 777                          slave, smp->method, smp->mgmt_class,
 778                          be16_to_cpu(smp->attr_id));
 779                 return -EPERM;
 780         }
 781         /*default:*/
 782         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 783                                     vhcr->in_modifier, vhcr->op_modifier,
 784                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 785 }
 786
 787 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 788                      struct mlx4_vhcr *vhcr,
 789                      struct mlx4_cmd_mailbox *inbox,
 790                      struct mlx4_cmd_mailbox *outbox,
 791                      struct mlx4_cmd_info *cmd)
 792 {
 793         u64 in_param;
 794         u64 out_param;
 795         int err;
 796
 797         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
 798         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
 799         if (cmd->encode_slave_id) {
 800                 in_param &= 0xffffffffffffff00ll;
 801                 in_param |= slave;
 802         }
 803
 804         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
 805                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
 806                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 807
 808         if (cmd->out_is_imm)
 809                 vhcr->out_param = out_param;
 810
 811         return err;
 812 }
 813
 814 static struct mlx4_cmd_info cmd_info[] = {
 815         {
 816                 .opcode = MLX4_CMD_QUERY_FW,
 817                 .has_inbox = false,
 818                 .has_outbox = true,
 819                 .out_is_imm = false,
 820                 .encode_slave_id = false,
 821                 .verify = NULL,
 822                 .wrapper = mlx4_QUERY_FW_wrapper
 823         },
 824         {
 825                 .opcode = MLX4_CMD_QUERY_HCA,
 826                 .has_inbox = false,
 827                 .has_outbox = true,
 828                 .out_is_imm = false,
 829                 .encode_slave_id = false,
 830                 .verify = NULL,
 831                 .wrapper = NULL
 832         },
 833         {
 834                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
 835                 .has_inbox = false,
 836                 .has_outbox = true,
 837                 .out_is_imm = false,
 838                 .encode_slave_id = false,
 839                 .verify = NULL,
 840                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
 841         },
 842         {
 843                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
 844                 .has_inbox = false,
 845                 .has_outbox = true,
 846                 .out_is_imm = false,
 847                 .encode_slave_id = false,
 848                 .verify = NULL,
 849                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
 850         },
 851         {
 852                 .opcode = MLX4_CMD_QUERY_ADAPTER,
 853                 .has_inbox = false,
 854                 .has_outbox = true,
 855                 .out_is_imm = false,
 856                 .encode_slave_id = false,
 857                 .verify = NULL,
 858                 .wrapper = NULL
 859         },
 860         {
 861                 .opcode = MLX4_CMD_INIT_PORT,
 862                 .has_inbox = false,
 863                 .has_outbox = false,
 864                 .out_is_imm = false,
 865                 .encode_slave_id = false,
 866                 .verify = NULL,
 867                 .wrapper = mlx4_INIT_PORT_wrapper
 868         },
 869         {
 870                 .opcode = MLX4_CMD_CLOSE_PORT,
 871                 .has_inbox = false,
 872                 .has_outbox = false,
 873                 .out_is_imm  = false,
 874                 .encode_slave_id = false,
 875                 .verify = NULL,
 876                 .wrapper = mlx4_CLOSE_PORT_wrapper
 877         },
 878         {
 879                 .opcode = MLX4_CMD_QUERY_PORT,
 880                 .has_inbox = false,
 881                 .has_outbox = true,
 882                 .out_is_imm = false,
 883                 .encode_slave_id = false,
 884                 .verify = NULL,
 885                 .wrapper = mlx4_QUERY_PORT_wrapper
 886         },
 887         {
 888                 .opcode = MLX4_CMD_SET_PORT,
 889                 .has_inbox = true,
 890                 .has_outbox = false,
 891                 .out_is_imm = false,
 892                 .encode_slave_id = false,
 893                 .verify = NULL,
 894                 .wrapper = mlx4_SET_PORT_wrapper
 895         },
 896         {
 897                 .opcode = MLX4_CMD_MAP_EQ,
 898                 .has_inbox = false,
 899                 .has_outbox = false,
 900                 .out_is_imm = false,
 901                 .encode_slave_id = false,
 902                 .verify = NULL,
 903                 .wrapper = mlx4_MAP_EQ_wrapper
 904         },
 905         {
 906                 .opcode = MLX4_CMD_SW2HW_EQ,
 907                 .has_inbox = true,
 908                 .has_outbox = false,
 909                 .out_is_imm = false,
 910                 .encode_slave_id = true,
 911                 .verify = NULL,
 912                 .wrapper = mlx4_SW2HW_EQ_wrapper
 913         },
 914         {
 915                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
 916                 .has_inbox = false,
 917                 .has_outbox = false,
 918                 .out_is_imm = false,
 919                 .encode_slave_id = false,
 920                 .verify = NULL,
 921                 .wrapper = NULL
 922         },
 923         {
 924                 .opcode = MLX4_CMD_NOP,
 925                 .has_inbox = false,
 926                 .has_outbox = false,
 927                 .out_is_imm = false,
 928                 .encode_slave_id = false,
 929                 .verify = NULL,
 930                 .wrapper = NULL
 931         },
 932         {
 933                 .opcode = MLX4_CMD_ALLOC_RES,
 934                 .has_inbox = false,
 935                 .has_outbox = false,
 936                 .out_is_imm = true,
 937                 .encode_slave_id = false,
 938                 .verify = NULL,
 939                 .wrapper = mlx4_ALLOC_RES_wrapper
 940         },
 941         {
 942                 .opcode = MLX4_CMD_FREE_RES,
 943                 .has_inbox = false,
 944                 .has_outbox = false,
 945                 .out_is_imm = false,
 946                 .encode_slave_id = false,
 947                 .verify = NULL,
 948                 .wrapper = mlx4_FREE_RES_wrapper
 949         },
 950         {
 951                 .opcode = MLX4_CMD_SW2HW_MPT,
 952                 .has_inbox = true,
 953                 .has_outbox = false,
 954                 .out_is_imm = false,
 955                 .encode_slave_id = true,
 956                 .verify = NULL,
 957                 .wrapper = mlx4_SW2HW_MPT_wrapper
 958         },
 959         {
 960                 .opcode = MLX4_CMD_QUERY_MPT,
 961                 .has_inbox = false,
 962                 .has_outbox = true,
 963                 .out_is_imm = false,
 964                 .encode_slave_id = false,
 965                 .verify = NULL,
 966                 .wrapper = mlx4_QUERY_MPT_wrapper
 967         },
 968         {
 969                 .opcode = MLX4_CMD_HW2SW_MPT,
 970                 .has_inbox = false,
 971                 .has_outbox = false,
 972                 .out_is_imm = false,
 973                 .encode_slave_id = false,
 974                 .verify = NULL,
 975                 .wrapper = mlx4_HW2SW_MPT_wrapper
 976         },
 977         {
 978                 .opcode = MLX4_CMD_READ_MTT,
 979                 .has_inbox = false,
 980                 .has_outbox = true,
 981                 .out_is_imm = false,
 982                 .encode_slave_id = false,
 983                 .verify = NULL,
 984                 .wrapper = NULL
 985         },
 986         {
 987                 .opcode = MLX4_CMD_WRITE_MTT,
 988                 .has_inbox = true,
 989                 .has_outbox = false,
 990                 .out_is_imm = false,
 991                 .encode_slave_id = false,
 992                 .verify = NULL,
 993                 .wrapper = mlx4_WRITE_MTT_wrapper
 994         },
 995         {
 996                 .opcode = MLX4_CMD_SYNC_TPT,
 997                 .has_inbox = true,
 998                 .has_outbox = false,
 999                 .out_is_imm = false,
1000                 .encode_slave_id = false,
1001                 .verify = NULL,
1002                 .wrapper = NULL
1003         },
1004         {
1005                 .opcode = MLX4_CMD_HW2SW_EQ,
1006                 .has_inbox = false,
1007                 .has_outbox = true,
1008                 .out_is_imm = false,
1009                 .encode_slave_id = true,
1010                 .verify = NULL,
1011                 .wrapper = mlx4_HW2SW_EQ_wrapper
1012         },
1013         {
1014                 .opcode = MLX4_CMD_QUERY_EQ,
1015                 .has_inbox = false,
1016                 .has_outbox = true,
1017                 .out_is_imm = false,
1018                 .encode_slave_id = true,
1019                 .verify = NULL,
1020                 .wrapper = mlx4_QUERY_EQ_wrapper
1021         },
1022         {
1023                 .opcode = MLX4_CMD_SW2HW_CQ,
1024                 .has_inbox = true,
1025                 .has_outbox = false,
1026                 .out_is_imm = false,
1027                 .encode_slave_id = true,
1028                 .verify = NULL,
1029                 .wrapper = mlx4_SW2HW_CQ_wrapper
1030         },
1031         {
1032                 .opcode = MLX4_CMD_HW2SW_CQ,
1033                 .has_inbox = false,
1034                 .has_outbox = false,
1035                 .out_is_imm = false,
1036                 .encode_slave_id = false,
1037                 .verify = NULL,
1038                 .wrapper = mlx4_HW2SW_CQ_wrapper
1039         },
1040         {
1041                 .opcode = MLX4_CMD_QUERY_CQ,
1042                 .has_inbox = false,
1043                 .has_outbox = true,
1044                 .out_is_imm = false,
1045                 .encode_slave_id = false,
1046                 .verify = NULL,
1047                 .wrapper = mlx4_QUERY_CQ_wrapper
1048         },
1049         {
1050                 .opcode = MLX4_CMD_MODIFY_CQ,
1051                 .has_inbox = true,
1052                 .has_outbox = false,
1053                 .out_is_imm = true,
1054                 .encode_slave_id = false,
1055                 .verify = NULL,
1056                 .wrapper = mlx4_MODIFY_CQ_wrapper
1057         },
1058         {
1059                 .opcode = MLX4_CMD_SW2HW_SRQ,
1060                 .has_inbox = true,
1061                 .has_outbox = false,
1062                 .out_is_imm = false,
1063                 .encode_slave_id = true,
1064                 .verify = NULL,
1065                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1066         },
1067         {
1068                 .opcode = MLX4_CMD_HW2SW_SRQ,
1069                 .has_inbox = false,
1070                 .has_outbox = false,
1071                 .out_is_imm = false,
1072                 .encode_slave_id = false,
1073                 .verify = NULL,
1074                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1075         },
1076         {
1077                 .opcode = MLX4_CMD_QUERY_SRQ,
1078                 .has_inbox = false,
1079                 .has_outbox = true,
1080                 .out_is_imm = false,
1081                 .encode_slave_id = false,
1082                 .verify = NULL,
1083                 .wrapper = mlx4_QUERY_SRQ_wrapper
1084         },
1085         {
1086                 .opcode = MLX4_CMD_ARM_SRQ,
1087                 .has_inbox = false,
1088                 .has_outbox = false,
1089                 .out_is_imm = false,
1090                 .encode_slave_id = false,
1091                 .verify = NULL,
1092                 .wrapper = mlx4_ARM_SRQ_wrapper
1093         },
1094         {
1095                 .opcode = MLX4_CMD_RST2INIT_QP,
1096                 .has_inbox = true,
1097                 .has_outbox = false,
1098                 .out_is_imm = false,
1099                 .encode_slave_id = true,
1100                 .verify = NULL,
1101                 .wrapper = mlx4_RST2INIT_QP_wrapper
1102         },
1103         {
1104                 .opcode = MLX4_CMD_INIT2INIT_QP,
1105                 .has_inbox = true,
1106                 .has_outbox = false,
1107                 .out_is_imm = false,
1108                 .encode_slave_id = false,
1109                 .verify = NULL,
1110                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1111         },
1112         {
1113                 .opcode = MLX4_CMD_INIT2RTR_QP,
1114                 .has_inbox = true,
1115                 .has_outbox = false,
1116                 .out_is_imm = false,
1117                 .encode_slave_id = false,
1118                 .verify = NULL,
1119                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1120         },
1121         {
1122                 .opcode = MLX4_CMD_RTR2RTS_QP,
1123                 .has_inbox = true,
1124                 .has_outbox = false,
1125                 .out_is_imm = false,
1126                 .encode_slave_id = false,
1127                 .verify = NULL,
1128                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1129         },
1130         {
1131                 .opcode = MLX4_CMD_RTS2RTS_QP,
1132                 .has_inbox = true,
1133                 .has_outbox = false,
1134                 .out_is_imm = false,
1135                 .encode_slave_id = false,
1136                 .verify = NULL,
1137                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1138         },
1139         {
1140                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1141                 .has_inbox = true,
1142                 .has_outbox = false,
1143                 .out_is_imm = false,
1144                 .encode_slave_id = false,
1145                 .verify = NULL,
1146                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1147         },
1148         {
1149                 .opcode = MLX4_CMD_2ERR_QP,
1150                 .has_inbox = false,
1151                 .has_outbox = false,
1152                 .out_is_imm = false,
1153                 .encode_slave_id = false,
1154                 .verify = NULL,
1155                 .wrapper = mlx4_GEN_QP_wrapper
1156         },
1157         {
1158                 .opcode = MLX4_CMD_RTS2SQD_QP,
1159                 .has_inbox = false,
1160                 .has_outbox = false,
1161                 .out_is_imm = false,
1162                 .encode_slave_id = false,
1163                 .verify = NULL,
1164                 .wrapper = mlx4_GEN_QP_wrapper
1165         },
1166         {
1167                 .opcode = MLX4_CMD_SQD2SQD_QP,
1168                 .has_inbox = true,
1169                 .has_outbox = false,
1170                 .out_is_imm = false,
1171                 .encode_slave_id = false,
1172                 .verify = NULL,
1173                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1174         },
1175         {
1176                 .opcode = MLX4_CMD_SQD2RTS_QP,
1177                 .has_inbox = true,
1178                 .has_outbox = false,
1179                 .out_is_imm = false,
1180                 .encode_slave_id = false,
1181                 .verify = NULL,
1182                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1183         },
1184         {
1185                 .opcode = MLX4_CMD_2RST_QP,
1186                 .has_inbox = false,
1187                 .has_outbox = false,
1188                 .out_is_imm = false,
1189                 .encode_slave_id = false,
1190                 .verify = NULL,
1191                 .wrapper = mlx4_2RST_QP_wrapper
1192         },
1193         {
1194                 .opcode = MLX4_CMD_QUERY_QP,
1195                 .has_inbox = false,
1196                 .has_outbox = true,
1197                 .out_is_imm = false,
1198                 .encode_slave_id = false,
1199                 .verify = NULL,
1200                 .wrapper = mlx4_GEN_QP_wrapper
1201         },
1202         {
1203                 .opcode = MLX4_CMD_SUSPEND_QP,
1204                 .has_inbox = false,
1205                 .has_outbox = false,
1206                 .out_is_imm = false,
1207                 .encode_slave_id = false,
1208                 .verify = NULL,
1209                 .wrapper = mlx4_GEN_QP_wrapper
1210         },
1211         {
1212                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1213                 .has_inbox = false,
1214                 .has_outbox = false,
1215                 .out_is_imm = false,
1216                 .encode_slave_id = false,
1217                 .verify = NULL,
1218                 .wrapper = mlx4_GEN_QP_wrapper
1219         },
1220         {
1221                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1222                 .has_inbox = false,
1223                 .has_outbox = false,
1224                 .out_is_imm = false,
1225                 .encode_slave_id = false,
1226                 .verify = NULL, /* XXX verify: only demux can do this */
1227                 .wrapper = NULL
1228         },
1229         {
1230                 .opcode = MLX4_CMD_MAD_IFC,
1231                 .has_inbox = true,
1232                 .has_outbox = true,
1233                 .out_is_imm = false,
1234                 .encode_slave_id = false,
1235                 .verify = NULL,
1236                 .wrapper = mlx4_MAD_IFC_wrapper
1237         },
1238         {
1239                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1240                 .has_inbox = false,
1241                 .has_outbox = true,
1242                 .out_is_imm = false,
1243                 .encode_slave_id = false,
1244                 .verify = NULL,
1245                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1246         },
1247         /* Native multicast commands are not available for guests */
1248         {
1249                 .opcode = MLX4_CMD_QP_ATTACH,
1250                 .has_inbox = true,
1251                 .has_outbox = false,
1252                 .out_is_imm = false,
1253                 .encode_slave_id = false,
1254                 .verify = NULL,
1255                 .wrapper = mlx4_QP_ATTACH_wrapper
1256         },
1257         {
1258                 .opcode = MLX4_CMD_PROMISC,
1259                 .has_inbox = false,
1260                 .has_outbox = false,
1261                 .out_is_imm = false,
1262                 .encode_slave_id = false,
1263                 .verify = NULL,
1264                 .wrapper = mlx4_PROMISC_wrapper
1265         },
1266         /* Ethernet specific commands */
1267         {
1268                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1269                 .has_inbox = true,
1270                 .has_outbox = false,
1271                 .out_is_imm = false,
1272                 .encode_slave_id = false,
1273                 .verify = NULL,
1274                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1275         },
1276         {
1277                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1278                 .has_inbox = false,
1279                 .has_outbox = false,
1280                 .out_is_imm = false,
1281                 .encode_slave_id = false,
1282                 .verify = NULL,
1283                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1284         },
1285         {
1286                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1287                 .has_inbox = false,
1288                 .has_outbox = true,
1289                 .out_is_imm = false,
1290                 .encode_slave_id = false,
1291                 .verify = NULL,
1292                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1293         },
1294         {
1295                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1296                 .has_inbox = false,
1297                 .has_outbox = false,
1298                 .out_is_imm = false,
1299                 .encode_slave_id = false,
1300                 .verify = NULL,
1301                 .wrapper = NULL
1302         },
1303         /* flow steering commands */
1304         {
1305                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1306                 .has_inbox = true,
1307                 .has_outbox = false,
1308                 .out_is_imm = true,
1309                 .encode_slave_id = false,
1310                 .verify = NULL,
1311                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1312         },
1313         {
1314                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1315                 .has_inbox = false,
1316                 .has_outbox = false,
1317                 .out_is_imm = false,
1318                 .encode_slave_id = false,
1319                 .verify = NULL,
1320                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1321         },
1322 };
1323
1324 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1325                                     struct mlx4_vhcr_cmd *in_vhcr)
1326 {
1327         struct mlx4_priv *priv = mlx4_priv(dev);
1328         struct mlx4_cmd_info *cmd = NULL;
1329         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1330         struct mlx4_vhcr *vhcr;
1331         struct mlx4_cmd_mailbox *inbox = NULL;
1332         struct mlx4_cmd_mailbox *outbox = NULL;
1333         u64 in_param;
1334         u64 out_param;
1335         int ret = 0;
1336         int i;
1337         int err = 0;
1338
1339         /* Create sw representation of Virtual HCR */
1340         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1341         if (!vhcr)
1342                 return -ENOMEM;
1343
1344         /* DMA in the vHCR */
1345         if (!in_vhcr) {
1346                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1347                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1348                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1349                                             MLX4_ACCESS_MEM_ALIGN), 1);
1350                 if (ret) {
1351                         mlx4_err(dev, "%s:Failed reading vhcr"
1352                                  "ret: 0x%x\n", __func__, ret);
1353                         kfree(vhcr);
1354                         return ret;
1355                 }
1356         }
1357
1358         /* Fill SW VHCR fields */
1359         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1360         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1361         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1362         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1363         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1364         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1365         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1366
1367         /* Lookup command */
1368         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1369                 if (vhcr->op == cmd_info[i].opcode) {
1370                         cmd = &cmd_info[i];
1371                         break;
1372                 }
1373         }
1374         if (!cmd) {
1375                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1376                          vhcr->op, slave);
1377                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1378                 goto out_status;
1379         }
1380
1381         /* Read inbox */
1382         if (cmd->has_inbox) {
1383                 vhcr->in_param &= INBOX_MASK;
1384                 inbox = mlx4_alloc_cmd_mailbox(dev);
1385                 if (IS_ERR(inbox)) {
1386                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1387                         inbox = NULL;
1388                         goto out_status;
1389                 }
1390
1391                 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1392                                     vhcr->in_param,
1393                                     MLX4_MAILBOX_SIZE, 1)) {
1394                         mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1395                                  __func__, cmd->opcode);
1396                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1397                         goto out_status;
1398                 }
1399         }
1400
1401         /* Apply permission and bound checks if applicable */
1402         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1403                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1404                           "checks for resource_id:%d\n", vhcr->op, slave,
1405                           vhcr->in_modifier);
1406                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1407                 goto out_status;
1408         }
1409
1410         /* Allocate outbox */
1411         if (cmd->has_outbox) {
1412                 outbox = mlx4_alloc_cmd_mailbox(dev);
1413                 if (IS_ERR(outbox)) {
1414                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1415                         outbox = NULL;
1416                         goto out_status;
1417                 }
1418         }
1419
1420         /* Execute the command! */
1421         if (cmd->wrapper) {
1422                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1423                                    cmd);
1424                 if (cmd->out_is_imm)
1425                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1426         } else {
1427                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1428                         vhcr->in_param;
1429                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1430                         vhcr->out_param;
1431                 err = __mlx4_cmd(dev, in_param, &out_param,
1432                                  cmd->out_is_imm, vhcr->in_modifier,
1433                                  vhcr->op_modifier, vhcr->op,
1434                                  MLX4_CMD_TIME_CLASS_A,
1435                                  MLX4_CMD_NATIVE);
1436
1437                 if (cmd->out_is_imm) {
1438                         vhcr->out_param = out_param;
1439                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1440                 }
1441         }
1442
1443         if (err) {
1444                 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1445                           " error:%d, status %d\n",
1446                           vhcr->op, slave, vhcr->errno, err);
1447                 vhcr_cmd->status = mlx4_errno_to_status(err);
1448                 goto out_status;
1449         }
1450
1451
1452         /* Write outbox if command completed successfully */
1453         if (cmd->has_outbox && !vhcr_cmd->status) {
1454                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1455                                       vhcr->out_param,
1456                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1457                 if (ret) {
1458                         /* If we failed to write back the outbox after the
1459                          *command was successfully executed, we must fail this
1460                          * slave, as it is now in undefined state */
1461                         mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1462                         goto out;
1463                 }
1464         }
1465
1466 out_status:
1467         /* DMA back vhcr result */
1468         if (!in_vhcr) {
1469                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1470                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1471                                       ALIGN(sizeof(struct mlx4_vhcr),
1472                                             MLX4_ACCESS_MEM_ALIGN),
1473                                       MLX4_CMD_WRAPPED);
1474                 if (ret)
1475                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1476                                  __func__);
1477                 else if (vhcr->e_bit &&
1478                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1479                                 mlx4_warn(dev, "Failed to generate command completion "
1480                                           "eqe for slave %d\n", slave);
1481         }
1482
1483 out:
1484         kfree(vhcr);
1485         mlx4_free_cmd_mailbox(dev, inbox);
1486         mlx4_free_cmd_mailbox(dev, outbox);
1487         return ret;
1488 }
1489
1490 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1491                                u16 param, u8 toggle)
1492 {
1493         struct mlx4_priv *priv = mlx4_priv(dev);
1494         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1495         u32 reply;
1496         u8 is_going_down = 0;
1497         int i;
1498
1499         slave_state[slave].comm_toggle ^= 1;
1500         reply = (u32) slave_state[slave].comm_toggle << 31;
1501         if (toggle != slave_state[slave].comm_toggle) {
1502                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1503                           "STATE COMPROMISIED ***\n", toggle, slave);
1504                 goto reset_slave;
1505         }
1506         if (cmd == MLX4_COMM_CMD_RESET) {
1507                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1508                 slave_state[slave].active = false;
1509                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1510                                 slave_state[slave].event_eq[i].eqn = -1;
1511                                 slave_state[slave].event_eq[i].token = 0;
1512                 }
1513                 /*check if we are in the middle of FLR process,
1514                 if so return "retry" status to the slave*/
1515                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1516                         goto inform_slave_state;
1517
1518                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1519
1520                 /* write the version in the event field */
1521                 reply |= mlx4_comm_get_version();
1522
1523                 goto reset_slave;
1524         }
1525         /*command from slave in the middle of FLR*/
1526         if (cmd != MLX4_COMM_CMD_RESET &&
1527             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1528                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1529                           "in the middle of FLR\n", slave, cmd);
1530                 return;
1531         }
1532
1533         switch (cmd) {
1534         case MLX4_COMM_CMD_VHCR0:
1535                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1536                         goto reset_slave;
1537                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1538                 priv->mfunc.master.slave_state[slave].cookie = 0;
1539                 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1540                 break;
1541         case MLX4_COMM_CMD_VHCR1:
1542                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1543                         goto reset_slave;
1544                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1545                 break;
1546         case MLX4_COMM_CMD_VHCR2:
1547                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1548                         goto reset_slave;
1549                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1550                 break;
1551         case MLX4_COMM_CMD_VHCR_EN:
1552                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1553                         goto reset_slave;
1554                 slave_state[slave].vhcr_dma |= param;
1555                 slave_state[slave].active = true;
1556                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1557                 break;
1558         case MLX4_COMM_CMD_VHCR_POST:
1559                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1560                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1561                         goto reset_slave;
1562                 down(&priv->cmd.slave_sem);
1563                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1564                         mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1565                                  " resetting slave.\n", slave);
1566                         up(&priv->cmd.slave_sem);
1567                         goto reset_slave;
1568                 }
1569                 up(&priv->cmd.slave_sem);
1570                 break;
1571         default:
1572                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1573                 goto reset_slave;
1574         }
1575         spin_lock(&priv->mfunc.master.slave_state_lock);
1576         if (!slave_state[slave].is_slave_going_down)
1577                 slave_state[slave].last_cmd = cmd;
1578         else
1579                 is_going_down = 1;
1580         spin_unlock(&priv->mfunc.master.slave_state_lock);
1581         if (is_going_down) {
1582                 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1583                           " executing from slave:%d\n",
1584                           cmd, slave);
1585                 return;
1586         }
1587         __raw_writel((__force u32) cpu_to_be32(reply),
1588                      &priv->mfunc.comm[slave].slave_read);
1589         mmiowb();
1590
1591         return;
1592
1593 reset_slave:
1594         /* cleanup any slave resources */
1595         mlx4_delete_all_resources_for_slave(dev, slave);
1596         spin_lock(&priv->mfunc.master.slave_state_lock);
1597         if (!slave_state[slave].is_slave_going_down)
1598                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1599         spin_unlock(&priv->mfunc.master.slave_state_lock);
1600         /*with slave in the middle of flr, no need to clean resources again.*/
1601 inform_slave_state:
1602         memset(&slave_state[slave].event_eq, 0,
1603                sizeof(struct mlx4_slave_event_eq_info));
1604         __raw_writel((__force u32) cpu_to_be32(reply),
1605                      &priv->mfunc.comm[slave].slave_read);
1606         wmb();
1607 }
1608
1609 /* master command processing */
1610 void mlx4_master_comm_channel(struct work_struct *work)
1611 {
1612         struct mlx4_mfunc_master_ctx *master =
1613                 container_of(work,
1614                              struct mlx4_mfunc_master_ctx,
1615                              comm_work);
1616         struct mlx4_mfunc *mfunc =
1617                 container_of(master, struct mlx4_mfunc, master);
1618         struct mlx4_priv *priv =
1619                 container_of(mfunc, struct mlx4_priv, mfunc);
1620         struct mlx4_dev *dev = &priv->dev;
1621         __be32 *bit_vec;
1622         u32 comm_cmd;
1623         u32 vec;
1624         int i, j, slave;
1625         int toggle;
1626         int served = 0;
1627         int reported = 0;
1628         u32 slt;
1629
1630         bit_vec = master->comm_arm_bit_vector;
1631         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1632                 vec = be32_to_cpu(bit_vec[i]);
1633                 for (j = 0; j < 32; j++) {
1634                         if (!(vec & (1 << j)))
1635                                 continue;
1636                         ++reported;
1637                         slave = (i * 32) + j;
1638                         comm_cmd = swab32(readl(
1639                                           &mfunc->comm[slave].slave_write));
1640                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
1641                                      >> 31;
1642                         toggle = comm_cmd >> 31;
1643                         if (toggle != slt) {
1644                                 if (master->slave_state[slave].comm_toggle
1645                                     != slt) {
1646                                         printk(KERN_INFO "slave %d out of sync."
1647                                                " read toggle %d, state toggle %d. "
1648                                                "Resynching.\n", slave, slt,
1649                                                master->slave_state[slave].comm_toggle);
1650                                         master->slave_state[slave].comm_toggle =
1651                                                 slt;
1652                                 }
1653                                 mlx4_master_do_cmd(dev, slave,
1654                                                    comm_cmd >> 16 & 0xff,
1655                                                    comm_cmd & 0xffff, toggle);
1656                                 ++served;
1657                         }
1658                 }
1659         }
1660
1661         if (reported && reported != served)
1662                 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1663                           " but %d were served\n",
1664                           reported, served);
1665
1666         if (mlx4_ARM_COMM_CHANNEL(dev))
1667                 mlx4_warn(dev, "Failed to arm comm channel events\n");
1668 }
1669
1670 static int sync_toggles(struct mlx4_dev *dev)
1671 {
1672         struct mlx4_priv *priv = mlx4_priv(dev);
1673         int wr_toggle;
1674         int rd_toggle;
1675         unsigned long end;
1676
1677         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1678         end = jiffies + msecs_to_jiffies(5000);
1679
1680         while (time_before(jiffies, end)) {
1681                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1682                 if (rd_toggle == wr_toggle) {
1683                         priv->cmd.comm_toggle = rd_toggle;
1684                         return 0;
1685                 }
1686
1687                 cond_resched();
1688         }
1689
1690         /*
1691          * we could reach here if for example the previous VM using this
1692          * function misbehaved and left the channel with unsynced state. We
1693          * should fix this here and give this VM a chance to use a properly
1694          * synced channel
1695          */
1696         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1697         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1698         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1699         priv->cmd.comm_toggle = 0;
1700
1701         return 0;
1702 }
1703
1704 int mlx4_multi_func_init(struct mlx4_dev *dev)
1705 {
1706         struct mlx4_priv *priv = mlx4_priv(dev);
1707         struct mlx4_slave_state *s_state;
1708         int i, j, err, port;
1709
1710         priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1711                                             &priv->mfunc.vhcr_dma,
1712                                             GFP_KERNEL);
1713         if (!priv->mfunc.vhcr) {
1714                 mlx4_err(dev, "Couldn't allocate vhcr.\n");
1715                 return -ENOMEM;
1716         }
1717
1718         if (mlx4_is_master(dev))
1719                 priv->mfunc.comm =
1720                 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1721                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1722         else
1723                 priv->mfunc.comm =
1724                 ioremap(pci_resource_start(dev->pdev, 2) +
1725                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1726         if (!priv->mfunc.comm) {
1727                 mlx4_err(dev, "Couldn't map communication vector.\n");
1728                 goto err_vhcr;
1729         }
1730
1731         if (mlx4_is_master(dev)) {
1732                 priv->mfunc.master.slave_state =
1733                         kzalloc(dev->num_slaves *
1734                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1735                 if (!priv->mfunc.master.slave_state)
1736                         goto err_comm;
1737
1738                 for (i = 0; i < dev->num_slaves; ++i) {
1739                         s_state = &priv->mfunc.master.slave_state[i];
1740                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
1741                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1742                                 s_state->event_eq[j].eqn = -1;
1743                         __raw_writel((__force u32) 0,
1744                                      &priv->mfunc.comm[i].slave_write);
1745                         __raw_writel((__force u32) 0,
1746                                      &priv->mfunc.comm[i].slave_read);
1747                         mmiowb();
1748                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1749                                 s_state->vlan_filter[port] =
1750                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
1751                                                 GFP_KERNEL);
1752                                 if (!s_state->vlan_filter[port]) {
1753                                         if (--port)
1754                                                 kfree(s_state->vlan_filter[port]);
1755                                         goto err_slaves;
1756                                 }
1757                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1758                         }
1759                         spin_lock_init(&s_state->lock);
1760                 }
1761
1762                 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
1763                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1764                 INIT_WORK(&priv->mfunc.master.comm_work,
1765                           mlx4_master_comm_channel);
1766                 INIT_WORK(&priv->mfunc.master.slave_event_work,
1767                           mlx4_gen_slave_eqe);
1768                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1769                           mlx4_master_handle_slave_flr);
1770                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1771                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1772                 priv->mfunc.master.comm_wq =
1773                         create_singlethread_workqueue("mlx4_comm");
1774                 if (!priv->mfunc.master.comm_wq)
1775                         goto err_slaves;
1776
1777                 if (mlx4_init_resource_tracker(dev))
1778                         goto err_thread;
1779
1780                 sema_init(&priv->cmd.slave_sem, 1);
1781                 err = mlx4_ARM_COMM_CHANNEL(dev);
1782                 if (err) {
1783                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1784                                  err);
1785                         goto err_resource;
1786                 }
1787
1788         } else {
1789                 err = sync_toggles(dev);
1790                 if (err) {
1791                         mlx4_err(dev, "Couldn't sync toggles\n");
1792                         goto err_comm;
1793                 }
1794
1795                 sema_init(&priv->cmd.slave_sem, 1);
1796         }
1797         return 0;
1798
1799 err_resource:
1800         mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1801 err_thread:
1802         flush_workqueue(priv->mfunc.master.comm_wq);
1803         destroy_workqueue(priv->mfunc.master.comm_wq);
1804 err_slaves:
1805         while (--i) {
1806                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1807                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1808         }
1809         kfree(priv->mfunc.master.slave_state);
1810 err_comm:
1811         iounmap(priv->mfunc.comm);
1812 err_vhcr:
1813         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1814                                              priv->mfunc.vhcr,
1815                                              priv->mfunc.vhcr_dma);
1816         priv->mfunc.vhcr = NULL;
1817         return -ENOMEM;
1818 }
1819
1820 int mlx4_cmd_init(struct mlx4_dev *dev)
1821 {
1822         struct mlx4_priv *priv = mlx4_priv(dev);
1823
1824         mutex_init(&priv->cmd.hcr_mutex);
1825         sema_init(&priv->cmd.poll_sem, 1);
1826         priv->cmd.use_events = 0;
1827         priv->cmd.toggle     = 1;
1828
1829         priv->cmd.hcr = NULL;
1830         priv->mfunc.vhcr = NULL;
1831
1832         if (!mlx4_is_slave(dev)) {
1833                 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1834                                         MLX4_HCR_BASE, MLX4_HCR_SIZE);
1835                 if (!priv->cmd.hcr) {
1836                         mlx4_err(dev, "Couldn't map command register.\n");
1837                         return -ENOMEM;
1838                 }
1839         }
1840
1841         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1842                                          MLX4_MAILBOX_SIZE,
1843                                          MLX4_MAILBOX_SIZE, 0);
1844         if (!priv->cmd.pool)
1845                 goto err_hcr;
1846
1847         return 0;
1848
1849 err_hcr:
1850         if (!mlx4_is_slave(dev))
1851                 iounmap(priv->cmd.hcr);
1852         return -ENOMEM;
1853 }
1854
1855 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1856 {
1857         struct mlx4_priv *priv = mlx4_priv(dev);
1858         int i, port;
1859
1860         if (mlx4_is_master(dev)) {
1861                 flush_workqueue(priv->mfunc.master.comm_wq);
1862                 destroy_workqueue(priv->mfunc.master.comm_wq);
1863                 for (i = 0; i < dev->num_slaves; i++) {
1864                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
1865                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1866                 }
1867                 kfree(priv->mfunc.master.slave_state);
1868         }
1869
1870         iounmap(priv->mfunc.comm);
1871         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1872                      priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1873         priv->mfunc.vhcr = NULL;
1874 }
1875
1876 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1877 {
1878         struct mlx4_priv *priv = mlx4_priv(dev);
1879
1880         pci_pool_destroy(priv->cmd.pool);
1881
1882         if (!mlx4_is_slave(dev))
1883                 iounmap(priv->cmd.hcr);
1884 }
1885
1886 /*
1887  * Switch to using events to issue FW commands (can only be called
1888  * after event queue for command events has been initialized).
1889  */
1890 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1891 {
1892         struct mlx4_priv *priv = mlx4_priv(dev);
1893         int i;
1894         int err = 0;
1895
1896         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1897                                    sizeof (struct mlx4_cmd_context),
1898                                    GFP_KERNEL);
1899         if (!priv->cmd.context)
1900                 return -ENOMEM;
1901
1902         for (i = 0; i < priv->cmd.max_cmds; ++i) {
1903                 priv->cmd.context[i].token = i;
1904                 priv->cmd.context[i].next  = i + 1;
1905         }
1906
1907         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
1908         priv->cmd.free_head = 0;
1909
1910         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
1911         spin_lock_init(&priv->cmd.context_lock);
1912
1913         for (priv->cmd.token_mask = 1;
1914              priv->cmd.token_mask < priv->cmd.max_cmds;
1915              priv->cmd.token_mask <<= 1)
1916                 ; /* nothing */
1917         --priv->cmd.token_mask;
1918
1919         down(&priv->cmd.poll_sem);
1920         priv->cmd.use_events = 1;
1921
1922         return err;
1923 }
1924
1925 /*
1926  * Switch back to polling (used when shutting down the device)
1927  */
1928 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
1929 {
1930         struct mlx4_priv *priv = mlx4_priv(dev);
1931         int i;
1932
1933         priv->cmd.use_events = 0;
1934
1935         for (i = 0; i < priv->cmd.max_cmds; ++i)
1936                 down(&priv->cmd.event_sem);
1937
1938         kfree(priv->cmd.context);
1939
1940         up(&priv->cmd.poll_sem);
1941 }
1942
1943 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
1944 {
1945         struct mlx4_cmd_mailbox *mailbox;
1946
1947         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
1948         if (!mailbox)
1949                 return ERR_PTR(-ENOMEM);
1950
1951         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
1952                                       &mailbox->dma);
1953         if (!mailbox->buf) {
1954                 kfree(mailbox);
1955                 return ERR_PTR(-ENOMEM);
1956         }
1957
1958         return mailbox;
1959 }
1960 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
1961
1962 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
1963                            struct mlx4_cmd_mailbox *mailbox)
1964 {
1965         if (!mailbox)
1966                 return;
1967
1968         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
1969         kfree(mailbox);
1970 }
1971 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
1972
1973 u32 mlx4_comm_get_version(void)
1974 {
1975          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
1976 }