drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45
  46 #include <asm/io.h>
  47
  48 #include "mlx4.h"
  49 #include "fw.h"
  50
  51 #define CMD_POLL_TOKEN 0xffff
  52 #define INBOX_MASK      0xffffffffffffff00ULL
  53
  54 #define CMD_CHAN_VER 1
  55 #define CMD_CHAN_IF_REV 1
  56
  57 enum {
  58         /* command completed successfully: */
  59         CMD_STAT_OK             = 0x00,
  60         /* Internal error (such as a bus error) occurred while processing command: */
  61         CMD_STAT_INTERNAL_ERR   = 0x01,
  62         /* Operation/command not supported or opcode modifier not supported: */
  63         CMD_STAT_BAD_OP         = 0x02,
  64         /* Parameter not supported or parameter out of range: */
  65         CMD_STAT_BAD_PARAM      = 0x03,
  66         /* System not enabled or bad system state: */
  67         CMD_STAT_BAD_SYS_STATE  = 0x04,
  68         /* Attempt to access reserved or unallocaterd resource: */
  69         CMD_STAT_BAD_RESOURCE   = 0x05,
  70         /* Requested resource is currently executing a command, or is otherwise busy: */
  71         CMD_STAT_RESOURCE_BUSY  = 0x06,
  72         /* Required capability exceeds device limits: */
  73         CMD_STAT_EXCEED_LIM     = 0x08,
  74         /* Resource is not in the appropriate state or ownership: */
  75         CMD_STAT_BAD_RES_STATE  = 0x09,
  76         /* Index out of range: */
  77         CMD_STAT_BAD_INDEX      = 0x0a,
  78         /* FW image corrupted: */
  79         CMD_STAT_BAD_NVMEM      = 0x0b,
  80         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  81         CMD_STAT_ICM_ERROR      = 0x0c,
  82         /* Attempt to modify a QP/EE which is not in the presumed state: */
  83         CMD_STAT_BAD_QP_STATE   = 0x10,
  84         /* Bad segment parameters (Address/Size): */
  85         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  86         /* Memory Region has Memory Windows bound to: */
  87         CMD_STAT_REG_BOUND      = 0x21,
  88         /* HCA local attached memory not present: */
  89         CMD_STAT_LAM_NOT_PRE    = 0x22,
  90         /* Bad management packet (silently discarded): */
  91         CMD_STAT_BAD_PKT        = 0x30,
  92         /* More outstanding CQEs in CQ than new CQ size: */
  93         CMD_STAT_BAD_SIZE       = 0x40,
  94         /* Multi Function device support required: */
  95         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  96 };
  97
  98 enum {
  99         HCR_IN_PARAM_OFFSET     = 0x00,
 100         HCR_IN_MODIFIER_OFFSET  = 0x08,
 101         HCR_OUT_PARAM_OFFSET    = 0x0c,
 102         HCR_TOKEN_OFFSET        = 0x14,
 103         HCR_STATUS_OFFSET       = 0x18,
 104
 105         HCR_OPMOD_SHIFT         = 12,
 106         HCR_T_BIT               = 21,
 107         HCR_E_BIT               = 22,
 108         HCR_GO_BIT              = 23
 109 };
 110
 111 enum {
 112         GO_BIT_TIMEOUT_MSECS    = 10000
 113 };
 114
 115 struct mlx4_cmd_context {
 116         struct completion       done;
 117         int                     result;
 118         int                     next;
 119         u64                     out_param;
 120         u16                     token;
 121         u8                      fw_status;
 122 };
 123
 124 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 125                                     struct mlx4_vhcr_cmd *in_vhcr);
 126
 127 static int mlx4_status_to_errno(u8 status)
 128 {
 129         static const int trans_table[] = {
 130                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 131                 [CMD_STAT_BAD_OP]         = -EPERM,
 132                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 133                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 134                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 135                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 136                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 137                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 138                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 139                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 140                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 141                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 142                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 143                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 144                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 145                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 146                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 147                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 148         };
 149
 150         if (status >= ARRAY_SIZE(trans_table) ||
 151             (status != CMD_STAT_OK && trans_table[status] == 0))
 152                 return -EIO;
 153
 154         return trans_table[status];
 155 }
 156
 157 static u8 mlx4_errno_to_status(int errno)
 158 {
 159         switch (errno) {
 160         case -EPERM:
 161                 return CMD_STAT_BAD_OP;
 162         case -EINVAL:
 163                 return CMD_STAT_BAD_PARAM;
 164         case -ENXIO:
 165                 return CMD_STAT_BAD_SYS_STATE;
 166         case -EBUSY:
 167                 return CMD_STAT_RESOURCE_BUSY;
 168         case -ENOMEM:
 169                 return CMD_STAT_EXCEED_LIM;
 170         case -ENFILE:
 171                 return CMD_STAT_ICM_ERROR;
 172         default:
 173                 return CMD_STAT_INTERNAL_ERR;
 174         }
 175 }
 176
 177 static int comm_pending(struct mlx4_dev *dev)
 178 {
 179         struct mlx4_priv *priv = mlx4_priv(dev);
 180         u32 status = readl(&priv->mfunc.comm->slave_read);
 181
 182         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 183 }
 184
 185 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 186 {
 187         struct mlx4_priv *priv = mlx4_priv(dev);
 188         u32 val;
 189
 190         priv->cmd.comm_toggle ^= 1;
 191         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 192         __raw_writel((__force u32) cpu_to_be32(val),
 193                      &priv->mfunc.comm->slave_write);
 194         mmiowb();
 195 }
 196
 197 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 198                        unsigned long timeout)
 199 {
 200         struct mlx4_priv *priv = mlx4_priv(dev);
 201         unsigned long end;
 202         int err = 0;
 203         int ret_from_pending = 0;
 204
 205         /* First, verify that the master reports correct status */
 206         if (comm_pending(dev)) {
 207                 mlx4_warn(dev, "Communication channel is not idle."
 208                           "my toggle is %d (cmd:0x%x)\n",
 209                           priv->cmd.comm_toggle, cmd);
 210                 return -EAGAIN;
 211         }
 212
 213         /* Write command */
 214         down(&priv->cmd.poll_sem);
 215         mlx4_comm_cmd_post(dev, cmd, param);
 216
 217         end = msecs_to_jiffies(timeout) + jiffies;
 218         while (comm_pending(dev) && time_before(jiffies, end))
 219                 cond_resched();
 220         ret_from_pending = comm_pending(dev);
 221         if (ret_from_pending) {
 222                 /* check if the slave is trying to boot in the middle of
 223                  * FLR process. The only non-zero result in the RESET command
 224                  * is MLX4_DELAY_RESET_SLAVE*/
 225                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 226                         err = MLX4_DELAY_RESET_SLAVE;
 227                 } else {
 228                         mlx4_warn(dev, "Communication channel timed out\n");
 229                         err = -ETIMEDOUT;
 230                 }
 231         }
 232
 233         up(&priv->cmd.poll_sem);
 234         return err;
 235 }
 236
 237 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
 238                               u16 param, unsigned long timeout)
 239 {
 240         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 241         struct mlx4_cmd_context *context;
 242         unsigned long end;
 243         int err = 0;
 244
 245         down(&cmd->event_sem);
 246
 247         spin_lock(&cmd->context_lock);
 248         BUG_ON(cmd->free_head < 0);
 249         context = &cmd->context[cmd->free_head];
 250         context->token += cmd->token_mask + 1;
 251         cmd->free_head = context->next;
 252         spin_unlock(&cmd->context_lock);
 253
 254         init_completion(&context->done);
 255
 256         mlx4_comm_cmd_post(dev, op, param);
 257
 258         if (!wait_for_completion_timeout(&context->done,
 259                                          msecs_to_jiffies(timeout))) {
 260                 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
 261                           op);
 262                 err = -EBUSY;
 263                 goto out;
 264         }
 265
 266         err = context->result;
 267         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 268                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 269                          op, context->fw_status);
 270                 goto out;
 271         }
 272
 273 out:
 274         /* wait for comm channel ready
 275          * this is necessary for prevention the race
 276          * when switching between event to polling mode
 277          */
 278         end = msecs_to_jiffies(timeout) + jiffies;
 279         while (comm_pending(dev) && time_before(jiffies, end))
 280                 cond_resched();
 281
 282         spin_lock(&cmd->context_lock);
 283         context->next = cmd->free_head;
 284         cmd->free_head = context - cmd->context;
 285         spin_unlock(&cmd->context_lock);
 286
 287         up(&cmd->event_sem);
 288         return err;
 289 }
 290
 291 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 292                   unsigned long timeout)
 293 {
 294         if (mlx4_priv(dev)->cmd.use_events)
 295                 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
 296         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 297 }
 298
 299 static int cmd_pending(struct mlx4_dev *dev)
 300 {
 301         u32 status;
 302
 303         if (pci_channel_offline(dev->pdev))
 304                 return -EIO;
 305
 306         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 307
 308         return (status & swab32(1 << HCR_GO_BIT)) ||
 309                 (mlx4_priv(dev)->cmd.toggle ==
 310                  !!(status & swab32(1 << HCR_T_BIT)));
 311 }
 312
 313 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 314                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 315                          int event)
 316 {
 317         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 318         u32 __iomem *hcr = cmd->hcr;
 319         int ret = -EAGAIN;
 320         unsigned long end;
 321
 322         mutex_lock(&cmd->hcr_mutex);
 323
 324         if (pci_channel_offline(dev->pdev)) {
 325                 /*
 326                  * Device is going through error recovery
 327                  * and cannot accept commands.
 328                  */
 329                 ret = -EIO;
 330                 goto out;
 331         }
 332
 333         end = jiffies;
 334         if (event)
 335                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 336
 337         while (cmd_pending(dev)) {
 338                 if (pci_channel_offline(dev->pdev)) {
 339                         /*
 340                          * Device is going through error recovery
 341                          * and cannot accept commands.
 342                          */
 343                         ret = -EIO;
 344                         goto out;
 345                 }
 346
 347                 if (time_after_eq(jiffies, end)) {
 348                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 349                         goto out;
 350                 }
 351                 cond_resched();
 352         }
 353
 354         /*
 355          * We use writel (instead of something like memcpy_toio)
 356          * because writes of less than 32 bits to the HCR don't work
 357          * (and some architectures such as ia64 implement memcpy_toio
 358          * in terms of writeb).
 359          */
 360         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 361         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 362         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 363         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 364         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 365         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 366
 367         /* __raw_writel may not order writes. */
 368         wmb();
 369
 370         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 371                                                (cmd->toggle << HCR_T_BIT)       |
 372                                                (event ? (1 << HCR_E_BIT) : 0)   |
 373                                                (op_modifier << HCR_OPMOD_SHIFT) |
 374                                                op), hcr + 6);
 375
 376         /*
 377          * Make sure that our HCR writes don't get mixed in with
 378          * writes from another CPU starting a FW command.
 379          */
 380         mmiowb();
 381
 382         cmd->toggle = cmd->toggle ^ 1;
 383
 384         ret = 0;
 385
 386 out:
 387         mutex_unlock(&cmd->hcr_mutex);
 388         return ret;
 389 }
 390
 391 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 392                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 393                           u16 op, unsigned long timeout)
 394 {
 395         struct mlx4_priv *priv = mlx4_priv(dev);
 396         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 397         int ret;
 398
 399         mutex_lock(&priv->cmd.slave_cmd_mutex);
 400
 401         vhcr->in_param = cpu_to_be64(in_param);
 402         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 403         vhcr->in_modifier = cpu_to_be32(in_modifier);
 404         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 405         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 406         vhcr->status = 0;
 407         vhcr->flags = !!(priv->cmd.use_events) << 6;
 408
 409         if (mlx4_is_master(dev)) {
 410                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 411                 if (!ret) {
 412                         if (out_is_imm) {
 413                                 if (out_param)
 414                                         *out_param =
 415                                                 be64_to_cpu(vhcr->out_param);
 416                                 else {
 417                                         mlx4_err(dev, "response expected while"
 418                                                  "output mailbox is NULL for "
 419                                                  "command 0x%x\n", op);
 420                                         vhcr->status = CMD_STAT_BAD_PARAM;
 421                                 }
 422                         }
 423                         ret = mlx4_status_to_errno(vhcr->status);
 424                 }
 425         } else {
 426                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
 427                                     MLX4_COMM_TIME + timeout);
 428                 if (!ret) {
 429                         if (out_is_imm) {
 430                                 if (out_param)
 431                                         *out_param =
 432                                                 be64_to_cpu(vhcr->out_param);
 433                                 else {
 434                                         mlx4_err(dev, "response expected while"
 435                                                  "output mailbox is NULL for "
 436                                                  "command 0x%x\n", op);
 437                                         vhcr->status = CMD_STAT_BAD_PARAM;
 438                                 }
 439                         }
 440                         ret = mlx4_status_to_errno(vhcr->status);
 441                 } else
 442                         mlx4_err(dev, "failed execution of VHCR_POST command"
 443                                  "opcode 0x%x\n", op);
 444         }
 445
 446         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 447         return ret;
 448 }
 449
 450 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 451                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 452                          u16 op, unsigned long timeout)
 453 {
 454         struct mlx4_priv *priv = mlx4_priv(dev);
 455         void __iomem *hcr = priv->cmd.hcr;
 456         int err = 0;
 457         unsigned long end;
 458         u32 stat;
 459
 460         down(&priv->cmd.poll_sem);
 461
 462         if (pci_channel_offline(dev->pdev)) {
 463                 /*
 464                  * Device is going through error recovery
 465                  * and cannot accept commands.
 466                  */
 467                 err = -EIO;
 468                 goto out;
 469         }
 470
 471         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 472                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 473         if (err)
 474                 goto out;
 475
 476         end = msecs_to_jiffies(timeout) + jiffies;
 477         while (cmd_pending(dev) && time_before(jiffies, end)) {
 478                 if (pci_channel_offline(dev->pdev)) {
 479                         /*
 480                          * Device is going through error recovery
 481                          * and cannot accept commands.
 482                          */
 483                         err = -EIO;
 484                         goto out;
 485                 }
 486
 487                 cond_resched();
 488         }
 489
 490         if (cmd_pending(dev)) {
 491                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 492                           op);
 493                 err = -ETIMEDOUT;
 494                 goto out;
 495         }
 496
 497         if (out_is_imm)
 498                 *out_param =
 499                         (u64) be32_to_cpu((__force __be32)
 500                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 501                         (u64) be32_to_cpu((__force __be32)
 502                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 503         stat = be32_to_cpu((__force __be32)
 504                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 505         err = mlx4_status_to_errno(stat);
 506         if (err)
 507                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 508                          op, stat);
 509
 510 out:
 511         up(&priv->cmd.poll_sem);
 512         return err;
 513 }
 514
 515 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 516 {
 517         struct mlx4_priv *priv = mlx4_priv(dev);
 518         struct mlx4_cmd_context *context =
 519                 &priv->cmd.context[token & priv->cmd.token_mask];
 520
 521         /* previously timed out command completing at long last */
 522         if (token != context->token)
 523                 return;
 524
 525         context->fw_status = status;
 526         context->result    = mlx4_status_to_errno(status);
 527         context->out_param = out_param;
 528
 529         complete(&context->done);
 530 }
 531
 532 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 533                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 534                          u16 op, unsigned long timeout)
 535 {
 536         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 537         struct mlx4_cmd_context *context;
 538         int err = 0;
 539
 540         down(&cmd->event_sem);
 541
 542         spin_lock(&cmd->context_lock);
 543         BUG_ON(cmd->free_head < 0);
 544         context = &cmd->context[cmd->free_head];
 545         context->token += cmd->token_mask + 1;
 546         cmd->free_head = context->next;
 547         spin_unlock(&cmd->context_lock);
 548
 549         init_completion(&context->done);
 550
 551         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 552                       in_modifier, op_modifier, op, context->token, 1);
 553
 554         if (!wait_for_completion_timeout(&context->done,
 555                                          msecs_to_jiffies(timeout))) {
 556                 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 557                           op);
 558                 err = -EBUSY;
 559                 goto out;
 560         }
 561
 562         err = context->result;
 563         if (err) {
 564                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 565                          op, context->fw_status);
 566                 goto out;
 567         }
 568
 569         if (out_is_imm)
 570                 *out_param = context->out_param;
 571
 572 out:
 573         spin_lock(&cmd->context_lock);
 574         context->next = cmd->free_head;
 575         cmd->free_head = context - cmd->context;
 576         spin_unlock(&cmd->context_lock);
 577
 578         up(&cmd->event_sem);
 579         return err;
 580 }
 581
 582 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 583                int out_is_imm, u32 in_modifier, u8 op_modifier,
 584                u16 op, unsigned long timeout, int native)
 585 {
 586         if (pci_channel_offline(dev->pdev))
 587                 return -EIO;
 588
 589         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 590                 if (mlx4_priv(dev)->cmd.use_events)
 591                         return mlx4_cmd_wait(dev, in_param, out_param,
 592                                              out_is_imm, in_modifier,
 593                                              op_modifier, op, timeout);
 594                 else
 595                         return mlx4_cmd_poll(dev, in_param, out_param,
 596                                              out_is_imm, in_modifier,
 597                                              op_modifier, op, timeout);
 598         }
 599         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 600                               in_modifier, op_modifier, op, timeout);
 601 }
 602 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 603
 604
 605 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 606 {
 607         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 608                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 609 }
 610
 611 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 612                            int slave, u64 slave_addr,
 613                            int size, int is_read)
 614 {
 615         u64 in_param;
 616         u64 out_param;
 617
 618         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 619             (slave & ~0x7f) | (size & 0xff)) {
 620                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
 621                               "master_addr:0x%llx slave_id:%d size:%d\n",
 622                               slave_addr, master_addr, slave, size);
 623                 return -EINVAL;
 624         }
 625
 626         if (is_read) {
 627                 in_param = (u64) slave | slave_addr;
 628                 out_param = (u64) dev->caps.function | master_addr;
 629         } else {
 630                 in_param = (u64) dev->caps.function | master_addr;
 631                 out_param = (u64) slave | slave_addr;
 632         }
 633
 634         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 635                             MLX4_CMD_ACCESS_MEM,
 636                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 637 }
 638
 639 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 640                                struct mlx4_cmd_mailbox *inbox,
 641                                struct mlx4_cmd_mailbox *outbox)
 642 {
 643         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 644         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 645         int err;
 646         int i;
 647
 648         if (index & 0x1f)
 649                 return -EINVAL;
 650
 651         in_mad->attr_mod = cpu_to_be32(index / 32);
 652
 653         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 654                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 655                            MLX4_CMD_NATIVE);
 656         if (err)
 657                 return err;
 658
 659         for (i = 0; i < 32; ++i)
 660                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 661
 662         return err;
 663 }
 664
 665 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 666                                struct mlx4_cmd_mailbox *inbox,
 667                                struct mlx4_cmd_mailbox *outbox)
 668 {
 669         int i;
 670         int err;
 671
 672         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 673                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 674                 if (err)
 675                         return err;
 676         }
 677
 678         return 0;
 679 }
 680 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 681 #define PORT_STATE_OFFSET 32
 682
 683 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 684 {
 685         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 686                 return IB_PORT_ACTIVE;
 687         else
 688                 return IB_PORT_DOWN;
 689 }
 690
 691 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 692                                 struct mlx4_vhcr *vhcr,
 693                                 struct mlx4_cmd_mailbox *inbox,
 694                                 struct mlx4_cmd_mailbox *outbox,
 695                                 struct mlx4_cmd_info *cmd)
 696 {
 697         struct ib_smp *smp = inbox->buf;
 698         u32 index;
 699         u8 port;
 700         u16 *table;
 701         int err;
 702         int vidx, pidx;
 703         struct mlx4_priv *priv = mlx4_priv(dev);
 704         struct ib_smp *outsmp = outbox->buf;
 705         __be16 *outtab = (__be16 *)(outsmp->data);
 706         __be32 slave_cap_mask;
 707         __be64 slave_node_guid;
 708         port = vhcr->in_modifier;
 709
 710         if (smp->base_version == 1 &&
 711             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 712             smp->class_version == 1) {
 713                 if (smp->method == IB_MGMT_METHOD_GET) {
 714                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 715                                 index = be32_to_cpu(smp->attr_mod);
 716                                 if (port < 1 || port > dev->caps.num_ports)
 717                                         return -EINVAL;
 718                                 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
 719                                 if (!table)
 720                                         return -ENOMEM;
 721                                 /* need to get the full pkey table because the paravirtualized
 722                                  * pkeys may be scattered among several pkey blocks.
 723                                  */
 724                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 725                                 if (!err) {
 726                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 727                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 728                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 729                                         }
 730                                 }
 731                                 kfree(table);
 732                                 return err;
 733                         }
 734                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 735                                 /*get the slave specific caps:*/
 736                                 /*do the command */
 737                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 738                                             vhcr->in_modifier, vhcr->op_modifier,
 739                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 740                                 /* modify the response for slaves */
 741                                 if (!err && slave != mlx4_master_func_num(dev)) {
 742                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 743
 744                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 745                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 746                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 747                                 }
 748                                 return err;
 749                         }
 750                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 751                                 /* compute slave's gid block */
 752                                 smp->attr_mod = cpu_to_be32(slave / 8);
 753                                 /* execute cmd */
 754                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 755                                              vhcr->in_modifier, vhcr->op_modifier,
 756                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 757                                 if (!err) {
 758                                         /* if needed, move slave gid to index 0 */
 759                                         if (slave % 8)
 760                                                 memcpy(outsmp->data,
 761                                                        outsmp->data + (slave % 8) * 8, 8);
 762                                         /* delete all other gids */
 763                                         memset(outsmp->data + 8, 0, 56);
 764                                 }
 765                                 return err;
 766                         }
 767                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 768                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 769                                              vhcr->in_modifier, vhcr->op_modifier,
 770                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 771                                 if (!err) {
 772                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 773                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 774                                 }
 775                                 return err;
 776                         }
 777                 }
 778         }
 779         if (slave != mlx4_master_func_num(dev) &&
 780             ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
 781              (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 782               smp->method == IB_MGMT_METHOD_SET))) {
 783                 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
 784                          "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
 785                          slave, smp->method, smp->mgmt_class,
 786                          be16_to_cpu(smp->attr_id));
 787                 return -EPERM;
 788         }
 789         /*default:*/
 790         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 791                                     vhcr->in_modifier, vhcr->op_modifier,
 792                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 793 }
 794
 795 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 796                      struct mlx4_vhcr *vhcr,
 797                      struct mlx4_cmd_mailbox *inbox,
 798                      struct mlx4_cmd_mailbox *outbox,
 799                      struct mlx4_cmd_info *cmd)
 800 {
 801         u64 in_param;
 802         u64 out_param;
 803         int err;
 804
 805         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
 806         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
 807         if (cmd->encode_slave_id) {
 808                 in_param &= 0xffffffffffffff00ll;
 809                 in_param |= slave;
 810         }
 811
 812         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
 813                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
 814                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 815
 816         if (cmd->out_is_imm)
 817                 vhcr->out_param = out_param;
 818
 819         return err;
 820 }
 821
 822 static struct mlx4_cmd_info cmd_info[] = {
 823         {
 824                 .opcode = MLX4_CMD_QUERY_FW,
 825                 .has_inbox = false,
 826                 .has_outbox = true,
 827                 .out_is_imm = false,
 828                 .encode_slave_id = false,
 829                 .verify = NULL,
 830                 .wrapper = mlx4_QUERY_FW_wrapper
 831         },
 832         {
 833                 .opcode = MLX4_CMD_QUERY_HCA,
 834                 .has_inbox = false,
 835                 .has_outbox = true,
 836                 .out_is_imm = false,
 837                 .encode_slave_id = false,
 838                 .verify = NULL,
 839                 .wrapper = NULL
 840         },
 841         {
 842                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
 843                 .has_inbox = false,
 844                 .has_outbox = true,
 845                 .out_is_imm = false,
 846                 .encode_slave_id = false,
 847                 .verify = NULL,
 848                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
 849         },
 850         {
 851                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
 852                 .has_inbox = false,
 853                 .has_outbox = true,
 854                 .out_is_imm = false,
 855                 .encode_slave_id = false,
 856                 .verify = NULL,
 857                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
 858         },
 859         {
 860                 .opcode = MLX4_CMD_QUERY_ADAPTER,
 861                 .has_inbox = false,
 862                 .has_outbox = true,
 863                 .out_is_imm = false,
 864                 .encode_slave_id = false,
 865                 .verify = NULL,
 866                 .wrapper = NULL
 867         },
 868         {
 869                 .opcode = MLX4_CMD_INIT_PORT,
 870                 .has_inbox = false,
 871                 .has_outbox = false,
 872                 .out_is_imm = false,
 873                 .encode_slave_id = false,
 874                 .verify = NULL,
 875                 .wrapper = mlx4_INIT_PORT_wrapper
 876         },
 877         {
 878                 .opcode = MLX4_CMD_CLOSE_PORT,
 879                 .has_inbox = false,
 880                 .has_outbox = false,
 881                 .out_is_imm  = false,
 882                 .encode_slave_id = false,
 883                 .verify = NULL,
 884                 .wrapper = mlx4_CLOSE_PORT_wrapper
 885         },
 886         {
 887                 .opcode = MLX4_CMD_QUERY_PORT,
 888                 .has_inbox = false,
 889                 .has_outbox = true,
 890                 .out_is_imm = false,
 891                 .encode_slave_id = false,
 892                 .verify = NULL,
 893                 .wrapper = mlx4_QUERY_PORT_wrapper
 894         },
 895         {
 896                 .opcode = MLX4_CMD_SET_PORT,
 897                 .has_inbox = true,
 898                 .has_outbox = false,
 899                 .out_is_imm = false,
 900                 .encode_slave_id = false,
 901                 .verify = NULL,
 902                 .wrapper = mlx4_SET_PORT_wrapper
 903         },
 904         {
 905                 .opcode = MLX4_CMD_MAP_EQ,
 906                 .has_inbox = false,
 907                 .has_outbox = false,
 908                 .out_is_imm = false,
 909                 .encode_slave_id = false,
 910                 .verify = NULL,
 911                 .wrapper = mlx4_MAP_EQ_wrapper
 912         },
 913         {
 914                 .opcode = MLX4_CMD_SW2HW_EQ,
 915                 .has_inbox = true,
 916                 .has_outbox = false,
 917                 .out_is_imm = false,
 918                 .encode_slave_id = true,
 919                 .verify = NULL,
 920                 .wrapper = mlx4_SW2HW_EQ_wrapper
 921         },
 922         {
 923                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
 924                 .has_inbox = false,
 925                 .has_outbox = false,
 926                 .out_is_imm = false,
 927                 .encode_slave_id = false,
 928                 .verify = NULL,
 929                 .wrapper = NULL
 930         },
 931         {
 932                 .opcode = MLX4_CMD_NOP,
 933                 .has_inbox = false,
 934                 .has_outbox = false,
 935                 .out_is_imm = false,
 936                 .encode_slave_id = false,
 937                 .verify = NULL,
 938                 .wrapper = NULL
 939         },
 940         {
 941                 .opcode = MLX4_CMD_ALLOC_RES,
 942                 .has_inbox = false,
 943                 .has_outbox = false,
 944                 .out_is_imm = true,
 945                 .encode_slave_id = false,
 946                 .verify = NULL,
 947                 .wrapper = mlx4_ALLOC_RES_wrapper
 948         },
 949         {
 950                 .opcode = MLX4_CMD_FREE_RES,
 951                 .has_inbox = false,
 952                 .has_outbox = false,
 953                 .out_is_imm = false,
 954                 .encode_slave_id = false,
 955                 .verify = NULL,
 956                 .wrapper = mlx4_FREE_RES_wrapper
 957         },
 958         {
 959                 .opcode = MLX4_CMD_SW2HW_MPT,
 960                 .has_inbox = true,
 961                 .has_outbox = false,
 962                 .out_is_imm = false,
 963                 .encode_slave_id = true,
 964                 .verify = NULL,
 965                 .wrapper = mlx4_SW2HW_MPT_wrapper
 966         },
 967         {
 968                 .opcode = MLX4_CMD_QUERY_MPT,
 969                 .has_inbox = false,
 970                 .has_outbox = true,
 971                 .out_is_imm = false,
 972                 .encode_slave_id = false,
 973                 .verify = NULL,
 974                 .wrapper = mlx4_QUERY_MPT_wrapper
 975         },
 976         {
 977                 .opcode = MLX4_CMD_HW2SW_MPT,
 978                 .has_inbox = false,
 979                 .has_outbox = false,
 980                 .out_is_imm = false,
 981                 .encode_slave_id = false,
 982                 .verify = NULL,
 983                 .wrapper = mlx4_HW2SW_MPT_wrapper
 984         },
 985         {
 986                 .opcode = MLX4_CMD_READ_MTT,
 987                 .has_inbox = false,
 988                 .has_outbox = true,
 989                 .out_is_imm = false,
 990                 .encode_slave_id = false,
 991                 .verify = NULL,
 992                 .wrapper = NULL
 993         },
 994         {
 995                 .opcode = MLX4_CMD_WRITE_MTT,
 996                 .has_inbox = true,
 997                 .has_outbox = false,
 998                 .out_is_imm = false,
 999                 .encode_slave_id = false,
1000                 .verify = NULL,
1001                 .wrapper = mlx4_WRITE_MTT_wrapper
1002         },
1003         {
1004                 .opcode = MLX4_CMD_SYNC_TPT,
1005                 .has_inbox = true,
1006                 .has_outbox = false,
1007                 .out_is_imm = false,
1008                 .encode_slave_id = false,
1009                 .verify = NULL,
1010                 .wrapper = NULL
1011         },
1012         {
1013                 .opcode = MLX4_CMD_HW2SW_EQ,
1014                 .has_inbox = false,
1015                 .has_outbox = true,
1016                 .out_is_imm = false,
1017                 .encode_slave_id = true,
1018                 .verify = NULL,
1019                 .wrapper = mlx4_HW2SW_EQ_wrapper
1020         },
1021         {
1022                 .opcode = MLX4_CMD_QUERY_EQ,
1023                 .has_inbox = false,
1024                 .has_outbox = true,
1025                 .out_is_imm = false,
1026                 .encode_slave_id = true,
1027                 .verify = NULL,
1028                 .wrapper = mlx4_QUERY_EQ_wrapper
1029         },
1030         {
1031                 .opcode = MLX4_CMD_SW2HW_CQ,
1032                 .has_inbox = true,
1033                 .has_outbox = false,
1034                 .out_is_imm = false,
1035                 .encode_slave_id = true,
1036                 .verify = NULL,
1037                 .wrapper = mlx4_SW2HW_CQ_wrapper
1038         },
1039         {
1040                 .opcode = MLX4_CMD_HW2SW_CQ,
1041                 .has_inbox = false,
1042                 .has_outbox = false,
1043                 .out_is_imm = false,
1044                 .encode_slave_id = false,
1045                 .verify = NULL,
1046                 .wrapper = mlx4_HW2SW_CQ_wrapper
1047         },
1048         {
1049                 .opcode = MLX4_CMD_QUERY_CQ,
1050                 .has_inbox = false,
1051                 .has_outbox = true,
1052                 .out_is_imm = false,
1053                 .encode_slave_id = false,
1054                 .verify = NULL,
1055                 .wrapper = mlx4_QUERY_CQ_wrapper
1056         },
1057         {
1058                 .opcode = MLX4_CMD_MODIFY_CQ,
1059                 .has_inbox = true,
1060                 .has_outbox = false,
1061                 .out_is_imm = true,
1062                 .encode_slave_id = false,
1063                 .verify = NULL,
1064                 .wrapper = mlx4_MODIFY_CQ_wrapper
1065         },
1066         {
1067                 .opcode = MLX4_CMD_SW2HW_SRQ,
1068                 .has_inbox = true,
1069                 .has_outbox = false,
1070                 .out_is_imm = false,
1071                 .encode_slave_id = true,
1072                 .verify = NULL,
1073                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1074         },
1075         {
1076                 .opcode = MLX4_CMD_HW2SW_SRQ,
1077                 .has_inbox = false,
1078                 .has_outbox = false,
1079                 .out_is_imm = false,
1080                 .encode_slave_id = false,
1081                 .verify = NULL,
1082                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1083         },
1084         {
1085                 .opcode = MLX4_CMD_QUERY_SRQ,
1086                 .has_inbox = false,
1087                 .has_outbox = true,
1088                 .out_is_imm = false,
1089                 .encode_slave_id = false,
1090                 .verify = NULL,
1091                 .wrapper = mlx4_QUERY_SRQ_wrapper
1092         },
1093         {
1094                 .opcode = MLX4_CMD_ARM_SRQ,
1095                 .has_inbox = false,
1096                 .has_outbox = false,
1097                 .out_is_imm = false,
1098                 .encode_slave_id = false,
1099                 .verify = NULL,
1100                 .wrapper = mlx4_ARM_SRQ_wrapper
1101         },
1102         {
1103                 .opcode = MLX4_CMD_RST2INIT_QP,
1104                 .has_inbox = true,
1105                 .has_outbox = false,
1106                 .out_is_imm = false,
1107                 .encode_slave_id = true,
1108                 .verify = NULL,
1109                 .wrapper = mlx4_RST2INIT_QP_wrapper
1110         },
1111         {
1112                 .opcode = MLX4_CMD_INIT2INIT_QP,
1113                 .has_inbox = true,
1114                 .has_outbox = false,
1115                 .out_is_imm = false,
1116                 .encode_slave_id = false,
1117                 .verify = NULL,
1118                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1119         },
1120         {
1121                 .opcode = MLX4_CMD_INIT2RTR_QP,
1122                 .has_inbox = true,
1123                 .has_outbox = false,
1124                 .out_is_imm = false,
1125                 .encode_slave_id = false,
1126                 .verify = NULL,
1127                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1128         },
1129         {
1130                 .opcode = MLX4_CMD_RTR2RTS_QP,
1131                 .has_inbox = true,
1132                 .has_outbox = false,
1133                 .out_is_imm = false,
1134                 .encode_slave_id = false,
1135                 .verify = NULL,
1136                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1137         },
1138         {
1139                 .opcode = MLX4_CMD_RTS2RTS_QP,
1140                 .has_inbox = true,
1141                 .has_outbox = false,
1142                 .out_is_imm = false,
1143                 .encode_slave_id = false,
1144                 .verify = NULL,
1145                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1146         },
1147         {
1148                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1149                 .has_inbox = true,
1150                 .has_outbox = false,
1151                 .out_is_imm = false,
1152                 .encode_slave_id = false,
1153                 .verify = NULL,
1154                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1155         },
1156         {
1157                 .opcode = MLX4_CMD_2ERR_QP,
1158                 .has_inbox = false,
1159                 .has_outbox = false,
1160                 .out_is_imm = false,
1161                 .encode_slave_id = false,
1162                 .verify = NULL,
1163                 .wrapper = mlx4_GEN_QP_wrapper
1164         },
1165         {
1166                 .opcode = MLX4_CMD_RTS2SQD_QP,
1167                 .has_inbox = false,
1168                 .has_outbox = false,
1169                 .out_is_imm = false,
1170                 .encode_slave_id = false,
1171                 .verify = NULL,
1172                 .wrapper = mlx4_GEN_QP_wrapper
1173         },
1174         {
1175                 .opcode = MLX4_CMD_SQD2SQD_QP,
1176                 .has_inbox = true,
1177                 .has_outbox = false,
1178                 .out_is_imm = false,
1179                 .encode_slave_id = false,
1180                 .verify = NULL,
1181                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1182         },
1183         {
1184                 .opcode = MLX4_CMD_SQD2RTS_QP,
1185                 .has_inbox = true,
1186                 .has_outbox = false,
1187                 .out_is_imm = false,
1188                 .encode_slave_id = false,
1189                 .verify = NULL,
1190                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1191         },
1192         {
1193                 .opcode = MLX4_CMD_2RST_QP,
1194                 .has_inbox = false,
1195                 .has_outbox = false,
1196                 .out_is_imm = false,
1197                 .encode_slave_id = false,
1198                 .verify = NULL,
1199                 .wrapper = mlx4_2RST_QP_wrapper
1200         },
1201         {
1202                 .opcode = MLX4_CMD_QUERY_QP,
1203                 .has_inbox = false,
1204                 .has_outbox = true,
1205                 .out_is_imm = false,
1206                 .encode_slave_id = false,
1207                 .verify = NULL,
1208                 .wrapper = mlx4_GEN_QP_wrapper
1209         },
1210         {
1211                 .opcode = MLX4_CMD_SUSPEND_QP,
1212                 .has_inbox = false,
1213                 .has_outbox = false,
1214                 .out_is_imm = false,
1215                 .encode_slave_id = false,
1216                 .verify = NULL,
1217                 .wrapper = mlx4_GEN_QP_wrapper
1218         },
1219         {
1220                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1221                 .has_inbox = false,
1222                 .has_outbox = false,
1223                 .out_is_imm = false,
1224                 .encode_slave_id = false,
1225                 .verify = NULL,
1226                 .wrapper = mlx4_GEN_QP_wrapper
1227         },
1228         {
1229                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1230                 .has_inbox = false,
1231                 .has_outbox = false,
1232                 .out_is_imm = false,
1233                 .encode_slave_id = false,
1234                 .verify = NULL, /* XXX verify: only demux can do this */
1235                 .wrapper = NULL
1236         },
1237         {
1238                 .opcode = MLX4_CMD_MAD_IFC,
1239                 .has_inbox = true,
1240                 .has_outbox = true,
1241                 .out_is_imm = false,
1242                 .encode_slave_id = false,
1243                 .verify = NULL,
1244                 .wrapper = mlx4_MAD_IFC_wrapper
1245         },
1246         {
1247                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1248                 .has_inbox = false,
1249                 .has_outbox = true,
1250                 .out_is_imm = false,
1251                 .encode_slave_id = false,
1252                 .verify = NULL,
1253                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1254         },
1255         /* Native multicast commands are not available for guests */
1256         {
1257                 .opcode = MLX4_CMD_QP_ATTACH,
1258                 .has_inbox = true,
1259                 .has_outbox = false,
1260                 .out_is_imm = false,
1261                 .encode_slave_id = false,
1262                 .verify = NULL,
1263                 .wrapper = mlx4_QP_ATTACH_wrapper
1264         },
1265         {
1266                 .opcode = MLX4_CMD_PROMISC,
1267                 .has_inbox = false,
1268                 .has_outbox = false,
1269                 .out_is_imm = false,
1270                 .encode_slave_id = false,
1271                 .verify = NULL,
1272                 .wrapper = mlx4_PROMISC_wrapper
1273         },
1274         /* Ethernet specific commands */
1275         {
1276                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1277                 .has_inbox = true,
1278                 .has_outbox = false,
1279                 .out_is_imm = false,
1280                 .encode_slave_id = false,
1281                 .verify = NULL,
1282                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1283         },
1284         {
1285                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1286                 .has_inbox = false,
1287                 .has_outbox = false,
1288                 .out_is_imm = false,
1289                 .encode_slave_id = false,
1290                 .verify = NULL,
1291                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1292         },
1293         {
1294                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1295                 .has_inbox = false,
1296                 .has_outbox = true,
1297                 .out_is_imm = false,
1298                 .encode_slave_id = false,
1299                 .verify = NULL,
1300                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1301         },
1302         {
1303                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1304                 .has_inbox = false,
1305                 .has_outbox = false,
1306                 .out_is_imm = false,
1307                 .encode_slave_id = false,
1308                 .verify = NULL,
1309                 .wrapper = NULL
1310         },
1311         /* flow steering commands */
1312         {
1313                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1314                 .has_inbox = true,
1315                 .has_outbox = false,
1316                 .out_is_imm = true,
1317                 .encode_slave_id = false,
1318                 .verify = NULL,
1319                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1320         },
1321         {
1322                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1323                 .has_inbox = false,
1324                 .has_outbox = false,
1325                 .out_is_imm = false,
1326                 .encode_slave_id = false,
1327                 .verify = NULL,
1328                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1329         },
1330 };
1331
1332 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1333                                     struct mlx4_vhcr_cmd *in_vhcr)
1334 {
1335         struct mlx4_priv *priv = mlx4_priv(dev);
1336         struct mlx4_cmd_info *cmd = NULL;
1337         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1338         struct mlx4_vhcr *vhcr;
1339         struct mlx4_cmd_mailbox *inbox = NULL;
1340         struct mlx4_cmd_mailbox *outbox = NULL;
1341         u64 in_param;
1342         u64 out_param;
1343         int ret = 0;
1344         int i;
1345         int err = 0;
1346
1347         /* Create sw representation of Virtual HCR */
1348         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1349         if (!vhcr)
1350                 return -ENOMEM;
1351
1352         /* DMA in the vHCR */
1353         if (!in_vhcr) {
1354                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1355                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1356                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1357                                             MLX4_ACCESS_MEM_ALIGN), 1);
1358                 if (ret) {
1359                         mlx4_err(dev, "%s:Failed reading vhcr"
1360                                  "ret: 0x%x\n", __func__, ret);
1361                         kfree(vhcr);
1362                         return ret;
1363                 }
1364         }
1365
1366         /* Fill SW VHCR fields */
1367         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1368         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1369         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1370         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1371         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1372         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1373         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1374
1375         /* Lookup command */
1376         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1377                 if (vhcr->op == cmd_info[i].opcode) {
1378                         cmd = &cmd_info[i];
1379                         break;
1380                 }
1381         }
1382         if (!cmd) {
1383                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1384                          vhcr->op, slave);
1385                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1386                 goto out_status;
1387         }
1388
1389         /* Read inbox */
1390         if (cmd->has_inbox) {
1391                 vhcr->in_param &= INBOX_MASK;
1392                 inbox = mlx4_alloc_cmd_mailbox(dev);
1393                 if (IS_ERR(inbox)) {
1394                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1395                         inbox = NULL;
1396                         goto out_status;
1397                 }
1398
1399                 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1400                                     vhcr->in_param,
1401                                     MLX4_MAILBOX_SIZE, 1)) {
1402                         mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1403                                  __func__, cmd->opcode);
1404                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1405                         goto out_status;
1406                 }
1407         }
1408
1409         /* Apply permission and bound checks if applicable */
1410         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1411                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1412                           "checks for resource_id:%d\n", vhcr->op, slave,
1413                           vhcr->in_modifier);
1414                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1415                 goto out_status;
1416         }
1417
1418         /* Allocate outbox */
1419         if (cmd->has_outbox) {
1420                 outbox = mlx4_alloc_cmd_mailbox(dev);
1421                 if (IS_ERR(outbox)) {
1422                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1423                         outbox = NULL;
1424                         goto out_status;
1425                 }
1426         }
1427
1428         /* Execute the command! */
1429         if (cmd->wrapper) {
1430                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1431                                    cmd);
1432                 if (cmd->out_is_imm)
1433                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1434         } else {
1435                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1436                         vhcr->in_param;
1437                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1438                         vhcr->out_param;
1439                 err = __mlx4_cmd(dev, in_param, &out_param,
1440                                  cmd->out_is_imm, vhcr->in_modifier,
1441                                  vhcr->op_modifier, vhcr->op,
1442                                  MLX4_CMD_TIME_CLASS_A,
1443                                  MLX4_CMD_NATIVE);
1444
1445                 if (cmd->out_is_imm) {
1446                         vhcr->out_param = out_param;
1447                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1448                 }
1449         }
1450
1451         if (err) {
1452                 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1453                           " error:%d, status %d\n",
1454                           vhcr->op, slave, vhcr->errno, err);
1455                 vhcr_cmd->status = mlx4_errno_to_status(err);
1456                 goto out_status;
1457         }
1458
1459
1460         /* Write outbox if command completed successfully */
1461         if (cmd->has_outbox && !vhcr_cmd->status) {
1462                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1463                                       vhcr->out_param,
1464                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1465                 if (ret) {
1466                         /* If we failed to write back the outbox after the
1467                          *command was successfully executed, we must fail this
1468                          * slave, as it is now in undefined state */
1469                         mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1470                         goto out;
1471                 }
1472         }
1473
1474 out_status:
1475         /* DMA back vhcr result */
1476         if (!in_vhcr) {
1477                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1478                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1479                                       ALIGN(sizeof(struct mlx4_vhcr),
1480                                             MLX4_ACCESS_MEM_ALIGN),
1481                                       MLX4_CMD_WRAPPED);
1482                 if (ret)
1483                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1484                                  __func__);
1485                 else if (vhcr->e_bit &&
1486                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1487                                 mlx4_warn(dev, "Failed to generate command completion "
1488                                           "eqe for slave %d\n", slave);
1489         }
1490
1491 out:
1492         kfree(vhcr);
1493         mlx4_free_cmd_mailbox(dev, inbox);
1494         mlx4_free_cmd_mailbox(dev, outbox);
1495         return ret;
1496 }
1497
1498 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1499 {
1500         int port, err;
1501         struct mlx4_vport_state *vp_admin;
1502         struct mlx4_vport_oper_state *vp_oper;
1503
1504         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1505                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1506                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1507                 vp_oper->state = *vp_admin;
1508                 if (MLX4_VGT != vp_admin->default_vlan) {
1509                         err = __mlx4_register_vlan(&priv->dev, port,
1510                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
1511                         if (err) {
1512                                 vp_oper->vlan_idx = NO_INDX;
1513                                 mlx4_warn((&priv->dev),
1514                                           "No vlan resorces slave %d, port %d\n",
1515                                           slave, port);
1516                                 return err;
1517                         }
1518                         mlx4_dbg((&(priv->dev)), "alloc vlan %d idx  %d slave %d port %d\n",
1519                                  (int)(vp_oper->state.default_vlan),
1520                                  vp_oper->vlan_idx, slave, port);
1521                 }
1522                 if (vp_admin->spoofchk) {
1523                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1524                                                                port,
1525                                                                vp_admin->mac);
1526                         if (0 > vp_oper->mac_idx) {
1527                                 err = vp_oper->mac_idx;
1528                                 vp_oper->mac_idx = NO_INDX;
1529                                 mlx4_warn((&priv->dev),
1530                                           "No mac resorces slave %d, port %d\n",
1531                                           slave, port);
1532                                 return err;
1533                         }
1534                         mlx4_dbg((&(priv->dev)), "alloc mac %llx idx  %d slave %d port %d\n",
1535                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1536                 }
1537         }
1538         return 0;
1539 }
1540
1541 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1542 {
1543         int port;
1544         struct mlx4_vport_oper_state *vp_oper;
1545
1546         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1547                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1548                 if (NO_INDX != vp_oper->vlan_idx) {
1549                         __mlx4_unregister_vlan(&priv->dev,
1550                                                port, vp_oper->vlan_idx);
1551                         vp_oper->vlan_idx = NO_INDX;
1552                 }
1553                 if (NO_INDX != vp_oper->mac_idx) {
1554                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->mac_idx);
1555                         vp_oper->mac_idx = NO_INDX;
1556                 }
1557         }
1558         return;
1559 }
1560
1561 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1562                                u16 param, u8 toggle)
1563 {
1564         struct mlx4_priv *priv = mlx4_priv(dev);
1565         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1566         u32 reply;
1567         u8 is_going_down = 0;
1568         int i;
1569         unsigned long flags;
1570
1571         slave_state[slave].comm_toggle ^= 1;
1572         reply = (u32) slave_state[slave].comm_toggle << 31;
1573         if (toggle != slave_state[slave].comm_toggle) {
1574                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1575                           "STATE COMPROMISIED ***\n", toggle, slave);
1576                 goto reset_slave;
1577         }
1578         if (cmd == MLX4_COMM_CMD_RESET) {
1579                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1580                 slave_state[slave].active = false;
1581                 mlx4_master_deactivate_admin_state(priv, slave);
1582                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1583                                 slave_state[slave].event_eq[i].eqn = -1;
1584                                 slave_state[slave].event_eq[i].token = 0;
1585                 }
1586                 /*check if we are in the middle of FLR process,
1587                 if so return "retry" status to the slave*/
1588                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1589                         goto inform_slave_state;
1590
1591                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1592
1593                 /* write the version in the event field */
1594                 reply |= mlx4_comm_get_version();
1595
1596                 goto reset_slave;
1597         }
1598         /*command from slave in the middle of FLR*/
1599         if (cmd != MLX4_COMM_CMD_RESET &&
1600             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1601                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1602                           "in the middle of FLR\n", slave, cmd);
1603                 return;
1604         }
1605
1606         switch (cmd) {
1607         case MLX4_COMM_CMD_VHCR0:
1608                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1609                         goto reset_slave;
1610                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1611                 priv->mfunc.master.slave_state[slave].cookie = 0;
1612                 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1613                 break;
1614         case MLX4_COMM_CMD_VHCR1:
1615                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1616                         goto reset_slave;
1617                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1618                 break;
1619         case MLX4_COMM_CMD_VHCR2:
1620                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1621                         goto reset_slave;
1622                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1623                 break;
1624         case MLX4_COMM_CMD_VHCR_EN:
1625                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1626                         goto reset_slave;
1627                 slave_state[slave].vhcr_dma |= param;
1628                 if (mlx4_master_activate_admin_state(priv, slave))
1629                                 goto reset_slave;
1630                 slave_state[slave].active = true;
1631                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1632                 break;
1633         case MLX4_COMM_CMD_VHCR_POST:
1634                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1635                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1636                         goto reset_slave;
1637
1638                 mutex_lock(&priv->cmd.slave_cmd_mutex);
1639                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1640                         mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1641                                  " resetting slave.\n", slave);
1642                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1643                         goto reset_slave;
1644                 }
1645                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1646                 break;
1647         default:
1648                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1649                 goto reset_slave;
1650         }
1651         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1652         if (!slave_state[slave].is_slave_going_down)
1653                 slave_state[slave].last_cmd = cmd;
1654         else
1655                 is_going_down = 1;
1656         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1657         if (is_going_down) {
1658                 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1659                           " executing from slave:%d\n",
1660                           cmd, slave);
1661                 return;
1662         }
1663         __raw_writel((__force u32) cpu_to_be32(reply),
1664                      &priv->mfunc.comm[slave].slave_read);
1665         mmiowb();
1666
1667         return;
1668
1669 reset_slave:
1670         /* cleanup any slave resources */
1671         mlx4_delete_all_resources_for_slave(dev, slave);
1672         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1673         if (!slave_state[slave].is_slave_going_down)
1674                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1675         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1676         /*with slave in the middle of flr, no need to clean resources again.*/
1677 inform_slave_state:
1678         memset(&slave_state[slave].event_eq, 0,
1679                sizeof(struct mlx4_slave_event_eq_info));
1680         __raw_writel((__force u32) cpu_to_be32(reply),
1681                      &priv->mfunc.comm[slave].slave_read);
1682         wmb();
1683 }
1684
1685 /* master command processing */
1686 void mlx4_master_comm_channel(struct work_struct *work)
1687 {
1688         struct mlx4_mfunc_master_ctx *master =
1689                 container_of(work,
1690                              struct mlx4_mfunc_master_ctx,
1691                              comm_work);
1692         struct mlx4_mfunc *mfunc =
1693                 container_of(master, struct mlx4_mfunc, master);
1694         struct mlx4_priv *priv =
1695                 container_of(mfunc, struct mlx4_priv, mfunc);
1696         struct mlx4_dev *dev = &priv->dev;
1697         __be32 *bit_vec;
1698         u32 comm_cmd;
1699         u32 vec;
1700         int i, j, slave;
1701         int toggle;
1702         int served = 0;
1703         int reported = 0;
1704         u32 slt;
1705
1706         bit_vec = master->comm_arm_bit_vector;
1707         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1708                 vec = be32_to_cpu(bit_vec[i]);
1709                 for (j = 0; j < 32; j++) {
1710                         if (!(vec & (1 << j)))
1711                                 continue;
1712                         ++reported;
1713                         slave = (i * 32) + j;
1714                         comm_cmd = swab32(readl(
1715                                           &mfunc->comm[slave].slave_write));
1716                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
1717                                      >> 31;
1718                         toggle = comm_cmd >> 31;
1719                         if (toggle != slt) {
1720                                 if (master->slave_state[slave].comm_toggle
1721                                     != slt) {
1722                                         printk(KERN_INFO "slave %d out of sync."
1723                                                " read toggle %d, state toggle %d. "
1724                                                "Resynching.\n", slave, slt,
1725                                                master->slave_state[slave].comm_toggle);
1726                                         master->slave_state[slave].comm_toggle =
1727                                                 slt;
1728                                 }
1729                                 mlx4_master_do_cmd(dev, slave,
1730                                                    comm_cmd >> 16 & 0xff,
1731                                                    comm_cmd & 0xffff, toggle);
1732                                 ++served;
1733                         }
1734                 }
1735         }
1736
1737         if (reported && reported != served)
1738                 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1739                           " but %d were served\n",
1740                           reported, served);
1741
1742         if (mlx4_ARM_COMM_CHANNEL(dev))
1743                 mlx4_warn(dev, "Failed to arm comm channel events\n");
1744 }
1745
1746 static int sync_toggles(struct mlx4_dev *dev)
1747 {
1748         struct mlx4_priv *priv = mlx4_priv(dev);
1749         int wr_toggle;
1750         int rd_toggle;
1751         unsigned long end;
1752
1753         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1754         end = jiffies + msecs_to_jiffies(5000);
1755
1756         while (time_before(jiffies, end)) {
1757                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1758                 if (rd_toggle == wr_toggle) {
1759                         priv->cmd.comm_toggle = rd_toggle;
1760                         return 0;
1761                 }
1762
1763                 cond_resched();
1764         }
1765
1766         /*
1767          * we could reach here if for example the previous VM using this
1768          * function misbehaved and left the channel with unsynced state. We
1769          * should fix this here and give this VM a chance to use a properly
1770          * synced channel
1771          */
1772         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1773         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1774         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1775         priv->cmd.comm_toggle = 0;
1776
1777         return 0;
1778 }
1779
1780 int mlx4_multi_func_init(struct mlx4_dev *dev)
1781 {
1782         struct mlx4_priv *priv = mlx4_priv(dev);
1783         struct mlx4_slave_state *s_state;
1784         int i, j, err, port;
1785
1786         if (mlx4_is_master(dev))
1787                 priv->mfunc.comm =
1788                 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1789                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1790         else
1791                 priv->mfunc.comm =
1792                 ioremap(pci_resource_start(dev->pdev, 2) +
1793                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1794         if (!priv->mfunc.comm) {
1795                 mlx4_err(dev, "Couldn't map communication vector.\n");
1796                 goto err_vhcr;
1797         }
1798
1799         if (mlx4_is_master(dev)) {
1800                 priv->mfunc.master.slave_state =
1801                         kzalloc(dev->num_slaves *
1802                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1803                 if (!priv->mfunc.master.slave_state)
1804                         goto err_comm;
1805
1806                 priv->mfunc.master.vf_admin =
1807                         kzalloc(dev->num_slaves *
1808                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1809                 if (!priv->mfunc.master.vf_admin)
1810                         goto err_comm_admin;
1811
1812                 priv->mfunc.master.vf_oper =
1813                         kzalloc(dev->num_slaves *
1814                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1815                 if (!priv->mfunc.master.vf_oper)
1816                         goto err_comm_oper;
1817
1818                 for (i = 0; i < dev->num_slaves; ++i) {
1819                         s_state = &priv->mfunc.master.slave_state[i];
1820                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
1821                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1822                                 s_state->event_eq[j].eqn = -1;
1823                         __raw_writel((__force u32) 0,
1824                                      &priv->mfunc.comm[i].slave_write);
1825                         __raw_writel((__force u32) 0,
1826                                      &priv->mfunc.comm[i].slave_read);
1827                         mmiowb();
1828                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1829                                 s_state->vlan_filter[port] =
1830                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
1831                                                 GFP_KERNEL);
1832                                 if (!s_state->vlan_filter[port]) {
1833                                         if (--port)
1834                                                 kfree(s_state->vlan_filter[port]);
1835                                         goto err_slaves;
1836                                 }
1837                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1838                                 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
1839                                 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
1840                                 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1841                                 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
1842                         }
1843                         spin_lock_init(&s_state->lock);
1844                 }
1845
1846                 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1847                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1848                 INIT_WORK(&priv->mfunc.master.comm_work,
1849                           mlx4_master_comm_channel);
1850                 INIT_WORK(&priv->mfunc.master.slave_event_work,
1851                           mlx4_gen_slave_eqe);
1852                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1853                           mlx4_master_handle_slave_flr);
1854                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1855                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1856                 priv->mfunc.master.comm_wq =
1857                         create_singlethread_workqueue("mlx4_comm");
1858                 if (!priv->mfunc.master.comm_wq)
1859                         goto err_slaves;
1860
1861                 if (mlx4_init_resource_tracker(dev))
1862                         goto err_thread;
1863
1864                 err = mlx4_ARM_COMM_CHANNEL(dev);
1865                 if (err) {
1866                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1867                                  err);
1868                         goto err_resource;
1869                 }
1870
1871         } else {
1872                 err = sync_toggles(dev);
1873                 if (err) {
1874                         mlx4_err(dev, "Couldn't sync toggles\n");
1875                         goto err_comm;
1876                 }
1877         }
1878         return 0;
1879
1880 err_resource:
1881         mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1882 err_thread:
1883         flush_workqueue(priv->mfunc.master.comm_wq);
1884         destroy_workqueue(priv->mfunc.master.comm_wq);
1885 err_slaves:
1886         while (--i) {
1887                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1888                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1889         }
1890         kfree(priv->mfunc.master.vf_oper);
1891 err_comm_oper:
1892         kfree(priv->mfunc.master.vf_admin);
1893 err_comm_admin:
1894         kfree(priv->mfunc.master.slave_state);
1895 err_comm:
1896         iounmap(priv->mfunc.comm);
1897 err_vhcr:
1898         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1899                                              priv->mfunc.vhcr,
1900                                              priv->mfunc.vhcr_dma);
1901         priv->mfunc.vhcr = NULL;
1902         return -ENOMEM;
1903 }
1904
1905 int mlx4_cmd_init(struct mlx4_dev *dev)
1906 {
1907         struct mlx4_priv *priv = mlx4_priv(dev);
1908
1909         mutex_init(&priv->cmd.hcr_mutex);
1910         mutex_init(&priv->cmd.slave_cmd_mutex);
1911         sema_init(&priv->cmd.poll_sem, 1);
1912         priv->cmd.use_events = 0;
1913         priv->cmd.toggle     = 1;
1914
1915         priv->cmd.hcr = NULL;
1916         priv->mfunc.vhcr = NULL;
1917
1918         if (!mlx4_is_slave(dev)) {
1919                 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1920                                         MLX4_HCR_BASE, MLX4_HCR_SIZE);
1921                 if (!priv->cmd.hcr) {
1922                         mlx4_err(dev, "Couldn't map command register.\n");
1923                         return -ENOMEM;
1924                 }
1925         }
1926
1927         if (mlx4_is_mfunc(dev)) {
1928                 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1929                                                       &priv->mfunc.vhcr_dma,
1930                                                       GFP_KERNEL);
1931                 if (!priv->mfunc.vhcr)
1932                         goto err_hcr;
1933         }
1934
1935         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1936                                          MLX4_MAILBOX_SIZE,
1937                                          MLX4_MAILBOX_SIZE, 0);
1938         if (!priv->cmd.pool)
1939                 goto err_vhcr;
1940
1941         return 0;
1942
1943 err_vhcr:
1944         if (mlx4_is_mfunc(dev))
1945                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1946                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1947         priv->mfunc.vhcr = NULL;
1948
1949 err_hcr:
1950         if (!mlx4_is_slave(dev))
1951                 iounmap(priv->cmd.hcr);
1952         return -ENOMEM;
1953 }
1954
1955 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1956 {
1957         struct mlx4_priv *priv = mlx4_priv(dev);
1958         int i, port;
1959
1960         if (mlx4_is_master(dev)) {
1961                 flush_workqueue(priv->mfunc.master.comm_wq);
1962                 destroy_workqueue(priv->mfunc.master.comm_wq);
1963                 for (i = 0; i < dev->num_slaves; i++) {
1964                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
1965                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1966                 }
1967                 kfree(priv->mfunc.master.slave_state);
1968                 kfree(priv->mfunc.master.vf_admin);
1969                 kfree(priv->mfunc.master.vf_oper);
1970         }
1971
1972         iounmap(priv->mfunc.comm);
1973 }
1974
1975 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1976 {
1977         struct mlx4_priv *priv = mlx4_priv(dev);
1978
1979         pci_pool_destroy(priv->cmd.pool);
1980
1981         if (!mlx4_is_slave(dev))
1982                 iounmap(priv->cmd.hcr);
1983         if (mlx4_is_mfunc(dev))
1984                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1985                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1986         priv->mfunc.vhcr = NULL;
1987 }
1988
1989 /*
1990  * Switch to using events to issue FW commands (can only be called
1991  * after event queue for command events has been initialized).
1992  */
1993 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1994 {
1995         struct mlx4_priv *priv = mlx4_priv(dev);
1996         int i;
1997         int err = 0;
1998
1999         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2000                                    sizeof (struct mlx4_cmd_context),
2001                                    GFP_KERNEL);
2002         if (!priv->cmd.context)
2003                 return -ENOMEM;
2004
2005         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2006                 priv->cmd.context[i].token = i;
2007                 priv->cmd.context[i].next  = i + 1;
2008         }
2009
2010         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2011         priv->cmd.free_head = 0;
2012
2013         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2014         spin_lock_init(&priv->cmd.context_lock);
2015
2016         for (priv->cmd.token_mask = 1;
2017              priv->cmd.token_mask < priv->cmd.max_cmds;
2018              priv->cmd.token_mask <<= 1)
2019                 ; /* nothing */
2020         --priv->cmd.token_mask;
2021
2022         down(&priv->cmd.poll_sem);
2023         priv->cmd.use_events = 1;
2024
2025         return err;
2026 }
2027
2028 /*
2029  * Switch back to polling (used when shutting down the device)
2030  */
2031 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2032 {
2033         struct mlx4_priv *priv = mlx4_priv(dev);
2034         int i;
2035
2036         priv->cmd.use_events = 0;
2037
2038         for (i = 0; i < priv->cmd.max_cmds; ++i)
2039                 down(&priv->cmd.event_sem);
2040
2041         kfree(priv->cmd.context);
2042
2043         up(&priv->cmd.poll_sem);
2044 }
2045
2046 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2047 {
2048         struct mlx4_cmd_mailbox *mailbox;
2049
2050         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2051         if (!mailbox)
2052                 return ERR_PTR(-ENOMEM);
2053
2054         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2055                                       &mailbox->dma);
2056         if (!mailbox->buf) {
2057                 kfree(mailbox);
2058                 return ERR_PTR(-ENOMEM);
2059         }
2060
2061         return mailbox;
2062 }
2063 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2064
2065 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2066                            struct mlx4_cmd_mailbox *mailbox)
2067 {
2068         if (!mailbox)
2069                 return;
2070
2071         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2072         kfree(mailbox);
2073 }
2074 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2075
2076 u32 mlx4_comm_get_version(void)
2077 {
2078          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2079 }
2080
2081 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2082 {
2083         if ((vf < 0) || (vf >= dev->num_vfs)) {
2084                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2085                 return -EINVAL;
2086         }
2087
2088         return vf+1;
2089 }
2090
2091 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2092 {
2093         struct mlx4_priv *priv = mlx4_priv(dev);
2094         struct mlx4_vport_state *s_info;
2095         int slave;
2096
2097         if (!mlx4_is_master(dev))
2098                 return -EPROTONOSUPPORT;
2099
2100         slave = mlx4_get_slave_indx(dev, vf);
2101         if (slave < 0)
2102                 return -EINVAL;
2103
2104         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2105         s_info->mac = mac;
2106         mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2107                   vf, port, s_info->mac);
2108         return 0;
2109 }
2110 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2111
2112 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2113 {
2114         struct mlx4_priv *priv = mlx4_priv(dev);
2115         struct mlx4_vport_state *s_info;
2116         int slave;
2117
2118         if ((!mlx4_is_master(dev)) ||
2119             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2120                 return -EPROTONOSUPPORT;
2121
2122         if ((vlan > 4095) || (qos > 7))
2123                 return -EINVAL;
2124
2125         slave = mlx4_get_slave_indx(dev, vf);
2126         if (slave < 0)
2127                 return -EINVAL;
2128
2129         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2130         if ((0 == vlan) && (0 == qos))
2131                 s_info->default_vlan = MLX4_VGT;
2132         else
2133                 s_info->default_vlan = vlan;
2134         s_info->default_qos = qos;
2135         return 0;
2136 }
2137 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2138
2139 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2140 {
2141         struct mlx4_priv *priv = mlx4_priv(dev);
2142         struct mlx4_vport_state *s_info;
2143         int slave;
2144
2145         if ((!mlx4_is_master(dev)) ||
2146             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2147                 return -EPROTONOSUPPORT;
2148
2149         slave = mlx4_get_slave_indx(dev, vf);
2150         if (slave < 0)
2151                 return -EINVAL;
2152
2153         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2154         s_info->spoofchk = setting;
2155
2156         return 0;
2157 }
2158 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2159
2160 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2161 {
2162         struct mlx4_priv *priv = mlx4_priv(dev);
2163         struct mlx4_vport_state *s_info;
2164         int slave;
2165
2166         if (!mlx4_is_master(dev))
2167                 return -EPROTONOSUPPORT;
2168
2169         slave = mlx4_get_slave_indx(dev, vf);
2170         if (slave < 0)
2171                 return -EINVAL;
2172
2173         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2174         ivf->vf = vf;
2175
2176         /* need to convert it to a func */
2177         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2178         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2179         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2180         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2181         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2182         ivf->mac[5] = ((s_info->mac)  & 0xff);
2183
2184         ivf->vlan       = s_info->default_vlan;
2185         ivf->qos        = s_info->default_qos;
2186         ivf->tx_rate    = s_info->tx_rate;
2187         ivf->spoofchk   = s_info->spoofchk;
2188         ivf->linkstate  = s_info->link_state;
2189
2190         return 0;
2191 }
2192 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2193
2194 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2195 {
2196         struct mlx4_priv *priv = mlx4_priv(dev);
2197         struct mlx4_vport_state *s_info;
2198         struct mlx4_vport_oper_state *vp_oper;
2199         int slave;
2200         u8 link_stat_event;
2201
2202         slave = mlx4_get_slave_indx(dev, vf);
2203         if (slave < 0)
2204                 return -EINVAL;
2205
2206         switch (link_state) {
2207         case IFLA_VF_LINK_STATE_AUTO:
2208                 /* get current link state */
2209                 if (!priv->sense.do_sense_port[port])
2210                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2211                 else
2212                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2213             break;
2214
2215         case IFLA_VF_LINK_STATE_ENABLE:
2216                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2217             break;
2218
2219         case IFLA_VF_LINK_STATE_DISABLE:
2220                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2221             break;
2222
2223         default:
2224                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2225                           link_state, slave, port);
2226                 return -EINVAL;
2227         };
2228         /* update the admin & oper state on the link state */
2229         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2230         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2231         s_info->link_state = link_state;
2232         vp_oper->state.link_state = link_state;
2233
2234         /* send event */
2235         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2236         return 0;
2237 }
2238 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);