2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/cmd.h>
44 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
45 u64 mac, u64 clear, u8 mode)
47 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
48 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
52 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
54 struct mlx4_cmd_mailbox *mailbox;
55 struct mlx4_set_vlan_fltr_mbox *filter;
62 mailbox = mlx4_alloc_cmd_mailbox(dev);
64 return PTR_ERR(mailbox);
66 filter = mailbox->buf;
67 memset(filter, 0, sizeof(*filter));
68 for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
70 for (j = 0; j < 32; j++)
71 if (test_bit(index++, priv->active_vlans))
73 filter->entry[i] = cpu_to_be32(entry);
75 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
76 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
77 mlx4_free_cmd_mailbox(dev, mailbox);
82 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
83 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
85 struct mlx4_cmd_mailbox *mailbox;
86 struct mlx4_set_port_general_context *context;
90 mailbox = mlx4_alloc_cmd_mailbox(dev);
92 return PTR_ERR(mailbox);
93 context = mailbox->buf;
94 memset(context, 0, sizeof *context);
96 context->flags = SET_PORT_GEN_ALL_VALID;
97 context->mtu = cpu_to_be16(mtu);
98 context->pptx = (pptx * (!pfctx)) << 7;
99 context->pfctx = pfctx;
100 context->pprx = (pprx * (!pfcrx)) << 7;
101 context->pfcrx = pfcrx;
103 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
104 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
105 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
107 mlx4_free_cmd_mailbox(dev, mailbox);
111 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
114 struct mlx4_cmd_mailbox *mailbox;
115 struct mlx4_set_port_rqp_calc_context *context;
118 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
119 MCAST_DIRECT : MCAST_DEFAULT;
121 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER &&
122 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)
125 mailbox = mlx4_alloc_cmd_mailbox(dev);
127 return PTR_ERR(mailbox);
128 context = mailbox->buf;
129 memset(context, 0, sizeof *context);
131 context->base_qpn = cpu_to_be32(base_qpn);
132 context->n_mac = dev->caps.log_num_macs;
133 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
135 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
137 context->intra_no_vlan = 0;
138 context->no_vlan = MLX4_NO_VLAN_IDX;
139 context->intra_vlan_miss = 0;
140 context->vlan_miss = MLX4_VLAN_MISS_IDX;
142 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
143 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
144 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
146 mlx4_free_cmd_mailbox(dev, mailbox);
150 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
152 struct mlx4_en_query_port_context *qport_context;
153 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
154 struct mlx4_en_port_state *state = &priv->port_state;
155 struct mlx4_cmd_mailbox *mailbox;
158 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
160 return PTR_ERR(mailbox);
161 memset(mailbox->buf, 0, sizeof(*qport_context));
162 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
163 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
167 qport_context = mailbox->buf;
169 /* This command is always accessed from Ethtool context
170 * already synchronized, no need in locking */
171 state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
172 switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
173 case MLX4_EN_1G_SPEED:
174 state->link_speed = 1000;
176 case MLX4_EN_10G_SPEED_XAUI:
177 case MLX4_EN_10G_SPEED_XFI:
178 state->link_speed = 10000;
180 case MLX4_EN_40G_SPEED:
181 state->link_speed = 40000;
184 state->link_speed = -1;
187 state->transciver = qport_context->transceiver;
190 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
194 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
196 struct mlx4_en_stat_out_mbox *mlx4_en_stats;
197 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
198 struct net_device_stats *stats = &priv->stats;
199 struct mlx4_cmd_mailbox *mailbox;
200 u64 in_mod = reset << 8 | port;
204 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
206 return PTR_ERR(mailbox);
207 memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
208 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
209 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
214 mlx4_en_stats = mailbox->buf;
216 spin_lock_bh(&priv->stats_lock);
218 stats->rx_packets = 0;
220 priv->port_stats.rx_chksum_good = 0;
221 priv->port_stats.rx_chksum_none = 0;
222 for (i = 0; i < priv->rx_ring_num; i++) {
223 stats->rx_packets += priv->rx_ring[i].packets;
224 stats->rx_bytes += priv->rx_ring[i].bytes;
225 priv->port_stats.rx_chksum_good += priv->rx_ring[i].csum_ok;
226 priv->port_stats.rx_chksum_none += priv->rx_ring[i].csum_none;
228 stats->tx_packets = 0;
230 priv->port_stats.tx_chksum_offload = 0;
231 for (i = 0; i < priv->tx_ring_num; i++) {
232 stats->tx_packets += priv->tx_ring[i].packets;
233 stats->tx_bytes += priv->tx_ring[i].bytes;
234 priv->port_stats.tx_chksum_offload += priv->tx_ring[i].tx_csum;
237 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
238 be32_to_cpu(mlx4_en_stats->RdropLength) +
239 be32_to_cpu(mlx4_en_stats->RJBBR) +
240 be32_to_cpu(mlx4_en_stats->RCRC) +
241 be32_to_cpu(mlx4_en_stats->RRUNT);
242 stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP);
243 stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
244 be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
245 be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
246 be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
247 be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
248 be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
249 be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
250 be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
251 be64_to_cpu(mlx4_en_stats->MCAST_novlan);
252 stats->collisions = 0;
253 stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
254 stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
255 stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
256 stats->rx_frame_errors = 0;
257 stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
258 stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
259 stats->tx_aborted_errors = 0;
260 stats->tx_carrier_errors = 0;
261 stats->tx_fifo_errors = 0;
262 stats->tx_heartbeat_errors = 0;
263 stats->tx_window_errors = 0;
265 priv->pkstats.broadcast =
266 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
267 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
268 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
269 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
270 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
271 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
272 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
273 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
274 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
275 priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
276 priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
277 priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
278 priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
279 priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
280 priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
281 priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
282 priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
283 priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
284 priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
285 priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
286 priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
287 priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
288 priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
289 priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
290 priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
291 spin_unlock_bh(&priv->stats_lock);
294 mlx4_free_cmd_mailbox(mdev->dev, mailbox);