drivers/net/ethernet/mellanox/mlx4/eq.c

   1 /*
   2  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/interrupt.h>
  35 #include <linux/slab.h>
  36 #include <linux/export.h>
  37 #include <linux/mm.h>
  38 #include <linux/dma-mapping.h>
  39
  40 #include <linux/mlx4/cmd.h>
  41 #include <linux/cpu_rmap.h>
  42
  43 #include "mlx4.h"
  44 #include "fw.h"
  45
  46 enum {
  47         MLX4_IRQNAME_SIZE       = 32
  48 };
  49
  50 enum {
  51         MLX4_NUM_ASYNC_EQE      = 0x100,
  52         MLX4_NUM_SPARE_EQE      = 0x80,
  53         MLX4_EQ_ENTRY_SIZE      = 0x20
  54 };
  55
  56 #define MLX4_EQ_STATUS_OK          ( 0 << 28)
  57 #define MLX4_EQ_STATUS_WRITE_FAIL  (10 << 28)
  58 #define MLX4_EQ_OWNER_SW           ( 0 << 24)
  59 #define MLX4_EQ_OWNER_HW           ( 1 << 24)
  60 #define MLX4_EQ_FLAG_EC            ( 1 << 18)
  61 #define MLX4_EQ_FLAG_OI            ( 1 << 17)
  62 #define MLX4_EQ_STATE_ARMED        ( 9 <<  8)
  63 #define MLX4_EQ_STATE_FIRED        (10 <<  8)
  64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 <<  8)
  65
  66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG)           | \
  67                                (1ull << MLX4_EVENT_TYPE_COMM_EST)           | \
  68                                (1ull << MLX4_EVENT_TYPE_SQ_DRAINED)         | \
  69                                (1ull << MLX4_EVENT_TYPE_CQ_ERROR)           | \
  70                                (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  71                                (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR)    | \
  72                                (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED)    | \
  73                                (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  74                                (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  75                                (1ull << MLX4_EVENT_TYPE_PORT_CHANGE)        | \
  76                                (1ull << MLX4_EVENT_TYPE_ECC_DETECT)         | \
  77                                (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  78                                (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE)    | \
  79                                (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT)          | \
  80                                (1ull << MLX4_EVENT_TYPE_CMD)                | \
  81                                (1ull << MLX4_EVENT_TYPE_OP_REQUIRED)        | \
  82                                (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL)       | \
  83                                (1ull << MLX4_EVENT_TYPE_FLR_EVENT)          | \
  84                                (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
  85
  86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
  87 {
  88         u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
  89         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
  90                 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
  91
  92         return async_ev_mask;
  93 }
  94
  95 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
  96 {
  97         __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
  98                                                req_not << 31),
  99                      eq->doorbell);
 100         /* We still want ordering, just not swabbing, so add a barrier */
 101         mb();
 102 }
 103
 104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
 105                                 u8 eqe_size)
 106 {
 107         /* (entry & (eq->nent - 1)) gives us a cyclic array */
 108         unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
 109         /* CX3 is capable of extending the EQE from 32 to 64 bytes with
 110          * strides of 64B,128B and 256B.
 111          * When 64B EQE is used, the first (in the lower addresses)
 112          * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
 113          * contain the legacy EQE information.
 114          * In all other cases, the first 32B contains the legacy EQE info.
 115          */
 116         return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
 117 }
 118
 119 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
 120 {
 121         struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
 122         return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
 123 }
 124
 125 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
 126 {
 127         struct mlx4_eqe *eqe =
 128                 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
 129         return (!!(eqe->owner & 0x80) ^
 130                 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
 131                 eqe : NULL;
 132 }
 133
 134 void mlx4_gen_slave_eqe(struct work_struct *work)
 135 {
 136         struct mlx4_mfunc_master_ctx *master =
 137                 container_of(work, struct mlx4_mfunc_master_ctx,
 138                              slave_event_work);
 139         struct mlx4_mfunc *mfunc =
 140                 container_of(master, struct mlx4_mfunc, master);
 141         struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
 142         struct mlx4_dev *dev = &priv->dev;
 143         struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
 144         struct mlx4_eqe *eqe;
 145         u8 slave;
 146         int i;
 147
 148         for (eqe = next_slave_event_eqe(slave_eq); eqe;
 149               eqe = next_slave_event_eqe(slave_eq)) {
 150                 slave = eqe->slave_id;
 151
 152                 /* All active slaves need to receive the event */
 153                 if (slave == ALL_SLAVES) {
 154                         for (i = 0; i < dev->num_slaves; i++) {
 155                                 if (i != dev->caps.function &&
 156                                     master->slave_state[i].active)
 157                                         if (mlx4_GEN_EQE(dev, i, eqe))
 158                                                 mlx4_warn(dev, "Failed to generate event for slave %d\n",
 159                                                           i);
 160                         }
 161                 } else {
 162                         if (mlx4_GEN_EQE(dev, slave, eqe))
 163                                 mlx4_warn(dev, "Failed to generate event for slave %d\n",
 164                                           slave);
 165                 }
 166                 ++slave_eq->cons;
 167         }
 168 }
 169
 170
 171 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
 172 {
 173         struct mlx4_priv *priv = mlx4_priv(dev);
 174         struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
 175         struct mlx4_eqe *s_eqe;
 176         unsigned long flags;
 177
 178         spin_lock_irqsave(&slave_eq->event_lock, flags);
 179         s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
 180         if ((!!(s_eqe->owner & 0x80)) ^
 181             (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
 182                 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
 183                           slave);
 184                 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
 185                 return;
 186         }
 187
 188         memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
 189         s_eqe->slave_id = slave;
 190         /* ensure all information is written before setting the ownersip bit */
 191         wmb();
 192         s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
 193         ++slave_eq->prod;
 194
 195         queue_work(priv->mfunc.master.comm_wq,
 196                    &priv->mfunc.master.slave_event_work);
 197         spin_unlock_irqrestore(&slave_eq->event_lock, flags);
 198 }
 199
 200 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
 201                              struct mlx4_eqe *eqe)
 202 {
 203         struct mlx4_priv *priv = mlx4_priv(dev);
 204         struct mlx4_slave_state *s_slave =
 205                 &priv->mfunc.master.slave_state[slave];
 206
 207         if (!s_slave->active) {
 208                 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
 209                 return;
 210         }
 211
 212         slave_event(dev, slave, eqe);
 213 }
 214
 215 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
 216 {
 217         struct mlx4_eqe eqe;
 218
 219         struct mlx4_priv *priv = mlx4_priv(dev);
 220         struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
 221
 222         if (!s_slave->active)
 223                 return 0;
 224
 225         memset(&eqe, 0, sizeof eqe);
 226
 227         eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
 228         eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
 229         eqe.event.port_mgmt_change.port = port;
 230
 231         return mlx4_GEN_EQE(dev, slave, &eqe);
 232 }
 233 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
 234
 235 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
 236 {
 237         struct mlx4_eqe eqe;
 238
 239         /*don't send if we don't have the that slave */
 240         if (dev->persist->num_vfs < slave)
 241                 return 0;
 242         memset(&eqe, 0, sizeof eqe);
 243
 244         eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
 245         eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
 246         eqe.event.port_mgmt_change.port = port;
 247
 248         return mlx4_GEN_EQE(dev, slave, &eqe);
 249 }
 250 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
 251
 252 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
 253                                    u8 port_subtype_change)
 254 {
 255         struct mlx4_eqe eqe;
 256
 257         /*don't send if we don't have the that slave */
 258         if (dev->persist->num_vfs < slave)
 259                 return 0;
 260         memset(&eqe, 0, sizeof eqe);
 261
 262         eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
 263         eqe.subtype = port_subtype_change;
 264         eqe.event.port_change.port = cpu_to_be32(port << 28);
 265
 266         mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
 267                  port_subtype_change, slave, port);
 268         return mlx4_GEN_EQE(dev, slave, &eqe);
 269 }
 270 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
 271
 272 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
 273 {
 274         struct mlx4_priv *priv = mlx4_priv(dev);
 275         struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
 276         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
 277
 278         if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
 279             port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
 280                 pr_err("%s: Error: asking for slave:%d, port:%d\n",
 281                        __func__, slave, port);
 282                 return SLAVE_PORT_DOWN;
 283         }
 284         return s_state[slave].port_state[port];
 285 }
 286 EXPORT_SYMBOL(mlx4_get_slave_port_state);
 287
 288 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
 289                                      enum slave_port_state state)
 290 {
 291         struct mlx4_priv *priv = mlx4_priv(dev);
 292         struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
 293         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
 294
 295         if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
 296             port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
 297                 pr_err("%s: Error: asking for slave:%d, port:%d\n",
 298                        __func__, slave, port);
 299                 return -1;
 300         }
 301         s_state[slave].port_state[port] = state;
 302
 303         return 0;
 304 }
 305
 306 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
 307 {
 308         int i;
 309         enum slave_port_gen_event gen_event;
 310         struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
 311                                                                           port);
 312
 313         for (i = 0; i < dev->persist->num_vfs + 1; i++)
 314                 if (test_bit(i, slaves_pport.slaves))
 315                         set_and_calc_slave_port_state(dev, i, port,
 316                                                       event, &gen_event);
 317 }
 318 /**************************************************************************
 319         The function get as input the new event to that port,
 320         and according to the prev state change the slave's port state.
 321         The events are:
 322                 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
 323                 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
 324                 MLX4_PORT_STATE_IB_EVENT_GID_VALID
 325                 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
 326 ***************************************************************************/
 327 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
 328                                   u8 port, int event,
 329                                   enum slave_port_gen_event *gen_event)
 330 {
 331         struct mlx4_priv *priv = mlx4_priv(dev);
 332         struct mlx4_slave_state *ctx = NULL;
 333         unsigned long flags;
 334         int ret = -1;
 335         struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
 336         enum slave_port_state cur_state =
 337                 mlx4_get_slave_port_state(dev, slave, port);
 338
 339         *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
 340
 341         if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
 342             port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
 343                 pr_err("%s: Error: asking for slave:%d, port:%d\n",
 344                        __func__, slave, port);
 345                 return ret;
 346         }
 347
 348         ctx = &priv->mfunc.master.slave_state[slave];
 349         spin_lock_irqsave(&ctx->lock, flags);
 350
 351         switch (cur_state) {
 352         case SLAVE_PORT_DOWN:
 353                 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
 354                         mlx4_set_slave_port_state(dev, slave, port,
 355                                                   SLAVE_PENDING_UP);
 356                 break;
 357         case SLAVE_PENDING_UP:
 358                 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
 359                         mlx4_set_slave_port_state(dev, slave, port,
 360                                                   SLAVE_PORT_DOWN);
 361                 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
 362                         mlx4_set_slave_port_state(dev, slave, port,
 363                                                   SLAVE_PORT_UP);
 364                         *gen_event = SLAVE_PORT_GEN_EVENT_UP;
 365                 }
 366                 break;
 367         case SLAVE_PORT_UP:
 368                 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
 369                         mlx4_set_slave_port_state(dev, slave, port,
 370                                                   SLAVE_PORT_DOWN);
 371                         *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
 372                 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
 373                                 event) {
 374                         mlx4_set_slave_port_state(dev, slave, port,
 375                                                   SLAVE_PENDING_UP);
 376                         *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
 377                 }
 378                 break;
 379         default:
 380                 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
 381                        __func__, slave, port);
 382                 goto out;
 383         }
 384         ret = mlx4_get_slave_port_state(dev, slave, port);
 385
 386 out:
 387         spin_unlock_irqrestore(&ctx->lock, flags);
 388         return ret;
 389 }
 390
 391 EXPORT_SYMBOL(set_and_calc_slave_port_state);
 392
 393 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
 394 {
 395         struct mlx4_eqe eqe;
 396
 397         memset(&eqe, 0, sizeof eqe);
 398
 399         eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
 400         eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
 401         eqe.event.port_mgmt_change.port = port;
 402         eqe.event.port_mgmt_change.params.port_info.changed_attr =
 403                 cpu_to_be32((u32) attr);
 404
 405         slave_event(dev, ALL_SLAVES, &eqe);
 406         return 0;
 407 }
 408 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
 409
 410 void mlx4_master_handle_slave_flr(struct work_struct *work)
 411 {
 412         struct mlx4_mfunc_master_ctx *master =
 413                 container_of(work, struct mlx4_mfunc_master_ctx,
 414                              slave_flr_event_work);
 415         struct mlx4_mfunc *mfunc =
 416                 container_of(master, struct mlx4_mfunc, master);
 417         struct mlx4_priv *priv =
 418                 container_of(mfunc, struct mlx4_priv, mfunc);
 419         struct mlx4_dev *dev = &priv->dev;
 420         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
 421         int i;
 422         int err;
 423         unsigned long flags;
 424
 425         mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
 426
 427         for (i = 0 ; i < dev->num_slaves; i++) {
 428
 429                 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
 430                         mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
 431                                  i);
 432                         /* In case of 'Reset flow' FLR can be generated for
 433                          * a slave before mlx4_load_one is done.
 434                          * make sure interface is up before trying to delete
 435                          * slave resources which weren't allocated yet.
 436                          */
 437                         if (dev->persist->interface_state &
 438                             MLX4_INTERFACE_STATE_UP)
 439                                 mlx4_delete_all_resources_for_slave(dev, i);
 440                         /*return the slave to running mode*/
 441                         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
 442                         slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
 443                         slave_state[i].is_slave_going_down = 0;
 444                         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
 445                         /*notify the FW:*/
 446                         err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
 447                                        MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 448                         if (err)
 449                                 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
 450                                           i);
 451                 }
 452         }
 453 }
 454
 455 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
 456 {
 457         struct mlx4_priv *priv = mlx4_priv(dev);
 458         struct mlx4_eqe *eqe;
 459         int cqn = -1;
 460         int eqes_found = 0;
 461         int set_ci = 0;
 462         int port;
 463         int slave = 0;
 464         int ret;
 465         u32 flr_slave;
 466         u8 update_slave_state;
 467         int i;
 468         enum slave_port_gen_event gen_event;
 469         unsigned long flags;
 470         struct mlx4_vport_state *s_info;
 471         int eqe_size = dev->caps.eqe_size;
 472
 473         while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
 474                 /*
 475                  * Make sure we read EQ entry contents after we've
 476                  * checked the ownership bit.
 477                  */
 478                 rmb();
 479
 480                 switch (eqe->type) {
 481                 case MLX4_EVENT_TYPE_COMP:
 482                         cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
 483                         mlx4_cq_completion(dev, cqn);
 484                         break;
 485
 486                 case MLX4_EVENT_TYPE_PATH_MIG:
 487                 case MLX4_EVENT_TYPE_COMM_EST:
 488                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 489                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 490                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 491                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 492                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 493                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 494                         mlx4_dbg(dev, "event %d arrived\n", eqe->type);
 495                         if (mlx4_is_master(dev)) {
 496                                 /* forward only to slave owning the QP */
 497                                 ret = mlx4_get_slave_from_resource_id(dev,
 498                                                 RES_QP,
 499                                                 be32_to_cpu(eqe->event.qp.qpn)
 500                                                 & 0xffffff, &slave);
 501                                 if (ret && ret != -ENOENT) {
 502                                         mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
 503                                                  eqe->type, eqe->subtype,
 504                                                  eq->eqn, eq->cons_index, ret);
 505                                         break;
 506                                 }
 507
 508                                 if (!ret && slave != dev->caps.function) {
 509                                         mlx4_slave_event(dev, slave, eqe);
 510                                         break;
 511                                 }
 512
 513                         }
 514                         mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
 515                                       0xffffff, eqe->type);
 516                         break;
 517
 518                 case MLX4_EVENT_TYPE_SRQ_LIMIT:
 519                         mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
 520                                  __func__);
 521                 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
 522                         if (mlx4_is_master(dev)) {
 523                                 /* forward only to slave owning the SRQ */
 524                                 ret = mlx4_get_slave_from_resource_id(dev,
 525                                                 RES_SRQ,
 526                                                 be32_to_cpu(eqe->event.srq.srqn)
 527                                                 & 0xffffff,
 528                                                 &slave);
 529                                 if (ret && ret != -ENOENT) {
 530                                         mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
 531                                                   eqe->type, eqe->subtype,
 532                                                   eq->eqn, eq->cons_index, ret);
 533                                         break;
 534                                 }
 535                                 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
 536                                           __func__, slave,
 537                                           be32_to_cpu(eqe->event.srq.srqn),
 538                                           eqe->type, eqe->subtype);
 539
 540                                 if (!ret && slave != dev->caps.function) {
 541                                         mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
 542                                                   __func__, eqe->type,
 543                                                   eqe->subtype, slave);
 544                                         mlx4_slave_event(dev, slave, eqe);
 545                                         break;
 546                                 }
 547                         }
 548                         mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
 549                                        0xffffff, eqe->type);
 550                         break;
 551
 552                 case MLX4_EVENT_TYPE_CMD:
 553                         mlx4_cmd_event(dev,
 554                                        be16_to_cpu(eqe->event.cmd.token),
 555                                        eqe->event.cmd.status,
 556                                        be64_to_cpu(eqe->event.cmd.out_param));
 557                         break;
 558
 559                 case MLX4_EVENT_TYPE_PORT_CHANGE: {
 560                         struct mlx4_slaves_pport slaves_port;
 561                         port = be32_to_cpu(eqe->event.port_change.port) >> 28;
 562                         slaves_port = mlx4_phys_to_slaves_pport(dev, port);
 563                         if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
 564                                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
 565                                                     port);
 566                                 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
 567                                 if (!mlx4_is_master(dev))
 568                                         break;
 569                                 for (i = 0; i < dev->persist->num_vfs + 1;
 570                                      i++) {
 571                                         if (!test_bit(i, slaves_port.slaves))
 572                                                 continue;
 573                                         if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
 574                                                 if (i == mlx4_master_func_num(dev))
 575                                                         continue;
 576                                                 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
 577                                                          __func__, i, port);
 578                                                 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
 579                                                 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
 580                                                         eqe->event.port_change.port =
 581                                                                 cpu_to_be32(
 582                                                                 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
 583                                                                 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
 584                                                         mlx4_slave_event(dev, i, eqe);
 585                                                 }
 586                                         } else {  /* IB port */
 587                                                 set_and_calc_slave_port_state(dev, i, port,
 588                                                                               MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
 589                                                                               &gen_event);
 590                                                 /*we can be in pending state, then do not send port_down event*/
 591                                                 if (SLAVE_PORT_GEN_EVENT_DOWN ==  gen_event) {
 592                                                         if (i == mlx4_master_func_num(dev))
 593                                                                 continue;
 594                                                         mlx4_slave_event(dev, i, eqe);
 595                                                 }
 596                                         }
 597                                 }
 598                         } else {
 599                                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
 600
 601                                 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
 602
 603                                 if (!mlx4_is_master(dev))
 604                                         break;
 605                                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 606                                         for (i = 0;
 607                                              i < dev->persist->num_vfs + 1;
 608                                              i++) {
 609                                                 if (!test_bit(i, slaves_port.slaves))
 610                                                         continue;
 611                                                 if (i == mlx4_master_func_num(dev))
 612                                                         continue;
 613                                                 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
 614                                                 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
 615                                                         eqe->event.port_change.port =
 616                                                                 cpu_to_be32(
 617                                                                 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
 618                                                                 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
 619                                                         mlx4_slave_event(dev, i, eqe);
 620                                                 }
 621                                         }
 622                                 else /* IB port */
 623                                         /* port-up event will be sent to a slave when the
 624                                          * slave's alias-guid is set. This is done in alias_GUID.c
 625                                          */
 626                                         set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
 627                         }
 628                         break;
 629                 }
 630
 631                 case MLX4_EVENT_TYPE_CQ_ERROR:
 632                         mlx4_warn(dev, "CQ %s on CQN %06x\n",
 633                                   eqe->event.cq_err.syndrome == 1 ?
 634                                   "overrun" : "access violation",
 635                                   be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
 636                         if (mlx4_is_master(dev)) {
 637                                 ret = mlx4_get_slave_from_resource_id(dev,
 638                                         RES_CQ,
 639                                         be32_to_cpu(eqe->event.cq_err.cqn)
 640                                         & 0xffffff, &slave);
 641                                 if (ret && ret != -ENOENT) {
 642                                         mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
 643                                                  eqe->type, eqe->subtype,
 644                                                  eq->eqn, eq->cons_index, ret);
 645                                         break;
 646                                 }
 647
 648                                 if (!ret && slave != dev->caps.function) {
 649                                         mlx4_slave_event(dev, slave, eqe);
 650                                         break;
 651                                 }
 652                         }
 653                         mlx4_cq_event(dev,
 654                                       be32_to_cpu(eqe->event.cq_err.cqn)
 655                                       & 0xffffff,
 656                                       eqe->type);
 657                         break;
 658
 659                 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
 660                         mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
 661                         break;
 662
 663                 case MLX4_EVENT_TYPE_OP_REQUIRED:
 664                         atomic_inc(&priv->opreq_count);
 665                         /* FW commands can't be executed from interrupt context
 666                          * working in deferred task
 667                          */
 668                         queue_work(mlx4_wq, &priv->opreq_task);
 669                         break;
 670
 671                 case MLX4_EVENT_TYPE_COMM_CHANNEL:
 672                         if (!mlx4_is_master(dev)) {
 673                                 mlx4_warn(dev, "Received comm channel event for non master device\n");
 674                                 break;
 675                         }
 676                         memcpy(&priv->mfunc.master.comm_arm_bit_vector,
 677                                eqe->event.comm_channel_arm.bit_vec,
 678                                sizeof eqe->event.comm_channel_arm.bit_vec);
 679                         queue_work(priv->mfunc.master.comm_wq,
 680                                    &priv->mfunc.master.comm_work);
 681                         break;
 682
 683                 case MLX4_EVENT_TYPE_FLR_EVENT:
 684                         flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
 685                         if (!mlx4_is_master(dev)) {
 686                                 mlx4_warn(dev, "Non-master function received FLR event\n");
 687                                 break;
 688                         }
 689
 690                         mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
 691
 692                         if (flr_slave >= dev->num_slaves) {
 693                                 mlx4_warn(dev,
 694                                           "Got FLR for unknown function: %d\n",
 695                                           flr_slave);
 696                                 update_slave_state = 0;
 697                         } else
 698                                 update_slave_state = 1;
 699
 700                         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
 701                         if (update_slave_state) {
 702                                 priv->mfunc.master.slave_state[flr_slave].active = false;
 703                                 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
 704                                 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
 705                         }
 706                         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
 707                         queue_work(priv->mfunc.master.comm_wq,
 708                                    &priv->mfunc.master.slave_flr_event_work);
 709                         break;
 710
 711                 case MLX4_EVENT_TYPE_FATAL_WARNING:
 712                         if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
 713                                 if (mlx4_is_master(dev))
 714                                         for (i = 0; i < dev->num_slaves; i++) {
 715                                                 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
 716                                                          __func__, i);
 717                                                 if (i == dev->caps.function)
 718                                                         continue;
 719                                                 mlx4_slave_event(dev, i, eqe);
 720                                         }
 721                                 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
 722                                          be16_to_cpu(eqe->event.warming.warning_threshold),
 723                                          be16_to_cpu(eqe->event.warming.current_temperature));
 724                         } else
 725                                 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
 726                                           eqe->type, eqe->subtype, eq->eqn,
 727                                           eq->cons_index, eqe->owner, eq->nent,
 728                                           eqe->slave_id,
 729                                           !!(eqe->owner & 0x80) ^
 730                                           !!(eq->cons_index & eq->nent) ? "HW" : "SW");
 731
 732                         break;
 733
 734                 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
 735                         mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
 736                                             (unsigned long) eqe);
 737                         break;
 738
 739                 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
 740                 case MLX4_EVENT_TYPE_ECC_DETECT:
 741                 default:
 742                         mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
 743                                   eqe->type, eqe->subtype, eq->eqn,
 744                                   eq->cons_index, eqe->owner, eq->nent,
 745                                   eqe->slave_id,
 746                                   !!(eqe->owner & 0x80) ^
 747                                   !!(eq->cons_index & eq->nent) ? "HW" : "SW");
 748                         break;
 749                 };
 750
 751                 ++eq->cons_index;
 752                 eqes_found = 1;
 753                 ++set_ci;
 754
 755                 /*
 756                  * The HCA will think the queue has overflowed if we
 757                  * don't tell it we've been processing events.  We
 758                  * create our EQs with MLX4_NUM_SPARE_EQE extra
 759                  * entries, so we must update our consumer index at
 760                  * least that often.
 761                  */
 762                 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
 763                         eq_set_ci(eq, 0);
 764                         set_ci = 0;
 765                 }
 766         }
 767
 768         eq_set_ci(eq, 1);
 769
 770         /* cqn is 24bit wide but is initialized such that its higher bits
 771          * are ones too. Thus, if we got any event, cqn's high bits should be off
 772          * and we need to schedule the tasklet.
 773          */
 774         if (!(cqn & ~0xffffff))
 775                 tasklet_schedule(&eq->tasklet_ctx.task);
 776
 777         return eqes_found;
 778 }
 779
 780 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
 781 {
 782         struct mlx4_dev *dev = dev_ptr;
 783         struct mlx4_priv *priv = mlx4_priv(dev);
 784         int work = 0;
 785         int i;
 786
 787         writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
 788
 789         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
 790                 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
 791
 792         return IRQ_RETVAL(work);
 793 }
 794
 795 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
 796 {
 797         struct mlx4_eq  *eq  = eq_ptr;
 798         struct mlx4_dev *dev = eq->dev;
 799
 800         mlx4_eq_int(dev, eq);
 801
 802         /* MSI-X vectors always belong to us */
 803         return IRQ_HANDLED;
 804 }
 805
 806 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
 807                         struct mlx4_vhcr *vhcr,
 808                         struct mlx4_cmd_mailbox *inbox,
 809                         struct mlx4_cmd_mailbox *outbox,
 810                         struct mlx4_cmd_info *cmd)
 811 {
 812         struct mlx4_priv *priv = mlx4_priv(dev);
 813         struct mlx4_slave_event_eq_info *event_eq =
 814                 priv->mfunc.master.slave_state[slave].event_eq;
 815         u32 in_modifier = vhcr->in_modifier;
 816         u32 eqn = in_modifier & 0x3FF;
 817         u64 in_param =  vhcr->in_param;
 818         int err = 0;
 819         int i;
 820
 821         if (slave == dev->caps.function)
 822                 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
 823                                0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
 824                                MLX4_CMD_NATIVE);
 825         if (!err)
 826                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
 827                         if (in_param & (1LL << i))
 828                                 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
 829
 830         return err;
 831 }
 832
 833 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
 834                         int eq_num)
 835 {
 836         return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
 837                         0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
 838                         MLX4_CMD_WRAPPED);
 839 }
 840
 841 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 842                          int eq_num)
 843 {
 844         return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
 845                         MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
 846                         MLX4_CMD_WRAPPED);
 847 }
 848
 849 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 850                          int eq_num)
 851 {
 852         return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
 853                             0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
 854                             MLX4_CMD_WRAPPED);
 855 }
 856
 857 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
 858 {
 859         /*
 860          * Each UAR holds 4 EQ doorbells.  To figure out how many UARs
 861          * we need to map, take the difference of highest index and
 862          * the lowest index we'll use and add 1.
 863          */
 864         return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
 865                  dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
 866 }
 867
 868 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
 869 {
 870         struct mlx4_priv *priv = mlx4_priv(dev);
 871         int index;
 872
 873         index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
 874
 875         if (!priv->eq_table.uar_map[index]) {
 876                 priv->eq_table.uar_map[index] =
 877                         ioremap(pci_resource_start(dev->persist->pdev, 2) +
 878                                 ((eq->eqn / 4) << PAGE_SHIFT),
 879                                 PAGE_SIZE);
 880                 if (!priv->eq_table.uar_map[index]) {
 881                         mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
 882                                  eq->eqn);
 883                         return NULL;
 884                 }
 885         }
 886
 887         return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
 888 }
 889
 890 static void mlx4_unmap_uar(struct mlx4_dev *dev)
 891 {
 892         struct mlx4_priv *priv = mlx4_priv(dev);
 893         int i;
 894
 895         for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
 896                 if (priv->eq_table.uar_map[i]) {
 897                         iounmap(priv->eq_table.uar_map[i]);
 898                         priv->eq_table.uar_map[i] = NULL;
 899                 }
 900 }
 901
 902 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
 903                           u8 intr, struct mlx4_eq *eq)
 904 {
 905         struct mlx4_priv *priv = mlx4_priv(dev);
 906         struct mlx4_cmd_mailbox *mailbox;
 907         struct mlx4_eq_context *eq_context;
 908         int npages;
 909         u64 *dma_list = NULL;
 910         dma_addr_t t;
 911         u64 mtt_addr;
 912         int err = -ENOMEM;
 913         int i;
 914
 915         eq->dev   = dev;
 916         eq->nent  = roundup_pow_of_two(max(nent, 2));
 917         /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
 918          * strides of 64B,128B and 256B.
 919          */
 920         npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
 921
 922         eq->page_list = kmalloc(npages * sizeof *eq->page_list,
 923                                 GFP_KERNEL);
 924         if (!eq->page_list)
 925                 goto err_out;
 926
 927         for (i = 0; i < npages; ++i)
 928                 eq->page_list[i].buf = NULL;
 929
 930         dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 931         if (!dma_list)
 932                 goto err_out_free;
 933
 934         mailbox = mlx4_alloc_cmd_mailbox(dev);
 935         if (IS_ERR(mailbox))
 936                 goto err_out_free;
 937         eq_context = mailbox->buf;
 938
 939         for (i = 0; i < npages; ++i) {
 940                 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
 941                                                           pdev->dev,
 942                                                           PAGE_SIZE, &t,
 943                                                           GFP_KERNEL);
 944                 if (!eq->page_list[i].buf)
 945                         goto err_out_free_pages;
 946
 947                 dma_list[i] = t;
 948                 eq->page_list[i].map = t;
 949
 950                 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
 951         }
 952
 953         eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
 954         if (eq->eqn == -1)
 955                 goto err_out_free_pages;
 956
 957         eq->doorbell = mlx4_get_eq_uar(dev, eq);
 958         if (!eq->doorbell) {
 959                 err = -ENOMEM;
 960                 goto err_out_free_eq;
 961         }
 962
 963         err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
 964         if (err)
 965                 goto err_out_free_eq;
 966
 967         err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
 968         if (err)
 969                 goto err_out_free_mtt;
 970
 971         eq_context->flags         = cpu_to_be32(MLX4_EQ_STATUS_OK   |
 972                                                 MLX4_EQ_STATE_ARMED);
 973         eq_context->log_eq_size   = ilog2(eq->nent);
 974         eq_context->intr          = intr;
 975         eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
 976
 977         mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
 978         eq_context->mtt_base_addr_h = mtt_addr >> 32;
 979         eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 980
 981         err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
 982         if (err) {
 983                 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
 984                 goto err_out_free_mtt;
 985         }
 986
 987         kfree(dma_list);
 988         mlx4_free_cmd_mailbox(dev, mailbox);
 989
 990         eq->cons_index = 0;
 991
 992         INIT_LIST_HEAD(&eq->tasklet_ctx.list);
 993         INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
 994         spin_lock_init(&eq->tasklet_ctx.lock);
 995         tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb,
 996                      (unsigned long)&eq->tasklet_ctx);
 997
 998         return err;
 999
1000 err_out_free_mtt:
1001         mlx4_mtt_cleanup(dev, &eq->mtt);
1002
1003 err_out_free_eq:
1004         mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1005
1006 err_out_free_pages:
1007         for (i = 0; i < npages; ++i)
1008                 if (eq->page_list[i].buf)
1009                         dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1010                                           eq->page_list[i].buf,
1011                                           eq->page_list[i].map);
1012
1013         mlx4_free_cmd_mailbox(dev, mailbox);
1014
1015 err_out_free:
1016         kfree(eq->page_list);
1017         kfree(dma_list);
1018
1019 err_out:
1020         return err;
1021 }
1022
1023 static void mlx4_free_eq(struct mlx4_dev *dev,
1024                          struct mlx4_eq *eq)
1025 {
1026         struct mlx4_priv *priv = mlx4_priv(dev);
1027         struct mlx4_cmd_mailbox *mailbox;
1028         int err;
1029         int i;
1030         /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1031          * strides of 64B,128B and 256B
1032          */
1033         int npages = PAGE_ALIGN(dev->caps.eqe_size  * eq->nent) / PAGE_SIZE;
1034
1035         mailbox = mlx4_alloc_cmd_mailbox(dev);
1036         if (IS_ERR(mailbox))
1037                 return;
1038
1039         err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
1040         if (err)
1041                 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1042
1043         if (0) {
1044                 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
1045                 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
1046                         if (i % 4 == 0)
1047                                 pr_cont("[%02x] ", i * 4);
1048                         pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
1049                         if ((i + 1) % 4 == 0)
1050                                 pr_cont("\n");
1051                 }
1052         }
1053         synchronize_irq(eq->irq);
1054         tasklet_disable(&eq->tasklet_ctx.task);
1055
1056         mlx4_mtt_cleanup(dev, &eq->mtt);
1057         for (i = 0; i < npages; ++i)
1058                 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1059                                   eq->page_list[i].buf,
1060                                   eq->page_list[i].map);
1061
1062         kfree(eq->page_list);
1063         mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1064         mlx4_free_cmd_mailbox(dev, mailbox);
1065 }
1066
1067 static void mlx4_free_irqs(struct mlx4_dev *dev)
1068 {
1069         struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1070         struct mlx4_priv *priv = mlx4_priv(dev);
1071         int     i, vec;
1072
1073         if (eq_table->have_irq)
1074                 free_irq(dev->persist->pdev->irq, dev);
1075
1076         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1077                 if (eq_table->eq[i].have_irq) {
1078                         free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1079                         eq_table->eq[i].have_irq = 0;
1080                 }
1081
1082         for (i = 0; i < dev->caps.comp_pool; i++) {
1083                 /*
1084                  * Freeing the assigned irq's
1085                  * all bits should be 0, but we need to validate
1086                  */
1087                 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1088                         /* NO need protecting*/
1089                         vec = dev->caps.num_comp_vectors + 1 + i;
1090                         free_irq(priv->eq_table.eq[vec].irq,
1091                                  &priv->eq_table.eq[vec]);
1092                 }
1093         }
1094
1095
1096         kfree(eq_table->irq_names);
1097 }
1098
1099 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1100 {
1101         struct mlx4_priv *priv = mlx4_priv(dev);
1102
1103         priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev,
1104                                  priv->fw.clr_int_bar) +
1105                                  priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1106         if (!priv->clr_base) {
1107                 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
1108                 return -ENOMEM;
1109         }
1110
1111         return 0;
1112 }
1113
1114 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1115 {
1116         struct mlx4_priv *priv = mlx4_priv(dev);
1117
1118         iounmap(priv->clr_base);
1119 }
1120
1121 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1122 {
1123         struct mlx4_priv *priv = mlx4_priv(dev);
1124
1125         priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1126                                     sizeof *priv->eq_table.eq, GFP_KERNEL);
1127         if (!priv->eq_table.eq)
1128                 return -ENOMEM;
1129
1130         return 0;
1131 }
1132
1133 void mlx4_free_eq_table(struct mlx4_dev *dev)
1134 {
1135         kfree(mlx4_priv(dev)->eq_table.eq);
1136 }
1137
1138 int mlx4_init_eq_table(struct mlx4_dev *dev)
1139 {
1140         struct mlx4_priv *priv = mlx4_priv(dev);
1141         int err;
1142         int i;
1143
1144         priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1145                                          sizeof *priv->eq_table.uar_map,
1146                                          GFP_KERNEL);
1147         if (!priv->eq_table.uar_map) {
1148                 err = -ENOMEM;
1149                 goto err_out_free;
1150         }
1151
1152         err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1153                                roundup_pow_of_two(dev->caps.num_eqs),
1154                                dev->caps.num_eqs - 1,
1155                                dev->caps.reserved_eqs,
1156                                roundup_pow_of_two(dev->caps.num_eqs) -
1157                                dev->caps.num_eqs);
1158         if (err)
1159                 goto err_out_free;
1160
1161         for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1162                 priv->eq_table.uar_map[i] = NULL;
1163
1164         if (!mlx4_is_slave(dev)) {
1165                 err = mlx4_map_clr_int(dev);
1166                 if (err)
1167                         goto err_out_bitmap;
1168
1169                 priv->eq_table.clr_mask =
1170                         swab32(1 << (priv->eq_table.inta_pin & 31));
1171                 priv->eq_table.clr_int  = priv->clr_base +
1172                         (priv->eq_table.inta_pin < 32 ? 4 : 0);
1173         }
1174
1175         priv->eq_table.irq_names =
1176                 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1177                                              dev->caps.comp_pool),
1178                         GFP_KERNEL);
1179         if (!priv->eq_table.irq_names) {
1180                 err = -ENOMEM;
1181                 goto err_out_bitmap;
1182         }
1183
1184         for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1185                 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1186                                           dev->caps.reserved_cqs +
1187                                           MLX4_NUM_SPARE_EQE,
1188                                      (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1189                                      &priv->eq_table.eq[i]);
1190                 if (err) {
1191                         --i;
1192                         goto err_out_unmap;
1193                 }
1194         }
1195
1196         err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1197                              (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1198                              &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1199         if (err)
1200                 goto err_out_comp;
1201
1202         /*if additional completion vectors poolsize is 0 this loop will not run*/
1203         for (i = dev->caps.num_comp_vectors + 1;
1204               i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1205
1206                 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1207                                           dev->caps.reserved_cqs +
1208                                           MLX4_NUM_SPARE_EQE,
1209                                      (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1210                                      &priv->eq_table.eq[i]);
1211                 if (err) {
1212                         --i;
1213                         goto err_out_unmap;
1214                 }
1215         }
1216
1217
1218         if (dev->flags & MLX4_FLAG_MSI_X) {
1219                 const char *eq_name;
1220
1221                 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1222                         if (i < dev->caps.num_comp_vectors) {
1223                                 snprintf(priv->eq_table.irq_names +
1224                                          i * MLX4_IRQNAME_SIZE,
1225                                          MLX4_IRQNAME_SIZE,
1226                                          "mlx4-comp-%d@pci:%s", i,
1227                                          pci_name(dev->persist->pdev));
1228                         } else {
1229                                 snprintf(priv->eq_table.irq_names +
1230                                          i * MLX4_IRQNAME_SIZE,
1231                                          MLX4_IRQNAME_SIZE,
1232                                          "mlx4-async@pci:%s",
1233                                          pci_name(dev->persist->pdev));
1234                         }
1235
1236                         eq_name = priv->eq_table.irq_names +
1237                                   i * MLX4_IRQNAME_SIZE;
1238                         err = request_irq(priv->eq_table.eq[i].irq,
1239                                           mlx4_msi_x_interrupt, 0, eq_name,
1240                                           priv->eq_table.eq + i);
1241                         if (err)
1242                                 goto err_out_async;
1243
1244                         priv->eq_table.eq[i].have_irq = 1;
1245                 }
1246         } else {
1247                 snprintf(priv->eq_table.irq_names,
1248                          MLX4_IRQNAME_SIZE,
1249                          DRV_NAME "@pci:%s",
1250                          pci_name(dev->persist->pdev));
1251                 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt,
1252                                   IRQF_SHARED, priv->eq_table.irq_names, dev);
1253                 if (err)
1254                         goto err_out_async;
1255
1256                 priv->eq_table.have_irq = 1;
1257         }
1258
1259         err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1260                           priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1261         if (err)
1262                 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1263                            priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1264
1265         for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1266                 eq_set_ci(&priv->eq_table.eq[i], 1);
1267
1268         return 0;
1269
1270 err_out_async:
1271         mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1272
1273 err_out_comp:
1274         i = dev->caps.num_comp_vectors - 1;
1275
1276 err_out_unmap:
1277         while (i >= 0) {
1278                 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1279                 --i;
1280         }
1281         if (!mlx4_is_slave(dev))
1282                 mlx4_unmap_clr_int(dev);
1283         mlx4_free_irqs(dev);
1284
1285 err_out_bitmap:
1286         mlx4_unmap_uar(dev);
1287         mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1288
1289 err_out_free:
1290         kfree(priv->eq_table.uar_map);
1291
1292         return err;
1293 }
1294
1295 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1296 {
1297         struct mlx4_priv *priv = mlx4_priv(dev);
1298         int i;
1299
1300         mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1301                     priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1302
1303         mlx4_free_irqs(dev);
1304
1305         for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1306                 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1307
1308         if (!mlx4_is_slave(dev))
1309                 mlx4_unmap_clr_int(dev);
1310
1311         mlx4_unmap_uar(dev);
1312         mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1313
1314         kfree(priv->eq_table.uar_map);
1315 }
1316
1317 /* A test that verifies that we can accept interrupts on all
1318  * the irq vectors of the device.
1319  * Interrupts are checked using the NOP command.
1320  */
1321 int mlx4_test_interrupts(struct mlx4_dev *dev)
1322 {
1323         struct mlx4_priv *priv = mlx4_priv(dev);
1324         int i;
1325         int err;
1326
1327         err = mlx4_NOP(dev);
1328         /* When not in MSI_X, there is only one irq to check */
1329         if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1330                 return err;
1331
1332         /* A loop over all completion vectors, for each vector we will check
1333          * whether it works by mapping command completions to that vector
1334          * and performing a NOP command
1335          */
1336         for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1337                 /* Temporary use polling for command completions */
1338                 mlx4_cmd_use_polling(dev);
1339
1340                 /* Map the new eq to handle all asynchronous events */
1341                 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1342                                   priv->eq_table.eq[i].eqn);
1343                 if (err) {
1344                         mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1345                         mlx4_cmd_use_events(dev);
1346                         break;
1347                 }
1348
1349                 /* Go back to using events */
1350                 mlx4_cmd_use_events(dev);
1351                 err = mlx4_NOP(dev);
1352         }
1353
1354         /* Return to default */
1355         mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1356                     priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1357         return err;
1358 }
1359 EXPORT_SYMBOL(mlx4_test_interrupts);
1360
1361 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1362                    int *vector)
1363 {
1364
1365         struct mlx4_priv *priv = mlx4_priv(dev);
1366         int vec = 0, err = 0, i;
1367
1368         mutex_lock(&priv->msix_ctl.pool_lock);
1369         for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1370                 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1371                         priv->msix_ctl.pool_bm |= 1ULL << i;
1372                         vec = dev->caps.num_comp_vectors + 1 + i;
1373                         snprintf(priv->eq_table.irq_names +
1374                                         vec * MLX4_IRQNAME_SIZE,
1375                                         MLX4_IRQNAME_SIZE, "%s", name);
1376 #ifdef CONFIG_RFS_ACCEL
1377                         if (rmap) {
1378                                 err = irq_cpu_rmap_add(rmap,
1379                                                        priv->eq_table.eq[vec].irq);
1380                                 if (err)
1381                                         mlx4_warn(dev, "Failed adding irq rmap\n");
1382                         }
1383 #endif
1384                         err = request_irq(priv->eq_table.eq[vec].irq,
1385                                           mlx4_msi_x_interrupt, 0,
1386                                           &priv->eq_table.irq_names[vec<<5],
1387                                           priv->eq_table.eq + vec);
1388                         if (err) {
1389                                 /*zero out bit by fliping it*/
1390                                 priv->msix_ctl.pool_bm ^= 1 << i;
1391                                 vec = 0;
1392                                 continue;
1393                                 /*we dont want to break here*/
1394                         }
1395
1396                         eq_set_ci(&priv->eq_table.eq[vec], 1);
1397                 }
1398         }
1399         mutex_unlock(&priv->msix_ctl.pool_lock);
1400
1401         if (vec) {
1402                 *vector = vec;
1403         } else {
1404                 *vector = 0;
1405                 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1406         }
1407         return err;
1408 }
1409 EXPORT_SYMBOL(mlx4_assign_eq);
1410
1411 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec)
1412 {
1413         struct mlx4_priv *priv = mlx4_priv(dev);
1414
1415         return priv->eq_table.eq[vec].irq;
1416 }
1417 EXPORT_SYMBOL(mlx4_eq_get_irq);
1418
1419 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1420 {
1421         struct mlx4_priv *priv = mlx4_priv(dev);
1422         /*bm index*/
1423         int i = vec - dev->caps.num_comp_vectors - 1;
1424
1425         if (likely(i >= 0)) {
1426                 /*sanity check , making sure were not trying to free irq's
1427                   Belonging to a legacy EQ*/
1428                 mutex_lock(&priv->msix_ctl.pool_lock);
1429                 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1430                         free_irq(priv->eq_table.eq[vec].irq,
1431                                  &priv->eq_table.eq[vec]);
1432                         priv->msix_ctl.pool_bm &= ~(1ULL << i);
1433                 }
1434                 mutex_unlock(&priv->msix_ctl.pool_lock);
1435         }
1436
1437 }
1438 EXPORT_SYMBOL(mlx4_release_eq);
1439