drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/netdevice.h>
  45
  46 #include <linux/mlx4/device.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "icm.h"
  52
  53 MODULE_AUTHOR("Roland Dreier");
  54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  55 MODULE_LICENSE("Dual BSD/GPL");
  56 MODULE_VERSION(DRV_VERSION);
  57
  58 struct workqueue_struct *mlx4_wq;
  59
  60 #ifdef CONFIG_MLX4_DEBUG
  61
  62 int mlx4_debug_level = 0;
  63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  65
  66 #endif /* CONFIG_MLX4_DEBUG */
  67
  68 #ifdef CONFIG_PCI_MSI
  69
  70 static int msi_x = 1;
  71 module_param(msi_x, int, 0444);
  72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  73
  74 #else /* CONFIG_PCI_MSI */
  75
  76 #define msi_x (0)
  77
  78 #endif /* CONFIG_PCI_MSI */
  79
  80 static int num_vfs;
  81 module_param(num_vfs, int, 0444);
  82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
  83
  84 static int probe_vf;
  85 module_param(probe_vf, int, 0644);
  86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
  87
  88 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  89 module_param_named(log_num_mgm_entry_size,
  90                         mlx4_log_num_mgm_entry_size, int, 0444);
  91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  92                                          " of qp per mcg, for example:"
  93                                          " 10 gives 248.range: 7 <="
  94                                          " log_num_mgm_entry_size <= 12."
  95                                          " To activate device managed"
  96                                          " flow steering when available, set to -1");
  97
  98 static bool enable_64b_cqe_eqe;
  99 module_param(enable_64b_cqe_eqe, bool, 0444);
 100 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 101                  "Enable 64 byte CQEs/EQEs when the the FW supports this");
 102
 103 #define HCA_GLOBAL_CAP_MASK            0
 104
 105 #define PF_CONTEXT_BEHAVIOUR_MASK       MLX4_FUNC_CAP_64B_EQE_CQE
 106
 107 static char mlx4_version[] =
 108         DRV_NAME ": Mellanox ConnectX core driver v"
 109         DRV_VERSION " (" DRV_RELDATE ")\n";
 110
 111 static struct mlx4_profile default_profile = {
 112         .num_qp         = 1 << 18,
 113         .num_srq        = 1 << 16,
 114         .rdmarc_per_qp  = 1 << 4,
 115         .num_cq         = 1 << 16,
 116         .num_mcg        = 1 << 13,
 117         .num_mpt        = 1 << 19,
 118         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 119 };
 120
 121 static int log_num_mac = 7;
 122 module_param_named(log_num_mac, log_num_mac, int, 0444);
 123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 124
 125 static int log_num_vlan;
 126 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 128 /* Log2 max number of VLANs per ETH port (0-7) */
 129 #define MLX4_LOG_NUM_VLANS 7
 130
 131 static bool use_prio;
 132 module_param_named(use_prio, use_prio, bool, 0444);
 133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 134                   "(0/1, default 0)");
 135
 136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 139
 140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 141 static int arr_argc = 2;
 142 module_param_array(port_type_array, int, &arr_argc, 0444);
 143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 144                                 "1 for IB, 2 for Ethernet");
 145
 146 struct mlx4_port_config {
 147         struct list_head list;
 148         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 149         struct pci_dev *pdev;
 150 };
 151
 152 int mlx4_check_port_params(struct mlx4_dev *dev,
 153                            enum mlx4_port_type *port_type)
 154 {
 155         int i;
 156
 157         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 158                 if (port_type[i] != port_type[i + 1]) {
 159                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 160                                 mlx4_err(dev, "Only same port types supported "
 161                                          "on this HCA, aborting.\n");
 162                                 return -EINVAL;
 163                         }
 164                 }
 165         }
 166
 167         for (i = 0; i < dev->caps.num_ports; i++) {
 168                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 169                         mlx4_err(dev, "Requested port type for port %d is not "
 170                                       "supported on this HCA\n", i + 1);
 171                         return -EINVAL;
 172                 }
 173         }
 174         return 0;
 175 }
 176
 177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 178 {
 179         int i;
 180
 181         for (i = 1; i <= dev->caps.num_ports; ++i)
 182                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 183 }
 184
 185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 186 {
 187         int err;
 188         int i;
 189
 190         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 191         if (err) {
 192                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 193                 return err;
 194         }
 195
 196         if (dev_cap->min_page_sz > PAGE_SIZE) {
 197                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 198                          "kernel PAGE_SIZE of %ld, aborting.\n",
 199                          dev_cap->min_page_sz, PAGE_SIZE);
 200                 return -ENODEV;
 201         }
 202         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 203                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 204                          "aborting.\n",
 205                          dev_cap->num_ports, MLX4_MAX_PORTS);
 206                 return -ENODEV;
 207         }
 208
 209         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 210                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 211                          "PCI resource 2 size of 0x%llx, aborting.\n",
 212                          dev_cap->uar_size,
 213                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 214                 return -ENODEV;
 215         }
 216
 217         dev->caps.num_ports          = dev_cap->num_ports;
 218         dev->phys_caps.num_phys_eqs  = MLX4_MAX_EQ_NUM;
 219         for (i = 1; i <= dev->caps.num_ports; ++i) {
 220                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 221                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 222                 dev->phys_caps.gid_phys_table_len[i]  = dev_cap->max_gids[i];
 223                 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
 224                 /* set gid and pkey table operating lengths by default
 225                  * to non-sriov values */
 226                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 227                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 228                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 229                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 230                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 231                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 232                 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
 233                 dev->caps.default_sense[i] = dev_cap->default_sense[i];
 234                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 235                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 236                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 237                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 238         }
 239
 240         dev->caps.uar_page_size      = PAGE_SIZE;
 241         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 242         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 243         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 244         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 245         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 246         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 247         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 248         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 249         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 250         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 251         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 252         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 253         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 254         /*
 255          * Subtract 1 from the limit because we need to allocate a
 256          * spare CQE so the HCA HW can tell the difference between an
 257          * empty CQ and a full CQ.
 258          */
 259         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 260         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 261         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 262         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 263         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 264
 265         /* The first 128 UARs are used for EQ doorbells */
 266         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 267         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 268         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 269                                         dev_cap->reserved_xrcds : 0;
 270         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 271                                         dev_cap->max_xrcds : 0;
 272         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 273
 274         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 275         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 276         dev->caps.flags              = dev_cap->flags;
 277         dev->caps.flags2             = dev_cap->flags2;
 278         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 279         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 280         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 281         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 282         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 283
 284         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 285         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 286                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 287         /* Don't do sense port on multifunction devices (for now at least) */
 288         if (mlx4_is_mfunc(dev))
 289                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 290
 291         dev->caps.log_num_macs  = log_num_mac;
 292         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 293         dev->caps.log_num_prios = use_prio ? 3 : 0;
 294
 295         for (i = 1; i <= dev->caps.num_ports; ++i) {
 296                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 297                 if (dev->caps.supported_type[i]) {
 298                         /* if only ETH is supported - assign ETH */
 299                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 300                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 301                         /* if only IB is supported, assign IB */
 302                         else if (dev->caps.supported_type[i] ==
 303                                  MLX4_PORT_TYPE_IB)
 304                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 305                         else {
 306                                 /* if IB and ETH are supported, we set the port
 307                                  * type according to user selection of port type;
 308                                  * if user selected none, take the FW hint */
 309                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 310                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 311                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 312                                 else
 313                                         dev->caps.port_type[i] = port_type_array[i - 1];
 314                         }
 315                 }
 316                 /*
 317                  * Link sensing is allowed on the port if 3 conditions are true:
 318                  * 1. Both protocols are supported on the port.
 319                  * 2. Different types are supported on the port
 320                  * 3. FW declared that it supports link sensing
 321                  */
 322                 mlx4_priv(dev)->sense.sense_allowed[i] =
 323                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 324                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 325                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 326
 327                 /*
 328                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 329                  * and perform sense_port FW command to try and set the correct
 330                  * port type from beginning
 331                  */
 332                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 333                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 334                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 335                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 336                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 337                                 dev->caps.port_type[i] = sensed_port;
 338                 } else {
 339                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 340                 }
 341
 342                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 343                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 344                         mlx4_warn(dev, "Requested number of MACs is too much "
 345                                   "for port %d, reducing to %d.\n",
 346                                   i, 1 << dev->caps.log_num_macs);
 347                 }
 348                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 349                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 350                         mlx4_warn(dev, "Requested number of VLANs is too much "
 351                                   "for port %d, reducing to %d.\n",
 352                                   i, 1 << dev->caps.log_num_vlans);
 353                 }
 354         }
 355
 356         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 357
 358         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 359         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 360                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 361                 (1 << dev->caps.log_num_macs) *
 362                 (1 << dev->caps.log_num_vlans) *
 363                 (1 << dev->caps.log_num_prios) *
 364                 dev->caps.num_ports;
 365         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 366
 367         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 368                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 369                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 370                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 371
 372         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 373
 374         if (!enable_64b_cqe_eqe) {
 375                 if (dev_cap->flags &
 376                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 377                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 378                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 379                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 380                 }
 381         }
 382
 383         if ((dev->caps.flags &
 384             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 385             mlx4_is_master(dev))
 386                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 387
 388         return 0;
 389 }
 390 /*The function checks if there are live vf, return the num of them*/
 391 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 392 {
 393         struct mlx4_priv *priv = mlx4_priv(dev);
 394         struct mlx4_slave_state *s_state;
 395         int i;
 396         int ret = 0;
 397
 398         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 399                 s_state = &priv->mfunc.master.slave_state[i];
 400                 if (s_state->active && s_state->last_cmd !=
 401                     MLX4_COMM_CMD_RESET) {
 402                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 403                                   __func__, i);
 404                         ret++;
 405                 }
 406         }
 407         return ret;
 408 }
 409
 410 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 411 {
 412         u32 qk = MLX4_RESERVED_QKEY_BASE;
 413
 414         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 415             qpn < dev->phys_caps.base_proxy_sqpn)
 416                 return -EINVAL;
 417
 418         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 419                 /* tunnel qp */
 420                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 421         else
 422                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 423         *qkey = qk;
 424         return 0;
 425 }
 426 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 427
 428 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 429 {
 430         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 431
 432         if (!mlx4_is_master(dev))
 433                 return;
 434
 435         priv->virt2phys_pkey[slave][port - 1][i] = val;
 436 }
 437 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 438
 439 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 440 {
 441         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 442
 443         if (!mlx4_is_master(dev))
 444                 return;
 445
 446         priv->slave_node_guids[slave] = guid;
 447 }
 448 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 449
 450 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 451 {
 452         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 453
 454         if (!mlx4_is_master(dev))
 455                 return 0;
 456
 457         return priv->slave_node_guids[slave];
 458 }
 459 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 460
 461 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 462 {
 463         struct mlx4_priv *priv = mlx4_priv(dev);
 464         struct mlx4_slave_state *s_slave;
 465
 466         if (!mlx4_is_master(dev))
 467                 return 0;
 468
 469         s_slave = &priv->mfunc.master.slave_state[slave];
 470         return !!s_slave->active;
 471 }
 472 EXPORT_SYMBOL(mlx4_is_slave_active);
 473
 474 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 475                                        struct mlx4_dev_cap *dev_cap,
 476                                        struct mlx4_init_hca_param *hca_param)
 477 {
 478         dev->caps.steering_mode = hca_param->steering_mode;
 479         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 480                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 481                 dev->caps.fs_log_max_ucast_qp_range_size =
 482                         dev_cap->fs_log_max_ucast_qp_range_size;
 483         } else
 484                 dev->caps.num_qp_per_mgm =
 485                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 486
 487         mlx4_dbg(dev, "Steering mode is: %s\n",
 488                  mlx4_steering_mode_str(dev->caps.steering_mode));
 489 }
 490
 491 static int mlx4_slave_cap(struct mlx4_dev *dev)
 492 {
 493         int                        err;
 494         u32                        page_size;
 495         struct mlx4_dev_cap        dev_cap;
 496         struct mlx4_func_cap       func_cap;
 497         struct mlx4_init_hca_param hca_param;
 498         int                        i;
 499
 500         memset(&hca_param, 0, sizeof(hca_param));
 501         err = mlx4_QUERY_HCA(dev, &hca_param);
 502         if (err) {
 503                 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
 504                 return err;
 505         }
 506
 507         /*fail if the hca has an unknown capability */
 508         if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
 509             HCA_GLOBAL_CAP_MASK) {
 510                 mlx4_err(dev, "Unknown hca global capabilities\n");
 511                 return -ENOSYS;
 512         }
 513
 514         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 515
 516         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 517
 518         memset(&dev_cap, 0, sizeof(dev_cap));
 519         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 520         err = mlx4_dev_cap(dev, &dev_cap);
 521         if (err) {
 522                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 523                 return err;
 524         }
 525
 526         err = mlx4_QUERY_FW(dev);
 527         if (err)
 528                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
 529
 530         page_size = ~dev->caps.page_size_cap + 1;
 531         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 532         if (page_size > PAGE_SIZE) {
 533                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 534                          "kernel PAGE_SIZE of %ld, aborting.\n",
 535                          page_size, PAGE_SIZE);
 536                 return -ENODEV;
 537         }
 538
 539         /* slave gets uar page size from QUERY_HCA fw command */
 540         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 541
 542         /* TODO: relax this assumption */
 543         if (dev->caps.uar_page_size != PAGE_SIZE) {
 544                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
 545                          dev->caps.uar_page_size, PAGE_SIZE);
 546                 return -ENODEV;
 547         }
 548
 549         memset(&func_cap, 0, sizeof(func_cap));
 550         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 551         if (err) {
 552                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
 553                           err);
 554                 return err;
 555         }
 556
 557         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 558             PF_CONTEXT_BEHAVIOUR_MASK) {
 559                 mlx4_err(dev, "Unknown pf context behaviour\n");
 560                 return -ENOSYS;
 561         }
 562
 563         dev->caps.num_ports             = func_cap.num_ports;
 564         dev->caps.num_qps               = func_cap.qp_quota;
 565         dev->caps.num_srqs              = func_cap.srq_quota;
 566         dev->caps.num_cqs               = func_cap.cq_quota;
 567         dev->caps.num_eqs               = func_cap.max_eq;
 568         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 569         dev->caps.num_mpts              = func_cap.mpt_quota;
 570         dev->caps.num_mtts              = func_cap.mtt_quota;
 571         dev->caps.num_pds               = MLX4_NUM_PDS;
 572         dev->caps.num_mgms              = 0;
 573         dev->caps.num_amgms             = 0;
 574
 575         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 576                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 577                          "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
 578                 return -ENODEV;
 579         }
 580
 581         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 582         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 583         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 584         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 585
 586         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 587             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
 588                 err = -ENOMEM;
 589                 goto err_mem;
 590         }
 591
 592         for (i = 1; i <= dev->caps.num_ports; ++i) {
 593                 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
 594                 if (err) {
 595                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
 596                                  " port %d, aborting (%d).\n", i, err);
 597                         goto err_mem;
 598                 }
 599                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 600                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 601                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 602                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 603                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 604                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 605                                                     &dev->caps.gid_table_len[i],
 606                                                     &dev->caps.pkey_table_len[i]))
 607                         goto err_mem;
 608         }
 609
 610         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 611                                        dev->caps.reserved_uars) >
 612                                        pci_resource_len(dev->pdev, 2)) {
 613                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
 614                          "PCI resource 2 size of 0x%llx, aborting.\n",
 615                          dev->caps.uar_page_size * dev->caps.num_uars,
 616                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 617                 goto err_mem;
 618         }
 619
 620         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 621                 dev->caps.eqe_size   = 64;
 622                 dev->caps.eqe_factor = 1;
 623         } else {
 624                 dev->caps.eqe_size   = 32;
 625                 dev->caps.eqe_factor = 0;
 626         }
 627
 628         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 629                 dev->caps.cqe_size   = 64;
 630                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
 631         } else {
 632                 dev->caps.cqe_size   = 32;
 633         }
 634
 635         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 636
 637         return 0;
 638
 639 err_mem:
 640         kfree(dev->caps.qp0_tunnel);
 641         kfree(dev->caps.qp0_proxy);
 642         kfree(dev->caps.qp1_tunnel);
 643         kfree(dev->caps.qp1_proxy);
 644         dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
 645                 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
 646
 647         return err;
 648 }
 649
 650 /*
 651  * Change the port configuration of the device.
 652  * Every user of this function must hold the port mutex.
 653  */
 654 int mlx4_change_port_types(struct mlx4_dev *dev,
 655                            enum mlx4_port_type *port_types)
 656 {
 657         int err = 0;
 658         int change = 0;
 659         int port;
 660
 661         for (port = 0; port <  dev->caps.num_ports; port++) {
 662                 /* Change the port type only if the new type is different
 663                  * from the current, and not set to Auto */
 664                 if (port_types[port] != dev->caps.port_type[port + 1])
 665                         change = 1;
 666         }
 667         if (change) {
 668                 mlx4_unregister_device(dev);
 669                 for (port = 1; port <= dev->caps.num_ports; port++) {
 670                         mlx4_CLOSE_PORT(dev, port);
 671                         dev->caps.port_type[port] = port_types[port - 1];
 672                         err = mlx4_SET_PORT(dev, port, -1);
 673                         if (err) {
 674                                 mlx4_err(dev, "Failed to set port %d, "
 675                                               "aborting\n", port);
 676                                 goto out;
 677                         }
 678                 }
 679                 mlx4_set_port_mask(dev);
 680                 err = mlx4_register_device(dev);
 681         }
 682
 683 out:
 684         return err;
 685 }
 686
 687 static ssize_t show_port_type(struct device *dev,
 688                               struct device_attribute *attr,
 689                               char *buf)
 690 {
 691         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 692                                                    port_attr);
 693         struct mlx4_dev *mdev = info->dev;
 694         char type[8];
 695
 696         sprintf(type, "%s",
 697                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 698                 "ib" : "eth");
 699         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 700                 sprintf(buf, "auto (%s)\n", type);
 701         else
 702                 sprintf(buf, "%s\n", type);
 703
 704         return strlen(buf);
 705 }
 706
 707 static ssize_t set_port_type(struct device *dev,
 708                              struct device_attribute *attr,
 709                              const char *buf, size_t count)
 710 {
 711         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 712                                                    port_attr);
 713         struct mlx4_dev *mdev = info->dev;
 714         struct mlx4_priv *priv = mlx4_priv(mdev);
 715         enum mlx4_port_type types[MLX4_MAX_PORTS];
 716         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 717         int i;
 718         int err = 0;
 719
 720         if (!strcmp(buf, "ib\n"))
 721                 info->tmp_type = MLX4_PORT_TYPE_IB;
 722         else if (!strcmp(buf, "eth\n"))
 723                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 724         else if (!strcmp(buf, "auto\n"))
 725                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 726         else {
 727                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 728                 return -EINVAL;
 729         }
 730
 731         mlx4_stop_sense(mdev);
 732         mutex_lock(&priv->port_mutex);
 733         /* Possible type is always the one that was delivered */
 734         mdev->caps.possible_type[info->port] = info->tmp_type;
 735
 736         for (i = 0; i < mdev->caps.num_ports; i++) {
 737                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 738                                         mdev->caps.possible_type[i+1];
 739                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 740                         types[i] = mdev->caps.port_type[i+1];
 741         }
 742
 743         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 744             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
 745                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 746                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 747                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 748                                 err = -EINVAL;
 749                         }
 750                 }
 751         }
 752         if (err) {
 753                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 754                                "Set only 'eth' or 'ib' for both ports "
 755                                "(should be the same)\n");
 756                 goto out;
 757         }
 758
 759         mlx4_do_sense_ports(mdev, new_types, types);
 760
 761         err = mlx4_check_port_params(mdev, new_types);
 762         if (err)
 763                 goto out;
 764
 765         /* We are about to apply the changes after the configuration
 766          * was verified, no need to remember the temporary types
 767          * any more */
 768         for (i = 0; i < mdev->caps.num_ports; i++)
 769                 priv->port[i + 1].tmp_type = 0;
 770
 771         err = mlx4_change_port_types(mdev, new_types);
 772
 773 out:
 774         mlx4_start_sense(mdev);
 775         mutex_unlock(&priv->port_mutex);
 776         return err ? err : count;
 777 }
 778
 779 enum ibta_mtu {
 780         IB_MTU_256  = 1,
 781         IB_MTU_512  = 2,
 782         IB_MTU_1024 = 3,
 783         IB_MTU_2048 = 4,
 784         IB_MTU_4096 = 5
 785 };
 786
 787 static inline int int_to_ibta_mtu(int mtu)
 788 {
 789         switch (mtu) {
 790         case 256:  return IB_MTU_256;
 791         case 512:  return IB_MTU_512;
 792         case 1024: return IB_MTU_1024;
 793         case 2048: return IB_MTU_2048;
 794         case 4096: return IB_MTU_4096;
 795         default: return -1;
 796         }
 797 }
 798
 799 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
 800 {
 801         switch (mtu) {
 802         case IB_MTU_256:  return  256;
 803         case IB_MTU_512:  return  512;
 804         case IB_MTU_1024: return 1024;
 805         case IB_MTU_2048: return 2048;
 806         case IB_MTU_4096: return 4096;
 807         default: return -1;
 808         }
 809 }
 810
 811 static ssize_t show_port_ib_mtu(struct device *dev,
 812                              struct device_attribute *attr,
 813                              char *buf)
 814 {
 815         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 816                                                    port_mtu_attr);
 817         struct mlx4_dev *mdev = info->dev;
 818
 819         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
 820                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 821
 822         sprintf(buf, "%d\n",
 823                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
 824         return strlen(buf);
 825 }
 826
 827 static ssize_t set_port_ib_mtu(struct device *dev,
 828                              struct device_attribute *attr,
 829                              const char *buf, size_t count)
 830 {
 831         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 832                                                    port_mtu_attr);
 833         struct mlx4_dev *mdev = info->dev;
 834         struct mlx4_priv *priv = mlx4_priv(mdev);
 835         int err, port, mtu, ibta_mtu = -1;
 836
 837         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
 838                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 839                 return -EINVAL;
 840         }
 841
 842         err = sscanf(buf, "%d", &mtu);
 843         if (err > 0)
 844                 ibta_mtu = int_to_ibta_mtu(mtu);
 845
 846         if (err <= 0 || ibta_mtu < 0) {
 847                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
 848                 return -EINVAL;
 849         }
 850
 851         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
 852
 853         mlx4_stop_sense(mdev);
 854         mutex_lock(&priv->port_mutex);
 855         mlx4_unregister_device(mdev);
 856         for (port = 1; port <= mdev->caps.num_ports; port++) {
 857                 mlx4_CLOSE_PORT(mdev, port);
 858                 err = mlx4_SET_PORT(mdev, port, -1);
 859                 if (err) {
 860                         mlx4_err(mdev, "Failed to set port %d, "
 861                                       "aborting\n", port);
 862                         goto err_set_port;
 863                 }
 864         }
 865         err = mlx4_register_device(mdev);
 866 err_set_port:
 867         mutex_unlock(&priv->port_mutex);
 868         mlx4_start_sense(mdev);
 869         return err ? err : count;
 870 }
 871
 872 static int mlx4_load_fw(struct mlx4_dev *dev)
 873 {
 874         struct mlx4_priv *priv = mlx4_priv(dev);
 875         int err;
 876
 877         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 878                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 879         if (!priv->fw.fw_icm) {
 880                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 881                 return -ENOMEM;
 882         }
 883
 884         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
 885         if (err) {
 886                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
 887                 goto err_free;
 888         }
 889
 890         err = mlx4_RUN_FW(dev);
 891         if (err) {
 892                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
 893                 goto err_unmap_fa;
 894         }
 895
 896         return 0;
 897
 898 err_unmap_fa:
 899         mlx4_UNMAP_FA(dev);
 900
 901 err_free:
 902         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 903         return err;
 904 }
 905
 906 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
 907                                 int cmpt_entry_sz)
 908 {
 909         struct mlx4_priv *priv = mlx4_priv(dev);
 910         int err;
 911         int num_eqs;
 912
 913         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
 914                                   cmpt_base +
 915                                   ((u64) (MLX4_CMPT_TYPE_QP *
 916                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 917                                   cmpt_entry_sz, dev->caps.num_qps,
 918                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 919                                   0, 0);
 920         if (err)
 921                 goto err;
 922
 923         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
 924                                   cmpt_base +
 925                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
 926                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 927                                   cmpt_entry_sz, dev->caps.num_srqs,
 928                                   dev->caps.reserved_srqs, 0, 0);
 929         if (err)
 930                 goto err_qp;
 931
 932         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
 933                                   cmpt_base +
 934                                   ((u64) (MLX4_CMPT_TYPE_CQ *
 935                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 936                                   cmpt_entry_sz, dev->caps.num_cqs,
 937                                   dev->caps.reserved_cqs, 0, 0);
 938         if (err)
 939                 goto err_srq;
 940
 941         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
 942                   dev->caps.num_eqs;
 943         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
 944                                   cmpt_base +
 945                                   ((u64) (MLX4_CMPT_TYPE_EQ *
 946                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 947                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
 948         if (err)
 949                 goto err_cq;
 950
 951         return 0;
 952
 953 err_cq:
 954         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 955
 956 err_srq:
 957         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 958
 959 err_qp:
 960         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 961
 962 err:
 963         return err;
 964 }
 965
 966 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
 967                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
 968 {
 969         struct mlx4_priv *priv = mlx4_priv(dev);
 970         u64 aux_pages;
 971         int num_eqs;
 972         int err;
 973
 974         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
 975         if (err) {
 976                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
 977                 return err;
 978         }
 979
 980         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
 981                  (unsigned long long) icm_size >> 10,
 982                  (unsigned long long) aux_pages << 2);
 983
 984         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
 985                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
 986         if (!priv->fw.aux_icm) {
 987                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
 988                 return -ENOMEM;
 989         }
 990
 991         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
 992         if (err) {
 993                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
 994                 goto err_free_aux;
 995         }
 996
 997         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
 998         if (err) {
 999                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1000                 goto err_unmap_aux;
1001         }
1002
1003
1004         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1005                    dev->caps.num_eqs;
1006         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1007                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1008                                   num_eqs, num_eqs, 0, 0);
1009         if (err) {
1010                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1011                 goto err_unmap_cmpt;
1012         }
1013
1014         /*
1015          * Reserved MTT entries must be aligned up to a cacheline
1016          * boundary, since the FW will write to them, while the driver
1017          * writes to all other MTT entries. (The variable
1018          * dev->caps.mtt_entry_sz below is really the MTT segment
1019          * size, not the raw entry size)
1020          */
1021         dev->caps.reserved_mtts =
1022                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1023                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1024
1025         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1026                                   init_hca->mtt_base,
1027                                   dev->caps.mtt_entry_sz,
1028                                   dev->caps.num_mtts,
1029                                   dev->caps.reserved_mtts, 1, 0);
1030         if (err) {
1031                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1032                 goto err_unmap_eq;
1033         }
1034
1035         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1036                                   init_hca->dmpt_base,
1037                                   dev_cap->dmpt_entry_sz,
1038                                   dev->caps.num_mpts,
1039                                   dev->caps.reserved_mrws, 1, 1);
1040         if (err) {
1041                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1042                 goto err_unmap_mtt;
1043         }
1044
1045         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1046                                   init_hca->qpc_base,
1047                                   dev_cap->qpc_entry_sz,
1048                                   dev->caps.num_qps,
1049                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1050                                   0, 0);
1051         if (err) {
1052                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1053                 goto err_unmap_dmpt;
1054         }
1055
1056         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1057                                   init_hca->auxc_base,
1058                                   dev_cap->aux_entry_sz,
1059                                   dev->caps.num_qps,
1060                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1061                                   0, 0);
1062         if (err) {
1063                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1064                 goto err_unmap_qp;
1065         }
1066
1067         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1068                                   init_hca->altc_base,
1069                                   dev_cap->altc_entry_sz,
1070                                   dev->caps.num_qps,
1071                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1072                                   0, 0);
1073         if (err) {
1074                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1075                 goto err_unmap_auxc;
1076         }
1077
1078         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1079                                   init_hca->rdmarc_base,
1080                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1081                                   dev->caps.num_qps,
1082                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1083                                   0, 0);
1084         if (err) {
1085                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1086                 goto err_unmap_altc;
1087         }
1088
1089         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1090                                   init_hca->cqc_base,
1091                                   dev_cap->cqc_entry_sz,
1092                                   dev->caps.num_cqs,
1093                                   dev->caps.reserved_cqs, 0, 0);
1094         if (err) {
1095                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1096                 goto err_unmap_rdmarc;
1097         }
1098
1099         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1100                                   init_hca->srqc_base,
1101                                   dev_cap->srq_entry_sz,
1102                                   dev->caps.num_srqs,
1103                                   dev->caps.reserved_srqs, 0, 0);
1104         if (err) {
1105                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1106                 goto err_unmap_cq;
1107         }
1108
1109         /*
1110          * For flow steering device managed mode it is required to use
1111          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1112          * required, but for simplicity just map the whole multicast
1113          * group table now.  The table isn't very big and it's a lot
1114          * easier than trying to track ref counts.
1115          */
1116         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1117                                   init_hca->mc_base,
1118                                   mlx4_get_mgm_entry_size(dev),
1119                                   dev->caps.num_mgms + dev->caps.num_amgms,
1120                                   dev->caps.num_mgms + dev->caps.num_amgms,
1121                                   0, 0);
1122         if (err) {
1123                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1124                 goto err_unmap_srq;
1125         }
1126
1127         return 0;
1128
1129 err_unmap_srq:
1130         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1131
1132 err_unmap_cq:
1133         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1134
1135 err_unmap_rdmarc:
1136         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1137
1138 err_unmap_altc:
1139         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1140
1141 err_unmap_auxc:
1142         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1143
1144 err_unmap_qp:
1145         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1146
1147 err_unmap_dmpt:
1148         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1149
1150 err_unmap_mtt:
1151         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1152
1153 err_unmap_eq:
1154         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1155
1156 err_unmap_cmpt:
1157         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1158         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1159         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1160         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1161
1162 err_unmap_aux:
1163         mlx4_UNMAP_ICM_AUX(dev);
1164
1165 err_free_aux:
1166         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1167
1168         return err;
1169 }
1170
1171 static void mlx4_free_icms(struct mlx4_dev *dev)
1172 {
1173         struct mlx4_priv *priv = mlx4_priv(dev);
1174
1175         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1176         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1177         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1178         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1179         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1180         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1181         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1182         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1183         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1184         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1185         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1186         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1187         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1188         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1189
1190         mlx4_UNMAP_ICM_AUX(dev);
1191         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1192 }
1193
1194 static void mlx4_slave_exit(struct mlx4_dev *dev)
1195 {
1196         struct mlx4_priv *priv = mlx4_priv(dev);
1197
1198         mutex_lock(&priv->cmd.slave_cmd_mutex);
1199         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1200                 mlx4_warn(dev, "Failed to close slave function.\n");
1201         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1202 }
1203
1204 static int map_bf_area(struct mlx4_dev *dev)
1205 {
1206         struct mlx4_priv *priv = mlx4_priv(dev);
1207         resource_size_t bf_start;
1208         resource_size_t bf_len;
1209         int err = 0;
1210
1211         if (!dev->caps.bf_reg_size)
1212                 return -ENXIO;
1213
1214         bf_start = pci_resource_start(dev->pdev, 2) +
1215                         (dev->caps.num_uars << PAGE_SHIFT);
1216         bf_len = pci_resource_len(dev->pdev, 2) -
1217                         (dev->caps.num_uars << PAGE_SHIFT);
1218         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1219         if (!priv->bf_mapping)
1220                 err = -ENOMEM;
1221
1222         return err;
1223 }
1224
1225 static void unmap_bf_area(struct mlx4_dev *dev)
1226 {
1227         if (mlx4_priv(dev)->bf_mapping)
1228                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1229 }
1230
1231 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1232 {
1233         u32 clockhi, clocklo, clockhi1;
1234         cycle_t cycles;
1235         int i;
1236         struct mlx4_priv *priv = mlx4_priv(dev);
1237
1238         for (i = 0; i < 10; i++) {
1239                 clockhi = swab32(readl(priv->clock_mapping));
1240                 clocklo = swab32(readl(priv->clock_mapping + 4));
1241                 clockhi1 = swab32(readl(priv->clock_mapping));
1242                 if (clockhi == clockhi1)
1243                         break;
1244         }
1245
1246         cycles = (u64) clockhi << 32 | (u64) clocklo;
1247
1248         return cycles;
1249 }
1250 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1251
1252
1253 static int map_internal_clock(struct mlx4_dev *dev)
1254 {
1255         struct mlx4_priv *priv = mlx4_priv(dev);
1256
1257         priv->clock_mapping =
1258                 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1259                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1260
1261         if (!priv->clock_mapping)
1262                 return -ENOMEM;
1263
1264         return 0;
1265 }
1266
1267 static void unmap_internal_clock(struct mlx4_dev *dev)
1268 {
1269         struct mlx4_priv *priv = mlx4_priv(dev);
1270
1271         if (priv->clock_mapping)
1272                 iounmap(priv->clock_mapping);
1273 }
1274
1275 static void mlx4_close_hca(struct mlx4_dev *dev)
1276 {
1277         unmap_internal_clock(dev);
1278         unmap_bf_area(dev);
1279         if (mlx4_is_slave(dev))
1280                 mlx4_slave_exit(dev);
1281         else {
1282                 mlx4_CLOSE_HCA(dev, 0);
1283                 mlx4_free_icms(dev);
1284                 mlx4_UNMAP_FA(dev);
1285                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1286         }
1287 }
1288
1289 static int mlx4_init_slave(struct mlx4_dev *dev)
1290 {
1291         struct mlx4_priv *priv = mlx4_priv(dev);
1292         u64 dma = (u64) priv->mfunc.vhcr_dma;
1293         int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1294         int ret_from_reset = 0;
1295         u32 slave_read;
1296         u32 cmd_channel_ver;
1297
1298         mutex_lock(&priv->cmd.slave_cmd_mutex);
1299         priv->cmd.max_cmds = 1;
1300         mlx4_warn(dev, "Sending reset\n");
1301         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1302                                        MLX4_COMM_TIME);
1303         /* if we are in the middle of flr the slave will try
1304          * NUM_OF_RESET_RETRIES times before leaving.*/
1305         if (ret_from_reset) {
1306                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1307                         msleep(SLEEP_TIME_IN_RESET);
1308                         while (ret_from_reset && num_of_reset_retries) {
1309                                 mlx4_warn(dev, "slave is currently in the"
1310                                           "middle of FLR. retrying..."
1311                                           "(try num:%d)\n",
1312                                           (NUM_OF_RESET_RETRIES -
1313                                            num_of_reset_retries  + 1));
1314                                 ret_from_reset =
1315                                         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1316                                                       0, MLX4_COMM_TIME);
1317                                 num_of_reset_retries = num_of_reset_retries - 1;
1318                         }
1319                 } else
1320                         goto err;
1321         }
1322
1323         /* check the driver version - the slave I/F revision
1324          * must match the master's */
1325         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1326         cmd_channel_ver = mlx4_comm_get_version();
1327
1328         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1329                 MLX4_COMM_GET_IF_REV(slave_read)) {
1330                 mlx4_err(dev, "slave driver version is not supported"
1331                          " by the master\n");
1332                 goto err;
1333         }
1334
1335         mlx4_warn(dev, "Sending vhcr0\n");
1336         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1337                                                     MLX4_COMM_TIME))
1338                 goto err;
1339         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1340                                                     MLX4_COMM_TIME))
1341                 goto err;
1342         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1343                                                     MLX4_COMM_TIME))
1344                 goto err;
1345         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1346                 goto err;
1347
1348         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1349         return 0;
1350
1351 err:
1352         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1353         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1354         return -EIO;
1355 }
1356
1357 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1358 {
1359         int i;
1360
1361         for (i = 1; i <= dev->caps.num_ports; i++) {
1362                 dev->caps.gid_table_len[i] = 1;
1363                 dev->caps.pkey_table_len[i] =
1364                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1365         }
1366 }
1367
1368 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1369 {
1370         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1371
1372         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1373               i++) {
1374                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1375                         break;
1376         }
1377
1378         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1379 }
1380
1381 static void choose_steering_mode(struct mlx4_dev *dev,
1382                                  struct mlx4_dev_cap *dev_cap)
1383 {
1384         if (mlx4_log_num_mgm_entry_size == -1 &&
1385             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1386             (!mlx4_is_mfunc(dev) ||
1387              (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1388             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1389                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1390                 dev->oper_log_mgm_entry_size =
1391                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1392                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1393                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1394                 dev->caps.fs_log_max_ucast_qp_range_size =
1395                         dev_cap->fs_log_max_ucast_qp_range_size;
1396         } else {
1397                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1398                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1399                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1400                 else {
1401                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1402
1403                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1404                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1405                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1406                                           "set to use B0 steering. Falling back to A0 steering mode.\n");
1407                 }
1408                 dev->oper_log_mgm_entry_size =
1409                         mlx4_log_num_mgm_entry_size > 0 ?
1410                         mlx4_log_num_mgm_entry_size :
1411                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1412                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1413         }
1414         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1415                  "modparam log_num_mgm_entry_size = %d\n",
1416                  mlx4_steering_mode_str(dev->caps.steering_mode),
1417                  dev->oper_log_mgm_entry_size,
1418                  mlx4_log_num_mgm_entry_size);
1419 }
1420
1421 static int mlx4_init_hca(struct mlx4_dev *dev)
1422 {
1423         struct mlx4_priv          *priv = mlx4_priv(dev);
1424         struct mlx4_adapter        adapter;
1425         struct mlx4_dev_cap        dev_cap;
1426         struct mlx4_mod_stat_cfg   mlx4_cfg;
1427         struct mlx4_profile        profile;
1428         struct mlx4_init_hca_param init_hca;
1429         u64 icm_size;
1430         int err;
1431
1432         if (!mlx4_is_slave(dev)) {
1433                 err = mlx4_QUERY_FW(dev);
1434                 if (err) {
1435                         if (err == -EACCES)
1436                                 mlx4_info(dev, "non-primary physical function, skipping.\n");
1437                         else
1438                                 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1439                         return err;
1440                 }
1441
1442                 err = mlx4_load_fw(dev);
1443                 if (err) {
1444                         mlx4_err(dev, "Failed to start FW, aborting.\n");
1445                         return err;
1446                 }
1447
1448                 mlx4_cfg.log_pg_sz_m = 1;
1449                 mlx4_cfg.log_pg_sz = 0;
1450                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1451                 if (err)
1452                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1453
1454                 err = mlx4_dev_cap(dev, &dev_cap);
1455                 if (err) {
1456                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1457                         goto err_stop_fw;
1458                 }
1459
1460                 choose_steering_mode(dev, &dev_cap);
1461
1462                 if (mlx4_is_master(dev))
1463                         mlx4_parav_master_pf_caps(dev);
1464
1465                 profile = default_profile;
1466                 if (dev->caps.steering_mode ==
1467                     MLX4_STEERING_MODE_DEVICE_MANAGED)
1468                         profile.num_mcg = MLX4_FS_NUM_MCG;
1469
1470                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1471                                              &init_hca);
1472                 if ((long long) icm_size < 0) {
1473                         err = icm_size;
1474                         goto err_stop_fw;
1475                 }
1476
1477                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1478
1479                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1480                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1481                 init_hca.mw_enabled = 0;
1482                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1483                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1484                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1485
1486                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1487                 if (err)
1488                         goto err_stop_fw;
1489
1490                 err = mlx4_INIT_HCA(dev, &init_hca);
1491                 if (err) {
1492                         mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1493                         goto err_free_icm;
1494                 }
1495                 /*
1496                  * If TS is supported by FW
1497                  * read HCA frequency by QUERY_HCA command
1498                  */
1499                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1500                         memset(&init_hca, 0, sizeof(init_hca));
1501                         err = mlx4_QUERY_HCA(dev, &init_hca);
1502                         if (err) {
1503                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1504                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1505                         } else {
1506                                 dev->caps.hca_core_clock =
1507                                         init_hca.hca_core_clock;
1508                         }
1509
1510                         /* In case we got HCA frequency 0 - disable timestamping
1511                          * to avoid dividing by zero
1512                          */
1513                         if (!dev->caps.hca_core_clock) {
1514                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1515                                 mlx4_err(dev,
1516                                          "HCA frequency is 0. Timestamping is not supported.");
1517                         } else if (map_internal_clock(dev)) {
1518                                 /*
1519                                  * Map internal clock,
1520                                  * in case of failure disable timestamping
1521                                  */
1522                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1523                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1524                         }
1525                 }
1526         } else {
1527                 err = mlx4_init_slave(dev);
1528                 if (err) {
1529                         mlx4_err(dev, "Failed to initialize slave\n");
1530                         return err;
1531                 }
1532
1533                 err = mlx4_slave_cap(dev);
1534                 if (err) {
1535                         mlx4_err(dev, "Failed to obtain slave caps\n");
1536                         goto err_close;
1537                 }
1538         }
1539
1540         if (map_bf_area(dev))
1541                 mlx4_dbg(dev, "Failed to map blue flame area\n");
1542
1543         /*Only the master set the ports, all the rest got it from it.*/
1544         if (!mlx4_is_slave(dev))
1545                 mlx4_set_port_mask(dev);
1546
1547         err = mlx4_QUERY_ADAPTER(dev, &adapter);
1548         if (err) {
1549                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1550                 goto unmap_bf;
1551         }
1552
1553         priv->eq_table.inta_pin = adapter.inta_pin;
1554         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1555
1556         return 0;
1557
1558 unmap_bf:
1559         unmap_internal_clock(dev);
1560         unmap_bf_area(dev);
1561
1562 err_close:
1563         if (mlx4_is_slave(dev))
1564                 mlx4_slave_exit(dev);
1565         else
1566                 mlx4_CLOSE_HCA(dev, 0);
1567
1568 err_free_icm:
1569         if (!mlx4_is_slave(dev))
1570                 mlx4_free_icms(dev);
1571
1572 err_stop_fw:
1573         if (!mlx4_is_slave(dev)) {
1574                 mlx4_UNMAP_FA(dev);
1575                 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1576         }
1577         return err;
1578 }
1579
1580 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1581 {
1582         struct mlx4_priv *priv = mlx4_priv(dev);
1583         int nent;
1584
1585         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1586                 return -ENOENT;
1587
1588         nent = dev->caps.max_counters;
1589         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1590 }
1591
1592 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1593 {
1594         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1595 }
1596
1597 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1598 {
1599         struct mlx4_priv *priv = mlx4_priv(dev);
1600
1601         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1602                 return -ENOENT;
1603
1604         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1605         if (*idx == -1)
1606                 return -ENOMEM;
1607
1608         return 0;
1609 }
1610
1611 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1612 {
1613         u64 out_param;
1614         int err;
1615
1616         if (mlx4_is_mfunc(dev)) {
1617                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1618                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1619                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1620                 if (!err)
1621                         *idx = get_param_l(&out_param);
1622
1623                 return err;
1624         }
1625         return __mlx4_counter_alloc(dev, idx);
1626 }
1627 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1628
1629 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1630 {
1631         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1632         return;
1633 }
1634
1635 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1636 {
1637         u64 in_param = 0;
1638
1639         if (mlx4_is_mfunc(dev)) {
1640                 set_param_l(&in_param, idx);
1641                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1642                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1643                          MLX4_CMD_WRAPPED);
1644                 return;
1645         }
1646         __mlx4_counter_free(dev, idx);
1647 }
1648 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1649
1650 static int mlx4_setup_hca(struct mlx4_dev *dev)
1651 {
1652         struct mlx4_priv *priv = mlx4_priv(dev);
1653         int err;
1654         int port;
1655         __be32 ib_port_default_caps;
1656
1657         err = mlx4_init_uar_table(dev);
1658         if (err) {
1659                 mlx4_err(dev, "Failed to initialize "
1660                          "user access region table, aborting.\n");
1661                 return err;
1662         }
1663
1664         err = mlx4_uar_alloc(dev, &priv->driver_uar);
1665         if (err) {
1666                 mlx4_err(dev, "Failed to allocate driver access region, "
1667                          "aborting.\n");
1668                 goto err_uar_table_free;
1669         }
1670
1671         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1672         if (!priv->kar) {
1673                 mlx4_err(dev, "Couldn't map kernel access region, "
1674                          "aborting.\n");
1675                 err = -ENOMEM;
1676                 goto err_uar_free;
1677         }
1678
1679         err = mlx4_init_pd_table(dev);
1680         if (err) {
1681                 mlx4_err(dev, "Failed to initialize "
1682                          "protection domain table, aborting.\n");
1683                 goto err_kar_unmap;
1684         }
1685
1686         err = mlx4_init_xrcd_table(dev);
1687         if (err) {
1688                 mlx4_err(dev, "Failed to initialize "
1689                          "reliable connection domain table, aborting.\n");
1690                 goto err_pd_table_free;
1691         }
1692
1693         err = mlx4_init_mr_table(dev);
1694         if (err) {
1695                 mlx4_err(dev, "Failed to initialize "
1696                          "memory region table, aborting.\n");
1697                 goto err_xrcd_table_free;
1698         }
1699
1700         err = mlx4_init_eq_table(dev);
1701         if (err) {
1702                 mlx4_err(dev, "Failed to initialize "
1703                          "event queue table, aborting.\n");
1704                 goto err_mr_table_free;
1705         }
1706
1707         err = mlx4_cmd_use_events(dev);
1708         if (err) {
1709                 mlx4_err(dev, "Failed to switch to event-driven "
1710                          "firmware commands, aborting.\n");
1711                 goto err_eq_table_free;
1712         }
1713
1714         err = mlx4_NOP(dev);
1715         if (err) {
1716                 if (dev->flags & MLX4_FLAG_MSI_X) {
1717                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
1718                                   "interrupt IRQ %d).\n",
1719                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1720                         mlx4_warn(dev, "Trying again without MSI-X.\n");
1721                 } else {
1722                         mlx4_err(dev, "NOP command failed to generate interrupt "
1723                                  "(IRQ %d), aborting.\n",
1724                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1725                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1726                 }
1727
1728                 goto err_cmd_poll;
1729         }
1730
1731         mlx4_dbg(dev, "NOP command IRQ test passed\n");
1732
1733         err = mlx4_init_cq_table(dev);
1734         if (err) {
1735                 mlx4_err(dev, "Failed to initialize "
1736                          "completion queue table, aborting.\n");
1737                 goto err_cmd_poll;
1738         }
1739
1740         err = mlx4_init_srq_table(dev);
1741         if (err) {
1742                 mlx4_err(dev, "Failed to initialize "
1743                          "shared receive queue table, aborting.\n");
1744                 goto err_cq_table_free;
1745         }
1746
1747         err = mlx4_init_qp_table(dev);
1748         if (err) {
1749                 mlx4_err(dev, "Failed to initialize "
1750                          "queue pair table, aborting.\n");
1751                 goto err_srq_table_free;
1752         }
1753
1754         if (!mlx4_is_slave(dev)) {
1755                 err = mlx4_init_mcg_table(dev);
1756                 if (err) {
1757                         mlx4_err(dev, "Failed to initialize "
1758                                  "multicast group table, aborting.\n");
1759                         goto err_qp_table_free;
1760                 }
1761         }
1762
1763         err = mlx4_init_counters_table(dev);
1764         if (err && err != -ENOENT) {
1765                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1766                 goto err_mcg_table_free;
1767         }
1768
1769         if (!mlx4_is_slave(dev)) {
1770                 for (port = 1; port <= dev->caps.num_ports; port++) {
1771                         ib_port_default_caps = 0;
1772                         err = mlx4_get_port_ib_caps(dev, port,
1773                                                     &ib_port_default_caps);
1774                         if (err)
1775                                 mlx4_warn(dev, "failed to get port %d default "
1776                                           "ib capabilities (%d). Continuing "
1777                                           "with caps = 0\n", port, err);
1778                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1779
1780                         /* initialize per-slave default ib port capabilities */
1781                         if (mlx4_is_master(dev)) {
1782                                 int i;
1783                                 for (i = 0; i < dev->num_slaves; i++) {
1784                                         if (i == mlx4_master_func_num(dev))
1785                                                 continue;
1786                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1787                                                         ib_port_default_caps;
1788                                 }
1789                         }
1790
1791                         if (mlx4_is_mfunc(dev))
1792                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1793                         else
1794                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1795
1796                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1797                                             dev->caps.pkey_table_len[port] : -1);
1798                         if (err) {
1799                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1800                                         port);
1801                                 goto err_counters_table_free;
1802                         }
1803                 }
1804         }
1805
1806         return 0;
1807
1808 err_counters_table_free:
1809         mlx4_cleanup_counters_table(dev);
1810
1811 err_mcg_table_free:
1812         mlx4_cleanup_mcg_table(dev);
1813
1814 err_qp_table_free:
1815         mlx4_cleanup_qp_table(dev);
1816
1817 err_srq_table_free:
1818         mlx4_cleanup_srq_table(dev);
1819
1820 err_cq_table_free:
1821         mlx4_cleanup_cq_table(dev);
1822
1823 err_cmd_poll:
1824         mlx4_cmd_use_polling(dev);
1825
1826 err_eq_table_free:
1827         mlx4_cleanup_eq_table(dev);
1828
1829 err_mr_table_free:
1830         mlx4_cleanup_mr_table(dev);
1831
1832 err_xrcd_table_free:
1833         mlx4_cleanup_xrcd_table(dev);
1834
1835 err_pd_table_free:
1836         mlx4_cleanup_pd_table(dev);
1837
1838 err_kar_unmap:
1839         iounmap(priv->kar);
1840
1841 err_uar_free:
1842         mlx4_uar_free(dev, &priv->driver_uar);
1843
1844 err_uar_table_free:
1845         mlx4_cleanup_uar_table(dev);
1846         return err;
1847 }
1848
1849 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1850 {
1851         struct mlx4_priv *priv = mlx4_priv(dev);
1852         struct msix_entry *entries;
1853         int nreq = min_t(int, dev->caps.num_ports *
1854                          min_t(int, netif_get_num_default_rss_queues() + 1,
1855                                MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1856         int err;
1857         int i;
1858
1859         if (msi_x) {
1860                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1861                              nreq);
1862
1863                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1864                 if (!entries)
1865                         goto no_msi;
1866
1867                 for (i = 0; i < nreq; ++i)
1868                         entries[i].entry = i;
1869
1870         retry:
1871                 err = pci_enable_msix(dev->pdev, entries, nreq);
1872                 if (err) {
1873                         /* Try again if at least 2 vectors are available */
1874                         if (err > 1) {
1875                                 mlx4_info(dev, "Requested %d vectors, "
1876                                           "but only %d MSI-X vectors available, "
1877                                           "trying again\n", nreq, err);
1878                                 nreq = err;
1879                                 goto retry;
1880                         }
1881                         kfree(entries);
1882                         goto no_msi;
1883                 }
1884
1885                 if (nreq <
1886                     MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1887                         /*Working in legacy mode , all EQ's shared*/
1888                         dev->caps.comp_pool           = 0;
1889                         dev->caps.num_comp_vectors = nreq - 1;
1890                 } else {
1891                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
1892                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1893                 }
1894                 for (i = 0; i < nreq; ++i)
1895                         priv->eq_table.eq[i].irq = entries[i].vector;
1896
1897                 dev->flags |= MLX4_FLAG_MSI_X;
1898
1899                 kfree(entries);
1900                 return;
1901         }
1902
1903 no_msi:
1904         dev->caps.num_comp_vectors = 1;
1905         dev->caps.comp_pool        = 0;
1906
1907         for (i = 0; i < 2; ++i)
1908                 priv->eq_table.eq[i].irq = dev->pdev->irq;
1909 }
1910
1911 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1912 {
1913         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1914         int err = 0;
1915
1916         info->dev = dev;
1917         info->port = port;
1918         if (!mlx4_is_slave(dev)) {
1919                 mlx4_init_mac_table(dev, &info->mac_table);
1920                 mlx4_init_vlan_table(dev, &info->vlan_table);
1921                 info->base_qpn = mlx4_get_base_qpn(dev, port);
1922         }
1923
1924         sprintf(info->dev_name, "mlx4_port%d", port);
1925         info->port_attr.attr.name = info->dev_name;
1926         if (mlx4_is_mfunc(dev))
1927                 info->port_attr.attr.mode = S_IRUGO;
1928         else {
1929                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1930                 info->port_attr.store     = set_port_type;
1931         }
1932         info->port_attr.show      = show_port_type;
1933         sysfs_attr_init(&info->port_attr.attr);
1934
1935         err = device_create_file(&dev->pdev->dev, &info->port_attr);
1936         if (err) {
1937                 mlx4_err(dev, "Failed to create file for port %d\n", port);
1938                 info->port = -1;
1939         }
1940
1941         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1942         info->port_mtu_attr.attr.name = info->dev_mtu_name;
1943         if (mlx4_is_mfunc(dev))
1944                 info->port_mtu_attr.attr.mode = S_IRUGO;
1945         else {
1946                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1947                 info->port_mtu_attr.store     = set_port_ib_mtu;
1948         }
1949         info->port_mtu_attr.show      = show_port_ib_mtu;
1950         sysfs_attr_init(&info->port_mtu_attr.attr);
1951
1952         err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1953         if (err) {
1954                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1955                 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1956                 info->port = -1;
1957         }
1958
1959         return err;
1960 }
1961
1962 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1963 {
1964         if (info->port < 0)
1965                 return;
1966
1967         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1968         device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1969 }
1970
1971 static int mlx4_init_steering(struct mlx4_dev *dev)
1972 {
1973         struct mlx4_priv *priv = mlx4_priv(dev);
1974         int num_entries = dev->caps.num_ports;
1975         int i, j;
1976
1977         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1978         if (!priv->steer)
1979                 return -ENOMEM;
1980
1981         for (i = 0; i < num_entries; i++)
1982                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1983                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1984                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1985                 }
1986         return 0;
1987 }
1988
1989 static void mlx4_clear_steering(struct mlx4_dev *dev)
1990 {
1991         struct mlx4_priv *priv = mlx4_priv(dev);
1992         struct mlx4_steer_index *entry, *tmp_entry;
1993         struct mlx4_promisc_qp *pqp, *tmp_pqp;
1994         int num_entries = dev->caps.num_ports;
1995         int i, j;
1996
1997         for (i = 0; i < num_entries; i++) {
1998                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1999                         list_for_each_entry_safe(pqp, tmp_pqp,
2000                                                  &priv->steer[i].promisc_qps[j],
2001                                                  list) {
2002                                 list_del(&pqp->list);
2003                                 kfree(pqp);
2004                         }
2005                         list_for_each_entry_safe(entry, tmp_entry,
2006                                                  &priv->steer[i].steer_entries[j],
2007                                                  list) {
2008                                 list_del(&entry->list);
2009                                 list_for_each_entry_safe(pqp, tmp_pqp,
2010                                                          &entry->duplicates,
2011                                                          list) {
2012                                         list_del(&pqp->list);
2013                                         kfree(pqp);
2014                                 }
2015                                 kfree(entry);
2016                         }
2017                 }
2018         }
2019         kfree(priv->steer);
2020 }
2021
2022 static int extended_func_num(struct pci_dev *pdev)
2023 {
2024         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2025 }
2026
2027 #define MLX4_OWNER_BASE 0x8069c
2028 #define MLX4_OWNER_SIZE 4
2029
2030 static int mlx4_get_ownership(struct mlx4_dev *dev)
2031 {
2032         void __iomem *owner;
2033         u32 ret;
2034
2035         if (pci_channel_offline(dev->pdev))
2036                 return -EIO;
2037
2038         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2039                         MLX4_OWNER_SIZE);
2040         if (!owner) {
2041                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2042                 return -ENOMEM;
2043         }
2044
2045         ret = readl(owner);
2046         iounmap(owner);
2047         return (int) !!ret;
2048 }
2049
2050 static void mlx4_free_ownership(struct mlx4_dev *dev)
2051 {
2052         void __iomem *owner;
2053
2054         if (pci_channel_offline(dev->pdev))
2055                 return;
2056
2057         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2058                         MLX4_OWNER_SIZE);
2059         if (!owner) {
2060                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2061                 return;
2062         }
2063         writel(0, owner);
2064         msleep(1000);
2065         iounmap(owner);
2066 }
2067
2068 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2069 {
2070         struct mlx4_priv *priv;
2071         struct mlx4_dev *dev;
2072         int err;
2073         int port;
2074
2075         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2076
2077         err = pci_enable_device(pdev);
2078         if (err) {
2079                 dev_err(&pdev->dev, "Cannot enable PCI device, "
2080                         "aborting.\n");
2081                 return err;
2082         }
2083         if (num_vfs > MLX4_MAX_NUM_VF) {
2084                 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
2085                        num_vfs, MLX4_MAX_NUM_VF);
2086                 return -EINVAL;
2087         }
2088         /*
2089          * Check for BARs.
2090          */
2091         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2092             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2093                 dev_err(&pdev->dev, "Missing DCS, aborting."
2094                         "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2095                         pci_dev_data, pci_resource_flags(pdev, 0));
2096                 err = -ENODEV;
2097                 goto err_disable_pdev;
2098         }
2099         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2100                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2101                 err = -ENODEV;
2102                 goto err_disable_pdev;
2103         }
2104
2105         err = pci_request_regions(pdev, DRV_NAME);
2106         if (err) {
2107                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2108                 goto err_disable_pdev;
2109         }
2110
2111         pci_set_master(pdev);
2112
2113         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2114         if (err) {
2115                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2116                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2117                 if (err) {
2118                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2119                         goto err_release_regions;
2120                 }
2121         }
2122         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2123         if (err) {
2124                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2125                          "consistent PCI DMA mask.\n");
2126                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2127                 if (err) {
2128                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2129                                 "aborting.\n");
2130                         goto err_release_regions;
2131                 }
2132         }
2133
2134         /* Allow large DMA segments, up to the firmware limit of 1 GB */
2135         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2136
2137         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2138         if (!priv) {
2139                 err = -ENOMEM;
2140                 goto err_release_regions;
2141         }
2142
2143         dev       = &priv->dev;
2144         dev->pdev = pdev;
2145         INIT_LIST_HEAD(&priv->ctx_list);
2146         spin_lock_init(&priv->ctx_lock);
2147
2148         mutex_init(&priv->port_mutex);
2149
2150         INIT_LIST_HEAD(&priv->pgdir_list);
2151         mutex_init(&priv->pgdir_mutex);
2152
2153         INIT_LIST_HEAD(&priv->bf_list);
2154         mutex_init(&priv->bf_mutex);
2155
2156         dev->rev_id = pdev->revision;
2157         /* Detect if this device is a virtual function */
2158         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2159                 /* When acting as pf, we normally skip vfs unless explicitly
2160                  * requested to probe them. */
2161                 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2162                         mlx4_warn(dev, "Skipping virtual function:%d\n",
2163                                                 extended_func_num(pdev));
2164                         err = -ENODEV;
2165                         goto err_free_dev;
2166                 }
2167                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2168                 dev->flags |= MLX4_FLAG_SLAVE;
2169         } else {
2170                 /* We reset the device and enable SRIOV only for physical
2171                  * devices.  Try to claim ownership on the device;
2172                  * if already taken, skip -- do not allow multiple PFs */
2173                 err = mlx4_get_ownership(dev);
2174                 if (err) {
2175                         if (err < 0)
2176                                 goto err_free_dev;
2177                         else {
2178                                 mlx4_warn(dev, "Multiple PFs not yet supported."
2179                                           " Skipping PF.\n");
2180                                 err = -EINVAL;
2181                                 goto err_free_dev;
2182                         }
2183                 }
2184
2185                 if (num_vfs) {
2186                         mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2187                         err = pci_enable_sriov(pdev, num_vfs);
2188                         if (err) {
2189                                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2190                                          err);
2191                                 err = 0;
2192                         } else {
2193                                 mlx4_warn(dev, "Running in master mode\n");
2194                                 dev->flags |= MLX4_FLAG_SRIOV |
2195                                               MLX4_FLAG_MASTER;
2196                                 dev->num_vfs = num_vfs;
2197                         }
2198                 }
2199
2200                 /*
2201                  * Now reset the HCA before we touch the PCI capabilities or
2202                  * attempt a firmware command, since a boot ROM may have left
2203                  * the HCA in an undefined state.
2204                  */
2205                 err = mlx4_reset(dev);
2206                 if (err) {
2207                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2208                         goto err_rel_own;
2209                 }
2210         }
2211
2212 slave_start:
2213         err = mlx4_cmd_init(dev);
2214         if (err) {
2215                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2216                 goto err_sriov;
2217         }
2218
2219         /* In slave functions, the communication channel must be initialized
2220          * before posting commands. Also, init num_slaves before calling
2221          * mlx4_init_hca */
2222         if (mlx4_is_mfunc(dev)) {
2223                 if (mlx4_is_master(dev))
2224                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2225                 else {
2226                         dev->num_slaves = 0;
2227                         err = mlx4_multi_func_init(dev);
2228                         if (err) {
2229                                 mlx4_err(dev, "Failed to init slave mfunc"
2230                                          " interface, aborting.\n");
2231                                 goto err_cmd;
2232                         }
2233                 }
2234         }
2235
2236         err = mlx4_init_hca(dev);
2237         if (err) {
2238                 if (err == -EACCES) {
2239                         /* Not primary Physical function
2240                          * Running in slave mode */
2241                         mlx4_cmd_cleanup(dev);
2242                         dev->flags |= MLX4_FLAG_SLAVE;
2243                         dev->flags &= ~MLX4_FLAG_MASTER;
2244                         goto slave_start;
2245                 } else
2246                         goto err_mfunc;
2247         }
2248
2249         /* In master functions, the communication channel must be initialized
2250          * after obtaining its address from fw */
2251         if (mlx4_is_master(dev)) {
2252                 err = mlx4_multi_func_init(dev);
2253                 if (err) {
2254                         mlx4_err(dev, "Failed to init master mfunc"
2255                                  "interface, aborting.\n");
2256                         goto err_close;
2257                 }
2258         }
2259
2260         err = mlx4_alloc_eq_table(dev);
2261         if (err)
2262                 goto err_master_mfunc;
2263
2264         priv->msix_ctl.pool_bm = 0;
2265         mutex_init(&priv->msix_ctl.pool_lock);
2266
2267         mlx4_enable_msi_x(dev);
2268         if ((mlx4_is_mfunc(dev)) &&
2269             !(dev->flags & MLX4_FLAG_MSI_X)) {
2270                 err = -ENOSYS;
2271                 mlx4_err(dev, "INTx is not supported in multi-function mode."
2272                          " aborting.\n");
2273                 goto err_free_eq;
2274         }
2275
2276         if (!mlx4_is_slave(dev)) {
2277                 err = mlx4_init_steering(dev);
2278                 if (err)
2279                         goto err_free_eq;
2280         }
2281
2282         err = mlx4_setup_hca(dev);
2283         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2284             !mlx4_is_mfunc(dev)) {
2285                 dev->flags &= ~MLX4_FLAG_MSI_X;
2286                 dev->caps.num_comp_vectors = 1;
2287                 dev->caps.comp_pool        = 0;
2288                 pci_disable_msix(pdev);
2289                 err = mlx4_setup_hca(dev);
2290         }
2291
2292         if (err)
2293                 goto err_steer;
2294
2295         for (port = 1; port <= dev->caps.num_ports; port++) {
2296                 err = mlx4_init_port_info(dev, port);
2297                 if (err)
2298                         goto err_port;
2299         }
2300
2301         err = mlx4_register_device(dev);
2302         if (err)
2303                 goto err_port;
2304
2305         mlx4_sense_init(dev);
2306         mlx4_start_sense(dev);
2307
2308         priv->pci_dev_data = pci_dev_data;
2309         pci_set_drvdata(pdev, dev);
2310
2311         return 0;
2312
2313 err_port:
2314         for (--port; port >= 1; --port)
2315                 mlx4_cleanup_port_info(&priv->port[port]);
2316
2317         mlx4_cleanup_counters_table(dev);
2318         mlx4_cleanup_mcg_table(dev);
2319         mlx4_cleanup_qp_table(dev);
2320         mlx4_cleanup_srq_table(dev);
2321         mlx4_cleanup_cq_table(dev);
2322         mlx4_cmd_use_polling(dev);
2323         mlx4_cleanup_eq_table(dev);
2324         mlx4_cleanup_mr_table(dev);
2325         mlx4_cleanup_xrcd_table(dev);
2326         mlx4_cleanup_pd_table(dev);
2327         mlx4_cleanup_uar_table(dev);
2328
2329 err_steer:
2330         if (!mlx4_is_slave(dev))
2331                 mlx4_clear_steering(dev);
2332
2333 err_free_eq:
2334         mlx4_free_eq_table(dev);
2335
2336 err_master_mfunc:
2337         if (mlx4_is_master(dev))
2338                 mlx4_multi_func_cleanup(dev);
2339
2340 err_close:
2341         if (dev->flags & MLX4_FLAG_MSI_X)
2342                 pci_disable_msix(pdev);
2343
2344         mlx4_close_hca(dev);
2345
2346 err_mfunc:
2347         if (mlx4_is_slave(dev))
2348                 mlx4_multi_func_cleanup(dev);
2349
2350 err_cmd:
2351         mlx4_cmd_cleanup(dev);
2352
2353 err_sriov:
2354         if (dev->flags & MLX4_FLAG_SRIOV)
2355                 pci_disable_sriov(pdev);
2356
2357 err_rel_own:
2358         if (!mlx4_is_slave(dev))
2359                 mlx4_free_ownership(dev);
2360
2361 err_free_dev:
2362         kfree(priv);
2363
2364 err_release_regions:
2365         pci_release_regions(pdev);
2366
2367 err_disable_pdev:
2368         pci_disable_device(pdev);
2369         pci_set_drvdata(pdev, NULL);
2370         return err;
2371 }
2372
2373 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2374 {
2375         printk_once(KERN_INFO "%s", mlx4_version);
2376
2377         return __mlx4_init_one(pdev, id->driver_data);
2378 }
2379
2380 static void mlx4_remove_one(struct pci_dev *pdev)
2381 {
2382         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2383         struct mlx4_priv *priv = mlx4_priv(dev);
2384         int p;
2385
2386         if (dev) {
2387                 /* in SRIOV it is not allowed to unload the pf's
2388                  * driver while there are alive vf's */
2389                 if (mlx4_is_master(dev)) {
2390                         if (mlx4_how_many_lives_vf(dev))
2391                                 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2392                 }
2393                 mlx4_stop_sense(dev);
2394                 mlx4_unregister_device(dev);
2395
2396                 for (p = 1; p <= dev->caps.num_ports; p++) {
2397                         mlx4_cleanup_port_info(&priv->port[p]);
2398                         mlx4_CLOSE_PORT(dev, p);
2399                 }
2400
2401                 if (mlx4_is_master(dev))
2402                         mlx4_free_resource_tracker(dev,
2403                                                    RES_TR_FREE_SLAVES_ONLY);
2404
2405                 mlx4_cleanup_counters_table(dev);
2406                 mlx4_cleanup_mcg_table(dev);
2407                 mlx4_cleanup_qp_table(dev);
2408                 mlx4_cleanup_srq_table(dev);
2409                 mlx4_cleanup_cq_table(dev);
2410                 mlx4_cmd_use_polling(dev);
2411                 mlx4_cleanup_eq_table(dev);
2412                 mlx4_cleanup_mr_table(dev);
2413                 mlx4_cleanup_xrcd_table(dev);
2414                 mlx4_cleanup_pd_table(dev);
2415
2416                 if (mlx4_is_master(dev))
2417                         mlx4_free_resource_tracker(dev,
2418                                                    RES_TR_FREE_STRUCTS_ONLY);
2419
2420                 iounmap(priv->kar);
2421                 mlx4_uar_free(dev, &priv->driver_uar);
2422                 mlx4_cleanup_uar_table(dev);
2423                 if (!mlx4_is_slave(dev))
2424                         mlx4_clear_steering(dev);
2425                 mlx4_free_eq_table(dev);
2426                 if (mlx4_is_master(dev))
2427                         mlx4_multi_func_cleanup(dev);
2428                 mlx4_close_hca(dev);
2429                 if (mlx4_is_slave(dev))
2430                         mlx4_multi_func_cleanup(dev);
2431                 mlx4_cmd_cleanup(dev);
2432
2433                 if (dev->flags & MLX4_FLAG_MSI_X)
2434                         pci_disable_msix(pdev);
2435                 if (dev->flags & MLX4_FLAG_SRIOV) {
2436                         mlx4_warn(dev, "Disabling SR-IOV\n");
2437                         pci_disable_sriov(pdev);
2438                 }
2439
2440                 if (!mlx4_is_slave(dev))
2441                         mlx4_free_ownership(dev);
2442
2443                 kfree(dev->caps.qp0_tunnel);
2444                 kfree(dev->caps.qp0_proxy);
2445                 kfree(dev->caps.qp1_tunnel);
2446                 kfree(dev->caps.qp1_proxy);
2447
2448                 kfree(priv);
2449                 pci_release_regions(pdev);
2450                 pci_disable_device(pdev);
2451                 pci_set_drvdata(pdev, NULL);
2452         }
2453 }
2454
2455 int mlx4_restart_one(struct pci_dev *pdev)
2456 {
2457         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2458         struct mlx4_priv *priv = mlx4_priv(dev);
2459         int               pci_dev_data;
2460
2461         pci_dev_data = priv->pci_dev_data;
2462         mlx4_remove_one(pdev);
2463         return __mlx4_init_one(pdev, pci_dev_data);
2464 }
2465
2466 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2467         /* MT25408 "Hermon" SDR */
2468         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2469         /* MT25408 "Hermon" DDR */
2470         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2471         /* MT25408 "Hermon" QDR */
2472         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2473         /* MT25408 "Hermon" DDR PCIe gen2 */
2474         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2475         /* MT25408 "Hermon" QDR PCIe gen2 */
2476         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2477         /* MT25408 "Hermon" EN 10GigE */
2478         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2479         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2480         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2481         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2482         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2483         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2484         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2485         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2486         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2487         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2488         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2489         /* MT26478 ConnectX2 40GigE PCIe gen2 */
2490         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2491         /* MT25400 Family [ConnectX-2 Virtual Function] */
2492         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2493         /* MT27500 Family [ConnectX-3] */
2494         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2495         /* MT27500 Family [ConnectX-3 Virtual Function] */
2496         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2497         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2498         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2499         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2500         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2501         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2502         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2503         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2504         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2505         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2506         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2507         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2508         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2509         { 0, }
2510 };
2511
2512 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2513
2514 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2515                                               pci_channel_state_t state)
2516 {
2517         mlx4_remove_one(pdev);
2518
2519         return state == pci_channel_io_perm_failure ?
2520                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2521 }
2522
2523 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2524 {
2525         int ret = __mlx4_init_one(pdev, 0);
2526
2527         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2528 }
2529
2530 static const struct pci_error_handlers mlx4_err_handler = {
2531         .error_detected = mlx4_pci_err_detected,
2532         .slot_reset     = mlx4_pci_slot_reset,
2533 };
2534
2535 static struct pci_driver mlx4_driver = {
2536         .name           = DRV_NAME,
2537         .id_table       = mlx4_pci_table,
2538         .probe          = mlx4_init_one,
2539         .remove         = mlx4_remove_one,
2540         .err_handler    = &mlx4_err_handler,
2541 };
2542
2543 static int __init mlx4_verify_params(void)
2544 {
2545         if ((log_num_mac < 0) || (log_num_mac > 7)) {
2546                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2547                 return -1;
2548         }
2549
2550         if (log_num_vlan != 0)
2551                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2552                            MLX4_LOG_NUM_VLANS);
2553
2554         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2555                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2556                 return -1;
2557         }
2558
2559         /* Check if module param for ports type has legal combination */
2560         if (port_type_array[0] == false && port_type_array[1] == true) {
2561                 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2562                 port_type_array[0] = true;
2563         }
2564
2565         if (mlx4_log_num_mgm_entry_size != -1 &&
2566             (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2567              mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2568                 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2569                            "in legal range (-1 or %d..%d)\n",
2570                            mlx4_log_num_mgm_entry_size,
2571                            MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2572                            MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2573                 return -1;
2574         }
2575
2576         return 0;
2577 }
2578
2579 static int __init mlx4_init(void)
2580 {
2581         int ret;
2582
2583         if (mlx4_verify_params())
2584                 return -EINVAL;
2585
2586         mlx4_catas_init();
2587
2588         mlx4_wq = create_singlethread_workqueue("mlx4");
2589         if (!mlx4_wq)
2590                 return -ENOMEM;
2591
2592         ret = pci_register_driver(&mlx4_driver);
2593         return ret < 0 ? ret : 0;
2594 }
2595
2596 static void __exit mlx4_cleanup(void)
2597 {
2598         pci_unregister_driver(&mlx4_driver);
2599         destroy_workqueue(mlx4_wq);
2600 }
2601
2602 module_init(mlx4_init);
2603 module_exit(mlx4_cleanup);