drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45
  46 #include <linux/mlx4/device.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "mlx4.h"
  50 #include "fw.h"
  51 #include "icm.h"
  52
  53 MODULE_AUTHOR("Roland Dreier");
  54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  55 MODULE_LICENSE("Dual BSD/GPL");
  56 MODULE_VERSION(DRV_VERSION);
  57
  58 struct workqueue_struct *mlx4_wq;
  59
  60 #ifdef CONFIG_MLX4_DEBUG
  61
  62 int mlx4_debug_level = 0;
  63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  65
  66 #endif /* CONFIG_MLX4_DEBUG */
  67
  68 #ifdef CONFIG_PCI_MSI
  69
  70 static int msi_x = 1;
  71 module_param(msi_x, int, 0444);
  72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  73
  74 #else /* CONFIG_PCI_MSI */
  75
  76 #define msi_x (0)
  77
  78 #endif /* CONFIG_PCI_MSI */
  79
  80 static uint8_t num_vfs[3] = {0, 0, 0};
  81 static int num_vfs_argc = 3;
  82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  84                           "num_vfs=port1,port2,port1+2");
  85
  86 static uint8_t probe_vf[3] = {0, 0, 0};
  87 static int probe_vfs_argc = 3;
  88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  90                            "probe_vf=port1,port2,port1+2");
  91
  92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  93 module_param_named(log_num_mgm_entry_size,
  94                         mlx4_log_num_mgm_entry_size, int, 0444);
  95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  96                                          " of qp per mcg, for example:"
  97                                          " 10 gives 248.range: 7 <="
  98                                          " log_num_mgm_entry_size <= 12."
  99                                          " To activate device managed"
 100                                          " flow steering when available, set to -1");
 101
 102 static bool enable_64b_cqe_eqe = true;
 103 module_param(enable_64b_cqe_eqe, bool, 0444);
 104 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 105                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 106
 107 #define HCA_GLOBAL_CAP_MASK            0
 108
 109 #define PF_CONTEXT_BEHAVIOUR_MASK       MLX4_FUNC_CAP_64B_EQE_CQE
 110
 111 static char mlx4_version[] =
 112         DRV_NAME ": Mellanox ConnectX core driver v"
 113         DRV_VERSION " (" DRV_RELDATE ")\n";
 114
 115 static struct mlx4_profile default_profile = {
 116         .num_qp         = 1 << 18,
 117         .num_srq        = 1 << 16,
 118         .rdmarc_per_qp  = 1 << 4,
 119         .num_cq         = 1 << 16,
 120         .num_mcg        = 1 << 13,
 121         .num_mpt        = 1 << 19,
 122         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 123 };
 124
 125 static int log_num_mac = 7;
 126 module_param_named(log_num_mac, log_num_mac, int, 0444);
 127 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 128
 129 static int log_num_vlan;
 130 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 131 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 132 /* Log2 max number of VLANs per ETH port (0-7) */
 133 #define MLX4_LOG_NUM_VLANS 7
 134
 135 static bool use_prio;
 136 module_param_named(use_prio, use_prio, bool, 0444);
 137 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 138                   "(0/1, default 0)");
 139
 140 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 141 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 142 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 143
 144 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 145 static int arr_argc = 2;
 146 module_param_array(port_type_array, int, &arr_argc, 0444);
 147 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 148                                 "1 for IB, 2 for Ethernet");
 149
 150 struct mlx4_port_config {
 151         struct list_head list;
 152         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 153         struct pci_dev *pdev;
 154 };
 155
 156 static atomic_t pf_loading = ATOMIC_INIT(0);
 157
 158 int mlx4_check_port_params(struct mlx4_dev *dev,
 159                            enum mlx4_port_type *port_type)
 160 {
 161         int i;
 162
 163         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 164                 if (port_type[i] != port_type[i + 1]) {
 165                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 166                                 mlx4_err(dev, "Only same port types supported "
 167                                          "on this HCA, aborting.\n");
 168                                 return -EINVAL;
 169                         }
 170                 }
 171         }
 172
 173         for (i = 0; i < dev->caps.num_ports; i++) {
 174                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 175                         mlx4_err(dev, "Requested port type for port %d is not "
 176                                       "supported on this HCA\n", i + 1);
 177                         return -EINVAL;
 178                 }
 179         }
 180         return 0;
 181 }
 182
 183 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 184 {
 185         int i;
 186
 187         for (i = 1; i <= dev->caps.num_ports; ++i)
 188                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 189 }
 190
 191 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 192 {
 193         int err;
 194         int i;
 195
 196         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 197         if (err) {
 198                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 199                 return err;
 200         }
 201
 202         if (dev_cap->min_page_sz > PAGE_SIZE) {
 203                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 204                          "kernel PAGE_SIZE of %ld, aborting.\n",
 205                          dev_cap->min_page_sz, PAGE_SIZE);
 206                 return -ENODEV;
 207         }
 208         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 209                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 210                          "aborting.\n",
 211                          dev_cap->num_ports, MLX4_MAX_PORTS);
 212                 return -ENODEV;
 213         }
 214
 215         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 216                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 217                          "PCI resource 2 size of 0x%llx, aborting.\n",
 218                          dev_cap->uar_size,
 219                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 220                 return -ENODEV;
 221         }
 222
 223         dev->caps.num_ports          = dev_cap->num_ports;
 224         dev->phys_caps.num_phys_eqs  = MLX4_MAX_EQ_NUM;
 225         for (i = 1; i <= dev->caps.num_ports; ++i) {
 226                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 227                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 228                 dev->phys_caps.gid_phys_table_len[i]  = dev_cap->max_gids[i];
 229                 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
 230                 /* set gid and pkey table operating lengths by default
 231                  * to non-sriov values */
 232                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 233                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 234                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 235                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 236                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 237                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 238                 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
 239                 dev->caps.default_sense[i] = dev_cap->default_sense[i];
 240                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 241                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 242                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 243                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 244         }
 245
 246         dev->caps.uar_page_size      = PAGE_SIZE;
 247         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 248         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 249         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 250         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 251         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 252         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 253         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 254         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 255         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 256         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 257         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 258         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 259         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 260         /*
 261          * Subtract 1 from the limit because we need to allocate a
 262          * spare CQE so the HCA HW can tell the difference between an
 263          * empty CQ and a full CQ.
 264          */
 265         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 266         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 267         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 268         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 269         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 270
 271         /* The first 128 UARs are used for EQ doorbells */
 272         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 273         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 274         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 275                                         dev_cap->reserved_xrcds : 0;
 276         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 277                                         dev_cap->max_xrcds : 0;
 278         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 279
 280         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 281         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 282         dev->caps.flags              = dev_cap->flags;
 283         dev->caps.flags2             = dev_cap->flags2;
 284         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 285         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 286         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 287         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 288         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 289
 290         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 291         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 292                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 293         /* Don't do sense port on multifunction devices (for now at least) */
 294         if (mlx4_is_mfunc(dev))
 295                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 296
 297         dev->caps.log_num_macs  = log_num_mac;
 298         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 299         dev->caps.log_num_prios = use_prio ? 3 : 0;
 300
 301         for (i = 1; i <= dev->caps.num_ports; ++i) {
 302                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 303                 if (dev->caps.supported_type[i]) {
 304                         /* if only ETH is supported - assign ETH */
 305                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 306                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 307                         /* if only IB is supported, assign IB */
 308                         else if (dev->caps.supported_type[i] ==
 309                                  MLX4_PORT_TYPE_IB)
 310                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 311                         else {
 312                                 /* if IB and ETH are supported, we set the port
 313                                  * type according to user selection of port type;
 314                                  * if user selected none, take the FW hint */
 315                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 316                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 317                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 318                                 else
 319                                         dev->caps.port_type[i] = port_type_array[i - 1];
 320                         }
 321                 }
 322                 /*
 323                  * Link sensing is allowed on the port if 3 conditions are true:
 324                  * 1. Both protocols are supported on the port.
 325                  * 2. Different types are supported on the port
 326                  * 3. FW declared that it supports link sensing
 327                  */
 328                 mlx4_priv(dev)->sense.sense_allowed[i] =
 329                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 330                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 331                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 332
 333                 /*
 334                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 335                  * and perform sense_port FW command to try and set the correct
 336                  * port type from beginning
 337                  */
 338                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 339                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 340                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 341                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 342                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 343                                 dev->caps.port_type[i] = sensed_port;
 344                 } else {
 345                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 346                 }
 347
 348                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 349                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 350                         mlx4_warn(dev, "Requested number of MACs is too much "
 351                                   "for port %d, reducing to %d.\n",
 352                                   i, 1 << dev->caps.log_num_macs);
 353                 }
 354                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 355                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 356                         mlx4_warn(dev, "Requested number of VLANs is too much "
 357                                   "for port %d, reducing to %d.\n",
 358                                   i, 1 << dev->caps.log_num_vlans);
 359                 }
 360         }
 361
 362         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 363
 364         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 365         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 366                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 367                 (1 << dev->caps.log_num_macs) *
 368                 (1 << dev->caps.log_num_vlans) *
 369                 (1 << dev->caps.log_num_prios) *
 370                 dev->caps.num_ports;
 371         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 372
 373         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 374                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 375                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 376                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 377
 378         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 379
 380         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 381                 if (dev_cap->flags &
 382                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 383                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 384                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 385                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 386                 }
 387         }
 388
 389         if ((dev->caps.flags &
 390             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 391             mlx4_is_master(dev))
 392                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 393
 394         return 0;
 395 }
 396
 397 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 398                                        enum pci_bus_speed *speed,
 399                                        enum pcie_link_width *width)
 400 {
 401         u32 lnkcap1, lnkcap2;
 402         int err1, err2;
 403
 404 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 405
 406         *speed = PCI_SPEED_UNKNOWN;
 407         *width = PCIE_LNK_WIDTH_UNKNOWN;
 408
 409         err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
 410         err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
 411         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 412                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 413                         *speed = PCIE_SPEED_8_0GT;
 414                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 415                         *speed = PCIE_SPEED_5_0GT;
 416                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 417                         *speed = PCIE_SPEED_2_5GT;
 418         }
 419         if (!err1) {
 420                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 421                 if (!lnkcap2) { /* pre-r3.0 */
 422                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 423                                 *speed = PCIE_SPEED_5_0GT;
 424                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 425                                 *speed = PCIE_SPEED_2_5GT;
 426                 }
 427         }
 428
 429         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 430                 return err1 ? err1 :
 431                         err2 ? err2 : -EINVAL;
 432         }
 433         return 0;
 434 }
 435
 436 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 437 {
 438         enum pcie_link_width width, width_cap;
 439         enum pci_bus_speed speed, speed_cap;
 440         int err;
 441
 442 #define PCIE_SPEED_STR(speed) \
 443         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 444          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 445          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 446          "Unknown")
 447
 448         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 449         if (err) {
 450                 mlx4_warn(dev,
 451                           "Unable to determine PCIe device BW capabilities\n");
 452                 return;
 453         }
 454
 455         err = pcie_get_minimum_link(dev->pdev, &speed, &width);
 456         if (err || speed == PCI_SPEED_UNKNOWN ||
 457             width == PCIE_LNK_WIDTH_UNKNOWN) {
 458                 mlx4_warn(dev,
 459                           "Unable to determine PCI device chain minimum BW\n");
 460                 return;
 461         }
 462
 463         if (width != width_cap || speed != speed_cap)
 464                 mlx4_warn(dev,
 465                           "PCIe BW is different than device's capability\n");
 466
 467         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 468                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 469         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 470                   width, width_cap);
 471         return;
 472 }
 473
 474 /*The function checks if there are live vf, return the num of them*/
 475 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 476 {
 477         struct mlx4_priv *priv = mlx4_priv(dev);
 478         struct mlx4_slave_state *s_state;
 479         int i;
 480         int ret = 0;
 481
 482         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 483                 s_state = &priv->mfunc.master.slave_state[i];
 484                 if (s_state->active && s_state->last_cmd !=
 485                     MLX4_COMM_CMD_RESET) {
 486                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 487                                   __func__, i);
 488                         ret++;
 489                 }
 490         }
 491         return ret;
 492 }
 493
 494 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 495 {
 496         u32 qk = MLX4_RESERVED_QKEY_BASE;
 497
 498         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 499             qpn < dev->phys_caps.base_proxy_sqpn)
 500                 return -EINVAL;
 501
 502         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 503                 /* tunnel qp */
 504                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 505         else
 506                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 507         *qkey = qk;
 508         return 0;
 509 }
 510 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 511
 512 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 513 {
 514         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 515
 516         if (!mlx4_is_master(dev))
 517                 return;
 518
 519         priv->virt2phys_pkey[slave][port - 1][i] = val;
 520 }
 521 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 522
 523 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 524 {
 525         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 526
 527         if (!mlx4_is_master(dev))
 528                 return;
 529
 530         priv->slave_node_guids[slave] = guid;
 531 }
 532 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 533
 534 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 535 {
 536         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 537
 538         if (!mlx4_is_master(dev))
 539                 return 0;
 540
 541         return priv->slave_node_guids[slave];
 542 }
 543 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 544
 545 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 546 {
 547         struct mlx4_priv *priv = mlx4_priv(dev);
 548         struct mlx4_slave_state *s_slave;
 549
 550         if (!mlx4_is_master(dev))
 551                 return 0;
 552
 553         s_slave = &priv->mfunc.master.slave_state[slave];
 554         return !!s_slave->active;
 555 }
 556 EXPORT_SYMBOL(mlx4_is_slave_active);
 557
 558 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 559                                        struct mlx4_dev_cap *dev_cap,
 560                                        struct mlx4_init_hca_param *hca_param)
 561 {
 562         dev->caps.steering_mode = hca_param->steering_mode;
 563         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 564                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 565                 dev->caps.fs_log_max_ucast_qp_range_size =
 566                         dev_cap->fs_log_max_ucast_qp_range_size;
 567         } else
 568                 dev->caps.num_qp_per_mgm =
 569                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 570
 571         mlx4_dbg(dev, "Steering mode is: %s\n",
 572                  mlx4_steering_mode_str(dev->caps.steering_mode));
 573 }
 574
 575 static int mlx4_slave_cap(struct mlx4_dev *dev)
 576 {
 577         int                        err;
 578         u32                        page_size;
 579         struct mlx4_dev_cap        dev_cap;
 580         struct mlx4_func_cap       func_cap;
 581         struct mlx4_init_hca_param hca_param;
 582         int                        i;
 583
 584         memset(&hca_param, 0, sizeof(hca_param));
 585         err = mlx4_QUERY_HCA(dev, &hca_param);
 586         if (err) {
 587                 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
 588                 return err;
 589         }
 590
 591         /*fail if the hca has an unknown capability */
 592         if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
 593             HCA_GLOBAL_CAP_MASK) {
 594                 mlx4_err(dev, "Unknown hca global capabilities\n");
 595                 return -ENOSYS;
 596         }
 597
 598         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 599
 600         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 601
 602         memset(&dev_cap, 0, sizeof(dev_cap));
 603         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 604         err = mlx4_dev_cap(dev, &dev_cap);
 605         if (err) {
 606                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 607                 return err;
 608         }
 609
 610         err = mlx4_QUERY_FW(dev);
 611         if (err)
 612                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
 613
 614         page_size = ~dev->caps.page_size_cap + 1;
 615         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 616         if (page_size > PAGE_SIZE) {
 617                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 618                          "kernel PAGE_SIZE of %ld, aborting.\n",
 619                          page_size, PAGE_SIZE);
 620                 return -ENODEV;
 621         }
 622
 623         /* slave gets uar page size from QUERY_HCA fw command */
 624         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 625
 626         /* TODO: relax this assumption */
 627         if (dev->caps.uar_page_size != PAGE_SIZE) {
 628                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
 629                          dev->caps.uar_page_size, PAGE_SIZE);
 630                 return -ENODEV;
 631         }
 632
 633         memset(&func_cap, 0, sizeof(func_cap));
 634         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 635         if (err) {
 636                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
 637                           err);
 638                 return err;
 639         }
 640
 641         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 642             PF_CONTEXT_BEHAVIOUR_MASK) {
 643                 mlx4_err(dev, "Unknown pf context behaviour\n");
 644                 return -ENOSYS;
 645         }
 646
 647         dev->caps.num_ports             = func_cap.num_ports;
 648         dev->quotas.qp                  = func_cap.qp_quota;
 649         dev->quotas.srq                 = func_cap.srq_quota;
 650         dev->quotas.cq                  = func_cap.cq_quota;
 651         dev->quotas.mpt                 = func_cap.mpt_quota;
 652         dev->quotas.mtt                 = func_cap.mtt_quota;
 653         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 654         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 655         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 656         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 657         dev->caps.num_eqs               = func_cap.max_eq;
 658         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 659         dev->caps.num_pds               = MLX4_NUM_PDS;
 660         dev->caps.num_mgms              = 0;
 661         dev->caps.num_amgms             = 0;
 662
 663         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 664                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 665                          "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
 666                 return -ENODEV;
 667         }
 668
 669         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 670         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 671         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 672         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 673
 674         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 675             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
 676                 err = -ENOMEM;
 677                 goto err_mem;
 678         }
 679
 680         for (i = 1; i <= dev->caps.num_ports; ++i) {
 681                 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
 682                 if (err) {
 683                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
 684                                  " port %d, aborting (%d).\n", i, err);
 685                         goto err_mem;
 686                 }
 687                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 688                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 689                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 690                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 691                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 692                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 693                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 694                                                     &dev->caps.gid_table_len[i],
 695                                                     &dev->caps.pkey_table_len[i]))
 696                         goto err_mem;
 697         }
 698
 699         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 700                                        dev->caps.reserved_uars) >
 701                                        pci_resource_len(dev->pdev, 2)) {
 702                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
 703                          "PCI resource 2 size of 0x%llx, aborting.\n",
 704                          dev->caps.uar_page_size * dev->caps.num_uars,
 705                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 706                 goto err_mem;
 707         }
 708
 709         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 710                 dev->caps.eqe_size   = 64;
 711                 dev->caps.eqe_factor = 1;
 712         } else {
 713                 dev->caps.eqe_size   = 32;
 714                 dev->caps.eqe_factor = 0;
 715         }
 716
 717         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 718                 dev->caps.cqe_size   = 64;
 719                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
 720         } else {
 721                 dev->caps.cqe_size   = 32;
 722         }
 723
 724         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 725         mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
 726
 727         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 728
 729         return 0;
 730
 731 err_mem:
 732         kfree(dev->caps.qp0_tunnel);
 733         kfree(dev->caps.qp0_proxy);
 734         kfree(dev->caps.qp1_tunnel);
 735         kfree(dev->caps.qp1_proxy);
 736         dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
 737                 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
 738
 739         return err;
 740 }
 741
 742 static void mlx4_request_modules(struct mlx4_dev *dev)
 743 {
 744         int port;
 745         int has_ib_port = false;
 746         int has_eth_port = false;
 747 #define EN_DRV_NAME     "mlx4_en"
 748 #define IB_DRV_NAME     "mlx4_ib"
 749
 750         for (port = 1; port <= dev->caps.num_ports; port++) {
 751                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
 752                         has_ib_port = true;
 753                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
 754                         has_eth_port = true;
 755         }
 756
 757         if (has_eth_port)
 758                 request_module_nowait(EN_DRV_NAME);
 759         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
 760                 request_module_nowait(IB_DRV_NAME);
 761 }
 762
 763 /*
 764  * Change the port configuration of the device.
 765  * Every user of this function must hold the port mutex.
 766  */
 767 int mlx4_change_port_types(struct mlx4_dev *dev,
 768                            enum mlx4_port_type *port_types)
 769 {
 770         int err = 0;
 771         int change = 0;
 772         int port;
 773
 774         for (port = 0; port <  dev->caps.num_ports; port++) {
 775                 /* Change the port type only if the new type is different
 776                  * from the current, and not set to Auto */
 777                 if (port_types[port] != dev->caps.port_type[port + 1])
 778                         change = 1;
 779         }
 780         if (change) {
 781                 mlx4_unregister_device(dev);
 782                 for (port = 1; port <= dev->caps.num_ports; port++) {
 783                         mlx4_CLOSE_PORT(dev, port);
 784                         dev->caps.port_type[port] = port_types[port - 1];
 785                         err = mlx4_SET_PORT(dev, port, -1);
 786                         if (err) {
 787                                 mlx4_err(dev, "Failed to set port %d, "
 788                                               "aborting\n", port);
 789                                 goto out;
 790                         }
 791                 }
 792                 mlx4_set_port_mask(dev);
 793                 err = mlx4_register_device(dev);
 794                 if (err) {
 795                         mlx4_err(dev, "Failed to register device\n");
 796                         goto out;
 797                 }
 798                 mlx4_request_modules(dev);
 799         }
 800
 801 out:
 802         return err;
 803 }
 804
 805 static ssize_t show_port_type(struct device *dev,
 806                               struct device_attribute *attr,
 807                               char *buf)
 808 {
 809         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 810                                                    port_attr);
 811         struct mlx4_dev *mdev = info->dev;
 812         char type[8];
 813
 814         sprintf(type, "%s",
 815                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 816                 "ib" : "eth");
 817         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 818                 sprintf(buf, "auto (%s)\n", type);
 819         else
 820                 sprintf(buf, "%s\n", type);
 821
 822         return strlen(buf);
 823 }
 824
 825 static ssize_t set_port_type(struct device *dev,
 826                              struct device_attribute *attr,
 827                              const char *buf, size_t count)
 828 {
 829         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 830                                                    port_attr);
 831         struct mlx4_dev *mdev = info->dev;
 832         struct mlx4_priv *priv = mlx4_priv(mdev);
 833         enum mlx4_port_type types[MLX4_MAX_PORTS];
 834         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 835         int i;
 836         int err = 0;
 837
 838         if (!strcmp(buf, "ib\n"))
 839                 info->tmp_type = MLX4_PORT_TYPE_IB;
 840         else if (!strcmp(buf, "eth\n"))
 841                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 842         else if (!strcmp(buf, "auto\n"))
 843                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 844         else {
 845                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 846                 return -EINVAL;
 847         }
 848
 849         mlx4_stop_sense(mdev);
 850         mutex_lock(&priv->port_mutex);
 851         /* Possible type is always the one that was delivered */
 852         mdev->caps.possible_type[info->port] = info->tmp_type;
 853
 854         for (i = 0; i < mdev->caps.num_ports; i++) {
 855                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 856                                         mdev->caps.possible_type[i+1];
 857                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 858                         types[i] = mdev->caps.port_type[i+1];
 859         }
 860
 861         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 862             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
 863                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 864                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 865                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 866                                 err = -EINVAL;
 867                         }
 868                 }
 869         }
 870         if (err) {
 871                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 872                                "Set only 'eth' or 'ib' for both ports "
 873                                "(should be the same)\n");
 874                 goto out;
 875         }
 876
 877         mlx4_do_sense_ports(mdev, new_types, types);
 878
 879         err = mlx4_check_port_params(mdev, new_types);
 880         if (err)
 881                 goto out;
 882
 883         /* We are about to apply the changes after the configuration
 884          * was verified, no need to remember the temporary types
 885          * any more */
 886         for (i = 0; i < mdev->caps.num_ports; i++)
 887                 priv->port[i + 1].tmp_type = 0;
 888
 889         err = mlx4_change_port_types(mdev, new_types);
 890
 891 out:
 892         mlx4_start_sense(mdev);
 893         mutex_unlock(&priv->port_mutex);
 894         return err ? err : count;
 895 }
 896
 897 enum ibta_mtu {
 898         IB_MTU_256  = 1,
 899         IB_MTU_512  = 2,
 900         IB_MTU_1024 = 3,
 901         IB_MTU_2048 = 4,
 902         IB_MTU_4096 = 5
 903 };
 904
 905 static inline int int_to_ibta_mtu(int mtu)
 906 {
 907         switch (mtu) {
 908         case 256:  return IB_MTU_256;
 909         case 512:  return IB_MTU_512;
 910         case 1024: return IB_MTU_1024;
 911         case 2048: return IB_MTU_2048;
 912         case 4096: return IB_MTU_4096;
 913         default: return -1;
 914         }
 915 }
 916
 917 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
 918 {
 919         switch (mtu) {
 920         case IB_MTU_256:  return  256;
 921         case IB_MTU_512:  return  512;
 922         case IB_MTU_1024: return 1024;
 923         case IB_MTU_2048: return 2048;
 924         case IB_MTU_4096: return 4096;
 925         default: return -1;
 926         }
 927 }
 928
 929 static ssize_t show_port_ib_mtu(struct device *dev,
 930                              struct device_attribute *attr,
 931                              char *buf)
 932 {
 933         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 934                                                    port_mtu_attr);
 935         struct mlx4_dev *mdev = info->dev;
 936
 937         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
 938                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 939
 940         sprintf(buf, "%d\n",
 941                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
 942         return strlen(buf);
 943 }
 944
 945 static ssize_t set_port_ib_mtu(struct device *dev,
 946                              struct device_attribute *attr,
 947                              const char *buf, size_t count)
 948 {
 949         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 950                                                    port_mtu_attr);
 951         struct mlx4_dev *mdev = info->dev;
 952         struct mlx4_priv *priv = mlx4_priv(mdev);
 953         int err, port, mtu, ibta_mtu = -1;
 954
 955         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
 956                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
 957                 return -EINVAL;
 958         }
 959
 960         err = kstrtoint(buf, 0, &mtu);
 961         if (!err)
 962                 ibta_mtu = int_to_ibta_mtu(mtu);
 963
 964         if (err || ibta_mtu < 0) {
 965                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
 966                 return -EINVAL;
 967         }
 968
 969         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
 970
 971         mlx4_stop_sense(mdev);
 972         mutex_lock(&priv->port_mutex);
 973         mlx4_unregister_device(mdev);
 974         for (port = 1; port <= mdev->caps.num_ports; port++) {
 975                 mlx4_CLOSE_PORT(mdev, port);
 976                 err = mlx4_SET_PORT(mdev, port, -1);
 977                 if (err) {
 978                         mlx4_err(mdev, "Failed to set port %d, "
 979                                       "aborting\n", port);
 980                         goto err_set_port;
 981                 }
 982         }
 983         err = mlx4_register_device(mdev);
 984 err_set_port:
 985         mutex_unlock(&priv->port_mutex);
 986         mlx4_start_sense(mdev);
 987         return err ? err : count;
 988 }
 989
 990 static int mlx4_load_fw(struct mlx4_dev *dev)
 991 {
 992         struct mlx4_priv *priv = mlx4_priv(dev);
 993         int err;
 994
 995         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 996                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 997         if (!priv->fw.fw_icm) {
 998                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 999                 return -ENOMEM;
1000         }
1001
1002         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1003         if (err) {
1004                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1005                 goto err_free;
1006         }
1007
1008         err = mlx4_RUN_FW(dev);
1009         if (err) {
1010                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1011                 goto err_unmap_fa;
1012         }
1013
1014         return 0;
1015
1016 err_unmap_fa:
1017         mlx4_UNMAP_FA(dev);
1018
1019 err_free:
1020         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1021         return err;
1022 }
1023
1024 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1025                                 int cmpt_entry_sz)
1026 {
1027         struct mlx4_priv *priv = mlx4_priv(dev);
1028         int err;
1029         int num_eqs;
1030
1031         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1032                                   cmpt_base +
1033                                   ((u64) (MLX4_CMPT_TYPE_QP *
1034                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1035                                   cmpt_entry_sz, dev->caps.num_qps,
1036                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1037                                   0, 0);
1038         if (err)
1039                 goto err;
1040
1041         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1042                                   cmpt_base +
1043                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1044                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1045                                   cmpt_entry_sz, dev->caps.num_srqs,
1046                                   dev->caps.reserved_srqs, 0, 0);
1047         if (err)
1048                 goto err_qp;
1049
1050         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1051                                   cmpt_base +
1052                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1053                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1054                                   cmpt_entry_sz, dev->caps.num_cqs,
1055                                   dev->caps.reserved_cqs, 0, 0);
1056         if (err)
1057                 goto err_srq;
1058
1059         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1060                   dev->caps.num_eqs;
1061         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1062                                   cmpt_base +
1063                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1064                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1065                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1066         if (err)
1067                 goto err_cq;
1068
1069         return 0;
1070
1071 err_cq:
1072         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1073
1074 err_srq:
1075         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1076
1077 err_qp:
1078         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1079
1080 err:
1081         return err;
1082 }
1083
1084 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1085                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1086 {
1087         struct mlx4_priv *priv = mlx4_priv(dev);
1088         u64 aux_pages;
1089         int num_eqs;
1090         int err;
1091
1092         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1093         if (err) {
1094                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1095                 return err;
1096         }
1097
1098         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1099                  (unsigned long long) icm_size >> 10,
1100                  (unsigned long long) aux_pages << 2);
1101
1102         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1103                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1104         if (!priv->fw.aux_icm) {
1105                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1106                 return -ENOMEM;
1107         }
1108
1109         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1110         if (err) {
1111                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1112                 goto err_free_aux;
1113         }
1114
1115         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1116         if (err) {
1117                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1118                 goto err_unmap_aux;
1119         }
1120
1121
1122         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1123                    dev->caps.num_eqs;
1124         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1125                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1126                                   num_eqs, num_eqs, 0, 0);
1127         if (err) {
1128                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1129                 goto err_unmap_cmpt;
1130         }
1131
1132         /*
1133          * Reserved MTT entries must be aligned up to a cacheline
1134          * boundary, since the FW will write to them, while the driver
1135          * writes to all other MTT entries. (The variable
1136          * dev->caps.mtt_entry_sz below is really the MTT segment
1137          * size, not the raw entry size)
1138          */
1139         dev->caps.reserved_mtts =
1140                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1141                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1142
1143         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1144                                   init_hca->mtt_base,
1145                                   dev->caps.mtt_entry_sz,
1146                                   dev->caps.num_mtts,
1147                                   dev->caps.reserved_mtts, 1, 0);
1148         if (err) {
1149                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1150                 goto err_unmap_eq;
1151         }
1152
1153         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1154                                   init_hca->dmpt_base,
1155                                   dev_cap->dmpt_entry_sz,
1156                                   dev->caps.num_mpts,
1157                                   dev->caps.reserved_mrws, 1, 1);
1158         if (err) {
1159                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1160                 goto err_unmap_mtt;
1161         }
1162
1163         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1164                                   init_hca->qpc_base,
1165                                   dev_cap->qpc_entry_sz,
1166                                   dev->caps.num_qps,
1167                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1168                                   0, 0);
1169         if (err) {
1170                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1171                 goto err_unmap_dmpt;
1172         }
1173
1174         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1175                                   init_hca->auxc_base,
1176                                   dev_cap->aux_entry_sz,
1177                                   dev->caps.num_qps,
1178                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1179                                   0, 0);
1180         if (err) {
1181                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1182                 goto err_unmap_qp;
1183         }
1184
1185         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1186                                   init_hca->altc_base,
1187                                   dev_cap->altc_entry_sz,
1188                                   dev->caps.num_qps,
1189                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1190                                   0, 0);
1191         if (err) {
1192                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1193                 goto err_unmap_auxc;
1194         }
1195
1196         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1197                                   init_hca->rdmarc_base,
1198                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1199                                   dev->caps.num_qps,
1200                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1201                                   0, 0);
1202         if (err) {
1203                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1204                 goto err_unmap_altc;
1205         }
1206
1207         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1208                                   init_hca->cqc_base,
1209                                   dev_cap->cqc_entry_sz,
1210                                   dev->caps.num_cqs,
1211                                   dev->caps.reserved_cqs, 0, 0);
1212         if (err) {
1213                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1214                 goto err_unmap_rdmarc;
1215         }
1216
1217         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1218                                   init_hca->srqc_base,
1219                                   dev_cap->srq_entry_sz,
1220                                   dev->caps.num_srqs,
1221                                   dev->caps.reserved_srqs, 0, 0);
1222         if (err) {
1223                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1224                 goto err_unmap_cq;
1225         }
1226
1227         /*
1228          * For flow steering device managed mode it is required to use
1229          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1230          * required, but for simplicity just map the whole multicast
1231          * group table now.  The table isn't very big and it's a lot
1232          * easier than trying to track ref counts.
1233          */
1234         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1235                                   init_hca->mc_base,
1236                                   mlx4_get_mgm_entry_size(dev),
1237                                   dev->caps.num_mgms + dev->caps.num_amgms,
1238                                   dev->caps.num_mgms + dev->caps.num_amgms,
1239                                   0, 0);
1240         if (err) {
1241                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1242                 goto err_unmap_srq;
1243         }
1244
1245         return 0;
1246
1247 err_unmap_srq:
1248         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1249
1250 err_unmap_cq:
1251         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1252
1253 err_unmap_rdmarc:
1254         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1255
1256 err_unmap_altc:
1257         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1258
1259 err_unmap_auxc:
1260         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1261
1262 err_unmap_qp:
1263         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1264
1265 err_unmap_dmpt:
1266         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1267
1268 err_unmap_mtt:
1269         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1270
1271 err_unmap_eq:
1272         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1273
1274 err_unmap_cmpt:
1275         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1276         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1277         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1278         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1279
1280 err_unmap_aux:
1281         mlx4_UNMAP_ICM_AUX(dev);
1282
1283 err_free_aux:
1284         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1285
1286         return err;
1287 }
1288
1289 static void mlx4_free_icms(struct mlx4_dev *dev)
1290 {
1291         struct mlx4_priv *priv = mlx4_priv(dev);
1292
1293         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1294         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1295         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1296         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1297         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1298         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1299         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1300         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1301         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1302         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1303         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1304         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1305         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1306         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1307
1308         mlx4_UNMAP_ICM_AUX(dev);
1309         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1310 }
1311
1312 static void mlx4_slave_exit(struct mlx4_dev *dev)
1313 {
1314         struct mlx4_priv *priv = mlx4_priv(dev);
1315
1316         mutex_lock(&priv->cmd.slave_cmd_mutex);
1317         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1318                 mlx4_warn(dev, "Failed to close slave function.\n");
1319         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1320 }
1321
1322 static int map_bf_area(struct mlx4_dev *dev)
1323 {
1324         struct mlx4_priv *priv = mlx4_priv(dev);
1325         resource_size_t bf_start;
1326         resource_size_t bf_len;
1327         int err = 0;
1328
1329         if (!dev->caps.bf_reg_size)
1330                 return -ENXIO;
1331
1332         bf_start = pci_resource_start(dev->pdev, 2) +
1333                         (dev->caps.num_uars << PAGE_SHIFT);
1334         bf_len = pci_resource_len(dev->pdev, 2) -
1335                         (dev->caps.num_uars << PAGE_SHIFT);
1336         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1337         if (!priv->bf_mapping)
1338                 err = -ENOMEM;
1339
1340         return err;
1341 }
1342
1343 static void unmap_bf_area(struct mlx4_dev *dev)
1344 {
1345         if (mlx4_priv(dev)->bf_mapping)
1346                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1347 }
1348
1349 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1350 {
1351         u32 clockhi, clocklo, clockhi1;
1352         cycle_t cycles;
1353         int i;
1354         struct mlx4_priv *priv = mlx4_priv(dev);
1355
1356         for (i = 0; i < 10; i++) {
1357                 clockhi = swab32(readl(priv->clock_mapping));
1358                 clocklo = swab32(readl(priv->clock_mapping + 4));
1359                 clockhi1 = swab32(readl(priv->clock_mapping));
1360                 if (clockhi == clockhi1)
1361                         break;
1362         }
1363
1364         cycles = (u64) clockhi << 32 | (u64) clocklo;
1365
1366         return cycles;
1367 }
1368 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1369
1370
1371 static int map_internal_clock(struct mlx4_dev *dev)
1372 {
1373         struct mlx4_priv *priv = mlx4_priv(dev);
1374
1375         priv->clock_mapping =
1376                 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1377                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1378
1379         if (!priv->clock_mapping)
1380                 return -ENOMEM;
1381
1382         return 0;
1383 }
1384
1385 static void unmap_internal_clock(struct mlx4_dev *dev)
1386 {
1387         struct mlx4_priv *priv = mlx4_priv(dev);
1388
1389         if (priv->clock_mapping)
1390                 iounmap(priv->clock_mapping);
1391 }
1392
1393 static void mlx4_close_hca(struct mlx4_dev *dev)
1394 {
1395         unmap_internal_clock(dev);
1396         unmap_bf_area(dev);
1397         if (mlx4_is_slave(dev))
1398                 mlx4_slave_exit(dev);
1399         else {
1400                 mlx4_CLOSE_HCA(dev, 0);
1401                 mlx4_free_icms(dev);
1402                 mlx4_UNMAP_FA(dev);
1403                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1404         }
1405 }
1406
1407 static int mlx4_init_slave(struct mlx4_dev *dev)
1408 {
1409         struct mlx4_priv *priv = mlx4_priv(dev);
1410         u64 dma = (u64) priv->mfunc.vhcr_dma;
1411         int ret_from_reset = 0;
1412         u32 slave_read;
1413         u32 cmd_channel_ver;
1414
1415         if (atomic_read(&pf_loading)) {
1416                 mlx4_warn(dev, "PF is not ready. Deferring probe\n");
1417                 return -EPROBE_DEFER;
1418         }
1419
1420         mutex_lock(&priv->cmd.slave_cmd_mutex);
1421         priv->cmd.max_cmds = 1;
1422         mlx4_warn(dev, "Sending reset\n");
1423         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1424                                        MLX4_COMM_TIME);
1425         /* if we are in the middle of flr the slave will try
1426          * NUM_OF_RESET_RETRIES times before leaving.*/
1427         if (ret_from_reset) {
1428                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1429                         mlx4_warn(dev, "slave is currently in the "
1430                                   "middle of FLR. Deferring probe.\n");
1431                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1432                         return -EPROBE_DEFER;
1433                 } else
1434                         goto err;
1435         }
1436
1437         /* check the driver version - the slave I/F revision
1438          * must match the master's */
1439         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1440         cmd_channel_ver = mlx4_comm_get_version();
1441
1442         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1443                 MLX4_COMM_GET_IF_REV(slave_read)) {
1444                 mlx4_err(dev, "slave driver version is not supported"
1445                          " by the master\n");
1446                 goto err;
1447         }
1448
1449         mlx4_warn(dev, "Sending vhcr0\n");
1450         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1451                                                     MLX4_COMM_TIME))
1452                 goto err;
1453         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1454                                                     MLX4_COMM_TIME))
1455                 goto err;
1456         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1457                                                     MLX4_COMM_TIME))
1458                 goto err;
1459         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1460                 goto err;
1461
1462         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1463         return 0;
1464
1465 err:
1466         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1467         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1468         return -EIO;
1469 }
1470
1471 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1472 {
1473         int i;
1474
1475         for (i = 1; i <= dev->caps.num_ports; i++) {
1476                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1477                         dev->caps.gid_table_len[i] =
1478                                 mlx4_get_slave_num_gids(dev, 0, i);
1479                 else
1480                         dev->caps.gid_table_len[i] = 1;
1481                 dev->caps.pkey_table_len[i] =
1482                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1483         }
1484 }
1485
1486 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1487 {
1488         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1489
1490         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1491               i++) {
1492                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1493                         break;
1494         }
1495
1496         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1497 }
1498
1499 static void choose_steering_mode(struct mlx4_dev *dev,
1500                                  struct mlx4_dev_cap *dev_cap)
1501 {
1502         if (mlx4_log_num_mgm_entry_size == -1 &&
1503             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1504             (!mlx4_is_mfunc(dev) ||
1505              (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
1506             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1507                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1508                 dev->oper_log_mgm_entry_size =
1509                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1510                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1511                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1512                 dev->caps.fs_log_max_ucast_qp_range_size =
1513                         dev_cap->fs_log_max_ucast_qp_range_size;
1514         } else {
1515                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1516                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1517                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1518                 else {
1519                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1520
1521                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1522                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1523                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1524                                           "set to use B0 steering. Falling back to A0 steering mode.\n");
1525                 }
1526                 dev->oper_log_mgm_entry_size =
1527                         mlx4_log_num_mgm_entry_size > 0 ?
1528                         mlx4_log_num_mgm_entry_size :
1529                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1530                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1531         }
1532         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1533                  "modparam log_num_mgm_entry_size = %d\n",
1534                  mlx4_steering_mode_str(dev->caps.steering_mode),
1535                  dev->oper_log_mgm_entry_size,
1536                  mlx4_log_num_mgm_entry_size);
1537 }
1538
1539 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1540                                        struct mlx4_dev_cap *dev_cap)
1541 {
1542         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1543             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1544                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1545         else
1546                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1547
1548         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
1549                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1550 }
1551
1552 static int mlx4_init_hca(struct mlx4_dev *dev)
1553 {
1554         struct mlx4_priv          *priv = mlx4_priv(dev);
1555         struct mlx4_adapter        adapter;
1556         struct mlx4_dev_cap        dev_cap;
1557         struct mlx4_mod_stat_cfg   mlx4_cfg;
1558         struct mlx4_profile        profile;
1559         struct mlx4_init_hca_param init_hca;
1560         u64 icm_size;
1561         int err;
1562
1563         if (!mlx4_is_slave(dev)) {
1564                 err = mlx4_QUERY_FW(dev);
1565                 if (err) {
1566                         if (err == -EACCES)
1567                                 mlx4_info(dev, "non-primary physical function, skipping.\n");
1568                         else
1569                                 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1570                         return err;
1571                 }
1572
1573                 err = mlx4_load_fw(dev);
1574                 if (err) {
1575                         mlx4_err(dev, "Failed to start FW, aborting.\n");
1576                         return err;
1577                 }
1578
1579                 mlx4_cfg.log_pg_sz_m = 1;
1580                 mlx4_cfg.log_pg_sz = 0;
1581                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1582                 if (err)
1583                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1584
1585                 err = mlx4_dev_cap(dev, &dev_cap);
1586                 if (err) {
1587                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1588                         goto err_stop_fw;
1589                 }
1590
1591                 choose_steering_mode(dev, &dev_cap);
1592                 choose_tunnel_offload_mode(dev, &dev_cap);
1593
1594                 err = mlx4_get_phys_port_id(dev);
1595                 if (err)
1596                         mlx4_err(dev, "Fail to get physical port id\n");
1597
1598                 if (mlx4_is_master(dev))
1599                         mlx4_parav_master_pf_caps(dev);
1600
1601                 profile = default_profile;
1602                 if (dev->caps.steering_mode ==
1603                     MLX4_STEERING_MODE_DEVICE_MANAGED)
1604                         profile.num_mcg = MLX4_FS_NUM_MCG;
1605
1606                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1607                                              &init_hca);
1608                 if ((long long) icm_size < 0) {
1609                         err = icm_size;
1610                         goto err_stop_fw;
1611                 }
1612
1613                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1614
1615                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1616                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1617                 init_hca.mw_enabled = 0;
1618                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1619                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1620                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1621
1622                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1623                 if (err)
1624                         goto err_stop_fw;
1625
1626                 err = mlx4_INIT_HCA(dev, &init_hca);
1627                 if (err) {
1628                         mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1629                         goto err_free_icm;
1630                 }
1631                 /*
1632                  * If TS is supported by FW
1633                  * read HCA frequency by QUERY_HCA command
1634                  */
1635                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1636                         memset(&init_hca, 0, sizeof(init_hca));
1637                         err = mlx4_QUERY_HCA(dev, &init_hca);
1638                         if (err) {
1639                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1640                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1641                         } else {
1642                                 dev->caps.hca_core_clock =
1643                                         init_hca.hca_core_clock;
1644                         }
1645
1646                         /* In case we got HCA frequency 0 - disable timestamping
1647                          * to avoid dividing by zero
1648                          */
1649                         if (!dev->caps.hca_core_clock) {
1650                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1651                                 mlx4_err(dev,
1652                                          "HCA frequency is 0. Timestamping is not supported.");
1653                         } else if (map_internal_clock(dev)) {
1654                                 /*
1655                                  * Map internal clock,
1656                                  * in case of failure disable timestamping
1657                                  */
1658                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1659                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1660                         }
1661                 }
1662         } else {
1663                 err = mlx4_init_slave(dev);
1664                 if (err) {
1665                         if (err != -EPROBE_DEFER)
1666                                 mlx4_err(dev, "Failed to initialize slave\n");
1667                         return err;
1668                 }
1669
1670                 err = mlx4_slave_cap(dev);
1671                 if (err) {
1672                         mlx4_err(dev, "Failed to obtain slave caps\n");
1673                         goto err_close;
1674                 }
1675         }
1676
1677         if (map_bf_area(dev))
1678                 mlx4_dbg(dev, "Failed to map blue flame area\n");
1679
1680         /*Only the master set the ports, all the rest got it from it.*/
1681         if (!mlx4_is_slave(dev))
1682                 mlx4_set_port_mask(dev);
1683
1684         err = mlx4_QUERY_ADAPTER(dev, &adapter);
1685         if (err) {
1686                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1687                 goto unmap_bf;
1688         }
1689
1690         priv->eq_table.inta_pin = adapter.inta_pin;
1691         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1692
1693         return 0;
1694
1695 unmap_bf:
1696         unmap_internal_clock(dev);
1697         unmap_bf_area(dev);
1698
1699         if (mlx4_is_slave(dev)) {
1700                 kfree(dev->caps.qp0_tunnel);
1701                 kfree(dev->caps.qp0_proxy);
1702                 kfree(dev->caps.qp1_tunnel);
1703                 kfree(dev->caps.qp1_proxy);
1704         }
1705
1706 err_close:
1707         if (mlx4_is_slave(dev))
1708                 mlx4_slave_exit(dev);
1709         else
1710                 mlx4_CLOSE_HCA(dev, 0);
1711
1712 err_free_icm:
1713         if (!mlx4_is_slave(dev))
1714                 mlx4_free_icms(dev);
1715
1716 err_stop_fw:
1717         if (!mlx4_is_slave(dev)) {
1718                 mlx4_UNMAP_FA(dev);
1719                 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1720         }
1721         return err;
1722 }
1723
1724 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1725 {
1726         struct mlx4_priv *priv = mlx4_priv(dev);
1727         int nent;
1728
1729         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1730                 return -ENOENT;
1731
1732         nent = dev->caps.max_counters;
1733         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1734 }
1735
1736 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1737 {
1738         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1739 }
1740
1741 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1742 {
1743         struct mlx4_priv *priv = mlx4_priv(dev);
1744
1745         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1746                 return -ENOENT;
1747
1748         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1749         if (*idx == -1)
1750                 return -ENOMEM;
1751
1752         return 0;
1753 }
1754
1755 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1756 {
1757         u64 out_param;
1758         int err;
1759
1760         if (mlx4_is_mfunc(dev)) {
1761                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1762                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1763                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1764                 if (!err)
1765                         *idx = get_param_l(&out_param);
1766
1767                 return err;
1768         }
1769         return __mlx4_counter_alloc(dev, idx);
1770 }
1771 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1772
1773 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1774 {
1775         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
1776         return;
1777 }
1778
1779 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1780 {
1781         u64 in_param = 0;
1782
1783         if (mlx4_is_mfunc(dev)) {
1784                 set_param_l(&in_param, idx);
1785                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1786                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1787                          MLX4_CMD_WRAPPED);
1788                 return;
1789         }
1790         __mlx4_counter_free(dev, idx);
1791 }
1792 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1793
1794 static int mlx4_setup_hca(struct mlx4_dev *dev)
1795 {
1796         struct mlx4_priv *priv = mlx4_priv(dev);
1797         int err;
1798         int port;
1799         __be32 ib_port_default_caps;
1800
1801         err = mlx4_init_uar_table(dev);
1802         if (err) {
1803                 mlx4_err(dev, "Failed to initialize "
1804                          "user access region table, aborting.\n");
1805                 return err;
1806         }
1807
1808         err = mlx4_uar_alloc(dev, &priv->driver_uar);
1809         if (err) {
1810                 mlx4_err(dev, "Failed to allocate driver access region, "
1811                          "aborting.\n");
1812                 goto err_uar_table_free;
1813         }
1814
1815         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1816         if (!priv->kar) {
1817                 mlx4_err(dev, "Couldn't map kernel access region, "
1818                          "aborting.\n");
1819                 err = -ENOMEM;
1820                 goto err_uar_free;
1821         }
1822
1823         err = mlx4_init_pd_table(dev);
1824         if (err) {
1825                 mlx4_err(dev, "Failed to initialize "
1826                          "protection domain table, aborting.\n");
1827                 goto err_kar_unmap;
1828         }
1829
1830         err = mlx4_init_xrcd_table(dev);
1831         if (err) {
1832                 mlx4_err(dev, "Failed to initialize "
1833                          "reliable connection domain table, aborting.\n");
1834                 goto err_pd_table_free;
1835         }
1836
1837         err = mlx4_init_mr_table(dev);
1838         if (err) {
1839                 mlx4_err(dev, "Failed to initialize "
1840                          "memory region table, aborting.\n");
1841                 goto err_xrcd_table_free;
1842         }
1843
1844         if (!mlx4_is_slave(dev)) {
1845                 err = mlx4_init_mcg_table(dev);
1846                 if (err) {
1847                         mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1848                         goto err_mr_table_free;
1849                 }
1850         }
1851
1852         err = mlx4_init_eq_table(dev);
1853         if (err) {
1854                 mlx4_err(dev, "Failed to initialize "
1855                          "event queue table, aborting.\n");
1856                 goto err_mcg_table_free;
1857         }
1858
1859         err = mlx4_cmd_use_events(dev);
1860         if (err) {
1861                 mlx4_err(dev, "Failed to switch to event-driven "
1862                          "firmware commands, aborting.\n");
1863                 goto err_eq_table_free;
1864         }
1865
1866         err = mlx4_NOP(dev);
1867         if (err) {
1868                 if (dev->flags & MLX4_FLAG_MSI_X) {
1869                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
1870                                   "interrupt IRQ %d).\n",
1871                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1872                         mlx4_warn(dev, "Trying again without MSI-X.\n");
1873                 } else {
1874                         mlx4_err(dev, "NOP command failed to generate interrupt "
1875                                  "(IRQ %d), aborting.\n",
1876                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1877                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1878                 }
1879
1880                 goto err_cmd_poll;
1881         }
1882
1883         mlx4_dbg(dev, "NOP command IRQ test passed\n");
1884
1885         err = mlx4_init_cq_table(dev);
1886         if (err) {
1887                 mlx4_err(dev, "Failed to initialize "
1888                          "completion queue table, aborting.\n");
1889                 goto err_cmd_poll;
1890         }
1891
1892         err = mlx4_init_srq_table(dev);
1893         if (err) {
1894                 mlx4_err(dev, "Failed to initialize "
1895                          "shared receive queue table, aborting.\n");
1896                 goto err_cq_table_free;
1897         }
1898
1899         err = mlx4_init_qp_table(dev);
1900         if (err) {
1901                 mlx4_err(dev, "Failed to initialize "
1902                          "queue pair table, aborting.\n");
1903                 goto err_srq_table_free;
1904         }
1905
1906         err = mlx4_init_counters_table(dev);
1907         if (err && err != -ENOENT) {
1908                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1909                 goto err_qp_table_free;
1910         }
1911
1912         if (!mlx4_is_slave(dev)) {
1913                 for (port = 1; port <= dev->caps.num_ports; port++) {
1914                         ib_port_default_caps = 0;
1915                         err = mlx4_get_port_ib_caps(dev, port,
1916                                                     &ib_port_default_caps);
1917                         if (err)
1918                                 mlx4_warn(dev, "failed to get port %d default "
1919                                           "ib capabilities (%d). Continuing "
1920                                           "with caps = 0\n", port, err);
1921                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1922
1923                         /* initialize per-slave default ib port capabilities */
1924                         if (mlx4_is_master(dev)) {
1925                                 int i;
1926                                 for (i = 0; i < dev->num_slaves; i++) {
1927                                         if (i == mlx4_master_func_num(dev))
1928                                                 continue;
1929                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1930                                                         ib_port_default_caps;
1931                                 }
1932                         }
1933
1934                         if (mlx4_is_mfunc(dev))
1935                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1936                         else
1937                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1938
1939                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1940                                             dev->caps.pkey_table_len[port] : -1);
1941                         if (err) {
1942                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1943                                         port);
1944                                 goto err_counters_table_free;
1945                         }
1946                 }
1947         }
1948
1949         return 0;
1950
1951 err_counters_table_free:
1952         mlx4_cleanup_counters_table(dev);
1953
1954 err_qp_table_free:
1955         mlx4_cleanup_qp_table(dev);
1956
1957 err_srq_table_free:
1958         mlx4_cleanup_srq_table(dev);
1959
1960 err_cq_table_free:
1961         mlx4_cleanup_cq_table(dev);
1962
1963 err_cmd_poll:
1964         mlx4_cmd_use_polling(dev);
1965
1966 err_eq_table_free:
1967         mlx4_cleanup_eq_table(dev);
1968
1969 err_mcg_table_free:
1970         if (!mlx4_is_slave(dev))
1971                 mlx4_cleanup_mcg_table(dev);
1972
1973 err_mr_table_free:
1974         mlx4_cleanup_mr_table(dev);
1975
1976 err_xrcd_table_free:
1977         mlx4_cleanup_xrcd_table(dev);
1978
1979 err_pd_table_free:
1980         mlx4_cleanup_pd_table(dev);
1981
1982 err_kar_unmap:
1983         iounmap(priv->kar);
1984
1985 err_uar_free:
1986         mlx4_uar_free(dev, &priv->driver_uar);
1987
1988 err_uar_table_free:
1989         mlx4_cleanup_uar_table(dev);
1990         return err;
1991 }
1992
1993 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1994 {
1995         struct mlx4_priv *priv = mlx4_priv(dev);
1996         struct msix_entry *entries;
1997         int nreq = min_t(int, dev->caps.num_ports *
1998                          min_t(int, num_online_cpus() + 1,
1999                                MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
2000         int i;
2001
2002         if (msi_x) {
2003                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2004                              nreq);
2005
2006                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2007                 if (!entries)
2008                         goto no_msi;
2009
2010                 for (i = 0; i < nreq; ++i)
2011                         entries[i].entry = i;
2012
2013                 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2014
2015                 if (nreq < 0) {
2016                         kfree(entries);
2017                         goto no_msi;
2018                 } else if (nreq < MSIX_LEGACY_SZ +
2019                                   dev->caps.num_ports * MIN_MSIX_P_PORT) {
2020                         /*Working in legacy mode , all EQ's shared*/
2021                         dev->caps.comp_pool           = 0;
2022                         dev->caps.num_comp_vectors = nreq - 1;
2023                 } else {
2024                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
2025                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2026                 }
2027                 for (i = 0; i < nreq; ++i)
2028                         priv->eq_table.eq[i].irq = entries[i].vector;
2029
2030                 dev->flags |= MLX4_FLAG_MSI_X;
2031
2032                 kfree(entries);
2033                 return;
2034         }
2035
2036 no_msi:
2037         dev->caps.num_comp_vectors = 1;
2038         dev->caps.comp_pool        = 0;
2039
2040         for (i = 0; i < 2; ++i)
2041                 priv->eq_table.eq[i].irq = dev->pdev->irq;
2042 }
2043
2044 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2045 {
2046         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2047         int err = 0;
2048
2049         info->dev = dev;
2050         info->port = port;
2051         if (!mlx4_is_slave(dev)) {
2052                 mlx4_init_mac_table(dev, &info->mac_table);
2053                 mlx4_init_vlan_table(dev, &info->vlan_table);
2054                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2055         }
2056
2057         sprintf(info->dev_name, "mlx4_port%d", port);
2058         info->port_attr.attr.name = info->dev_name;
2059         if (mlx4_is_mfunc(dev))
2060                 info->port_attr.attr.mode = S_IRUGO;
2061         else {
2062                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2063                 info->port_attr.store     = set_port_type;
2064         }
2065         info->port_attr.show      = show_port_type;
2066         sysfs_attr_init(&info->port_attr.attr);
2067
2068         err = device_create_file(&dev->pdev->dev, &info->port_attr);
2069         if (err) {
2070                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2071                 info->port = -1;
2072         }
2073
2074         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2075         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2076         if (mlx4_is_mfunc(dev))
2077                 info->port_mtu_attr.attr.mode = S_IRUGO;
2078         else {
2079                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2080                 info->port_mtu_attr.store     = set_port_ib_mtu;
2081         }
2082         info->port_mtu_attr.show      = show_port_ib_mtu;
2083         sysfs_attr_init(&info->port_mtu_attr.attr);
2084
2085         err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2086         if (err) {
2087                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2088                 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2089                 info->port = -1;
2090         }
2091
2092         return err;
2093 }
2094
2095 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2096 {
2097         if (info->port < 0)
2098                 return;
2099
2100         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2101         device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2102 }
2103
2104 static int mlx4_init_steering(struct mlx4_dev *dev)
2105 {
2106         struct mlx4_priv *priv = mlx4_priv(dev);
2107         int num_entries = dev->caps.num_ports;
2108         int i, j;
2109
2110         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2111         if (!priv->steer)
2112                 return -ENOMEM;
2113
2114         for (i = 0; i < num_entries; i++)
2115                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2116                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2117                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2118                 }
2119         return 0;
2120 }
2121
2122 static void mlx4_clear_steering(struct mlx4_dev *dev)
2123 {
2124         struct mlx4_priv *priv = mlx4_priv(dev);
2125         struct mlx4_steer_index *entry, *tmp_entry;
2126         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2127         int num_entries = dev->caps.num_ports;
2128         int i, j;
2129
2130         for (i = 0; i < num_entries; i++) {
2131                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2132                         list_for_each_entry_safe(pqp, tmp_pqp,
2133                                                  &priv->steer[i].promisc_qps[j],
2134                                                  list) {
2135                                 list_del(&pqp->list);
2136                                 kfree(pqp);
2137                         }
2138                         list_for_each_entry_safe(entry, tmp_entry,
2139                                                  &priv->steer[i].steer_entries[j],
2140                                                  list) {
2141                                 list_del(&entry->list);
2142                                 list_for_each_entry_safe(pqp, tmp_pqp,
2143                                                          &entry->duplicates,
2144                                                          list) {
2145                                         list_del(&pqp->list);
2146                                         kfree(pqp);
2147                                 }
2148                                 kfree(entry);
2149                         }
2150                 }
2151         }
2152         kfree(priv->steer);
2153 }
2154
2155 static int extended_func_num(struct pci_dev *pdev)
2156 {
2157         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2158 }
2159
2160 #define MLX4_OWNER_BASE 0x8069c
2161 #define MLX4_OWNER_SIZE 4
2162
2163 static int mlx4_get_ownership(struct mlx4_dev *dev)
2164 {
2165         void __iomem *owner;
2166         u32 ret;
2167
2168         if (pci_channel_offline(dev->pdev))
2169                 return -EIO;
2170
2171         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2172                         MLX4_OWNER_SIZE);
2173         if (!owner) {
2174                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2175                 return -ENOMEM;
2176         }
2177
2178         ret = readl(owner);
2179         iounmap(owner);
2180         return (int) !!ret;
2181 }
2182
2183 static void mlx4_free_ownership(struct mlx4_dev *dev)
2184 {
2185         void __iomem *owner;
2186
2187         if (pci_channel_offline(dev->pdev))
2188                 return;
2189
2190         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2191                         MLX4_OWNER_SIZE);
2192         if (!owner) {
2193                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2194                 return;
2195         }
2196         writel(0, owner);
2197         msleep(1000);
2198         iounmap(owner);
2199 }
2200
2201 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2202 {
2203         struct mlx4_priv *priv;
2204         struct mlx4_dev *dev;
2205         int err;
2206         int port;
2207         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2208         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2209         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2210                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2211         unsigned total_vfs = 0;
2212         int sriov_initialized = 0;
2213         unsigned int i;
2214
2215         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2216
2217         err = pci_enable_device(pdev);
2218         if (err) {
2219                 dev_err(&pdev->dev, "Cannot enable PCI device, "
2220                         "aborting.\n");
2221                 return err;
2222         }
2223
2224         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2225          * per port, we must limit the number of VFs to 63 (since their are
2226          * 128 MACs)
2227          */
2228         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2229              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2230                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2231                 if (nvfs[i] < 0) {
2232                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2233                         return -EINVAL;
2234                 }
2235         }
2236         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2237              i++) {
2238                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2239                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2240                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2241                         return -EINVAL;
2242                 }
2243         }
2244         if (total_vfs >= MLX4_MAX_NUM_VF) {
2245                 dev_err(&pdev->dev,
2246                         "Requested more VF's (%d) than allowed (%d)\n",
2247                         total_vfs, MLX4_MAX_NUM_VF - 1);
2248                 return -EINVAL;
2249         }
2250
2251         for (i = 0; i < MLX4_MAX_PORTS; i++) {
2252                 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2253                         dev_err(&pdev->dev,
2254                                 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2255                                 nvfs[i] + nvfs[2], i + 1,
2256                                 MLX4_MAX_NUM_VF_P_PORT - 1);
2257                         return -EINVAL;
2258                 }
2259         }
2260
2261
2262         /*
2263          * Check for BARs.
2264          */
2265         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2266             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2267                 dev_err(&pdev->dev, "Missing DCS, aborting."
2268                         "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2269                         pci_dev_data, pci_resource_flags(pdev, 0));
2270                 err = -ENODEV;
2271                 goto err_disable_pdev;
2272         }
2273         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2274                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2275                 err = -ENODEV;
2276                 goto err_disable_pdev;
2277         }
2278
2279         err = pci_request_regions(pdev, DRV_NAME);
2280         if (err) {
2281                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2282                 goto err_disable_pdev;
2283         }
2284
2285         pci_set_master(pdev);
2286
2287         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2288         if (err) {
2289                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2290                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2291                 if (err) {
2292                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2293                         goto err_release_regions;
2294                 }
2295         }
2296         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2297         if (err) {
2298                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2299                          "consistent PCI DMA mask.\n");
2300                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2301                 if (err) {
2302                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2303                                 "aborting.\n");
2304                         goto err_release_regions;
2305                 }
2306         }
2307
2308         /* Allow large DMA segments, up to the firmware limit of 1 GB */
2309         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2310
2311         dev       = pci_get_drvdata(pdev);
2312         priv      = mlx4_priv(dev);
2313         dev->pdev = pdev;
2314         INIT_LIST_HEAD(&priv->ctx_list);
2315         spin_lock_init(&priv->ctx_lock);
2316
2317         mutex_init(&priv->port_mutex);
2318
2319         INIT_LIST_HEAD(&priv->pgdir_list);
2320         mutex_init(&priv->pgdir_mutex);
2321
2322         INIT_LIST_HEAD(&priv->bf_list);
2323         mutex_init(&priv->bf_mutex);
2324
2325         dev->rev_id = pdev->revision;
2326         dev->numa_node = dev_to_node(&pdev->dev);
2327         /* Detect if this device is a virtual function */
2328         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2329                 /* When acting as pf, we normally skip vfs unless explicitly
2330                  * requested to probe them. */
2331                 if (total_vfs) {
2332                         unsigned vfs_offset = 0;
2333                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2334                              vfs_offset + nvfs[i] < extended_func_num(pdev);
2335                              vfs_offset += nvfs[i], i++)
2336                                 ;
2337                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2338                                 err = -ENODEV;
2339                                 goto err_free_dev;
2340                         }
2341                         if ((extended_func_num(pdev) - vfs_offset)
2342                             > prb_vf[i]) {
2343                                 mlx4_warn(dev, "Skipping virtual function:%d\n",
2344                                           extended_func_num(pdev));
2345                                 err = -ENODEV;
2346                                 goto err_free_dev;
2347                         }
2348                 }
2349                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2350                 dev->flags |= MLX4_FLAG_SLAVE;
2351         } else {
2352                 /* We reset the device and enable SRIOV only for physical
2353                  * devices.  Try to claim ownership on the device;
2354                  * if already taken, skip -- do not allow multiple PFs */
2355                 err = mlx4_get_ownership(dev);
2356                 if (err) {
2357                         if (err < 0)
2358                                 goto err_free_dev;
2359                         else {
2360                                 mlx4_warn(dev, "Multiple PFs not yet supported."
2361                                           " Skipping PF.\n");
2362                                 err = -EINVAL;
2363                                 goto err_free_dev;
2364                         }
2365                 }
2366
2367                 if (total_vfs) {
2368                         mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n",
2369                                   total_vfs);
2370                         dev->dev_vfs = kzalloc(
2371                                         total_vfs * sizeof(*dev->dev_vfs),
2372                                         GFP_KERNEL);
2373                         if (NULL == dev->dev_vfs) {
2374                                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2375                                 err = 0;
2376                         } else {
2377                                 atomic_inc(&pf_loading);
2378                                 err = pci_enable_sriov(pdev, total_vfs);
2379                                 if (err) {
2380                                         mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2381                                                  err);
2382                                         atomic_dec(&pf_loading);
2383                                         err = 0;
2384                                 } else {
2385                                         mlx4_warn(dev, "Running in master mode\n");
2386                                         dev->flags |= MLX4_FLAG_SRIOV |
2387                                                       MLX4_FLAG_MASTER;
2388                                         dev->num_vfs = total_vfs;
2389                                         sriov_initialized = 1;
2390                                 }
2391                         }
2392                 }
2393
2394                 atomic_set(&priv->opreq_count, 0);
2395                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2396
2397                 /*
2398                  * Now reset the HCA before we touch the PCI capabilities or
2399                  * attempt a firmware command, since a boot ROM may have left
2400                  * the HCA in an undefined state.
2401                  */
2402                 err = mlx4_reset(dev);
2403                 if (err) {
2404                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2405                         goto err_rel_own;
2406                 }
2407         }
2408
2409 slave_start:
2410         err = mlx4_cmd_init(dev);
2411         if (err) {
2412                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2413                 goto err_sriov;
2414         }
2415
2416         /* In slave functions, the communication channel must be initialized
2417          * before posting commands. Also, init num_slaves before calling
2418          * mlx4_init_hca */
2419         if (mlx4_is_mfunc(dev)) {
2420                 if (mlx4_is_master(dev))
2421                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2422                 else {
2423                         dev->num_slaves = 0;
2424                         err = mlx4_multi_func_init(dev);
2425                         if (err) {
2426                                 mlx4_err(dev, "Failed to init slave mfunc"
2427                                          " interface, aborting.\n");
2428                                 goto err_cmd;
2429                         }
2430                 }
2431         }
2432
2433         err = mlx4_init_hca(dev);
2434         if (err) {
2435                 if (err == -EACCES) {
2436                         /* Not primary Physical function
2437                          * Running in slave mode */
2438                         mlx4_cmd_cleanup(dev);
2439                         dev->flags |= MLX4_FLAG_SLAVE;
2440                         dev->flags &= ~MLX4_FLAG_MASTER;
2441                         goto slave_start;
2442                 } else
2443                         goto err_mfunc;
2444         }
2445
2446         /* check if the device is functioning at its maximum possible speed.
2447          * No return code for this call, just warn the user in case of PCI
2448          * express device capabilities are under-satisfied by the bus.
2449          */
2450         if (!mlx4_is_slave(dev))
2451                 mlx4_check_pcie_caps(dev);
2452
2453         /* In master functions, the communication channel must be initialized
2454          * after obtaining its address from fw */
2455         if (mlx4_is_master(dev)) {
2456                 unsigned sum = 0;
2457                 err = mlx4_multi_func_init(dev);
2458                 if (err) {
2459                         mlx4_err(dev, "Failed to init master mfunc"
2460                                  "interface, aborting.\n");
2461                         goto err_close;
2462                 }
2463                 if (sriov_initialized) {
2464                         int ib_ports = 0;
2465                         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2466                                 ib_ports++;
2467
2468                         if (ib_ports &&
2469                             (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2470                                 mlx4_err(dev,
2471                                          "Invalid syntax of num_vfs/probe_vfs "
2472                                          "with IB port. Single port VFs syntax"
2473                                          " is only supported when all ports "
2474                                          "are configured as ethernet\n");
2475                                 goto err_close;
2476                         }
2477                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) {
2478                                 unsigned j;
2479                                 for (j = 0; j < nvfs[i]; ++sum, ++j) {
2480                                         dev->dev_vfs[sum].min_port =
2481                                                 i < 2 ? i + 1 : 1;
2482                                         dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2483                                                 dev->caps.num_ports;
2484                                 }
2485                         }
2486                 }
2487         }
2488
2489         err = mlx4_alloc_eq_table(dev);
2490         if (err)
2491                 goto err_master_mfunc;
2492
2493         priv->msix_ctl.pool_bm = 0;
2494         mutex_init(&priv->msix_ctl.pool_lock);
2495
2496         mlx4_enable_msi_x(dev);
2497         if ((mlx4_is_mfunc(dev)) &&
2498             !(dev->flags & MLX4_FLAG_MSI_X)) {
2499                 err = -ENOSYS;
2500                 mlx4_err(dev, "INTx is not supported in multi-function mode."
2501                          " aborting.\n");
2502                 goto err_free_eq;
2503         }
2504
2505         if (!mlx4_is_slave(dev)) {
2506                 err = mlx4_init_steering(dev);
2507                 if (err)
2508                         goto err_free_eq;
2509         }
2510
2511         err = mlx4_setup_hca(dev);
2512         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2513             !mlx4_is_mfunc(dev)) {
2514                 dev->flags &= ~MLX4_FLAG_MSI_X;
2515                 dev->caps.num_comp_vectors = 1;
2516                 dev->caps.comp_pool        = 0;
2517                 pci_disable_msix(pdev);
2518                 err = mlx4_setup_hca(dev);
2519         }
2520
2521         if (err)
2522                 goto err_steer;
2523
2524         mlx4_init_quotas(dev);
2525
2526         for (port = 1; port <= dev->caps.num_ports; port++) {
2527                 err = mlx4_init_port_info(dev, port);
2528                 if (err)
2529                         goto err_port;
2530         }
2531
2532         err = mlx4_register_device(dev);
2533         if (err)
2534                 goto err_port;
2535
2536         mlx4_request_modules(dev);
2537
2538         mlx4_sense_init(dev);
2539         mlx4_start_sense(dev);
2540
2541         priv->removed = 0;
2542
2543         if (mlx4_is_master(dev) && dev->num_vfs)
2544                 atomic_dec(&pf_loading);
2545
2546         return 0;
2547
2548 err_port:
2549         for (--port; port >= 1; --port)
2550                 mlx4_cleanup_port_info(&priv->port[port]);
2551
2552         mlx4_cleanup_counters_table(dev);
2553         mlx4_cleanup_qp_table(dev);
2554         mlx4_cleanup_srq_table(dev);
2555         mlx4_cleanup_cq_table(dev);
2556         mlx4_cmd_use_polling(dev);
2557         mlx4_cleanup_eq_table(dev);
2558         mlx4_cleanup_mcg_table(dev);
2559         mlx4_cleanup_mr_table(dev);
2560         mlx4_cleanup_xrcd_table(dev);
2561         mlx4_cleanup_pd_table(dev);
2562         mlx4_cleanup_uar_table(dev);
2563
2564 err_steer:
2565         if (!mlx4_is_slave(dev))
2566                 mlx4_clear_steering(dev);
2567
2568 err_free_eq:
2569         mlx4_free_eq_table(dev);
2570
2571 err_master_mfunc:
2572         if (mlx4_is_master(dev))
2573                 mlx4_multi_func_cleanup(dev);
2574
2575         if (mlx4_is_slave(dev)) {
2576                 kfree(dev->caps.qp0_tunnel);
2577                 kfree(dev->caps.qp0_proxy);
2578                 kfree(dev->caps.qp1_tunnel);
2579                 kfree(dev->caps.qp1_proxy);
2580         }
2581
2582 err_close:
2583         if (dev->flags & MLX4_FLAG_MSI_X)
2584                 pci_disable_msix(pdev);
2585
2586         mlx4_close_hca(dev);
2587
2588 err_mfunc:
2589         if (mlx4_is_slave(dev))
2590                 mlx4_multi_func_cleanup(dev);
2591
2592 err_cmd:
2593         mlx4_cmd_cleanup(dev);
2594
2595 err_sriov:
2596         if (dev->flags & MLX4_FLAG_SRIOV)
2597                 pci_disable_sriov(pdev);
2598
2599 err_rel_own:
2600         if (!mlx4_is_slave(dev))
2601                 mlx4_free_ownership(dev);
2602
2603         if (mlx4_is_master(dev) && dev->num_vfs)
2604                 atomic_dec(&pf_loading);
2605
2606         kfree(priv->dev.dev_vfs);
2607
2608 err_free_dev:
2609         kfree(priv);
2610
2611 err_release_regions:
2612         pci_release_regions(pdev);
2613
2614 err_disable_pdev:
2615         pci_disable_device(pdev);
2616         pci_set_drvdata(pdev, NULL);
2617         return err;
2618 }
2619
2620 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2621 {
2622         struct mlx4_priv *priv;
2623         struct mlx4_dev *dev;
2624
2625         printk_once(KERN_INFO "%s", mlx4_version);
2626
2627         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2628         if (!priv)
2629                 return -ENOMEM;
2630
2631         dev       = &priv->dev;
2632         pci_set_drvdata(pdev, dev);
2633         priv->pci_dev_data = id->driver_data;
2634
2635         return __mlx4_init_one(pdev, id->driver_data);
2636 }
2637
2638 static void __mlx4_remove_one(struct pci_dev *pdev)
2639 {
2640         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2641         struct mlx4_priv *priv = mlx4_priv(dev);
2642         int               pci_dev_data;
2643         int p;
2644
2645         if (priv->removed)
2646                 return;
2647
2648         pci_dev_data = priv->pci_dev_data;
2649
2650         /* in SRIOV it is not allowed to unload the pf's
2651          * driver while there are alive vf's */
2652         if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev))
2653                 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2654         mlx4_stop_sense(dev);
2655         mlx4_unregister_device(dev);
2656
2657         for (p = 1; p <= dev->caps.num_ports; p++) {
2658                 mlx4_cleanup_port_info(&priv->port[p]);
2659                 mlx4_CLOSE_PORT(dev, p);
2660         }
2661
2662         if (mlx4_is_master(dev))
2663                 mlx4_free_resource_tracker(dev,
2664                                            RES_TR_FREE_SLAVES_ONLY);
2665
2666         mlx4_cleanup_counters_table(dev);
2667         mlx4_cleanup_qp_table(dev);
2668         mlx4_cleanup_srq_table(dev);
2669         mlx4_cleanup_cq_table(dev);
2670         mlx4_cmd_use_polling(dev);
2671         mlx4_cleanup_eq_table(dev);
2672         mlx4_cleanup_mcg_table(dev);
2673         mlx4_cleanup_mr_table(dev);
2674         mlx4_cleanup_xrcd_table(dev);
2675         mlx4_cleanup_pd_table(dev);
2676
2677         if (mlx4_is_master(dev))
2678                 mlx4_free_resource_tracker(dev,
2679                                            RES_TR_FREE_STRUCTS_ONLY);
2680
2681         iounmap(priv->kar);
2682         mlx4_uar_free(dev, &priv->driver_uar);
2683         mlx4_cleanup_uar_table(dev);
2684         if (!mlx4_is_slave(dev))
2685                 mlx4_clear_steering(dev);
2686         mlx4_free_eq_table(dev);
2687         if (mlx4_is_master(dev))
2688                 mlx4_multi_func_cleanup(dev);
2689         mlx4_close_hca(dev);
2690         if (mlx4_is_slave(dev))
2691                 mlx4_multi_func_cleanup(dev);
2692         mlx4_cmd_cleanup(dev);
2693
2694         if (dev->flags & MLX4_FLAG_MSI_X)
2695                 pci_disable_msix(pdev);
2696         if (dev->flags & MLX4_FLAG_SRIOV) {
2697                 mlx4_warn(dev, "Disabling SR-IOV\n");
2698                 pci_disable_sriov(pdev);
2699                 dev->num_vfs = 0;
2700         }
2701
2702         if (!mlx4_is_slave(dev))
2703                 mlx4_free_ownership(dev);
2704
2705         kfree(dev->caps.qp0_tunnel);
2706         kfree(dev->caps.qp0_proxy);
2707         kfree(dev->caps.qp1_tunnel);
2708         kfree(dev->caps.qp1_proxy);
2709         kfree(dev->dev_vfs);
2710
2711         pci_release_regions(pdev);
2712         pci_disable_device(pdev);
2713         memset(priv, 0, sizeof(*priv));
2714         priv->pci_dev_data = pci_dev_data;
2715         priv->removed = 1;
2716 }
2717
2718 static void mlx4_remove_one(struct pci_dev *pdev)
2719 {
2720         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2721         struct mlx4_priv *priv = mlx4_priv(dev);
2722
2723         __mlx4_remove_one(pdev);
2724         kfree(priv);
2725         pci_set_drvdata(pdev, NULL);
2726 }
2727
2728 int mlx4_restart_one(struct pci_dev *pdev)
2729 {
2730         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2731         struct mlx4_priv *priv = mlx4_priv(dev);
2732         int               pci_dev_data;
2733
2734         pci_dev_data = priv->pci_dev_data;
2735         __mlx4_remove_one(pdev);
2736         return __mlx4_init_one(pdev, pci_dev_data);
2737 }
2738
2739 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2740         /* MT25408 "Hermon" SDR */
2741         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2742         /* MT25408 "Hermon" DDR */
2743         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2744         /* MT25408 "Hermon" QDR */
2745         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2746         /* MT25408 "Hermon" DDR PCIe gen2 */
2747         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2748         /* MT25408 "Hermon" QDR PCIe gen2 */
2749         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2750         /* MT25408 "Hermon" EN 10GigE */
2751         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2752         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2753         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2754         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2755         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2756         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2757         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2758         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2759         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2760         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2761         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2762         /* MT26478 ConnectX2 40GigE PCIe gen2 */
2763         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2764         /* MT25400 Family [ConnectX-2 Virtual Function] */
2765         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2766         /* MT27500 Family [ConnectX-3] */
2767         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2768         /* MT27500 Family [ConnectX-3 Virtual Function] */
2769         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2770         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2771         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2772         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2773         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2774         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2775         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2776         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2777         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2778         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2779         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2780         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2781         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2782         { 0, }
2783 };
2784
2785 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2786
2787 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2788                                               pci_channel_state_t state)
2789 {
2790         __mlx4_remove_one(pdev);
2791
2792         return state == pci_channel_io_perm_failure ?
2793                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2794 }
2795
2796 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2797 {
2798         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
2799         struct mlx4_priv *priv = mlx4_priv(dev);
2800         int               ret;
2801
2802         ret = __mlx4_init_one(pdev, priv->pci_dev_data);
2803
2804         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2805 }
2806
2807 static const struct pci_error_handlers mlx4_err_handler = {
2808         .error_detected = mlx4_pci_err_detected,
2809         .slot_reset     = mlx4_pci_slot_reset,
2810 };
2811
2812 static struct pci_driver mlx4_driver = {
2813         .name           = DRV_NAME,
2814         .id_table       = mlx4_pci_table,
2815         .probe          = mlx4_init_one,
2816         .shutdown       = mlx4_remove_one,
2817         .remove         = mlx4_remove_one,
2818         .err_handler    = &mlx4_err_handler,
2819 };
2820
2821 static int __init mlx4_verify_params(void)
2822 {
2823         if ((log_num_mac < 0) || (log_num_mac > 7)) {
2824                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2825                 return -1;
2826         }
2827
2828         if (log_num_vlan != 0)
2829                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2830                            MLX4_LOG_NUM_VLANS);
2831
2832         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2833                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2834                 return -1;
2835         }
2836
2837         /* Check if module param for ports type has legal combination */
2838         if (port_type_array[0] == false && port_type_array[1] == true) {
2839                 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2840                 port_type_array[0] = true;
2841         }
2842
2843         if (mlx4_log_num_mgm_entry_size != -1 &&
2844             (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2845              mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2846                 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2847                            "in legal range (-1 or %d..%d)\n",
2848                            mlx4_log_num_mgm_entry_size,
2849                            MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2850                            MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2851                 return -1;
2852         }
2853
2854         return 0;
2855 }
2856
2857 static int __init mlx4_init(void)
2858 {
2859         int ret;
2860
2861         if (mlx4_verify_params())
2862                 return -EINVAL;
2863
2864         mlx4_catas_init();
2865
2866         mlx4_wq = create_singlethread_workqueue("mlx4");
2867         if (!mlx4_wq)
2868                 return -ENOMEM;
2869
2870         ret = pci_register_driver(&mlx4_driver);
2871         if (ret < 0)
2872                 destroy_workqueue(mlx4_wq);
2873         return ret < 0 ? ret : 0;
2874 }
2875
2876 static void __exit mlx4_cleanup(void)
2877 {
2878         pci_unregister_driver(&mlx4_driver);
2879         destroy_workqueue(mlx4_wq);
2880 }
2881
2882 module_init(mlx4_init);
2883 module_exit(mlx4_cleanup);