2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
81 module_param(num_vfs, int, 0444);
82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
85 module_param(probe_vf, int, 0644);
86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
88 int mlx4_log_num_mgm_entry_size = 10;
89 module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 9<="
94 " log_num_mgm_entry_size <= 12."
95 " Not in use with device managed"
98 #define MLX4_VF (1 << 0)
100 #define HCA_GLOBAL_CAP_MASK 0
101 #define PF_CONTEXT_BEHAVIOUR_MASK 0
103 static char mlx4_version[] __devinitdata =
104 DRV_NAME ": Mellanox ConnectX core driver v"
105 DRV_VERSION " (" DRV_RELDATE ")\n";
107 static struct mlx4_profile default_profile = {
110 .rdmarc_per_qp = 1 << 4,
114 .num_mtt = 1 << 20, /* It is really num mtt segements */
117 static int log_num_mac = 7;
118 module_param_named(log_num_mac, log_num_mac, int, 0444);
119 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
121 static int log_num_vlan;
122 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
123 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
124 /* Log2 max number of VLANs per ETH port (0-7) */
125 #define MLX4_LOG_NUM_VLANS 7
127 static bool use_prio;
128 module_param_named(use_prio, use_prio, bool, 0444);
129 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
132 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
133 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
134 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
136 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
137 static int arr_argc = 2;
138 module_param_array(port_type_array, int, &arr_argc, 0444);
139 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
140 "1 for IB, 2 for Ethernet");
142 struct mlx4_port_config {
143 struct list_head list;
144 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
145 struct pci_dev *pdev;
148 int mlx4_check_port_params(struct mlx4_dev *dev,
149 enum mlx4_port_type *port_type)
153 for (i = 0; i < dev->caps.num_ports - 1; i++) {
154 if (port_type[i] != port_type[i + 1]) {
155 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
156 mlx4_err(dev, "Only same port types supported "
157 "on this HCA, aborting.\n");
163 for (i = 0; i < dev->caps.num_ports; i++) {
164 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
165 mlx4_err(dev, "Requested port type for port %d is not "
166 "supported on this HCA\n", i + 1);
173 static void mlx4_set_port_mask(struct mlx4_dev *dev)
177 for (i = 1; i <= dev->caps.num_ports; ++i)
178 dev->caps.port_mask[i] = dev->caps.port_type[i];
181 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
186 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
188 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
192 if (dev_cap->min_page_sz > PAGE_SIZE) {
193 mlx4_err(dev, "HCA minimum page size of %d bigger than "
194 "kernel PAGE_SIZE of %ld, aborting.\n",
195 dev_cap->min_page_sz, PAGE_SIZE);
198 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
199 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
201 dev_cap->num_ports, MLX4_MAX_PORTS);
205 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
206 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
207 "PCI resource 2 size of 0x%llx, aborting.\n",
209 (unsigned long long) pci_resource_len(dev->pdev, 2));
213 dev->caps.num_ports = dev_cap->num_ports;
214 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
215 for (i = 1; i <= dev->caps.num_ports; ++i) {
216 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
217 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
218 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
219 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
220 /* set gid and pkey table operating lengths by default
221 * to non-sriov values */
222 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
223 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
224 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
225 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
226 dev->caps.def_mac[i] = dev_cap->def_mac[i];
227 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
228 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
229 dev->caps.default_sense[i] = dev_cap->default_sense[i];
230 dev->caps.trans_type[i] = dev_cap->trans_type[i];
231 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
232 dev->caps.wavelength[i] = dev_cap->wavelength[i];
233 dev->caps.trans_code[i] = dev_cap->trans_code[i];
236 dev->caps.uar_page_size = PAGE_SIZE;
237 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
238 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
239 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
240 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
241 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
242 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
243 dev->caps.max_wqes = dev_cap->max_qp_sz;
244 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
245 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
246 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
247 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
248 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
249 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
251 * Subtract 1 from the limit because we need to allocate a
252 * spare CQE so the HCA HW can tell the difference between an
253 * empty CQ and a full CQ.
255 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
256 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
257 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
258 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
259 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
261 /* The first 128 UARs are used for EQ doorbells */
262 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
263 dev->caps.reserved_pds = dev_cap->reserved_pds;
264 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
265 dev_cap->reserved_xrcds : 0;
266 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
267 dev_cap->max_xrcds : 0;
268 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
270 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
271 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
272 dev->caps.flags = dev_cap->flags;
273 dev->caps.flags2 = dev_cap->flags2;
274 dev->caps.bmme_flags = dev_cap->bmme_flags;
275 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
276 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
277 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
278 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
280 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
281 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
282 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
283 dev->caps.fs_log_max_ucast_qp_range_size =
284 dev_cap->fs_log_max_ucast_qp_range_size;
286 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
287 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) {
288 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
290 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
292 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
293 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
294 mlx4_warn(dev, "Must have UC_STEER and MC_STEER flags "
295 "set to use B0 steering. Falling back to A0 steering mode.\n");
297 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
299 mlx4_dbg(dev, "Steering mode is: %s\n",
300 mlx4_steering_mode_str(dev->caps.steering_mode));
302 /* Sense port always allowed on supported devices for ConnectX1 and 2 */
303 if (dev->pdev->device != 0x1003)
304 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
306 dev->caps.log_num_macs = log_num_mac;
307 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
308 dev->caps.log_num_prios = use_prio ? 3 : 0;
310 for (i = 1; i <= dev->caps.num_ports; ++i) {
311 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
312 if (dev->caps.supported_type[i]) {
313 /* if only ETH is supported - assign ETH */
314 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
315 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
316 /* if only IB is supported, assign IB */
317 else if (dev->caps.supported_type[i] ==
319 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
321 /* if IB and ETH are supported, we set the port
322 * type according to user selection of port type;
323 * if user selected none, take the FW hint */
324 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
325 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
326 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
328 dev->caps.port_type[i] = port_type_array[i - 1];
332 * Link sensing is allowed on the port if 3 conditions are true:
333 * 1. Both protocols are supported on the port.
334 * 2. Different types are supported on the port
335 * 3. FW declared that it supports link sensing
337 mlx4_priv(dev)->sense.sense_allowed[i] =
338 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
339 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
340 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
343 * If "default_sense" bit is set, we move the port to "AUTO" mode
344 * and perform sense_port FW command to try and set the correct
345 * port type from beginning
347 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
348 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
349 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
350 mlx4_SENSE_PORT(dev, i, &sensed_port);
351 if (sensed_port != MLX4_PORT_TYPE_NONE)
352 dev->caps.port_type[i] = sensed_port;
354 dev->caps.possible_type[i] = dev->caps.port_type[i];
357 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
358 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
359 mlx4_warn(dev, "Requested number of MACs is too much "
360 "for port %d, reducing to %d.\n",
361 i, 1 << dev->caps.log_num_macs);
363 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
364 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
365 mlx4_warn(dev, "Requested number of VLANs is too much "
366 "for port %d, reducing to %d.\n",
367 i, 1 << dev->caps.log_num_vlans);
371 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
373 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
374 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
376 (1 << dev->caps.log_num_macs) *
377 (1 << dev->caps.log_num_vlans) *
378 (1 << dev->caps.log_num_prios) *
380 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
382 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
383 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
384 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
385 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
387 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
390 /*The function checks if there are live vf, return the num of them*/
391 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
393 struct mlx4_priv *priv = mlx4_priv(dev);
394 struct mlx4_slave_state *s_state;
398 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
399 s_state = &priv->mfunc.master.slave_state[i];
400 if (s_state->active && s_state->last_cmd !=
401 MLX4_COMM_CMD_RESET) {
402 mlx4_warn(dev, "%s: slave: %d is still active\n",
410 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
412 u32 qk = MLX4_RESERVED_QKEY_BASE;
414 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
415 qpn < dev->phys_caps.base_proxy_sqpn)
418 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
420 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
422 qk += qpn - dev->phys_caps.base_proxy_sqpn;
426 EXPORT_SYMBOL(mlx4_get_parav_qkey);
428 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
430 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
432 if (!mlx4_is_master(dev))
435 priv->virt2phys_pkey[slave][port - 1][i] = val;
437 EXPORT_SYMBOL(mlx4_sync_pkey_table);
439 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
441 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
443 if (!mlx4_is_master(dev))
446 priv->slave_node_guids[slave] = guid;
448 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
450 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
452 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
454 if (!mlx4_is_master(dev))
457 return priv->slave_node_guids[slave];
459 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
461 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
463 struct mlx4_priv *priv = mlx4_priv(dev);
464 struct mlx4_slave_state *s_slave;
466 if (!mlx4_is_master(dev))
469 s_slave = &priv->mfunc.master.slave_state[slave];
470 return !!s_slave->active;
472 EXPORT_SYMBOL(mlx4_is_slave_active);
474 static int mlx4_slave_cap(struct mlx4_dev *dev)
478 struct mlx4_dev_cap dev_cap;
479 struct mlx4_func_cap func_cap;
480 struct mlx4_init_hca_param hca_param;
483 memset(&hca_param, 0, sizeof(hca_param));
484 err = mlx4_QUERY_HCA(dev, &hca_param);
486 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
490 /*fail if the hca has an unknown capability */
491 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
492 HCA_GLOBAL_CAP_MASK) {
493 mlx4_err(dev, "Unknown hca global capabilities\n");
497 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
499 memset(&dev_cap, 0, sizeof(dev_cap));
500 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
501 err = mlx4_dev_cap(dev, &dev_cap);
503 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
507 err = mlx4_QUERY_FW(dev);
509 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
511 page_size = ~dev->caps.page_size_cap + 1;
512 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
513 if (page_size > PAGE_SIZE) {
514 mlx4_err(dev, "HCA minimum page size of %d bigger than "
515 "kernel PAGE_SIZE of %ld, aborting.\n",
516 page_size, PAGE_SIZE);
520 /* slave gets uar page size from QUERY_HCA fw command */
521 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
523 /* TODO: relax this assumption */
524 if (dev->caps.uar_page_size != PAGE_SIZE) {
525 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
526 dev->caps.uar_page_size, PAGE_SIZE);
530 memset(&func_cap, 0, sizeof(func_cap));
531 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
533 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
538 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
539 PF_CONTEXT_BEHAVIOUR_MASK) {
540 mlx4_err(dev, "Unknown pf context behaviour\n");
544 dev->caps.num_ports = func_cap.num_ports;
545 dev->caps.num_qps = func_cap.qp_quota;
546 dev->caps.num_srqs = func_cap.srq_quota;
547 dev->caps.num_cqs = func_cap.cq_quota;
548 dev->caps.num_eqs = func_cap.max_eq;
549 dev->caps.reserved_eqs = func_cap.reserved_eq;
550 dev->caps.num_mpts = func_cap.mpt_quota;
551 dev->caps.num_mtts = func_cap.mtt_quota;
552 dev->caps.num_pds = MLX4_NUM_PDS;
553 dev->caps.num_mgms = 0;
554 dev->caps.num_amgms = 0;
556 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
557 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
558 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
562 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
563 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
564 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
565 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
567 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
568 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
573 for (i = 1; i <= dev->caps.num_ports; ++i) {
574 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
576 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
577 " port %d, aborting (%d).\n", i, err);
580 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
581 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
582 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
583 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
584 dev->caps.port_mask[i] = dev->caps.port_type[i];
585 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
586 &dev->caps.gid_table_len[i],
587 &dev->caps.pkey_table_len[i]))
591 if (dev->caps.uar_page_size * (dev->caps.num_uars -
592 dev->caps.reserved_uars) >
593 pci_resource_len(dev->pdev, 2)) {
594 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
595 "PCI resource 2 size of 0x%llx, aborting.\n",
596 dev->caps.uar_page_size * dev->caps.num_uars,
597 (unsigned long long) pci_resource_len(dev->pdev, 2));
604 kfree(dev->caps.qp0_tunnel);
605 kfree(dev->caps.qp0_proxy);
606 kfree(dev->caps.qp1_tunnel);
607 kfree(dev->caps.qp1_proxy);
608 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
609 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
615 * Change the port configuration of the device.
616 * Every user of this function must hold the port mutex.
618 int mlx4_change_port_types(struct mlx4_dev *dev,
619 enum mlx4_port_type *port_types)
625 for (port = 0; port < dev->caps.num_ports; port++) {
626 /* Change the port type only if the new type is different
627 * from the current, and not set to Auto */
628 if (port_types[port] != dev->caps.port_type[port + 1])
632 mlx4_unregister_device(dev);
633 for (port = 1; port <= dev->caps.num_ports; port++) {
634 mlx4_CLOSE_PORT(dev, port);
635 dev->caps.port_type[port] = port_types[port - 1];
636 err = mlx4_SET_PORT(dev, port, -1);
638 mlx4_err(dev, "Failed to set port %d, "
643 mlx4_set_port_mask(dev);
644 err = mlx4_register_device(dev);
651 static ssize_t show_port_type(struct device *dev,
652 struct device_attribute *attr,
655 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
657 struct mlx4_dev *mdev = info->dev;
661 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
663 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
664 sprintf(buf, "auto (%s)\n", type);
666 sprintf(buf, "%s\n", type);
671 static ssize_t set_port_type(struct device *dev,
672 struct device_attribute *attr,
673 const char *buf, size_t count)
675 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
677 struct mlx4_dev *mdev = info->dev;
678 struct mlx4_priv *priv = mlx4_priv(mdev);
679 enum mlx4_port_type types[MLX4_MAX_PORTS];
680 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
684 if (!strcmp(buf, "ib\n"))
685 info->tmp_type = MLX4_PORT_TYPE_IB;
686 else if (!strcmp(buf, "eth\n"))
687 info->tmp_type = MLX4_PORT_TYPE_ETH;
688 else if (!strcmp(buf, "auto\n"))
689 info->tmp_type = MLX4_PORT_TYPE_AUTO;
691 mlx4_err(mdev, "%s is not supported port type\n", buf);
695 mlx4_stop_sense(mdev);
696 mutex_lock(&priv->port_mutex);
697 /* Possible type is always the one that was delivered */
698 mdev->caps.possible_type[info->port] = info->tmp_type;
700 for (i = 0; i < mdev->caps.num_ports; i++) {
701 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
702 mdev->caps.possible_type[i+1];
703 if (types[i] == MLX4_PORT_TYPE_AUTO)
704 types[i] = mdev->caps.port_type[i+1];
707 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
708 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
709 for (i = 1; i <= mdev->caps.num_ports; i++) {
710 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
711 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
717 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
718 "Set only 'eth' or 'ib' for both ports "
719 "(should be the same)\n");
723 mlx4_do_sense_ports(mdev, new_types, types);
725 err = mlx4_check_port_params(mdev, new_types);
729 /* We are about to apply the changes after the configuration
730 * was verified, no need to remember the temporary types
732 for (i = 0; i < mdev->caps.num_ports; i++)
733 priv->port[i + 1].tmp_type = 0;
735 err = mlx4_change_port_types(mdev, new_types);
738 mlx4_start_sense(mdev);
739 mutex_unlock(&priv->port_mutex);
740 return err ? err : count;
751 static inline int int_to_ibta_mtu(int mtu)
754 case 256: return IB_MTU_256;
755 case 512: return IB_MTU_512;
756 case 1024: return IB_MTU_1024;
757 case 2048: return IB_MTU_2048;
758 case 4096: return IB_MTU_4096;
763 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
766 case IB_MTU_256: return 256;
767 case IB_MTU_512: return 512;
768 case IB_MTU_1024: return 1024;
769 case IB_MTU_2048: return 2048;
770 case IB_MTU_4096: return 4096;
775 static ssize_t show_port_ib_mtu(struct device *dev,
776 struct device_attribute *attr,
779 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
781 struct mlx4_dev *mdev = info->dev;
783 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
784 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
787 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
791 static ssize_t set_port_ib_mtu(struct device *dev,
792 struct device_attribute *attr,
793 const char *buf, size_t count)
795 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
797 struct mlx4_dev *mdev = info->dev;
798 struct mlx4_priv *priv = mlx4_priv(mdev);
799 int err, port, mtu, ibta_mtu = -1;
801 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
802 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
806 err = sscanf(buf, "%d", &mtu);
808 ibta_mtu = int_to_ibta_mtu(mtu);
810 if (err <= 0 || ibta_mtu < 0) {
811 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
815 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
817 mlx4_stop_sense(mdev);
818 mutex_lock(&priv->port_mutex);
819 mlx4_unregister_device(mdev);
820 for (port = 1; port <= mdev->caps.num_ports; port++) {
821 mlx4_CLOSE_PORT(mdev, port);
822 err = mlx4_SET_PORT(mdev, port, -1);
824 mlx4_err(mdev, "Failed to set port %d, "
829 err = mlx4_register_device(mdev);
831 mutex_unlock(&priv->port_mutex);
832 mlx4_start_sense(mdev);
833 return err ? err : count;
836 static int mlx4_load_fw(struct mlx4_dev *dev)
838 struct mlx4_priv *priv = mlx4_priv(dev);
841 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
842 GFP_HIGHUSER | __GFP_NOWARN, 0);
843 if (!priv->fw.fw_icm) {
844 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
848 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
850 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
854 err = mlx4_RUN_FW(dev);
856 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
866 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
870 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
873 struct mlx4_priv *priv = mlx4_priv(dev);
877 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
879 ((u64) (MLX4_CMPT_TYPE_QP *
880 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
881 cmpt_entry_sz, dev->caps.num_qps,
882 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
887 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
889 ((u64) (MLX4_CMPT_TYPE_SRQ *
890 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
891 cmpt_entry_sz, dev->caps.num_srqs,
892 dev->caps.reserved_srqs, 0, 0);
896 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
898 ((u64) (MLX4_CMPT_TYPE_CQ *
899 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
900 cmpt_entry_sz, dev->caps.num_cqs,
901 dev->caps.reserved_cqs, 0, 0);
905 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
907 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
909 ((u64) (MLX4_CMPT_TYPE_EQ *
910 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
911 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
918 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
921 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
924 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
930 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
931 struct mlx4_init_hca_param *init_hca, u64 icm_size)
933 struct mlx4_priv *priv = mlx4_priv(dev);
938 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
940 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
944 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
945 (unsigned long long) icm_size >> 10,
946 (unsigned long long) aux_pages << 2);
948 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
949 GFP_HIGHUSER | __GFP_NOWARN, 0);
950 if (!priv->fw.aux_icm) {
951 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
955 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
957 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
961 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
963 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
968 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
970 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
971 init_hca->eqc_base, dev_cap->eqc_entry_sz,
972 num_eqs, num_eqs, 0, 0);
974 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
979 * Reserved MTT entries must be aligned up to a cacheline
980 * boundary, since the FW will write to them, while the driver
981 * writes to all other MTT entries. (The variable
982 * dev->caps.mtt_entry_sz below is really the MTT segment
983 * size, not the raw entry size)
985 dev->caps.reserved_mtts =
986 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
987 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
989 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
991 dev->caps.mtt_entry_sz,
993 dev->caps.reserved_mtts, 1, 0);
995 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
999 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1000 init_hca->dmpt_base,
1001 dev_cap->dmpt_entry_sz,
1003 dev->caps.reserved_mrws, 1, 1);
1005 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1009 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1011 dev_cap->qpc_entry_sz,
1013 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1016 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1017 goto err_unmap_dmpt;
1020 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1021 init_hca->auxc_base,
1022 dev_cap->aux_entry_sz,
1024 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1027 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1031 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1032 init_hca->altc_base,
1033 dev_cap->altc_entry_sz,
1035 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1038 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1039 goto err_unmap_auxc;
1042 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1043 init_hca->rdmarc_base,
1044 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1046 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1049 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1050 goto err_unmap_altc;
1053 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1055 dev_cap->cqc_entry_sz,
1057 dev->caps.reserved_cqs, 0, 0);
1059 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1060 goto err_unmap_rdmarc;
1063 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1064 init_hca->srqc_base,
1065 dev_cap->srq_entry_sz,
1067 dev->caps.reserved_srqs, 0, 0);
1069 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1074 * For flow steering device managed mode it is required to use
1075 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1076 * required, but for simplicity just map the whole multicast
1077 * group table now. The table isn't very big and it's a lot
1078 * easier than trying to track ref counts.
1080 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1082 mlx4_get_mgm_entry_size(dev),
1083 dev->caps.num_mgms + dev->caps.num_amgms,
1084 dev->caps.num_mgms + dev->caps.num_amgms,
1087 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1094 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1097 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1100 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1103 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1106 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1109 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1112 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1115 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1118 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1121 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1122 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1123 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1124 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1127 mlx4_UNMAP_ICM_AUX(dev);
1130 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1135 static void mlx4_free_icms(struct mlx4_dev *dev)
1137 struct mlx4_priv *priv = mlx4_priv(dev);
1139 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1140 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1141 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1142 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1143 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1144 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1145 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1146 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1147 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1148 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1149 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1150 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1151 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1152 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1154 mlx4_UNMAP_ICM_AUX(dev);
1155 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1158 static void mlx4_slave_exit(struct mlx4_dev *dev)
1160 struct mlx4_priv *priv = mlx4_priv(dev);
1162 down(&priv->cmd.slave_sem);
1163 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1164 mlx4_warn(dev, "Failed to close slave function.\n");
1165 up(&priv->cmd.slave_sem);
1168 static int map_bf_area(struct mlx4_dev *dev)
1170 struct mlx4_priv *priv = mlx4_priv(dev);
1171 resource_size_t bf_start;
1172 resource_size_t bf_len;
1175 if (!dev->caps.bf_reg_size)
1178 bf_start = pci_resource_start(dev->pdev, 2) +
1179 (dev->caps.num_uars << PAGE_SHIFT);
1180 bf_len = pci_resource_len(dev->pdev, 2) -
1181 (dev->caps.num_uars << PAGE_SHIFT);
1182 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1183 if (!priv->bf_mapping)
1189 static void unmap_bf_area(struct mlx4_dev *dev)
1191 if (mlx4_priv(dev)->bf_mapping)
1192 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1195 static void mlx4_close_hca(struct mlx4_dev *dev)
1198 if (mlx4_is_slave(dev))
1199 mlx4_slave_exit(dev);
1201 mlx4_CLOSE_HCA(dev, 0);
1202 mlx4_free_icms(dev);
1204 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1208 static int mlx4_init_slave(struct mlx4_dev *dev)
1210 struct mlx4_priv *priv = mlx4_priv(dev);
1211 u64 dma = (u64) priv->mfunc.vhcr_dma;
1212 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1213 int ret_from_reset = 0;
1215 u32 cmd_channel_ver;
1217 down(&priv->cmd.slave_sem);
1218 priv->cmd.max_cmds = 1;
1219 mlx4_warn(dev, "Sending reset\n");
1220 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1222 /* if we are in the middle of flr the slave will try
1223 * NUM_OF_RESET_RETRIES times before leaving.*/
1224 if (ret_from_reset) {
1225 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1226 msleep(SLEEP_TIME_IN_RESET);
1227 while (ret_from_reset && num_of_reset_retries) {
1228 mlx4_warn(dev, "slave is currently in the"
1229 "middle of FLR. retrying..."
1231 (NUM_OF_RESET_RETRIES -
1232 num_of_reset_retries + 1));
1234 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1236 num_of_reset_retries = num_of_reset_retries - 1;
1242 /* check the driver version - the slave I/F revision
1243 * must match the master's */
1244 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1245 cmd_channel_ver = mlx4_comm_get_version();
1247 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1248 MLX4_COMM_GET_IF_REV(slave_read)) {
1249 mlx4_err(dev, "slave driver version is not supported"
1250 " by the master\n");
1254 mlx4_warn(dev, "Sending vhcr0\n");
1255 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1258 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1261 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1264 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1266 up(&priv->cmd.slave_sem);
1270 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1271 up(&priv->cmd.slave_sem);
1275 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1279 for (i = 1; i <= dev->caps.num_ports; i++) {
1280 dev->caps.gid_table_len[i] = 1;
1281 dev->caps.pkey_table_len[i] =
1282 dev->phys_caps.pkey_phys_table_len[i] - 1;
1286 static int mlx4_init_hca(struct mlx4_dev *dev)
1288 struct mlx4_priv *priv = mlx4_priv(dev);
1289 struct mlx4_adapter adapter;
1290 struct mlx4_dev_cap dev_cap;
1291 struct mlx4_mod_stat_cfg mlx4_cfg;
1292 struct mlx4_profile profile;
1293 struct mlx4_init_hca_param init_hca;
1297 if (!mlx4_is_slave(dev)) {
1298 err = mlx4_QUERY_FW(dev);
1301 mlx4_info(dev, "non-primary physical function, skipping.\n");
1303 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1307 err = mlx4_load_fw(dev);
1309 mlx4_err(dev, "Failed to start FW, aborting.\n");
1313 mlx4_cfg.log_pg_sz_m = 1;
1314 mlx4_cfg.log_pg_sz = 0;
1315 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1317 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1319 err = mlx4_dev_cap(dev, &dev_cap);
1321 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1325 if (mlx4_is_master(dev))
1326 mlx4_parav_master_pf_caps(dev);
1328 priv->fs_hash_mode = MLX4_FS_L2_HASH;
1330 switch (priv->fs_hash_mode) {
1331 case MLX4_FS_L2_HASH:
1332 init_hca.fs_hash_enable_bits = 0;
1335 case MLX4_FS_L2_L3_L4_HASH:
1336 /* Enable flow steering with
1337 * udp unicast and tcp unicast
1339 init_hca.fs_hash_enable_bits =
1340 MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
1344 profile = default_profile;
1345 if (dev->caps.steering_mode ==
1346 MLX4_STEERING_MODE_DEVICE_MANAGED)
1347 profile.num_mcg = MLX4_FS_NUM_MCG;
1349 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1351 if ((long long) icm_size < 0) {
1356 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1358 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1359 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1361 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1365 err = mlx4_INIT_HCA(dev, &init_hca);
1367 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1371 err = mlx4_init_slave(dev);
1373 mlx4_err(dev, "Failed to initialize slave\n");
1377 err = mlx4_slave_cap(dev);
1379 mlx4_err(dev, "Failed to obtain slave caps\n");
1384 if (map_bf_area(dev))
1385 mlx4_dbg(dev, "Failed to map blue flame area\n");
1387 /*Only the master set the ports, all the rest got it from it.*/
1388 if (!mlx4_is_slave(dev))
1389 mlx4_set_port_mask(dev);
1391 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1393 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1397 priv->eq_table.inta_pin = adapter.inta_pin;
1398 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1406 mlx4_close_hca(dev);
1409 if (!mlx4_is_slave(dev))
1410 mlx4_free_icms(dev);
1413 if (!mlx4_is_slave(dev)) {
1415 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1420 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1422 struct mlx4_priv *priv = mlx4_priv(dev);
1425 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1428 nent = dev->caps.max_counters;
1429 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1432 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1434 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1437 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1439 struct mlx4_priv *priv = mlx4_priv(dev);
1441 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1444 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1451 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1456 if (mlx4_is_mfunc(dev)) {
1457 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1458 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1459 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1461 *idx = get_param_l(&out_param);
1465 return __mlx4_counter_alloc(dev, idx);
1467 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1469 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1471 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
1475 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1479 if (mlx4_is_mfunc(dev)) {
1480 set_param_l(&in_param, idx);
1481 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1482 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1486 __mlx4_counter_free(dev, idx);
1488 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1490 static int mlx4_setup_hca(struct mlx4_dev *dev)
1492 struct mlx4_priv *priv = mlx4_priv(dev);
1495 __be32 ib_port_default_caps;
1497 err = mlx4_init_uar_table(dev);
1499 mlx4_err(dev, "Failed to initialize "
1500 "user access region table, aborting.\n");
1504 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1506 mlx4_err(dev, "Failed to allocate driver access region, "
1508 goto err_uar_table_free;
1511 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1513 mlx4_err(dev, "Couldn't map kernel access region, "
1519 err = mlx4_init_pd_table(dev);
1521 mlx4_err(dev, "Failed to initialize "
1522 "protection domain table, aborting.\n");
1526 err = mlx4_init_xrcd_table(dev);
1528 mlx4_err(dev, "Failed to initialize "
1529 "reliable connection domain table, aborting.\n");
1530 goto err_pd_table_free;
1533 err = mlx4_init_mr_table(dev);
1535 mlx4_err(dev, "Failed to initialize "
1536 "memory region table, aborting.\n");
1537 goto err_xrcd_table_free;
1540 err = mlx4_init_eq_table(dev);
1542 mlx4_err(dev, "Failed to initialize "
1543 "event queue table, aborting.\n");
1544 goto err_mr_table_free;
1547 err = mlx4_cmd_use_events(dev);
1549 mlx4_err(dev, "Failed to switch to event-driven "
1550 "firmware commands, aborting.\n");
1551 goto err_eq_table_free;
1554 err = mlx4_NOP(dev);
1556 if (dev->flags & MLX4_FLAG_MSI_X) {
1557 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1558 "interrupt IRQ %d).\n",
1559 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1560 mlx4_warn(dev, "Trying again without MSI-X.\n");
1562 mlx4_err(dev, "NOP command failed to generate interrupt "
1563 "(IRQ %d), aborting.\n",
1564 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1565 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1571 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1573 err = mlx4_init_cq_table(dev);
1575 mlx4_err(dev, "Failed to initialize "
1576 "completion queue table, aborting.\n");
1580 err = mlx4_init_srq_table(dev);
1582 mlx4_err(dev, "Failed to initialize "
1583 "shared receive queue table, aborting.\n");
1584 goto err_cq_table_free;
1587 err = mlx4_init_qp_table(dev);
1589 mlx4_err(dev, "Failed to initialize "
1590 "queue pair table, aborting.\n");
1591 goto err_srq_table_free;
1594 if (!mlx4_is_slave(dev)) {
1595 err = mlx4_init_mcg_table(dev);
1597 mlx4_err(dev, "Failed to initialize "
1598 "multicast group table, aborting.\n");
1599 goto err_qp_table_free;
1603 err = mlx4_init_counters_table(dev);
1604 if (err && err != -ENOENT) {
1605 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1606 goto err_mcg_table_free;
1609 if (!mlx4_is_slave(dev)) {
1610 for (port = 1; port <= dev->caps.num_ports; port++) {
1611 ib_port_default_caps = 0;
1612 err = mlx4_get_port_ib_caps(dev, port,
1613 &ib_port_default_caps);
1615 mlx4_warn(dev, "failed to get port %d default "
1616 "ib capabilities (%d). Continuing "
1617 "with caps = 0\n", port, err);
1618 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1620 /* initialize per-slave default ib port capabilities */
1621 if (mlx4_is_master(dev)) {
1623 for (i = 0; i < dev->num_slaves; i++) {
1624 if (i == mlx4_master_func_num(dev))
1626 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1627 ib_port_default_caps;
1631 if (mlx4_is_mfunc(dev))
1632 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1634 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1636 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1637 dev->caps.pkey_table_len[port] : -1);
1639 mlx4_err(dev, "Failed to set port %d, aborting\n",
1641 goto err_counters_table_free;
1648 err_counters_table_free:
1649 mlx4_cleanup_counters_table(dev);
1652 mlx4_cleanup_mcg_table(dev);
1655 mlx4_cleanup_qp_table(dev);
1658 mlx4_cleanup_srq_table(dev);
1661 mlx4_cleanup_cq_table(dev);
1664 mlx4_cmd_use_polling(dev);
1667 mlx4_cleanup_eq_table(dev);
1670 mlx4_cleanup_mr_table(dev);
1672 err_xrcd_table_free:
1673 mlx4_cleanup_xrcd_table(dev);
1676 mlx4_cleanup_pd_table(dev);
1682 mlx4_uar_free(dev, &priv->driver_uar);
1685 mlx4_cleanup_uar_table(dev);
1689 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1691 struct mlx4_priv *priv = mlx4_priv(dev);
1692 struct msix_entry *entries;
1693 int nreq = min_t(int, dev->caps.num_ports *
1694 min_t(int, netif_get_num_default_rss_queues() + 1,
1695 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1700 /* In multifunction mode each function gets 2 msi-X vectors
1701 * one for data path completions anf the other for asynch events
1702 * or command completions */
1703 if (mlx4_is_mfunc(dev)) {
1706 nreq = min_t(int, dev->caps.num_eqs -
1707 dev->caps.reserved_eqs, nreq);
1710 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1714 for (i = 0; i < nreq; ++i)
1715 entries[i].entry = i;
1718 err = pci_enable_msix(dev->pdev, entries, nreq);
1720 /* Try again if at least 2 vectors are available */
1722 mlx4_info(dev, "Requested %d vectors, "
1723 "but only %d MSI-X vectors available, "
1724 "trying again\n", nreq, err);
1733 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1734 /*Working in legacy mode , all EQ's shared*/
1735 dev->caps.comp_pool = 0;
1736 dev->caps.num_comp_vectors = nreq - 1;
1738 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1739 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1741 for (i = 0; i < nreq; ++i)
1742 priv->eq_table.eq[i].irq = entries[i].vector;
1744 dev->flags |= MLX4_FLAG_MSI_X;
1751 dev->caps.num_comp_vectors = 1;
1752 dev->caps.comp_pool = 0;
1754 for (i = 0; i < 2; ++i)
1755 priv->eq_table.eq[i].irq = dev->pdev->irq;
1758 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1760 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1765 if (!mlx4_is_slave(dev)) {
1766 INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL);
1767 mlx4_init_mac_table(dev, &info->mac_table);
1768 mlx4_init_vlan_table(dev, &info->vlan_table);
1770 dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1771 (port - 1) * (1 << log_num_mac);
1774 sprintf(info->dev_name, "mlx4_port%d", port);
1775 info->port_attr.attr.name = info->dev_name;
1776 if (mlx4_is_mfunc(dev))
1777 info->port_attr.attr.mode = S_IRUGO;
1779 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1780 info->port_attr.store = set_port_type;
1782 info->port_attr.show = show_port_type;
1783 sysfs_attr_init(&info->port_attr.attr);
1785 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1787 mlx4_err(dev, "Failed to create file for port %d\n", port);
1791 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
1792 info->port_mtu_attr.attr.name = info->dev_mtu_name;
1793 if (mlx4_is_mfunc(dev))
1794 info->port_mtu_attr.attr.mode = S_IRUGO;
1796 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
1797 info->port_mtu_attr.store = set_port_ib_mtu;
1799 info->port_mtu_attr.show = show_port_ib_mtu;
1800 sysfs_attr_init(&info->port_mtu_attr.attr);
1802 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
1804 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
1805 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1812 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1817 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1818 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
1821 static int mlx4_init_steering(struct mlx4_dev *dev)
1823 struct mlx4_priv *priv = mlx4_priv(dev);
1824 int num_entries = dev->caps.num_ports;
1827 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1831 for (i = 0; i < num_entries; i++)
1832 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1833 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1834 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1839 static void mlx4_clear_steering(struct mlx4_dev *dev)
1841 struct mlx4_priv *priv = mlx4_priv(dev);
1842 struct mlx4_steer_index *entry, *tmp_entry;
1843 struct mlx4_promisc_qp *pqp, *tmp_pqp;
1844 int num_entries = dev->caps.num_ports;
1847 for (i = 0; i < num_entries; i++) {
1848 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1849 list_for_each_entry_safe(pqp, tmp_pqp,
1850 &priv->steer[i].promisc_qps[j],
1852 list_del(&pqp->list);
1855 list_for_each_entry_safe(entry, tmp_entry,
1856 &priv->steer[i].steer_entries[j],
1858 list_del(&entry->list);
1859 list_for_each_entry_safe(pqp, tmp_pqp,
1862 list_del(&pqp->list);
1872 static int extended_func_num(struct pci_dev *pdev)
1874 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
1877 #define MLX4_OWNER_BASE 0x8069c
1878 #define MLX4_OWNER_SIZE 4
1880 static int mlx4_get_ownership(struct mlx4_dev *dev)
1882 void __iomem *owner;
1885 if (pci_channel_offline(dev->pdev))
1888 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1891 mlx4_err(dev, "Failed to obtain ownership bit\n");
1900 static void mlx4_free_ownership(struct mlx4_dev *dev)
1902 void __iomem *owner;
1904 if (pci_channel_offline(dev->pdev))
1907 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
1910 mlx4_err(dev, "Failed to obtain ownership bit\n");
1918 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1920 struct mlx4_priv *priv;
1921 struct mlx4_dev *dev;
1925 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1927 err = pci_enable_device(pdev);
1929 dev_err(&pdev->dev, "Cannot enable PCI device, "
1933 if (num_vfs > MLX4_MAX_NUM_VF) {
1934 printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n",
1935 num_vfs, MLX4_MAX_NUM_VF);
1941 if (((id == NULL) || !(id->driver_data & MLX4_VF)) &&
1942 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1943 dev_err(&pdev->dev, "Missing DCS, aborting."
1944 "(id == 0X%p, id->driver_data: 0x%lx,"
1945 " pci_resource_flags(pdev, 0):0x%lx)\n", id,
1946 id ? id->driver_data : 0, pci_resource_flags(pdev, 0));
1948 goto err_disable_pdev;
1950 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1951 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1953 goto err_disable_pdev;
1956 err = pci_request_regions(pdev, DRV_NAME);
1958 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1959 goto err_disable_pdev;
1962 pci_set_master(pdev);
1964 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1966 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1967 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1969 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1970 goto err_release_regions;
1973 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1975 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1976 "consistent PCI DMA mask.\n");
1977 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1979 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1981 goto err_release_regions;
1985 /* Allow large DMA segments, up to the firmware limit of 1 GB */
1986 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1988 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1990 dev_err(&pdev->dev, "Device struct alloc failed, "
1993 goto err_release_regions;
1998 INIT_LIST_HEAD(&priv->ctx_list);
1999 spin_lock_init(&priv->ctx_lock);
2001 mutex_init(&priv->port_mutex);
2003 INIT_LIST_HEAD(&priv->pgdir_list);
2004 mutex_init(&priv->pgdir_mutex);
2006 INIT_LIST_HEAD(&priv->bf_list);
2007 mutex_init(&priv->bf_mutex);
2009 dev->rev_id = pdev->revision;
2010 /* Detect if this device is a virtual function */
2011 if (id && id->driver_data & MLX4_VF) {
2012 /* When acting as pf, we normally skip vfs unless explicitly
2013 * requested to probe them. */
2014 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2015 mlx4_warn(dev, "Skipping virtual function:%d\n",
2016 extended_func_num(pdev));
2020 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2021 dev->flags |= MLX4_FLAG_SLAVE;
2023 /* We reset the device and enable SRIOV only for physical
2024 * devices. Try to claim ownership on the device;
2025 * if already taken, skip -- do not allow multiple PFs */
2026 err = mlx4_get_ownership(dev);
2031 mlx4_warn(dev, "Multiple PFs not yet supported."
2039 mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs);
2040 err = pci_enable_sriov(pdev, num_vfs);
2042 mlx4_err(dev, "Failed to enable sriov,"
2043 "continuing without sriov enabled"
2044 " (err = %d).\n", err);
2047 mlx4_warn(dev, "Running in master mode\n");
2048 dev->flags |= MLX4_FLAG_SRIOV |
2050 dev->num_vfs = num_vfs;
2055 * Now reset the HCA before we touch the PCI capabilities or
2056 * attempt a firmware command, since a boot ROM may have left
2057 * the HCA in an undefined state.
2059 err = mlx4_reset(dev);
2061 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2067 err = mlx4_cmd_init(dev);
2069 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2073 /* In slave functions, the communication channel must be initialized
2074 * before posting commands. Also, init num_slaves before calling
2076 if (mlx4_is_mfunc(dev)) {
2077 if (mlx4_is_master(dev))
2078 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2080 dev->num_slaves = 0;
2081 if (mlx4_multi_func_init(dev)) {
2082 mlx4_err(dev, "Failed to init slave mfunc"
2083 " interface, aborting.\n");
2089 err = mlx4_init_hca(dev);
2091 if (err == -EACCES) {
2092 /* Not primary Physical function
2093 * Running in slave mode */
2094 mlx4_cmd_cleanup(dev);
2095 dev->flags |= MLX4_FLAG_SLAVE;
2096 dev->flags &= ~MLX4_FLAG_MASTER;
2102 /* In master functions, the communication channel must be initialized
2103 * after obtaining its address from fw */
2104 if (mlx4_is_master(dev)) {
2105 if (mlx4_multi_func_init(dev)) {
2106 mlx4_err(dev, "Failed to init master mfunc"
2107 "interface, aborting.\n");
2112 err = mlx4_alloc_eq_table(dev);
2114 goto err_master_mfunc;
2116 priv->msix_ctl.pool_bm = 0;
2117 mutex_init(&priv->msix_ctl.pool_lock);
2119 mlx4_enable_msi_x(dev);
2120 if ((mlx4_is_mfunc(dev)) &&
2121 !(dev->flags & MLX4_FLAG_MSI_X)) {
2122 mlx4_err(dev, "INTx is not supported in multi-function mode."
2127 if (!mlx4_is_slave(dev)) {
2128 err = mlx4_init_steering(dev);
2133 err = mlx4_setup_hca(dev);
2134 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2135 !mlx4_is_mfunc(dev)) {
2136 dev->flags &= ~MLX4_FLAG_MSI_X;
2137 dev->caps.num_comp_vectors = 1;
2138 dev->caps.comp_pool = 0;
2139 pci_disable_msix(pdev);
2140 err = mlx4_setup_hca(dev);
2146 for (port = 1; port <= dev->caps.num_ports; port++) {
2147 err = mlx4_init_port_info(dev, port);
2152 err = mlx4_register_device(dev);
2156 mlx4_sense_init(dev);
2157 mlx4_start_sense(dev);
2159 pci_set_drvdata(pdev, dev);
2164 for (--port; port >= 1; --port)
2165 mlx4_cleanup_port_info(&priv->port[port]);
2167 mlx4_cleanup_counters_table(dev);
2168 mlx4_cleanup_mcg_table(dev);
2169 mlx4_cleanup_qp_table(dev);
2170 mlx4_cleanup_srq_table(dev);
2171 mlx4_cleanup_cq_table(dev);
2172 mlx4_cmd_use_polling(dev);
2173 mlx4_cleanup_eq_table(dev);
2174 mlx4_cleanup_mr_table(dev);
2175 mlx4_cleanup_xrcd_table(dev);
2176 mlx4_cleanup_pd_table(dev);
2177 mlx4_cleanup_uar_table(dev);
2180 if (!mlx4_is_slave(dev))
2181 mlx4_clear_steering(dev);
2184 mlx4_free_eq_table(dev);
2187 if (mlx4_is_master(dev))
2188 mlx4_multi_func_cleanup(dev);
2191 if (dev->flags & MLX4_FLAG_MSI_X)
2192 pci_disable_msix(pdev);
2194 mlx4_close_hca(dev);
2197 if (mlx4_is_slave(dev))
2198 mlx4_multi_func_cleanup(dev);
2201 mlx4_cmd_cleanup(dev);
2204 if (dev->flags & MLX4_FLAG_SRIOV)
2205 pci_disable_sriov(pdev);
2208 if (!mlx4_is_slave(dev))
2209 mlx4_free_ownership(dev);
2214 err_release_regions:
2215 pci_release_regions(pdev);
2218 pci_disable_device(pdev);
2219 pci_set_drvdata(pdev, NULL);
2223 static int __devinit mlx4_init_one(struct pci_dev *pdev,
2224 const struct pci_device_id *id)
2226 printk_once(KERN_INFO "%s", mlx4_version);
2228 return __mlx4_init_one(pdev, id);
2231 static void mlx4_remove_one(struct pci_dev *pdev)
2233 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2234 struct mlx4_priv *priv = mlx4_priv(dev);
2238 /* in SRIOV it is not allowed to unload the pf's
2239 * driver while there are alive vf's */
2240 if (mlx4_is_master(dev)) {
2241 if (mlx4_how_many_lives_vf(dev))
2242 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2244 mlx4_stop_sense(dev);
2245 mlx4_unregister_device(dev);
2247 for (p = 1; p <= dev->caps.num_ports; p++) {
2248 mlx4_cleanup_port_info(&priv->port[p]);
2249 mlx4_CLOSE_PORT(dev, p);
2252 if (mlx4_is_master(dev))
2253 mlx4_free_resource_tracker(dev,
2254 RES_TR_FREE_SLAVES_ONLY);
2256 mlx4_cleanup_counters_table(dev);
2257 mlx4_cleanup_mcg_table(dev);
2258 mlx4_cleanup_qp_table(dev);
2259 mlx4_cleanup_srq_table(dev);
2260 mlx4_cleanup_cq_table(dev);
2261 mlx4_cmd_use_polling(dev);
2262 mlx4_cleanup_eq_table(dev);
2263 mlx4_cleanup_mr_table(dev);
2264 mlx4_cleanup_xrcd_table(dev);
2265 mlx4_cleanup_pd_table(dev);
2267 if (mlx4_is_master(dev))
2268 mlx4_free_resource_tracker(dev,
2269 RES_TR_FREE_STRUCTS_ONLY);
2272 mlx4_uar_free(dev, &priv->driver_uar);
2273 mlx4_cleanup_uar_table(dev);
2274 if (!mlx4_is_slave(dev))
2275 mlx4_clear_steering(dev);
2276 mlx4_free_eq_table(dev);
2277 if (mlx4_is_master(dev))
2278 mlx4_multi_func_cleanup(dev);
2279 mlx4_close_hca(dev);
2280 if (mlx4_is_slave(dev))
2281 mlx4_multi_func_cleanup(dev);
2282 mlx4_cmd_cleanup(dev);
2284 if (dev->flags & MLX4_FLAG_MSI_X)
2285 pci_disable_msix(pdev);
2286 if (dev->flags & MLX4_FLAG_SRIOV) {
2287 mlx4_warn(dev, "Disabling sriov\n");
2288 pci_disable_sriov(pdev);
2291 if (!mlx4_is_slave(dev))
2292 mlx4_free_ownership(dev);
2294 kfree(dev->caps.qp0_tunnel);
2295 kfree(dev->caps.qp0_proxy);
2296 kfree(dev->caps.qp1_tunnel);
2297 kfree(dev->caps.qp1_proxy);
2300 pci_release_regions(pdev);
2301 pci_disable_device(pdev);
2302 pci_set_drvdata(pdev, NULL);
2306 int mlx4_restart_one(struct pci_dev *pdev)
2308 mlx4_remove_one(pdev);
2309 return __mlx4_init_one(pdev, NULL);
2312 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2313 /* MT25408 "Hermon" SDR */
2314 { PCI_VDEVICE(MELLANOX, 0x6340), 0 },
2315 /* MT25408 "Hermon" DDR */
2316 { PCI_VDEVICE(MELLANOX, 0x634a), 0 },
2317 /* MT25408 "Hermon" QDR */
2318 { PCI_VDEVICE(MELLANOX, 0x6354), 0 },
2319 /* MT25408 "Hermon" DDR PCIe gen2 */
2320 { PCI_VDEVICE(MELLANOX, 0x6732), 0 },
2321 /* MT25408 "Hermon" QDR PCIe gen2 */
2322 { PCI_VDEVICE(MELLANOX, 0x673c), 0 },
2323 /* MT25408 "Hermon" EN 10GigE */
2324 { PCI_VDEVICE(MELLANOX, 0x6368), 0 },
2325 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2326 { PCI_VDEVICE(MELLANOX, 0x6750), 0 },
2327 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2328 { PCI_VDEVICE(MELLANOX, 0x6372), 0 },
2329 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2330 { PCI_VDEVICE(MELLANOX, 0x675a), 0 },
2331 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2332 { PCI_VDEVICE(MELLANOX, 0x6764), 0 },
2333 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2334 { PCI_VDEVICE(MELLANOX, 0x6746), 0 },
2335 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2336 { PCI_VDEVICE(MELLANOX, 0x676e), 0 },
2337 /* MT25400 Family [ConnectX-2 Virtual Function] */
2338 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF },
2339 /* MT27500 Family [ConnectX-3] */
2340 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2341 /* MT27500 Family [ConnectX-3 Virtual Function] */
2342 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF },
2343 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2344 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2345 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2346 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2347 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2348 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2349 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2350 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2351 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2352 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2353 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2354 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2358 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2360 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2361 pci_channel_state_t state)
2363 mlx4_remove_one(pdev);
2365 return state == pci_channel_io_perm_failure ?
2366 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2369 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2371 int ret = __mlx4_init_one(pdev, NULL);
2373 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2376 static struct pci_error_handlers mlx4_err_handler = {
2377 .error_detected = mlx4_pci_err_detected,
2378 .slot_reset = mlx4_pci_slot_reset,
2381 static struct pci_driver mlx4_driver = {
2383 .id_table = mlx4_pci_table,
2384 .probe = mlx4_init_one,
2385 .remove = __devexit_p(mlx4_remove_one),
2386 .err_handler = &mlx4_err_handler,
2389 static int __init mlx4_verify_params(void)
2391 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2392 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2396 if (log_num_vlan != 0)
2397 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2398 MLX4_LOG_NUM_VLANS);
2400 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2401 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2405 /* Check if module param for ports type has legal combination */
2406 if (port_type_array[0] == false && port_type_array[1] == true) {
2407 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2408 port_type_array[0] = true;
2414 static int __init mlx4_init(void)
2418 if (mlx4_verify_params())
2423 mlx4_wq = create_singlethread_workqueue("mlx4");
2427 ret = pci_register_driver(&mlx4_driver);
2428 return ret < 0 ? ret : 0;
2431 static void __exit mlx4_cleanup(void)
2433 pci_unregister_driver(&mlx4_driver);
2434 destroy_workqueue(mlx4_wq);
2437 module_init(mlx4_init);
2438 module_exit(mlx4_cleanup);