2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
81 module_param(num_vfs, int, 0444);
82 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
85 module_param(probe_vf, int, 0644);
86 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
88 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
89 module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
93 " 10 gives 248.range: 7 <="
94 " log_num_mgm_entry_size <= 12."
95 " To activate device managed"
96 " flow steering when available, set to -1");
98 static bool enable_64b_cqe_eqe = true;
99 module_param(enable_64b_cqe_eqe, bool, 0444);
100 MODULE_PARM_DESC(enable_64b_cqe_eqe,
101 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
103 #define HCA_GLOBAL_CAP_MASK 0
105 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
107 static char mlx4_version[] =
108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
111 static struct mlx4_profile default_profile = {
114 .rdmarc_per_qp = 1 << 4,
118 .num_mtt = 1 << 20, /* It is really num mtt segements */
121 static int log_num_mac = 7;
122 module_param_named(log_num_mac, log_num_mac, int, 0444);
123 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
125 static int log_num_vlan;
126 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
128 /* Log2 max number of VLANs per ETH port (0-7) */
129 #define MLX4_LOG_NUM_VLANS 7
131 static bool use_prio;
132 module_param_named(use_prio, use_prio, bool, 0444);
133 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
136 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
137 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
138 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
140 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
141 static int arr_argc = 2;
142 module_param_array(port_type_array, int, &arr_argc, 0444);
143 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
146 struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
152 int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
177 static void mlx4_set_port_mask(struct mlx4_dev *dev)
181 for (i = 1; i <= dev->caps.num_ports; ++i)
182 dev->caps.port_mask[i] = dev->caps.port_type[i];
185 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
205 dev_cap->num_ports, MLX4_MAX_PORTS);
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
217 dev->caps.num_ports = dev_cap->num_ports;
218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
240 dev->caps.uar_page_size = PAGE_SIZE;
241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
267 dev->caps.reserved_pds = dev_cap->reserved_pds;
268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
277 dev->caps.flags2 = dev_cap->flags2;
278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev))
289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
291 dev->caps.log_num_macs = log_num_mac;
292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
293 dev->caps.log_num_prios = use_prio ? 3 : 0;
295 for (i = 1; i <= dev->caps.num_ports; ++i) {
296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
297 if (dev->caps.supported_type[i]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
301 /* if only IB is supported, assign IB */
302 else if (dev->caps.supported_type[i] ==
304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
313 dev->caps.port_type[i] = port_type_array[i - 1];
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
322 mlx4_priv(dev)->sense.sense_allowed[i] =
323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
335 mlx4_SENSE_PORT(dev, i, &sensed_port);
336 if (sensed_port != MLX4_PORT_TYPE_NONE)
337 dev->caps.port_type[i] = sensed_port;
339 dev->caps.possible_type[i] = dev->caps.port_type[i];
342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
343 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
344 mlx4_warn(dev, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i, 1 << dev->caps.log_num_macs);
348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
350 mlx4_warn(dev, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_vlans);
356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
361 (1 << dev->caps.log_num_macs) *
362 (1 << dev->caps.log_num_vlans) *
363 (1 << dev->caps.log_num_prios) *
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
374 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
383 if ((dev->caps.flags &
384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
391 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
392 enum pci_bus_speed *speed,
393 enum pcie_link_width *width)
395 u32 lnkcap1, lnkcap2;
398 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
400 *speed = PCI_SPEED_UNKNOWN;
401 *width = PCIE_LNK_WIDTH_UNKNOWN;
403 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
404 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
405 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
406 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
407 *speed = PCIE_SPEED_8_0GT;
408 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
409 *speed = PCIE_SPEED_5_0GT;
410 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
411 *speed = PCIE_SPEED_2_5GT;
414 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
415 if (!lnkcap2) { /* pre-r3.0 */
416 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
417 *speed = PCIE_SPEED_5_0GT;
418 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
419 *speed = PCIE_SPEED_2_5GT;
423 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
425 err2 ? err2 : -EINVAL;
430 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
432 enum pcie_link_width width, width_cap;
433 enum pci_bus_speed speed, speed_cap;
436 #define PCIE_SPEED_STR(speed) \
437 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
438 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
439 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
442 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
445 "Unable to determine PCIe device BW capabilities\n");
449 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
450 if (err || speed == PCI_SPEED_UNKNOWN ||
451 width == PCIE_LNK_WIDTH_UNKNOWN) {
453 "Unable to determine PCI device chain minimum BW\n");
457 if (width != width_cap || speed != speed_cap)
459 "PCIe BW is different than device's capability\n");
461 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
462 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
463 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
468 /*The function checks if there are live vf, return the num of them*/
469 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
471 struct mlx4_priv *priv = mlx4_priv(dev);
472 struct mlx4_slave_state *s_state;
476 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
477 s_state = &priv->mfunc.master.slave_state[i];
478 if (s_state->active && s_state->last_cmd !=
479 MLX4_COMM_CMD_RESET) {
480 mlx4_warn(dev, "%s: slave: %d is still active\n",
488 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
490 u32 qk = MLX4_RESERVED_QKEY_BASE;
492 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
493 qpn < dev->phys_caps.base_proxy_sqpn)
496 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
498 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
500 qk += qpn - dev->phys_caps.base_proxy_sqpn;
504 EXPORT_SYMBOL(mlx4_get_parav_qkey);
506 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
508 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
510 if (!mlx4_is_master(dev))
513 priv->virt2phys_pkey[slave][port - 1][i] = val;
515 EXPORT_SYMBOL(mlx4_sync_pkey_table);
517 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
519 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
521 if (!mlx4_is_master(dev))
524 priv->slave_node_guids[slave] = guid;
526 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
528 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
530 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
532 if (!mlx4_is_master(dev))
535 return priv->slave_node_guids[slave];
537 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
539 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
541 struct mlx4_priv *priv = mlx4_priv(dev);
542 struct mlx4_slave_state *s_slave;
544 if (!mlx4_is_master(dev))
547 s_slave = &priv->mfunc.master.slave_state[slave];
548 return !!s_slave->active;
550 EXPORT_SYMBOL(mlx4_is_slave_active);
552 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
553 struct mlx4_dev_cap *dev_cap,
554 struct mlx4_init_hca_param *hca_param)
556 dev->caps.steering_mode = hca_param->steering_mode;
557 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
558 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
559 dev->caps.fs_log_max_ucast_qp_range_size =
560 dev_cap->fs_log_max_ucast_qp_range_size;
562 dev->caps.num_qp_per_mgm =
563 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
565 mlx4_dbg(dev, "Steering mode is: %s\n",
566 mlx4_steering_mode_str(dev->caps.steering_mode));
569 static int mlx4_slave_cap(struct mlx4_dev *dev)
573 struct mlx4_dev_cap dev_cap;
574 struct mlx4_func_cap func_cap;
575 struct mlx4_init_hca_param hca_param;
578 memset(&hca_param, 0, sizeof(hca_param));
579 err = mlx4_QUERY_HCA(dev, &hca_param);
581 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
585 /*fail if the hca has an unknown capability */
586 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
587 HCA_GLOBAL_CAP_MASK) {
588 mlx4_err(dev, "Unknown hca global capabilities\n");
592 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
594 dev->caps.hca_core_clock = hca_param.hca_core_clock;
596 memset(&dev_cap, 0, sizeof(dev_cap));
597 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
598 err = mlx4_dev_cap(dev, &dev_cap);
600 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
604 err = mlx4_QUERY_FW(dev);
606 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
608 page_size = ~dev->caps.page_size_cap + 1;
609 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
610 if (page_size > PAGE_SIZE) {
611 mlx4_err(dev, "HCA minimum page size of %d bigger than "
612 "kernel PAGE_SIZE of %ld, aborting.\n",
613 page_size, PAGE_SIZE);
617 /* slave gets uar page size from QUERY_HCA fw command */
618 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
620 /* TODO: relax this assumption */
621 if (dev->caps.uar_page_size != PAGE_SIZE) {
622 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
623 dev->caps.uar_page_size, PAGE_SIZE);
627 memset(&func_cap, 0, sizeof(func_cap));
628 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
630 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
635 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
636 PF_CONTEXT_BEHAVIOUR_MASK) {
637 mlx4_err(dev, "Unknown pf context behaviour\n");
641 dev->caps.num_ports = func_cap.num_ports;
642 dev->quotas.qp = func_cap.qp_quota;
643 dev->quotas.srq = func_cap.srq_quota;
644 dev->quotas.cq = func_cap.cq_quota;
645 dev->quotas.mpt = func_cap.mpt_quota;
646 dev->quotas.mtt = func_cap.mtt_quota;
647 dev->caps.num_qps = 1 << hca_param.log_num_qps;
648 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
649 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
650 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
651 dev->caps.num_eqs = func_cap.max_eq;
652 dev->caps.reserved_eqs = func_cap.reserved_eq;
653 dev->caps.num_pds = MLX4_NUM_PDS;
654 dev->caps.num_mgms = 0;
655 dev->caps.num_amgms = 0;
657 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
658 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
659 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
663 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
664 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
665 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
666 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
668 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
669 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
674 for (i = 1; i <= dev->caps.num_ports; ++i) {
675 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
677 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
678 " port %d, aborting (%d).\n", i, err);
681 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
682 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
683 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
684 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
685 dev->caps.port_mask[i] = dev->caps.port_type[i];
686 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
687 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
688 &dev->caps.gid_table_len[i],
689 &dev->caps.pkey_table_len[i]))
693 if (dev->caps.uar_page_size * (dev->caps.num_uars -
694 dev->caps.reserved_uars) >
695 pci_resource_len(dev->pdev, 2)) {
696 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
697 "PCI resource 2 size of 0x%llx, aborting.\n",
698 dev->caps.uar_page_size * dev->caps.num_uars,
699 (unsigned long long) pci_resource_len(dev->pdev, 2));
703 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
704 dev->caps.eqe_size = 64;
705 dev->caps.eqe_factor = 1;
707 dev->caps.eqe_size = 32;
708 dev->caps.eqe_factor = 0;
711 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
712 dev->caps.cqe_size = 64;
713 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
715 dev->caps.cqe_size = 32;
718 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
719 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
721 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
726 kfree(dev->caps.qp0_tunnel);
727 kfree(dev->caps.qp0_proxy);
728 kfree(dev->caps.qp1_tunnel);
729 kfree(dev->caps.qp1_proxy);
730 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
731 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
736 static void mlx4_request_modules(struct mlx4_dev *dev)
739 int has_ib_port = false;
740 int has_eth_port = false;
741 #define EN_DRV_NAME "mlx4_en"
742 #define IB_DRV_NAME "mlx4_ib"
744 for (port = 1; port <= dev->caps.num_ports; port++) {
745 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
747 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
752 request_module_nowait(IB_DRV_NAME);
754 request_module_nowait(EN_DRV_NAME);
758 * Change the port configuration of the device.
759 * Every user of this function must hold the port mutex.
761 int mlx4_change_port_types(struct mlx4_dev *dev,
762 enum mlx4_port_type *port_types)
768 for (port = 0; port < dev->caps.num_ports; port++) {
769 /* Change the port type only if the new type is different
770 * from the current, and not set to Auto */
771 if (port_types[port] != dev->caps.port_type[port + 1])
775 mlx4_unregister_device(dev);
776 for (port = 1; port <= dev->caps.num_ports; port++) {
777 mlx4_CLOSE_PORT(dev, port);
778 dev->caps.port_type[port] = port_types[port - 1];
779 err = mlx4_SET_PORT(dev, port, -1);
781 mlx4_err(dev, "Failed to set port %d, "
786 mlx4_set_port_mask(dev);
787 err = mlx4_register_device(dev);
789 mlx4_err(dev, "Failed to register device\n");
792 mlx4_request_modules(dev);
799 static ssize_t show_port_type(struct device *dev,
800 struct device_attribute *attr,
803 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
805 struct mlx4_dev *mdev = info->dev;
809 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
811 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
812 sprintf(buf, "auto (%s)\n", type);
814 sprintf(buf, "%s\n", type);
819 static ssize_t set_port_type(struct device *dev,
820 struct device_attribute *attr,
821 const char *buf, size_t count)
823 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
825 struct mlx4_dev *mdev = info->dev;
826 struct mlx4_priv *priv = mlx4_priv(mdev);
827 enum mlx4_port_type types[MLX4_MAX_PORTS];
828 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
832 if (!strcmp(buf, "ib\n"))
833 info->tmp_type = MLX4_PORT_TYPE_IB;
834 else if (!strcmp(buf, "eth\n"))
835 info->tmp_type = MLX4_PORT_TYPE_ETH;
836 else if (!strcmp(buf, "auto\n"))
837 info->tmp_type = MLX4_PORT_TYPE_AUTO;
839 mlx4_err(mdev, "%s is not supported port type\n", buf);
843 mlx4_stop_sense(mdev);
844 mutex_lock(&priv->port_mutex);
845 /* Possible type is always the one that was delivered */
846 mdev->caps.possible_type[info->port] = info->tmp_type;
848 for (i = 0; i < mdev->caps.num_ports; i++) {
849 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
850 mdev->caps.possible_type[i+1];
851 if (types[i] == MLX4_PORT_TYPE_AUTO)
852 types[i] = mdev->caps.port_type[i+1];
855 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
856 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
857 for (i = 1; i <= mdev->caps.num_ports; i++) {
858 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
859 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
865 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
866 "Set only 'eth' or 'ib' for both ports "
867 "(should be the same)\n");
871 mlx4_do_sense_ports(mdev, new_types, types);
873 err = mlx4_check_port_params(mdev, new_types);
877 /* We are about to apply the changes after the configuration
878 * was verified, no need to remember the temporary types
880 for (i = 0; i < mdev->caps.num_ports; i++)
881 priv->port[i + 1].tmp_type = 0;
883 err = mlx4_change_port_types(mdev, new_types);
886 mlx4_start_sense(mdev);
887 mutex_unlock(&priv->port_mutex);
888 return err ? err : count;
899 static inline int int_to_ibta_mtu(int mtu)
902 case 256: return IB_MTU_256;
903 case 512: return IB_MTU_512;
904 case 1024: return IB_MTU_1024;
905 case 2048: return IB_MTU_2048;
906 case 4096: return IB_MTU_4096;
911 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
914 case IB_MTU_256: return 256;
915 case IB_MTU_512: return 512;
916 case IB_MTU_1024: return 1024;
917 case IB_MTU_2048: return 2048;
918 case IB_MTU_4096: return 4096;
923 static ssize_t show_port_ib_mtu(struct device *dev,
924 struct device_attribute *attr,
927 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
929 struct mlx4_dev *mdev = info->dev;
931 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
932 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
935 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
939 static ssize_t set_port_ib_mtu(struct device *dev,
940 struct device_attribute *attr,
941 const char *buf, size_t count)
943 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
945 struct mlx4_dev *mdev = info->dev;
946 struct mlx4_priv *priv = mlx4_priv(mdev);
947 int err, port, mtu, ibta_mtu = -1;
949 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
950 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
954 err = kstrtoint(buf, 0, &mtu);
956 ibta_mtu = int_to_ibta_mtu(mtu);
958 if (err || ibta_mtu < 0) {
959 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
963 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
965 mlx4_stop_sense(mdev);
966 mutex_lock(&priv->port_mutex);
967 mlx4_unregister_device(mdev);
968 for (port = 1; port <= mdev->caps.num_ports; port++) {
969 mlx4_CLOSE_PORT(mdev, port);
970 err = mlx4_SET_PORT(mdev, port, -1);
972 mlx4_err(mdev, "Failed to set port %d, "
977 err = mlx4_register_device(mdev);
979 mutex_unlock(&priv->port_mutex);
980 mlx4_start_sense(mdev);
981 return err ? err : count;
984 static int mlx4_load_fw(struct mlx4_dev *dev)
986 struct mlx4_priv *priv = mlx4_priv(dev);
989 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
990 GFP_HIGHUSER | __GFP_NOWARN, 0);
991 if (!priv->fw.fw_icm) {
992 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
996 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
998 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1002 err = mlx4_RUN_FW(dev);
1004 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1014 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1018 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1021 struct mlx4_priv *priv = mlx4_priv(dev);
1025 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1027 ((u64) (MLX4_CMPT_TYPE_QP *
1028 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1029 cmpt_entry_sz, dev->caps.num_qps,
1030 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1035 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1037 ((u64) (MLX4_CMPT_TYPE_SRQ *
1038 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1039 cmpt_entry_sz, dev->caps.num_srqs,
1040 dev->caps.reserved_srqs, 0, 0);
1044 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1046 ((u64) (MLX4_CMPT_TYPE_CQ *
1047 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1048 cmpt_entry_sz, dev->caps.num_cqs,
1049 dev->caps.reserved_cqs, 0, 0);
1053 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1055 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1057 ((u64) (MLX4_CMPT_TYPE_EQ *
1058 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1059 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1066 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1069 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1072 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1078 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1079 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1081 struct mlx4_priv *priv = mlx4_priv(dev);
1086 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1088 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1092 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1093 (unsigned long long) icm_size >> 10,
1094 (unsigned long long) aux_pages << 2);
1096 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1097 GFP_HIGHUSER | __GFP_NOWARN, 0);
1098 if (!priv->fw.aux_icm) {
1099 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1103 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1105 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1109 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1111 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1116 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1118 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1119 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1120 num_eqs, num_eqs, 0, 0);
1122 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1123 goto err_unmap_cmpt;
1127 * Reserved MTT entries must be aligned up to a cacheline
1128 * boundary, since the FW will write to them, while the driver
1129 * writes to all other MTT entries. (The variable
1130 * dev->caps.mtt_entry_sz below is really the MTT segment
1131 * size, not the raw entry size)
1133 dev->caps.reserved_mtts =
1134 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1135 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1137 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1139 dev->caps.mtt_entry_sz,
1141 dev->caps.reserved_mtts, 1, 0);
1143 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1147 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1148 init_hca->dmpt_base,
1149 dev_cap->dmpt_entry_sz,
1151 dev->caps.reserved_mrws, 1, 1);
1153 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1157 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1159 dev_cap->qpc_entry_sz,
1161 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1164 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1165 goto err_unmap_dmpt;
1168 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1169 init_hca->auxc_base,
1170 dev_cap->aux_entry_sz,
1172 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1175 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1179 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1180 init_hca->altc_base,
1181 dev_cap->altc_entry_sz,
1183 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1186 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1187 goto err_unmap_auxc;
1190 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1191 init_hca->rdmarc_base,
1192 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1194 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1197 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1198 goto err_unmap_altc;
1201 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1203 dev_cap->cqc_entry_sz,
1205 dev->caps.reserved_cqs, 0, 0);
1207 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1208 goto err_unmap_rdmarc;
1211 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1212 init_hca->srqc_base,
1213 dev_cap->srq_entry_sz,
1215 dev->caps.reserved_srqs, 0, 0);
1217 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1222 * For flow steering device managed mode it is required to use
1223 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1224 * required, but for simplicity just map the whole multicast
1225 * group table now. The table isn't very big and it's a lot
1226 * easier than trying to track ref counts.
1228 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1230 mlx4_get_mgm_entry_size(dev),
1231 dev->caps.num_mgms + dev->caps.num_amgms,
1232 dev->caps.num_mgms + dev->caps.num_amgms,
1235 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1242 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1245 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1248 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1251 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1254 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1257 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1260 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1263 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1266 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1269 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1270 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1271 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1272 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1275 mlx4_UNMAP_ICM_AUX(dev);
1278 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1283 static void mlx4_free_icms(struct mlx4_dev *dev)
1285 struct mlx4_priv *priv = mlx4_priv(dev);
1287 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1288 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1289 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1290 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1291 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1292 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1293 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1294 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1295 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1296 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1297 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1298 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1299 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1300 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1302 mlx4_UNMAP_ICM_AUX(dev);
1303 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1306 static void mlx4_slave_exit(struct mlx4_dev *dev)
1308 struct mlx4_priv *priv = mlx4_priv(dev);
1310 mutex_lock(&priv->cmd.slave_cmd_mutex);
1311 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1312 mlx4_warn(dev, "Failed to close slave function.\n");
1313 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1316 static int map_bf_area(struct mlx4_dev *dev)
1318 struct mlx4_priv *priv = mlx4_priv(dev);
1319 resource_size_t bf_start;
1320 resource_size_t bf_len;
1323 if (!dev->caps.bf_reg_size)
1326 bf_start = pci_resource_start(dev->pdev, 2) +
1327 (dev->caps.num_uars << PAGE_SHIFT);
1328 bf_len = pci_resource_len(dev->pdev, 2) -
1329 (dev->caps.num_uars << PAGE_SHIFT);
1330 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1331 if (!priv->bf_mapping)
1337 static void unmap_bf_area(struct mlx4_dev *dev)
1339 if (mlx4_priv(dev)->bf_mapping)
1340 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1343 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1345 u32 clockhi, clocklo, clockhi1;
1348 struct mlx4_priv *priv = mlx4_priv(dev);
1350 for (i = 0; i < 10; i++) {
1351 clockhi = swab32(readl(priv->clock_mapping));
1352 clocklo = swab32(readl(priv->clock_mapping + 4));
1353 clockhi1 = swab32(readl(priv->clock_mapping));
1354 if (clockhi == clockhi1)
1358 cycles = (u64) clockhi << 32 | (u64) clocklo;
1362 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1365 static int map_internal_clock(struct mlx4_dev *dev)
1367 struct mlx4_priv *priv = mlx4_priv(dev);
1369 priv->clock_mapping =
1370 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1371 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1373 if (!priv->clock_mapping)
1379 static void unmap_internal_clock(struct mlx4_dev *dev)
1381 struct mlx4_priv *priv = mlx4_priv(dev);
1383 if (priv->clock_mapping)
1384 iounmap(priv->clock_mapping);
1387 static void mlx4_close_hca(struct mlx4_dev *dev)
1389 unmap_internal_clock(dev);
1391 if (mlx4_is_slave(dev))
1392 mlx4_slave_exit(dev);
1394 mlx4_CLOSE_HCA(dev, 0);
1395 mlx4_free_icms(dev);
1397 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1401 static int mlx4_init_slave(struct mlx4_dev *dev)
1403 struct mlx4_priv *priv = mlx4_priv(dev);
1404 u64 dma = (u64) priv->mfunc.vhcr_dma;
1405 int ret_from_reset = 0;
1407 u32 cmd_channel_ver;
1409 mutex_lock(&priv->cmd.slave_cmd_mutex);
1410 priv->cmd.max_cmds = 1;
1411 mlx4_warn(dev, "Sending reset\n");
1412 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1414 /* if we are in the middle of flr the slave will try
1415 * NUM_OF_RESET_RETRIES times before leaving.*/
1416 if (ret_from_reset) {
1417 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1418 mlx4_warn(dev, "slave is currently in the "
1419 "middle of FLR. Deferring probe.\n");
1420 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1421 return -EPROBE_DEFER;
1426 /* check the driver version - the slave I/F revision
1427 * must match the master's */
1428 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1429 cmd_channel_ver = mlx4_comm_get_version();
1431 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1432 MLX4_COMM_GET_IF_REV(slave_read)) {
1433 mlx4_err(dev, "slave driver version is not supported"
1434 " by the master\n");
1438 mlx4_warn(dev, "Sending vhcr0\n");
1439 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1442 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1445 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1448 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1455 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1456 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1460 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1464 for (i = 1; i <= dev->caps.num_ports; i++) {
1465 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1466 dev->caps.gid_table_len[i] =
1467 mlx4_get_slave_num_gids(dev, 0);
1469 dev->caps.gid_table_len[i] = 1;
1470 dev->caps.pkey_table_len[i] =
1471 dev->phys_caps.pkey_phys_table_len[i] - 1;
1475 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1477 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1479 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1481 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1485 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1488 static void choose_steering_mode(struct mlx4_dev *dev,
1489 struct mlx4_dev_cap *dev_cap)
1491 if (mlx4_log_num_mgm_entry_size == -1 &&
1492 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1493 (!mlx4_is_mfunc(dev) ||
1494 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1495 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1496 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1497 dev->oper_log_mgm_entry_size =
1498 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1499 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1500 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1501 dev->caps.fs_log_max_ucast_qp_range_size =
1502 dev_cap->fs_log_max_ucast_qp_range_size;
1504 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1505 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1506 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1508 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1510 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1511 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1512 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1513 "set to use B0 steering. Falling back to A0 steering mode.\n");
1515 dev->oper_log_mgm_entry_size =
1516 mlx4_log_num_mgm_entry_size > 0 ?
1517 mlx4_log_num_mgm_entry_size :
1518 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1519 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1521 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1522 "modparam log_num_mgm_entry_size = %d\n",
1523 mlx4_steering_mode_str(dev->caps.steering_mode),
1524 dev->oper_log_mgm_entry_size,
1525 mlx4_log_num_mgm_entry_size);
1528 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1529 struct mlx4_dev_cap *dev_cap)
1531 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1532 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1533 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1535 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1537 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1538 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1541 static int mlx4_init_hca(struct mlx4_dev *dev)
1543 struct mlx4_priv *priv = mlx4_priv(dev);
1544 struct mlx4_adapter adapter;
1545 struct mlx4_dev_cap dev_cap;
1546 struct mlx4_mod_stat_cfg mlx4_cfg;
1547 struct mlx4_profile profile;
1548 struct mlx4_init_hca_param init_hca;
1552 if (!mlx4_is_slave(dev)) {
1553 err = mlx4_QUERY_FW(dev);
1556 mlx4_info(dev, "non-primary physical function, skipping.\n");
1558 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1562 err = mlx4_load_fw(dev);
1564 mlx4_err(dev, "Failed to start FW, aborting.\n");
1568 mlx4_cfg.log_pg_sz_m = 1;
1569 mlx4_cfg.log_pg_sz = 0;
1570 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1572 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1574 err = mlx4_dev_cap(dev, &dev_cap);
1576 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1580 choose_steering_mode(dev, &dev_cap);
1581 choose_tunnel_offload_mode(dev, &dev_cap);
1583 err = mlx4_get_phys_port_id(dev);
1585 mlx4_err(dev, "Fail to get physical port id\n");
1587 if (mlx4_is_master(dev))
1588 mlx4_parav_master_pf_caps(dev);
1590 profile = default_profile;
1591 if (dev->caps.steering_mode ==
1592 MLX4_STEERING_MODE_DEVICE_MANAGED)
1593 profile.num_mcg = MLX4_FS_NUM_MCG;
1595 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1597 if ((long long) icm_size < 0) {
1602 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1604 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1605 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1606 init_hca.mw_enabled = 0;
1607 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1608 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1609 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1611 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1615 err = mlx4_INIT_HCA(dev, &init_hca);
1617 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1621 * If TS is supported by FW
1622 * read HCA frequency by QUERY_HCA command
1624 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1625 memset(&init_hca, 0, sizeof(init_hca));
1626 err = mlx4_QUERY_HCA(dev, &init_hca);
1628 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1629 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1631 dev->caps.hca_core_clock =
1632 init_hca.hca_core_clock;
1635 /* In case we got HCA frequency 0 - disable timestamping
1636 * to avoid dividing by zero
1638 if (!dev->caps.hca_core_clock) {
1639 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1641 "HCA frequency is 0. Timestamping is not supported.");
1642 } else if (map_internal_clock(dev)) {
1644 * Map internal clock,
1645 * in case of failure disable timestamping
1647 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1648 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1652 err = mlx4_init_slave(dev);
1654 if (err != -EPROBE_DEFER)
1655 mlx4_err(dev, "Failed to initialize slave\n");
1659 err = mlx4_slave_cap(dev);
1661 mlx4_err(dev, "Failed to obtain slave caps\n");
1666 if (map_bf_area(dev))
1667 mlx4_dbg(dev, "Failed to map blue flame area\n");
1669 /*Only the master set the ports, all the rest got it from it.*/
1670 if (!mlx4_is_slave(dev))
1671 mlx4_set_port_mask(dev);
1673 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1675 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
1679 priv->eq_table.inta_pin = adapter.inta_pin;
1680 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1685 unmap_internal_clock(dev);
1689 if (mlx4_is_slave(dev))
1690 mlx4_slave_exit(dev);
1692 mlx4_CLOSE_HCA(dev, 0);
1695 if (!mlx4_is_slave(dev))
1696 mlx4_free_icms(dev);
1699 if (!mlx4_is_slave(dev)) {
1701 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1706 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1708 struct mlx4_priv *priv = mlx4_priv(dev);
1711 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1714 nent = dev->caps.max_counters;
1715 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1718 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1720 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1723 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1725 struct mlx4_priv *priv = mlx4_priv(dev);
1727 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1730 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1737 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1742 if (mlx4_is_mfunc(dev)) {
1743 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1744 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1745 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1747 *idx = get_param_l(&out_param);
1751 return __mlx4_counter_alloc(dev, idx);
1753 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1755 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1757 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
1761 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1765 if (mlx4_is_mfunc(dev)) {
1766 set_param_l(&in_param, idx);
1767 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1768 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1772 __mlx4_counter_free(dev, idx);
1774 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1776 static int mlx4_setup_hca(struct mlx4_dev *dev)
1778 struct mlx4_priv *priv = mlx4_priv(dev);
1781 __be32 ib_port_default_caps;
1783 err = mlx4_init_uar_table(dev);
1785 mlx4_err(dev, "Failed to initialize "
1786 "user access region table, aborting.\n");
1790 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1792 mlx4_err(dev, "Failed to allocate driver access region, "
1794 goto err_uar_table_free;
1797 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1799 mlx4_err(dev, "Couldn't map kernel access region, "
1805 err = mlx4_init_pd_table(dev);
1807 mlx4_err(dev, "Failed to initialize "
1808 "protection domain table, aborting.\n");
1812 err = mlx4_init_xrcd_table(dev);
1814 mlx4_err(dev, "Failed to initialize "
1815 "reliable connection domain table, aborting.\n");
1816 goto err_pd_table_free;
1819 err = mlx4_init_mr_table(dev);
1821 mlx4_err(dev, "Failed to initialize "
1822 "memory region table, aborting.\n");
1823 goto err_xrcd_table_free;
1826 if (!mlx4_is_slave(dev)) {
1827 err = mlx4_init_mcg_table(dev);
1829 mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1830 goto err_mr_table_free;
1834 err = mlx4_init_eq_table(dev);
1836 mlx4_err(dev, "Failed to initialize "
1837 "event queue table, aborting.\n");
1838 goto err_mcg_table_free;
1841 err = mlx4_cmd_use_events(dev);
1843 mlx4_err(dev, "Failed to switch to event-driven "
1844 "firmware commands, aborting.\n");
1845 goto err_eq_table_free;
1848 err = mlx4_NOP(dev);
1850 if (dev->flags & MLX4_FLAG_MSI_X) {
1851 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1852 "interrupt IRQ %d).\n",
1853 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1854 mlx4_warn(dev, "Trying again without MSI-X.\n");
1856 mlx4_err(dev, "NOP command failed to generate interrupt "
1857 "(IRQ %d), aborting.\n",
1858 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1859 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1865 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1867 err = mlx4_init_cq_table(dev);
1869 mlx4_err(dev, "Failed to initialize "
1870 "completion queue table, aborting.\n");
1874 err = mlx4_init_srq_table(dev);
1876 mlx4_err(dev, "Failed to initialize "
1877 "shared receive queue table, aborting.\n");
1878 goto err_cq_table_free;
1881 err = mlx4_init_qp_table(dev);
1883 mlx4_err(dev, "Failed to initialize "
1884 "queue pair table, aborting.\n");
1885 goto err_srq_table_free;
1888 err = mlx4_init_counters_table(dev);
1889 if (err && err != -ENOENT) {
1890 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1891 goto err_qp_table_free;
1894 if (!mlx4_is_slave(dev)) {
1895 for (port = 1; port <= dev->caps.num_ports; port++) {
1896 ib_port_default_caps = 0;
1897 err = mlx4_get_port_ib_caps(dev, port,
1898 &ib_port_default_caps);
1900 mlx4_warn(dev, "failed to get port %d default "
1901 "ib capabilities (%d). Continuing "
1902 "with caps = 0\n", port, err);
1903 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1905 /* initialize per-slave default ib port capabilities */
1906 if (mlx4_is_master(dev)) {
1908 for (i = 0; i < dev->num_slaves; i++) {
1909 if (i == mlx4_master_func_num(dev))
1911 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1912 ib_port_default_caps;
1916 if (mlx4_is_mfunc(dev))
1917 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1919 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1921 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1922 dev->caps.pkey_table_len[port] : -1);
1924 mlx4_err(dev, "Failed to set port %d, aborting\n",
1926 goto err_counters_table_free;
1933 err_counters_table_free:
1934 mlx4_cleanup_counters_table(dev);
1937 mlx4_cleanup_qp_table(dev);
1940 mlx4_cleanup_srq_table(dev);
1943 mlx4_cleanup_cq_table(dev);
1946 mlx4_cmd_use_polling(dev);
1949 mlx4_cleanup_eq_table(dev);
1952 if (!mlx4_is_slave(dev))
1953 mlx4_cleanup_mcg_table(dev);
1956 mlx4_cleanup_mr_table(dev);
1958 err_xrcd_table_free:
1959 mlx4_cleanup_xrcd_table(dev);
1962 mlx4_cleanup_pd_table(dev);
1968 mlx4_uar_free(dev, &priv->driver_uar);
1971 mlx4_cleanup_uar_table(dev);
1975 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1977 struct mlx4_priv *priv = mlx4_priv(dev);
1978 struct msix_entry *entries;
1979 int nreq = min_t(int, dev->caps.num_ports *
1980 min_t(int, num_online_cpus() + 1,
1981 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
1985 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1988 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1992 for (i = 0; i < nreq; ++i)
1993 entries[i].entry = i;
1995 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2000 } else if (nreq < MSIX_LEGACY_SZ +
2001 dev->caps.num_ports * MIN_MSIX_P_PORT) {
2002 /*Working in legacy mode , all EQ's shared*/
2003 dev->caps.comp_pool = 0;
2004 dev->caps.num_comp_vectors = nreq - 1;
2006 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2007 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2009 for (i = 0; i < nreq; ++i)
2010 priv->eq_table.eq[i].irq = entries[i].vector;
2012 dev->flags |= MLX4_FLAG_MSI_X;
2019 dev->caps.num_comp_vectors = 1;
2020 dev->caps.comp_pool = 0;
2022 for (i = 0; i < 2; ++i)
2023 priv->eq_table.eq[i].irq = dev->pdev->irq;
2026 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2028 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2033 if (!mlx4_is_slave(dev)) {
2034 mlx4_init_mac_table(dev, &info->mac_table);
2035 mlx4_init_vlan_table(dev, &info->vlan_table);
2036 info->base_qpn = mlx4_get_base_qpn(dev, port);
2039 sprintf(info->dev_name, "mlx4_port%d", port);
2040 info->port_attr.attr.name = info->dev_name;
2041 if (mlx4_is_mfunc(dev))
2042 info->port_attr.attr.mode = S_IRUGO;
2044 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2045 info->port_attr.store = set_port_type;
2047 info->port_attr.show = show_port_type;
2048 sysfs_attr_init(&info->port_attr.attr);
2050 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2052 mlx4_err(dev, "Failed to create file for port %d\n", port);
2056 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2057 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2058 if (mlx4_is_mfunc(dev))
2059 info->port_mtu_attr.attr.mode = S_IRUGO;
2061 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2062 info->port_mtu_attr.store = set_port_ib_mtu;
2064 info->port_mtu_attr.show = show_port_ib_mtu;
2065 sysfs_attr_init(&info->port_mtu_attr.attr);
2067 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2069 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2070 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2077 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2082 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2083 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2086 static int mlx4_init_steering(struct mlx4_dev *dev)
2088 struct mlx4_priv *priv = mlx4_priv(dev);
2089 int num_entries = dev->caps.num_ports;
2092 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2096 for (i = 0; i < num_entries; i++)
2097 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2098 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2099 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2104 static void mlx4_clear_steering(struct mlx4_dev *dev)
2106 struct mlx4_priv *priv = mlx4_priv(dev);
2107 struct mlx4_steer_index *entry, *tmp_entry;
2108 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2109 int num_entries = dev->caps.num_ports;
2112 for (i = 0; i < num_entries; i++) {
2113 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2114 list_for_each_entry_safe(pqp, tmp_pqp,
2115 &priv->steer[i].promisc_qps[j],
2117 list_del(&pqp->list);
2120 list_for_each_entry_safe(entry, tmp_entry,
2121 &priv->steer[i].steer_entries[j],
2123 list_del(&entry->list);
2124 list_for_each_entry_safe(pqp, tmp_pqp,
2127 list_del(&pqp->list);
2137 static int extended_func_num(struct pci_dev *pdev)
2139 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2142 #define MLX4_OWNER_BASE 0x8069c
2143 #define MLX4_OWNER_SIZE 4
2145 static int mlx4_get_ownership(struct mlx4_dev *dev)
2147 void __iomem *owner;
2150 if (pci_channel_offline(dev->pdev))
2153 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2156 mlx4_err(dev, "Failed to obtain ownership bit\n");
2165 static void mlx4_free_ownership(struct mlx4_dev *dev)
2167 void __iomem *owner;
2169 if (pci_channel_offline(dev->pdev))
2172 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2175 mlx4_err(dev, "Failed to obtain ownership bit\n");
2183 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
2185 struct mlx4_priv *priv;
2186 struct mlx4_dev *dev;
2190 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2192 err = pci_enable_device(pdev);
2194 dev_err(&pdev->dev, "Cannot enable PCI device, "
2199 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2200 * per port, we must limit the number of VFs to 63 (since their are
2203 if (num_vfs >= MLX4_MAX_NUM_VF) {
2205 "Requested more VF's (%d) than allowed (%d)\n",
2206 num_vfs, MLX4_MAX_NUM_VF - 1);
2211 pr_err("num_vfs module parameter cannot be negative\n");
2217 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2218 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2219 dev_err(&pdev->dev, "Missing DCS, aborting."
2220 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2221 pci_dev_data, pci_resource_flags(pdev, 0));
2223 goto err_disable_pdev;
2225 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2226 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2228 goto err_disable_pdev;
2231 err = pci_request_regions(pdev, DRV_NAME);
2233 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2234 goto err_disable_pdev;
2237 pci_set_master(pdev);
2239 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2241 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2244 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
2245 goto err_release_regions;
2248 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2250 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2251 "consistent PCI DMA mask.\n");
2252 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2254 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2256 goto err_release_regions;
2260 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2261 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2263 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2266 goto err_release_regions;
2271 INIT_LIST_HEAD(&priv->ctx_list);
2272 spin_lock_init(&priv->ctx_lock);
2274 mutex_init(&priv->port_mutex);
2276 INIT_LIST_HEAD(&priv->pgdir_list);
2277 mutex_init(&priv->pgdir_mutex);
2279 INIT_LIST_HEAD(&priv->bf_list);
2280 mutex_init(&priv->bf_mutex);
2282 dev->rev_id = pdev->revision;
2283 dev->numa_node = dev_to_node(&pdev->dev);
2284 /* Detect if this device is a virtual function */
2285 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2286 /* When acting as pf, we normally skip vfs unless explicitly
2287 * requested to probe them. */
2288 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2289 mlx4_warn(dev, "Skipping virtual function:%d\n",
2290 extended_func_num(pdev));
2294 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2295 dev->flags |= MLX4_FLAG_SLAVE;
2297 /* We reset the device and enable SRIOV only for physical
2298 * devices. Try to claim ownership on the device;
2299 * if already taken, skip -- do not allow multiple PFs */
2300 err = mlx4_get_ownership(dev);
2305 mlx4_warn(dev, "Multiple PFs not yet supported."
2313 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
2314 err = pci_enable_sriov(pdev, num_vfs);
2316 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2320 mlx4_warn(dev, "Running in master mode\n");
2321 dev->flags |= MLX4_FLAG_SRIOV |
2323 dev->num_vfs = num_vfs;
2327 atomic_set(&priv->opreq_count, 0);
2328 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2331 * Now reset the HCA before we touch the PCI capabilities or
2332 * attempt a firmware command, since a boot ROM may have left
2333 * the HCA in an undefined state.
2335 err = mlx4_reset(dev);
2337 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2343 err = mlx4_cmd_init(dev);
2345 mlx4_err(dev, "Failed to init command interface, aborting.\n");
2349 /* In slave functions, the communication channel must be initialized
2350 * before posting commands. Also, init num_slaves before calling
2352 if (mlx4_is_mfunc(dev)) {
2353 if (mlx4_is_master(dev))
2354 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2356 dev->num_slaves = 0;
2357 err = mlx4_multi_func_init(dev);
2359 mlx4_err(dev, "Failed to init slave mfunc"
2360 " interface, aborting.\n");
2366 err = mlx4_init_hca(dev);
2368 if (err == -EACCES) {
2369 /* Not primary Physical function
2370 * Running in slave mode */
2371 mlx4_cmd_cleanup(dev);
2372 dev->flags |= MLX4_FLAG_SLAVE;
2373 dev->flags &= ~MLX4_FLAG_MASTER;
2379 /* check if the device is functioning at its maximum possible speed.
2380 * No return code for this call, just warn the user in case of PCI
2381 * express device capabilities are under-satisfied by the bus.
2383 mlx4_check_pcie_caps(dev);
2385 /* In master functions, the communication channel must be initialized
2386 * after obtaining its address from fw */
2387 if (mlx4_is_master(dev)) {
2388 err = mlx4_multi_func_init(dev);
2390 mlx4_err(dev, "Failed to init master mfunc"
2391 "interface, aborting.\n");
2396 err = mlx4_alloc_eq_table(dev);
2398 goto err_master_mfunc;
2400 priv->msix_ctl.pool_bm = 0;
2401 mutex_init(&priv->msix_ctl.pool_lock);
2403 mlx4_enable_msi_x(dev);
2404 if ((mlx4_is_mfunc(dev)) &&
2405 !(dev->flags & MLX4_FLAG_MSI_X)) {
2407 mlx4_err(dev, "INTx is not supported in multi-function mode."
2412 if (!mlx4_is_slave(dev)) {
2413 err = mlx4_init_steering(dev);
2418 err = mlx4_setup_hca(dev);
2419 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2420 !mlx4_is_mfunc(dev)) {
2421 dev->flags &= ~MLX4_FLAG_MSI_X;
2422 dev->caps.num_comp_vectors = 1;
2423 dev->caps.comp_pool = 0;
2424 pci_disable_msix(pdev);
2425 err = mlx4_setup_hca(dev);
2431 mlx4_init_quotas(dev);
2433 for (port = 1; port <= dev->caps.num_ports; port++) {
2434 err = mlx4_init_port_info(dev, port);
2439 err = mlx4_register_device(dev);
2443 mlx4_request_modules(dev);
2445 mlx4_sense_init(dev);
2446 mlx4_start_sense(dev);
2448 priv->pci_dev_data = pci_dev_data;
2449 pci_set_drvdata(pdev, dev);
2454 for (--port; port >= 1; --port)
2455 mlx4_cleanup_port_info(&priv->port[port]);
2457 mlx4_cleanup_counters_table(dev);
2458 mlx4_cleanup_qp_table(dev);
2459 mlx4_cleanup_srq_table(dev);
2460 mlx4_cleanup_cq_table(dev);
2461 mlx4_cmd_use_polling(dev);
2462 mlx4_cleanup_eq_table(dev);
2463 mlx4_cleanup_mcg_table(dev);
2464 mlx4_cleanup_mr_table(dev);
2465 mlx4_cleanup_xrcd_table(dev);
2466 mlx4_cleanup_pd_table(dev);
2467 mlx4_cleanup_uar_table(dev);
2470 if (!mlx4_is_slave(dev))
2471 mlx4_clear_steering(dev);
2474 mlx4_free_eq_table(dev);
2477 if (mlx4_is_master(dev))
2478 mlx4_multi_func_cleanup(dev);
2481 if (dev->flags & MLX4_FLAG_MSI_X)
2482 pci_disable_msix(pdev);
2484 mlx4_close_hca(dev);
2487 if (mlx4_is_slave(dev))
2488 mlx4_multi_func_cleanup(dev);
2491 mlx4_cmd_cleanup(dev);
2494 if (dev->flags & MLX4_FLAG_SRIOV)
2495 pci_disable_sriov(pdev);
2498 if (!mlx4_is_slave(dev))
2499 mlx4_free_ownership(dev);
2504 err_release_regions:
2505 pci_release_regions(pdev);
2508 pci_disable_device(pdev);
2509 pci_set_drvdata(pdev, NULL);
2513 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2515 printk_once(KERN_INFO "%s", mlx4_version);
2517 return __mlx4_init_one(pdev, id->driver_data);
2520 static void mlx4_remove_one(struct pci_dev *pdev)
2522 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2523 struct mlx4_priv *priv = mlx4_priv(dev);
2527 /* in SRIOV it is not allowed to unload the pf's
2528 * driver while there are alive vf's */
2529 if (mlx4_is_master(dev)) {
2530 if (mlx4_how_many_lives_vf(dev))
2531 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2533 mlx4_stop_sense(dev);
2534 mlx4_unregister_device(dev);
2536 for (p = 1; p <= dev->caps.num_ports; p++) {
2537 mlx4_cleanup_port_info(&priv->port[p]);
2538 mlx4_CLOSE_PORT(dev, p);
2541 if (mlx4_is_master(dev))
2542 mlx4_free_resource_tracker(dev,
2543 RES_TR_FREE_SLAVES_ONLY);
2545 mlx4_cleanup_counters_table(dev);
2546 mlx4_cleanup_qp_table(dev);
2547 mlx4_cleanup_srq_table(dev);
2548 mlx4_cleanup_cq_table(dev);
2549 mlx4_cmd_use_polling(dev);
2550 mlx4_cleanup_eq_table(dev);
2551 mlx4_cleanup_mcg_table(dev);
2552 mlx4_cleanup_mr_table(dev);
2553 mlx4_cleanup_xrcd_table(dev);
2554 mlx4_cleanup_pd_table(dev);
2556 if (mlx4_is_master(dev))
2557 mlx4_free_resource_tracker(dev,
2558 RES_TR_FREE_STRUCTS_ONLY);
2561 mlx4_uar_free(dev, &priv->driver_uar);
2562 mlx4_cleanup_uar_table(dev);
2563 if (!mlx4_is_slave(dev))
2564 mlx4_clear_steering(dev);
2565 mlx4_free_eq_table(dev);
2566 if (mlx4_is_master(dev))
2567 mlx4_multi_func_cleanup(dev);
2568 mlx4_close_hca(dev);
2569 if (mlx4_is_slave(dev))
2570 mlx4_multi_func_cleanup(dev);
2571 mlx4_cmd_cleanup(dev);
2573 if (dev->flags & MLX4_FLAG_MSI_X)
2574 pci_disable_msix(pdev);
2575 if (dev->flags & MLX4_FLAG_SRIOV) {
2576 mlx4_warn(dev, "Disabling SR-IOV\n");
2577 pci_disable_sriov(pdev);
2580 if (!mlx4_is_slave(dev))
2581 mlx4_free_ownership(dev);
2583 kfree(dev->caps.qp0_tunnel);
2584 kfree(dev->caps.qp0_proxy);
2585 kfree(dev->caps.qp1_tunnel);
2586 kfree(dev->caps.qp1_proxy);
2589 pci_release_regions(pdev);
2590 pci_disable_device(pdev);
2591 pci_set_drvdata(pdev, NULL);
2595 int mlx4_restart_one(struct pci_dev *pdev)
2597 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2598 struct mlx4_priv *priv = mlx4_priv(dev);
2601 pci_dev_data = priv->pci_dev_data;
2602 mlx4_remove_one(pdev);
2603 return __mlx4_init_one(pdev, pci_dev_data);
2606 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
2607 /* MT25408 "Hermon" SDR */
2608 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2609 /* MT25408 "Hermon" DDR */
2610 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2611 /* MT25408 "Hermon" QDR */
2612 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2613 /* MT25408 "Hermon" DDR PCIe gen2 */
2614 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2615 /* MT25408 "Hermon" QDR PCIe gen2 */
2616 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2617 /* MT25408 "Hermon" EN 10GigE */
2618 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2619 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2620 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2621 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2622 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2623 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2624 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2625 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2626 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2627 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2628 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2629 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2630 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2631 /* MT25400 Family [ConnectX-2 Virtual Function] */
2632 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2633 /* MT27500 Family [ConnectX-3] */
2634 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2635 /* MT27500 Family [ConnectX-3 Virtual Function] */
2636 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2637 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2638 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2639 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2640 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2641 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2642 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2643 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2644 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2645 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2646 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2647 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2648 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2652 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2654 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2655 pci_channel_state_t state)
2657 mlx4_remove_one(pdev);
2659 return state == pci_channel_io_perm_failure ?
2660 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2663 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2665 int ret = __mlx4_init_one(pdev, 0);
2667 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2670 static const struct pci_error_handlers mlx4_err_handler = {
2671 .error_detected = mlx4_pci_err_detected,
2672 .slot_reset = mlx4_pci_slot_reset,
2675 static struct pci_driver mlx4_driver = {
2677 .id_table = mlx4_pci_table,
2678 .probe = mlx4_init_one,
2679 .remove = mlx4_remove_one,
2680 .err_handler = &mlx4_err_handler,
2683 static int __init mlx4_verify_params(void)
2685 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2686 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
2690 if (log_num_vlan != 0)
2691 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2692 MLX4_LOG_NUM_VLANS);
2694 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2695 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
2699 /* Check if module param for ports type has legal combination */
2700 if (port_type_array[0] == false && port_type_array[1] == true) {
2701 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2702 port_type_array[0] = true;
2705 if (mlx4_log_num_mgm_entry_size != -1 &&
2706 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2707 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2708 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2709 "in legal range (-1 or %d..%d)\n",
2710 mlx4_log_num_mgm_entry_size,
2711 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2712 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2719 static int __init mlx4_init(void)
2723 if (mlx4_verify_params())
2728 mlx4_wq = create_singlethread_workqueue("mlx4");
2732 ret = pci_register_driver(&mlx4_driver);
2734 destroy_workqueue(mlx4_wq);
2735 return ret < 0 ? ret : 0;
2738 static void __exit mlx4_cleanup(void)
2740 pci_unregister_driver(&mlx4_driver);
2741 destroy_workqueue(mlx4_wq);
2744 module_init(mlx4_init);
2745 module_exit(mlx4_cleanup);