2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
58 struct workqueue_struct *mlx4_wq;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs[3] = {0, 0, 0};
81 static int num_vfs_argc;
82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf[3] = {0, 0, 0};
87 static int probe_vfs_argc;
88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
93 module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe = true;
103 module_param(enable_64b_cqe_eqe, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
109 MLX4_FUNC_CAP_DMFS_A0_STATIC)
111 static char mlx4_version[] =
112 DRV_NAME ": Mellanox ConnectX core driver v"
113 DRV_VERSION " (" DRV_RELDATE ")\n";
115 static struct mlx4_profile default_profile = {
118 .rdmarc_per_qp = 1 << 4,
122 .num_mtt = 1 << 20, /* It is really num mtt segements */
125 static struct mlx4_profile low_mem_profile = {
128 .rdmarc_per_qp = 1 << 4,
135 static int log_num_mac = 7;
136 module_param_named(log_num_mac, log_num_mac, int, 0444);
137 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
139 static int log_num_vlan;
140 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
141 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
142 /* Log2 max number of VLANs per ETH port (0-7) */
143 #define MLX4_LOG_NUM_VLANS 7
144 #define MLX4_MIN_LOG_NUM_VLANS 0
145 #define MLX4_MIN_LOG_NUM_MAC 1
147 static bool use_prio;
148 module_param_named(use_prio, use_prio, bool, 0444);
149 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
151 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
152 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
153 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
155 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
156 static int arr_argc = 2;
157 module_param_array(port_type_array, int, &arr_argc, 0444);
158 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
159 "1 for IB, 2 for Ethernet");
161 struct mlx4_port_config {
162 struct list_head list;
163 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
164 struct pci_dev *pdev;
167 static atomic_t pf_loading = ATOMIC_INIT(0);
169 int mlx4_check_port_params(struct mlx4_dev *dev,
170 enum mlx4_port_type *port_type)
174 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
175 for (i = 0; i < dev->caps.num_ports - 1; i++) {
176 if (port_type[i] != port_type[i + 1]) {
177 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
183 for (i = 0; i < dev->caps.num_ports; i++) {
184 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
185 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
193 static void mlx4_set_port_mask(struct mlx4_dev *dev)
197 for (i = 1; i <= dev->caps.num_ports; ++i)
198 dev->caps.port_mask[i] = dev->caps.port_type[i];
202 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
205 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
208 struct mlx4_func func;
210 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
211 err = mlx4_QUERY_FUNC(dev, &func, 0);
213 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
216 dev_cap->max_eqs = func.max_eq;
217 dev_cap->reserved_eqs = func.rsvd_eqs;
218 dev_cap->reserved_uars = func.rsvd_uars;
219 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
224 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
226 struct mlx4_caps *dev_cap = &dev->caps;
228 /* FW not supporting or cancelled by user */
229 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
230 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
233 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
234 * When FW has NCSI it may decide not to report 64B CQE/EQEs
236 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
237 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
238 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
239 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
243 if (cache_line_size() == 128 || cache_line_size() == 256) {
244 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
245 /* Changing the real data inside CQE size to 32B */
246 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
247 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
249 if (mlx4_is_master(dev))
250 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
252 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
253 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
254 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
258 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
259 struct mlx4_port_cap *port_cap)
261 dev->caps.vl_cap[port] = port_cap->max_vl;
262 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
263 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
264 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
265 /* set gid and pkey table operating lengths by default
266 * to non-sriov values
268 dev->caps.gid_table_len[port] = port_cap->max_gids;
269 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
270 dev->caps.port_width_cap[port] = port_cap->max_port_width;
271 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
272 dev->caps.def_mac[port] = port_cap->def_mac;
273 dev->caps.supported_type[port] = port_cap->supported_port_types;
274 dev->caps.suggested_type[port] = port_cap->suggested_type;
275 dev->caps.default_sense[port] = port_cap->default_sense;
276 dev->caps.trans_type[port] = port_cap->trans_type;
277 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
278 dev->caps.wavelength[port] = port_cap->wavelength;
279 dev->caps.trans_code[port] = port_cap->trans_code;
284 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
285 struct mlx4_port_cap *port_cap)
289 err = mlx4_QUERY_PORT(dev, port, port_cap);
292 mlx4_err(dev, "QUERY_PORT command failed.\n");
297 #define MLX4_A0_STEERING_TABLE_SIZE 256
298 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
303 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
305 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
308 mlx4_dev_cap_dump(dev, dev_cap);
310 if (dev_cap->min_page_sz > PAGE_SIZE) {
311 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
312 dev_cap->min_page_sz, PAGE_SIZE);
315 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
316 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
317 dev_cap->num_ports, MLX4_MAX_PORTS);
321 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
322 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
325 pci_resource_len(dev->persist->pdev, 2));
329 dev->caps.num_ports = dev_cap->num_ports;
330 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
331 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
332 dev->caps.num_sys_eqs :
334 for (i = 1; i <= dev->caps.num_ports; ++i) {
335 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
337 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
342 dev->caps.uar_page_size = PAGE_SIZE;
343 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
344 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
345 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
346 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
347 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
348 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
349 dev->caps.max_wqes = dev_cap->max_qp_sz;
350 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
351 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
352 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
353 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
354 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
355 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
357 * Subtract 1 from the limit because we need to allocate a
358 * spare CQE so the HCA HW can tell the difference between an
359 * empty CQ and a full CQ.
361 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
362 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
363 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
364 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
365 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
367 /* The first 128 UARs are used for EQ doorbells */
368 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
369 dev->caps.reserved_pds = dev_cap->reserved_pds;
370 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
371 dev_cap->reserved_xrcds : 0;
372 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
373 dev_cap->max_xrcds : 0;
374 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
376 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
377 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
378 dev->caps.flags = dev_cap->flags;
379 dev->caps.flags2 = dev_cap->flags2;
380 dev->caps.bmme_flags = dev_cap->bmme_flags;
381 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
382 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
383 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
384 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
386 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
387 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
388 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
389 /* Don't do sense port on multifunction devices (for now at least) */
390 if (mlx4_is_mfunc(dev))
391 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
393 if (mlx4_low_memory_profile()) {
394 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
395 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
397 dev->caps.log_num_macs = log_num_mac;
398 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
401 for (i = 1; i <= dev->caps.num_ports; ++i) {
402 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
403 if (dev->caps.supported_type[i]) {
404 /* if only ETH is supported - assign ETH */
405 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
406 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
407 /* if only IB is supported, assign IB */
408 else if (dev->caps.supported_type[i] ==
410 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
412 /* if IB and ETH are supported, we set the port
413 * type according to user selection of port type;
414 * if user selected none, take the FW hint */
415 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
416 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
417 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
419 dev->caps.port_type[i] = port_type_array[i - 1];
423 * Link sensing is allowed on the port if 3 conditions are true:
424 * 1. Both protocols are supported on the port.
425 * 2. Different types are supported on the port
426 * 3. FW declared that it supports link sensing
428 mlx4_priv(dev)->sense.sense_allowed[i] =
429 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
430 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
431 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
434 * If "default_sense" bit is set, we move the port to "AUTO" mode
435 * and perform sense_port FW command to try and set the correct
436 * port type from beginning
438 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
439 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
440 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
441 mlx4_SENSE_PORT(dev, i, &sensed_port);
442 if (sensed_port != MLX4_PORT_TYPE_NONE)
443 dev->caps.port_type[i] = sensed_port;
445 dev->caps.possible_type[i] = dev->caps.port_type[i];
448 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
449 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
450 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
451 i, 1 << dev->caps.log_num_macs);
453 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
454 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
455 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
456 i, 1 << dev->caps.log_num_vlans);
460 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
462 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
463 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
464 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
465 (1 << dev->caps.log_num_macs) *
466 (1 << dev->caps.log_num_vlans) *
468 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
470 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
471 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
472 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
474 dev->caps.dmfs_high_rate_qpn_base =
475 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
477 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
478 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
479 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
480 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
481 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
483 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
484 dev->caps.dmfs_high_rate_qpn_base =
485 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
486 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
489 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
490 dev->caps.dmfs_high_rate_qpn_range;
492 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
493 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
494 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
495 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
497 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
499 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
501 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
502 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
503 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
504 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
507 if (dev_cap->flags2 &
508 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
509 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
510 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
511 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
512 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
516 if ((dev->caps.flags &
517 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
519 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
521 if (!mlx4_is_slave(dev)) {
522 mlx4_enable_cqe_eqe_stride(dev);
523 dev->caps.alloc_res_qp_mask =
524 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
527 dev->caps.alloc_res_qp_mask = 0;
533 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
534 enum pci_bus_speed *speed,
535 enum pcie_link_width *width)
537 u32 lnkcap1, lnkcap2;
540 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
542 *speed = PCI_SPEED_UNKNOWN;
543 *width = PCIE_LNK_WIDTH_UNKNOWN;
545 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
547 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
549 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
550 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
551 *speed = PCIE_SPEED_8_0GT;
552 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
553 *speed = PCIE_SPEED_5_0GT;
554 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
555 *speed = PCIE_SPEED_2_5GT;
558 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
559 if (!lnkcap2) { /* pre-r3.0 */
560 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
561 *speed = PCIE_SPEED_5_0GT;
562 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
563 *speed = PCIE_SPEED_2_5GT;
567 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
569 err2 ? err2 : -EINVAL;
574 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
576 enum pcie_link_width width, width_cap;
577 enum pci_bus_speed speed, speed_cap;
580 #define PCIE_SPEED_STR(speed) \
581 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
582 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
583 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
586 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
589 "Unable to determine PCIe device BW capabilities\n");
593 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
594 if (err || speed == PCI_SPEED_UNKNOWN ||
595 width == PCIE_LNK_WIDTH_UNKNOWN) {
597 "Unable to determine PCI device chain minimum BW\n");
601 if (width != width_cap || speed != speed_cap)
603 "PCIe BW is different than device's capability\n");
605 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
606 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
607 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
612 /*The function checks if there are live vf, return the num of them*/
613 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
615 struct mlx4_priv *priv = mlx4_priv(dev);
616 struct mlx4_slave_state *s_state;
620 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
621 s_state = &priv->mfunc.master.slave_state[i];
622 if (s_state->active && s_state->last_cmd !=
623 MLX4_COMM_CMD_RESET) {
624 mlx4_warn(dev, "%s: slave: %d is still active\n",
632 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
634 u32 qk = MLX4_RESERVED_QKEY_BASE;
636 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
637 qpn < dev->phys_caps.base_proxy_sqpn)
640 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
642 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
644 qk += qpn - dev->phys_caps.base_proxy_sqpn;
648 EXPORT_SYMBOL(mlx4_get_parav_qkey);
650 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
652 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
654 if (!mlx4_is_master(dev))
657 priv->virt2phys_pkey[slave][port - 1][i] = val;
659 EXPORT_SYMBOL(mlx4_sync_pkey_table);
661 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
663 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
665 if (!mlx4_is_master(dev))
668 priv->slave_node_guids[slave] = guid;
670 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
672 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
674 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
676 if (!mlx4_is_master(dev))
679 return priv->slave_node_guids[slave];
681 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
683 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
685 struct mlx4_priv *priv = mlx4_priv(dev);
686 struct mlx4_slave_state *s_slave;
688 if (!mlx4_is_master(dev))
691 s_slave = &priv->mfunc.master.slave_state[slave];
692 return !!s_slave->active;
694 EXPORT_SYMBOL(mlx4_is_slave_active);
696 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
697 struct mlx4_dev_cap *dev_cap,
698 struct mlx4_init_hca_param *hca_param)
700 dev->caps.steering_mode = hca_param->steering_mode;
701 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
702 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
703 dev->caps.fs_log_max_ucast_qp_range_size =
704 dev_cap->fs_log_max_ucast_qp_range_size;
706 dev->caps.num_qp_per_mgm =
707 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
709 mlx4_dbg(dev, "Steering mode is: %s\n",
710 mlx4_steering_mode_str(dev->caps.steering_mode));
713 static int mlx4_slave_cap(struct mlx4_dev *dev)
717 struct mlx4_dev_cap dev_cap;
718 struct mlx4_func_cap func_cap;
719 struct mlx4_init_hca_param hca_param;
722 memset(&hca_param, 0, sizeof(hca_param));
723 err = mlx4_QUERY_HCA(dev, &hca_param);
725 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
729 /* fail if the hca has an unknown global capability
730 * at this time global_caps should be always zeroed
732 if (hca_param.global_caps) {
733 mlx4_err(dev, "Unknown hca global capabilities\n");
737 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
739 dev->caps.hca_core_clock = hca_param.hca_core_clock;
741 memset(&dev_cap, 0, sizeof(dev_cap));
742 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
743 err = mlx4_dev_cap(dev, &dev_cap);
745 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
749 err = mlx4_QUERY_FW(dev);
751 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
753 page_size = ~dev->caps.page_size_cap + 1;
754 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
755 if (page_size > PAGE_SIZE) {
756 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
757 page_size, PAGE_SIZE);
761 /* slave gets uar page size from QUERY_HCA fw command */
762 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
764 /* TODO: relax this assumption */
765 if (dev->caps.uar_page_size != PAGE_SIZE) {
766 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
767 dev->caps.uar_page_size, PAGE_SIZE);
771 memset(&func_cap, 0, sizeof(func_cap));
772 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
774 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
779 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
780 PF_CONTEXT_BEHAVIOUR_MASK) {
781 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
782 func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
786 dev->caps.num_ports = func_cap.num_ports;
787 dev->quotas.qp = func_cap.qp_quota;
788 dev->quotas.srq = func_cap.srq_quota;
789 dev->quotas.cq = func_cap.cq_quota;
790 dev->quotas.mpt = func_cap.mpt_quota;
791 dev->quotas.mtt = func_cap.mtt_quota;
792 dev->caps.num_qps = 1 << hca_param.log_num_qps;
793 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
794 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
795 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
796 dev->caps.num_eqs = func_cap.max_eq;
797 dev->caps.reserved_eqs = func_cap.reserved_eq;
798 dev->caps.num_pds = MLX4_NUM_PDS;
799 dev->caps.num_mgms = 0;
800 dev->caps.num_amgms = 0;
802 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
803 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
804 dev->caps.num_ports, MLX4_MAX_PORTS);
808 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
809 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
810 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
811 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
812 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
814 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
815 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
816 !dev->caps.qp0_qkey) {
821 for (i = 1; i <= dev->caps.num_ports; ++i) {
822 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
824 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
828 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
829 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
830 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
831 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
832 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
833 dev->caps.port_mask[i] = dev->caps.port_type[i];
834 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
835 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
836 &dev->caps.gid_table_len[i],
837 &dev->caps.pkey_table_len[i]))
841 if (dev->caps.uar_page_size * (dev->caps.num_uars -
842 dev->caps.reserved_uars) >
843 pci_resource_len(dev->persist->pdev,
845 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
846 dev->caps.uar_page_size * dev->caps.num_uars,
848 pci_resource_len(dev->persist->pdev, 2));
852 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
853 dev->caps.eqe_size = 64;
854 dev->caps.eqe_factor = 1;
856 dev->caps.eqe_size = 32;
857 dev->caps.eqe_factor = 0;
860 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
861 dev->caps.cqe_size = 64;
862 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
864 dev->caps.cqe_size = 32;
867 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
868 dev->caps.eqe_size = hca_param.eqe_size;
869 dev->caps.eqe_factor = 0;
872 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
873 dev->caps.cqe_size = hca_param.cqe_size;
874 /* User still need to know when CQE > 32B */
875 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
878 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
879 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
881 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
883 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
884 dev->caps.bf_reg_size)
885 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
887 if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
888 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
893 kfree(dev->caps.qp0_qkey);
894 kfree(dev->caps.qp0_tunnel);
895 kfree(dev->caps.qp0_proxy);
896 kfree(dev->caps.qp1_tunnel);
897 kfree(dev->caps.qp1_proxy);
898 dev->caps.qp0_qkey = NULL;
899 dev->caps.qp0_tunnel = NULL;
900 dev->caps.qp0_proxy = NULL;
901 dev->caps.qp1_tunnel = NULL;
902 dev->caps.qp1_proxy = NULL;
907 static void mlx4_request_modules(struct mlx4_dev *dev)
910 int has_ib_port = false;
911 int has_eth_port = false;
912 #define EN_DRV_NAME "mlx4_en"
913 #define IB_DRV_NAME "mlx4_ib"
915 for (port = 1; port <= dev->caps.num_ports; port++) {
916 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
918 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
923 request_module_nowait(EN_DRV_NAME);
924 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
925 request_module_nowait(IB_DRV_NAME);
929 * Change the port configuration of the device.
930 * Every user of this function must hold the port mutex.
932 int mlx4_change_port_types(struct mlx4_dev *dev,
933 enum mlx4_port_type *port_types)
939 for (port = 0; port < dev->caps.num_ports; port++) {
940 /* Change the port type only if the new type is different
941 * from the current, and not set to Auto */
942 if (port_types[port] != dev->caps.port_type[port + 1])
946 mlx4_unregister_device(dev);
947 for (port = 1; port <= dev->caps.num_ports; port++) {
948 mlx4_CLOSE_PORT(dev, port);
949 dev->caps.port_type[port] = port_types[port - 1];
950 err = mlx4_SET_PORT(dev, port, -1);
952 mlx4_err(dev, "Failed to set port %d, aborting\n",
957 mlx4_set_port_mask(dev);
958 err = mlx4_register_device(dev);
960 mlx4_err(dev, "Failed to register device\n");
963 mlx4_request_modules(dev);
970 static ssize_t show_port_type(struct device *dev,
971 struct device_attribute *attr,
974 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
976 struct mlx4_dev *mdev = info->dev;
980 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
982 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
983 sprintf(buf, "auto (%s)\n", type);
985 sprintf(buf, "%s\n", type);
990 static ssize_t set_port_type(struct device *dev,
991 struct device_attribute *attr,
992 const char *buf, size_t count)
994 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
996 struct mlx4_dev *mdev = info->dev;
997 struct mlx4_priv *priv = mlx4_priv(mdev);
998 enum mlx4_port_type types[MLX4_MAX_PORTS];
999 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1000 static DEFINE_MUTEX(set_port_type_mutex);
1004 mutex_lock(&set_port_type_mutex);
1006 if (!strcmp(buf, "ib\n"))
1007 info->tmp_type = MLX4_PORT_TYPE_IB;
1008 else if (!strcmp(buf, "eth\n"))
1009 info->tmp_type = MLX4_PORT_TYPE_ETH;
1010 else if (!strcmp(buf, "auto\n"))
1011 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1013 mlx4_err(mdev, "%s is not supported port type\n", buf);
1018 mlx4_stop_sense(mdev);
1019 mutex_lock(&priv->port_mutex);
1020 /* Possible type is always the one that was delivered */
1021 mdev->caps.possible_type[info->port] = info->tmp_type;
1023 for (i = 0; i < mdev->caps.num_ports; i++) {
1024 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1025 mdev->caps.possible_type[i+1];
1026 if (types[i] == MLX4_PORT_TYPE_AUTO)
1027 types[i] = mdev->caps.port_type[i+1];
1030 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1031 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1032 for (i = 1; i <= mdev->caps.num_ports; i++) {
1033 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1034 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1040 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1044 mlx4_do_sense_ports(mdev, new_types, types);
1046 err = mlx4_check_port_params(mdev, new_types);
1050 /* We are about to apply the changes after the configuration
1051 * was verified, no need to remember the temporary types
1053 for (i = 0; i < mdev->caps.num_ports; i++)
1054 priv->port[i + 1].tmp_type = 0;
1056 err = mlx4_change_port_types(mdev, new_types);
1059 mlx4_start_sense(mdev);
1060 mutex_unlock(&priv->port_mutex);
1062 mutex_unlock(&set_port_type_mutex);
1064 return err ? err : count;
1075 static inline int int_to_ibta_mtu(int mtu)
1078 case 256: return IB_MTU_256;
1079 case 512: return IB_MTU_512;
1080 case 1024: return IB_MTU_1024;
1081 case 2048: return IB_MTU_2048;
1082 case 4096: return IB_MTU_4096;
1087 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1090 case IB_MTU_256: return 256;
1091 case IB_MTU_512: return 512;
1092 case IB_MTU_1024: return 1024;
1093 case IB_MTU_2048: return 2048;
1094 case IB_MTU_4096: return 4096;
1099 static ssize_t show_port_ib_mtu(struct device *dev,
1100 struct device_attribute *attr,
1103 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1105 struct mlx4_dev *mdev = info->dev;
1107 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1108 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1110 sprintf(buf, "%d\n",
1111 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1115 static ssize_t set_port_ib_mtu(struct device *dev,
1116 struct device_attribute *attr,
1117 const char *buf, size_t count)
1119 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1121 struct mlx4_dev *mdev = info->dev;
1122 struct mlx4_priv *priv = mlx4_priv(mdev);
1123 int err, port, mtu, ibta_mtu = -1;
1125 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1126 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1130 err = kstrtoint(buf, 0, &mtu);
1132 ibta_mtu = int_to_ibta_mtu(mtu);
1134 if (err || ibta_mtu < 0) {
1135 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1139 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1141 mlx4_stop_sense(mdev);
1142 mutex_lock(&priv->port_mutex);
1143 mlx4_unregister_device(mdev);
1144 for (port = 1; port <= mdev->caps.num_ports; port++) {
1145 mlx4_CLOSE_PORT(mdev, port);
1146 err = mlx4_SET_PORT(mdev, port, -1);
1148 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1153 err = mlx4_register_device(mdev);
1155 mutex_unlock(&priv->port_mutex);
1156 mlx4_start_sense(mdev);
1157 return err ? err : count;
1160 static int mlx4_load_fw(struct mlx4_dev *dev)
1162 struct mlx4_priv *priv = mlx4_priv(dev);
1165 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1166 GFP_HIGHUSER | __GFP_NOWARN, 0);
1167 if (!priv->fw.fw_icm) {
1168 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1172 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1174 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1178 err = mlx4_RUN_FW(dev);
1180 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1190 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1194 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1197 struct mlx4_priv *priv = mlx4_priv(dev);
1201 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1203 ((u64) (MLX4_CMPT_TYPE_QP *
1204 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1205 cmpt_entry_sz, dev->caps.num_qps,
1206 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1211 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1213 ((u64) (MLX4_CMPT_TYPE_SRQ *
1214 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1215 cmpt_entry_sz, dev->caps.num_srqs,
1216 dev->caps.reserved_srqs, 0, 0);
1220 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1222 ((u64) (MLX4_CMPT_TYPE_CQ *
1223 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1224 cmpt_entry_sz, dev->caps.num_cqs,
1225 dev->caps.reserved_cqs, 0, 0);
1229 num_eqs = dev->phys_caps.num_phys_eqs;
1230 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1232 ((u64) (MLX4_CMPT_TYPE_EQ *
1233 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1234 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1241 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1244 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1247 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1253 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1254 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1256 struct mlx4_priv *priv = mlx4_priv(dev);
1261 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1263 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1267 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1268 (unsigned long long) icm_size >> 10,
1269 (unsigned long long) aux_pages << 2);
1271 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1272 GFP_HIGHUSER | __GFP_NOWARN, 0);
1273 if (!priv->fw.aux_icm) {
1274 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1278 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1280 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1284 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1286 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1291 num_eqs = dev->phys_caps.num_phys_eqs;
1292 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1293 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1294 num_eqs, num_eqs, 0, 0);
1296 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1297 goto err_unmap_cmpt;
1301 * Reserved MTT entries must be aligned up to a cacheline
1302 * boundary, since the FW will write to them, while the driver
1303 * writes to all other MTT entries. (The variable
1304 * dev->caps.mtt_entry_sz below is really the MTT segment
1305 * size, not the raw entry size)
1307 dev->caps.reserved_mtts =
1308 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1309 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1311 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1313 dev->caps.mtt_entry_sz,
1315 dev->caps.reserved_mtts, 1, 0);
1317 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1321 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1322 init_hca->dmpt_base,
1323 dev_cap->dmpt_entry_sz,
1325 dev->caps.reserved_mrws, 1, 1);
1327 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1331 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1333 dev_cap->qpc_entry_sz,
1335 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1338 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1339 goto err_unmap_dmpt;
1342 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1343 init_hca->auxc_base,
1344 dev_cap->aux_entry_sz,
1346 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1349 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1353 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1354 init_hca->altc_base,
1355 dev_cap->altc_entry_sz,
1357 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1360 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1361 goto err_unmap_auxc;
1364 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1365 init_hca->rdmarc_base,
1366 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1371 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1372 goto err_unmap_altc;
1375 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1377 dev_cap->cqc_entry_sz,
1379 dev->caps.reserved_cqs, 0, 0);
1381 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1382 goto err_unmap_rdmarc;
1385 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1386 init_hca->srqc_base,
1387 dev_cap->srq_entry_sz,
1389 dev->caps.reserved_srqs, 0, 0);
1391 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1396 * For flow steering device managed mode it is required to use
1397 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1398 * required, but for simplicity just map the whole multicast
1399 * group table now. The table isn't very big and it's a lot
1400 * easier than trying to track ref counts.
1402 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1404 mlx4_get_mgm_entry_size(dev),
1405 dev->caps.num_mgms + dev->caps.num_amgms,
1406 dev->caps.num_mgms + dev->caps.num_amgms,
1409 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1416 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1419 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1422 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1425 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1428 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1431 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1434 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1437 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1440 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1443 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1444 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1445 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1446 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1449 mlx4_UNMAP_ICM_AUX(dev);
1452 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1457 static void mlx4_free_icms(struct mlx4_dev *dev)
1459 struct mlx4_priv *priv = mlx4_priv(dev);
1461 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1462 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1463 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1464 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1465 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1466 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1467 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1468 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1469 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1470 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1471 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1472 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1473 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1474 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1476 mlx4_UNMAP_ICM_AUX(dev);
1477 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1480 static void mlx4_slave_exit(struct mlx4_dev *dev)
1482 struct mlx4_priv *priv = mlx4_priv(dev);
1484 mutex_lock(&priv->cmd.slave_cmd_mutex);
1485 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1486 mlx4_warn(dev, "Failed to close slave function\n");
1487 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1490 static int map_bf_area(struct mlx4_dev *dev)
1492 struct mlx4_priv *priv = mlx4_priv(dev);
1493 resource_size_t bf_start;
1494 resource_size_t bf_len;
1497 if (!dev->caps.bf_reg_size)
1500 bf_start = pci_resource_start(dev->persist->pdev, 2) +
1501 (dev->caps.num_uars << PAGE_SHIFT);
1502 bf_len = pci_resource_len(dev->persist->pdev, 2) -
1503 (dev->caps.num_uars << PAGE_SHIFT);
1504 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1505 if (!priv->bf_mapping)
1511 static void unmap_bf_area(struct mlx4_dev *dev)
1513 if (mlx4_priv(dev)->bf_mapping)
1514 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1517 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1519 u32 clockhi, clocklo, clockhi1;
1522 struct mlx4_priv *priv = mlx4_priv(dev);
1524 for (i = 0; i < 10; i++) {
1525 clockhi = swab32(readl(priv->clock_mapping));
1526 clocklo = swab32(readl(priv->clock_mapping + 4));
1527 clockhi1 = swab32(readl(priv->clock_mapping));
1528 if (clockhi == clockhi1)
1532 cycles = (u64) clockhi << 32 | (u64) clocklo;
1536 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1539 static int map_internal_clock(struct mlx4_dev *dev)
1541 struct mlx4_priv *priv = mlx4_priv(dev);
1543 priv->clock_mapping =
1544 ioremap(pci_resource_start(dev->persist->pdev,
1545 priv->fw.clock_bar) +
1546 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1548 if (!priv->clock_mapping)
1554 static void unmap_internal_clock(struct mlx4_dev *dev)
1556 struct mlx4_priv *priv = mlx4_priv(dev);
1558 if (priv->clock_mapping)
1559 iounmap(priv->clock_mapping);
1562 static void mlx4_close_hca(struct mlx4_dev *dev)
1564 unmap_internal_clock(dev);
1566 if (mlx4_is_slave(dev))
1567 mlx4_slave_exit(dev);
1569 mlx4_CLOSE_HCA(dev, 0);
1570 mlx4_free_icms(dev);
1574 static void mlx4_close_fw(struct mlx4_dev *dev)
1576 if (!mlx4_is_slave(dev)) {
1578 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1582 static int mlx4_init_slave(struct mlx4_dev *dev)
1584 struct mlx4_priv *priv = mlx4_priv(dev);
1585 u64 dma = (u64) priv->mfunc.vhcr_dma;
1586 int ret_from_reset = 0;
1588 u32 cmd_channel_ver;
1590 if (atomic_read(&pf_loading)) {
1591 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1592 return -EPROBE_DEFER;
1595 mutex_lock(&priv->cmd.slave_cmd_mutex);
1596 priv->cmd.max_cmds = 1;
1597 mlx4_warn(dev, "Sending reset\n");
1598 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1600 /* if we are in the middle of flr the slave will try
1601 * NUM_OF_RESET_RETRIES times before leaving.*/
1602 if (ret_from_reset) {
1603 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1604 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1605 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1606 return -EPROBE_DEFER;
1611 /* check the driver version - the slave I/F revision
1612 * must match the master's */
1613 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1614 cmd_channel_ver = mlx4_comm_get_version();
1616 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1617 MLX4_COMM_GET_IF_REV(slave_read)) {
1618 mlx4_err(dev, "slave driver version is not supported by the master\n");
1622 mlx4_warn(dev, "Sending vhcr0\n");
1623 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1626 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1629 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1632 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1635 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1639 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1640 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1644 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1648 for (i = 1; i <= dev->caps.num_ports; i++) {
1649 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1650 dev->caps.gid_table_len[i] =
1651 mlx4_get_slave_num_gids(dev, 0, i);
1653 dev->caps.gid_table_len[i] = 1;
1654 dev->caps.pkey_table_len[i] =
1655 dev->phys_caps.pkey_phys_table_len[i] - 1;
1659 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1661 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1663 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1665 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1669 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1672 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1674 switch (dmfs_high_steer_mode) {
1675 case MLX4_STEERING_DMFS_A0_DEFAULT:
1676 return "default performance";
1678 case MLX4_STEERING_DMFS_A0_DYNAMIC:
1679 return "dynamic hybrid mode";
1681 case MLX4_STEERING_DMFS_A0_STATIC:
1682 return "performance optimized for limited rule configuration (static)";
1684 case MLX4_STEERING_DMFS_A0_DISABLE:
1685 return "disabled performance optimized steering";
1687 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1688 return "performance optimized steering not supported";
1691 return "Unrecognized mode";
1695 #define MLX4_DMFS_A0_STEERING (1UL << 2)
1697 static void choose_steering_mode(struct mlx4_dev *dev,
1698 struct mlx4_dev_cap *dev_cap)
1700 if (mlx4_log_num_mgm_entry_size <= 0) {
1701 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1702 if (dev->caps.dmfs_high_steer_mode ==
1703 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1704 mlx4_err(dev, "DMFS high rate mode not supported\n");
1706 dev->caps.dmfs_high_steer_mode =
1707 MLX4_STEERING_DMFS_A0_STATIC;
1711 if (mlx4_log_num_mgm_entry_size <= 0 &&
1712 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1713 (!mlx4_is_mfunc(dev) ||
1714 (dev_cap->fs_max_num_qp_per_entry >=
1715 (dev->persist->num_vfs + 1))) &&
1716 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1717 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1718 dev->oper_log_mgm_entry_size =
1719 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1720 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1721 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1722 dev->caps.fs_log_max_ucast_qp_range_size =
1723 dev_cap->fs_log_max_ucast_qp_range_size;
1725 if (dev->caps.dmfs_high_steer_mode !=
1726 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1727 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
1728 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1729 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1730 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1732 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1734 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1735 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1736 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1738 dev->oper_log_mgm_entry_size =
1739 mlx4_log_num_mgm_entry_size > 0 ?
1740 mlx4_log_num_mgm_entry_size :
1741 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1742 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1744 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1745 mlx4_steering_mode_str(dev->caps.steering_mode),
1746 dev->oper_log_mgm_entry_size,
1747 mlx4_log_num_mgm_entry_size);
1750 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1751 struct mlx4_dev_cap *dev_cap)
1753 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1754 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS &&
1755 dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1756 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1758 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1760 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1761 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1764 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1767 struct mlx4_port_cap port_cap;
1769 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1772 for (i = 1; i <= dev->caps.num_ports; i++) {
1773 if (mlx4_dev_port(dev, i, &port_cap)) {
1775 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1776 } else if ((dev->caps.dmfs_high_steer_mode !=
1777 MLX4_STEERING_DMFS_A0_DEFAULT) &&
1778 (port_cap.dmfs_optimized_state ==
1779 !!(dev->caps.dmfs_high_steer_mode ==
1780 MLX4_STEERING_DMFS_A0_DISABLE))) {
1782 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1783 dmfs_high_rate_steering_mode_str(
1784 dev->caps.dmfs_high_steer_mode),
1785 (port_cap.dmfs_optimized_state ?
1786 "enabled" : "disabled"));
1793 static int mlx4_init_fw(struct mlx4_dev *dev)
1795 struct mlx4_mod_stat_cfg mlx4_cfg;
1798 if (!mlx4_is_slave(dev)) {
1799 err = mlx4_QUERY_FW(dev);
1802 mlx4_info(dev, "non-primary physical function, skipping\n");
1804 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
1808 err = mlx4_load_fw(dev);
1810 mlx4_err(dev, "Failed to start FW, aborting\n");
1814 mlx4_cfg.log_pg_sz_m = 1;
1815 mlx4_cfg.log_pg_sz = 0;
1816 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1818 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1824 static int mlx4_init_hca(struct mlx4_dev *dev)
1826 struct mlx4_priv *priv = mlx4_priv(dev);
1827 struct mlx4_adapter adapter;
1828 struct mlx4_dev_cap dev_cap;
1829 struct mlx4_profile profile;
1830 struct mlx4_init_hca_param init_hca;
1832 struct mlx4_config_dev_params params;
1835 if (!mlx4_is_slave(dev)) {
1836 err = mlx4_dev_cap(dev, &dev_cap);
1838 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
1842 choose_steering_mode(dev, &dev_cap);
1843 choose_tunnel_offload_mode(dev, &dev_cap);
1845 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
1846 mlx4_is_master(dev))
1847 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
1849 err = mlx4_get_phys_port_id(dev);
1851 mlx4_err(dev, "Fail to get physical port id\n");
1853 if (mlx4_is_master(dev))
1854 mlx4_parav_master_pf_caps(dev);
1856 if (mlx4_low_memory_profile()) {
1857 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1858 profile = low_mem_profile;
1860 profile = default_profile;
1862 if (dev->caps.steering_mode ==
1863 MLX4_STEERING_MODE_DEVICE_MANAGED)
1864 profile.num_mcg = MLX4_FS_NUM_MCG;
1866 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1868 if ((long long) icm_size < 0) {
1873 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1875 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1876 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1877 init_hca.mw_enabled = 0;
1878 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1879 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1880 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1882 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1886 err = mlx4_INIT_HCA(dev, &init_hca);
1888 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
1892 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
1893 err = mlx4_query_func(dev, &dev_cap);
1895 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
1897 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
1898 dev->caps.num_eqs = dev_cap.max_eqs;
1899 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
1900 dev->caps.reserved_uars = dev_cap.reserved_uars;
1905 * If TS is supported by FW
1906 * read HCA frequency by QUERY_HCA command
1908 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1909 memset(&init_hca, 0, sizeof(init_hca));
1910 err = mlx4_QUERY_HCA(dev, &init_hca);
1912 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
1913 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1915 dev->caps.hca_core_clock =
1916 init_hca.hca_core_clock;
1919 /* In case we got HCA frequency 0 - disable timestamping
1920 * to avoid dividing by zero
1922 if (!dev->caps.hca_core_clock) {
1923 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1925 "HCA frequency is 0 - timestamping is not supported\n");
1926 } else if (map_internal_clock(dev)) {
1928 * Map internal clock,
1929 * in case of failure disable timestamping
1931 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1932 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
1936 if (dev->caps.dmfs_high_steer_mode !=
1937 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
1938 if (mlx4_validate_optimized_steering(dev))
1939 mlx4_warn(dev, "Optimized steering validation failed\n");
1941 if (dev->caps.dmfs_high_steer_mode ==
1942 MLX4_STEERING_DMFS_A0_DISABLE) {
1943 dev->caps.dmfs_high_rate_qpn_base =
1944 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1945 dev->caps.dmfs_high_rate_qpn_range =
1946 MLX4_A0_STEERING_TABLE_SIZE;
1949 mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
1950 dmfs_high_rate_steering_mode_str(
1951 dev->caps.dmfs_high_steer_mode));
1954 err = mlx4_init_slave(dev);
1956 if (err != -EPROBE_DEFER)
1957 mlx4_err(dev, "Failed to initialize slave\n");
1961 err = mlx4_slave_cap(dev);
1963 mlx4_err(dev, "Failed to obtain slave caps\n");
1968 if (map_bf_area(dev))
1969 mlx4_dbg(dev, "Failed to map blue flame area\n");
1971 /*Only the master set the ports, all the rest got it from it.*/
1972 if (!mlx4_is_slave(dev))
1973 mlx4_set_port_mask(dev);
1975 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1977 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
1981 /* Query CONFIG_DEV parameters */
1982 err = mlx4_config_dev_retrieval(dev, ¶ms);
1983 if (err && err != -ENOTSUPP) {
1984 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
1986 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
1987 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
1989 priv->eq_table.inta_pin = adapter.inta_pin;
1990 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1995 unmap_internal_clock(dev);
1998 if (mlx4_is_slave(dev)) {
1999 kfree(dev->caps.qp0_qkey);
2000 kfree(dev->caps.qp0_tunnel);
2001 kfree(dev->caps.qp0_proxy);
2002 kfree(dev->caps.qp1_tunnel);
2003 kfree(dev->caps.qp1_proxy);
2007 if (mlx4_is_slave(dev))
2008 mlx4_slave_exit(dev);
2010 mlx4_CLOSE_HCA(dev, 0);
2013 if (!mlx4_is_slave(dev))
2014 mlx4_free_icms(dev);
2019 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2021 struct mlx4_priv *priv = mlx4_priv(dev);
2024 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2027 nent = dev->caps.max_counters;
2028 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2031 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2033 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2036 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2038 struct mlx4_priv *priv = mlx4_priv(dev);
2040 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2043 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2050 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2055 if (mlx4_is_mfunc(dev)) {
2056 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2057 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2058 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2060 *idx = get_param_l(&out_param);
2064 return __mlx4_counter_alloc(dev, idx);
2066 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2068 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2070 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2074 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2078 if (mlx4_is_mfunc(dev)) {
2079 set_param_l(&in_param, idx);
2080 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2081 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2085 __mlx4_counter_free(dev, idx);
2087 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2089 static int mlx4_setup_hca(struct mlx4_dev *dev)
2091 struct mlx4_priv *priv = mlx4_priv(dev);
2094 __be32 ib_port_default_caps;
2096 err = mlx4_init_uar_table(dev);
2098 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2102 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2104 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2105 goto err_uar_table_free;
2108 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2110 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2115 err = mlx4_init_pd_table(dev);
2117 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2121 err = mlx4_init_xrcd_table(dev);
2123 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2124 goto err_pd_table_free;
2127 err = mlx4_init_mr_table(dev);
2129 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2130 goto err_xrcd_table_free;
2133 if (!mlx4_is_slave(dev)) {
2134 err = mlx4_init_mcg_table(dev);
2136 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2137 goto err_mr_table_free;
2139 err = mlx4_config_mad_demux(dev);
2141 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2142 goto err_mcg_table_free;
2146 err = mlx4_init_eq_table(dev);
2148 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2149 goto err_mcg_table_free;
2152 err = mlx4_cmd_use_events(dev);
2154 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2155 goto err_eq_table_free;
2158 err = mlx4_NOP(dev);
2160 if (dev->flags & MLX4_FLAG_MSI_X) {
2161 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2162 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2163 mlx4_warn(dev, "Trying again without MSI-X\n");
2165 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2166 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2167 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2173 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2175 err = mlx4_init_cq_table(dev);
2177 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2181 err = mlx4_init_srq_table(dev);
2183 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2184 goto err_cq_table_free;
2187 err = mlx4_init_qp_table(dev);
2189 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2190 goto err_srq_table_free;
2193 err = mlx4_init_counters_table(dev);
2194 if (err && err != -ENOENT) {
2195 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2196 goto err_qp_table_free;
2199 if (!mlx4_is_slave(dev)) {
2200 for (port = 1; port <= dev->caps.num_ports; port++) {
2201 ib_port_default_caps = 0;
2202 err = mlx4_get_port_ib_caps(dev, port,
2203 &ib_port_default_caps);
2205 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2207 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2209 /* initialize per-slave default ib port capabilities */
2210 if (mlx4_is_master(dev)) {
2212 for (i = 0; i < dev->num_slaves; i++) {
2213 if (i == mlx4_master_func_num(dev))
2215 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2216 ib_port_default_caps;
2220 if (mlx4_is_mfunc(dev))
2221 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2223 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2225 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2226 dev->caps.pkey_table_len[port] : -1);
2228 mlx4_err(dev, "Failed to set port %d, aborting\n",
2230 goto err_counters_table_free;
2237 err_counters_table_free:
2238 mlx4_cleanup_counters_table(dev);
2241 mlx4_cleanup_qp_table(dev);
2244 mlx4_cleanup_srq_table(dev);
2247 mlx4_cleanup_cq_table(dev);
2250 mlx4_cmd_use_polling(dev);
2253 mlx4_cleanup_eq_table(dev);
2256 if (!mlx4_is_slave(dev))
2257 mlx4_cleanup_mcg_table(dev);
2260 mlx4_cleanup_mr_table(dev);
2262 err_xrcd_table_free:
2263 mlx4_cleanup_xrcd_table(dev);
2266 mlx4_cleanup_pd_table(dev);
2272 mlx4_uar_free(dev, &priv->driver_uar);
2275 mlx4_cleanup_uar_table(dev);
2279 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2281 struct mlx4_priv *priv = mlx4_priv(dev);
2282 struct msix_entry *entries;
2286 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2288 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2291 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2295 for (i = 0; i < nreq; ++i)
2296 entries[i].entry = i;
2298 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2304 } else if (nreq < MSIX_LEGACY_SZ +
2305 dev->caps.num_ports * MIN_MSIX_P_PORT) {
2306 /*Working in legacy mode , all EQ's shared*/
2307 dev->caps.comp_pool = 0;
2308 dev->caps.num_comp_vectors = nreq - 1;
2310 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2311 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2313 for (i = 0; i < nreq; ++i)
2314 priv->eq_table.eq[i].irq = entries[i].vector;
2316 dev->flags |= MLX4_FLAG_MSI_X;
2323 dev->caps.num_comp_vectors = 1;
2324 dev->caps.comp_pool = 0;
2326 for (i = 0; i < 2; ++i)
2327 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2330 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2332 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2337 if (!mlx4_is_slave(dev)) {
2338 mlx4_init_mac_table(dev, &info->mac_table);
2339 mlx4_init_vlan_table(dev, &info->vlan_table);
2340 mlx4_init_roce_gid_table(dev, &info->gid_table);
2341 info->base_qpn = mlx4_get_base_qpn(dev, port);
2344 sprintf(info->dev_name, "mlx4_port%d", port);
2345 info->port_attr.attr.name = info->dev_name;
2346 if (mlx4_is_mfunc(dev))
2347 info->port_attr.attr.mode = S_IRUGO;
2349 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2350 info->port_attr.store = set_port_type;
2352 info->port_attr.show = show_port_type;
2353 sysfs_attr_init(&info->port_attr.attr);
2355 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2357 mlx4_err(dev, "Failed to create file for port %d\n", port);
2361 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2362 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2363 if (mlx4_is_mfunc(dev))
2364 info->port_mtu_attr.attr.mode = S_IRUGO;
2366 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2367 info->port_mtu_attr.store = set_port_ib_mtu;
2369 info->port_mtu_attr.show = show_port_ib_mtu;
2370 sysfs_attr_init(&info->port_mtu_attr.attr);
2372 err = device_create_file(&dev->persist->pdev->dev,
2373 &info->port_mtu_attr);
2375 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2376 device_remove_file(&info->dev->persist->pdev->dev,
2384 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2389 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2390 device_remove_file(&info->dev->persist->pdev->dev,
2391 &info->port_mtu_attr);
2394 static int mlx4_init_steering(struct mlx4_dev *dev)
2396 struct mlx4_priv *priv = mlx4_priv(dev);
2397 int num_entries = dev->caps.num_ports;
2400 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2404 for (i = 0; i < num_entries; i++)
2405 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2406 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2407 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2412 static void mlx4_clear_steering(struct mlx4_dev *dev)
2414 struct mlx4_priv *priv = mlx4_priv(dev);
2415 struct mlx4_steer_index *entry, *tmp_entry;
2416 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2417 int num_entries = dev->caps.num_ports;
2420 for (i = 0; i < num_entries; i++) {
2421 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2422 list_for_each_entry_safe(pqp, tmp_pqp,
2423 &priv->steer[i].promisc_qps[j],
2425 list_del(&pqp->list);
2428 list_for_each_entry_safe(entry, tmp_entry,
2429 &priv->steer[i].steer_entries[j],
2431 list_del(&entry->list);
2432 list_for_each_entry_safe(pqp, tmp_pqp,
2435 list_del(&pqp->list);
2445 static int extended_func_num(struct pci_dev *pdev)
2447 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2450 #define MLX4_OWNER_BASE 0x8069c
2451 #define MLX4_OWNER_SIZE 4
2453 static int mlx4_get_ownership(struct mlx4_dev *dev)
2455 void __iomem *owner;
2458 if (pci_channel_offline(dev->persist->pdev))
2461 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2465 mlx4_err(dev, "Failed to obtain ownership bit\n");
2474 static void mlx4_free_ownership(struct mlx4_dev *dev)
2476 void __iomem *owner;
2478 if (pci_channel_offline(dev->persist->pdev))
2481 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2485 mlx4_err(dev, "Failed to obtain ownership bit\n");
2493 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2494 !!((flags) & MLX4_FLAG_MASTER))
2496 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
2497 u8 total_vfs, int existing_vfs)
2499 u64 dev_flags = dev->flags;
2502 atomic_inc(&pf_loading);
2503 if (dev->flags & MLX4_FLAG_SRIOV) {
2504 if (existing_vfs != total_vfs) {
2505 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2506 existing_vfs, total_vfs);
2507 total_vfs = existing_vfs;
2511 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
2512 if (NULL == dev->dev_vfs) {
2513 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2517 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
2518 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2519 err = pci_enable_sriov(pdev, total_vfs);
2522 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2526 mlx4_warn(dev, "Running in master mode\n");
2527 dev_flags |= MLX4_FLAG_SRIOV |
2529 dev_flags &= ~MLX4_FLAG_SLAVE;
2530 dev->persist->num_vfs = total_vfs;
2535 atomic_dec(&pf_loading);
2536 dev->persist->num_vfs = 0;
2537 kfree(dev->dev_vfs);
2538 return dev_flags & ~MLX4_FLAG_MASTER;
2542 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2545 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2548 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2549 /* Checking for 64 VFs as a limitation of CX2 */
2550 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2551 requested_vfs >= 64) {
2552 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2554 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2559 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2560 int total_vfs, int *nvfs, struct mlx4_priv *priv)
2562 struct mlx4_dev *dev;
2567 struct mlx4_dev_cap *dev_cap = NULL;
2568 int existing_vfs = 0;
2572 INIT_LIST_HEAD(&priv->ctx_list);
2573 spin_lock_init(&priv->ctx_lock);
2575 mutex_init(&priv->port_mutex);
2577 INIT_LIST_HEAD(&priv->pgdir_list);
2578 mutex_init(&priv->pgdir_mutex);
2580 INIT_LIST_HEAD(&priv->bf_list);
2581 mutex_init(&priv->bf_mutex);
2583 dev->rev_id = pdev->revision;
2584 dev->numa_node = dev_to_node(&pdev->dev);
2586 /* Detect if this device is a virtual function */
2587 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2588 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2589 dev->flags |= MLX4_FLAG_SLAVE;
2591 /* We reset the device and enable SRIOV only for physical
2592 * devices. Try to claim ownership on the device;
2593 * if already taken, skip -- do not allow multiple PFs */
2594 err = mlx4_get_ownership(dev);
2599 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
2604 atomic_set(&priv->opreq_count, 0);
2605 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2608 * Now reset the HCA before we touch the PCI capabilities or
2609 * attempt a firmware command, since a boot ROM may have left
2610 * the HCA in an undefined state.
2612 err = mlx4_reset(dev);
2614 mlx4_err(dev, "Failed to reset HCA, aborting\n");
2619 dev->flags = MLX4_FLAG_MASTER;
2620 existing_vfs = pci_num_vf(pdev);
2622 dev->flags |= MLX4_FLAG_SRIOV;
2623 dev->persist->num_vfs = total_vfs;
2628 err = mlx4_cmd_init(dev);
2630 mlx4_err(dev, "Failed to init command interface, aborting\n");
2634 /* In slave functions, the communication channel must be initialized
2635 * before posting commands. Also, init num_slaves before calling
2637 if (mlx4_is_mfunc(dev)) {
2638 if (mlx4_is_master(dev)) {
2639 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2642 dev->num_slaves = 0;
2643 err = mlx4_multi_func_init(dev);
2645 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
2651 err = mlx4_init_fw(dev);
2653 mlx4_err(dev, "Failed to init fw, aborting.\n");
2657 if (mlx4_is_master(dev)) {
2658 /* when we hit the goto slave_start below, dev_cap already initialized */
2660 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2667 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2669 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2673 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2676 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2677 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2680 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2681 dev->flags = dev_flags;
2682 if (!SRIOV_VALID_STATE(dev->flags)) {
2683 mlx4_err(dev, "Invalid SRIOV state\n");
2686 err = mlx4_reset(dev);
2688 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2694 /* Legacy mode FW requires SRIOV to be enabled before
2695 * doing QUERY_DEV_CAP, since max_eq's value is different if
2698 memset(dev_cap, 0, sizeof(*dev_cap));
2699 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2701 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2705 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2710 err = mlx4_init_hca(dev);
2712 if (err == -EACCES) {
2713 /* Not primary Physical function
2714 * Running in slave mode */
2715 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2716 /* We're not a PF */
2717 if (dev->flags & MLX4_FLAG_SRIOV) {
2719 pci_disable_sriov(pdev);
2720 if (mlx4_is_master(dev))
2721 atomic_dec(&pf_loading);
2722 dev->flags &= ~MLX4_FLAG_SRIOV;
2724 if (!mlx4_is_slave(dev))
2725 mlx4_free_ownership(dev);
2726 dev->flags |= MLX4_FLAG_SLAVE;
2727 dev->flags &= ~MLX4_FLAG_MASTER;
2733 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2734 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, existing_vfs);
2736 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2737 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
2738 dev->flags = dev_flags;
2739 err = mlx4_cmd_init(dev);
2741 /* Only VHCR is cleaned up, so could still
2744 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
2748 dev->flags = dev_flags;
2751 if (!SRIOV_VALID_STATE(dev->flags)) {
2752 mlx4_err(dev, "Invalid SRIOV state\n");
2757 /* check if the device is functioning at its maximum possible speed.
2758 * No return code for this call, just warn the user in case of PCI
2759 * express device capabilities are under-satisfied by the bus.
2761 if (!mlx4_is_slave(dev))
2762 mlx4_check_pcie_caps(dev);
2764 /* In master functions, the communication channel must be initialized
2765 * after obtaining its address from fw */
2766 if (mlx4_is_master(dev)) {
2769 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2773 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2775 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2779 if (dev->caps.num_ports < 2 &&
2783 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2784 dev->caps.num_ports);
2787 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
2790 i < sizeof(dev->persist->nvfs)/
2791 sizeof(dev->persist->nvfs[0]); i++) {
2794 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
2795 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2796 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2797 dev->caps.num_ports;
2801 /* In master functions, the communication channel
2802 * must be initialized after obtaining its address from fw
2804 err = mlx4_multi_func_init(dev);
2806 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2811 err = mlx4_alloc_eq_table(dev);
2813 goto err_master_mfunc;
2815 priv->msix_ctl.pool_bm = 0;
2816 mutex_init(&priv->msix_ctl.pool_lock);
2818 mlx4_enable_msi_x(dev);
2819 if ((mlx4_is_mfunc(dev)) &&
2820 !(dev->flags & MLX4_FLAG_MSI_X)) {
2822 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
2826 if (!mlx4_is_slave(dev)) {
2827 err = mlx4_init_steering(dev);
2829 goto err_disable_msix;
2832 err = mlx4_setup_hca(dev);
2833 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2834 !mlx4_is_mfunc(dev)) {
2835 dev->flags &= ~MLX4_FLAG_MSI_X;
2836 dev->caps.num_comp_vectors = 1;
2837 dev->caps.comp_pool = 0;
2838 pci_disable_msix(pdev);
2839 err = mlx4_setup_hca(dev);
2845 mlx4_init_quotas(dev);
2847 for (port = 1; port <= dev->caps.num_ports; port++) {
2848 err = mlx4_init_port_info(dev, port);
2853 err = mlx4_register_device(dev);
2857 mlx4_request_modules(dev);
2859 mlx4_sense_init(dev);
2860 mlx4_start_sense(dev);
2864 if (mlx4_is_master(dev) && dev->persist->num_vfs)
2865 atomic_dec(&pf_loading);
2871 for (--port; port >= 1; --port)
2872 mlx4_cleanup_port_info(&priv->port[port]);
2874 mlx4_cleanup_counters_table(dev);
2875 mlx4_cleanup_qp_table(dev);
2876 mlx4_cleanup_srq_table(dev);
2877 mlx4_cleanup_cq_table(dev);
2878 mlx4_cmd_use_polling(dev);
2879 mlx4_cleanup_eq_table(dev);
2880 mlx4_cleanup_mcg_table(dev);
2881 mlx4_cleanup_mr_table(dev);
2882 mlx4_cleanup_xrcd_table(dev);
2883 mlx4_cleanup_pd_table(dev);
2884 mlx4_cleanup_uar_table(dev);
2887 if (!mlx4_is_slave(dev))
2888 mlx4_clear_steering(dev);
2891 if (dev->flags & MLX4_FLAG_MSI_X)
2892 pci_disable_msix(pdev);
2895 mlx4_free_eq_table(dev);
2898 if (mlx4_is_master(dev))
2899 mlx4_multi_func_cleanup(dev);
2901 if (mlx4_is_slave(dev)) {
2902 kfree(dev->caps.qp0_qkey);
2903 kfree(dev->caps.qp0_tunnel);
2904 kfree(dev->caps.qp0_proxy);
2905 kfree(dev->caps.qp1_tunnel);
2906 kfree(dev->caps.qp1_proxy);
2910 mlx4_close_hca(dev);
2916 if (mlx4_is_slave(dev))
2917 mlx4_multi_func_cleanup(dev);
2920 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2923 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
2924 pci_disable_sriov(pdev);
2926 if (mlx4_is_master(dev) && dev->persist->num_vfs)
2927 atomic_dec(&pf_loading);
2929 kfree(priv->dev.dev_vfs);
2931 if (!mlx4_is_slave(dev))
2932 mlx4_free_ownership(dev);
2938 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2939 struct mlx4_priv *priv)
2942 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2943 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2944 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2945 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2946 unsigned total_vfs = 0;
2949 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2951 err = pci_enable_device(pdev);
2953 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2957 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2958 * per port, we must limit the number of VFs to 63 (since their are
2961 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2962 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2963 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2965 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2967 goto err_disable_pdev;
2970 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2972 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2973 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2974 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2976 goto err_disable_pdev;
2979 if (total_vfs >= MLX4_MAX_NUM_VF) {
2981 "Requested more VF's (%d) than allowed (%d)\n",
2982 total_vfs, MLX4_MAX_NUM_VF - 1);
2984 goto err_disable_pdev;
2987 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2988 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2990 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2991 nvfs[i] + nvfs[2], i + 1,
2992 MLX4_MAX_NUM_VF_P_PORT - 1);
2994 goto err_disable_pdev;
2998 /* Check for BARs. */
2999 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3000 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3001 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3002 pci_dev_data, pci_resource_flags(pdev, 0));
3004 goto err_disable_pdev;
3006 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3007 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3009 goto err_disable_pdev;
3012 err = pci_request_regions(pdev, DRV_NAME);
3014 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3015 goto err_disable_pdev;
3018 pci_set_master(pdev);
3020 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3022 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3023 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3025 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3026 goto err_release_regions;
3029 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3031 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3032 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3034 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3035 goto err_release_regions;
3039 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3040 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3041 /* Detect if this device is a virtual function */
3042 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3043 /* When acting as pf, we normally skip vfs unless explicitly
3044 * requested to probe them.
3047 unsigned vfs_offset = 0;
3049 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3050 vfs_offset + nvfs[i] < extended_func_num(pdev);
3051 vfs_offset += nvfs[i], i++)
3053 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3055 goto err_release_regions;
3057 if ((extended_func_num(pdev) - vfs_offset)
3059 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3060 extended_func_num(pdev));
3062 goto err_release_regions;
3067 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3069 goto err_release_regions;
3072 err_release_regions:
3073 pci_release_regions(pdev);
3076 pci_disable_device(pdev);
3077 pci_set_drvdata(pdev, NULL);
3081 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3083 struct mlx4_priv *priv;
3084 struct mlx4_dev *dev;
3087 printk_once(KERN_INFO "%s", mlx4_version);
3089 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
3094 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3095 if (!dev->persist) {
3099 dev->persist->pdev = pdev;
3100 dev->persist->dev = dev;
3101 pci_set_drvdata(pdev, dev->persist);
3102 priv->pci_dev_data = id->driver_data;
3104 ret = __mlx4_init_one(pdev, id->driver_data, priv);
3106 kfree(dev->persist);
3112 static void mlx4_clean_dev(struct mlx4_dev *dev)
3114 struct mlx4_dev_persistent *persist = dev->persist;
3115 struct mlx4_priv *priv = mlx4_priv(dev);
3117 memset(priv, 0, sizeof(*priv));
3118 priv->dev.persist = persist;
3121 static void mlx4_unload_one(struct pci_dev *pdev)
3123 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3124 struct mlx4_dev *dev = persist->dev;
3125 struct mlx4_priv *priv = mlx4_priv(dev);
3133 /* saving current ports type for further use */
3134 for (i = 0; i < dev->caps.num_ports; i++) {
3135 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3136 dev->persist->curr_port_poss_type[i] = dev->caps.
3137 possible_type[i + 1];
3140 pci_dev_data = priv->pci_dev_data;
3142 /* Disabling SR-IOV is not allowed while there are active vf's */
3143 if (mlx4_is_master(dev)) {
3144 active_vfs = mlx4_how_many_lives_vf(dev);
3146 pr_warn("Removing PF when there are active VF's !!\n");
3147 pr_warn("Will not disable SR-IOV.\n");
3150 mlx4_stop_sense(dev);
3151 mlx4_unregister_device(dev);
3153 for (p = 1; p <= dev->caps.num_ports; p++) {
3154 mlx4_cleanup_port_info(&priv->port[p]);
3155 mlx4_CLOSE_PORT(dev, p);
3158 if (mlx4_is_master(dev))
3159 mlx4_free_resource_tracker(dev,
3160 RES_TR_FREE_SLAVES_ONLY);
3162 mlx4_cleanup_counters_table(dev);
3163 mlx4_cleanup_qp_table(dev);
3164 mlx4_cleanup_srq_table(dev);
3165 mlx4_cleanup_cq_table(dev);
3166 mlx4_cmd_use_polling(dev);
3167 mlx4_cleanup_eq_table(dev);
3168 mlx4_cleanup_mcg_table(dev);
3169 mlx4_cleanup_mr_table(dev);
3170 mlx4_cleanup_xrcd_table(dev);
3171 mlx4_cleanup_pd_table(dev);
3173 if (mlx4_is_master(dev))
3174 mlx4_free_resource_tracker(dev,
3175 RES_TR_FREE_STRUCTS_ONLY);
3178 mlx4_uar_free(dev, &priv->driver_uar);
3179 mlx4_cleanup_uar_table(dev);
3180 if (!mlx4_is_slave(dev))
3181 mlx4_clear_steering(dev);
3182 mlx4_free_eq_table(dev);
3183 if (mlx4_is_master(dev))
3184 mlx4_multi_func_cleanup(dev);
3185 mlx4_close_hca(dev);
3187 if (mlx4_is_slave(dev))
3188 mlx4_multi_func_cleanup(dev);
3189 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3191 if (dev->flags & MLX4_FLAG_MSI_X)
3192 pci_disable_msix(pdev);
3193 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3194 mlx4_warn(dev, "Disabling SR-IOV\n");
3195 pci_disable_sriov(pdev);
3196 dev->flags &= ~MLX4_FLAG_SRIOV;
3197 dev->persist->num_vfs = 0;
3200 if (!mlx4_is_slave(dev))
3201 mlx4_free_ownership(dev);
3203 kfree(dev->caps.qp0_qkey);
3204 kfree(dev->caps.qp0_tunnel);
3205 kfree(dev->caps.qp0_proxy);
3206 kfree(dev->caps.qp1_tunnel);
3207 kfree(dev->caps.qp1_proxy);
3208 kfree(dev->dev_vfs);
3210 mlx4_clean_dev(dev);
3211 priv->pci_dev_data = pci_dev_data;
3215 static void mlx4_remove_one(struct pci_dev *pdev)
3217 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3218 struct mlx4_dev *dev = persist->dev;
3219 struct mlx4_priv *priv = mlx4_priv(dev);
3221 mlx4_unload_one(pdev);
3222 pci_release_regions(pdev);
3223 pci_disable_device(pdev);
3224 kfree(dev->persist);
3226 pci_set_drvdata(pdev, NULL);
3229 static int restore_current_port_types(struct mlx4_dev *dev,
3230 enum mlx4_port_type *types,
3231 enum mlx4_port_type *poss_types)
3233 struct mlx4_priv *priv = mlx4_priv(dev);
3236 mlx4_stop_sense(dev);
3238 mutex_lock(&priv->port_mutex);
3239 for (i = 0; i < dev->caps.num_ports; i++)
3240 dev->caps.possible_type[i + 1] = poss_types[i];
3241 err = mlx4_change_port_types(dev, types);
3242 mlx4_start_sense(dev);
3243 mutex_unlock(&priv->port_mutex);
3248 int mlx4_restart_one(struct pci_dev *pdev)
3250 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3251 struct mlx4_dev *dev = persist->dev;
3252 struct mlx4_priv *priv = mlx4_priv(dev);
3253 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3254 int pci_dev_data, err, total_vfs;
3256 pci_dev_data = priv->pci_dev_data;
3257 total_vfs = dev->persist->num_vfs;
3258 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3260 mlx4_unload_one(pdev);
3261 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
3263 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3264 __func__, pci_name(pdev), err);
3268 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3269 dev->persist->curr_port_poss_type);
3271 mlx4_err(dev, "could not restore original port types (%d)\n",
3277 static const struct pci_device_id mlx4_pci_table[] = {
3278 /* MT25408 "Hermon" SDR */
3279 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3280 /* MT25408 "Hermon" DDR */
3281 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3282 /* MT25408 "Hermon" QDR */
3283 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3284 /* MT25408 "Hermon" DDR PCIe gen2 */
3285 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3286 /* MT25408 "Hermon" QDR PCIe gen2 */
3287 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3288 /* MT25408 "Hermon" EN 10GigE */
3289 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3290 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3291 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3292 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3293 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3294 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3295 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3296 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3297 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3298 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3299 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3300 /* MT26478 ConnectX2 40GigE PCIe gen2 */
3301 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3302 /* MT25400 Family [ConnectX-2 Virtual Function] */
3303 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3304 /* MT27500 Family [ConnectX-3] */
3305 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3306 /* MT27500 Family [ConnectX-3 Virtual Function] */
3307 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
3308 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3309 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3310 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3311 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3312 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3313 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3314 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3315 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3316 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3317 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3318 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3319 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
3323 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3325 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3326 pci_channel_state_t state)
3328 mlx4_unload_one(pdev);
3330 return state == pci_channel_io_perm_failure ?
3331 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3334 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3336 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3337 struct mlx4_priv *priv = mlx4_priv(dev);
3340 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
3342 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3345 static const struct pci_error_handlers mlx4_err_handler = {
3346 .error_detected = mlx4_pci_err_detected,
3347 .slot_reset = mlx4_pci_slot_reset,
3350 static struct pci_driver mlx4_driver = {
3352 .id_table = mlx4_pci_table,
3353 .probe = mlx4_init_one,
3354 .shutdown = mlx4_unload_one,
3355 .remove = mlx4_remove_one,
3356 .err_handler = &mlx4_err_handler,
3359 static int __init mlx4_verify_params(void)
3361 if ((log_num_mac < 0) || (log_num_mac > 7)) {
3362 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
3366 if (log_num_vlan != 0)
3367 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3368 MLX4_LOG_NUM_VLANS);
3371 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
3373 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
3374 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3379 /* Check if module param for ports type has legal combination */
3380 if (port_type_array[0] == false && port_type_array[1] == true) {
3381 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
3382 port_type_array[0] = true;
3385 if (mlx4_log_num_mgm_entry_size < -7 ||
3386 (mlx4_log_num_mgm_entry_size > 0 &&
3387 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3388 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
3389 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
3390 mlx4_log_num_mgm_entry_size,
3391 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3392 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3399 static int __init mlx4_init(void)
3403 if (mlx4_verify_params())
3408 mlx4_wq = create_singlethread_workqueue("mlx4");
3412 ret = pci_register_driver(&mlx4_driver);
3414 destroy_workqueue(mlx4_wq);
3415 return ret < 0 ? ret : 0;
3418 static void __exit mlx4_cleanup(void)
3420 pci_unregister_driver(&mlx4_driver);
3421 destroy_workqueue(mlx4_wq);
3424 module_init(mlx4_init);
3425 module_exit(mlx4_cleanup);