2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/semaphore.h>
44 #include <linux/workqueue.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/driver.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
51 #define DRV_NAME "mlx4_core"
52 #define PFX DRV_NAME ": "
53 #define DRV_VERSION "1.0"
54 #define DRV_RELDATE "July 14, 2011"
57 MLX4_HCR_BASE = 0x80680,
58 MLX4_HCR_SIZE = 0x0001c,
59 MLX4_CLR_INT_SIZE = 0x00008,
60 MLX4_SLAVE_COMM_BASE = 0x0,
61 MLX4_COMM_PAGESIZE = 0x1000
65 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
66 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
67 MLX4_MTT_ENTRY_PER_SEG = 8,
71 MLX4_NUM_PDS = 1 << 15
75 MLX4_CMPT_TYPE_QP = 0,
76 MLX4_CMPT_TYPE_SRQ = 1,
77 MLX4_CMPT_TYPE_CQ = 2,
78 MLX4_CMPT_TYPE_EQ = 3,
84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
93 #define MLX4_COMM_TIME 10000
99 MLX4_COMM_CMD_VHCR_EN,
100 MLX4_COMM_CMD_VHCR_POST,
101 MLX4_COMM_CMD_FLR = 254
104 /*The flag indicates that the slave should delay the RESET cmd*/
105 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
106 /*indicates how many retries will be done if we are in the middle of FLR*/
107 #define NUM_OF_RESET_RETRIES 10
108 #define SLEEP_TIME_IN_RESET (2 * 1000)
120 MLX4_NUM_OF_RESOURCE_TYPE
123 enum mlx4_alloc_mode {
125 RES_OP_RESERVE_AND_MAP,
131 *Virtual HCR structures.
132 * mlx4_vhcr is the sw representation, in machine endianess
134 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
135 * to FW to go through communication channel.
136 * It is big endian, and has the same structure as the physical HCR
137 * used by command interface
150 struct mlx4_vhcr_cmd {
161 struct mlx4_cmd_info {
166 bool encode_slave_id;
167 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
168 struct mlx4_cmd_mailbox *inbox);
169 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
170 struct mlx4_cmd_mailbox *inbox,
171 struct mlx4_cmd_mailbox *outbox,
172 struct mlx4_cmd_info *cmd);
175 #ifdef CONFIG_MLX4_DEBUG
176 extern int mlx4_debug_level;
177 #else /* CONFIG_MLX4_DEBUG */
178 #define mlx4_debug_level (0)
179 #endif /* CONFIG_MLX4_DEBUG */
181 #define mlx4_dbg(mdev, format, arg...) \
183 if (mlx4_debug_level) \
184 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
187 #define mlx4_err(mdev, format, arg...) \
188 dev_err(&mdev->pdev->dev, format, ##arg)
189 #define mlx4_info(mdev, format, arg...) \
190 dev_info(&mdev->pdev->dev, format, ##arg)
191 #define mlx4_warn(mdev, format, arg...) \
192 dev_warn(&mdev->pdev->dev, format, ##arg)
194 extern int mlx4_log_num_mgm_entry_size;
195 extern int log_mtts_per_seg;
197 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
198 #define ALL_SLAVES 0xff
208 unsigned long *table;
212 unsigned long **bits;
213 unsigned int *num_free;
220 struct mlx4_icm_table {
228 struct mlx4_icm **icm;
232 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
234 struct mlx4_mpt_entry {
248 __be32 first_byte_offset;
252 * Must be packed because start is 64 bits but only aligned to 32 bits.
254 struct mlx4_eq_context {
268 __be32 mtt_base_addr_l;
270 __be32 consumer_index;
271 __be32 producer_index;
275 struct mlx4_cq_context {
279 __be32 logsize_usrpage;
287 __be32 mtt_base_addr_l;
288 __be32 last_notified_index;
289 __be32 solicit_producer_index;
290 __be32 consumer_index;
291 __be32 producer_index;
296 struct mlx4_srq_context {
297 __be32 state_logsize_srqn;
301 __be32 pg_offset_cqn;
306 __be32 mtt_base_addr_l;
308 __be16 limit_watermark;
349 } __packed port_change;
351 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
353 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
354 } __packed comm_channel_arm;
359 } __packed mac_update;
365 } __packed flr_event;
373 struct mlx4_dev *dev;
374 void __iomem *doorbell;
380 struct mlx4_buf_list *page_list;
384 struct mlx4_slave_eqe {
390 struct mlx4_slave_event_eq_info {
396 struct mlx4_profile {
410 struct mlx4_icm *fw_icm;
411 struct mlx4_icm *aux_icm;
425 MLX4_MCAST_CONFIG = 0,
426 MLX4_MCAST_DISABLE = 1,
427 MLX4_MCAST_ENABLE = 2,
430 #define VLAN_FLTR_SIZE 128
432 struct mlx4_vlan_fltr {
433 __be32 entry[VLAN_FLTR_SIZE];
436 struct mlx4_mcast_entry {
437 struct list_head list;
441 struct mlx4_promisc_qp {
442 struct list_head list;
446 struct mlx4_steer_index {
447 struct list_head list;
449 struct list_head duplicates;
452 struct mlx4_slave_state {
459 u16 mtu[MLX4_MAX_PORTS + 1];
460 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
461 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
462 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
463 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
464 struct mlx4_slave_event_eq_info event_eq;
468 /*initialized via the kzalloc*/
469 u8 is_slave_going_down;
475 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
478 struct mlx4_resource_tracker {
480 /* tree for each resources */
481 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
482 /* num_of_slave's lists, one per slave */
483 struct slave_list *slave_list;
486 #define SLAVE_EVENT_EQ_SIZE 128
487 struct mlx4_slave_event_eq {
491 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
494 struct mlx4_master_qp0_state {
495 int proxy_qp0_active;
500 struct mlx4_mfunc_master_ctx {
501 struct mlx4_slave_state *slave_state;
502 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
503 int init_port_ref[MLX4_MAX_PORTS + 1];
504 u16 max_mtu[MLX4_MAX_PORTS + 1];
505 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
506 struct mlx4_resource_tracker res_tracker;
507 struct workqueue_struct *comm_wq;
508 struct work_struct comm_work;
509 struct work_struct slave_event_work;
510 struct work_struct slave_flr_event_work;
511 spinlock_t slave_state_lock;
512 __be32 comm_arm_bit_vector[4];
513 struct mlx4_eqe cmd_eqe;
514 struct mlx4_slave_event_eq slave_eq;
515 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
519 struct mlx4_comm __iomem *comm;
520 struct mlx4_vhcr_cmd *vhcr;
523 struct mlx4_mfunc_master_ctx master;
527 struct pci_pool *pool;
529 struct mutex hcr_mutex;
530 struct semaphore poll_sem;
531 struct semaphore event_sem;
532 struct semaphore slave_sem;
534 spinlock_t context_lock;
536 struct mlx4_cmd_context *context;
543 struct mlx4_uar_table {
544 struct mlx4_bitmap bitmap;
547 struct mlx4_mr_table {
548 struct mlx4_bitmap mpt_bitmap;
549 struct mlx4_buddy mtt_buddy;
552 struct mlx4_icm_table mtt_table;
553 struct mlx4_icm_table dmpt_table;
556 struct mlx4_cq_table {
557 struct mlx4_bitmap bitmap;
559 struct radix_tree_root tree;
560 struct mlx4_icm_table table;
561 struct mlx4_icm_table cmpt_table;
564 struct mlx4_eq_table {
565 struct mlx4_bitmap bitmap;
567 void __iomem *clr_int;
568 void __iomem **uar_map;
571 struct mlx4_icm_table table;
572 struct mlx4_icm_table cmpt_table;
577 struct mlx4_srq_table {
578 struct mlx4_bitmap bitmap;
580 struct radix_tree_root tree;
581 struct mlx4_icm_table table;
582 struct mlx4_icm_table cmpt_table;
585 struct mlx4_qp_table {
586 struct mlx4_bitmap bitmap;
590 struct mlx4_icm_table qp_table;
591 struct mlx4_icm_table auxc_table;
592 struct mlx4_icm_table altc_table;
593 struct mlx4_icm_table rdmarc_table;
594 struct mlx4_icm_table cmpt_table;
597 struct mlx4_mcg_table {
599 struct mlx4_bitmap bitmap;
600 struct mlx4_icm_table table;
603 struct mlx4_catas_err {
605 struct timer_list timer;
606 struct list_head list;
609 #define MLX4_MAX_MAC_NUM 128
610 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
612 struct mlx4_mac_table {
613 __be64 entries[MLX4_MAX_MAC_NUM];
614 int refs[MLX4_MAX_MAC_NUM];
620 #define MLX4_MAX_VLAN_NUM 128
621 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
623 struct mlx4_vlan_table {
624 __be32 entries[MLX4_MAX_VLAN_NUM];
625 int refs[MLX4_MAX_VLAN_NUM];
631 #define SET_PORT_GEN_ALL_VALID 0x7
632 #define SET_PORT_PROMISC_SHIFT 31
633 #define SET_PORT_MC_PROMISC_SHIFT 30
636 MCAST_DIRECT_ONLY = 0,
642 struct mlx4_set_port_general_context {
655 struct mlx4_set_port_rqp_calc_context {
673 struct mlx4_mac_entry {
677 struct mlx4_port_info {
678 struct mlx4_dev *dev;
681 struct device_attribute port_attr;
682 enum mlx4_port_type tmp_type;
683 struct mlx4_mac_table mac_table;
684 struct radix_tree_root mac_tree;
685 struct mlx4_vlan_table vlan_table;
690 struct mlx4_dev *dev;
691 u8 do_sense_port[MLX4_MAX_PORTS + 1];
692 u8 sense_allowed[MLX4_MAX_PORTS + 1];
693 struct delayed_work sense_poll;
696 struct mlx4_msix_ctl {
698 spinlock_t pool_lock;
702 struct list_head promisc_qps[MLX4_NUM_STEERS];
703 struct list_head steer_entries[MLX4_NUM_STEERS];
704 struct list_head high_prios;
710 struct list_head dev_list;
711 struct list_head ctx_list;
714 struct list_head pgdir_list;
715 struct mutex pgdir_mutex;
719 struct mlx4_mfunc mfunc;
721 struct mlx4_bitmap pd_bitmap;
722 struct mlx4_bitmap xrcd_bitmap;
723 struct mlx4_uar_table uar_table;
724 struct mlx4_mr_table mr_table;
725 struct mlx4_cq_table cq_table;
726 struct mlx4_eq_table eq_table;
727 struct mlx4_srq_table srq_table;
728 struct mlx4_qp_table qp_table;
729 struct mlx4_mcg_table mcg_table;
730 struct mlx4_bitmap counters_bitmap;
732 struct mlx4_catas_err catas_err;
734 void __iomem *clr_base;
736 struct mlx4_uar driver_uar;
738 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
739 struct mlx4_sense sense;
740 struct mutex port_mutex;
741 struct mlx4_msix_ctl msix_ctl;
742 struct mlx4_steer *steer;
743 struct list_head bf_list;
744 struct mutex bf_mutex;
745 struct io_mapping *bf_mapping;
749 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
751 return container_of(dev, struct mlx4_priv, dev);
754 #define MLX4_SENSE_RANGE (HZ * 3)
756 extern struct workqueue_struct *mlx4_wq;
758 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
759 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
760 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
761 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
762 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
763 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
764 u32 reserved_bot, u32 resetrved_top);
765 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
767 int mlx4_reset(struct mlx4_dev *dev);
769 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
770 void mlx4_free_eq_table(struct mlx4_dev *dev);
772 int mlx4_init_pd_table(struct mlx4_dev *dev);
773 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
774 int mlx4_init_uar_table(struct mlx4_dev *dev);
775 int mlx4_init_mr_table(struct mlx4_dev *dev);
776 int mlx4_init_eq_table(struct mlx4_dev *dev);
777 int mlx4_init_cq_table(struct mlx4_dev *dev);
778 int mlx4_init_qp_table(struct mlx4_dev *dev);
779 int mlx4_init_srq_table(struct mlx4_dev *dev);
780 int mlx4_init_mcg_table(struct mlx4_dev *dev);
782 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
783 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
784 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
785 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
786 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
787 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
788 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
789 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
790 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
791 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
792 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
793 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
794 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
795 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
796 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
797 int __mlx4_mr_reserve(struct mlx4_dev *dev);
798 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
799 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
800 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
801 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
802 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
804 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
805 struct mlx4_vhcr *vhcr,
806 struct mlx4_cmd_mailbox *inbox,
807 struct mlx4_cmd_mailbox *outbox,
808 struct mlx4_cmd_info *cmd);
809 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
810 struct mlx4_vhcr *vhcr,
811 struct mlx4_cmd_mailbox *inbox,
812 struct mlx4_cmd_mailbox *outbox,
813 struct mlx4_cmd_info *cmd);
814 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
815 struct mlx4_vhcr *vhcr,
816 struct mlx4_cmd_mailbox *inbox,
817 struct mlx4_cmd_mailbox *outbox,
818 struct mlx4_cmd_info *cmd);
819 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
820 struct mlx4_vhcr *vhcr,
821 struct mlx4_cmd_mailbox *inbox,
822 struct mlx4_cmd_mailbox *outbox,
823 struct mlx4_cmd_info *cmd);
824 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
825 struct mlx4_vhcr *vhcr,
826 struct mlx4_cmd_mailbox *inbox,
827 struct mlx4_cmd_mailbox *outbox,
828 struct mlx4_cmd_info *cmd);
829 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
830 struct mlx4_vhcr *vhcr,
831 struct mlx4_cmd_mailbox *inbox,
832 struct mlx4_cmd_mailbox *outbox,
833 struct mlx4_cmd_info *cmd);
834 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
835 struct mlx4_vhcr *vhcr,
836 struct mlx4_cmd_mailbox *inbox,
837 struct mlx4_cmd_mailbox *outbox,
838 struct mlx4_cmd_info *cmd);
839 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
841 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
842 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
843 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
844 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
845 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
846 int start_index, int npages, u64 *page_list);
848 void mlx4_start_catas_poll(struct mlx4_dev *dev);
849 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
850 void mlx4_catas_init(void);
851 int mlx4_restart_one(struct pci_dev *pdev);
852 int mlx4_register_device(struct mlx4_dev *dev);
853 void mlx4_unregister_device(struct mlx4_dev *dev);
854 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
857 struct mlx4_init_hca_param;
859 u64 mlx4_make_profile(struct mlx4_dev *dev,
860 struct mlx4_profile *request,
861 struct mlx4_dev_cap *dev_cap,
862 struct mlx4_init_hca_param *init_hca);
863 void mlx4_master_comm_channel(struct work_struct *work);
864 void mlx4_gen_slave_eqe(struct work_struct *work);
865 void mlx4_master_handle_slave_flr(struct work_struct *work);
867 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
868 struct mlx4_vhcr *vhcr,
869 struct mlx4_cmd_mailbox *inbox,
870 struct mlx4_cmd_mailbox *outbox,
871 struct mlx4_cmd_info *cmd);
872 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd);
877 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
878 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
879 struct mlx4_cmd_mailbox *outbox,
880 struct mlx4_cmd_info *cmd);
881 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
882 struct mlx4_vhcr *vhcr,
883 struct mlx4_cmd_mailbox *inbox,
884 struct mlx4_cmd_mailbox *outbox,
885 struct mlx4_cmd_info *cmd);
886 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
887 struct mlx4_vhcr *vhcr,
888 struct mlx4_cmd_mailbox *inbox,
889 struct mlx4_cmd_mailbox *outbox,
890 struct mlx4_cmd_info *cmd);
891 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
892 struct mlx4_vhcr *vhcr,
893 struct mlx4_cmd_mailbox *inbox,
894 struct mlx4_cmd_mailbox *outbox,
895 struct mlx4_cmd_info *cmd);
896 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
897 struct mlx4_vhcr *vhcr,
898 struct mlx4_cmd_mailbox *inbox,
899 struct mlx4_cmd_mailbox *outbox,
900 struct mlx4_cmd_info *cmd);
901 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
902 struct mlx4_vhcr *vhcr,
903 struct mlx4_cmd_mailbox *inbox,
904 struct mlx4_cmd_mailbox *outbox,
905 struct mlx4_cmd_info *cmd);
906 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
907 struct mlx4_vhcr *vhcr,
908 struct mlx4_cmd_mailbox *inbox,
909 struct mlx4_cmd_mailbox *outbox,
910 struct mlx4_cmd_info *cmd);
911 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
912 struct mlx4_vhcr *vhcr,
913 struct mlx4_cmd_mailbox *inbox,
914 struct mlx4_cmd_mailbox *outbox,
915 struct mlx4_cmd_info *cmd);
916 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
917 struct mlx4_vhcr *vhcr,
918 struct mlx4_cmd_mailbox *inbox,
919 struct mlx4_cmd_mailbox *outbox,
920 struct mlx4_cmd_info *cmd);
921 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
922 struct mlx4_vhcr *vhcr,
923 struct mlx4_cmd_mailbox *inbox,
924 struct mlx4_cmd_mailbox *outbox,
925 struct mlx4_cmd_info *cmd);
926 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
927 struct mlx4_vhcr *vhcr,
928 struct mlx4_cmd_mailbox *inbox,
929 struct mlx4_cmd_mailbox *outbox,
930 struct mlx4_cmd_info *cmd);
931 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
932 struct mlx4_vhcr *vhcr,
933 struct mlx4_cmd_mailbox *inbox,
934 struct mlx4_cmd_mailbox *outbox,
935 struct mlx4_cmd_info *cmd);
936 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
937 struct mlx4_vhcr *vhcr,
938 struct mlx4_cmd_mailbox *inbox,
939 struct mlx4_cmd_mailbox *outbox,
940 struct mlx4_cmd_info *cmd);
941 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
942 struct mlx4_vhcr *vhcr,
943 struct mlx4_cmd_mailbox *inbox,
944 struct mlx4_cmd_mailbox *outbox,
945 struct mlx4_cmd_info *cmd);
946 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
947 struct mlx4_vhcr *vhcr,
948 struct mlx4_cmd_mailbox *inbox,
949 struct mlx4_cmd_mailbox *outbox,
950 struct mlx4_cmd_info *cmd);
951 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
952 struct mlx4_vhcr *vhcr,
953 struct mlx4_cmd_mailbox *inbox,
954 struct mlx4_cmd_mailbox *outbox,
955 struct mlx4_cmd_info *cmd);
957 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
959 int mlx4_cmd_init(struct mlx4_dev *dev);
960 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
961 int mlx4_multi_func_init(struct mlx4_dev *dev);
962 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
963 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
964 int mlx4_cmd_use_events(struct mlx4_dev *dev);
965 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
967 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
968 unsigned long timeout);
970 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
971 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
973 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
975 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
977 void mlx4_handle_catas_err(struct mlx4_dev *dev);
979 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
980 enum mlx4_port_type *type);
981 void mlx4_do_sense_ports(struct mlx4_dev *dev,
982 enum mlx4_port_type *stype,
983 enum mlx4_port_type *defaults);
984 void mlx4_start_sense(struct mlx4_dev *dev);
985 void mlx4_stop_sense(struct mlx4_dev *dev);
986 void mlx4_sense_init(struct mlx4_dev *dev);
987 int mlx4_check_port_params(struct mlx4_dev *dev,
988 enum mlx4_port_type *port_type);
989 int mlx4_change_port_types(struct mlx4_dev *dev,
990 enum mlx4_port_type *port_types);
992 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
993 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
995 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
996 /* resource tracker functions*/
997 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
998 enum mlx4_resource resource_type,
999 int resource_id, int *slave);
1000 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1001 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1003 void mlx4_free_resource_tracker(struct mlx4_dev *dev);
1005 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1006 struct mlx4_vhcr *vhcr,
1007 struct mlx4_cmd_mailbox *inbox,
1008 struct mlx4_cmd_mailbox *outbox,
1009 struct mlx4_cmd_info *cmd);
1010 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1011 struct mlx4_vhcr *vhcr,
1012 struct mlx4_cmd_mailbox *inbox,
1013 struct mlx4_cmd_mailbox *outbox,
1014 struct mlx4_cmd_info *cmd);
1015 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1016 struct mlx4_vhcr *vhcr,
1017 struct mlx4_cmd_mailbox *inbox,
1018 struct mlx4_cmd_mailbox *outbox,
1019 struct mlx4_cmd_info *cmd);
1020 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1021 struct mlx4_vhcr *vhcr,
1022 struct mlx4_cmd_mailbox *inbox,
1023 struct mlx4_cmd_mailbox *outbox,
1024 struct mlx4_cmd_info *cmd);
1025 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1026 int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
1029 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
1035 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1036 struct mlx4_vhcr *vhcr,
1037 struct mlx4_cmd_mailbox *inbox,
1038 struct mlx4_cmd_mailbox *outbox,
1039 struct mlx4_cmd_info *cmd);
1040 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1041 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1042 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1043 int block_mcast_loopback, enum mlx4_protocol prot,
1044 enum mlx4_steer_type steer);
1045 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1046 struct mlx4_vhcr *vhcr,
1047 struct mlx4_cmd_mailbox *inbox,
1048 struct mlx4_cmd_mailbox *outbox,
1049 struct mlx4_cmd_info *cmd);
1050 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1051 struct mlx4_vhcr *vhcr,
1052 struct mlx4_cmd_mailbox *inbox,
1053 struct mlx4_cmd_mailbox *outbox,
1054 struct mlx4_cmd_info *cmd);
1055 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1056 int port, void *buf);
1057 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1058 struct mlx4_cmd_mailbox *outbox);
1059 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1060 struct mlx4_vhcr *vhcr,
1061 struct mlx4_cmd_mailbox *inbox,
1062 struct mlx4_cmd_mailbox *outbox,
1063 struct mlx4_cmd_info *cmd);
1064 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1065 struct mlx4_vhcr *vhcr,
1066 struct mlx4_cmd_mailbox *inbox,
1067 struct mlx4_cmd_mailbox *outbox,
1068 struct mlx4_cmd_info *cmd);
1069 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
1075 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1076 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1078 static inline void set_param_l(u64 *arg, u32 val)
1080 *((u32 *)arg) = val;
1083 static inline void set_param_h(u64 *arg, u32 val)
1085 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1088 static inline u32 get_param_l(u64 *arg)
1090 return (u32) (*arg & 0xffffffff);
1093 static inline u32 get_param_h(u64 *arg)
1095 return (u32)(*arg >> 32);
1098 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1100 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1103 #define NOT_MASKED_PD_BITS 17