2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68 #define MLX4_RATELIMIT_DEFAULT 0xffff
70 struct mlx4_set_port_prio2tc_context {
74 struct mlx4_port_scheduler_tc_cfg_be {
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
90 MLX4_COMM_PAGESIZE = 0x1000,
91 MLX4_CLOCK_SIZE = 0x00008
95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
119 enum mlx4_mpt_state {
120 MLX4_MPT_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
153 MLX4_NUM_OF_RESOURCE_TYPE
156 enum mlx4_alloc_mode {
158 RES_OP_RESERVE_AND_MAP,
162 enum mlx4_res_tracker_free_type {
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
188 struct mlx4_vhcr_cmd {
199 struct mlx4_cmd_info {
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level (0)
217 #endif /* CONFIG_MLX4_DEBUG */
219 #define mlx4_dbg(mdev, format, arg...) \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225 #define mlx4_err(mdev, format, arg...) \
226 dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 dev_warn(&mdev->pdev->dev, format, ##arg)
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
246 unsigned long *table;
250 unsigned long **bits;
251 unsigned int *num_free;
258 struct mlx4_icm_table {
266 struct mlx4_icm **icm;
269 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
270 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
271 #define MLX4_MPT_FLAG_MIO (1 << 17)
272 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
273 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
274 #define MLX4_MPT_FLAG_REGION (1 << 8)
276 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
277 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
278 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
280 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
282 #define MLX4_MPT_STATUS_SW 0xF0
283 #define MLX4_MPT_STATUS_HW 0x00
286 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
288 struct mlx4_mpt_entry {
302 __be32 first_byte_offset;
306 * Must be packed because start is 64 bits but only aligned to 32 bits.
308 struct mlx4_eq_context {
322 __be32 mtt_base_addr_l;
324 __be32 consumer_index;
325 __be32 producer_index;
329 struct mlx4_cq_context {
333 __be32 logsize_usrpage;
341 __be32 mtt_base_addr_l;
342 __be32 last_notified_index;
343 __be32 solicit_producer_index;
344 __be32 consumer_index;
345 __be32 producer_index;
350 struct mlx4_srq_context {
351 __be32 state_logsize_srqn;
355 __be32 pg_offset_cqn;
360 __be32 mtt_base_addr_l;
362 __be16 limit_watermark;
371 struct mlx4_dev *dev;
372 void __iomem *doorbell;
378 struct mlx4_buf_list *page_list;
382 struct mlx4_slave_eqe {
388 struct mlx4_slave_event_eq_info {
393 struct mlx4_profile {
408 struct mlx4_icm *fw_icm;
409 struct mlx4_icm *aux_icm;
424 MLX4_MCAST_CONFIG = 0,
425 MLX4_MCAST_DISABLE = 1,
426 MLX4_MCAST_ENABLE = 2,
429 #define VLAN_FLTR_SIZE 128
431 struct mlx4_vlan_fltr {
432 __be32 entry[VLAN_FLTR_SIZE];
435 struct mlx4_mcast_entry {
436 struct list_head list;
440 struct mlx4_promisc_qp {
441 struct list_head list;
445 struct mlx4_steer_index {
446 struct list_head list;
448 struct list_head duplicates;
451 #define MLX4_EVENT_TYPES_NUM 64
453 struct mlx4_slave_state {
460 u16 mtu[MLX4_MAX_PORTS + 1];
461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
465 /* event type to eq number lookup */
466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
470 /*initialized via the kzalloc*/
471 u8 is_slave_going_down;
473 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
476 #define MLX4_VGT 4095
479 struct mlx4_vport_state {
488 struct mlx4_vf_admin_state {
489 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
492 struct mlx4_vport_oper_state {
493 struct mlx4_vport_state state;
497 struct mlx4_vf_oper_state {
498 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
503 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
506 struct mlx4_resource_tracker {
508 /* tree for each resources */
509 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
510 /* num_of_slave's lists, one per slave */
511 struct slave_list *slave_list;
514 #define SLAVE_EVENT_EQ_SIZE 128
515 struct mlx4_slave_event_eq {
519 spinlock_t event_lock;
520 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
523 struct mlx4_master_qp0_state {
524 int proxy_qp0_active;
529 struct mlx4_mfunc_master_ctx {
530 struct mlx4_slave_state *slave_state;
531 struct mlx4_vf_admin_state *vf_admin;
532 struct mlx4_vf_oper_state *vf_oper;
533 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
534 int init_port_ref[MLX4_MAX_PORTS + 1];
535 u16 max_mtu[MLX4_MAX_PORTS + 1];
536 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
537 struct mlx4_resource_tracker res_tracker;
538 struct workqueue_struct *comm_wq;
539 struct work_struct comm_work;
540 struct work_struct slave_event_work;
541 struct work_struct slave_flr_event_work;
542 spinlock_t slave_state_lock;
543 __be32 comm_arm_bit_vector[4];
544 struct mlx4_eqe cmd_eqe;
545 struct mlx4_slave_event_eq slave_eq;
546 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
550 struct mlx4_comm __iomem *comm;
551 struct mlx4_vhcr_cmd *vhcr;
554 struct mlx4_mfunc_master_ctx master;
558 struct pci_pool *pool;
560 struct mutex hcr_mutex;
561 struct mutex slave_cmd_mutex;
562 struct semaphore poll_sem;
563 struct semaphore event_sem;
565 spinlock_t context_lock;
567 struct mlx4_cmd_context *context;
575 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
576 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
578 struct mlx4_vf_immed_vlan_work {
579 struct work_struct work;
580 struct mlx4_priv *priv;
592 struct mlx4_uar_table {
593 struct mlx4_bitmap bitmap;
596 struct mlx4_mr_table {
597 struct mlx4_bitmap mpt_bitmap;
598 struct mlx4_buddy mtt_buddy;
601 struct mlx4_icm_table mtt_table;
602 struct mlx4_icm_table dmpt_table;
605 struct mlx4_cq_table {
606 struct mlx4_bitmap bitmap;
608 struct radix_tree_root tree;
609 struct mlx4_icm_table table;
610 struct mlx4_icm_table cmpt_table;
613 struct mlx4_eq_table {
614 struct mlx4_bitmap bitmap;
616 void __iomem *clr_int;
617 void __iomem **uar_map;
620 struct mlx4_icm_table table;
621 struct mlx4_icm_table cmpt_table;
626 struct mlx4_srq_table {
627 struct mlx4_bitmap bitmap;
629 struct radix_tree_root tree;
630 struct mlx4_icm_table table;
631 struct mlx4_icm_table cmpt_table;
634 struct mlx4_qp_table {
635 struct mlx4_bitmap bitmap;
639 struct mlx4_icm_table qp_table;
640 struct mlx4_icm_table auxc_table;
641 struct mlx4_icm_table altc_table;
642 struct mlx4_icm_table rdmarc_table;
643 struct mlx4_icm_table cmpt_table;
646 struct mlx4_mcg_table {
648 struct mlx4_bitmap bitmap;
649 struct mlx4_icm_table table;
652 struct mlx4_catas_err {
654 struct timer_list timer;
655 struct list_head list;
658 #define MLX4_MAX_MAC_NUM 128
659 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
661 struct mlx4_mac_table {
662 __be64 entries[MLX4_MAX_MAC_NUM];
663 int refs[MLX4_MAX_MAC_NUM];
669 #define MLX4_MAX_VLAN_NUM 128
670 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
672 struct mlx4_vlan_table {
673 __be32 entries[MLX4_MAX_VLAN_NUM];
674 int refs[MLX4_MAX_VLAN_NUM];
680 #define SET_PORT_GEN_ALL_VALID 0x7
681 #define SET_PORT_PROMISC_SHIFT 31
682 #define SET_PORT_MC_PROMISC_SHIFT 30
685 MCAST_DIRECT_ONLY = 0,
691 struct mlx4_set_port_general_context {
704 struct mlx4_set_port_rqp_calc_context {
722 struct mlx4_port_info {
723 struct mlx4_dev *dev;
726 struct device_attribute port_attr;
727 enum mlx4_port_type tmp_type;
728 char dev_mtu_name[16];
729 struct device_attribute port_mtu_attr;
730 struct mlx4_mac_table mac_table;
731 struct mlx4_vlan_table vlan_table;
736 struct mlx4_dev *dev;
737 u8 do_sense_port[MLX4_MAX_PORTS + 1];
738 u8 sense_allowed[MLX4_MAX_PORTS + 1];
739 struct delayed_work sense_poll;
742 struct mlx4_msix_ctl {
744 struct mutex pool_lock;
748 struct list_head promisc_qps[MLX4_NUM_STEERS];
749 struct list_head steer_entries[MLX4_NUM_STEERS];
753 MLX4_PCI_DEV_IS_VF = 1 << 0,
754 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
760 struct list_head dev_list;
761 struct list_head ctx_list;
766 struct list_head pgdir_list;
767 struct mutex pgdir_mutex;
771 struct mlx4_mfunc mfunc;
773 struct mlx4_bitmap pd_bitmap;
774 struct mlx4_bitmap xrcd_bitmap;
775 struct mlx4_uar_table uar_table;
776 struct mlx4_mr_table mr_table;
777 struct mlx4_cq_table cq_table;
778 struct mlx4_eq_table eq_table;
779 struct mlx4_srq_table srq_table;
780 struct mlx4_qp_table qp_table;
781 struct mlx4_mcg_table mcg_table;
782 struct mlx4_bitmap counters_bitmap;
784 struct mlx4_catas_err catas_err;
786 void __iomem *clr_base;
788 struct mlx4_uar driver_uar;
790 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
791 struct mlx4_sense sense;
792 struct mutex port_mutex;
793 struct mlx4_msix_ctl msix_ctl;
794 struct mlx4_steer *steer;
795 struct list_head bf_list;
796 struct mutex bf_mutex;
797 struct io_mapping *bf_mapping;
798 void __iomem *clock_mapping;
801 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
802 __be64 slave_node_guids[MLX4_MFUNC_MAX];
806 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
808 return container_of(dev, struct mlx4_priv, dev);
811 #define MLX4_SENSE_RANGE (HZ * 3)
813 extern struct workqueue_struct *mlx4_wq;
815 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
816 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
817 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
818 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
819 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
820 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
821 u32 reserved_bot, u32 resetrved_top);
822 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
824 int mlx4_reset(struct mlx4_dev *dev);
826 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
827 void mlx4_free_eq_table(struct mlx4_dev *dev);
829 int mlx4_init_pd_table(struct mlx4_dev *dev);
830 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
831 int mlx4_init_uar_table(struct mlx4_dev *dev);
832 int mlx4_init_mr_table(struct mlx4_dev *dev);
833 int mlx4_init_eq_table(struct mlx4_dev *dev);
834 int mlx4_init_cq_table(struct mlx4_dev *dev);
835 int mlx4_init_qp_table(struct mlx4_dev *dev);
836 int mlx4_init_srq_table(struct mlx4_dev *dev);
837 int mlx4_init_mcg_table(struct mlx4_dev *dev);
839 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
840 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
841 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
842 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
843 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
844 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
845 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
846 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
847 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
848 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
849 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
850 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
851 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
852 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
853 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
854 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
855 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
856 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
857 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
858 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
859 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
861 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
862 struct mlx4_vhcr *vhcr,
863 struct mlx4_cmd_mailbox *inbox,
864 struct mlx4_cmd_mailbox *outbox,
865 struct mlx4_cmd_info *cmd);
866 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd);
871 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
872 struct mlx4_vhcr *vhcr,
873 struct mlx4_cmd_mailbox *inbox,
874 struct mlx4_cmd_mailbox *outbox,
875 struct mlx4_cmd_info *cmd);
876 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
877 struct mlx4_vhcr *vhcr,
878 struct mlx4_cmd_mailbox *inbox,
879 struct mlx4_cmd_mailbox *outbox,
880 struct mlx4_cmd_info *cmd);
881 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
882 struct mlx4_vhcr *vhcr,
883 struct mlx4_cmd_mailbox *inbox,
884 struct mlx4_cmd_mailbox *outbox,
885 struct mlx4_cmd_info *cmd);
886 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
887 struct mlx4_vhcr *vhcr,
888 struct mlx4_cmd_mailbox *inbox,
889 struct mlx4_cmd_mailbox *outbox,
890 struct mlx4_cmd_info *cmd);
891 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
892 struct mlx4_vhcr *vhcr,
893 struct mlx4_cmd_mailbox *inbox,
894 struct mlx4_cmd_mailbox *outbox,
895 struct mlx4_cmd_info *cmd);
896 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
898 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
899 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
900 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
901 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
902 int start_index, int npages, u64 *page_list);
903 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
904 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
905 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
906 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
908 void mlx4_start_catas_poll(struct mlx4_dev *dev);
909 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
910 void mlx4_catas_init(void);
911 int mlx4_restart_one(struct pci_dev *pdev);
912 int mlx4_register_device(struct mlx4_dev *dev);
913 void mlx4_unregister_device(struct mlx4_dev *dev);
914 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
915 unsigned long param);
918 struct mlx4_init_hca_param;
920 u64 mlx4_make_profile(struct mlx4_dev *dev,
921 struct mlx4_profile *request,
922 struct mlx4_dev_cap *dev_cap,
923 struct mlx4_init_hca_param *init_hca);
924 void mlx4_master_comm_channel(struct work_struct *work);
925 void mlx4_gen_slave_eqe(struct work_struct *work);
926 void mlx4_master_handle_slave_flr(struct work_struct *work);
928 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr,
930 struct mlx4_cmd_mailbox *inbox,
931 struct mlx4_cmd_mailbox *outbox,
932 struct mlx4_cmd_info *cmd);
933 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
934 struct mlx4_vhcr *vhcr,
935 struct mlx4_cmd_mailbox *inbox,
936 struct mlx4_cmd_mailbox *outbox,
937 struct mlx4_cmd_info *cmd);
938 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
939 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr,
959 struct mlx4_cmd_mailbox *inbox,
960 struct mlx4_cmd_mailbox *outbox,
961 struct mlx4_cmd_info *cmd);
962 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd);
997 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1007 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1008 struct mlx4_vhcr *vhcr,
1009 struct mlx4_cmd_mailbox *inbox,
1010 struct mlx4_cmd_mailbox *outbox,
1011 struct mlx4_cmd_info *cmd);
1012 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1013 struct mlx4_vhcr *vhcr,
1014 struct mlx4_cmd_mailbox *inbox,
1015 struct mlx4_cmd_mailbox *outbox,
1016 struct mlx4_cmd_info *cmd);
1017 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1018 struct mlx4_vhcr *vhcr,
1019 struct mlx4_cmd_mailbox *inbox,
1020 struct mlx4_cmd_mailbox *outbox,
1021 struct mlx4_cmd_info *cmd);
1022 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1028 struct mlx4_vhcr *vhcr,
1029 struct mlx4_cmd_mailbox *inbox,
1030 struct mlx4_cmd_mailbox *outbox,
1031 struct mlx4_cmd_info *cmd);
1032 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd);
1037 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
1042 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1063 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1065 int mlx4_cmd_init(struct mlx4_dev *dev);
1066 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1067 int mlx4_multi_func_init(struct mlx4_dev *dev);
1068 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1069 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1070 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1071 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1073 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1074 unsigned long timeout);
1076 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1077 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1079 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1081 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1083 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1085 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1086 enum mlx4_port_type *type);
1087 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1088 enum mlx4_port_type *stype,
1089 enum mlx4_port_type *defaults);
1090 void mlx4_start_sense(struct mlx4_dev *dev);
1091 void mlx4_stop_sense(struct mlx4_dev *dev);
1092 void mlx4_sense_init(struct mlx4_dev *dev);
1093 int mlx4_check_port_params(struct mlx4_dev *dev,
1094 enum mlx4_port_type *port_type);
1095 int mlx4_change_port_types(struct mlx4_dev *dev,
1096 enum mlx4_port_type *port_types);
1098 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1099 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1100 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
1101 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1103 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1104 /* resource tracker functions*/
1105 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1106 enum mlx4_resource resource_type,
1107 u64 resource_id, int *slave);
1108 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1109 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1111 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1112 enum mlx4_res_tracker_free_type type);
1114 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1115 struct mlx4_vhcr *vhcr,
1116 struct mlx4_cmd_mailbox *inbox,
1117 struct mlx4_cmd_mailbox *outbox,
1118 struct mlx4_cmd_info *cmd);
1119 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1120 struct mlx4_vhcr *vhcr,
1121 struct mlx4_cmd_mailbox *inbox,
1122 struct mlx4_cmd_mailbox *outbox,
1123 struct mlx4_cmd_info *cmd);
1124 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1125 struct mlx4_vhcr *vhcr,
1126 struct mlx4_cmd_mailbox *inbox,
1127 struct mlx4_cmd_mailbox *outbox,
1128 struct mlx4_cmd_info *cmd);
1129 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1130 struct mlx4_vhcr *vhcr,
1131 struct mlx4_cmd_mailbox *inbox,
1132 struct mlx4_cmd_mailbox *outbox,
1133 struct mlx4_cmd_info *cmd);
1134 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1135 struct mlx4_vhcr *vhcr,
1136 struct mlx4_cmd_mailbox *inbox,
1137 struct mlx4_cmd_mailbox *outbox,
1138 struct mlx4_cmd_info *cmd);
1139 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1140 struct mlx4_vhcr *vhcr,
1141 struct mlx4_cmd_mailbox *inbox,
1142 struct mlx4_cmd_mailbox *outbox,
1143 struct mlx4_cmd_info *cmd);
1144 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1146 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1147 int *gid_tbl_len, int *pkey_tbl_len);
1149 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1150 struct mlx4_vhcr *vhcr,
1151 struct mlx4_cmd_mailbox *inbox,
1152 struct mlx4_cmd_mailbox *outbox,
1153 struct mlx4_cmd_info *cmd);
1155 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1156 struct mlx4_vhcr *vhcr,
1157 struct mlx4_cmd_mailbox *inbox,
1158 struct mlx4_cmd_mailbox *outbox,
1159 struct mlx4_cmd_info *cmd);
1160 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1161 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1162 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1163 int block_mcast_loopback, enum mlx4_protocol prot,
1164 enum mlx4_steer_type steer);
1165 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1166 u8 gid[16], u8 port,
1167 int block_mcast_loopback,
1168 enum mlx4_protocol prot, u64 *reg_id);
1169 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1170 struct mlx4_vhcr *vhcr,
1171 struct mlx4_cmd_mailbox *inbox,
1172 struct mlx4_cmd_mailbox *outbox,
1173 struct mlx4_cmd_info *cmd);
1174 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1175 struct mlx4_vhcr *vhcr,
1176 struct mlx4_cmd_mailbox *inbox,
1177 struct mlx4_cmd_mailbox *outbox,
1178 struct mlx4_cmd_info *cmd);
1179 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1180 int port, void *buf);
1181 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1182 struct mlx4_cmd_mailbox *outbox);
1183 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1184 struct mlx4_vhcr *vhcr,
1185 struct mlx4_cmd_mailbox *inbox,
1186 struct mlx4_cmd_mailbox *outbox,
1187 struct mlx4_cmd_info *cmd);
1188 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1189 struct mlx4_vhcr *vhcr,
1190 struct mlx4_cmd_mailbox *inbox,
1191 struct mlx4_cmd_mailbox *outbox,
1192 struct mlx4_cmd_info *cmd);
1193 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1194 struct mlx4_vhcr *vhcr,
1195 struct mlx4_cmd_mailbox *inbox,
1196 struct mlx4_cmd_mailbox *outbox,
1197 struct mlx4_cmd_info *cmd);
1198 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1199 struct mlx4_vhcr *vhcr,
1200 struct mlx4_cmd_mailbox *inbox,
1201 struct mlx4_cmd_mailbox *outbox,
1202 struct mlx4_cmd_info *cmd);
1203 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1204 struct mlx4_vhcr *vhcr,
1205 struct mlx4_cmd_mailbox *inbox,
1206 struct mlx4_cmd_mailbox *outbox,
1207 struct mlx4_cmd_info *cmd);
1209 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1210 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1212 static inline void set_param_l(u64 *arg, u32 val)
1214 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1217 static inline void set_param_h(u64 *arg, u32 val)
1219 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1222 static inline u32 get_param_l(u64 *arg)
1224 return (u32) (*arg & 0xffffffff);
1227 static inline u32 get_param_h(u64 *arg)
1229 return (u32)(*arg >> 32);
1232 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1234 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1237 #define NOT_MASKED_PD_BITS 17
1239 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);