2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/if_vlan.h>
36 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
42 #define MLX4_MAC_VALID (1ull << 63)
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
56 mutex_init(&table->mutex);
57 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
58 table->entries[i] = 0;
61 table->max = 1 << dev->caps.log_num_macs;
65 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
69 mutex_init(&table->mutex);
70 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
71 table->entries[i] = 0;
74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
78 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
79 struct mlx4_roce_gid_table *table)
83 mutex_init(&table->mutex);
84 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++)
85 memset(table->roce_gids[i].raw, 0, MLX4_ROCE_GID_ENTRY_SIZE);
88 static int validate_index(struct mlx4_dev *dev,
89 struct mlx4_mac_table *table, int index)
93 if (index < 0 || index >= table->max || !table->entries[index]) {
94 mlx4_warn(dev, "No valid Mac entry for the given index\n");
100 static int find_index(struct mlx4_dev *dev,
101 struct mlx4_mac_table *table, u64 mac)
105 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
106 if ((mac & MLX4_MAC_MASK) ==
107 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
114 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
117 struct mlx4_cmd_mailbox *mailbox;
121 mailbox = mlx4_alloc_cmd_mailbox(dev);
123 return PTR_ERR(mailbox);
125 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
127 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
129 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
130 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
132 mlx4_free_cmd_mailbox(dev, mailbox);
136 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx)
138 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
139 struct mlx4_mac_table *table = &info->mac_table;
142 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
146 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
154 EXPORT_SYMBOL_GPL(mlx4_find_cached_mac);
156 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
158 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
159 struct mlx4_mac_table *table = &info->mac_table;
163 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
164 (unsigned long long) mac, port);
166 mutex_lock(&table->mutex);
167 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
168 if (free < 0 && !table->entries[i]) {
173 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
174 /* MAC already registered, increment ref count */
181 mlx4_dbg(dev, "Free MAC index is %d\n", free);
183 if (table->total == table->max) {
184 /* No free mac entries */
189 /* Register new MAC */
190 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
192 err = mlx4_set_port_mac_table(dev, port, table->entries);
194 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
195 (unsigned long long) mac);
196 table->entries[free] = 0;
199 table->refs[free] = 1;
203 mutex_unlock(&table->mutex);
206 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
208 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
213 if (mlx4_is_mfunc(dev)) {
214 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
215 err = mlx4_cmd_imm(dev, mac, &out_param,
216 ((u32) port) << 8 | (u32) RES_MAC,
217 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
218 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
220 if (err && err == -EINVAL && mlx4_is_slave(dev)) {
221 /* retry using old REG_MAC format */
222 set_param_l(&out_param, port);
223 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
224 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
225 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
227 dev->flags |= MLX4_FLAG_OLD_REG_MAC;
232 return get_param_l(&out_param);
234 return __mlx4_register_mac(dev, port, mac);
236 EXPORT_SYMBOL_GPL(mlx4_register_mac);
238 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
240 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
241 (port - 1) * (1 << dev->caps.log_num_macs);
243 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
245 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
247 struct mlx4_port_info *info;
248 struct mlx4_mac_table *table;
251 if (port < 1 || port > dev->caps.num_ports) {
252 mlx4_warn(dev, "invalid port number (%d), aborting...\n", port);
255 info = &mlx4_priv(dev)->port[port];
256 table = &info->mac_table;
257 mutex_lock(&table->mutex);
258 index = find_index(dev, table, mac);
260 if (validate_index(dev, table, index))
262 if (--table->refs[index]) {
263 mlx4_dbg(dev, "Have more references for index %d, no need to modify mac table\n",
268 table->entries[index] = 0;
269 mlx4_set_port_mac_table(dev, port, table->entries);
272 mutex_unlock(&table->mutex);
274 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
276 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
280 if (mlx4_is_mfunc(dev)) {
281 if (!(dev->flags & MLX4_FLAG_OLD_REG_MAC)) {
282 (void) mlx4_cmd_imm(dev, mac, &out_param,
283 ((u32) port) << 8 | (u32) RES_MAC,
284 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
285 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
287 /* use old unregister mac format */
288 set_param_l(&out_param, port);
289 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
290 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
291 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
295 __mlx4_unregister_mac(dev, port, mac);
298 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
300 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
302 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
303 struct mlx4_mac_table *table = &info->mac_table;
304 int index = qpn - info->base_qpn;
307 /* CX1 doesn't support multi-functions */
308 mutex_lock(&table->mutex);
310 err = validate_index(dev, table, index);
314 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
316 err = mlx4_set_port_mac_table(dev, port, table->entries);
318 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
319 (unsigned long long) new_mac);
320 table->entries[index] = 0;
323 mutex_unlock(&table->mutex);
326 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
328 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
331 struct mlx4_cmd_mailbox *mailbox;
335 mailbox = mlx4_alloc_cmd_mailbox(dev);
337 return PTR_ERR(mailbox);
339 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
340 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
341 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
342 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
344 mlx4_free_cmd_mailbox(dev, mailbox);
349 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
351 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
354 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
355 if (table->refs[i] &&
356 (vid == (MLX4_VLAN_MASK &
357 be32_to_cpu(table->entries[i])))) {
358 /* VLAN already registered, increase reference count */
366 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
368 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
371 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
375 mutex_lock(&table->mutex);
377 if (table->total == table->max) {
378 /* No free vlan entries */
383 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
384 if (free < 0 && (table->refs[i] == 0)) {
389 if (table->refs[i] &&
390 (vlan == (MLX4_VLAN_MASK &
391 be32_to_cpu(table->entries[i])))) {
392 /* Vlan already registered, increase references count */
404 /* Register new VLAN */
405 table->refs[free] = 1;
406 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
408 err = mlx4_set_port_vlan_table(dev, port, table->entries);
410 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
411 table->refs[free] = 0;
412 table->entries[free] = 0;
419 mutex_unlock(&table->mutex);
423 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
431 if (mlx4_is_mfunc(dev)) {
432 err = mlx4_cmd_imm(dev, vlan, &out_param,
433 ((u32) port) << 8 | (u32) RES_VLAN,
434 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
435 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
437 *index = get_param_l(&out_param);
441 return __mlx4_register_vlan(dev, port, vlan, index);
443 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
445 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
447 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
450 mutex_lock(&table->mutex);
451 if (mlx4_find_cached_vlan(dev, port, vlan, &index)) {
452 mlx4_warn(dev, "vlan 0x%x is not in the vlan table\n", vlan);
456 if (index < MLX4_VLAN_REGULAR) {
457 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
461 if (--table->refs[index]) {
462 mlx4_dbg(dev, "Have %d more references for index %d, no need to modify vlan table\n",
463 table->refs[index], index);
466 table->entries[index] = 0;
467 mlx4_set_port_vlan_table(dev, port, table->entries);
470 mutex_unlock(&table->mutex);
473 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
477 if (mlx4_is_mfunc(dev)) {
478 (void) mlx4_cmd_imm(dev, vlan, &out_param,
479 ((u32) port) << 8 | (u32) RES_VLAN,
480 RES_OP_RESERVE_AND_MAP,
481 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
485 __mlx4_unregister_vlan(dev, port, vlan);
487 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
489 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
491 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
495 inmailbox = mlx4_alloc_cmd_mailbox(dev);
496 if (IS_ERR(inmailbox))
497 return PTR_ERR(inmailbox);
499 outmailbox = mlx4_alloc_cmd_mailbox(dev);
500 if (IS_ERR(outmailbox)) {
501 mlx4_free_cmd_mailbox(dev, inmailbox);
502 return PTR_ERR(outmailbox);
505 inbuf = inmailbox->buf;
506 outbuf = outmailbox->buf;
511 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
512 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
514 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
515 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
518 *caps = *(__be32 *) (outbuf + 84);
519 mlx4_free_cmd_mailbox(dev, inmailbox);
520 mlx4_free_cmd_mailbox(dev, outmailbox);
523 static struct mlx4_roce_gid_entry zgid_entry;
525 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port)
528 int slave_gid = slave;
530 struct mlx4_slaves_pport slaves_pport;
531 struct mlx4_active_ports actv_ports;
532 unsigned max_port_p_one;
535 return MLX4_ROCE_PF_GIDS;
538 slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
539 actv_ports = mlx4_get_active_ports(dev, slave);
540 max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) +
541 bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1;
543 for (i = 1; i < max_port_p_one; i++) {
544 struct mlx4_active_ports exclusive_ports;
545 struct mlx4_slaves_pport slaves_pport_actv;
546 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
547 set_bit(i - 1, exclusive_ports.ports);
550 slaves_pport_actv = mlx4_phys_to_slaves_pport_actv(
551 dev, &exclusive_ports);
552 slave_gid -= bitmap_weight(slaves_pport_actv.slaves,
555 vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1;
556 if (slave_gid <= ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) % vfs))
557 return ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs) + 1;
558 return (MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / vfs;
561 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port)
565 int slave_gid = slave;
568 struct mlx4_slaves_pport slaves_pport;
569 struct mlx4_active_ports actv_ports;
570 unsigned max_port_p_one;
575 slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
576 actv_ports = mlx4_get_active_ports(dev, slave);
577 max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) +
578 bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1;
580 for (i = 1; i < max_port_p_one; i++) {
581 struct mlx4_active_ports exclusive_ports;
582 struct mlx4_slaves_pport slaves_pport_actv;
583 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
584 set_bit(i - 1, exclusive_ports.ports);
587 slaves_pport_actv = mlx4_phys_to_slaves_pport_actv(
588 dev, &exclusive_ports);
589 slave_gid -= bitmap_weight(slaves_pport_actv.slaves,
592 gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
593 vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1;
594 if (slave_gid <= gids % vfs)
595 return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave_gid - 1);
597 return MLX4_ROCE_PF_GIDS + (gids % vfs) +
598 ((gids / vfs) * (slave_gid - 1));
600 EXPORT_SYMBOL_GPL(mlx4_get_base_gid_ix);
602 static int mlx4_reset_roce_port_gids(struct mlx4_dev *dev, int slave,
603 int port, struct mlx4_cmd_mailbox *mailbox)
605 struct mlx4_roce_gid_entry *gid_entry_mbox;
606 struct mlx4_priv *priv = mlx4_priv(dev);
607 int num_gids, base, offset;
610 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
611 base = mlx4_get_base_gid_ix(dev, slave, port);
613 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
615 mutex_lock(&(priv->port[port].gid_table.mutex));
616 /* Zero-out gids belonging to that slave in the port GID table */
617 for (i = 0, offset = base; i < num_gids; offset++, i++)
618 memcpy(priv->port[port].gid_table.roce_gids[offset].raw,
619 zgid_entry.raw, MLX4_ROCE_GID_ENTRY_SIZE);
621 /* Now, copy roce port gids table to mailbox for passing to FW */
622 gid_entry_mbox = (struct mlx4_roce_gid_entry *)mailbox->buf;
623 for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
624 memcpy(gid_entry_mbox->raw,
625 priv->port[port].gid_table.roce_gids[i].raw,
626 MLX4_ROCE_GID_ENTRY_SIZE);
628 err = mlx4_cmd(dev, mailbox->dma,
629 ((u32)port) | (MLX4_SET_PORT_GID_TABLE << 8), 1,
630 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
632 mutex_unlock(&(priv->port[port].gid_table.mutex));
637 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave)
639 struct mlx4_active_ports actv_ports;
640 struct mlx4_cmd_mailbox *mailbox;
641 int num_eth_ports, err;
644 if (slave < 0 || slave > dev->num_vfs)
647 actv_ports = mlx4_get_active_ports(dev, slave);
649 for (i = 0, num_eth_ports = 0; i < dev->caps.num_ports; i++) {
650 if (test_bit(i, actv_ports.ports)) {
651 if (dev->caps.port_type[i + 1] != MLX4_PORT_TYPE_ETH)
660 /* have ETH ports. Alloc mailbox for SET_PORT command */
661 mailbox = mlx4_alloc_cmd_mailbox(dev);
665 for (i = 0; i < dev->caps.num_ports; i++) {
666 if (test_bit(i, actv_ports.ports)) {
667 if (dev->caps.port_type[i + 1] != MLX4_PORT_TYPE_ETH)
669 err = mlx4_reset_roce_port_gids(dev, slave, i + 1, mailbox);
671 mlx4_warn(dev, "Could not reset ETH port GID table for slave %d, port %d (%d)\n",
676 mlx4_free_cmd_mailbox(dev, mailbox);
680 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
681 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
683 struct mlx4_priv *priv = mlx4_priv(dev);
684 struct mlx4_port_info *port_info;
685 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
686 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
687 struct mlx4_set_port_rqp_calc_context *qpn_context;
688 struct mlx4_set_port_general_context *gen_context;
689 struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1;
690 int reset_qkey_viols;
702 __be32 slave_cap_mask;
705 port = in_mod & 0xff;
706 in_modifier = in_mod >> 8;
708 port_info = &priv->port[port];
710 /* Slaves cannot perform SET_PORT operations except changing MTU */
712 if (slave != dev->caps.function &&
713 in_modifier != MLX4_SET_PORT_GENERAL &&
714 in_modifier != MLX4_SET_PORT_GID_TABLE) {
715 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
719 switch (in_modifier) {
720 case MLX4_SET_PORT_RQP_CALC:
721 qpn_context = inbox->buf;
722 qpn_context->base_qpn =
723 cpu_to_be32(port_info->base_qpn);
724 qpn_context->n_mac = 0x7;
725 promisc = be32_to_cpu(qpn_context->promisc) >>
726 SET_PORT_PROMISC_SHIFT;
727 qpn_context->promisc = cpu_to_be32(
728 promisc << SET_PORT_PROMISC_SHIFT |
729 port_info->base_qpn);
730 promisc = be32_to_cpu(qpn_context->mcast) >>
731 SET_PORT_MC_PROMISC_SHIFT;
732 qpn_context->mcast = cpu_to_be32(
733 promisc << SET_PORT_MC_PROMISC_SHIFT |
734 port_info->base_qpn);
736 case MLX4_SET_PORT_GENERAL:
737 gen_context = inbox->buf;
738 /* Mtu is configured as the max MTU among all the
739 * the functions on the port. */
740 mtu = be16_to_cpu(gen_context->mtu);
741 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port] +
742 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
743 prev_mtu = slave_st->mtu[port];
744 slave_st->mtu[port] = mtu;
745 if (mtu > master->max_mtu[port])
746 master->max_mtu[port] = mtu;
747 if (mtu < prev_mtu && prev_mtu ==
748 master->max_mtu[port]) {
749 slave_st->mtu[port] = mtu;
750 master->max_mtu[port] = mtu;
751 for (i = 0; i < dev->num_slaves; i++) {
752 master->max_mtu[port] =
753 max(master->max_mtu[port],
754 master->slave_state[i].mtu[port]);
758 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
760 case MLX4_SET_PORT_GID_TABLE:
761 /* change to MULTIPLE entries: number of guest's gids
762 * need a FOR-loop here over number of gids the guest has.
763 * 1. Check no duplicates in gids passed by slave
765 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
766 base = mlx4_get_base_gid_ix(dev, slave, port);
767 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
768 for (i = 0; i < num_gids; gid_entry_mbox++, i++) {
769 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
772 gid_entry_mb1 = gid_entry_mbox + 1;
773 for (j = i + 1; j < num_gids; gid_entry_mb1++, j++) {
774 if (!memcmp(gid_entry_mb1->raw,
775 zgid_entry.raw, sizeof(zgid_entry)))
777 if (!memcmp(gid_entry_mb1->raw, gid_entry_mbox->raw,
778 sizeof(gid_entry_mbox->raw))) {
779 /* found duplicate */
785 /* 2. Check that do not have duplicates in OTHER
786 * entries in the port GID table
789 mutex_lock(&(priv->port[port].gid_table.mutex));
790 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
791 if (i >= base && i < base + num_gids)
792 continue; /* don't compare to slave's current gids */
793 gid_entry_tbl = &priv->port[port].gid_table.roce_gids[i];
794 if (!memcmp(gid_entry_tbl->raw, zgid_entry.raw, sizeof(zgid_entry)))
796 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
797 for (j = 0; j < num_gids; gid_entry_mbox++, j++) {
798 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
801 if (!memcmp(gid_entry_mbox->raw, gid_entry_tbl->raw,
802 sizeof(gid_entry_tbl->raw))) {
803 /* found duplicate */
804 mlx4_warn(dev, "requested gid entry for slave:%d is a duplicate of gid at index %d\n",
806 mutex_unlock(&(priv->port[port].gid_table.mutex));
812 /* insert slave GIDs with memcpy, starting at slave's base index */
813 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
814 for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++)
815 memcpy(priv->port[port].gid_table.roce_gids[offset].raw,
816 gid_entry_mbox->raw, MLX4_ROCE_GID_ENTRY_SIZE);
818 /* Now, copy roce port gids table to current mailbox for passing to FW */
819 gid_entry_mbox = (struct mlx4_roce_gid_entry *)(inbox->buf);
820 for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
821 memcpy(gid_entry_mbox->raw,
822 priv->port[port].gid_table.roce_gids[i].raw,
823 MLX4_ROCE_GID_ENTRY_SIZE);
825 err = mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
826 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
828 mutex_unlock(&(priv->port[port].gid_table.mutex));
832 return mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
833 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
837 /* For IB, we only consider:
838 * - The capability mask, which is set to the aggregate of all
839 * slave function capabilities
840 * - The QKey violatin counter - reset according to each request.
843 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
844 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
845 new_cap_mask = ((__be32 *) inbox->buf)[2];
847 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
848 new_cap_mask = ((__be32 *) inbox->buf)[1];
851 /* slave may not set the IS_SM capability for the port */
852 if (slave != mlx4_master_func_num(dev) &&
853 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
856 /* No DEV_MGMT in multifunc mode */
857 if (mlx4_is_mfunc(dev) &&
858 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
863 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
864 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
865 for (i = 0; i < dev->num_slaves; i++)
867 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
869 /* only clear mailbox for guests. Master may be setting
870 * MTU or PKEY table size
872 if (slave != dev->caps.function)
873 memset(inbox->buf, 0, 256);
874 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
875 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
876 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
878 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
879 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
882 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
883 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
885 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
890 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
891 struct mlx4_vhcr *vhcr,
892 struct mlx4_cmd_mailbox *inbox,
893 struct mlx4_cmd_mailbox *outbox,
894 struct mlx4_cmd_info *cmd)
896 int port = mlx4_slave_convert_port(
897 dev, slave, vhcr->in_modifier & 0xFF);
902 vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) |
905 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
906 vhcr->op_modifier, inbox);
909 /* bit locations for set port command with zero op modifier */
911 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
912 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
913 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
914 MLX4_CHANGE_PORT_VL_CAP = 21,
915 MLX4_CHANGE_PORT_MTU_CAP = 22,
918 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
920 struct mlx4_cmd_mailbox *mailbox;
921 int err, vl_cap, pkey_tbl_flag = 0;
923 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
926 mailbox = mlx4_alloc_cmd_mailbox(dev);
928 return PTR_ERR(mailbox);
930 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
932 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
934 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
937 /* IB VL CAP enum isn't used by the firmware, just numerical values */
938 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
939 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
940 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
941 (1 << MLX4_CHANGE_PORT_VL_CAP) |
942 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
943 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
944 (vl_cap << MLX4_SET_PORT_VL_CAP));
945 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
946 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
951 mlx4_free_cmd_mailbox(dev, mailbox);
955 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
956 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
958 struct mlx4_cmd_mailbox *mailbox;
959 struct mlx4_set_port_general_context *context;
963 mailbox = mlx4_alloc_cmd_mailbox(dev);
965 return PTR_ERR(mailbox);
966 context = mailbox->buf;
967 context->flags = SET_PORT_GEN_ALL_VALID;
968 context->mtu = cpu_to_be16(mtu);
969 context->pptx = (pptx * (!pfctx)) << 7;
970 context->pfctx = pfctx;
971 context->pprx = (pprx * (!pfcrx)) << 7;
972 context->pfcrx = pfcrx;
974 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
975 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
976 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
978 mlx4_free_cmd_mailbox(dev, mailbox);
981 EXPORT_SYMBOL(mlx4_SET_PORT_general);
983 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
986 struct mlx4_cmd_mailbox *mailbox;
987 struct mlx4_set_port_rqp_calc_context *context;
990 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
991 MCAST_DIRECT : MCAST_DEFAULT;
993 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
996 mailbox = mlx4_alloc_cmd_mailbox(dev);
998 return PTR_ERR(mailbox);
999 context = mailbox->buf;
1000 context->base_qpn = cpu_to_be32(base_qpn);
1001 context->n_mac = dev->caps.log_num_macs;
1002 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
1004 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
1006 context->intra_no_vlan = 0;
1007 context->no_vlan = MLX4_NO_VLAN_IDX;
1008 context->intra_vlan_miss = 0;
1009 context->vlan_miss = MLX4_VLAN_MISS_IDX;
1011 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
1012 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
1013 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
1015 mlx4_free_cmd_mailbox(dev, mailbox);
1018 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
1020 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
1022 struct mlx4_cmd_mailbox *mailbox;
1023 struct mlx4_set_port_prio2tc_context *context;
1028 mailbox = mlx4_alloc_cmd_mailbox(dev);
1029 if (IS_ERR(mailbox))
1030 return PTR_ERR(mailbox);
1031 context = mailbox->buf;
1032 for (i = 0; i < MLX4_NUM_UP; i += 2)
1033 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
1035 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
1036 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
1037 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1039 mlx4_free_cmd_mailbox(dev, mailbox);
1042 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
1044 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1045 u8 *pg, u16 *ratelimit)
1047 struct mlx4_cmd_mailbox *mailbox;
1048 struct mlx4_set_port_scheduler_context *context;
1053 mailbox = mlx4_alloc_cmd_mailbox(dev);
1054 if (IS_ERR(mailbox))
1055 return PTR_ERR(mailbox);
1056 context = mailbox->buf;
1058 for (i = 0; i < MLX4_NUM_TC; i++) {
1059 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
1062 if (ratelimit && ratelimit[i]) {
1063 if (ratelimit[i] <= MLX4_MAX_100M_UNITS_VAL) {
1066 htons(MLX4_RATELIMIT_100M_UNITS);
1068 r = ratelimit[i]/10;
1070 htons(MLX4_RATELIMIT_1G_UNITS);
1072 tc->max_bw_value = htons(r);
1074 tc->max_bw_value = htons(MLX4_RATELIMIT_DEFAULT);
1075 tc->max_bw_units = htons(MLX4_RATELIMIT_1G_UNITS);
1078 tc->pg = htons(pg[i]);
1079 tc->bw_precentage = htons(tc_tx_bw[i]);
1082 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
1083 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
1084 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1086 mlx4_free_cmd_mailbox(dev, mailbox);
1089 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
1092 VXLAN_ENABLE_MODIFY = 1 << 7,
1093 VXLAN_STEERING_MODIFY = 1 << 6,
1095 VXLAN_ENABLE = 1 << 7,
1098 struct mlx4_set_port_vxlan_context {
1106 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable)
1110 struct mlx4_cmd_mailbox *mailbox;
1111 struct mlx4_set_port_vxlan_context *context;
1113 mailbox = mlx4_alloc_cmd_mailbox(dev);
1114 if (IS_ERR(mailbox))
1115 return PTR_ERR(mailbox);
1116 context = mailbox->buf;
1117 memset(context, 0, sizeof(*context));
1119 context->modify_flags = VXLAN_ENABLE_MODIFY | VXLAN_STEERING_MODIFY;
1121 context->enable_flags = VXLAN_ENABLE;
1122 context->steering = steering;
1124 in_mod = MLX4_SET_PORT_VXLAN << 8 | port;
1125 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
1126 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1128 mlx4_free_cmd_mailbox(dev, mailbox);
1131 EXPORT_SYMBOL(mlx4_SET_PORT_VXLAN);
1133 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1134 struct mlx4_vhcr *vhcr,
1135 struct mlx4_cmd_mailbox *inbox,
1136 struct mlx4_cmd_mailbox *outbox,
1137 struct mlx4_cmd_info *cmd)
1144 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
1145 u64 mac, u64 clear, u8 mode)
1147 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
1148 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
1151 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
1153 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1154 struct mlx4_vhcr *vhcr,
1155 struct mlx4_cmd_mailbox *inbox,
1156 struct mlx4_cmd_mailbox *outbox,
1157 struct mlx4_cmd_info *cmd)
1164 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
1165 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
1167 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
1168 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
1172 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1173 struct mlx4_vhcr *vhcr,
1174 struct mlx4_cmd_mailbox *inbox,
1175 struct mlx4_cmd_mailbox *outbox,
1176 struct mlx4_cmd_info *cmd)
1178 if (slave != dev->caps.function)
1180 return mlx4_common_dump_eth_stats(dev, slave,
1181 vhcr->in_modifier, outbox);
1184 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
1186 if (!mlx4_is_mfunc(dev)) {
1191 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
1192 MLX4_STATS_TRAFFIC_DROPS_MASK |
1193 MLX4_STATS_PORT_COUNTERS_MASK);
1195 if (mlx4_is_master(dev))
1196 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
1198 EXPORT_SYMBOL(mlx4_set_stats_bitmap);
1200 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1203 struct mlx4_priv *priv = mlx4_priv(dev);
1204 int i, found_ix = -1;
1205 int vf_gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1206 struct mlx4_slaves_pport slaves_pport;
1210 if (!mlx4_is_mfunc(dev))
1213 slaves_pport = mlx4_phys_to_slaves_pport(dev, port);
1214 num_vfs = bitmap_weight(slaves_pport.slaves, dev->num_vfs + 1) - 1;
1216 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
1217 if (!memcmp(priv->port[port].gid_table.roce_gids[i].raw, gid,
1218 MLX4_ROCE_GID_ENTRY_SIZE)) {
1224 if (found_ix >= 0) {
1225 /* Calculate a slave_gid which is the slave number in the gid
1226 * table and not a globally unique slave number.
1228 if (found_ix < MLX4_ROCE_PF_GIDS)
1230 else if (found_ix < MLX4_ROCE_PF_GIDS + (vf_gids % num_vfs) *
1231 (vf_gids / num_vfs + 1))
1232 slave_gid = ((found_ix - MLX4_ROCE_PF_GIDS) /
1233 (vf_gids / num_vfs + 1)) + 1;
1236 ((found_ix - MLX4_ROCE_PF_GIDS -
1237 ((vf_gids % num_vfs) * ((vf_gids / num_vfs + 1)))) /
1238 (vf_gids / num_vfs)) + vf_gids % num_vfs + 1;
1240 /* Calculate the globally unique slave id */
1242 struct mlx4_active_ports exclusive_ports;
1243 struct mlx4_active_ports actv_ports;
1244 struct mlx4_slaves_pport slaves_pport_actv;
1245 unsigned max_port_p_one;
1246 int num_vfs_before = 0;
1247 int candidate_slave_gid;
1249 /* Calculate how many VFs are on the previous port, if exists */
1250 for (i = 1; i < port; i++) {
1251 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports);
1252 set_bit(i - 1, exclusive_ports.ports);
1254 mlx4_phys_to_slaves_pport_actv(
1255 dev, &exclusive_ports);
1256 num_vfs_before += bitmap_weight(
1257 slaves_pport_actv.slaves,
1261 /* candidate_slave_gid isn't necessarily the correct slave, but
1262 * it has the same number of ports and is assigned to the same
1263 * ports as the real slave we're looking for. On dual port VF,
1264 * slave_gid = [single port VFs on port <port>] +
1265 * [offset of the current slave from the first dual port VF] +
1268 candidate_slave_gid = slave_gid + num_vfs_before;
1270 actv_ports = mlx4_get_active_ports(dev, candidate_slave_gid);
1271 max_port_p_one = find_first_bit(
1272 actv_ports.ports, dev->caps.num_ports) +
1273 bitmap_weight(actv_ports.ports,
1274 dev->caps.num_ports) + 1;
1276 /* Calculate the real slave number */
1277 for (i = 1; i < max_port_p_one; i++) {
1280 bitmap_zero(exclusive_ports.ports,
1281 dev->caps.num_ports);
1282 set_bit(i - 1, exclusive_ports.ports);
1284 mlx4_phys_to_slaves_pport_actv(
1285 dev, &exclusive_ports);
1286 slave_gid += bitmap_weight(
1287 slaves_pport_actv.slaves,
1291 *slave_id = slave_gid;
1294 return (found_ix >= 0) ? 0 : -EINVAL;
1296 EXPORT_SYMBOL(mlx4_get_slave_from_roce_gid);
1298 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1301 struct mlx4_priv *priv = mlx4_priv(dev);
1303 if (!mlx4_is_master(dev))
1306 memcpy(gid, priv->port[port].gid_table.roce_gids[slave_id].raw,
1307 MLX4_ROCE_GID_ENTRY_SIZE);
1310 EXPORT_SYMBOL(mlx4_get_roce_gid_from_slave);