2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/gfp.h>
37 #include <linux/export.h>
38 #include <linux/mlx4/cmd.h>
39 #include <linux/mlx4/qp.h>
44 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
46 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
49 spin_lock(&qp_table->lock);
51 qp = __mlx4_qp_lookup(dev, qpn);
53 atomic_inc(&qp->refcount);
55 spin_unlock(&qp_table->lock);
58 mlx4_warn(dev, "Async event for bogus QP %08x\n", qpn);
62 qp->event(qp, event_type);
64 if (atomic_dec_and_test(&qp->refcount))
68 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
69 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
70 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
71 int sqd_event, struct mlx4_qp *qp)
73 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
74 [MLX4_QP_STATE_RST] = {
75 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
76 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
77 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP,
79 [MLX4_QP_STATE_INIT] = {
80 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
81 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
82 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP,
83 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP,
85 [MLX4_QP_STATE_RTR] = {
86 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
87 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
88 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP,
90 [MLX4_QP_STATE_RTS] = {
91 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
92 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
93 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP,
94 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP,
96 [MLX4_QP_STATE_SQD] = {
97 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
98 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
99 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP,
100 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP,
102 [MLX4_QP_STATE_SQER] = {
103 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
104 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
105 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP,
107 [MLX4_QP_STATE_ERR] = {
108 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
109 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
113 struct mlx4_cmd_mailbox *mailbox;
116 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
117 !op[cur_state][new_state])
120 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP)
121 return mlx4_cmd(dev, 0, qp->qpn, 2,
122 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A,
125 mailbox = mlx4_alloc_cmd_mailbox(dev);
127 return PTR_ERR(mailbox);
129 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
130 u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
131 context->mtt_base_addr_h = mtt_addr >> 32;
132 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
133 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
136 *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
137 memcpy(mailbox->buf + 8, context, sizeof *context);
139 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
140 cpu_to_be32(qp->qpn);
142 ret = mlx4_cmd(dev, mailbox->dma, qp->qpn | (!!sqd_event << 31),
143 new_state == MLX4_QP_STATE_RST ? 2 : 0,
144 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C,
147 mlx4_free_cmd_mailbox(dev, mailbox);
150 EXPORT_SYMBOL_GPL(mlx4_qp_modify);
152 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base)
154 struct mlx4_priv *priv = mlx4_priv(dev);
155 struct mlx4_qp_table *qp_table = &priv->qp_table;
158 qpn = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align);
165 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
167 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
169 struct mlx4_priv *priv = mlx4_priv(dev);
170 struct mlx4_qp_table *qp_table = &priv->qp_table;
171 if (base_qpn < dev->caps.sqp_start + 8)
174 mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt);
176 EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
178 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp)
180 struct mlx4_priv *priv = mlx4_priv(dev);
181 struct mlx4_qp_table *qp_table = &priv->qp_table;
189 err = mlx4_table_get(dev, &qp_table->qp_table, qp->qpn);
193 err = mlx4_table_get(dev, &qp_table->auxc_table, qp->qpn);
197 err = mlx4_table_get(dev, &qp_table->altc_table, qp->qpn);
201 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qp->qpn);
205 err = mlx4_table_get(dev, &qp_table->cmpt_table, qp->qpn);
209 spin_lock_irq(&qp_table->lock);
210 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1), qp);
211 spin_unlock_irq(&qp_table->lock);
215 atomic_set(&qp->refcount, 1);
216 init_completion(&qp->free);
221 mlx4_table_put(dev, &qp_table->cmpt_table, qp->qpn);
224 mlx4_table_put(dev, &qp_table->rdmarc_table, qp->qpn);
227 mlx4_table_put(dev, &qp_table->altc_table, qp->qpn);
230 mlx4_table_put(dev, &qp_table->auxc_table, qp->qpn);
233 mlx4_table_put(dev, &qp_table->qp_table, qp->qpn);
238 EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
240 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
242 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
245 spin_lock_irqsave(&qp_table->lock, flags);
246 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
247 spin_unlock_irqrestore(&qp_table->lock, flags);
249 EXPORT_SYMBOL_GPL(mlx4_qp_remove);
251 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
253 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
255 if (atomic_dec_and_test(&qp->refcount))
257 wait_for_completion(&qp->free);
259 mlx4_table_put(dev, &qp_table->cmpt_table, qp->qpn);
260 mlx4_table_put(dev, &qp_table->rdmarc_table, qp->qpn);
261 mlx4_table_put(dev, &qp_table->altc_table, qp->qpn);
262 mlx4_table_put(dev, &qp_table->auxc_table, qp->qpn);
263 mlx4_table_put(dev, &qp_table->qp_table, qp->qpn);
265 EXPORT_SYMBOL_GPL(mlx4_qp_free);
267 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
269 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
270 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
273 int mlx4_init_qp_table(struct mlx4_dev *dev)
275 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
277 int reserved_from_top = 0;
279 spin_lock_init(&qp_table->lock);
280 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
283 * We reserve 2 extra QPs per port for the special QPs. The
284 * block of special QPs must be aligned to a multiple of 8, so
287 * We also reserve the MSB of the 24-bit QP number to indicate
288 * that a QP is an XRC QP.
290 dev->caps.sqp_start =
291 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8);
294 int sort[MLX4_NUM_QP_REGION];
296 int last_base = dev->caps.num_qps;
298 for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
301 for (i = MLX4_NUM_QP_REGION; i > 0; --i) {
302 for (j = 2; j < i; ++j) {
303 if (dev->caps.reserved_qps_cnt[sort[j]] >
304 dev->caps.reserved_qps_cnt[sort[j - 1]]) {
306 sort[j] = sort[j - 1];
312 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) {
313 last_base -= dev->caps.reserved_qps_cnt[sort[i]];
314 dev->caps.reserved_qps_base[sort[i]] = last_base;
316 dev->caps.reserved_qps_cnt[sort[i]];
321 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps,
322 (1 << 23) - 1, dev->caps.sqp_start + 8,
327 return mlx4_CONF_SPECIAL_QP(dev, dev->caps.sqp_start);
330 void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
332 mlx4_CONF_SPECIAL_QP(dev, 0);
333 mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap);
336 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
337 struct mlx4_qp_context *context)
339 struct mlx4_cmd_mailbox *mailbox;
342 mailbox = mlx4_alloc_cmd_mailbox(dev);
344 return PTR_ERR(mailbox);
346 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
347 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
350 memcpy(context, mailbox->buf + 8, sizeof *context);
352 mlx4_free_cmd_mailbox(dev, mailbox);
355 EXPORT_SYMBOL_GPL(mlx4_qp_query);
357 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
358 struct mlx4_qp_context *context,
359 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
363 enum mlx4_qp_state states[] = {
370 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
371 context->flags &= cpu_to_be32(~(0xf << 28));
372 context->flags |= cpu_to_be32(states[i + 1] << 28);
373 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
376 mlx4_err(dev, "Failed to bring QP to state: "
377 "%d with error: %d\n",
382 *qp_state = states[i + 1];
387 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);