drivers/net/ethernet/mellanox/mlx4/resource_tracker.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
   4  * All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/sched.h>
  37 #include <linux/pci.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/io.h>
  41 #include <linux/slab.h>
  42 #include <linux/mlx4/cmd.h>
  43 #include <linux/mlx4/qp.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/etherdevice.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49
  50 #define MLX4_MAC_VALID          (1ull << 63)
  51
  52 struct mac_res {
  53         struct list_head list;
  54         u64 mac;
  55         u8 port;
  56 };
  57
  58 struct res_common {
  59         struct list_head        list;
  60         struct rb_node          node;
  61         u64                     res_id;
  62         int                     owner;
  63         int                     state;
  64         int                     from_state;
  65         int                     to_state;
  66         int                     removing;
  67 };
  68
  69 enum {
  70         RES_ANY_BUSY = 1
  71 };
  72
  73 struct res_gid {
  74         struct list_head        list;
  75         u8                      gid[16];
  76         enum mlx4_protocol      prot;
  77         enum mlx4_steer_type    steer;
  78         u64                     reg_id;
  79 };
  80
  81 enum res_qp_states {
  82         RES_QP_BUSY = RES_ANY_BUSY,
  83
  84         /* QP number was allocated */
  85         RES_QP_RESERVED,
  86
  87         /* ICM memory for QP context was mapped */
  88         RES_QP_MAPPED,
  89
  90         /* QP is in hw ownership */
  91         RES_QP_HW
  92 };
  93
  94 struct res_qp {
  95         struct res_common       com;
  96         struct res_mtt         *mtt;
  97         struct res_cq          *rcq;
  98         struct res_cq          *scq;
  99         struct res_srq         *srq;
 100         struct list_head        mcg_list;
 101         spinlock_t              mcg_spl;
 102         int                     local_qpn;
 103         atomic_t                ref_count;
 104         u32                     qpc_flags;
 105         u8                      sched_queue;
 106 };
 107
 108 enum res_mtt_states {
 109         RES_MTT_BUSY = RES_ANY_BUSY,
 110         RES_MTT_ALLOCATED,
 111 };
 112
 113 static inline const char *mtt_states_str(enum res_mtt_states state)
 114 {
 115         switch (state) {
 116         case RES_MTT_BUSY: return "RES_MTT_BUSY";
 117         case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
 118         default: return "Unknown";
 119         }
 120 }
 121
 122 struct res_mtt {
 123         struct res_common       com;
 124         int                     order;
 125         atomic_t                ref_count;
 126 };
 127
 128 enum res_mpt_states {
 129         RES_MPT_BUSY = RES_ANY_BUSY,
 130         RES_MPT_RESERVED,
 131         RES_MPT_MAPPED,
 132         RES_MPT_HW,
 133 };
 134
 135 struct res_mpt {
 136         struct res_common       com;
 137         struct res_mtt         *mtt;
 138         int                     key;
 139 };
 140
 141 enum res_eq_states {
 142         RES_EQ_BUSY = RES_ANY_BUSY,
 143         RES_EQ_RESERVED,
 144         RES_EQ_HW,
 145 };
 146
 147 struct res_eq {
 148         struct res_common       com;
 149         struct res_mtt         *mtt;
 150 };
 151
 152 enum res_cq_states {
 153         RES_CQ_BUSY = RES_ANY_BUSY,
 154         RES_CQ_ALLOCATED,
 155         RES_CQ_HW,
 156 };
 157
 158 struct res_cq {
 159         struct res_common       com;
 160         struct res_mtt         *mtt;
 161         atomic_t                ref_count;
 162 };
 163
 164 enum res_srq_states {
 165         RES_SRQ_BUSY = RES_ANY_BUSY,
 166         RES_SRQ_ALLOCATED,
 167         RES_SRQ_HW,
 168 };
 169
 170 struct res_srq {
 171         struct res_common       com;
 172         struct res_mtt         *mtt;
 173         struct res_cq          *cq;
 174         atomic_t                ref_count;
 175 };
 176
 177 enum res_counter_states {
 178         RES_COUNTER_BUSY = RES_ANY_BUSY,
 179         RES_COUNTER_ALLOCATED,
 180 };
 181
 182 struct res_counter {
 183         struct res_common       com;
 184         int                     port;
 185 };
 186
 187 enum res_xrcdn_states {
 188         RES_XRCD_BUSY = RES_ANY_BUSY,
 189         RES_XRCD_ALLOCATED,
 190 };
 191
 192 struct res_xrcdn {
 193         struct res_common       com;
 194         int                     port;
 195 };
 196
 197 enum res_fs_rule_states {
 198         RES_FS_RULE_BUSY = RES_ANY_BUSY,
 199         RES_FS_RULE_ALLOCATED,
 200 };
 201
 202 struct res_fs_rule {
 203         struct res_common       com;
 204         int                     qpn;
 205 };
 206
 207 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
 208 {
 209         struct rb_node *node = root->rb_node;
 210
 211         while (node) {
 212                 struct res_common *res = container_of(node, struct res_common,
 213                                                       node);
 214
 215                 if (res_id < res->res_id)
 216                         node = node->rb_left;
 217                 else if (res_id > res->res_id)
 218                         node = node->rb_right;
 219                 else
 220                         return res;
 221         }
 222         return NULL;
 223 }
 224
 225 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
 226 {
 227         struct rb_node **new = &(root->rb_node), *parent = NULL;
 228
 229         /* Figure out where to put new node */
 230         while (*new) {
 231                 struct res_common *this = container_of(*new, struct res_common,
 232                                                        node);
 233
 234                 parent = *new;
 235                 if (res->res_id < this->res_id)
 236                         new = &((*new)->rb_left);
 237                 else if (res->res_id > this->res_id)
 238                         new = &((*new)->rb_right);
 239                 else
 240                         return -EEXIST;
 241         }
 242
 243         /* Add new node and rebalance tree. */
 244         rb_link_node(&res->node, parent, new);
 245         rb_insert_color(&res->node, root);
 246
 247         return 0;
 248 }
 249
 250 enum qp_transition {
 251         QP_TRANS_INIT2RTR,
 252         QP_TRANS_RTR2RTS,
 253         QP_TRANS_RTS2RTS,
 254         QP_TRANS_SQERR2RTS,
 255         QP_TRANS_SQD2SQD,
 256         QP_TRANS_SQD2RTS
 257 };
 258
 259 /* For Debug uses */
 260 static const char *ResourceType(enum mlx4_resource rt)
 261 {
 262         switch (rt) {
 263         case RES_QP: return "RES_QP";
 264         case RES_CQ: return "RES_CQ";
 265         case RES_SRQ: return "RES_SRQ";
 266         case RES_MPT: return "RES_MPT";
 267         case RES_MTT: return "RES_MTT";
 268         case RES_MAC: return  "RES_MAC";
 269         case RES_EQ: return "RES_EQ";
 270         case RES_COUNTER: return "RES_COUNTER";
 271         case RES_FS_RULE: return "RES_FS_RULE";
 272         case RES_XRCD: return "RES_XRCD";
 273         default: return "Unknown resource type !!!";
 274         };
 275 }
 276
 277 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
 278 {
 279         struct mlx4_priv *priv = mlx4_priv(dev);
 280         int i;
 281         int t;
 282
 283         priv->mfunc.master.res_tracker.slave_list =
 284                 kzalloc(dev->num_slaves * sizeof(struct slave_list),
 285                         GFP_KERNEL);
 286         if (!priv->mfunc.master.res_tracker.slave_list)
 287                 return -ENOMEM;
 288
 289         for (i = 0 ; i < dev->num_slaves; i++) {
 290                 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
 291                         INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
 292                                        slave_list[i].res_list[t]);
 293                 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 294         }
 295
 296         mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
 297                  dev->num_slaves);
 298         for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
 299                 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
 300
 301         spin_lock_init(&priv->mfunc.master.res_tracker.lock);
 302         return 0 ;
 303 }
 304
 305 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
 306                                 enum mlx4_res_tracker_free_type type)
 307 {
 308         struct mlx4_priv *priv = mlx4_priv(dev);
 309         int i;
 310
 311         if (priv->mfunc.master.res_tracker.slave_list) {
 312                 if (type != RES_TR_FREE_STRUCTS_ONLY)
 313                         for (i = 0 ; i < dev->num_slaves; i++)
 314                                 if (type == RES_TR_FREE_ALL ||
 315                                     dev->caps.function != i)
 316                                         mlx4_delete_all_resources_for_slave(dev, i);
 317
 318                 if (type != RES_TR_FREE_SLAVES_ONLY) {
 319                         kfree(priv->mfunc.master.res_tracker.slave_list);
 320                         priv->mfunc.master.res_tracker.slave_list = NULL;
 321                 }
 322         }
 323 }
 324
 325 static void update_pkey_index(struct mlx4_dev *dev, int slave,
 326                               struct mlx4_cmd_mailbox *inbox)
 327 {
 328         u8 sched = *(u8 *)(inbox->buf + 64);
 329         u8 orig_index = *(u8 *)(inbox->buf + 35);
 330         u8 new_index;
 331         struct mlx4_priv *priv = mlx4_priv(dev);
 332         int port;
 333
 334         port = (sched >> 6 & 1) + 1;
 335
 336         new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
 337         *(u8 *)(inbox->buf + 35) = new_index;
 338 }
 339
 340 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
 341                        u8 slave)
 342 {
 343         struct mlx4_qp_context  *qp_ctx = inbox->buf + 8;
 344         enum mlx4_qp_optpar     optpar = be32_to_cpu(*(__be32 *) inbox->buf);
 345         u32                     ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
 346
 347         if (MLX4_QP_ST_UD == ts)
 348                 qp_ctx->pri_path.mgid_index = 0x80 | slave;
 349
 350         if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
 351                 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
 352                         qp_ctx->pri_path.mgid_index = slave & 0x7F;
 353                 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
 354                         qp_ctx->alt_path.mgid_index = slave & 0x7F;
 355         }
 356 }
 357
 358 static int update_vport_qp_param(struct mlx4_dev *dev,
 359                                  struct mlx4_cmd_mailbox *inbox,
 360                                  u8 slave, u32 qpn)
 361 {
 362         struct mlx4_qp_context  *qpc = inbox->buf + 8;
 363         struct mlx4_vport_oper_state *vp_oper;
 364         struct mlx4_priv *priv;
 365         u32 qp_type;
 366         int port;
 367
 368         port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
 369         priv = mlx4_priv(dev);
 370         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
 371
 372         if (MLX4_VGT != vp_oper->state.default_vlan) {
 373                 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
 374                 if (MLX4_QP_ST_RC == qp_type ||
 375                     (MLX4_QP_ST_UD == qp_type &&
 376                      !mlx4_is_qp_reserved(dev, qpn)))
 377                         return -EINVAL;
 378
 379                 /* the reserved QPs (special, proxy, tunnel)
 380                  * do not operate over vlans
 381                  */
 382                 if (mlx4_is_qp_reserved(dev, qpn))
 383                         return 0;
 384
 385                 /* force strip vlan by clear vsd */
 386                 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
 387                 if (0 != vp_oper->state.default_vlan) {
 388                         qpc->pri_path.vlan_control =
 389                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 390                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
 391                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
 392                 } else { /* priority tagged */
 393                         qpc->pri_path.vlan_control =
 394                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 395                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
 396                 }
 397
 398                 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
 399                 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
 400                 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
 401                 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
 402                 qpc->pri_path.sched_queue &= 0xC7;
 403                 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
 404         }
 405         if (vp_oper->state.spoofchk) {
 406                 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
 407                 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
 408         }
 409         return 0;
 410 }
 411
 412 static int mpt_mask(struct mlx4_dev *dev)
 413 {
 414         return dev->caps.num_mpts - 1;
 415 }
 416
 417 static void *find_res(struct mlx4_dev *dev, u64 res_id,
 418                       enum mlx4_resource type)
 419 {
 420         struct mlx4_priv *priv = mlx4_priv(dev);
 421
 422         return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
 423                                   res_id);
 424 }
 425
 426 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
 427                    enum mlx4_resource type,
 428                    void *res)
 429 {
 430         struct res_common *r;
 431         int err = 0;
 432
 433         spin_lock_irq(mlx4_tlock(dev));
 434         r = find_res(dev, res_id, type);
 435         if (!r) {
 436                 err = -ENONET;
 437                 goto exit;
 438         }
 439
 440         if (r->state == RES_ANY_BUSY) {
 441                 err = -EBUSY;
 442                 goto exit;
 443         }
 444
 445         if (r->owner != slave) {
 446                 err = -EPERM;
 447                 goto exit;
 448         }
 449
 450         r->from_state = r->state;
 451         r->state = RES_ANY_BUSY;
 452
 453         if (res)
 454                 *((struct res_common **)res) = r;
 455
 456 exit:
 457         spin_unlock_irq(mlx4_tlock(dev));
 458         return err;
 459 }
 460
 461 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
 462                                     enum mlx4_resource type,
 463                                     u64 res_id, int *slave)
 464 {
 465
 466         struct res_common *r;
 467         int err = -ENOENT;
 468         int id = res_id;
 469
 470         if (type == RES_QP)
 471                 id &= 0x7fffff;
 472         spin_lock(mlx4_tlock(dev));
 473
 474         r = find_res(dev, id, type);
 475         if (r) {
 476                 *slave = r->owner;
 477                 err = 0;
 478         }
 479         spin_unlock(mlx4_tlock(dev));
 480
 481         return err;
 482 }
 483
 484 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
 485                     enum mlx4_resource type)
 486 {
 487         struct res_common *r;
 488
 489         spin_lock_irq(mlx4_tlock(dev));
 490         r = find_res(dev, res_id, type);
 491         if (r)
 492                 r->state = r->from_state;
 493         spin_unlock_irq(mlx4_tlock(dev));
 494 }
 495
 496 static struct res_common *alloc_qp_tr(int id)
 497 {
 498         struct res_qp *ret;
 499
 500         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 501         if (!ret)
 502                 return NULL;
 503
 504         ret->com.res_id = id;
 505         ret->com.state = RES_QP_RESERVED;
 506         ret->local_qpn = id;
 507         INIT_LIST_HEAD(&ret->mcg_list);
 508         spin_lock_init(&ret->mcg_spl);
 509         atomic_set(&ret->ref_count, 0);
 510
 511         return &ret->com;
 512 }
 513
 514 static struct res_common *alloc_mtt_tr(int id, int order)
 515 {
 516         struct res_mtt *ret;
 517
 518         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 519         if (!ret)
 520                 return NULL;
 521
 522         ret->com.res_id = id;
 523         ret->order = order;
 524         ret->com.state = RES_MTT_ALLOCATED;
 525         atomic_set(&ret->ref_count, 0);
 526
 527         return &ret->com;
 528 }
 529
 530 static struct res_common *alloc_mpt_tr(int id, int key)
 531 {
 532         struct res_mpt *ret;
 533
 534         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 535         if (!ret)
 536                 return NULL;
 537
 538         ret->com.res_id = id;
 539         ret->com.state = RES_MPT_RESERVED;
 540         ret->key = key;
 541
 542         return &ret->com;
 543 }
 544
 545 static struct res_common *alloc_eq_tr(int id)
 546 {
 547         struct res_eq *ret;
 548
 549         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 550         if (!ret)
 551                 return NULL;
 552
 553         ret->com.res_id = id;
 554         ret->com.state = RES_EQ_RESERVED;
 555
 556         return &ret->com;
 557 }
 558
 559 static struct res_common *alloc_cq_tr(int id)
 560 {
 561         struct res_cq *ret;
 562
 563         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 564         if (!ret)
 565                 return NULL;
 566
 567         ret->com.res_id = id;
 568         ret->com.state = RES_CQ_ALLOCATED;
 569         atomic_set(&ret->ref_count, 0);
 570
 571         return &ret->com;
 572 }
 573
 574 static struct res_common *alloc_srq_tr(int id)
 575 {
 576         struct res_srq *ret;
 577
 578         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 579         if (!ret)
 580                 return NULL;
 581
 582         ret->com.res_id = id;
 583         ret->com.state = RES_SRQ_ALLOCATED;
 584         atomic_set(&ret->ref_count, 0);
 585
 586         return &ret->com;
 587 }
 588
 589 static struct res_common *alloc_counter_tr(int id)
 590 {
 591         struct res_counter *ret;
 592
 593         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 594         if (!ret)
 595                 return NULL;
 596
 597         ret->com.res_id = id;
 598         ret->com.state = RES_COUNTER_ALLOCATED;
 599
 600         return &ret->com;
 601 }
 602
 603 static struct res_common *alloc_xrcdn_tr(int id)
 604 {
 605         struct res_xrcdn *ret;
 606
 607         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 608         if (!ret)
 609                 return NULL;
 610
 611         ret->com.res_id = id;
 612         ret->com.state = RES_XRCD_ALLOCATED;
 613
 614         return &ret->com;
 615 }
 616
 617 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
 618 {
 619         struct res_fs_rule *ret;
 620
 621         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 622         if (!ret)
 623                 return NULL;
 624
 625         ret->com.res_id = id;
 626         ret->com.state = RES_FS_RULE_ALLOCATED;
 627         ret->qpn = qpn;
 628         return &ret->com;
 629 }
 630
 631 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
 632                                    int extra)
 633 {
 634         struct res_common *ret;
 635
 636         switch (type) {
 637         case RES_QP:
 638                 ret = alloc_qp_tr(id);
 639                 break;
 640         case RES_MPT:
 641                 ret = alloc_mpt_tr(id, extra);
 642                 break;
 643         case RES_MTT:
 644                 ret = alloc_mtt_tr(id, extra);
 645                 break;
 646         case RES_EQ:
 647                 ret = alloc_eq_tr(id);
 648                 break;
 649         case RES_CQ:
 650                 ret = alloc_cq_tr(id);
 651                 break;
 652         case RES_SRQ:
 653                 ret = alloc_srq_tr(id);
 654                 break;
 655         case RES_MAC:
 656                 printk(KERN_ERR "implementation missing\n");
 657                 return NULL;
 658         case RES_COUNTER:
 659                 ret = alloc_counter_tr(id);
 660                 break;
 661         case RES_XRCD:
 662                 ret = alloc_xrcdn_tr(id);
 663                 break;
 664         case RES_FS_RULE:
 665                 ret = alloc_fs_rule_tr(id, extra);
 666                 break;
 667         default:
 668                 return NULL;
 669         }
 670         if (ret)
 671                 ret->owner = slave;
 672
 673         return ret;
 674 }
 675
 676 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
 677                          enum mlx4_resource type, int extra)
 678 {
 679         int i;
 680         int err;
 681         struct mlx4_priv *priv = mlx4_priv(dev);
 682         struct res_common **res_arr;
 683         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
 684         struct rb_root *root = &tracker->res_tree[type];
 685
 686         res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
 687         if (!res_arr)
 688                 return -ENOMEM;
 689
 690         for (i = 0; i < count; ++i) {
 691                 res_arr[i] = alloc_tr(base + i, type, slave, extra);
 692                 if (!res_arr[i]) {
 693                         for (--i; i >= 0; --i)
 694                                 kfree(res_arr[i]);
 695
 696                         kfree(res_arr);
 697                         return -ENOMEM;
 698                 }
 699         }
 700
 701         spin_lock_irq(mlx4_tlock(dev));
 702         for (i = 0; i < count; ++i) {
 703                 if (find_res(dev, base + i, type)) {
 704                         err = -EEXIST;
 705                         goto undo;
 706                 }
 707                 err = res_tracker_insert(root, res_arr[i]);
 708                 if (err)
 709                         goto undo;
 710                 list_add_tail(&res_arr[i]->list,
 711                               &tracker->slave_list[slave].res_list[type]);
 712         }
 713         spin_unlock_irq(mlx4_tlock(dev));
 714         kfree(res_arr);
 715
 716         return 0;
 717
 718 undo:
 719         for (--i; i >= base; --i)
 720                 rb_erase(&res_arr[i]->node, root);
 721
 722         spin_unlock_irq(mlx4_tlock(dev));
 723
 724         for (i = 0; i < count; ++i)
 725                 kfree(res_arr[i]);
 726
 727         kfree(res_arr);
 728
 729         return err;
 730 }
 731
 732 static int remove_qp_ok(struct res_qp *res)
 733 {
 734         if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
 735             !list_empty(&res->mcg_list)) {
 736                 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
 737                        res->com.state, atomic_read(&res->ref_count));
 738                 return -EBUSY;
 739         } else if (res->com.state != RES_QP_RESERVED) {
 740                 return -EPERM;
 741         }
 742
 743         return 0;
 744 }
 745
 746 static int remove_mtt_ok(struct res_mtt *res, int order)
 747 {
 748         if (res->com.state == RES_MTT_BUSY ||
 749             atomic_read(&res->ref_count)) {
 750                 printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
 751                        __func__, __LINE__,
 752                        mtt_states_str(res->com.state),
 753                        atomic_read(&res->ref_count));
 754                 return -EBUSY;
 755         } else if (res->com.state != RES_MTT_ALLOCATED)
 756                 return -EPERM;
 757         else if (res->order != order)
 758                 return -EINVAL;
 759
 760         return 0;
 761 }
 762
 763 static int remove_mpt_ok(struct res_mpt *res)
 764 {
 765         if (res->com.state == RES_MPT_BUSY)
 766                 return -EBUSY;
 767         else if (res->com.state != RES_MPT_RESERVED)
 768                 return -EPERM;
 769
 770         return 0;
 771 }
 772
 773 static int remove_eq_ok(struct res_eq *res)
 774 {
 775         if (res->com.state == RES_MPT_BUSY)
 776                 return -EBUSY;
 777         else if (res->com.state != RES_MPT_RESERVED)
 778                 return -EPERM;
 779
 780         return 0;
 781 }
 782
 783 static int remove_counter_ok(struct res_counter *res)
 784 {
 785         if (res->com.state == RES_COUNTER_BUSY)
 786                 return -EBUSY;
 787         else if (res->com.state != RES_COUNTER_ALLOCATED)
 788                 return -EPERM;
 789
 790         return 0;
 791 }
 792
 793 static int remove_xrcdn_ok(struct res_xrcdn *res)
 794 {
 795         if (res->com.state == RES_XRCD_BUSY)
 796                 return -EBUSY;
 797         else if (res->com.state != RES_XRCD_ALLOCATED)
 798                 return -EPERM;
 799
 800         return 0;
 801 }
 802
 803 static int remove_fs_rule_ok(struct res_fs_rule *res)
 804 {
 805         if (res->com.state == RES_FS_RULE_BUSY)
 806                 return -EBUSY;
 807         else if (res->com.state != RES_FS_RULE_ALLOCATED)
 808                 return -EPERM;
 809
 810         return 0;
 811 }
 812
 813 static int remove_cq_ok(struct res_cq *res)
 814 {
 815         if (res->com.state == RES_CQ_BUSY)
 816                 return -EBUSY;
 817         else if (res->com.state != RES_CQ_ALLOCATED)
 818                 return -EPERM;
 819
 820         return 0;
 821 }
 822
 823 static int remove_srq_ok(struct res_srq *res)
 824 {
 825         if (res->com.state == RES_SRQ_BUSY)
 826                 return -EBUSY;
 827         else if (res->com.state != RES_SRQ_ALLOCATED)
 828                 return -EPERM;
 829
 830         return 0;
 831 }
 832
 833 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
 834 {
 835         switch (type) {
 836         case RES_QP:
 837                 return remove_qp_ok((struct res_qp *)res);
 838         case RES_CQ:
 839                 return remove_cq_ok((struct res_cq *)res);
 840         case RES_SRQ:
 841                 return remove_srq_ok((struct res_srq *)res);
 842         case RES_MPT:
 843                 return remove_mpt_ok((struct res_mpt *)res);
 844         case RES_MTT:
 845                 return remove_mtt_ok((struct res_mtt *)res, extra);
 846         case RES_MAC:
 847                 return -ENOSYS;
 848         case RES_EQ:
 849                 return remove_eq_ok((struct res_eq *)res);
 850         case RES_COUNTER:
 851                 return remove_counter_ok((struct res_counter *)res);
 852         case RES_XRCD:
 853                 return remove_xrcdn_ok((struct res_xrcdn *)res);
 854         case RES_FS_RULE:
 855                 return remove_fs_rule_ok((struct res_fs_rule *)res);
 856         default:
 857                 return -EINVAL;
 858         }
 859 }
 860
 861 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
 862                          enum mlx4_resource type, int extra)
 863 {
 864         u64 i;
 865         int err;
 866         struct mlx4_priv *priv = mlx4_priv(dev);
 867         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
 868         struct res_common *r;
 869
 870         spin_lock_irq(mlx4_tlock(dev));
 871         for (i = base; i < base + count; ++i) {
 872                 r = res_tracker_lookup(&tracker->res_tree[type], i);
 873                 if (!r) {
 874                         err = -ENOENT;
 875                         goto out;
 876                 }
 877                 if (r->owner != slave) {
 878                         err = -EPERM;
 879                         goto out;
 880                 }
 881                 err = remove_ok(r, type, extra);
 882                 if (err)
 883                         goto out;
 884         }
 885
 886         for (i = base; i < base + count; ++i) {
 887                 r = res_tracker_lookup(&tracker->res_tree[type], i);
 888                 rb_erase(&r->node, &tracker->res_tree[type]);
 889                 list_del(&r->list);
 890                 kfree(r);
 891         }
 892         err = 0;
 893
 894 out:
 895         spin_unlock_irq(mlx4_tlock(dev));
 896
 897         return err;
 898 }
 899
 900 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
 901                                 enum res_qp_states state, struct res_qp **qp,
 902                                 int alloc)
 903 {
 904         struct mlx4_priv *priv = mlx4_priv(dev);
 905         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
 906         struct res_qp *r;
 907         int err = 0;
 908
 909         spin_lock_irq(mlx4_tlock(dev));
 910         r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
 911         if (!r)
 912                 err = -ENOENT;
 913         else if (r->com.owner != slave)
 914                 err = -EPERM;
 915         else {
 916                 switch (state) {
 917                 case RES_QP_BUSY:
 918                         mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
 919                                  __func__, r->com.res_id);
 920                         err = -EBUSY;
 921                         break;
 922
 923                 case RES_QP_RESERVED:
 924                         if (r->com.state == RES_QP_MAPPED && !alloc)
 925                                 break;
 926
 927                         mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
 928                         err = -EINVAL;
 929                         break;
 930
 931                 case RES_QP_MAPPED:
 932                         if ((r->com.state == RES_QP_RESERVED && alloc) ||
 933                             r->com.state == RES_QP_HW)
 934                                 break;
 935                         else {
 936                                 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
 937                                           r->com.res_id);
 938                                 err = -EINVAL;
 939                         }
 940
 941                         break;
 942
 943                 case RES_QP_HW:
 944                         if (r->com.state != RES_QP_MAPPED)
 945                                 err = -EINVAL;
 946                         break;
 947                 default:
 948                         err = -EINVAL;
 949                 }
 950
 951                 if (!err) {
 952                         r->com.from_state = r->com.state;
 953                         r->com.to_state = state;
 954                         r->com.state = RES_QP_BUSY;
 955                         if (qp)
 956                                 *qp = r;
 957                 }
 958         }
 959
 960         spin_unlock_irq(mlx4_tlock(dev));
 961
 962         return err;
 963 }
 964
 965 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
 966                                 enum res_mpt_states state, struct res_mpt **mpt)
 967 {
 968         struct mlx4_priv *priv = mlx4_priv(dev);
 969         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
 970         struct res_mpt *r;
 971         int err = 0;
 972
 973         spin_lock_irq(mlx4_tlock(dev));
 974         r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
 975         if (!r)
 976                 err = -ENOENT;
 977         else if (r->com.owner != slave)
 978                 err = -EPERM;
 979         else {
 980                 switch (state) {
 981                 case RES_MPT_BUSY:
 982                         err = -EINVAL;
 983                         break;
 984
 985                 case RES_MPT_RESERVED:
 986                         if (r->com.state != RES_MPT_MAPPED)
 987                                 err = -EINVAL;
 988                         break;
 989
 990                 case RES_MPT_MAPPED:
 991                         if (r->com.state != RES_MPT_RESERVED &&
 992                             r->com.state != RES_MPT_HW)
 993                                 err = -EINVAL;
 994                         break;
 995
 996                 case RES_MPT_HW:
 997                         if (r->com.state != RES_MPT_MAPPED)
 998                                 err = -EINVAL;
 999                         break;
1000                 default:
1001                         err = -EINVAL;
1002                 }
1003
1004                 if (!err) {
1005                         r->com.from_state = r->com.state;
1006                         r->com.to_state = state;
1007                         r->com.state = RES_MPT_BUSY;
1008                         if (mpt)
1009                                 *mpt = r;
1010                 }
1011         }
1012
1013         spin_unlock_irq(mlx4_tlock(dev));
1014
1015         return err;
1016 }
1017
1018 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1019                                 enum res_eq_states state, struct res_eq **eq)
1020 {
1021         struct mlx4_priv *priv = mlx4_priv(dev);
1022         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1023         struct res_eq *r;
1024         int err = 0;
1025
1026         spin_lock_irq(mlx4_tlock(dev));
1027         r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1028         if (!r)
1029                 err = -ENOENT;
1030         else if (r->com.owner != slave)
1031                 err = -EPERM;
1032         else {
1033                 switch (state) {
1034                 case RES_EQ_BUSY:
1035                         err = -EINVAL;
1036                         break;
1037
1038                 case RES_EQ_RESERVED:
1039                         if (r->com.state != RES_EQ_HW)
1040                                 err = -EINVAL;
1041                         break;
1042
1043                 case RES_EQ_HW:
1044                         if (r->com.state != RES_EQ_RESERVED)
1045                                 err = -EINVAL;
1046                         break;
1047
1048                 default:
1049                         err = -EINVAL;
1050                 }
1051
1052                 if (!err) {
1053                         r->com.from_state = r->com.state;
1054                         r->com.to_state = state;
1055                         r->com.state = RES_EQ_BUSY;
1056                         if (eq)
1057                                 *eq = r;
1058                 }
1059         }
1060
1061         spin_unlock_irq(mlx4_tlock(dev));
1062
1063         return err;
1064 }
1065
1066 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1067                                 enum res_cq_states state, struct res_cq **cq)
1068 {
1069         struct mlx4_priv *priv = mlx4_priv(dev);
1070         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1071         struct res_cq *r;
1072         int err;
1073
1074         spin_lock_irq(mlx4_tlock(dev));
1075         r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1076         if (!r)
1077                 err = -ENOENT;
1078         else if (r->com.owner != slave)
1079                 err = -EPERM;
1080         else {
1081                 switch (state) {
1082                 case RES_CQ_BUSY:
1083                         err = -EBUSY;
1084                         break;
1085
1086                 case RES_CQ_ALLOCATED:
1087                         if (r->com.state != RES_CQ_HW)
1088                                 err = -EINVAL;
1089                         else if (atomic_read(&r->ref_count))
1090                                 err = -EBUSY;
1091                         else
1092                                 err = 0;
1093                         break;
1094
1095                 case RES_CQ_HW:
1096                         if (r->com.state != RES_CQ_ALLOCATED)
1097                                 err = -EINVAL;
1098                         else
1099                                 err = 0;
1100                         break;
1101
1102                 default:
1103                         err = -EINVAL;
1104                 }
1105
1106                 if (!err) {
1107                         r->com.from_state = r->com.state;
1108                         r->com.to_state = state;
1109                         r->com.state = RES_CQ_BUSY;
1110                         if (cq)
1111                                 *cq = r;
1112                 }
1113         }
1114
1115         spin_unlock_irq(mlx4_tlock(dev));
1116
1117         return err;
1118 }
1119
1120 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1121                                  enum res_cq_states state, struct res_srq **srq)
1122 {
1123         struct mlx4_priv *priv = mlx4_priv(dev);
1124         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1125         struct res_srq *r;
1126         int err = 0;
1127
1128         spin_lock_irq(mlx4_tlock(dev));
1129         r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1130         if (!r)
1131                 err = -ENOENT;
1132         else if (r->com.owner != slave)
1133                 err = -EPERM;
1134         else {
1135                 switch (state) {
1136                 case RES_SRQ_BUSY:
1137                         err = -EINVAL;
1138                         break;
1139
1140                 case RES_SRQ_ALLOCATED:
1141                         if (r->com.state != RES_SRQ_HW)
1142                                 err = -EINVAL;
1143                         else if (atomic_read(&r->ref_count))
1144                                 err = -EBUSY;
1145                         break;
1146
1147                 case RES_SRQ_HW:
1148                         if (r->com.state != RES_SRQ_ALLOCATED)
1149                                 err = -EINVAL;
1150                         break;
1151
1152                 default:
1153                         err = -EINVAL;
1154                 }
1155
1156                 if (!err) {
1157                         r->com.from_state = r->com.state;
1158                         r->com.to_state = state;
1159                         r->com.state = RES_SRQ_BUSY;
1160                         if (srq)
1161                                 *srq = r;
1162                 }
1163         }
1164
1165         spin_unlock_irq(mlx4_tlock(dev));
1166
1167         return err;
1168 }
1169
1170 static void res_abort_move(struct mlx4_dev *dev, int slave,
1171                            enum mlx4_resource type, int id)
1172 {
1173         struct mlx4_priv *priv = mlx4_priv(dev);
1174         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1175         struct res_common *r;
1176
1177         spin_lock_irq(mlx4_tlock(dev));
1178         r = res_tracker_lookup(&tracker->res_tree[type], id);
1179         if (r && (r->owner == slave))
1180                 r->state = r->from_state;
1181         spin_unlock_irq(mlx4_tlock(dev));
1182 }
1183
1184 static void res_end_move(struct mlx4_dev *dev, int slave,
1185                          enum mlx4_resource type, int id)
1186 {
1187         struct mlx4_priv *priv = mlx4_priv(dev);
1188         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1189         struct res_common *r;
1190
1191         spin_lock_irq(mlx4_tlock(dev));
1192         r = res_tracker_lookup(&tracker->res_tree[type], id);
1193         if (r && (r->owner == slave))
1194                 r->state = r->to_state;
1195         spin_unlock_irq(mlx4_tlock(dev));
1196 }
1197
1198 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1199 {
1200         return mlx4_is_qp_reserved(dev, qpn) &&
1201                 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1202 }
1203
1204 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1205 {
1206         return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1207 }
1208
1209 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1210                         u64 in_param, u64 *out_param)
1211 {
1212         int err;
1213         int count;
1214         int align;
1215         int base;
1216         int qpn;
1217
1218         switch (op) {
1219         case RES_OP_RESERVE:
1220                 count = get_param_l(&in_param);
1221                 align = get_param_h(&in_param);
1222                 err = __mlx4_qp_reserve_range(dev, count, align, &base);
1223                 if (err)
1224                         return err;
1225
1226                 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1227                 if (err) {
1228                         __mlx4_qp_release_range(dev, base, count);
1229                         return err;
1230                 }
1231                 set_param_l(out_param, base);
1232                 break;
1233         case RES_OP_MAP_ICM:
1234                 qpn = get_param_l(&in_param) & 0x7fffff;
1235                 if (valid_reserved(dev, slave, qpn)) {
1236                         err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1237                         if (err)
1238                                 return err;
1239                 }
1240
1241                 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1242                                            NULL, 1);
1243                 if (err)
1244                         return err;
1245
1246                 if (!fw_reserved(dev, qpn)) {
1247                         err = __mlx4_qp_alloc_icm(dev, qpn);
1248                         if (err) {
1249                                 res_abort_move(dev, slave, RES_QP, qpn);
1250                                 return err;
1251                         }
1252                 }
1253
1254                 res_end_move(dev, slave, RES_QP, qpn);
1255                 break;
1256
1257         default:
1258                 err = -EINVAL;
1259                 break;
1260         }
1261         return err;
1262 }
1263
1264 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1265                          u64 in_param, u64 *out_param)
1266 {
1267         int err = -EINVAL;
1268         int base;
1269         int order;
1270
1271         if (op != RES_OP_RESERVE_AND_MAP)
1272                 return err;
1273
1274         order = get_param_l(&in_param);
1275         base = __mlx4_alloc_mtt_range(dev, order);
1276         if (base == -1)
1277                 return -ENOMEM;
1278
1279         err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1280         if (err)
1281                 __mlx4_free_mtt_range(dev, base, order);
1282         else
1283                 set_param_l(out_param, base);
1284
1285         return err;
1286 }
1287
1288 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1289                          u64 in_param, u64 *out_param)
1290 {
1291         int err = -EINVAL;
1292         int index;
1293         int id;
1294         struct res_mpt *mpt;
1295
1296         switch (op) {
1297         case RES_OP_RESERVE:
1298                 index = __mlx4_mpt_reserve(dev);
1299                 if (index == -1)
1300                         break;
1301                 id = index & mpt_mask(dev);
1302
1303                 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1304                 if (err) {
1305                         __mlx4_mpt_release(dev, index);
1306                         break;
1307                 }
1308                 set_param_l(out_param, index);
1309                 break;
1310         case RES_OP_MAP_ICM:
1311                 index = get_param_l(&in_param);
1312                 id = index & mpt_mask(dev);
1313                 err = mr_res_start_move_to(dev, slave, id,
1314                                            RES_MPT_MAPPED, &mpt);
1315                 if (err)
1316                         return err;
1317
1318                 err = __mlx4_mpt_alloc_icm(dev, mpt->key);
1319                 if (err) {
1320                         res_abort_move(dev, slave, RES_MPT, id);
1321                         return err;
1322                 }
1323
1324                 res_end_move(dev, slave, RES_MPT, id);
1325                 break;
1326         }
1327         return err;
1328 }
1329
1330 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1331                         u64 in_param, u64 *out_param)
1332 {
1333         int cqn;
1334         int err;
1335
1336         switch (op) {
1337         case RES_OP_RESERVE_AND_MAP:
1338                 err = __mlx4_cq_alloc_icm(dev, &cqn);
1339                 if (err)
1340                         break;
1341
1342                 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1343                 if (err) {
1344                         __mlx4_cq_free_icm(dev, cqn);
1345                         break;
1346                 }
1347
1348                 set_param_l(out_param, cqn);
1349                 break;
1350
1351         default:
1352                 err = -EINVAL;
1353         }
1354
1355         return err;
1356 }
1357
1358 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1359                          u64 in_param, u64 *out_param)
1360 {
1361         int srqn;
1362         int err;
1363
1364         switch (op) {
1365         case RES_OP_RESERVE_AND_MAP:
1366                 err = __mlx4_srq_alloc_icm(dev, &srqn);
1367                 if (err)
1368                         break;
1369
1370                 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1371                 if (err) {
1372                         __mlx4_srq_free_icm(dev, srqn);
1373                         break;
1374                 }
1375
1376                 set_param_l(out_param, srqn);
1377                 break;
1378
1379         default:
1380                 err = -EINVAL;
1381         }
1382
1383         return err;
1384 }
1385
1386 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
1387 {
1388         struct mlx4_priv *priv = mlx4_priv(dev);
1389         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1390         struct mac_res *res;
1391
1392         res = kzalloc(sizeof *res, GFP_KERNEL);
1393         if (!res)
1394                 return -ENOMEM;
1395         res->mac = mac;
1396         res->port = (u8) port;
1397         list_add_tail(&res->list,
1398                       &tracker->slave_list[slave].res_list[RES_MAC]);
1399         return 0;
1400 }
1401
1402 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1403                                int port)
1404 {
1405         struct mlx4_priv *priv = mlx4_priv(dev);
1406         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1407         struct list_head *mac_list =
1408                 &tracker->slave_list[slave].res_list[RES_MAC];
1409         struct mac_res *res, *tmp;
1410
1411         list_for_each_entry_safe(res, tmp, mac_list, list) {
1412                 if (res->mac == mac && res->port == (u8) port) {
1413                         list_del(&res->list);
1414                         kfree(res);
1415                         break;
1416                 }
1417         }
1418 }
1419
1420 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
1421 {
1422         struct mlx4_priv *priv = mlx4_priv(dev);
1423         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1424         struct list_head *mac_list =
1425                 &tracker->slave_list[slave].res_list[RES_MAC];
1426         struct mac_res *res, *tmp;
1427
1428         list_for_each_entry_safe(res, tmp, mac_list, list) {
1429                 list_del(&res->list);
1430                 __mlx4_unregister_mac(dev, res->port, res->mac);
1431                 kfree(res);
1432         }
1433 }
1434
1435 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1436                          u64 in_param, u64 *out_param)
1437 {
1438         int err = -EINVAL;
1439         int port;
1440         u64 mac;
1441
1442         if (op != RES_OP_RESERVE_AND_MAP)
1443                 return err;
1444
1445         port = get_param_l(out_param);
1446         mac = in_param;
1447
1448         err = __mlx4_register_mac(dev, port, mac);
1449         if (err >= 0) {
1450                 set_param_l(out_param, err);
1451                 err = 0;
1452         }
1453
1454         if (!err) {
1455                 err = mac_add_to_slave(dev, slave, mac, port);
1456                 if (err)
1457                         __mlx4_unregister_mac(dev, port, mac);
1458         }
1459         return err;
1460 }
1461
1462 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1463                          u64 in_param, u64 *out_param)
1464 {
1465         return 0;
1466 }
1467
1468 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1469                              u64 in_param, u64 *out_param)
1470 {
1471         u32 index;
1472         int err;
1473
1474         if (op != RES_OP_RESERVE)
1475                 return -EINVAL;
1476
1477         err = __mlx4_counter_alloc(dev, &index);
1478         if (err)
1479                 return err;
1480
1481         err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
1482         if (err)
1483                 __mlx4_counter_free(dev, index);
1484         else
1485                 set_param_l(out_param, index);
1486
1487         return err;
1488 }
1489
1490 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1491                            u64 in_param, u64 *out_param)
1492 {
1493         u32 xrcdn;
1494         int err;
1495
1496         if (op != RES_OP_RESERVE)
1497                 return -EINVAL;
1498
1499         err = __mlx4_xrcd_alloc(dev, &xrcdn);
1500         if (err)
1501                 return err;
1502
1503         err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
1504         if (err)
1505                 __mlx4_xrcd_free(dev, xrcdn);
1506         else
1507                 set_param_l(out_param, xrcdn);
1508
1509         return err;
1510 }
1511
1512 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1513                            struct mlx4_vhcr *vhcr,
1514                            struct mlx4_cmd_mailbox *inbox,
1515                            struct mlx4_cmd_mailbox *outbox,
1516                            struct mlx4_cmd_info *cmd)
1517 {
1518         int err;
1519         int alop = vhcr->op_modifier;
1520
1521         switch (vhcr->in_modifier) {
1522         case RES_QP:
1523                 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
1524                                    vhcr->in_param, &vhcr->out_param);
1525                 break;
1526
1527         case RES_MTT:
1528                 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
1529                                     vhcr->in_param, &vhcr->out_param);
1530                 break;
1531
1532         case RES_MPT:
1533                 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
1534                                     vhcr->in_param, &vhcr->out_param);
1535                 break;
1536
1537         case RES_CQ:
1538                 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
1539                                    vhcr->in_param, &vhcr->out_param);
1540                 break;
1541
1542         case RES_SRQ:
1543                 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
1544                                     vhcr->in_param, &vhcr->out_param);
1545                 break;
1546
1547         case RES_MAC:
1548                 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
1549                                     vhcr->in_param, &vhcr->out_param);
1550                 break;
1551
1552         case RES_VLAN:
1553                 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
1554                                     vhcr->in_param, &vhcr->out_param);
1555                 break;
1556
1557         case RES_COUNTER:
1558                 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
1559                                         vhcr->in_param, &vhcr->out_param);
1560                 break;
1561
1562         case RES_XRCD:
1563                 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
1564                                       vhcr->in_param, &vhcr->out_param);
1565                 break;
1566
1567         default:
1568                 err = -EINVAL;
1569                 break;
1570         }
1571
1572         return err;
1573 }
1574
1575 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1576                        u64 in_param)
1577 {
1578         int err;
1579         int count;
1580         int base;
1581         int qpn;
1582
1583         switch (op) {
1584         case RES_OP_RESERVE:
1585                 base = get_param_l(&in_param) & 0x7fffff;
1586                 count = get_param_h(&in_param);
1587                 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
1588                 if (err)
1589                         break;
1590                 __mlx4_qp_release_range(dev, base, count);
1591                 break;
1592         case RES_OP_MAP_ICM:
1593                 qpn = get_param_l(&in_param) & 0x7fffff;
1594                 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
1595                                            NULL, 0);
1596                 if (err)
1597                         return err;
1598
1599                 if (!fw_reserved(dev, qpn))
1600                         __mlx4_qp_free_icm(dev, qpn);
1601
1602                 res_end_move(dev, slave, RES_QP, qpn);
1603
1604                 if (valid_reserved(dev, slave, qpn))
1605                         err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
1606                 break;
1607         default:
1608                 err = -EINVAL;
1609                 break;
1610         }
1611         return err;
1612 }
1613
1614 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1615                         u64 in_param, u64 *out_param)
1616 {
1617         int err = -EINVAL;
1618         int base;
1619         int order;
1620
1621         if (op != RES_OP_RESERVE_AND_MAP)
1622                 return err;
1623
1624         base = get_param_l(&in_param);
1625         order = get_param_h(&in_param);
1626         err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
1627         if (!err)
1628                 __mlx4_free_mtt_range(dev, base, order);
1629         return err;
1630 }
1631
1632 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1633                         u64 in_param)
1634 {
1635         int err = -EINVAL;
1636         int index;
1637         int id;
1638         struct res_mpt *mpt;
1639
1640         switch (op) {
1641         case RES_OP_RESERVE:
1642                 index = get_param_l(&in_param);
1643                 id = index & mpt_mask(dev);
1644                 err = get_res(dev, slave, id, RES_MPT, &mpt);
1645                 if (err)
1646                         break;
1647                 index = mpt->key;
1648                 put_res(dev, slave, id, RES_MPT);
1649
1650                 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
1651                 if (err)
1652                         break;
1653                 __mlx4_mpt_release(dev, index);
1654                 break;
1655         case RES_OP_MAP_ICM:
1656                         index = get_param_l(&in_param);
1657                         id = index & mpt_mask(dev);
1658                         err = mr_res_start_move_to(dev, slave, id,
1659                                                    RES_MPT_RESERVED, &mpt);
1660                         if (err)
1661                                 return err;
1662
1663                         __mlx4_mpt_free_icm(dev, mpt->key);
1664                         res_end_move(dev, slave, RES_MPT, id);
1665                         return err;
1666                 break;
1667         default:
1668                 err = -EINVAL;
1669                 break;
1670         }
1671         return err;
1672 }
1673
1674 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1675                        u64 in_param, u64 *out_param)
1676 {
1677         int cqn;
1678         int err;
1679
1680         switch (op) {
1681         case RES_OP_RESERVE_AND_MAP:
1682                 cqn = get_param_l(&in_param);
1683                 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1684                 if (err)
1685                         break;
1686
1687                 __mlx4_cq_free_icm(dev, cqn);
1688                 break;
1689
1690         default:
1691                 err = -EINVAL;
1692                 break;
1693         }
1694
1695         return err;
1696 }
1697
1698 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1699                         u64 in_param, u64 *out_param)
1700 {
1701         int srqn;
1702         int err;
1703
1704         switch (op) {
1705         case RES_OP_RESERVE_AND_MAP:
1706                 srqn = get_param_l(&in_param);
1707                 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1708                 if (err)
1709                         break;
1710
1711                 __mlx4_srq_free_icm(dev, srqn);
1712                 break;
1713
1714         default:
1715                 err = -EINVAL;
1716                 break;
1717         }
1718
1719         return err;
1720 }
1721
1722 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1723                             u64 in_param, u64 *out_param)
1724 {
1725         int port;
1726         int err = 0;
1727
1728         switch (op) {
1729         case RES_OP_RESERVE_AND_MAP:
1730                 port = get_param_l(out_param);
1731                 mac_del_from_slave(dev, slave, in_param, port);
1732                 __mlx4_unregister_mac(dev, port, in_param);
1733                 break;
1734         default:
1735                 err = -EINVAL;
1736                 break;
1737         }
1738
1739         return err;
1740
1741 }
1742
1743 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1744                             u64 in_param, u64 *out_param)
1745 {
1746         return 0;
1747 }
1748
1749 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1750                             u64 in_param, u64 *out_param)
1751 {
1752         int index;
1753         int err;
1754
1755         if (op != RES_OP_RESERVE)
1756                 return -EINVAL;
1757
1758         index = get_param_l(&in_param);
1759         err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
1760         if (err)
1761                 return err;
1762
1763         __mlx4_counter_free(dev, index);
1764
1765         return err;
1766 }
1767
1768 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1769                           u64 in_param, u64 *out_param)
1770 {
1771         int xrcdn;
1772         int err;
1773
1774         if (op != RES_OP_RESERVE)
1775                 return -EINVAL;
1776
1777         xrcdn = get_param_l(&in_param);
1778         err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
1779         if (err)
1780                 return err;
1781
1782         __mlx4_xrcd_free(dev, xrcdn);
1783
1784         return err;
1785 }
1786
1787 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1788                           struct mlx4_vhcr *vhcr,
1789                           struct mlx4_cmd_mailbox *inbox,
1790                           struct mlx4_cmd_mailbox *outbox,
1791                           struct mlx4_cmd_info *cmd)
1792 {
1793         int err = -EINVAL;
1794         int alop = vhcr->op_modifier;
1795
1796         switch (vhcr->in_modifier) {
1797         case RES_QP:
1798                 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
1799                                   vhcr->in_param);
1800                 break;
1801
1802         case RES_MTT:
1803                 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
1804                                    vhcr->in_param, &vhcr->out_param);
1805                 break;
1806
1807         case RES_MPT:
1808                 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
1809                                    vhcr->in_param);
1810                 break;
1811
1812         case RES_CQ:
1813                 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
1814                                   vhcr->in_param, &vhcr->out_param);
1815                 break;
1816
1817         case RES_SRQ:
1818                 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
1819                                    vhcr->in_param, &vhcr->out_param);
1820                 break;
1821
1822         case RES_MAC:
1823                 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
1824                                    vhcr->in_param, &vhcr->out_param);
1825                 break;
1826
1827         case RES_VLAN:
1828                 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
1829                                    vhcr->in_param, &vhcr->out_param);
1830                 break;
1831
1832         case RES_COUNTER:
1833                 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
1834                                        vhcr->in_param, &vhcr->out_param);
1835                 break;
1836
1837         case RES_XRCD:
1838                 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
1839                                      vhcr->in_param, &vhcr->out_param);
1840
1841         default:
1842                 break;
1843         }
1844         return err;
1845 }
1846
1847 /* ugly but other choices are uglier */
1848 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
1849 {
1850         return (be32_to_cpu(mpt->flags) >> 9) & 1;
1851 }
1852
1853 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
1854 {
1855         return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
1856 }
1857
1858 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
1859 {
1860         return be32_to_cpu(mpt->mtt_sz);
1861 }
1862
1863 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
1864 {
1865         return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
1866 }
1867
1868 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
1869 {
1870         return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
1871 }
1872
1873 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
1874 {
1875         return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
1876 }
1877
1878 static int mr_is_region(struct mlx4_mpt_entry *mpt)
1879 {
1880         return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
1881 }
1882
1883 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
1884 {
1885         return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
1886 }
1887
1888 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
1889 {
1890         return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
1891 }
1892
1893 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
1894 {
1895         int page_shift = (qpc->log_page_size & 0x3f) + 12;
1896         int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
1897         int log_sq_sride = qpc->sq_size_stride & 7;
1898         int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
1899         int log_rq_stride = qpc->rq_size_stride & 7;
1900         int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
1901         int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
1902         int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
1903         int sq_size;
1904         int rq_size;
1905         int total_pages;
1906         int total_mem;
1907         int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
1908
1909         sq_size = 1 << (log_sq_size + log_sq_sride + 4);
1910         rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
1911         total_mem = sq_size + rq_size;
1912         total_pages =
1913                 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
1914                                    page_shift);
1915
1916         return total_pages;
1917 }
1918
1919 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
1920                            int size, struct res_mtt *mtt)
1921 {
1922         int res_start = mtt->com.res_id;
1923         int res_size = (1 << mtt->order);
1924
1925         if (start < res_start || start + size > res_start + res_size)
1926                 return -EPERM;
1927         return 0;
1928 }
1929
1930 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
1931                            struct mlx4_vhcr *vhcr,
1932                            struct mlx4_cmd_mailbox *inbox,
1933                            struct mlx4_cmd_mailbox *outbox,
1934                            struct mlx4_cmd_info *cmd)
1935 {
1936         int err;
1937         int index = vhcr->in_modifier;
1938         struct res_mtt *mtt;
1939         struct res_mpt *mpt;
1940         int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
1941         int phys;
1942         int id;
1943         u32 pd;
1944         int pd_slave;
1945
1946         id = index & mpt_mask(dev);
1947         err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
1948         if (err)
1949                 return err;
1950
1951         /* Disable memory windows for VFs. */
1952         if (!mr_is_region(inbox->buf)) {
1953                 err = -EPERM;
1954                 goto ex_abort;
1955         }
1956
1957         /* Make sure that the PD bits related to the slave id are zeros. */
1958         pd = mr_get_pd(inbox->buf);
1959         pd_slave = (pd >> 17) & 0x7f;
1960         if (pd_slave != 0 && pd_slave != slave) {
1961                 err = -EPERM;
1962                 goto ex_abort;
1963         }
1964
1965         if (mr_is_fmr(inbox->buf)) {
1966                 /* FMR and Bind Enable are forbidden in slave devices. */
1967                 if (mr_is_bind_enabled(inbox->buf)) {
1968                         err = -EPERM;
1969                         goto ex_abort;
1970                 }
1971                 /* FMR and Memory Windows are also forbidden. */
1972                 if (!mr_is_region(inbox->buf)) {
1973                         err = -EPERM;
1974                         goto ex_abort;
1975                 }
1976         }
1977
1978         phys = mr_phys_mpt(inbox->buf);
1979         if (!phys) {
1980                 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
1981                 if (err)
1982                         goto ex_abort;
1983
1984                 err = check_mtt_range(dev, slave, mtt_base,
1985                                       mr_get_mtt_size(inbox->buf), mtt);
1986                 if (err)
1987                         goto ex_put;
1988
1989                 mpt->mtt = mtt;
1990         }
1991
1992         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
1993         if (err)
1994                 goto ex_put;
1995
1996         if (!phys) {
1997                 atomic_inc(&mtt->ref_count);
1998                 put_res(dev, slave, mtt->com.res_id, RES_MTT);
1999         }
2000
2001         res_end_move(dev, slave, RES_MPT, id);
2002         return 0;
2003
2004 ex_put:
2005         if (!phys)
2006                 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2007 ex_abort:
2008         res_abort_move(dev, slave, RES_MPT, id);
2009
2010         return err;
2011 }
2012
2013 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2014                            struct mlx4_vhcr *vhcr,
2015                            struct mlx4_cmd_mailbox *inbox,
2016                            struct mlx4_cmd_mailbox *outbox,
2017                            struct mlx4_cmd_info *cmd)
2018 {
2019         int err;
2020         int index = vhcr->in_modifier;
2021         struct res_mpt *mpt;
2022         int id;
2023
2024         id = index & mpt_mask(dev);
2025         err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2026         if (err)
2027                 return err;
2028
2029         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2030         if (err)
2031                 goto ex_abort;
2032
2033         if (mpt->mtt)
2034                 atomic_dec(&mpt->mtt->ref_count);
2035
2036         res_end_move(dev, slave, RES_MPT, id);
2037         return 0;
2038
2039 ex_abort:
2040         res_abort_move(dev, slave, RES_MPT, id);
2041
2042         return err;
2043 }
2044
2045 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2046                            struct mlx4_vhcr *vhcr,
2047                            struct mlx4_cmd_mailbox *inbox,
2048                            struct mlx4_cmd_mailbox *outbox,
2049                            struct mlx4_cmd_info *cmd)
2050 {
2051         int err;
2052         int index = vhcr->in_modifier;
2053         struct res_mpt *mpt;
2054         int id;
2055
2056         id = index & mpt_mask(dev);
2057         err = get_res(dev, slave, id, RES_MPT, &mpt);
2058         if (err)
2059                 return err;
2060
2061         if (mpt->com.from_state != RES_MPT_HW) {
2062                 err = -EBUSY;
2063                 goto out;
2064         }
2065
2066         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2067
2068 out:
2069         put_res(dev, slave, id, RES_MPT);
2070         return err;
2071 }
2072
2073 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2074 {
2075         return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2076 }
2077
2078 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2079 {
2080         return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2081 }
2082
2083 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2084 {
2085         return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2086 }
2087
2088 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2089                                   struct mlx4_qp_context *context)
2090 {
2091         u32 qpn = vhcr->in_modifier & 0xffffff;
2092         u32 qkey = 0;
2093
2094         if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2095                 return;
2096
2097         /* adjust qkey in qp context */
2098         context->qkey = cpu_to_be32(qkey);
2099 }
2100
2101 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2102                              struct mlx4_vhcr *vhcr,
2103                              struct mlx4_cmd_mailbox *inbox,
2104                              struct mlx4_cmd_mailbox *outbox,
2105                              struct mlx4_cmd_info *cmd)
2106 {
2107         int err;
2108         int qpn = vhcr->in_modifier & 0x7fffff;
2109         struct res_mtt *mtt;
2110         struct res_qp *qp;
2111         struct mlx4_qp_context *qpc = inbox->buf + 8;
2112         int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2113         int mtt_size = qp_get_mtt_size(qpc);
2114         struct res_cq *rcq;
2115         struct res_cq *scq;
2116         int rcqn = qp_get_rcqn(qpc);
2117         int scqn = qp_get_scqn(qpc);
2118         u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2119         int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2120         struct res_srq *srq;
2121         int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2122
2123         err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2124         if (err)
2125                 return err;
2126         qp->local_qpn = local_qpn;
2127         qp->sched_queue = 0;
2128         qp->qpc_flags = be32_to_cpu(qpc->flags);
2129
2130         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2131         if (err)
2132                 goto ex_abort;
2133
2134         err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2135         if (err)
2136                 goto ex_put_mtt;
2137
2138         err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2139         if (err)
2140                 goto ex_put_mtt;
2141
2142         if (scqn != rcqn) {
2143                 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2144                 if (err)
2145                         goto ex_put_rcq;
2146         } else
2147                 scq = rcq;
2148
2149         if (use_srq) {
2150                 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2151                 if (err)
2152                         goto ex_put_scq;
2153         }
2154
2155         adjust_proxy_tun_qkey(dev, vhcr, qpc);
2156         update_pkey_index(dev, slave, inbox);
2157         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2158         if (err)
2159                 goto ex_put_srq;
2160         atomic_inc(&mtt->ref_count);
2161         qp->mtt = mtt;
2162         atomic_inc(&rcq->ref_count);
2163         qp->rcq = rcq;
2164         atomic_inc(&scq->ref_count);
2165         qp->scq = scq;
2166
2167         if (scqn != rcqn)
2168                 put_res(dev, slave, scqn, RES_CQ);
2169
2170         if (use_srq) {
2171                 atomic_inc(&srq->ref_count);
2172                 put_res(dev, slave, srqn, RES_SRQ);
2173                 qp->srq = srq;
2174         }
2175         put_res(dev, slave, rcqn, RES_CQ);
2176         put_res(dev, slave, mtt_base, RES_MTT);
2177         res_end_move(dev, slave, RES_QP, qpn);
2178
2179         return 0;
2180
2181 ex_put_srq:
2182         if (use_srq)
2183                 put_res(dev, slave, srqn, RES_SRQ);
2184 ex_put_scq:
2185         if (scqn != rcqn)
2186                 put_res(dev, slave, scqn, RES_CQ);
2187 ex_put_rcq:
2188         put_res(dev, slave, rcqn, RES_CQ);
2189 ex_put_mtt:
2190         put_res(dev, slave, mtt_base, RES_MTT);
2191 ex_abort:
2192         res_abort_move(dev, slave, RES_QP, qpn);
2193
2194         return err;
2195 }
2196
2197 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
2198 {
2199         return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2200 }
2201
2202 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2203 {
2204         int log_eq_size = eqc->log_eq_size & 0x1f;
2205         int page_shift = (eqc->log_page_size & 0x3f) + 12;
2206
2207         if (log_eq_size + 5 < page_shift)
2208                 return 1;
2209
2210         return 1 << (log_eq_size + 5 - page_shift);
2211 }
2212
2213 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
2214 {
2215         return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
2216 }
2217
2218 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
2219 {
2220         int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
2221         int page_shift = (cqc->log_page_size & 0x3f) + 12;
2222
2223         if (log_cq_size + 5 < page_shift)
2224                 return 1;
2225
2226         return 1 << (log_cq_size + 5 - page_shift);
2227 }
2228
2229 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2230                           struct mlx4_vhcr *vhcr,
2231                           struct mlx4_cmd_mailbox *inbox,
2232                           struct mlx4_cmd_mailbox *outbox,
2233                           struct mlx4_cmd_info *cmd)
2234 {
2235         int err;
2236         int eqn = vhcr->in_modifier;
2237         int res_id = (slave << 8) | eqn;
2238         struct mlx4_eq_context *eqc = inbox->buf;
2239         int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
2240         int mtt_size = eq_get_mtt_size(eqc);
2241         struct res_eq *eq;
2242         struct res_mtt *mtt;
2243
2244         err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2245         if (err)
2246                 return err;
2247         err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
2248         if (err)
2249                 goto out_add;
2250
2251         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2252         if (err)
2253                 goto out_move;
2254
2255         err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2256         if (err)
2257                 goto out_put;
2258
2259         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2260         if (err)
2261                 goto out_put;
2262
2263         atomic_inc(&mtt->ref_count);
2264         eq->mtt = mtt;
2265         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2266         res_end_move(dev, slave, RES_EQ, res_id);
2267         return 0;
2268
2269 out_put:
2270         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2271 out_move:
2272         res_abort_move(dev, slave, RES_EQ, res_id);
2273 out_add:
2274         rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2275         return err;
2276 }
2277
2278 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
2279                               int len, struct res_mtt **res)
2280 {
2281         struct mlx4_priv *priv = mlx4_priv(dev);
2282         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2283         struct res_mtt *mtt;
2284         int err = -EINVAL;
2285
2286         spin_lock_irq(mlx4_tlock(dev));
2287         list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
2288                             com.list) {
2289                 if (!check_mtt_range(dev, slave, start, len, mtt)) {
2290                         *res = mtt;
2291                         mtt->com.from_state = mtt->com.state;
2292                         mtt->com.state = RES_MTT_BUSY;
2293                         err = 0;
2294                         break;
2295                 }
2296         }
2297         spin_unlock_irq(mlx4_tlock(dev));
2298
2299         return err;
2300 }
2301
2302 static int verify_qp_parameters(struct mlx4_dev *dev,
2303                                 struct mlx4_cmd_mailbox *inbox,
2304                                 enum qp_transition transition, u8 slave)
2305 {
2306         u32                     qp_type;
2307         struct mlx4_qp_context  *qp_ctx;
2308         enum mlx4_qp_optpar     optpar;
2309
2310         qp_ctx  = inbox->buf + 8;
2311         qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
2312         optpar  = be32_to_cpu(*(__be32 *) inbox->buf);
2313
2314         switch (qp_type) {
2315         case MLX4_QP_ST_RC:
2316         case MLX4_QP_ST_UC:
2317                 switch (transition) {
2318                 case QP_TRANS_INIT2RTR:
2319                 case QP_TRANS_RTR2RTS:
2320                 case QP_TRANS_RTS2RTS:
2321                 case QP_TRANS_SQD2SQD:
2322                 case QP_TRANS_SQD2RTS:
2323                         if (slave != mlx4_master_func_num(dev))
2324                                 /* slaves have only gid index 0 */
2325                                 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
2326                                         if (qp_ctx->pri_path.mgid_index)
2327                                                 return -EINVAL;
2328                                 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
2329                                         if (qp_ctx->alt_path.mgid_index)
2330                                                 return -EINVAL;
2331                         break;
2332                 default:
2333                         break;
2334                 }
2335
2336                 break;
2337         default:
2338                 break;
2339         }
2340
2341         return 0;
2342 }
2343
2344 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
2345                            struct mlx4_vhcr *vhcr,
2346                            struct mlx4_cmd_mailbox *inbox,
2347                            struct mlx4_cmd_mailbox *outbox,
2348                            struct mlx4_cmd_info *cmd)
2349 {
2350         struct mlx4_mtt mtt;
2351         __be64 *page_list = inbox->buf;
2352         u64 *pg_list = (u64 *)page_list;
2353         int i;
2354         struct res_mtt *rmtt = NULL;
2355         int start = be64_to_cpu(page_list[0]);
2356         int npages = vhcr->in_modifier;
2357         int err;
2358
2359         err = get_containing_mtt(dev, slave, start, npages, &rmtt);
2360         if (err)
2361                 return err;
2362
2363         /* Call the SW implementation of write_mtt:
2364          * - Prepare a dummy mtt struct
2365          * - Translate inbox contents to simple addresses in host endianess */
2366         mtt.offset = 0;  /* TBD this is broken but I don't handle it since
2367                             we don't really use it */
2368         mtt.order = 0;
2369         mtt.page_shift = 0;
2370         for (i = 0; i < npages; ++i)
2371                 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
2372
2373         err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
2374                                ((u64 *)page_list + 2));
2375
2376         if (rmtt)
2377                 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
2378
2379         return err;
2380 }
2381
2382 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2383                           struct mlx4_vhcr *vhcr,
2384                           struct mlx4_cmd_mailbox *inbox,
2385                           struct mlx4_cmd_mailbox *outbox,
2386                           struct mlx4_cmd_info *cmd)
2387 {
2388         int eqn = vhcr->in_modifier;
2389         int res_id = eqn | (slave << 8);
2390         struct res_eq *eq;
2391         int err;
2392
2393         err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
2394         if (err)
2395                 return err;
2396
2397         err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
2398         if (err)
2399                 goto ex_abort;
2400
2401         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2402         if (err)
2403                 goto ex_put;
2404
2405         atomic_dec(&eq->mtt->ref_count);
2406         put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
2407         res_end_move(dev, slave, RES_EQ, res_id);
2408         rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2409
2410         return 0;
2411
2412 ex_put:
2413         put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
2414 ex_abort:
2415         res_abort_move(dev, slave, RES_EQ, res_id);
2416
2417         return err;
2418 }
2419
2420 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
2421 {
2422         struct mlx4_priv *priv = mlx4_priv(dev);
2423         struct mlx4_slave_event_eq_info *event_eq;
2424         struct mlx4_cmd_mailbox *mailbox;
2425         u32 in_modifier = 0;
2426         int err;
2427         int res_id;
2428         struct res_eq *req;
2429
2430         if (!priv->mfunc.master.slave_state)
2431                 return -EINVAL;
2432
2433         event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
2434
2435         /* Create the event only if the slave is registered */
2436         if (event_eq->eqn < 0)
2437                 return 0;
2438
2439         mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
2440         res_id = (slave << 8) | event_eq->eqn;
2441         err = get_res(dev, slave, res_id, RES_EQ, &req);
2442         if (err)
2443                 goto unlock;
2444
2445         if (req->com.from_state != RES_EQ_HW) {
2446                 err = -EINVAL;
2447                 goto put;
2448         }
2449
2450         mailbox = mlx4_alloc_cmd_mailbox(dev);
2451         if (IS_ERR(mailbox)) {
2452                 err = PTR_ERR(mailbox);
2453                 goto put;
2454         }
2455
2456         if (eqe->type == MLX4_EVENT_TYPE_CMD) {
2457                 ++event_eq->token;
2458                 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
2459         }
2460
2461         memcpy(mailbox->buf, (u8 *) eqe, 28);
2462
2463         in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
2464
2465         err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
2466                        MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
2467                        MLX4_CMD_NATIVE);
2468
2469         put_res(dev, slave, res_id, RES_EQ);
2470         mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
2471         mlx4_free_cmd_mailbox(dev, mailbox);
2472         return err;
2473
2474 put:
2475         put_res(dev, slave, res_id, RES_EQ);
2476
2477 unlock:
2478         mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
2479         return err;
2480 }
2481
2482 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
2483                           struct mlx4_vhcr *vhcr,
2484                           struct mlx4_cmd_mailbox *inbox,
2485                           struct mlx4_cmd_mailbox *outbox,
2486                           struct mlx4_cmd_info *cmd)
2487 {
2488         int eqn = vhcr->in_modifier;
2489         int res_id = eqn | (slave << 8);
2490         struct res_eq *eq;
2491         int err;
2492
2493         err = get_res(dev, slave, res_id, RES_EQ, &eq);
2494         if (err)
2495                 return err;
2496
2497         if (eq->com.from_state != RES_EQ_HW) {
2498                 err = -EINVAL;
2499                 goto ex_put;
2500         }
2501
2502         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2503
2504 ex_put:
2505         put_res(dev, slave, res_id, RES_EQ);
2506         return err;
2507 }
2508
2509 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
2510                           struct mlx4_vhcr *vhcr,
2511                           struct mlx4_cmd_mailbox *inbox,
2512                           struct mlx4_cmd_mailbox *outbox,
2513                           struct mlx4_cmd_info *cmd)
2514 {
2515         int err;
2516         int cqn = vhcr->in_modifier;
2517         struct mlx4_cq_context *cqc = inbox->buf;
2518         int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
2519         struct res_cq *cq;
2520         struct res_mtt *mtt;
2521
2522         err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
2523         if (err)
2524                 return err;
2525         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2526         if (err)
2527                 goto out_move;
2528         err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
2529         if (err)
2530                 goto out_put;
2531         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2532         if (err)
2533                 goto out_put;
2534         atomic_inc(&mtt->ref_count);
2535         cq->mtt = mtt;
2536         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2537         res_end_move(dev, slave, RES_CQ, cqn);
2538         return 0;
2539
2540 out_put:
2541         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2542 out_move:
2543         res_abort_move(dev, slave, RES_CQ, cqn);
2544         return err;
2545 }
2546
2547 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
2548                           struct mlx4_vhcr *vhcr,
2549                           struct mlx4_cmd_mailbox *inbox,
2550                           struct mlx4_cmd_mailbox *outbox,
2551                           struct mlx4_cmd_info *cmd)
2552 {
2553         int err;
2554         int cqn = vhcr->in_modifier;
2555         struct res_cq *cq;
2556
2557         err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
2558         if (err)
2559                 return err;
2560         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2561         if (err)
2562                 goto out_move;
2563         atomic_dec(&cq->mtt->ref_count);
2564         res_end_move(dev, slave, RES_CQ, cqn);
2565         return 0;
2566
2567 out_move:
2568         res_abort_move(dev, slave, RES_CQ, cqn);
2569         return err;
2570 }
2571
2572 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
2573                           struct mlx4_vhcr *vhcr,
2574                           struct mlx4_cmd_mailbox *inbox,
2575                           struct mlx4_cmd_mailbox *outbox,
2576                           struct mlx4_cmd_info *cmd)
2577 {
2578         int cqn = vhcr->in_modifier;
2579         struct res_cq *cq;
2580         int err;
2581
2582         err = get_res(dev, slave, cqn, RES_CQ, &cq);
2583         if (err)
2584                 return err;
2585
2586         if (cq->com.from_state != RES_CQ_HW)
2587                 goto ex_put;
2588
2589         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2590 ex_put:
2591         put_res(dev, slave, cqn, RES_CQ);
2592
2593         return err;
2594 }
2595
2596 static int handle_resize(struct mlx4_dev *dev, int slave,
2597                          struct mlx4_vhcr *vhcr,
2598                          struct mlx4_cmd_mailbox *inbox,
2599                          struct mlx4_cmd_mailbox *outbox,
2600                          struct mlx4_cmd_info *cmd,
2601                          struct res_cq *cq)
2602 {
2603         int err;
2604         struct res_mtt *orig_mtt;
2605         struct res_mtt *mtt;
2606         struct mlx4_cq_context *cqc = inbox->buf;
2607         int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
2608
2609         err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
2610         if (err)
2611                 return err;
2612
2613         if (orig_mtt != cq->mtt) {
2614                 err = -EINVAL;
2615                 goto ex_put;
2616         }
2617
2618         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2619         if (err)
2620                 goto ex_put;
2621
2622         err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
2623         if (err)
2624                 goto ex_put1;
2625         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2626         if (err)
2627                 goto ex_put1;
2628         atomic_dec(&orig_mtt->ref_count);
2629         put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
2630         atomic_inc(&mtt->ref_count);
2631         cq->mtt = mtt;
2632         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2633         return 0;
2634
2635 ex_put1:
2636         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2637 ex_put:
2638         put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
2639
2640         return err;
2641
2642 }
2643
2644 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
2645                            struct mlx4_vhcr *vhcr,
2646                            struct mlx4_cmd_mailbox *inbox,
2647                            struct mlx4_cmd_mailbox *outbox,
2648                            struct mlx4_cmd_info *cmd)
2649 {
2650         int cqn = vhcr->in_modifier;
2651         struct res_cq *cq;
2652         int err;
2653
2654         err = get_res(dev, slave, cqn, RES_CQ, &cq);
2655         if (err)
2656                 return err;
2657
2658         if (cq->com.from_state != RES_CQ_HW)
2659                 goto ex_put;
2660
2661         if (vhcr->op_modifier == 0) {
2662                 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
2663                 goto ex_put;
2664         }
2665
2666         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2667 ex_put:
2668         put_res(dev, slave, cqn, RES_CQ);
2669
2670         return err;
2671 }
2672
2673 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
2674 {
2675         int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
2676         int log_rq_stride = srqc->logstride & 7;
2677         int page_shift = (srqc->log_page_size & 0x3f) + 12;
2678
2679         if (log_srq_size + log_rq_stride + 4 < page_shift)
2680                 return 1;
2681
2682         return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
2683 }
2684
2685 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
2686                            struct mlx4_vhcr *vhcr,
2687                            struct mlx4_cmd_mailbox *inbox,
2688                            struct mlx4_cmd_mailbox *outbox,
2689                            struct mlx4_cmd_info *cmd)
2690 {
2691         int err;
2692         int srqn = vhcr->in_modifier;
2693         struct res_mtt *mtt;
2694         struct res_srq *srq;
2695         struct mlx4_srq_context *srqc = inbox->buf;
2696         int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
2697
2698         if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
2699                 return -EINVAL;
2700
2701         err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
2702         if (err)
2703                 return err;
2704         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2705         if (err)
2706                 goto ex_abort;
2707         err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
2708                               mtt);
2709         if (err)
2710                 goto ex_put_mtt;
2711
2712         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2713         if (err)
2714                 goto ex_put_mtt;
2715
2716         atomic_inc(&mtt->ref_count);
2717         srq->mtt = mtt;
2718         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2719         res_end_move(dev, slave, RES_SRQ, srqn);
2720         return 0;
2721
2722 ex_put_mtt:
2723         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2724 ex_abort:
2725         res_abort_move(dev, slave, RES_SRQ, srqn);
2726
2727         return err;
2728 }
2729
2730 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
2731                            struct mlx4_vhcr *vhcr,
2732                            struct mlx4_cmd_mailbox *inbox,
2733                            struct mlx4_cmd_mailbox *outbox,
2734                            struct mlx4_cmd_info *cmd)
2735 {
2736         int err;
2737         int srqn = vhcr->in_modifier;
2738         struct res_srq *srq;
2739
2740         err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
2741         if (err)
2742                 return err;
2743         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2744         if (err)
2745                 goto ex_abort;
2746         atomic_dec(&srq->mtt->ref_count);
2747         if (srq->cq)
2748                 atomic_dec(&srq->cq->ref_count);
2749         res_end_move(dev, slave, RES_SRQ, srqn);
2750
2751         return 0;
2752
2753 ex_abort:
2754         res_abort_move(dev, slave, RES_SRQ, srqn);
2755
2756         return err;
2757 }
2758
2759 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
2760                            struct mlx4_vhcr *vhcr,
2761                            struct mlx4_cmd_mailbox *inbox,
2762                            struct mlx4_cmd_mailbox *outbox,
2763                            struct mlx4_cmd_info *cmd)
2764 {
2765         int err;
2766         int srqn = vhcr->in_modifier;
2767         struct res_srq *srq;
2768
2769         err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2770         if (err)
2771                 return err;
2772         if (srq->com.from_state != RES_SRQ_HW) {
2773                 err = -EBUSY;
2774                 goto out;
2775         }
2776         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2777 out:
2778         put_res(dev, slave, srqn, RES_SRQ);
2779         return err;
2780 }
2781
2782 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
2783                          struct mlx4_vhcr *vhcr,
2784                          struct mlx4_cmd_mailbox *inbox,
2785                          struct mlx4_cmd_mailbox *outbox,
2786                          struct mlx4_cmd_info *cmd)
2787 {
2788         int err;
2789         int srqn = vhcr->in_modifier;
2790         struct res_srq *srq;
2791
2792         err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2793         if (err)
2794                 return err;
2795
2796         if (srq->com.from_state != RES_SRQ_HW) {
2797                 err = -EBUSY;
2798                 goto out;
2799         }
2800
2801         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2802 out:
2803         put_res(dev, slave, srqn, RES_SRQ);
2804         return err;
2805 }
2806
2807 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
2808                         struct mlx4_vhcr *vhcr,
2809                         struct mlx4_cmd_mailbox *inbox,
2810                         struct mlx4_cmd_mailbox *outbox,
2811                         struct mlx4_cmd_info *cmd)
2812 {
2813         int err;
2814         int qpn = vhcr->in_modifier & 0x7fffff;
2815         struct res_qp *qp;
2816
2817         err = get_res(dev, slave, qpn, RES_QP, &qp);
2818         if (err)
2819                 return err;
2820         if (qp->com.from_state != RES_QP_HW) {
2821                 err = -EBUSY;
2822                 goto out;
2823         }
2824
2825         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2826 out:
2827         put_res(dev, slave, qpn, RES_QP);
2828         return err;
2829 }
2830
2831 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2832                               struct mlx4_vhcr *vhcr,
2833                               struct mlx4_cmd_mailbox *inbox,
2834                               struct mlx4_cmd_mailbox *outbox,
2835                               struct mlx4_cmd_info *cmd)
2836 {
2837         struct mlx4_qp_context *context = inbox->buf + 8;
2838         adjust_proxy_tun_qkey(dev, vhcr, context);
2839         update_pkey_index(dev, slave, inbox);
2840         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2841 }
2842
2843 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
2844                              struct mlx4_vhcr *vhcr,
2845                              struct mlx4_cmd_mailbox *inbox,
2846                              struct mlx4_cmd_mailbox *outbox,
2847                              struct mlx4_cmd_info *cmd)
2848 {
2849         int err;
2850         struct mlx4_qp_context *qpc = inbox->buf + 8;
2851         int qpn = vhcr->in_modifier & 0x7fffff;
2852         struct res_qp *qp;
2853         u8 orig_sched_queue;
2854
2855         err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
2856         if (err)
2857                 return err;
2858
2859         update_pkey_index(dev, slave, inbox);
2860         update_gid(dev, inbox, (u8)slave);
2861         adjust_proxy_tun_qkey(dev, vhcr, qpc);
2862         orig_sched_queue = qpc->pri_path.sched_queue;
2863         err = update_vport_qp_param(dev, inbox, slave, qpn);
2864         if (err)
2865                 return err;
2866
2867         err = get_res(dev, slave, qpn, RES_QP, &qp);
2868         if (err)
2869                 return err;
2870         if (qp->com.from_state != RES_QP_HW) {
2871                 err = -EBUSY;
2872                 goto out;
2873         }
2874
2875         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2876 out:
2877         /* if no error, save sched queue value passed in by VF. This is
2878          * essentially the QOS value provided by the VF. This will be useful
2879          * if we allow dynamic changes from VST back to VGT
2880          */
2881         if (!err)
2882                 qp->sched_queue = orig_sched_queue;
2883
2884         put_res(dev, slave, qpn, RES_QP);
2885         return err;
2886 }
2887
2888 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
2889                             struct mlx4_vhcr *vhcr,
2890                             struct mlx4_cmd_mailbox *inbox,
2891                             struct mlx4_cmd_mailbox *outbox,
2892                             struct mlx4_cmd_info *cmd)
2893 {
2894         int err;
2895         struct mlx4_qp_context *context = inbox->buf + 8;
2896
2897         err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
2898         if (err)
2899                 return err;
2900
2901         update_pkey_index(dev, slave, inbox);
2902         update_gid(dev, inbox, (u8)slave);
2903         adjust_proxy_tun_qkey(dev, vhcr, context);
2904         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2905 }
2906
2907 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
2908                             struct mlx4_vhcr *vhcr,
2909                             struct mlx4_cmd_mailbox *inbox,
2910                             struct mlx4_cmd_mailbox *outbox,
2911                             struct mlx4_cmd_info *cmd)
2912 {
2913         int err;
2914         struct mlx4_qp_context *context = inbox->buf + 8;
2915
2916         err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
2917         if (err)
2918                 return err;
2919
2920         update_pkey_index(dev, slave, inbox);
2921         update_gid(dev, inbox, (u8)slave);
2922         adjust_proxy_tun_qkey(dev, vhcr, context);
2923         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2924 }
2925
2926
2927 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
2928                               struct mlx4_vhcr *vhcr,
2929                               struct mlx4_cmd_mailbox *inbox,
2930                               struct mlx4_cmd_mailbox *outbox,
2931                               struct mlx4_cmd_info *cmd)
2932 {
2933         struct mlx4_qp_context *context = inbox->buf + 8;
2934         adjust_proxy_tun_qkey(dev, vhcr, context);
2935         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2936 }
2937
2938 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
2939                             struct mlx4_vhcr *vhcr,
2940                             struct mlx4_cmd_mailbox *inbox,
2941                             struct mlx4_cmd_mailbox *outbox,
2942                             struct mlx4_cmd_info *cmd)
2943 {
2944         int err;
2945         struct mlx4_qp_context *context = inbox->buf + 8;
2946
2947         err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
2948         if (err)
2949                 return err;
2950
2951         adjust_proxy_tun_qkey(dev, vhcr, context);
2952         update_gid(dev, inbox, (u8)slave);
2953         update_pkey_index(dev, slave, inbox);
2954         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2955 }
2956
2957 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
2958                             struct mlx4_vhcr *vhcr,
2959                             struct mlx4_cmd_mailbox *inbox,
2960                             struct mlx4_cmd_mailbox *outbox,
2961                             struct mlx4_cmd_info *cmd)
2962 {
2963         int err;
2964         struct mlx4_qp_context *context = inbox->buf + 8;
2965
2966         err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
2967         if (err)
2968                 return err;
2969
2970         adjust_proxy_tun_qkey(dev, vhcr, context);
2971         update_gid(dev, inbox, (u8)slave);
2972         update_pkey_index(dev, slave, inbox);
2973         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2974 }
2975
2976 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
2977                          struct mlx4_vhcr *vhcr,
2978                          struct mlx4_cmd_mailbox *inbox,
2979                          struct mlx4_cmd_mailbox *outbox,
2980                          struct mlx4_cmd_info *cmd)
2981 {
2982         int err;
2983         int qpn = vhcr->in_modifier & 0x7fffff;
2984         struct res_qp *qp;
2985
2986         err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
2987         if (err)
2988                 return err;
2989         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2990         if (err)
2991                 goto ex_abort;
2992
2993         atomic_dec(&qp->mtt->ref_count);
2994         atomic_dec(&qp->rcq->ref_count);
2995         atomic_dec(&qp->scq->ref_count);
2996         if (qp->srq)
2997                 atomic_dec(&qp->srq->ref_count);
2998         res_end_move(dev, slave, RES_QP, qpn);
2999         return 0;
3000
3001 ex_abort:
3002         res_abort_move(dev, slave, RES_QP, qpn);
3003
3004         return err;
3005 }
3006
3007 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3008                                 struct res_qp *rqp, u8 *gid)
3009 {
3010         struct res_gid *res;
3011
3012         list_for_each_entry(res, &rqp->mcg_list, list) {
3013                 if (!memcmp(res->gid, gid, 16))
3014                         return res;
3015         }
3016         return NULL;
3017 }
3018
3019 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3020                        u8 *gid, enum mlx4_protocol prot,
3021                        enum mlx4_steer_type steer, u64 reg_id)
3022 {
3023         struct res_gid *res;
3024         int err;
3025
3026         res = kzalloc(sizeof *res, GFP_KERNEL);
3027         if (!res)
3028                 return -ENOMEM;
3029
3030         spin_lock_irq(&rqp->mcg_spl);
3031         if (find_gid(dev, slave, rqp, gid)) {
3032                 kfree(res);
3033                 err = -EEXIST;
3034         } else {
3035                 memcpy(res->gid, gid, 16);
3036                 res->prot = prot;
3037                 res->steer = steer;
3038                 res->reg_id = reg_id;
3039                 list_add_tail(&res->list, &rqp->mcg_list);
3040                 err = 0;
3041         }
3042         spin_unlock_irq(&rqp->mcg_spl);
3043
3044         return err;
3045 }
3046
3047 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3048                        u8 *gid, enum mlx4_protocol prot,
3049                        enum mlx4_steer_type steer, u64 *reg_id)
3050 {
3051         struct res_gid *res;
3052         int err;
3053
3054         spin_lock_irq(&rqp->mcg_spl);
3055         res = find_gid(dev, slave, rqp, gid);
3056         if (!res || res->prot != prot || res->steer != steer)
3057                 err = -EINVAL;
3058         else {
3059                 *reg_id = res->reg_id;
3060                 list_del(&res->list);
3061                 kfree(res);
3062                 err = 0;
3063         }
3064         spin_unlock_irq(&rqp->mcg_spl);
3065
3066         return err;
3067 }
3068
3069 static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
3070                      int block_loopback, enum mlx4_protocol prot,
3071                      enum mlx4_steer_type type, u64 *reg_id)
3072 {
3073         switch (dev->caps.steering_mode) {
3074         case MLX4_STEERING_MODE_DEVICE_MANAGED:
3075                 return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
3076                                                 block_loopback, prot,
3077                                                 reg_id);
3078         case MLX4_STEERING_MODE_B0:
3079                 return mlx4_qp_attach_common(dev, qp, gid,
3080                                             block_loopback, prot, type);
3081         default:
3082                 return -EINVAL;
3083         }
3084 }
3085
3086 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
3087                      enum mlx4_protocol prot, enum mlx4_steer_type type,
3088                      u64 reg_id)
3089 {
3090         switch (dev->caps.steering_mode) {
3091         case MLX4_STEERING_MODE_DEVICE_MANAGED:
3092                 return mlx4_flow_detach(dev, reg_id);
3093         case MLX4_STEERING_MODE_B0:
3094                 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
3095         default:
3096                 return -EINVAL;
3097         }
3098 }
3099
3100 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3101                                struct mlx4_vhcr *vhcr,
3102                                struct mlx4_cmd_mailbox *inbox,
3103                                struct mlx4_cmd_mailbox *outbox,
3104                                struct mlx4_cmd_info *cmd)
3105 {
3106         struct mlx4_qp qp; /* dummy for calling attach/detach */
3107         u8 *gid = inbox->buf;
3108         enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
3109         int err;
3110         int qpn;
3111         struct res_qp *rqp;
3112         u64 reg_id = 0;
3113         int attach = vhcr->op_modifier;
3114         int block_loopback = vhcr->in_modifier >> 31;
3115         u8 steer_type_mask = 2;
3116         enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
3117
3118         qpn = vhcr->in_modifier & 0xffffff;
3119         err = get_res(dev, slave, qpn, RES_QP, &rqp);
3120         if (err)
3121                 return err;
3122
3123         qp.qpn = qpn;
3124         if (attach) {
3125                 err = qp_attach(dev, &qp, gid, block_loopback, prot,
3126                                 type, &reg_id);
3127                 if (err) {
3128                         pr_err("Fail to attach rule to qp 0x%x\n", qpn);
3129                         goto ex_put;
3130                 }
3131                 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
3132                 if (err)
3133                         goto ex_detach;
3134         } else {
3135                 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
3136                 if (err)
3137                         goto ex_put;
3138
3139                 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
3140                 if (err)
3141                         pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
3142                                qpn, reg_id);
3143         }
3144         put_res(dev, slave, qpn, RES_QP);
3145         return err;
3146
3147 ex_detach:
3148         qp_detach(dev, &qp, gid, prot, type, reg_id);
3149 ex_put:
3150         put_res(dev, slave, qpn, RES_QP);
3151         return err;
3152 }
3153
3154 /*
3155  * MAC validation for Flow Steering rules.
3156  * VF can attach rules only with a mac address which is assigned to it.
3157  */
3158 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
3159                                    struct list_head *rlist)
3160 {
3161         struct mac_res *res, *tmp;
3162         __be64 be_mac;
3163
3164         /* make sure it isn't multicast or broadcast mac*/
3165         if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
3166             !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
3167                 list_for_each_entry_safe(res, tmp, rlist, list) {
3168                         be_mac = cpu_to_be64(res->mac << 16);
3169                         if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
3170                                 return 0;
3171                 }
3172                 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
3173                        eth_header->eth.dst_mac, slave);
3174                 return -EINVAL;
3175         }
3176         return 0;
3177 }
3178
3179 /*
3180  * In case of missing eth header, append eth header with a MAC address
3181  * assigned to the VF.
3182  */
3183 static int add_eth_header(struct mlx4_dev *dev, int slave,
3184                           struct mlx4_cmd_mailbox *inbox,
3185                           struct list_head *rlist, int header_id)
3186 {
3187         struct mac_res *res, *tmp;
3188         u8 port;
3189         struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3190         struct mlx4_net_trans_rule_hw_eth *eth_header;
3191         struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
3192         struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
3193         __be64 be_mac = 0;
3194         __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
3195
3196         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
3197         port = ctrl->port;
3198         eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
3199
3200         /* Clear a space in the inbox for eth header */
3201         switch (header_id) {
3202         case MLX4_NET_TRANS_RULE_ID_IPV4:
3203                 ip_header =
3204                         (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
3205                 memmove(ip_header, eth_header,
3206                         sizeof(*ip_header) + sizeof(*l4_header));
3207                 break;
3208         case MLX4_NET_TRANS_RULE_ID_TCP:
3209         case MLX4_NET_TRANS_RULE_ID_UDP:
3210                 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
3211                             (eth_header + 1);
3212                 memmove(l4_header, eth_header, sizeof(*l4_header));
3213                 break;
3214         default:
3215                 return -EINVAL;
3216         }
3217         list_for_each_entry_safe(res, tmp, rlist, list) {
3218                 if (port == res->port) {
3219                         be_mac = cpu_to_be64(res->mac << 16);
3220                         break;
3221                 }
3222         }
3223         if (!be_mac) {
3224                 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
3225                        port);
3226                 return -EINVAL;
3227         }
3228
3229         memset(eth_header, 0, sizeof(*eth_header));
3230         eth_header->size = sizeof(*eth_header) >> 2;
3231         eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
3232         memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
3233         memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
3234
3235         return 0;
3236
3237 }
3238
3239 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3240                                          struct mlx4_vhcr *vhcr,
3241                                          struct mlx4_cmd_mailbox *inbox,
3242                                          struct mlx4_cmd_mailbox *outbox,
3243                                          struct mlx4_cmd_info *cmd)
3244 {
3245
3246         struct mlx4_priv *priv = mlx4_priv(dev);
3247         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3248         struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
3249         int err;
3250         int qpn;
3251         struct res_qp *rqp;
3252         struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3253         struct _rule_hw  *rule_header;
3254         int header_id;
3255
3256         if (dev->caps.steering_mode !=
3257             MLX4_STEERING_MODE_DEVICE_MANAGED)
3258                 return -EOPNOTSUPP;
3259
3260         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
3261         qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
3262         err = get_res(dev, slave, qpn, RES_QP, &rqp);
3263         if (err) {
3264                 pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
3265                 return err;
3266         }
3267         rule_header = (struct _rule_hw *)(ctrl + 1);
3268         header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
3269
3270         switch (header_id) {
3271         case MLX4_NET_TRANS_RULE_ID_ETH:
3272                 if (validate_eth_header_mac(slave, rule_header, rlist)) {
3273                         err = -EINVAL;
3274                         goto err_put;
3275                 }
3276                 break;
3277         case MLX4_NET_TRANS_RULE_ID_IB:
3278                 break;
3279         case MLX4_NET_TRANS_RULE_ID_IPV4:
3280         case MLX4_NET_TRANS_RULE_ID_TCP:
3281         case MLX4_NET_TRANS_RULE_ID_UDP:
3282                 pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
3283                 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
3284                         err = -EINVAL;
3285                         goto err_put;
3286                 }
3287                 vhcr->in_modifier +=
3288                         sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
3289                 break;
3290         default:
3291                 pr_err("Corrupted mailbox.\n");
3292                 err = -EINVAL;
3293                 goto err_put;
3294         }
3295
3296         err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
3297                            vhcr->in_modifier, 0,
3298                            MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
3299                            MLX4_CMD_NATIVE);
3300         if (err)
3301                 goto err_put;
3302
3303         err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
3304         if (err) {
3305                 mlx4_err(dev, "Fail to add flow steering resources.\n ");
3306                 /* detach rule*/
3307                 mlx4_cmd(dev, vhcr->out_param, 0, 0,
3308                          MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
3309                          MLX4_CMD_NATIVE);
3310                 goto err_put;
3311         }
3312         atomic_inc(&rqp->ref_count);
3313 err_put:
3314         put_res(dev, slave, qpn, RES_QP);
3315         return err;
3316 }
3317
3318 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
3319                                          struct mlx4_vhcr *vhcr,
3320                                          struct mlx4_cmd_mailbox *inbox,
3321                                          struct mlx4_cmd_mailbox *outbox,
3322                                          struct mlx4_cmd_info *cmd)
3323 {
3324         int err;
3325         struct res_qp *rqp;
3326         struct res_fs_rule *rrule;
3327
3328         if (dev->caps.steering_mode !=
3329             MLX4_STEERING_MODE_DEVICE_MANAGED)
3330                 return -EOPNOTSUPP;
3331
3332         err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
3333         if (err)
3334                 return err;
3335         /* Release the rule form busy state before removal */
3336         put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
3337         err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
3338         if (err)
3339                 return err;
3340
3341         err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
3342         if (err) {
3343                 mlx4_err(dev, "Fail to remove flow steering resources.\n ");
3344                 goto out;
3345         }
3346
3347         err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
3348                        MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
3349                        MLX4_CMD_NATIVE);
3350         if (!err)
3351                 atomic_dec(&rqp->ref_count);
3352 out:
3353         put_res(dev, slave, rrule->qpn, RES_QP);
3354         return err;
3355 }
3356
3357 enum {
3358         BUSY_MAX_RETRIES = 10
3359 };
3360
3361 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
3362                                struct mlx4_vhcr *vhcr,
3363                                struct mlx4_cmd_mailbox *inbox,
3364                                struct mlx4_cmd_mailbox *outbox,
3365                                struct mlx4_cmd_info *cmd)
3366 {
3367         int err;
3368         int index = vhcr->in_modifier & 0xffff;
3369
3370         err = get_res(dev, slave, index, RES_COUNTER, NULL);
3371         if (err)
3372                 return err;
3373
3374         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3375         put_res(dev, slave, index, RES_COUNTER);
3376         return err;
3377 }
3378
3379 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
3380 {
3381         struct res_gid *rgid;
3382         struct res_gid *tmp;
3383         struct mlx4_qp qp; /* dummy for calling attach/detach */
3384
3385         list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
3386                 switch (dev->caps.steering_mode) {
3387                 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3388                         mlx4_flow_detach(dev, rgid->reg_id);
3389                         break;
3390                 case MLX4_STEERING_MODE_B0:
3391                         qp.qpn = rqp->local_qpn;
3392                         (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
3393                                                      rgid->prot, rgid->steer);
3394                         break;
3395                 }
3396                 list_del(&rgid->list);
3397                 kfree(rgid);
3398         }
3399 }
3400
3401 static int _move_all_busy(struct mlx4_dev *dev, int slave,
3402                           enum mlx4_resource type, int print)
3403 {
3404         struct mlx4_priv *priv = mlx4_priv(dev);
3405         struct mlx4_resource_tracker *tracker =
3406                 &priv->mfunc.master.res_tracker;
3407         struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
3408         struct res_common *r;
3409         struct res_common *tmp;
3410         int busy;
3411
3412         busy = 0;
3413         spin_lock_irq(mlx4_tlock(dev));
3414         list_for_each_entry_safe(r, tmp, rlist, list) {
3415                 if (r->owner == slave) {
3416                         if (!r->removing) {
3417                                 if (r->state == RES_ANY_BUSY) {
3418                                         if (print)
3419                                                 mlx4_dbg(dev,
3420                                                          "%s id 0x%llx is busy\n",
3421                                                           ResourceType(type),
3422                                                           r->res_id);
3423                                         ++busy;
3424                                 } else {
3425                                         r->from_state = r->state;
3426                                         r->state = RES_ANY_BUSY;
3427                                         r->removing = 1;
3428                                 }
3429                         }
3430                 }
3431         }
3432         spin_unlock_irq(mlx4_tlock(dev));
3433
3434         return busy;
3435 }
3436
3437 static int move_all_busy(struct mlx4_dev *dev, int slave,
3438                          enum mlx4_resource type)
3439 {
3440         unsigned long begin;
3441         int busy;
3442
3443         begin = jiffies;
3444         do {
3445                 busy = _move_all_busy(dev, slave, type, 0);
3446                 if (time_after(jiffies, begin + 5 * HZ))
3447                         break;
3448                 if (busy)
3449                         cond_resched();
3450         } while (busy);
3451
3452         if (busy)
3453                 busy = _move_all_busy(dev, slave, type, 1);
3454
3455         return busy;
3456 }
3457 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
3458 {
3459         struct mlx4_priv *priv = mlx4_priv(dev);
3460         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3461         struct list_head *qp_list =
3462                 &tracker->slave_list[slave].res_list[RES_QP];
3463         struct res_qp *qp;
3464         struct res_qp *tmp;
3465         int state;
3466         u64 in_param;
3467         int qpn;
3468         int err;
3469
3470         err = move_all_busy(dev, slave, RES_QP);
3471         if (err)
3472                 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
3473                           "for slave %d\n", slave);
3474
3475         spin_lock_irq(mlx4_tlock(dev));
3476         list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
3477                 spin_unlock_irq(mlx4_tlock(dev));
3478                 if (qp->com.owner == slave) {
3479                         qpn = qp->com.res_id;
3480                         detach_qp(dev, slave, qp);
3481                         state = qp->com.from_state;
3482                         while (state != 0) {
3483                                 switch (state) {
3484                                 case RES_QP_RESERVED:
3485                                         spin_lock_irq(mlx4_tlock(dev));
3486                                         rb_erase(&qp->com.node,
3487                                                  &tracker->res_tree[RES_QP]);
3488                                         list_del(&qp->com.list);
3489                                         spin_unlock_irq(mlx4_tlock(dev));
3490                                         kfree(qp);
3491                                         state = 0;
3492                                         break;
3493                                 case RES_QP_MAPPED:
3494                                         if (!valid_reserved(dev, slave, qpn))
3495                                                 __mlx4_qp_free_icm(dev, qpn);
3496                                         state = RES_QP_RESERVED;
3497                                         break;
3498                                 case RES_QP_HW:
3499                                         in_param = slave;
3500                                         err = mlx4_cmd(dev, in_param,
3501                                                        qp->local_qpn, 2,
3502                                                        MLX4_CMD_2RST_QP,
3503                                                        MLX4_CMD_TIME_CLASS_A,
3504                                                        MLX4_CMD_NATIVE);
3505                                         if (err)
3506                                                 mlx4_dbg(dev, "rem_slave_qps: failed"
3507                                                          " to move slave %d qpn %d to"
3508                                                          " reset\n", slave,
3509                                                          qp->local_qpn);
3510                                         atomic_dec(&qp->rcq->ref_count);
3511                                         atomic_dec(&qp->scq->ref_count);
3512                                         atomic_dec(&qp->mtt->ref_count);
3513                                         if (qp->srq)
3514                                                 atomic_dec(&qp->srq->ref_count);
3515                                         state = RES_QP_MAPPED;
3516                                         break;
3517                                 default:
3518                                         state = 0;
3519                                 }
3520                         }
3521                 }
3522                 spin_lock_irq(mlx4_tlock(dev));
3523         }
3524         spin_unlock_irq(mlx4_tlock(dev));
3525 }
3526
3527 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
3528 {
3529         struct mlx4_priv *priv = mlx4_priv(dev);
3530         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3531         struct list_head *srq_list =
3532                 &tracker->slave_list[slave].res_list[RES_SRQ];
3533         struct res_srq *srq;
3534         struct res_srq *tmp;
3535         int state;
3536         u64 in_param;
3537         LIST_HEAD(tlist);
3538         int srqn;
3539         int err;
3540
3541         err = move_all_busy(dev, slave, RES_SRQ);
3542         if (err)
3543                 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
3544                           "busy for slave %d\n", slave);
3545
3546         spin_lock_irq(mlx4_tlock(dev));
3547         list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
3548                 spin_unlock_irq(mlx4_tlock(dev));
3549                 if (srq->com.owner == slave) {
3550                         srqn = srq->com.res_id;
3551                         state = srq->com.from_state;
3552                         while (state != 0) {
3553                                 switch (state) {
3554                                 case RES_SRQ_ALLOCATED:
3555                                         __mlx4_srq_free_icm(dev, srqn);
3556                                         spin_lock_irq(mlx4_tlock(dev));
3557                                         rb_erase(&srq->com.node,
3558                                                  &tracker->res_tree[RES_SRQ]);
3559                                         list_del(&srq->com.list);
3560                                         spin_unlock_irq(mlx4_tlock(dev));
3561                                         kfree(srq);
3562                                         state = 0;
3563                                         break;
3564
3565                                 case RES_SRQ_HW:
3566                                         in_param = slave;
3567                                         err = mlx4_cmd(dev, in_param, srqn, 1,
3568                                                        MLX4_CMD_HW2SW_SRQ,
3569                                                        MLX4_CMD_TIME_CLASS_A,
3570                                                        MLX4_CMD_NATIVE);
3571                                         if (err)
3572                                                 mlx4_dbg(dev, "rem_slave_srqs: failed"
3573                                                          " to move slave %d srq %d to"
3574                                                          " SW ownership\n",
3575                                                          slave, srqn);
3576
3577                                         atomic_dec(&srq->mtt->ref_count);
3578                                         if (srq->cq)
3579                                                 atomic_dec(&srq->cq->ref_count);
3580                                         state = RES_SRQ_ALLOCATED;
3581                                         break;
3582
3583                                 default:
3584                                         state = 0;
3585                                 }
3586                         }
3587                 }
3588                 spin_lock_irq(mlx4_tlock(dev));
3589         }
3590         spin_unlock_irq(mlx4_tlock(dev));
3591 }
3592
3593 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
3594 {
3595         struct mlx4_priv *priv = mlx4_priv(dev);
3596         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3597         struct list_head *cq_list =
3598                 &tracker->slave_list[slave].res_list[RES_CQ];
3599         struct res_cq *cq;
3600         struct res_cq *tmp;
3601         int state;
3602         u64 in_param;
3603         LIST_HEAD(tlist);
3604         int cqn;
3605         int err;
3606
3607         err = move_all_busy(dev, slave, RES_CQ);
3608         if (err)
3609                 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
3610                           "busy for slave %d\n", slave);
3611
3612         spin_lock_irq(mlx4_tlock(dev));
3613         list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
3614                 spin_unlock_irq(mlx4_tlock(dev));
3615                 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
3616                         cqn = cq->com.res_id;
3617                         state = cq->com.from_state;
3618                         while (state != 0) {
3619                                 switch (state) {
3620                                 case RES_CQ_ALLOCATED:
3621                                         __mlx4_cq_free_icm(dev, cqn);
3622                                         spin_lock_irq(mlx4_tlock(dev));
3623                                         rb_erase(&cq->com.node,
3624                                                  &tracker->res_tree[RES_CQ]);
3625                                         list_del(&cq->com.list);
3626                                         spin_unlock_irq(mlx4_tlock(dev));
3627                                         kfree(cq);
3628                                         state = 0;
3629                                         break;
3630
3631                                 case RES_CQ_HW:
3632                                         in_param = slave;
3633                                         err = mlx4_cmd(dev, in_param, cqn, 1,
3634                                                        MLX4_CMD_HW2SW_CQ,
3635                                                        MLX4_CMD_TIME_CLASS_A,
3636                                                        MLX4_CMD_NATIVE);
3637                                         if (err)
3638                                                 mlx4_dbg(dev, "rem_slave_cqs: failed"
3639                                                          " to move slave %d cq %d to"
3640                                                          " SW ownership\n",
3641                                                          slave, cqn);
3642                                         atomic_dec(&cq->mtt->ref_count);
3643                                         state = RES_CQ_ALLOCATED;
3644                                         break;
3645
3646                                 default:
3647                                         state = 0;
3648                                 }
3649                         }
3650                 }
3651                 spin_lock_irq(mlx4_tlock(dev));
3652         }
3653         spin_unlock_irq(mlx4_tlock(dev));
3654 }
3655
3656 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
3657 {
3658         struct mlx4_priv *priv = mlx4_priv(dev);
3659         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3660         struct list_head *mpt_list =
3661                 &tracker->slave_list[slave].res_list[RES_MPT];
3662         struct res_mpt *mpt;
3663         struct res_mpt *tmp;
3664         int state;
3665         u64 in_param;
3666         LIST_HEAD(tlist);
3667         int mptn;
3668         int err;
3669
3670         err = move_all_busy(dev, slave, RES_MPT);
3671         if (err)
3672                 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
3673                           "busy for slave %d\n", slave);
3674
3675         spin_lock_irq(mlx4_tlock(dev));
3676         list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
3677                 spin_unlock_irq(mlx4_tlock(dev));
3678                 if (mpt->com.owner == slave) {
3679                         mptn = mpt->com.res_id;
3680                         state = mpt->com.from_state;
3681                         while (state != 0) {
3682                                 switch (state) {
3683                                 case RES_MPT_RESERVED:
3684                                         __mlx4_mpt_release(dev, mpt->key);
3685                                         spin_lock_irq(mlx4_tlock(dev));
3686                                         rb_erase(&mpt->com.node,
3687                                                  &tracker->res_tree[RES_MPT]);
3688                                         list_del(&mpt->com.list);
3689                                         spin_unlock_irq(mlx4_tlock(dev));
3690                                         kfree(mpt);
3691                                         state = 0;
3692                                         break;
3693
3694                                 case RES_MPT_MAPPED:
3695                                         __mlx4_mpt_free_icm(dev, mpt->key);
3696                                         state = RES_MPT_RESERVED;
3697                                         break;
3698
3699                                 case RES_MPT_HW:
3700                                         in_param = slave;
3701                                         err = mlx4_cmd(dev, in_param, mptn, 0,
3702                                                      MLX4_CMD_HW2SW_MPT,
3703                                                      MLX4_CMD_TIME_CLASS_A,
3704                                                      MLX4_CMD_NATIVE);
3705                                         if (err)
3706                                                 mlx4_dbg(dev, "rem_slave_mrs: failed"
3707                                                          " to move slave %d mpt %d to"
3708                                                          " SW ownership\n",
3709                                                          slave, mptn);
3710                                         if (mpt->mtt)
3711                                                 atomic_dec(&mpt->mtt->ref_count);
3712                                         state = RES_MPT_MAPPED;
3713                                         break;
3714                                 default:
3715                                         state = 0;
3716                                 }
3717                         }
3718                 }
3719                 spin_lock_irq(mlx4_tlock(dev));
3720         }
3721         spin_unlock_irq(mlx4_tlock(dev));
3722 }
3723
3724 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
3725 {
3726         struct mlx4_priv *priv = mlx4_priv(dev);
3727         struct mlx4_resource_tracker *tracker =
3728                 &priv->mfunc.master.res_tracker;
3729         struct list_head *mtt_list =
3730                 &tracker->slave_list[slave].res_list[RES_MTT];
3731         struct res_mtt *mtt;
3732         struct res_mtt *tmp;
3733         int state;
3734         LIST_HEAD(tlist);
3735         int base;
3736         int err;
3737
3738         err = move_all_busy(dev, slave, RES_MTT);
3739         if (err)
3740                 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
3741                           "busy for slave %d\n", slave);
3742
3743         spin_lock_irq(mlx4_tlock(dev));
3744         list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
3745                 spin_unlock_irq(mlx4_tlock(dev));
3746                 if (mtt->com.owner == slave) {
3747                         base = mtt->com.res_id;
3748                         state = mtt->com.from_state;
3749                         while (state != 0) {
3750                                 switch (state) {
3751                                 case RES_MTT_ALLOCATED:
3752                                         __mlx4_free_mtt_range(dev, base,
3753                                                               mtt->order);
3754                                         spin_lock_irq(mlx4_tlock(dev));
3755                                         rb_erase(&mtt->com.node,
3756                                                  &tracker->res_tree[RES_MTT]);
3757                                         list_del(&mtt->com.list);
3758                                         spin_unlock_irq(mlx4_tlock(dev));
3759                                         kfree(mtt);
3760                                         state = 0;
3761                                         break;
3762
3763                                 default:
3764                                         state = 0;
3765                                 }
3766                         }
3767                 }
3768                 spin_lock_irq(mlx4_tlock(dev));
3769         }
3770         spin_unlock_irq(mlx4_tlock(dev));
3771 }
3772
3773 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
3774 {
3775         struct mlx4_priv *priv = mlx4_priv(dev);
3776         struct mlx4_resource_tracker *tracker =
3777                 &priv->mfunc.master.res_tracker;
3778         struct list_head *fs_rule_list =
3779                 &tracker->slave_list[slave].res_list[RES_FS_RULE];
3780         struct res_fs_rule *fs_rule;
3781         struct res_fs_rule *tmp;
3782         int state;
3783         u64 base;
3784         int err;
3785
3786         err = move_all_busy(dev, slave, RES_FS_RULE);
3787         if (err)
3788                 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
3789                           slave);
3790
3791         spin_lock_irq(mlx4_tlock(dev));
3792         list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
3793                 spin_unlock_irq(mlx4_tlock(dev));
3794                 if (fs_rule->com.owner == slave) {
3795                         base = fs_rule->com.res_id;
3796                         state = fs_rule->com.from_state;
3797                         while (state != 0) {
3798                                 switch (state) {
3799                                 case RES_FS_RULE_ALLOCATED:
3800                                         /* detach rule */
3801                                         err = mlx4_cmd(dev, base, 0, 0,
3802                                                        MLX4_QP_FLOW_STEERING_DETACH,
3803                                                        MLX4_CMD_TIME_CLASS_A,
3804                                                        MLX4_CMD_NATIVE);
3805
3806                                         spin_lock_irq(mlx4_tlock(dev));
3807                                         rb_erase(&fs_rule->com.node,
3808                                                  &tracker->res_tree[RES_FS_RULE]);
3809                                         list_del(&fs_rule->com.list);
3810                                         spin_unlock_irq(mlx4_tlock(dev));
3811                                         kfree(fs_rule);
3812                                         state = 0;
3813                                         break;
3814
3815                                 default:
3816                                         state = 0;
3817                                 }
3818                         }
3819                 }
3820                 spin_lock_irq(mlx4_tlock(dev));
3821         }
3822         spin_unlock_irq(mlx4_tlock(dev));
3823 }
3824
3825 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
3826 {
3827         struct mlx4_priv *priv = mlx4_priv(dev);
3828         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3829         struct list_head *eq_list =
3830                 &tracker->slave_list[slave].res_list[RES_EQ];
3831         struct res_eq *eq;
3832         struct res_eq *tmp;
3833         int err;
3834         int state;
3835         LIST_HEAD(tlist);
3836         int eqn;
3837         struct mlx4_cmd_mailbox *mailbox;
3838
3839         err = move_all_busy(dev, slave, RES_EQ);
3840         if (err)
3841                 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
3842                           "busy for slave %d\n", slave);
3843
3844         spin_lock_irq(mlx4_tlock(dev));
3845         list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
3846                 spin_unlock_irq(mlx4_tlock(dev));
3847                 if (eq->com.owner == slave) {
3848                         eqn = eq->com.res_id;
3849                         state = eq->com.from_state;
3850                         while (state != 0) {
3851                                 switch (state) {
3852                                 case RES_EQ_RESERVED:
3853                                         spin_lock_irq(mlx4_tlock(dev));
3854                                         rb_erase(&eq->com.node,
3855                                                  &tracker->res_tree[RES_EQ]);
3856                                         list_del(&eq->com.list);
3857                                         spin_unlock_irq(mlx4_tlock(dev));
3858                                         kfree(eq);
3859                                         state = 0;
3860                                         break;
3861
3862                                 case RES_EQ_HW:
3863                                         mailbox = mlx4_alloc_cmd_mailbox(dev);
3864                                         if (IS_ERR(mailbox)) {
3865                                                 cond_resched();
3866                                                 continue;
3867                                         }
3868                                         err = mlx4_cmd_box(dev, slave, 0,
3869                                                            eqn & 0xff, 0,
3870                                                            MLX4_CMD_HW2SW_EQ,
3871                                                            MLX4_CMD_TIME_CLASS_A,
3872                                                            MLX4_CMD_NATIVE);
3873                                         if (err)
3874                                                 mlx4_dbg(dev, "rem_slave_eqs: failed"
3875                                                          " to move slave %d eqs %d to"
3876                                                          " SW ownership\n", slave, eqn);
3877                                         mlx4_free_cmd_mailbox(dev, mailbox);
3878                                         atomic_dec(&eq->mtt->ref_count);
3879                                         state = RES_EQ_RESERVED;
3880                                         break;
3881
3882                                 default:
3883                                         state = 0;
3884                                 }
3885                         }
3886                 }
3887                 spin_lock_irq(mlx4_tlock(dev));
3888         }
3889         spin_unlock_irq(mlx4_tlock(dev));
3890 }
3891
3892 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
3893 {
3894         struct mlx4_priv *priv = mlx4_priv(dev);
3895         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3896         struct list_head *counter_list =
3897                 &tracker->slave_list[slave].res_list[RES_COUNTER];
3898         struct res_counter *counter;
3899         struct res_counter *tmp;
3900         int err;
3901         int index;
3902
3903         err = move_all_busy(dev, slave, RES_COUNTER);
3904         if (err)
3905                 mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
3906                           "busy for slave %d\n", slave);
3907
3908         spin_lock_irq(mlx4_tlock(dev));
3909         list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
3910                 if (counter->com.owner == slave) {
3911                         index = counter->com.res_id;
3912                         rb_erase(&counter->com.node,
3913                                  &tracker->res_tree[RES_COUNTER]);
3914                         list_del(&counter->com.list);
3915                         kfree(counter);
3916                         __mlx4_counter_free(dev, index);
3917                 }
3918         }
3919         spin_unlock_irq(mlx4_tlock(dev));
3920 }
3921
3922 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
3923 {
3924         struct mlx4_priv *priv = mlx4_priv(dev);
3925         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3926         struct list_head *xrcdn_list =
3927                 &tracker->slave_list[slave].res_list[RES_XRCD];
3928         struct res_xrcdn *xrcd;
3929         struct res_xrcdn *tmp;
3930         int err;
3931         int xrcdn;
3932
3933         err = move_all_busy(dev, slave, RES_XRCD);
3934         if (err)
3935                 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
3936                           "busy for slave %d\n", slave);
3937
3938         spin_lock_irq(mlx4_tlock(dev));
3939         list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
3940                 if (xrcd->com.owner == slave) {
3941                         xrcdn = xrcd->com.res_id;
3942                         rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
3943                         list_del(&xrcd->com.list);
3944                         kfree(xrcd);
3945                         __mlx4_xrcd_free(dev, xrcdn);
3946                 }
3947         }
3948         spin_unlock_irq(mlx4_tlock(dev));
3949 }
3950
3951 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
3952 {
3953         struct mlx4_priv *priv = mlx4_priv(dev);
3954
3955         mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
3956         /*VLAN*/
3957         rem_slave_macs(dev, slave);
3958         rem_slave_fs_rule(dev, slave);
3959         rem_slave_qps(dev, slave);
3960         rem_slave_srqs(dev, slave);
3961         rem_slave_cqs(dev, slave);
3962         rem_slave_mrs(dev, slave);
3963         rem_slave_eqs(dev, slave);
3964         rem_slave_mtts(dev, slave);
3965         rem_slave_counters(dev, slave);
3966         rem_slave_xrcdns(dev, slave);
3967         mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
3968 }
3969
3970 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
3971 {
3972         struct mlx4_vf_immed_vlan_work *work =
3973                 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
3974         struct mlx4_cmd_mailbox *mailbox;
3975         struct mlx4_update_qp_context *upd_context;
3976         struct mlx4_dev *dev = &work->priv->dev;
3977         struct mlx4_resource_tracker *tracker =
3978                 &work->priv->mfunc.master.res_tracker;
3979         struct list_head *qp_list =
3980                 &tracker->slave_list[work->slave].res_list[RES_QP];
3981         struct res_qp *qp;
3982         struct res_qp *tmp;
3983         u64 qp_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
3984                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
3985                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
3986                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
3987                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
3988                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED) |
3989                        (1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
3990                        (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
3991
3992         int err;
3993         int port, errors = 0;
3994         u8 vlan_control;
3995
3996         if (mlx4_is_slave(dev)) {
3997                 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
3998                           work->slave);
3999                 goto out;
4000         }
4001
4002         mailbox = mlx4_alloc_cmd_mailbox(dev);
4003         if (IS_ERR(mailbox))
4004                 goto out;
4005
4006         if (!work->vlan_id)
4007                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4008                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4009         else
4010                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4011                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4012                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
4013
4014         upd_context = mailbox->buf;
4015         upd_context->primary_addr_path_mask = cpu_to_be64(qp_mask);
4016         upd_context->qp_context.pri_path.vlan_control = vlan_control;
4017         upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
4018
4019         spin_lock_irq(mlx4_tlock(dev));
4020         list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4021                 spin_unlock_irq(mlx4_tlock(dev));
4022                 if (qp->com.owner == work->slave) {
4023                         if (qp->com.from_state != RES_QP_HW ||
4024                             !qp->sched_queue ||  /* no INIT2RTR trans yet */
4025                             mlx4_is_qp_reserved(dev, qp->local_qpn) ||
4026                             qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
4027                                 spin_lock_irq(mlx4_tlock(dev));
4028                                 continue;
4029                         }
4030                         port = (qp->sched_queue >> 6 & 1) + 1;
4031                         if (port != work->port) {
4032                                 spin_lock_irq(mlx4_tlock(dev));
4033                                 continue;
4034                         }
4035                         upd_context->qp_context.pri_path.sched_queue =
4036                                 qp->sched_queue & 0xC7;
4037                         upd_context->qp_context.pri_path.sched_queue |=
4038                                 ((work->qos & 0x7) << 3);
4039
4040                         err = mlx4_cmd(dev, mailbox->dma,
4041                                        qp->local_qpn & 0xffffff,
4042                                        0, MLX4_CMD_UPDATE_QP,
4043                                        MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
4044                         if (err) {
4045                                 mlx4_info(dev, "UPDATE_QP failed for slave %d, "
4046                                           "port %d, qpn %d (%d)\n",
4047                                           work->slave, port, qp->local_qpn,
4048                                           err);
4049                                 errors++;
4050                         }
4051                 }
4052                 spin_lock_irq(mlx4_tlock(dev));
4053         }
4054         spin_unlock_irq(mlx4_tlock(dev));
4055         mlx4_free_cmd_mailbox(dev, mailbox);
4056
4057         if (errors)
4058                 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
4059                          errors, work->slave, work->port);
4060
4061         /* unregister previous vlan_id if needed and we had no errors
4062          * while updating the QPs
4063          */
4064         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
4065             NO_INDX != work->orig_vlan_ix)
4066                 __mlx4_unregister_vlan(&work->priv->dev, work->port,
4067                                        work->orig_vlan_ix);
4068 out:
4069         kfree(work);
4070         return;
4071 }