drivers/net/ethernet/mellanox/mlx4/resource_tracker.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
   4  * All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/sched.h>
  37 #include <linux/pci.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/io.h>
  41 #include <linux/slab.h>
  42 #include <linux/mlx4/cmd.h>
  43 #include <linux/mlx4/qp.h>
  44 #include <linux/if_ether.h>
  45 #include <linux/etherdevice.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49
  50 #define MLX4_MAC_VALID          (1ull << 63)
  51
  52 struct mac_res {
  53         struct list_head list;
  54         u64 mac;
  55         int ref_count;
  56         u8 smac_index;
  57         u8 port;
  58 };
  59
  60 struct vlan_res {
  61         struct list_head list;
  62         u16 vlan;
  63         int ref_count;
  64         int vlan_index;
  65         u8 port;
  66 };
  67
  68 struct res_common {
  69         struct list_head        list;
  70         struct rb_node          node;
  71         u64                     res_id;
  72         int                     owner;
  73         int                     state;
  74         int                     from_state;
  75         int                     to_state;
  76         int                     removing;
  77 };
  78
  79 enum {
  80         RES_ANY_BUSY = 1
  81 };
  82
  83 struct res_gid {
  84         struct list_head        list;
  85         u8                      gid[16];
  86         enum mlx4_protocol      prot;
  87         enum mlx4_steer_type    steer;
  88         u64                     reg_id;
  89 };
  90
  91 enum res_qp_states {
  92         RES_QP_BUSY = RES_ANY_BUSY,
  93
  94         /* QP number was allocated */
  95         RES_QP_RESERVED,
  96
  97         /* ICM memory for QP context was mapped */
  98         RES_QP_MAPPED,
  99
 100         /* QP is in hw ownership */
 101         RES_QP_HW
 102 };
 103
 104 struct res_qp {
 105         struct res_common       com;
 106         struct res_mtt         *mtt;
 107         struct res_cq          *rcq;
 108         struct res_cq          *scq;
 109         struct res_srq         *srq;
 110         struct list_head        mcg_list;
 111         spinlock_t              mcg_spl;
 112         int                     local_qpn;
 113         atomic_t                ref_count;
 114         u32                     qpc_flags;
 115         /* saved qp params before VST enforcement in order to restore on VGT */
 116         u8                      sched_queue;
 117         __be32                  param3;
 118         u8                      vlan_control;
 119         u8                      fvl_rx;
 120         u8                      pri_path_fl;
 121         u8                      vlan_index;
 122         u8                      feup;
 123 };
 124
 125 enum res_mtt_states {
 126         RES_MTT_BUSY = RES_ANY_BUSY,
 127         RES_MTT_ALLOCATED,
 128 };
 129
 130 static inline const char *mtt_states_str(enum res_mtt_states state)
 131 {
 132         switch (state) {
 133         case RES_MTT_BUSY: return "RES_MTT_BUSY";
 134         case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
 135         default: return "Unknown";
 136         }
 137 }
 138
 139 struct res_mtt {
 140         struct res_common       com;
 141         int                     order;
 142         atomic_t                ref_count;
 143 };
 144
 145 enum res_mpt_states {
 146         RES_MPT_BUSY = RES_ANY_BUSY,
 147         RES_MPT_RESERVED,
 148         RES_MPT_MAPPED,
 149         RES_MPT_HW,
 150 };
 151
 152 struct res_mpt {
 153         struct res_common       com;
 154         struct res_mtt         *mtt;
 155         int                     key;
 156 };
 157
 158 enum res_eq_states {
 159         RES_EQ_BUSY = RES_ANY_BUSY,
 160         RES_EQ_RESERVED,
 161         RES_EQ_HW,
 162 };
 163
 164 struct res_eq {
 165         struct res_common       com;
 166         struct res_mtt         *mtt;
 167 };
 168
 169 enum res_cq_states {
 170         RES_CQ_BUSY = RES_ANY_BUSY,
 171         RES_CQ_ALLOCATED,
 172         RES_CQ_HW,
 173 };
 174
 175 struct res_cq {
 176         struct res_common       com;
 177         struct res_mtt         *mtt;
 178         atomic_t                ref_count;
 179 };
 180
 181 enum res_srq_states {
 182         RES_SRQ_BUSY = RES_ANY_BUSY,
 183         RES_SRQ_ALLOCATED,
 184         RES_SRQ_HW,
 185 };
 186
 187 struct res_srq {
 188         struct res_common       com;
 189         struct res_mtt         *mtt;
 190         struct res_cq          *cq;
 191         atomic_t                ref_count;
 192 };
 193
 194 enum res_counter_states {
 195         RES_COUNTER_BUSY = RES_ANY_BUSY,
 196         RES_COUNTER_ALLOCATED,
 197 };
 198
 199 struct res_counter {
 200         struct res_common       com;
 201         int                     port;
 202 };
 203
 204 enum res_xrcdn_states {
 205         RES_XRCD_BUSY = RES_ANY_BUSY,
 206         RES_XRCD_ALLOCATED,
 207 };
 208
 209 struct res_xrcdn {
 210         struct res_common       com;
 211         int                     port;
 212 };
 213
 214 enum res_fs_rule_states {
 215         RES_FS_RULE_BUSY = RES_ANY_BUSY,
 216         RES_FS_RULE_ALLOCATED,
 217 };
 218
 219 struct res_fs_rule {
 220         struct res_common       com;
 221         int                     qpn;
 222 };
 223
 224 static int mlx4_is_eth(struct mlx4_dev *dev, int port)
 225 {
 226         return dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
 227 }
 228
 229 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
 230 {
 231         struct rb_node *node = root->rb_node;
 232
 233         while (node) {
 234                 struct res_common *res = container_of(node, struct res_common,
 235                                                       node);
 236
 237                 if (res_id < res->res_id)
 238                         node = node->rb_left;
 239                 else if (res_id > res->res_id)
 240                         node = node->rb_right;
 241                 else
 242                         return res;
 243         }
 244         return NULL;
 245 }
 246
 247 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
 248 {
 249         struct rb_node **new = &(root->rb_node), *parent = NULL;
 250
 251         /* Figure out where to put new node */
 252         while (*new) {
 253                 struct res_common *this = container_of(*new, struct res_common,
 254                                                        node);
 255
 256                 parent = *new;
 257                 if (res->res_id < this->res_id)
 258                         new = &((*new)->rb_left);
 259                 else if (res->res_id > this->res_id)
 260                         new = &((*new)->rb_right);
 261                 else
 262                         return -EEXIST;
 263         }
 264
 265         /* Add new node and rebalance tree. */
 266         rb_link_node(&res->node, parent, new);
 267         rb_insert_color(&res->node, root);
 268
 269         return 0;
 270 }
 271
 272 enum qp_transition {
 273         QP_TRANS_INIT2RTR,
 274         QP_TRANS_RTR2RTS,
 275         QP_TRANS_RTS2RTS,
 276         QP_TRANS_SQERR2RTS,
 277         QP_TRANS_SQD2SQD,
 278         QP_TRANS_SQD2RTS
 279 };
 280
 281 /* For Debug uses */
 282 static const char *ResourceType(enum mlx4_resource rt)
 283 {
 284         switch (rt) {
 285         case RES_QP: return "RES_QP";
 286         case RES_CQ: return "RES_CQ";
 287         case RES_SRQ: return "RES_SRQ";
 288         case RES_MPT: return "RES_MPT";
 289         case RES_MTT: return "RES_MTT";
 290         case RES_MAC: return  "RES_MAC";
 291         case RES_VLAN: return  "RES_VLAN";
 292         case RES_EQ: return "RES_EQ";
 293         case RES_COUNTER: return "RES_COUNTER";
 294         case RES_FS_RULE: return "RES_FS_RULE";
 295         case RES_XRCD: return "RES_XRCD";
 296         default: return "Unknown resource type !!!";
 297         };
 298 }
 299
 300 static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
 301 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
 302                                       enum mlx4_resource res_type, int count,
 303                                       int port)
 304 {
 305         struct mlx4_priv *priv = mlx4_priv(dev);
 306         struct resource_allocator *res_alloc =
 307                 &priv->mfunc.master.res_tracker.res_alloc[res_type];
 308         int err = -EINVAL;
 309         int allocated, free, reserved, guaranteed, from_free;
 310
 311         if (slave > dev->num_vfs)
 312                 return -EINVAL;
 313
 314         spin_lock(&res_alloc->alloc_lock);
 315         allocated = (port > 0) ?
 316                 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] :
 317                 res_alloc->allocated[slave];
 318         free = (port > 0) ? res_alloc->res_port_free[port - 1] :
 319                 res_alloc->res_free;
 320         reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
 321                 res_alloc->res_reserved;
 322         guaranteed = res_alloc->guaranteed[slave];
 323
 324         if (allocated + count > res_alloc->quota[slave])
 325                 goto out;
 326
 327         if (allocated + count <= guaranteed) {
 328                 err = 0;
 329         } else {
 330                 /* portion may need to be obtained from free area */
 331                 if (guaranteed - allocated > 0)
 332                         from_free = count - (guaranteed - allocated);
 333                 else
 334                         from_free = count;
 335
 336                 if (free - from_free > reserved)
 337                         err = 0;
 338         }
 339
 340         if (!err) {
 341                 /* grant the request */
 342                 if (port > 0) {
 343                         res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] += count;
 344                         res_alloc->res_port_free[port - 1] -= count;
 345                 } else {
 346                         res_alloc->allocated[slave] += count;
 347                         res_alloc->res_free -= count;
 348                 }
 349         }
 350
 351 out:
 352         spin_unlock(&res_alloc->alloc_lock);
 353         return err;
 354 }
 355
 356 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
 357                                     enum mlx4_resource res_type, int count,
 358                                     int port)
 359 {
 360         struct mlx4_priv *priv = mlx4_priv(dev);
 361         struct resource_allocator *res_alloc =
 362                 &priv->mfunc.master.res_tracker.res_alloc[res_type];
 363
 364         if (slave > dev->num_vfs)
 365                 return;
 366
 367         spin_lock(&res_alloc->alloc_lock);
 368         if (port > 0) {
 369                 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] -= count;
 370                 res_alloc->res_port_free[port - 1] += count;
 371         } else {
 372                 res_alloc->allocated[slave] -= count;
 373                 res_alloc->res_free += count;
 374         }
 375
 376         spin_unlock(&res_alloc->alloc_lock);
 377         return;
 378 }
 379
 380 static inline void initialize_res_quotas(struct mlx4_dev *dev,
 381                                          struct resource_allocator *res_alloc,
 382                                          enum mlx4_resource res_type,
 383                                          int vf, int num_instances)
 384 {
 385         res_alloc->guaranteed[vf] = num_instances / (2 * (dev->num_vfs + 1));
 386         res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
 387         if (vf == mlx4_master_func_num(dev)) {
 388                 res_alloc->res_free = num_instances;
 389                 if (res_type == RES_MTT) {
 390                         /* reserved mtts will be taken out of the PF allocation */
 391                         res_alloc->res_free += dev->caps.reserved_mtts;
 392                         res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
 393                         res_alloc->quota[vf] += dev->caps.reserved_mtts;
 394                 }
 395         }
 396 }
 397
 398 void mlx4_init_quotas(struct mlx4_dev *dev)
 399 {
 400         struct mlx4_priv *priv = mlx4_priv(dev);
 401         int pf;
 402
 403         /* quotas for VFs are initialized in mlx4_slave_cap */
 404         if (mlx4_is_slave(dev))
 405                 return;
 406
 407         if (!mlx4_is_mfunc(dev)) {
 408                 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
 409                         mlx4_num_reserved_sqps(dev);
 410                 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
 411                 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
 412                 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
 413                 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
 414                 return;
 415         }
 416
 417         pf = mlx4_master_func_num(dev);
 418         dev->quotas.qp =
 419                 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
 420         dev->quotas.cq =
 421                 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
 422         dev->quotas.srq =
 423                 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
 424         dev->quotas.mtt =
 425                 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
 426         dev->quotas.mpt =
 427                 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
 428 }
 429 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
 430 {
 431         struct mlx4_priv *priv = mlx4_priv(dev);
 432         int i, j;
 433         int t;
 434
 435         priv->mfunc.master.res_tracker.slave_list =
 436                 kzalloc(dev->num_slaves * sizeof(struct slave_list),
 437                         GFP_KERNEL);
 438         if (!priv->mfunc.master.res_tracker.slave_list)
 439                 return -ENOMEM;
 440
 441         for (i = 0 ; i < dev->num_slaves; i++) {
 442                 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
 443                         INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
 444                                        slave_list[i].res_list[t]);
 445                 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 446         }
 447
 448         mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
 449                  dev->num_slaves);
 450         for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
 451                 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
 452
 453         for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
 454                 struct resource_allocator *res_alloc =
 455                         &priv->mfunc.master.res_tracker.res_alloc[i];
 456                 res_alloc->quota = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
 457                 res_alloc->guaranteed = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
 458                 if (i == RES_MAC || i == RES_VLAN)
 459                         res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
 460                                                        (dev->num_vfs + 1) * sizeof(int),
 461                                                         GFP_KERNEL);
 462                 else
 463                         res_alloc->allocated = kzalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
 464
 465                 if (!res_alloc->quota || !res_alloc->guaranteed ||
 466                     !res_alloc->allocated)
 467                         goto no_mem_err;
 468
 469                 spin_lock_init(&res_alloc->alloc_lock);
 470                 for (t = 0; t < dev->num_vfs + 1; t++) {
 471                         struct mlx4_active_ports actv_ports =
 472                                 mlx4_get_active_ports(dev, t);
 473                         switch (i) {
 474                         case RES_QP:
 475                                 initialize_res_quotas(dev, res_alloc, RES_QP,
 476                                                       t, dev->caps.num_qps -
 477                                                       dev->caps.reserved_qps -
 478                                                       mlx4_num_reserved_sqps(dev));
 479                                 break;
 480                         case RES_CQ:
 481                                 initialize_res_quotas(dev, res_alloc, RES_CQ,
 482                                                       t, dev->caps.num_cqs -
 483                                                       dev->caps.reserved_cqs);
 484                                 break;
 485                         case RES_SRQ:
 486                                 initialize_res_quotas(dev, res_alloc, RES_SRQ,
 487                                                       t, dev->caps.num_srqs -
 488                                                       dev->caps.reserved_srqs);
 489                                 break;
 490                         case RES_MPT:
 491                                 initialize_res_quotas(dev, res_alloc, RES_MPT,
 492                                                       t, dev->caps.num_mpts -
 493                                                       dev->caps.reserved_mrws);
 494                                 break;
 495                         case RES_MTT:
 496                                 initialize_res_quotas(dev, res_alloc, RES_MTT,
 497                                                       t, dev->caps.num_mtts -
 498                                                       dev->caps.reserved_mtts);
 499                                 break;
 500                         case RES_MAC:
 501                                 if (t == mlx4_master_func_num(dev)) {
 502                                         int max_vfs_pport = 0;
 503                                         /* Calculate the max vfs per port for */
 504                                         /* both ports.                        */
 505                                         for (j = 0; j < dev->caps.num_ports;
 506                                              j++) {
 507                                                 struct mlx4_slaves_pport slaves_pport =
 508                                                         mlx4_phys_to_slaves_pport(dev, j + 1);
 509                                                 unsigned current_slaves =
 510                                                         bitmap_weight(slaves_pport.slaves,
 511                                                                       dev->caps.num_ports) - 1;
 512                                                 if (max_vfs_pport < current_slaves)
 513                                                         max_vfs_pport =
 514                                                                 current_slaves;
 515                                         }
 516                                         res_alloc->quota[t] =
 517                                                 MLX4_MAX_MAC_NUM -
 518                                                 2 * max_vfs_pport;
 519                                         res_alloc->guaranteed[t] = 2;
 520                                         for (j = 0; j < MLX4_MAX_PORTS; j++)
 521                                                 res_alloc->res_port_free[j] =
 522                                                         MLX4_MAX_MAC_NUM;
 523                                 } else {
 524                                         res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
 525                                         res_alloc->guaranteed[t] = 2;
 526                                 }
 527                                 break;
 528                         case RES_VLAN:
 529                                 if (t == mlx4_master_func_num(dev)) {
 530                                         res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
 531                                         res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
 532                                         for (j = 0; j < MLX4_MAX_PORTS; j++)
 533                                                 res_alloc->res_port_free[j] =
 534                                                         res_alloc->quota[t];
 535                                 } else {
 536                                         res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
 537                                         res_alloc->guaranteed[t] = 0;
 538                                 }
 539                                 break;
 540                         case RES_COUNTER:
 541                                 res_alloc->quota[t] = dev->caps.max_counters;
 542                                 res_alloc->guaranteed[t] = 0;
 543                                 if (t == mlx4_master_func_num(dev))
 544                                         res_alloc->res_free = res_alloc->quota[t];
 545                                 break;
 546                         default:
 547                                 break;
 548                         }
 549                         if (i == RES_MAC || i == RES_VLAN) {
 550                                 for (j = 0; j < dev->caps.num_ports; j++)
 551                                         if (test_bit(j, actv_ports.ports))
 552                                                 res_alloc->res_port_rsvd[j] +=
 553                                                         res_alloc->guaranteed[t];
 554                         } else {
 555                                 res_alloc->res_reserved += res_alloc->guaranteed[t];
 556                         }
 557                 }
 558         }
 559         spin_lock_init(&priv->mfunc.master.res_tracker.lock);
 560         return 0;
 561
 562 no_mem_err:
 563         for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
 564                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
 565                 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
 566                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
 567                 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
 568                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
 569                 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
 570         }
 571         return -ENOMEM;
 572 }
 573
 574 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
 575                                 enum mlx4_res_tracker_free_type type)
 576 {
 577         struct mlx4_priv *priv = mlx4_priv(dev);
 578         int i;
 579
 580         if (priv->mfunc.master.res_tracker.slave_list) {
 581                 if (type != RES_TR_FREE_STRUCTS_ONLY) {
 582                         for (i = 0; i < dev->num_slaves; i++) {
 583                                 if (type == RES_TR_FREE_ALL ||
 584                                     dev->caps.function != i)
 585                                         mlx4_delete_all_resources_for_slave(dev, i);
 586                         }
 587                         /* free master's vlans */
 588                         i = dev->caps.function;
 589                         mlx4_reset_roce_gids(dev, i);
 590                         mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 591                         rem_slave_vlans(dev, i);
 592                         mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
 593                 }
 594
 595                 if (type != RES_TR_FREE_SLAVES_ONLY) {
 596                         for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
 597                                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
 598                                 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
 599                                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
 600                                 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
 601                                 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
 602                                 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
 603                         }
 604                         kfree(priv->mfunc.master.res_tracker.slave_list);
 605                         priv->mfunc.master.res_tracker.slave_list = NULL;
 606                 }
 607         }
 608 }
 609
 610 static void update_pkey_index(struct mlx4_dev *dev, int slave,
 611                               struct mlx4_cmd_mailbox *inbox)
 612 {
 613         u8 sched = *(u8 *)(inbox->buf + 64);
 614         u8 orig_index = *(u8 *)(inbox->buf + 35);
 615         u8 new_index;
 616         struct mlx4_priv *priv = mlx4_priv(dev);
 617         int port;
 618
 619         port = (sched >> 6 & 1) + 1;
 620
 621         new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
 622         *(u8 *)(inbox->buf + 35) = new_index;
 623 }
 624
 625 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
 626                        u8 slave)
 627 {
 628         struct mlx4_qp_context  *qp_ctx = inbox->buf + 8;
 629         enum mlx4_qp_optpar     optpar = be32_to_cpu(*(__be32 *) inbox->buf);
 630         u32                     ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
 631         int port;
 632
 633         if (MLX4_QP_ST_UD == ts) {
 634                 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
 635                 if (mlx4_is_eth(dev, port))
 636                         qp_ctx->pri_path.mgid_index =
 637                                 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
 638                 else
 639                         qp_ctx->pri_path.mgid_index = slave | 0x80;
 640
 641         } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
 642                 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
 643                         port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
 644                         if (mlx4_is_eth(dev, port)) {
 645                                 qp_ctx->pri_path.mgid_index +=
 646                                         mlx4_get_base_gid_ix(dev, slave, port);
 647                                 qp_ctx->pri_path.mgid_index &= 0x7f;
 648                         } else {
 649                                 qp_ctx->pri_path.mgid_index = slave & 0x7F;
 650                         }
 651                 }
 652                 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
 653                         port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
 654                         if (mlx4_is_eth(dev, port)) {
 655                                 qp_ctx->alt_path.mgid_index +=
 656                                         mlx4_get_base_gid_ix(dev, slave, port);
 657                                 qp_ctx->alt_path.mgid_index &= 0x7f;
 658                         } else {
 659                                 qp_ctx->alt_path.mgid_index = slave & 0x7F;
 660                         }
 661                 }
 662         }
 663 }
 664
 665 static int update_vport_qp_param(struct mlx4_dev *dev,
 666                                  struct mlx4_cmd_mailbox *inbox,
 667                                  u8 slave, u32 qpn)
 668 {
 669         struct mlx4_qp_context  *qpc = inbox->buf + 8;
 670         struct mlx4_vport_oper_state *vp_oper;
 671         struct mlx4_priv *priv;
 672         int port;
 673
 674         port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
 675         priv = mlx4_priv(dev);
 676         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
 677
 678         if (MLX4_VGT != vp_oper->state.default_vlan) {
 679                 /* the reserved QPs (special, proxy, tunnel)
 680                  * do not operate over vlans
 681                  */
 682                 if (mlx4_is_qp_reserved(dev, qpn))
 683                         return 0;
 684
 685                 /* force strip vlan by clear vsd */
 686                 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
 687
 688                 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
 689                     dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
 690                         qpc->pri_path.vlan_control =
 691                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 692                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
 693                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
 694                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
 695                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
 696                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
 697                 } else if (0 != vp_oper->state.default_vlan) {
 698                         qpc->pri_path.vlan_control =
 699                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 700                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
 701                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
 702                 } else { /* priority tagged */
 703                         qpc->pri_path.vlan_control =
 704                                 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
 705                                 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
 706                 }
 707
 708                 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
 709                 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
 710                 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
 711                 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
 712                 qpc->pri_path.sched_queue &= 0xC7;
 713                 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
 714         }
 715         if (vp_oper->state.spoofchk) {
 716                 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
 717                 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
 718         }
 719         return 0;
 720 }
 721
 722 static int mpt_mask(struct mlx4_dev *dev)
 723 {
 724         return dev->caps.num_mpts - 1;
 725 }
 726
 727 static void *find_res(struct mlx4_dev *dev, u64 res_id,
 728                       enum mlx4_resource type)
 729 {
 730         struct mlx4_priv *priv = mlx4_priv(dev);
 731
 732         return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
 733                                   res_id);
 734 }
 735
 736 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
 737                    enum mlx4_resource type,
 738                    void *res)
 739 {
 740         struct res_common *r;
 741         int err = 0;
 742
 743         spin_lock_irq(mlx4_tlock(dev));
 744         r = find_res(dev, res_id, type);
 745         if (!r) {
 746                 err = -ENONET;
 747                 goto exit;
 748         }
 749
 750         if (r->state == RES_ANY_BUSY) {
 751                 err = -EBUSY;
 752                 goto exit;
 753         }
 754
 755         if (r->owner != slave) {
 756                 err = -EPERM;
 757                 goto exit;
 758         }
 759
 760         r->from_state = r->state;
 761         r->state = RES_ANY_BUSY;
 762
 763         if (res)
 764                 *((struct res_common **)res) = r;
 765
 766 exit:
 767         spin_unlock_irq(mlx4_tlock(dev));
 768         return err;
 769 }
 770
 771 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
 772                                     enum mlx4_resource type,
 773                                     u64 res_id, int *slave)
 774 {
 775
 776         struct res_common *r;
 777         int err = -ENOENT;
 778         int id = res_id;
 779
 780         if (type == RES_QP)
 781                 id &= 0x7fffff;
 782         spin_lock(mlx4_tlock(dev));
 783
 784         r = find_res(dev, id, type);
 785         if (r) {
 786                 *slave = r->owner;
 787                 err = 0;
 788         }
 789         spin_unlock(mlx4_tlock(dev));
 790
 791         return err;
 792 }
 793
 794 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
 795                     enum mlx4_resource type)
 796 {
 797         struct res_common *r;
 798
 799         spin_lock_irq(mlx4_tlock(dev));
 800         r = find_res(dev, res_id, type);
 801         if (r)
 802                 r->state = r->from_state;
 803         spin_unlock_irq(mlx4_tlock(dev));
 804 }
 805
 806 static struct res_common *alloc_qp_tr(int id)
 807 {
 808         struct res_qp *ret;
 809
 810         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 811         if (!ret)
 812                 return NULL;
 813
 814         ret->com.res_id = id;
 815         ret->com.state = RES_QP_RESERVED;
 816         ret->local_qpn = id;
 817         INIT_LIST_HEAD(&ret->mcg_list);
 818         spin_lock_init(&ret->mcg_spl);
 819         atomic_set(&ret->ref_count, 0);
 820
 821         return &ret->com;
 822 }
 823
 824 static struct res_common *alloc_mtt_tr(int id, int order)
 825 {
 826         struct res_mtt *ret;
 827
 828         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 829         if (!ret)
 830                 return NULL;
 831
 832         ret->com.res_id = id;
 833         ret->order = order;
 834         ret->com.state = RES_MTT_ALLOCATED;
 835         atomic_set(&ret->ref_count, 0);
 836
 837         return &ret->com;
 838 }
 839
 840 static struct res_common *alloc_mpt_tr(int id, int key)
 841 {
 842         struct res_mpt *ret;
 843
 844         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 845         if (!ret)
 846                 return NULL;
 847
 848         ret->com.res_id = id;
 849         ret->com.state = RES_MPT_RESERVED;
 850         ret->key = key;
 851
 852         return &ret->com;
 853 }
 854
 855 static struct res_common *alloc_eq_tr(int id)
 856 {
 857         struct res_eq *ret;
 858
 859         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 860         if (!ret)
 861                 return NULL;
 862
 863         ret->com.res_id = id;
 864         ret->com.state = RES_EQ_RESERVED;
 865
 866         return &ret->com;
 867 }
 868
 869 static struct res_common *alloc_cq_tr(int id)
 870 {
 871         struct res_cq *ret;
 872
 873         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 874         if (!ret)
 875                 return NULL;
 876
 877         ret->com.res_id = id;
 878         ret->com.state = RES_CQ_ALLOCATED;
 879         atomic_set(&ret->ref_count, 0);
 880
 881         return &ret->com;
 882 }
 883
 884 static struct res_common *alloc_srq_tr(int id)
 885 {
 886         struct res_srq *ret;
 887
 888         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 889         if (!ret)
 890                 return NULL;
 891
 892         ret->com.res_id = id;
 893         ret->com.state = RES_SRQ_ALLOCATED;
 894         atomic_set(&ret->ref_count, 0);
 895
 896         return &ret->com;
 897 }
 898
 899 static struct res_common *alloc_counter_tr(int id)
 900 {
 901         struct res_counter *ret;
 902
 903         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 904         if (!ret)
 905                 return NULL;
 906
 907         ret->com.res_id = id;
 908         ret->com.state = RES_COUNTER_ALLOCATED;
 909
 910         return &ret->com;
 911 }
 912
 913 static struct res_common *alloc_xrcdn_tr(int id)
 914 {
 915         struct res_xrcdn *ret;
 916
 917         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 918         if (!ret)
 919                 return NULL;
 920
 921         ret->com.res_id = id;
 922         ret->com.state = RES_XRCD_ALLOCATED;
 923
 924         return &ret->com;
 925 }
 926
 927 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
 928 {
 929         struct res_fs_rule *ret;
 930
 931         ret = kzalloc(sizeof *ret, GFP_KERNEL);
 932         if (!ret)
 933                 return NULL;
 934
 935         ret->com.res_id = id;
 936         ret->com.state = RES_FS_RULE_ALLOCATED;
 937         ret->qpn = qpn;
 938         return &ret->com;
 939 }
 940
 941 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
 942                                    int extra)
 943 {
 944         struct res_common *ret;
 945
 946         switch (type) {
 947         case RES_QP:
 948                 ret = alloc_qp_tr(id);
 949                 break;
 950         case RES_MPT:
 951                 ret = alloc_mpt_tr(id, extra);
 952                 break;
 953         case RES_MTT:
 954                 ret = alloc_mtt_tr(id, extra);
 955                 break;
 956         case RES_EQ:
 957                 ret = alloc_eq_tr(id);
 958                 break;
 959         case RES_CQ:
 960                 ret = alloc_cq_tr(id);
 961                 break;
 962         case RES_SRQ:
 963                 ret = alloc_srq_tr(id);
 964                 break;
 965         case RES_MAC:
 966                 printk(KERN_ERR "implementation missing\n");
 967                 return NULL;
 968         case RES_COUNTER:
 969                 ret = alloc_counter_tr(id);
 970                 break;
 971         case RES_XRCD:
 972                 ret = alloc_xrcdn_tr(id);
 973                 break;
 974         case RES_FS_RULE:
 975                 ret = alloc_fs_rule_tr(id, extra);
 976                 break;
 977         default:
 978                 return NULL;
 979         }
 980         if (ret)
 981                 ret->owner = slave;
 982
 983         return ret;
 984 }
 985
 986 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
 987                          enum mlx4_resource type, int extra)
 988 {
 989         int i;
 990         int err;
 991         struct mlx4_priv *priv = mlx4_priv(dev);
 992         struct res_common **res_arr;
 993         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
 994         struct rb_root *root = &tracker->res_tree[type];
 995
 996         res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
 997         if (!res_arr)
 998                 return -ENOMEM;
 999
1000         for (i = 0; i < count; ++i) {
1001                 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1002                 if (!res_arr[i]) {
1003                         for (--i; i >= 0; --i)
1004                                 kfree(res_arr[i]);
1005
1006                         kfree(res_arr);
1007                         return -ENOMEM;
1008                 }
1009         }
1010
1011         spin_lock_irq(mlx4_tlock(dev));
1012         for (i = 0; i < count; ++i) {
1013                 if (find_res(dev, base + i, type)) {
1014                         err = -EEXIST;
1015                         goto undo;
1016                 }
1017                 err = res_tracker_insert(root, res_arr[i]);
1018                 if (err)
1019                         goto undo;
1020                 list_add_tail(&res_arr[i]->list,
1021                               &tracker->slave_list[slave].res_list[type]);
1022         }
1023         spin_unlock_irq(mlx4_tlock(dev));
1024         kfree(res_arr);
1025
1026         return 0;
1027
1028 undo:
1029         for (--i; i >= base; --i)
1030                 rb_erase(&res_arr[i]->node, root);
1031
1032         spin_unlock_irq(mlx4_tlock(dev));
1033
1034         for (i = 0; i < count; ++i)
1035                 kfree(res_arr[i]);
1036
1037         kfree(res_arr);
1038
1039         return err;
1040 }
1041
1042 static int remove_qp_ok(struct res_qp *res)
1043 {
1044         if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1045             !list_empty(&res->mcg_list)) {
1046                 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1047                        res->com.state, atomic_read(&res->ref_count));
1048                 return -EBUSY;
1049         } else if (res->com.state != RES_QP_RESERVED) {
1050                 return -EPERM;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int remove_mtt_ok(struct res_mtt *res, int order)
1057 {
1058         if (res->com.state == RES_MTT_BUSY ||
1059             atomic_read(&res->ref_count)) {
1060                 printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
1061                        __func__, __LINE__,
1062                        mtt_states_str(res->com.state),
1063                        atomic_read(&res->ref_count));
1064                 return -EBUSY;
1065         } else if (res->com.state != RES_MTT_ALLOCATED)
1066                 return -EPERM;
1067         else if (res->order != order)
1068                 return -EINVAL;
1069
1070         return 0;
1071 }
1072
1073 static int remove_mpt_ok(struct res_mpt *res)
1074 {
1075         if (res->com.state == RES_MPT_BUSY)
1076                 return -EBUSY;
1077         else if (res->com.state != RES_MPT_RESERVED)
1078                 return -EPERM;
1079
1080         return 0;
1081 }
1082
1083 static int remove_eq_ok(struct res_eq *res)
1084 {
1085         if (res->com.state == RES_MPT_BUSY)
1086                 return -EBUSY;
1087         else if (res->com.state != RES_MPT_RESERVED)
1088                 return -EPERM;
1089
1090         return 0;
1091 }
1092
1093 static int remove_counter_ok(struct res_counter *res)
1094 {
1095         if (res->com.state == RES_COUNTER_BUSY)
1096                 return -EBUSY;
1097         else if (res->com.state != RES_COUNTER_ALLOCATED)
1098                 return -EPERM;
1099
1100         return 0;
1101 }
1102
1103 static int remove_xrcdn_ok(struct res_xrcdn *res)
1104 {
1105         if (res->com.state == RES_XRCD_BUSY)
1106                 return -EBUSY;
1107         else if (res->com.state != RES_XRCD_ALLOCATED)
1108                 return -EPERM;
1109
1110         return 0;
1111 }
1112
1113 static int remove_fs_rule_ok(struct res_fs_rule *res)
1114 {
1115         if (res->com.state == RES_FS_RULE_BUSY)
1116                 return -EBUSY;
1117         else if (res->com.state != RES_FS_RULE_ALLOCATED)
1118                 return -EPERM;
1119
1120         return 0;
1121 }
1122
1123 static int remove_cq_ok(struct res_cq *res)
1124 {
1125         if (res->com.state == RES_CQ_BUSY)
1126                 return -EBUSY;
1127         else if (res->com.state != RES_CQ_ALLOCATED)
1128                 return -EPERM;
1129
1130         return 0;
1131 }
1132
1133 static int remove_srq_ok(struct res_srq *res)
1134 {
1135         if (res->com.state == RES_SRQ_BUSY)
1136                 return -EBUSY;
1137         else if (res->com.state != RES_SRQ_ALLOCATED)
1138                 return -EPERM;
1139
1140         return 0;
1141 }
1142
1143 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1144 {
1145         switch (type) {
1146         case RES_QP:
1147                 return remove_qp_ok((struct res_qp *)res);
1148         case RES_CQ:
1149                 return remove_cq_ok((struct res_cq *)res);
1150         case RES_SRQ:
1151                 return remove_srq_ok((struct res_srq *)res);
1152         case RES_MPT:
1153                 return remove_mpt_ok((struct res_mpt *)res);
1154         case RES_MTT:
1155                 return remove_mtt_ok((struct res_mtt *)res, extra);
1156         case RES_MAC:
1157                 return -ENOSYS;
1158         case RES_EQ:
1159                 return remove_eq_ok((struct res_eq *)res);
1160         case RES_COUNTER:
1161                 return remove_counter_ok((struct res_counter *)res);
1162         case RES_XRCD:
1163                 return remove_xrcdn_ok((struct res_xrcdn *)res);
1164         case RES_FS_RULE:
1165                 return remove_fs_rule_ok((struct res_fs_rule *)res);
1166         default:
1167                 return -EINVAL;
1168         }
1169 }
1170
1171 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1172                          enum mlx4_resource type, int extra)
1173 {
1174         u64 i;
1175         int err;
1176         struct mlx4_priv *priv = mlx4_priv(dev);
1177         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1178         struct res_common *r;
1179
1180         spin_lock_irq(mlx4_tlock(dev));
1181         for (i = base; i < base + count; ++i) {
1182                 r = res_tracker_lookup(&tracker->res_tree[type], i);
1183                 if (!r) {
1184                         err = -ENOENT;
1185                         goto out;
1186                 }
1187                 if (r->owner != slave) {
1188                         err = -EPERM;
1189                         goto out;
1190                 }
1191                 err = remove_ok(r, type, extra);
1192                 if (err)
1193                         goto out;
1194         }
1195
1196         for (i = base; i < base + count; ++i) {
1197                 r = res_tracker_lookup(&tracker->res_tree[type], i);
1198                 rb_erase(&r->node, &tracker->res_tree[type]);
1199                 list_del(&r->list);
1200                 kfree(r);
1201         }
1202         err = 0;
1203
1204 out:
1205         spin_unlock_irq(mlx4_tlock(dev));
1206
1207         return err;
1208 }
1209
1210 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1211                                 enum res_qp_states state, struct res_qp **qp,
1212                                 int alloc)
1213 {
1214         struct mlx4_priv *priv = mlx4_priv(dev);
1215         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1216         struct res_qp *r;
1217         int err = 0;
1218
1219         spin_lock_irq(mlx4_tlock(dev));
1220         r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
1221         if (!r)
1222                 err = -ENOENT;
1223         else if (r->com.owner != slave)
1224                 err = -EPERM;
1225         else {
1226                 switch (state) {
1227                 case RES_QP_BUSY:
1228                         mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
1229                                  __func__, r->com.res_id);
1230                         err = -EBUSY;
1231                         break;
1232
1233                 case RES_QP_RESERVED:
1234                         if (r->com.state == RES_QP_MAPPED && !alloc)
1235                                 break;
1236
1237                         mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
1238                         err = -EINVAL;
1239                         break;
1240
1241                 case RES_QP_MAPPED:
1242                         if ((r->com.state == RES_QP_RESERVED && alloc) ||
1243                             r->com.state == RES_QP_HW)
1244                                 break;
1245                         else {
1246                                 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
1247                                           r->com.res_id);
1248                                 err = -EINVAL;
1249                         }
1250
1251                         break;
1252
1253                 case RES_QP_HW:
1254                         if (r->com.state != RES_QP_MAPPED)
1255                                 err = -EINVAL;
1256                         break;
1257                 default:
1258                         err = -EINVAL;
1259                 }
1260
1261                 if (!err) {
1262                         r->com.from_state = r->com.state;
1263                         r->com.to_state = state;
1264                         r->com.state = RES_QP_BUSY;
1265                         if (qp)
1266                                 *qp = r;
1267                 }
1268         }
1269
1270         spin_unlock_irq(mlx4_tlock(dev));
1271
1272         return err;
1273 }
1274
1275 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1276                                 enum res_mpt_states state, struct res_mpt **mpt)
1277 {
1278         struct mlx4_priv *priv = mlx4_priv(dev);
1279         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1280         struct res_mpt *r;
1281         int err = 0;
1282
1283         spin_lock_irq(mlx4_tlock(dev));
1284         r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
1285         if (!r)
1286                 err = -ENOENT;
1287         else if (r->com.owner != slave)
1288                 err = -EPERM;
1289         else {
1290                 switch (state) {
1291                 case RES_MPT_BUSY:
1292                         err = -EINVAL;
1293                         break;
1294
1295                 case RES_MPT_RESERVED:
1296                         if (r->com.state != RES_MPT_MAPPED)
1297                                 err = -EINVAL;
1298                         break;
1299
1300                 case RES_MPT_MAPPED:
1301                         if (r->com.state != RES_MPT_RESERVED &&
1302                             r->com.state != RES_MPT_HW)
1303                                 err = -EINVAL;
1304                         break;
1305
1306                 case RES_MPT_HW:
1307                         if (r->com.state != RES_MPT_MAPPED)
1308                                 err = -EINVAL;
1309                         break;
1310                 default:
1311                         err = -EINVAL;
1312                 }
1313
1314                 if (!err) {
1315                         r->com.from_state = r->com.state;
1316                         r->com.to_state = state;
1317                         r->com.state = RES_MPT_BUSY;
1318                         if (mpt)
1319                                 *mpt = r;
1320                 }
1321         }
1322
1323         spin_unlock_irq(mlx4_tlock(dev));
1324
1325         return err;
1326 }
1327
1328 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1329                                 enum res_eq_states state, struct res_eq **eq)
1330 {
1331         struct mlx4_priv *priv = mlx4_priv(dev);
1332         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1333         struct res_eq *r;
1334         int err = 0;
1335
1336         spin_lock_irq(mlx4_tlock(dev));
1337         r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1338         if (!r)
1339                 err = -ENOENT;
1340         else if (r->com.owner != slave)
1341                 err = -EPERM;
1342         else {
1343                 switch (state) {
1344                 case RES_EQ_BUSY:
1345                         err = -EINVAL;
1346                         break;
1347
1348                 case RES_EQ_RESERVED:
1349                         if (r->com.state != RES_EQ_HW)
1350                                 err = -EINVAL;
1351                         break;
1352
1353                 case RES_EQ_HW:
1354                         if (r->com.state != RES_EQ_RESERVED)
1355                                 err = -EINVAL;
1356                         break;
1357
1358                 default:
1359                         err = -EINVAL;
1360                 }
1361
1362                 if (!err) {
1363                         r->com.from_state = r->com.state;
1364                         r->com.to_state = state;
1365                         r->com.state = RES_EQ_BUSY;
1366                         if (eq)
1367                                 *eq = r;
1368                 }
1369         }
1370
1371         spin_unlock_irq(mlx4_tlock(dev));
1372
1373         return err;
1374 }
1375
1376 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1377                                 enum res_cq_states state, struct res_cq **cq)
1378 {
1379         struct mlx4_priv *priv = mlx4_priv(dev);
1380         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1381         struct res_cq *r;
1382         int err;
1383
1384         spin_lock_irq(mlx4_tlock(dev));
1385         r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1386         if (!r) {
1387                 err = -ENOENT;
1388         } else if (r->com.owner != slave) {
1389                 err = -EPERM;
1390         } else if (state == RES_CQ_ALLOCATED) {
1391                 if (r->com.state != RES_CQ_HW)
1392                         err = -EINVAL;
1393                 else if (atomic_read(&r->ref_count))
1394                         err = -EBUSY;
1395                 else
1396                         err = 0;
1397         } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1398                 err = -EINVAL;
1399         } else {
1400                 err = 0;
1401         }
1402
1403         if (!err) {
1404                 r->com.from_state = r->com.state;
1405                 r->com.to_state = state;
1406                 r->com.state = RES_CQ_BUSY;
1407                 if (cq)
1408                         *cq = r;
1409         }
1410
1411         spin_unlock_irq(mlx4_tlock(dev));
1412
1413         return err;
1414 }
1415
1416 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1417                                  enum res_srq_states state, struct res_srq **srq)
1418 {
1419         struct mlx4_priv *priv = mlx4_priv(dev);
1420         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1421         struct res_srq *r;
1422         int err = 0;
1423
1424         spin_lock_irq(mlx4_tlock(dev));
1425         r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1426         if (!r) {
1427                 err = -ENOENT;
1428         } else if (r->com.owner != slave) {
1429                 err = -EPERM;
1430         } else if (state == RES_SRQ_ALLOCATED) {
1431                 if (r->com.state != RES_SRQ_HW)
1432                         err = -EINVAL;
1433                 else if (atomic_read(&r->ref_count))
1434                         err = -EBUSY;
1435         } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1436                 err = -EINVAL;
1437         }
1438
1439         if (!err) {
1440                 r->com.from_state = r->com.state;
1441                 r->com.to_state = state;
1442                 r->com.state = RES_SRQ_BUSY;
1443                 if (srq)
1444                         *srq = r;
1445         }
1446
1447         spin_unlock_irq(mlx4_tlock(dev));
1448
1449         return err;
1450 }
1451
1452 static void res_abort_move(struct mlx4_dev *dev, int slave,
1453                            enum mlx4_resource type, int id)
1454 {
1455         struct mlx4_priv *priv = mlx4_priv(dev);
1456         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1457         struct res_common *r;
1458
1459         spin_lock_irq(mlx4_tlock(dev));
1460         r = res_tracker_lookup(&tracker->res_tree[type], id);
1461         if (r && (r->owner == slave))
1462                 r->state = r->from_state;
1463         spin_unlock_irq(mlx4_tlock(dev));
1464 }
1465
1466 static void res_end_move(struct mlx4_dev *dev, int slave,
1467                          enum mlx4_resource type, int id)
1468 {
1469         struct mlx4_priv *priv = mlx4_priv(dev);
1470         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1471         struct res_common *r;
1472
1473         spin_lock_irq(mlx4_tlock(dev));
1474         r = res_tracker_lookup(&tracker->res_tree[type], id);
1475         if (r && (r->owner == slave))
1476                 r->state = r->to_state;
1477         spin_unlock_irq(mlx4_tlock(dev));
1478 }
1479
1480 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1481 {
1482         return mlx4_is_qp_reserved(dev, qpn) &&
1483                 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1484 }
1485
1486 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1487 {
1488         return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1489 }
1490
1491 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1492                         u64 in_param, u64 *out_param)
1493 {
1494         int err;
1495         int count;
1496         int align;
1497         int base;
1498         int qpn;
1499
1500         switch (op) {
1501         case RES_OP_RESERVE:
1502                 count = get_param_l(&in_param);
1503                 align = get_param_h(&in_param);
1504                 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
1505                 if (err)
1506                         return err;
1507
1508                 err = __mlx4_qp_reserve_range(dev, count, align, &base);
1509                 if (err) {
1510                         mlx4_release_resource(dev, slave, RES_QP, count, 0);
1511                         return err;
1512                 }
1513
1514                 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1515                 if (err) {
1516                         mlx4_release_resource(dev, slave, RES_QP, count, 0);
1517                         __mlx4_qp_release_range(dev, base, count);
1518                         return err;
1519                 }
1520                 set_param_l(out_param, base);
1521                 break;
1522         case RES_OP_MAP_ICM:
1523                 qpn = get_param_l(&in_param) & 0x7fffff;
1524                 if (valid_reserved(dev, slave, qpn)) {
1525                         err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1526                         if (err)
1527                                 return err;
1528                 }
1529
1530                 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1531                                            NULL, 1);
1532                 if (err)
1533                         return err;
1534
1535                 if (!fw_reserved(dev, qpn)) {
1536                         err = __mlx4_qp_alloc_icm(dev, qpn);
1537                         if (err) {
1538                                 res_abort_move(dev, slave, RES_QP, qpn);
1539                                 return err;
1540                         }
1541                 }
1542
1543                 res_end_move(dev, slave, RES_QP, qpn);
1544                 break;
1545
1546         default:
1547                 err = -EINVAL;
1548                 break;
1549         }
1550         return err;
1551 }
1552
1553 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1554                          u64 in_param, u64 *out_param)
1555 {
1556         int err = -EINVAL;
1557         int base;
1558         int order;
1559
1560         if (op != RES_OP_RESERVE_AND_MAP)
1561                 return err;
1562
1563         order = get_param_l(&in_param);
1564
1565         err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1566         if (err)
1567                 return err;
1568
1569         base = __mlx4_alloc_mtt_range(dev, order);
1570         if (base == -1) {
1571                 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1572                 return -ENOMEM;
1573         }
1574
1575         err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1576         if (err) {
1577                 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1578                 __mlx4_free_mtt_range(dev, base, order);
1579         } else {
1580                 set_param_l(out_param, base);
1581         }
1582
1583         return err;
1584 }
1585
1586 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1587                          u64 in_param, u64 *out_param)
1588 {
1589         int err = -EINVAL;
1590         int index;
1591         int id;
1592         struct res_mpt *mpt;
1593
1594         switch (op) {
1595         case RES_OP_RESERVE:
1596                 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1597                 if (err)
1598                         break;
1599
1600                 index = __mlx4_mpt_reserve(dev);
1601                 if (index == -1) {
1602                         mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1603                         break;
1604                 }
1605                 id = index & mpt_mask(dev);
1606
1607                 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1608                 if (err) {
1609                         mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1610                         __mlx4_mpt_release(dev, index);
1611                         break;
1612                 }
1613                 set_param_l(out_param, index);
1614                 break;
1615         case RES_OP_MAP_ICM:
1616                 index = get_param_l(&in_param);
1617                 id = index & mpt_mask(dev);
1618                 err = mr_res_start_move_to(dev, slave, id,
1619                                            RES_MPT_MAPPED, &mpt);
1620                 if (err)
1621                         return err;
1622
1623                 err = __mlx4_mpt_alloc_icm(dev, mpt->key);
1624                 if (err) {
1625                         res_abort_move(dev, slave, RES_MPT, id);
1626                         return err;
1627                 }
1628
1629                 res_end_move(dev, slave, RES_MPT, id);
1630                 break;
1631         }
1632         return err;
1633 }
1634
1635 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1636                         u64 in_param, u64 *out_param)
1637 {
1638         int cqn;
1639         int err;
1640
1641         switch (op) {
1642         case RES_OP_RESERVE_AND_MAP:
1643                 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
1644                 if (err)
1645                         break;
1646
1647                 err = __mlx4_cq_alloc_icm(dev, &cqn);
1648                 if (err) {
1649                         mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1650                         break;
1651                 }
1652
1653                 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1654                 if (err) {
1655                         mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1656                         __mlx4_cq_free_icm(dev, cqn);
1657                         break;
1658                 }
1659
1660                 set_param_l(out_param, cqn);
1661                 break;
1662
1663         default:
1664                 err = -EINVAL;
1665         }
1666
1667         return err;
1668 }
1669
1670 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1671                          u64 in_param, u64 *out_param)
1672 {
1673         int srqn;
1674         int err;
1675
1676         switch (op) {
1677         case RES_OP_RESERVE_AND_MAP:
1678                 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
1679                 if (err)
1680                         break;
1681
1682                 err = __mlx4_srq_alloc_icm(dev, &srqn);
1683                 if (err) {
1684                         mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1685                         break;
1686                 }
1687
1688                 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1689                 if (err) {
1690                         mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1691                         __mlx4_srq_free_icm(dev, srqn);
1692                         break;
1693                 }
1694
1695                 set_param_l(out_param, srqn);
1696                 break;
1697
1698         default:
1699                 err = -EINVAL;
1700         }
1701
1702         return err;
1703 }
1704
1705 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1706                                      u8 smac_index, u64 *mac)
1707 {
1708         struct mlx4_priv *priv = mlx4_priv(dev);
1709         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1710         struct list_head *mac_list =
1711                 &tracker->slave_list[slave].res_list[RES_MAC];
1712         struct mac_res *res, *tmp;
1713
1714         list_for_each_entry_safe(res, tmp, mac_list, list) {
1715                 if (res->smac_index == smac_index && res->port == (u8) port) {
1716                         *mac = res->mac;
1717                         return 0;
1718                 }
1719         }
1720         return -ENOENT;
1721 }
1722
1723 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
1724 {
1725         struct mlx4_priv *priv = mlx4_priv(dev);
1726         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1727         struct list_head *mac_list =
1728                 &tracker->slave_list[slave].res_list[RES_MAC];
1729         struct mac_res *res, *tmp;
1730
1731         list_for_each_entry_safe(res, tmp, mac_list, list) {
1732                 if (res->mac == mac && res->port == (u8) port) {
1733                         /* mac found. update ref count */
1734                         ++res->ref_count;
1735                         return 0;
1736                 }
1737         }
1738
1739         if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1740                 return -EINVAL;
1741         res = kzalloc(sizeof *res, GFP_KERNEL);
1742         if (!res) {
1743                 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1744                 return -ENOMEM;
1745         }
1746         res->mac = mac;
1747         res->port = (u8) port;
1748         res->smac_index = smac_index;
1749         res->ref_count = 1;
1750         list_add_tail(&res->list,
1751                       &tracker->slave_list[slave].res_list[RES_MAC]);
1752         return 0;
1753 }
1754
1755 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1756                                int port)
1757 {
1758         struct mlx4_priv *priv = mlx4_priv(dev);
1759         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1760         struct list_head *mac_list =
1761                 &tracker->slave_list[slave].res_list[RES_MAC];
1762         struct mac_res *res, *tmp;
1763
1764         list_for_each_entry_safe(res, tmp, mac_list, list) {
1765                 if (res->mac == mac && res->port == (u8) port) {
1766                         if (!--res->ref_count) {
1767                                 list_del(&res->list);
1768                                 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1769                                 kfree(res);
1770                         }
1771                         break;
1772                 }
1773         }
1774 }
1775
1776 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
1777 {
1778         struct mlx4_priv *priv = mlx4_priv(dev);
1779         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1780         struct list_head *mac_list =
1781                 &tracker->slave_list[slave].res_list[RES_MAC];
1782         struct mac_res *res, *tmp;
1783         int i;
1784
1785         list_for_each_entry_safe(res, tmp, mac_list, list) {
1786                 list_del(&res->list);
1787                 /* dereference the mac the num times the slave referenced it */
1788                 for (i = 0; i < res->ref_count; i++)
1789                         __mlx4_unregister_mac(dev, res->port, res->mac);
1790                 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
1791                 kfree(res);
1792         }
1793 }
1794
1795 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1796                          u64 in_param, u64 *out_param, int in_port)
1797 {
1798         int err = -EINVAL;
1799         int port;
1800         u64 mac;
1801         u8 smac_index;
1802
1803         if (op != RES_OP_RESERVE_AND_MAP)
1804                 return err;
1805
1806         port = !in_port ? get_param_l(out_param) : in_port;
1807         port = mlx4_slave_convert_port(
1808                         dev, slave, port);
1809
1810         if (port < 0)
1811                 return -EINVAL;
1812         mac = in_param;
1813
1814         err = __mlx4_register_mac(dev, port, mac);
1815         if (err >= 0) {
1816                 smac_index = err;
1817                 set_param_l(out_param, err);
1818                 err = 0;
1819         }
1820
1821         if (!err) {
1822                 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
1823                 if (err)
1824                         __mlx4_unregister_mac(dev, port, mac);
1825         }
1826         return err;
1827 }
1828
1829 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1830                              int port, int vlan_index)
1831 {
1832         struct mlx4_priv *priv = mlx4_priv(dev);
1833         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1834         struct list_head *vlan_list =
1835                 &tracker->slave_list[slave].res_list[RES_VLAN];
1836         struct vlan_res *res, *tmp;
1837
1838         list_for_each_entry_safe(res, tmp, vlan_list, list) {
1839                 if (res->vlan == vlan && res->port == (u8) port) {
1840                         /* vlan found. update ref count */
1841                         ++res->ref_count;
1842                         return 0;
1843                 }
1844         }
1845
1846         if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
1847                 return -EINVAL;
1848         res = kzalloc(sizeof(*res), GFP_KERNEL);
1849         if (!res) {
1850                 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
1851                 return -ENOMEM;
1852         }
1853         res->vlan = vlan;
1854         res->port = (u8) port;
1855         res->vlan_index = vlan_index;
1856         res->ref_count = 1;
1857         list_add_tail(&res->list,
1858                       &tracker->slave_list[slave].res_list[RES_VLAN]);
1859         return 0;
1860 }
1861
1862
1863 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1864                                 int port)
1865 {
1866         struct mlx4_priv *priv = mlx4_priv(dev);
1867         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1868         struct list_head *vlan_list =
1869                 &tracker->slave_list[slave].res_list[RES_VLAN];
1870         struct vlan_res *res, *tmp;
1871
1872         list_for_each_entry_safe(res, tmp, vlan_list, list) {
1873                 if (res->vlan == vlan && res->port == (u8) port) {
1874                         if (!--res->ref_count) {
1875                                 list_del(&res->list);
1876                                 mlx4_release_resource(dev, slave, RES_VLAN,
1877                                                       1, port);
1878                                 kfree(res);
1879                         }
1880                         break;
1881                 }
1882         }
1883 }
1884
1885 static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
1886 {
1887         struct mlx4_priv *priv = mlx4_priv(dev);
1888         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1889         struct list_head *vlan_list =
1890                 &tracker->slave_list[slave].res_list[RES_VLAN];
1891         struct vlan_res *res, *tmp;
1892         int i;
1893
1894         list_for_each_entry_safe(res, tmp, vlan_list, list) {
1895                 list_del(&res->list);
1896                 /* dereference the vlan the num times the slave referenced it */
1897                 for (i = 0; i < res->ref_count; i++)
1898                         __mlx4_unregister_vlan(dev, res->port, res->vlan);
1899                 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
1900                 kfree(res);
1901         }
1902 }
1903
1904 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1905                           u64 in_param, u64 *out_param, int in_port)
1906 {
1907         struct mlx4_priv *priv = mlx4_priv(dev);
1908         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1909         int err;
1910         u16 vlan;
1911         int vlan_index;
1912         int port;
1913
1914         port = !in_port ? get_param_l(out_param) : in_port;
1915
1916         if (!port || op != RES_OP_RESERVE_AND_MAP)
1917                 return -EINVAL;
1918
1919         port = mlx4_slave_convert_port(
1920                         dev, slave, port);
1921
1922         if (port < 0)
1923                 return -EINVAL;
1924         /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
1925         if (!in_port && port > 0 && port <= dev->caps.num_ports) {
1926                 slave_state[slave].old_vlan_api = true;
1927                 return 0;
1928         }
1929
1930         vlan = (u16) in_param;
1931
1932         err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
1933         if (!err) {
1934                 set_param_l(out_param, (u32) vlan_index);
1935                 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
1936                 if (err)
1937                         __mlx4_unregister_vlan(dev, port, vlan);
1938         }
1939         return err;
1940 }
1941
1942 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1943                              u64 in_param, u64 *out_param)
1944 {
1945         u32 index;
1946         int err;
1947
1948         if (op != RES_OP_RESERVE)
1949                 return -EINVAL;
1950
1951         err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
1952         if (err)
1953                 return err;
1954
1955         err = __mlx4_counter_alloc(dev, &index);
1956         if (err) {
1957                 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
1958                 return err;
1959         }
1960
1961         err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
1962         if (err) {
1963                 __mlx4_counter_free(dev, index);
1964                 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
1965         } else {
1966                 set_param_l(out_param, index);
1967         }
1968
1969         return err;
1970 }
1971
1972 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1973                            u64 in_param, u64 *out_param)
1974 {
1975         u32 xrcdn;
1976         int err;
1977
1978         if (op != RES_OP_RESERVE)
1979                 return -EINVAL;
1980
1981         err = __mlx4_xrcd_alloc(dev, &xrcdn);
1982         if (err)
1983                 return err;
1984
1985         err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
1986         if (err)
1987                 __mlx4_xrcd_free(dev, xrcdn);
1988         else
1989                 set_param_l(out_param, xrcdn);
1990
1991         return err;
1992 }
1993
1994 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1995                            struct mlx4_vhcr *vhcr,
1996                            struct mlx4_cmd_mailbox *inbox,
1997                            struct mlx4_cmd_mailbox *outbox,
1998                            struct mlx4_cmd_info *cmd)
1999 {
2000         int err;
2001         int alop = vhcr->op_modifier;
2002
2003         switch (vhcr->in_modifier & 0xFF) {
2004         case RES_QP:
2005                 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2006                                    vhcr->in_param, &vhcr->out_param);
2007                 break;
2008
2009         case RES_MTT:
2010                 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2011                                     vhcr->in_param, &vhcr->out_param);
2012                 break;
2013
2014         case RES_MPT:
2015                 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2016                                     vhcr->in_param, &vhcr->out_param);
2017                 break;
2018
2019         case RES_CQ:
2020                 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2021                                    vhcr->in_param, &vhcr->out_param);
2022                 break;
2023
2024         case RES_SRQ:
2025                 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2026                                     vhcr->in_param, &vhcr->out_param);
2027                 break;
2028
2029         case RES_MAC:
2030                 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
2031                                     vhcr->in_param, &vhcr->out_param,
2032                                     (vhcr->in_modifier >> 8) & 0xFF);
2033                 break;
2034
2035         case RES_VLAN:
2036                 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
2037                                      vhcr->in_param, &vhcr->out_param,
2038                                      (vhcr->in_modifier >> 8) & 0xFF);
2039                 break;
2040
2041         case RES_COUNTER:
2042                 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2043                                         vhcr->in_param, &vhcr->out_param);
2044                 break;
2045
2046         case RES_XRCD:
2047                 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2048                                       vhcr->in_param, &vhcr->out_param);
2049                 break;
2050
2051         default:
2052                 err = -EINVAL;
2053                 break;
2054         }
2055
2056         return err;
2057 }
2058
2059 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2060                        u64 in_param)
2061 {
2062         int err;
2063         int count;
2064         int base;
2065         int qpn;
2066
2067         switch (op) {
2068         case RES_OP_RESERVE:
2069                 base = get_param_l(&in_param) & 0x7fffff;
2070                 count = get_param_h(&in_param);
2071                 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2072                 if (err)
2073                         break;
2074                 mlx4_release_resource(dev, slave, RES_QP, count, 0);
2075                 __mlx4_qp_release_range(dev, base, count);
2076                 break;
2077         case RES_OP_MAP_ICM:
2078                 qpn = get_param_l(&in_param) & 0x7fffff;
2079                 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2080                                            NULL, 0);
2081                 if (err)
2082                         return err;
2083
2084                 if (!fw_reserved(dev, qpn))
2085                         __mlx4_qp_free_icm(dev, qpn);
2086
2087                 res_end_move(dev, slave, RES_QP, qpn);
2088
2089                 if (valid_reserved(dev, slave, qpn))
2090                         err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2091                 break;
2092         default:
2093                 err = -EINVAL;
2094                 break;
2095         }
2096         return err;
2097 }
2098
2099 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2100                         u64 in_param, u64 *out_param)
2101 {
2102         int err = -EINVAL;
2103         int base;
2104         int order;
2105
2106         if (op != RES_OP_RESERVE_AND_MAP)
2107                 return err;
2108
2109         base = get_param_l(&in_param);
2110         order = get_param_h(&in_param);
2111         err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
2112         if (!err) {
2113                 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
2114                 __mlx4_free_mtt_range(dev, base, order);
2115         }
2116         return err;
2117 }
2118
2119 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2120                         u64 in_param)
2121 {
2122         int err = -EINVAL;
2123         int index;
2124         int id;
2125         struct res_mpt *mpt;
2126
2127         switch (op) {
2128         case RES_OP_RESERVE:
2129                 index = get_param_l(&in_param);
2130                 id = index & mpt_mask(dev);
2131                 err = get_res(dev, slave, id, RES_MPT, &mpt);
2132                 if (err)
2133                         break;
2134                 index = mpt->key;
2135                 put_res(dev, slave, id, RES_MPT);
2136
2137                 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2138                 if (err)
2139                         break;
2140                 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
2141                 __mlx4_mpt_release(dev, index);
2142                 break;
2143         case RES_OP_MAP_ICM:
2144                         index = get_param_l(&in_param);
2145                         id = index & mpt_mask(dev);
2146                         err = mr_res_start_move_to(dev, slave, id,
2147                                                    RES_MPT_RESERVED, &mpt);
2148                         if (err)
2149                                 return err;
2150
2151                         __mlx4_mpt_free_icm(dev, mpt->key);
2152                         res_end_move(dev, slave, RES_MPT, id);
2153                         return err;
2154                 break;
2155         default:
2156                 err = -EINVAL;
2157                 break;
2158         }
2159         return err;
2160 }
2161
2162 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2163                        u64 in_param, u64 *out_param)
2164 {
2165         int cqn;
2166         int err;
2167
2168         switch (op) {
2169         case RES_OP_RESERVE_AND_MAP:
2170                 cqn = get_param_l(&in_param);
2171                 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2172                 if (err)
2173                         break;
2174
2175                 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
2176                 __mlx4_cq_free_icm(dev, cqn);
2177                 break;
2178
2179         default:
2180                 err = -EINVAL;
2181                 break;
2182         }
2183
2184         return err;
2185 }
2186
2187 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2188                         u64 in_param, u64 *out_param)
2189 {
2190         int srqn;
2191         int err;
2192
2193         switch (op) {
2194         case RES_OP_RESERVE_AND_MAP:
2195                 srqn = get_param_l(&in_param);
2196                 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2197                 if (err)
2198                         break;
2199
2200                 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
2201                 __mlx4_srq_free_icm(dev, srqn);
2202                 break;
2203
2204         default:
2205                 err = -EINVAL;
2206                 break;
2207         }
2208
2209         return err;
2210 }
2211
2212 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2213                             u64 in_param, u64 *out_param, int in_port)
2214 {
2215         int port;
2216         int err = 0;
2217
2218         switch (op) {
2219         case RES_OP_RESERVE_AND_MAP:
2220                 port = !in_port ? get_param_l(out_param) : in_port;
2221                 port = mlx4_slave_convert_port(
2222                                 dev, slave, port);
2223
2224                 if (port < 0)
2225                         return -EINVAL;
2226                 mac_del_from_slave(dev, slave, in_param, port);
2227                 __mlx4_unregister_mac(dev, port, in_param);
2228                 break;
2229         default:
2230                 err = -EINVAL;
2231                 break;
2232         }
2233
2234         return err;
2235
2236 }
2237
2238 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2239                             u64 in_param, u64 *out_param, int port)
2240 {
2241         struct mlx4_priv *priv = mlx4_priv(dev);
2242         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2243         int err = 0;
2244
2245         port = mlx4_slave_convert_port(
2246                         dev, slave, port);
2247
2248         if (port < 0)
2249                 return -EINVAL;
2250         switch (op) {
2251         case RES_OP_RESERVE_AND_MAP:
2252                 if (slave_state[slave].old_vlan_api)
2253                         return 0;
2254                 if (!port)
2255                         return -EINVAL;
2256                 vlan_del_from_slave(dev, slave, in_param, port);
2257                 __mlx4_unregister_vlan(dev, port, in_param);
2258                 break;
2259         default:
2260                 err = -EINVAL;
2261                 break;
2262         }
2263
2264         return err;
2265 }
2266
2267 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2268                             u64 in_param, u64 *out_param)
2269 {
2270         int index;
2271         int err;
2272
2273         if (op != RES_OP_RESERVE)
2274                 return -EINVAL;
2275
2276         index = get_param_l(&in_param);
2277         err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2278         if (err)
2279                 return err;
2280
2281         __mlx4_counter_free(dev, index);
2282         mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2283
2284         return err;
2285 }
2286
2287 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2288                           u64 in_param, u64 *out_param)
2289 {
2290         int xrcdn;
2291         int err;
2292
2293         if (op != RES_OP_RESERVE)
2294                 return -EINVAL;
2295
2296         xrcdn = get_param_l(&in_param);
2297         err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2298         if (err)
2299                 return err;
2300
2301         __mlx4_xrcd_free(dev, xrcdn);
2302
2303         return err;
2304 }
2305
2306 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2307                           struct mlx4_vhcr *vhcr,
2308                           struct mlx4_cmd_mailbox *inbox,
2309                           struct mlx4_cmd_mailbox *outbox,
2310                           struct mlx4_cmd_info *cmd)
2311 {
2312         int err = -EINVAL;
2313         int alop = vhcr->op_modifier;
2314
2315         switch (vhcr->in_modifier & 0xFF) {
2316         case RES_QP:
2317                 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2318                                   vhcr->in_param);
2319                 break;
2320
2321         case RES_MTT:
2322                 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2323                                    vhcr->in_param, &vhcr->out_param);
2324                 break;
2325
2326         case RES_MPT:
2327                 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2328                                    vhcr->in_param);
2329                 break;
2330
2331         case RES_CQ:
2332                 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2333                                   vhcr->in_param, &vhcr->out_param);
2334                 break;
2335
2336         case RES_SRQ:
2337                 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2338                                    vhcr->in_param, &vhcr->out_param);
2339                 break;
2340
2341         case RES_MAC:
2342                 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
2343                                    vhcr->in_param, &vhcr->out_param,
2344                                    (vhcr->in_modifier >> 8) & 0xFF);
2345                 break;
2346
2347         case RES_VLAN:
2348                 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
2349                                     vhcr->in_param, &vhcr->out_param,
2350                                     (vhcr->in_modifier >> 8) & 0xFF);
2351                 break;
2352
2353         case RES_COUNTER:
2354                 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2355                                        vhcr->in_param, &vhcr->out_param);
2356                 break;
2357
2358         case RES_XRCD:
2359                 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2360                                      vhcr->in_param, &vhcr->out_param);
2361
2362         default:
2363                 break;
2364         }
2365         return err;
2366 }
2367
2368 /* ugly but other choices are uglier */
2369 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2370 {
2371         return (be32_to_cpu(mpt->flags) >> 9) & 1;
2372 }
2373
2374 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
2375 {
2376         return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
2377 }
2378
2379 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2380 {
2381         return be32_to_cpu(mpt->mtt_sz);
2382 }
2383
2384 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2385 {
2386         return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2387 }
2388
2389 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2390 {
2391         return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2392 }
2393
2394 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2395 {
2396         return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2397 }
2398
2399 static int mr_is_region(struct mlx4_mpt_entry *mpt)
2400 {
2401         return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2402 }
2403
2404 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
2405 {
2406         return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2407 }
2408
2409 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
2410 {
2411         return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2412 }
2413
2414 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2415 {
2416         int page_shift = (qpc->log_page_size & 0x3f) + 12;
2417         int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2418         int log_sq_sride = qpc->sq_size_stride & 7;
2419         int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2420         int log_rq_stride = qpc->rq_size_stride & 7;
2421         int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2422         int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
2423         u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2424         int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
2425         int sq_size;
2426         int rq_size;
2427         int total_pages;
2428         int total_mem;
2429         int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2430
2431         sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2432         rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2433         total_mem = sq_size + rq_size;
2434         total_pages =
2435                 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2436                                    page_shift);
2437
2438         return total_pages;
2439 }
2440
2441 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2442                            int size, struct res_mtt *mtt)
2443 {
2444         int res_start = mtt->com.res_id;
2445         int res_size = (1 << mtt->order);
2446
2447         if (start < res_start || start + size > res_start + res_size)
2448                 return -EPERM;
2449         return 0;
2450 }
2451
2452 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2453                            struct mlx4_vhcr *vhcr,
2454                            struct mlx4_cmd_mailbox *inbox,
2455                            struct mlx4_cmd_mailbox *outbox,
2456                            struct mlx4_cmd_info *cmd)
2457 {
2458         int err;
2459         int index = vhcr->in_modifier;
2460         struct res_mtt *mtt;
2461         struct res_mpt *mpt;
2462         int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
2463         int phys;
2464         int id;
2465         u32 pd;
2466         int pd_slave;
2467
2468         id = index & mpt_mask(dev);
2469         err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2470         if (err)
2471                 return err;
2472
2473         /* Disable memory windows for VFs. */
2474         if (!mr_is_region(inbox->buf)) {
2475                 err = -EPERM;
2476                 goto ex_abort;
2477         }
2478
2479         /* Make sure that the PD bits related to the slave id are zeros. */
2480         pd = mr_get_pd(inbox->buf);
2481         pd_slave = (pd >> 17) & 0x7f;
2482         if (pd_slave != 0 && pd_slave != slave) {
2483                 err = -EPERM;
2484                 goto ex_abort;
2485         }
2486
2487         if (mr_is_fmr(inbox->buf)) {
2488                 /* FMR and Bind Enable are forbidden in slave devices. */
2489                 if (mr_is_bind_enabled(inbox->buf)) {
2490                         err = -EPERM;
2491                         goto ex_abort;
2492                 }
2493                 /* FMR and Memory Windows are also forbidden. */
2494                 if (!mr_is_region(inbox->buf)) {
2495                         err = -EPERM;
2496                         goto ex_abort;
2497                 }
2498         }
2499
2500         phys = mr_phys_mpt(inbox->buf);
2501         if (!phys) {
2502                 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2503                 if (err)
2504                         goto ex_abort;
2505
2506                 err = check_mtt_range(dev, slave, mtt_base,
2507                                       mr_get_mtt_size(inbox->buf), mtt);
2508                 if (err)
2509                         goto ex_put;
2510
2511                 mpt->mtt = mtt;
2512         }
2513
2514         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2515         if (err)
2516                 goto ex_put;
2517
2518         if (!phys) {
2519                 atomic_inc(&mtt->ref_count);
2520                 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2521         }
2522
2523         res_end_move(dev, slave, RES_MPT, id);
2524         return 0;
2525
2526 ex_put:
2527         if (!phys)
2528                 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2529 ex_abort:
2530         res_abort_move(dev, slave, RES_MPT, id);
2531
2532         return err;
2533 }
2534
2535 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2536                            struct mlx4_vhcr *vhcr,
2537                            struct mlx4_cmd_mailbox *inbox,
2538                            struct mlx4_cmd_mailbox *outbox,
2539                            struct mlx4_cmd_info *cmd)
2540 {
2541         int err;
2542         int index = vhcr->in_modifier;
2543         struct res_mpt *mpt;
2544         int id;
2545
2546         id = index & mpt_mask(dev);
2547         err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2548         if (err)
2549                 return err;
2550
2551         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2552         if (err)
2553                 goto ex_abort;
2554
2555         if (mpt->mtt)
2556                 atomic_dec(&mpt->mtt->ref_count);
2557
2558         res_end_move(dev, slave, RES_MPT, id);
2559         return 0;
2560
2561 ex_abort:
2562         res_abort_move(dev, slave, RES_MPT, id);
2563
2564         return err;
2565 }
2566
2567 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2568                            struct mlx4_vhcr *vhcr,
2569                            struct mlx4_cmd_mailbox *inbox,
2570                            struct mlx4_cmd_mailbox *outbox,
2571                            struct mlx4_cmd_info *cmd)
2572 {
2573         int err;
2574         int index = vhcr->in_modifier;
2575         struct res_mpt *mpt;
2576         int id;
2577
2578         id = index & mpt_mask(dev);
2579         err = get_res(dev, slave, id, RES_MPT, &mpt);
2580         if (err)
2581                 return err;
2582
2583         if (mpt->com.from_state != RES_MPT_HW) {
2584                 err = -EBUSY;
2585                 goto out;
2586         }
2587
2588         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2589
2590 out:
2591         put_res(dev, slave, id, RES_MPT);
2592         return err;
2593 }
2594
2595 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2596 {
2597         return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2598 }
2599
2600 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2601 {
2602         return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2603 }
2604
2605 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2606 {
2607         return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2608 }
2609
2610 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2611                                   struct mlx4_qp_context *context)
2612 {
2613         u32 qpn = vhcr->in_modifier & 0xffffff;
2614         u32 qkey = 0;
2615
2616         if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2617                 return;
2618
2619         /* adjust qkey in qp context */
2620         context->qkey = cpu_to_be32(qkey);
2621 }
2622
2623 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2624                              struct mlx4_vhcr *vhcr,
2625                              struct mlx4_cmd_mailbox *inbox,
2626                              struct mlx4_cmd_mailbox *outbox,
2627                              struct mlx4_cmd_info *cmd)
2628 {
2629         int err;
2630         int qpn = vhcr->in_modifier & 0x7fffff;
2631         struct res_mtt *mtt;
2632         struct res_qp *qp;
2633         struct mlx4_qp_context *qpc = inbox->buf + 8;
2634         int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2635         int mtt_size = qp_get_mtt_size(qpc);
2636         struct res_cq *rcq;
2637         struct res_cq *scq;
2638         int rcqn = qp_get_rcqn(qpc);
2639         int scqn = qp_get_scqn(qpc);
2640         u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2641         int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2642         struct res_srq *srq;
2643         int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2644
2645         err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2646         if (err)
2647                 return err;
2648         qp->local_qpn = local_qpn;
2649         qp->sched_queue = 0;
2650         qp->param3 = 0;
2651         qp->vlan_control = 0;
2652         qp->fvl_rx = 0;
2653         qp->pri_path_fl = 0;
2654         qp->vlan_index = 0;
2655         qp->feup = 0;
2656         qp->qpc_flags = be32_to_cpu(qpc->flags);
2657
2658         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2659         if (err)
2660                 goto ex_abort;
2661
2662         err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2663         if (err)
2664                 goto ex_put_mtt;
2665
2666         err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2667         if (err)
2668                 goto ex_put_mtt;
2669
2670         if (scqn != rcqn) {
2671                 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2672                 if (err)
2673                         goto ex_put_rcq;
2674         } else
2675                 scq = rcq;
2676
2677         if (use_srq) {
2678                 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2679                 if (err)
2680                         goto ex_put_scq;
2681         }
2682
2683         adjust_proxy_tun_qkey(dev, vhcr, qpc);
2684         update_pkey_index(dev, slave, inbox);
2685         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2686         if (err)
2687                 goto ex_put_srq;
2688         atomic_inc(&mtt->ref_count);
2689         qp->mtt = mtt;
2690         atomic_inc(&rcq->ref_count);
2691         qp->rcq = rcq;
2692         atomic_inc(&scq->ref_count);
2693         qp->scq = scq;
2694
2695         if (scqn != rcqn)
2696                 put_res(dev, slave, scqn, RES_CQ);
2697
2698         if (use_srq) {
2699                 atomic_inc(&srq->ref_count);
2700                 put_res(dev, slave, srqn, RES_SRQ);
2701                 qp->srq = srq;
2702         }
2703         put_res(dev, slave, rcqn, RES_CQ);
2704         put_res(dev, slave, mtt_base, RES_MTT);
2705         res_end_move(dev, slave, RES_QP, qpn);
2706
2707         return 0;
2708
2709 ex_put_srq:
2710         if (use_srq)
2711                 put_res(dev, slave, srqn, RES_SRQ);
2712 ex_put_scq:
2713         if (scqn != rcqn)
2714                 put_res(dev, slave, scqn, RES_CQ);
2715 ex_put_rcq:
2716         put_res(dev, slave, rcqn, RES_CQ);
2717 ex_put_mtt:
2718         put_res(dev, slave, mtt_base, RES_MTT);
2719 ex_abort:
2720         res_abort_move(dev, slave, RES_QP, qpn);
2721
2722         return err;
2723 }
2724
2725 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
2726 {
2727         return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2728 }
2729
2730 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2731 {
2732         int log_eq_size = eqc->log_eq_size & 0x1f;
2733         int page_shift = (eqc->log_page_size & 0x3f) + 12;
2734
2735         if (log_eq_size + 5 < page_shift)
2736                 return 1;
2737
2738         return 1 << (log_eq_size + 5 - page_shift);
2739 }
2740
2741 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
2742 {
2743         return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
2744 }
2745
2746 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
2747 {
2748         int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
2749         int page_shift = (cqc->log_page_size & 0x3f) + 12;
2750
2751         if (log_cq_size + 5 < page_shift)
2752                 return 1;
2753
2754         return 1 << (log_cq_size + 5 - page_shift);
2755 }
2756
2757 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2758                           struct mlx4_vhcr *vhcr,
2759                           struct mlx4_cmd_mailbox *inbox,
2760                           struct mlx4_cmd_mailbox *outbox,
2761                           struct mlx4_cmd_info *cmd)
2762 {
2763         int err;
2764         int eqn = vhcr->in_modifier;
2765         int res_id = (slave << 8) | eqn;
2766         struct mlx4_eq_context *eqc = inbox->buf;
2767         int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
2768         int mtt_size = eq_get_mtt_size(eqc);
2769         struct res_eq *eq;
2770         struct res_mtt *mtt;
2771
2772         err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2773         if (err)
2774                 return err;
2775         err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
2776         if (err)
2777                 goto out_add;
2778
2779         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2780         if (err)
2781                 goto out_move;
2782
2783         err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2784         if (err)
2785                 goto out_put;
2786
2787         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2788         if (err)
2789                 goto out_put;
2790
2791         atomic_inc(&mtt->ref_count);
2792         eq->mtt = mtt;
2793         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2794         res_end_move(dev, slave, RES_EQ, res_id);
2795         return 0;
2796
2797 out_put:
2798         put_res(dev, slave, mtt->com.res_id, RES_MTT);
2799 out_move:
2800         res_abort_move(dev, slave, RES_EQ, res_id);
2801 out_add:
2802         rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2803         return err;
2804 }
2805
2806 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
2807                               int len, struct res_mtt **res)
2808 {
2809         struct mlx4_priv *priv = mlx4_priv(dev);
2810         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2811         struct res_mtt *mtt;
2812         int err = -EINVAL;
2813
2814         spin_lock_irq(mlx4_tlock(dev));
2815         list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
2816                             com.list) {
2817                 if (!check_mtt_range(dev, slave, start, len, mtt)) {
2818                         *res = mtt;
2819                         mtt->com.from_state = mtt->com.state;
2820                         mtt->com.state = RES_MTT_BUSY;
2821                         err = 0;
2822                         break;
2823                 }
2824         }
2825         spin_unlock_irq(mlx4_tlock(dev));
2826
2827         return err;
2828 }
2829
2830 static int verify_qp_parameters(struct mlx4_dev *dev,
2831                                 struct mlx4_cmd_mailbox *inbox,
2832                                 enum qp_transition transition, u8 slave)
2833 {
2834         u32                     qp_type;
2835         struct mlx4_qp_context  *qp_ctx;
2836         enum mlx4_qp_optpar     optpar;
2837         int port;
2838         int num_gids;
2839
2840         qp_ctx  = inbox->buf + 8;
2841         qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
2842         optpar  = be32_to_cpu(*(__be32 *) inbox->buf);
2843
2844         switch (qp_type) {
2845         case MLX4_QP_ST_RC:
2846         case MLX4_QP_ST_XRC:
2847         case MLX4_QP_ST_UC:
2848                 switch (transition) {
2849                 case QP_TRANS_INIT2RTR:
2850                 case QP_TRANS_RTR2RTS:
2851                 case QP_TRANS_RTS2RTS:
2852                 case QP_TRANS_SQD2SQD:
2853                 case QP_TRANS_SQD2RTS:
2854                         if (slave != mlx4_master_func_num(dev))
2855                                 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
2856                                         port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
2857                                         if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
2858                                                 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
2859                                         else
2860                                                 num_gids = 1;
2861                                         if (qp_ctx->pri_path.mgid_index >= num_gids)
2862                                                 return -EINVAL;
2863                                 }
2864                                 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
2865                                         port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
2866                                         if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
2867                                                 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
2868                                         else
2869                                                 num_gids = 1;
2870                                         if (qp_ctx->alt_path.mgid_index >= num_gids)
2871                                                 return -EINVAL;
2872                                 }
2873                         break;
2874                 default:
2875                         break;
2876                 }
2877
2878                 break;
2879         default:
2880                 break;
2881         }
2882
2883         return 0;
2884 }
2885
2886 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
2887                            struct mlx4_vhcr *vhcr,
2888                            struct mlx4_cmd_mailbox *inbox,
2889                            struct mlx4_cmd_mailbox *outbox,
2890                            struct mlx4_cmd_info *cmd)
2891 {
2892         struct mlx4_mtt mtt;
2893         __be64 *page_list = inbox->buf;
2894         u64 *pg_list = (u64 *)page_list;
2895         int i;
2896         struct res_mtt *rmtt = NULL;
2897         int start = be64_to_cpu(page_list[0]);
2898         int npages = vhcr->in_modifier;
2899         int err;
2900
2901         err = get_containing_mtt(dev, slave, start, npages, &rmtt);
2902         if (err)
2903                 return err;
2904
2905         /* Call the SW implementation of write_mtt:
2906          * - Prepare a dummy mtt struct
2907          * - Translate inbox contents to simple addresses in host endianess */
2908         mtt.offset = 0;  /* TBD this is broken but I don't handle it since
2909                             we don't really use it */
2910         mtt.order = 0;
2911         mtt.page_shift = 0;
2912         for (i = 0; i < npages; ++i)
2913                 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
2914
2915         err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
2916                                ((u64 *)page_list + 2));
2917
2918         if (rmtt)
2919                 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
2920
2921         return err;
2922 }
2923
2924 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2925                           struct mlx4_vhcr *vhcr,
2926                           struct mlx4_cmd_mailbox *inbox,
2927                           struct mlx4_cmd_mailbox *outbox,
2928                           struct mlx4_cmd_info *cmd)
2929 {
2930         int eqn = vhcr->in_modifier;
2931         int res_id = eqn | (slave << 8);
2932         struct res_eq *eq;
2933         int err;
2934
2935         err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
2936         if (err)
2937                 return err;
2938
2939         err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
2940         if (err)
2941                 goto ex_abort;
2942
2943         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2944         if (err)
2945                 goto ex_put;
2946
2947         atomic_dec(&eq->mtt->ref_count);
2948         put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
2949         res_end_move(dev, slave, RES_EQ, res_id);
2950         rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2951
2952         return 0;
2953
2954 ex_put:
2955         put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
2956 ex_abort:
2957         res_abort_move(dev, slave, RES_EQ, res_id);
2958
2959         return err;
2960 }
2961
2962 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
2963 {
2964         struct mlx4_priv *priv = mlx4_priv(dev);
2965         struct mlx4_slave_event_eq_info *event_eq;
2966         struct mlx4_cmd_mailbox *mailbox;
2967         u32 in_modifier = 0;
2968         int err;
2969         int res_id;
2970         struct res_eq *req;
2971
2972         if (!priv->mfunc.master.slave_state)
2973                 return -EINVAL;
2974
2975         event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
2976
2977         /* Create the event only if the slave is registered */
2978         if (event_eq->eqn < 0)
2979                 return 0;
2980
2981         mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
2982         res_id = (slave << 8) | event_eq->eqn;
2983         err = get_res(dev, slave, res_id, RES_EQ, &req);
2984         if (err)
2985                 goto unlock;
2986
2987         if (req->com.from_state != RES_EQ_HW) {
2988                 err = -EINVAL;
2989                 goto put;
2990         }
2991
2992         mailbox = mlx4_alloc_cmd_mailbox(dev);
2993         if (IS_ERR(mailbox)) {
2994                 err = PTR_ERR(mailbox);
2995                 goto put;
2996         }
2997
2998         if (eqe->type == MLX4_EVENT_TYPE_CMD) {
2999                 ++event_eq->token;
3000                 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3001         }
3002
3003         memcpy(mailbox->buf, (u8 *) eqe, 28);
3004
3005         in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
3006
3007         err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3008                        MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3009                        MLX4_CMD_NATIVE);
3010
3011         put_res(dev, slave, res_id, RES_EQ);
3012         mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3013         mlx4_free_cmd_mailbox(dev, mailbox);
3014         return err;
3015
3016 put:
3017         put_res(dev, slave, res_id, RES_EQ);
3018
3019 unlock:
3020         mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3021         return err;
3022 }
3023
3024 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3025                           struct mlx4_vhcr *vhcr,
3026                           struct mlx4_cmd_mailbox *inbox,
3027                           struct mlx4_cmd_mailbox *outbox,
3028                           struct mlx4_cmd_info *cmd)
3029 {
3030         int eqn = vhcr->in_modifier;
3031         int res_id = eqn | (slave << 8);
3032         struct res_eq *eq;
3033         int err;
3034
3035         err = get_res(dev, slave, res_id, RES_EQ, &eq);
3036         if (err)
3037                 return err;
3038
3039         if (eq->com.from_state != RES_EQ_HW) {
3040                 err = -EINVAL;
3041                 goto ex_put;
3042         }
3043
3044         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3045
3046 ex_put:
3047         put_res(dev, slave, res_id, RES_EQ);
3048         return err;
3049 }
3050
3051 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3052                           struct mlx4_vhcr *vhcr,
3053                           struct mlx4_cmd_mailbox *inbox,
3054                           struct mlx4_cmd_mailbox *outbox,
3055                           struct mlx4_cmd_info *cmd)
3056 {
3057         int err;
3058         int cqn = vhcr->in_modifier;
3059         struct mlx4_cq_context *cqc = inbox->buf;
3060         int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3061         struct res_cq *cq;
3062         struct res_mtt *mtt;
3063
3064         err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3065         if (err)
3066                 return err;
3067         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3068         if (err)
3069                 goto out_move;
3070         err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3071         if (err)
3072                 goto out_put;
3073         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3074         if (err)
3075                 goto out_put;
3076         atomic_inc(&mtt->ref_count);
3077         cq->mtt = mtt;
3078         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3079         res_end_move(dev, slave, RES_CQ, cqn);
3080         return 0;
3081
3082 out_put:
3083         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3084 out_move:
3085         res_abort_move(dev, slave, RES_CQ, cqn);
3086         return err;
3087 }
3088
3089 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3090                           struct mlx4_vhcr *vhcr,
3091                           struct mlx4_cmd_mailbox *inbox,
3092                           struct mlx4_cmd_mailbox *outbox,
3093                           struct mlx4_cmd_info *cmd)
3094 {
3095         int err;
3096         int cqn = vhcr->in_modifier;
3097         struct res_cq *cq;
3098
3099         err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3100         if (err)
3101                 return err;
3102         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3103         if (err)
3104                 goto out_move;
3105         atomic_dec(&cq->mtt->ref_count);
3106         res_end_move(dev, slave, RES_CQ, cqn);
3107         return 0;
3108
3109 out_move:
3110         res_abort_move(dev, slave, RES_CQ, cqn);
3111         return err;
3112 }
3113
3114 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3115                           struct mlx4_vhcr *vhcr,
3116                           struct mlx4_cmd_mailbox *inbox,
3117                           struct mlx4_cmd_mailbox *outbox,
3118                           struct mlx4_cmd_info *cmd)
3119 {
3120         int cqn = vhcr->in_modifier;
3121         struct res_cq *cq;
3122         int err;
3123
3124         err = get_res(dev, slave, cqn, RES_CQ, &cq);
3125         if (err)
3126                 return err;
3127
3128         if (cq->com.from_state != RES_CQ_HW)
3129                 goto ex_put;
3130
3131         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3132 ex_put:
3133         put_res(dev, slave, cqn, RES_CQ);
3134
3135         return err;
3136 }
3137
3138 static int handle_resize(struct mlx4_dev *dev, int slave,
3139                          struct mlx4_vhcr *vhcr,
3140                          struct mlx4_cmd_mailbox *inbox,
3141                          struct mlx4_cmd_mailbox *outbox,
3142                          struct mlx4_cmd_info *cmd,
3143                          struct res_cq *cq)
3144 {
3145         int err;
3146         struct res_mtt *orig_mtt;
3147         struct res_mtt *mtt;
3148         struct mlx4_cq_context *cqc = inbox->buf;
3149         int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3150
3151         err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3152         if (err)
3153                 return err;
3154
3155         if (orig_mtt != cq->mtt) {
3156                 err = -EINVAL;
3157                 goto ex_put;
3158         }
3159
3160         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3161         if (err)
3162                 goto ex_put;
3163
3164         err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3165         if (err)
3166                 goto ex_put1;
3167         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3168         if (err)
3169                 goto ex_put1;
3170         atomic_dec(&orig_mtt->ref_count);
3171         put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3172         atomic_inc(&mtt->ref_count);
3173         cq->mtt = mtt;
3174         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3175         return 0;
3176
3177 ex_put1:
3178         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3179 ex_put:
3180         put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3181
3182         return err;
3183
3184 }
3185
3186 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3187                            struct mlx4_vhcr *vhcr,
3188                            struct mlx4_cmd_mailbox *inbox,
3189                            struct mlx4_cmd_mailbox *outbox,
3190                            struct mlx4_cmd_info *cmd)
3191 {
3192         int cqn = vhcr->in_modifier;
3193         struct res_cq *cq;
3194         int err;
3195
3196         err = get_res(dev, slave, cqn, RES_CQ, &cq);
3197         if (err)
3198                 return err;
3199
3200         if (cq->com.from_state != RES_CQ_HW)
3201                 goto ex_put;
3202
3203         if (vhcr->op_modifier == 0) {
3204                 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
3205                 goto ex_put;
3206         }
3207
3208         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3209 ex_put:
3210         put_res(dev, slave, cqn, RES_CQ);
3211
3212         return err;
3213 }
3214
3215 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3216 {
3217         int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3218         int log_rq_stride = srqc->logstride & 7;
3219         int page_shift = (srqc->log_page_size & 0x3f) + 12;
3220
3221         if (log_srq_size + log_rq_stride + 4 < page_shift)
3222                 return 1;
3223
3224         return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3225 }
3226
3227 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3228                            struct mlx4_vhcr *vhcr,
3229                            struct mlx4_cmd_mailbox *inbox,
3230                            struct mlx4_cmd_mailbox *outbox,
3231                            struct mlx4_cmd_info *cmd)
3232 {
3233         int err;
3234         int srqn = vhcr->in_modifier;
3235         struct res_mtt *mtt;
3236         struct res_srq *srq;
3237         struct mlx4_srq_context *srqc = inbox->buf;
3238         int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
3239
3240         if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3241                 return -EINVAL;
3242
3243         err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3244         if (err)
3245                 return err;
3246         err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3247         if (err)
3248                 goto ex_abort;
3249         err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3250                               mtt);
3251         if (err)
3252                 goto ex_put_mtt;
3253
3254         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3255         if (err)
3256                 goto ex_put_mtt;
3257
3258         atomic_inc(&mtt->ref_count);
3259         srq->mtt = mtt;
3260         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3261         res_end_move(dev, slave, RES_SRQ, srqn);
3262         return 0;
3263
3264 ex_put_mtt:
3265         put_res(dev, slave, mtt->com.res_id, RES_MTT);
3266 ex_abort:
3267         res_abort_move(dev, slave, RES_SRQ, srqn);
3268
3269         return err;
3270 }
3271
3272 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3273                            struct mlx4_vhcr *vhcr,
3274                            struct mlx4_cmd_mailbox *inbox,
3275                            struct mlx4_cmd_mailbox *outbox,
3276                            struct mlx4_cmd_info *cmd)
3277 {
3278         int err;
3279         int srqn = vhcr->in_modifier;
3280         struct res_srq *srq;
3281
3282         err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3283         if (err)
3284                 return err;
3285         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3286         if (err)
3287                 goto ex_abort;
3288         atomic_dec(&srq->mtt->ref_count);
3289         if (srq->cq)
3290                 atomic_dec(&srq->cq->ref_count);
3291         res_end_move(dev, slave, RES_SRQ, srqn);
3292
3293         return 0;
3294
3295 ex_abort:
3296         res_abort_move(dev, slave, RES_SRQ, srqn);
3297
3298         return err;
3299 }
3300
3301 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3302                            struct mlx4_vhcr *vhcr,
3303                            struct mlx4_cmd_mailbox *inbox,
3304                            struct mlx4_cmd_mailbox *outbox,
3305                            struct mlx4_cmd_info *cmd)
3306 {
3307         int err;
3308         int srqn = vhcr->in_modifier;
3309         struct res_srq *srq;
3310
3311         err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3312         if (err)
3313                 return err;
3314         if (srq->com.from_state != RES_SRQ_HW) {
3315                 err = -EBUSY;
3316                 goto out;
3317         }
3318         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3319 out:
3320         put_res(dev, slave, srqn, RES_SRQ);
3321         return err;
3322 }
3323
3324 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3325                          struct mlx4_vhcr *vhcr,
3326                          struct mlx4_cmd_mailbox *inbox,
3327                          struct mlx4_cmd_mailbox *outbox,
3328                          struct mlx4_cmd_info *cmd)
3329 {
3330         int err;
3331         int srqn = vhcr->in_modifier;
3332         struct res_srq *srq;
3333
3334         err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3335         if (err)
3336                 return err;
3337
3338         if (srq->com.from_state != RES_SRQ_HW) {
3339                 err = -EBUSY;
3340                 goto out;
3341         }
3342
3343         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3344 out:
3345         put_res(dev, slave, srqn, RES_SRQ);
3346         return err;
3347 }
3348
3349 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3350                         struct mlx4_vhcr *vhcr,
3351                         struct mlx4_cmd_mailbox *inbox,
3352                         struct mlx4_cmd_mailbox *outbox,
3353                         struct mlx4_cmd_info *cmd)
3354 {
3355         int err;
3356         int qpn = vhcr->in_modifier & 0x7fffff;
3357         struct res_qp *qp;
3358
3359         err = get_res(dev, slave, qpn, RES_QP, &qp);
3360         if (err)
3361                 return err;
3362         if (qp->com.from_state != RES_QP_HW) {
3363                 err = -EBUSY;
3364                 goto out;
3365         }
3366
3367         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3368 out:
3369         put_res(dev, slave, qpn, RES_QP);
3370         return err;
3371 }
3372
3373 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3374                               struct mlx4_vhcr *vhcr,
3375                               struct mlx4_cmd_mailbox *inbox,
3376                               struct mlx4_cmd_mailbox *outbox,
3377                               struct mlx4_cmd_info *cmd)
3378 {
3379         struct mlx4_qp_context *context = inbox->buf + 8;
3380         adjust_proxy_tun_qkey(dev, vhcr, context);
3381         update_pkey_index(dev, slave, inbox);
3382         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3383 }
3384
3385 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3386                                   struct mlx4_qp_context *qpc,
3387                                   struct mlx4_cmd_mailbox *inbox)
3388 {
3389         enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3390         u8 pri_sched_queue;
3391         int port = mlx4_slave_convert_port(
3392                    dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3393
3394         if (port < 0)
3395                 return -EINVAL;
3396
3397         pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3398                           ((port & 1) << 6);
3399
3400         if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH ||
3401             mlx4_is_eth(dev, port + 1)) {
3402                 qpc->pri_path.sched_queue = pri_sched_queue;
3403         }
3404
3405         if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3406                 port = mlx4_slave_convert_port(
3407                                 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3408                                 + 1) - 1;
3409                 if (port < 0)
3410                         return -EINVAL;
3411                 qpc->alt_path.sched_queue =
3412                         (qpc->alt_path.sched_queue & ~(1 << 6)) |
3413                         (port & 1) << 6;
3414         }
3415         return 0;
3416 }
3417
3418 static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3419                                 struct mlx4_qp_context *qpc,
3420                                 struct mlx4_cmd_mailbox *inbox)
3421 {
3422         u64 mac;
3423         int port;
3424         u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3425         u8 sched = *(u8 *)(inbox->buf + 64);
3426         u8 smac_ix;
3427
3428         port = (sched >> 6 & 1) + 1;
3429         if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3430                 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3431                 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3432                         return -ENOENT;
3433         }
3434         return 0;
3435 }
3436
3437 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3438                              struct mlx4_vhcr *vhcr,
3439                              struct mlx4_cmd_mailbox *inbox,
3440                              struct mlx4_cmd_mailbox *outbox,
3441                              struct mlx4_cmd_info *cmd)
3442 {
3443         int err;
3444         struct mlx4_qp_context *qpc = inbox->buf + 8;
3445         int qpn = vhcr->in_modifier & 0x7fffff;
3446         struct res_qp *qp;
3447         u8 orig_sched_queue;
3448         __be32  orig_param3 = qpc->param3;
3449         u8 orig_vlan_control = qpc->pri_path.vlan_control;
3450         u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3451         u8 orig_pri_path_fl = qpc->pri_path.fl;
3452         u8 orig_vlan_index = qpc->pri_path.vlan_index;
3453         u8 orig_feup = qpc->pri_path.feup;
3454
3455         err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3456         if (err)
3457                 return err;
3458         err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
3459         if (err)
3460                 return err;
3461
3462         if (roce_verify_mac(dev, slave, qpc, inbox))
3463                 return -EINVAL;
3464
3465         update_pkey_index(dev, slave, inbox);
3466         update_gid(dev, inbox, (u8)slave);
3467         adjust_proxy_tun_qkey(dev, vhcr, qpc);
3468         orig_sched_queue = qpc->pri_path.sched_queue;
3469         err = update_vport_qp_param(dev, inbox, slave, qpn);
3470         if (err)
3471                 return err;
3472
3473         err = get_res(dev, slave, qpn, RES_QP, &qp);
3474         if (err)
3475                 return err;
3476         if (qp->com.from_state != RES_QP_HW) {
3477                 err = -EBUSY;
3478                 goto out;
3479         }
3480
3481         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3482 out:
3483         /* if no error, save sched queue value passed in by VF. This is
3484          * essentially the QOS value provided by the VF. This will be useful
3485          * if we allow dynamic changes from VST back to VGT
3486          */
3487         if (!err) {
3488                 qp->sched_queue = orig_sched_queue;
3489                 qp->param3      = orig_param3;
3490                 qp->vlan_control = orig_vlan_control;
3491                 qp->fvl_rx      =  orig_fvl_rx;
3492                 qp->pri_path_fl = orig_pri_path_fl;
3493                 qp->vlan_index  = orig_vlan_index;
3494                 qp->feup        = orig_feup;
3495         }
3496         put_res(dev, slave, qpn, RES_QP);
3497         return err;
3498 }
3499
3500 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3501                             struct mlx4_vhcr *vhcr,
3502                             struct mlx4_cmd_mailbox *inbox,
3503                             struct mlx4_cmd_mailbox *outbox,
3504                             struct mlx4_cmd_info *cmd)
3505 {
3506         int err;
3507         struct mlx4_qp_context *context = inbox->buf + 8;
3508
3509         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3510         if (err)
3511                 return err;
3512         err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
3513         if (err)
3514                 return err;
3515
3516         update_pkey_index(dev, slave, inbox);
3517         update_gid(dev, inbox, (u8)slave);
3518         adjust_proxy_tun_qkey(dev, vhcr, context);
3519         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3520 }
3521
3522 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3523                             struct mlx4_vhcr *vhcr,
3524                             struct mlx4_cmd_mailbox *inbox,
3525                             struct mlx4_cmd_mailbox *outbox,
3526                             struct mlx4_cmd_info *cmd)
3527 {
3528         int err;
3529         struct mlx4_qp_context *context = inbox->buf + 8;
3530
3531         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3532         if (err)
3533                 return err;
3534         err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
3535         if (err)
3536                 return err;
3537
3538         update_pkey_index(dev, slave, inbox);
3539         update_gid(dev, inbox, (u8)slave);
3540         adjust_proxy_tun_qkey(dev, vhcr, context);
3541         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3542 }
3543
3544
3545 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3546                               struct mlx4_vhcr *vhcr,
3547                               struct mlx4_cmd_mailbox *inbox,
3548                               struct mlx4_cmd_mailbox *outbox,
3549                               struct mlx4_cmd_info *cmd)
3550 {
3551         struct mlx4_qp_context *context = inbox->buf + 8;
3552         int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3553         if (err)
3554                 return err;
3555         adjust_proxy_tun_qkey(dev, vhcr, context);
3556         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3557 }
3558
3559 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3560                             struct mlx4_vhcr *vhcr,
3561                             struct mlx4_cmd_mailbox *inbox,
3562                             struct mlx4_cmd_mailbox *outbox,
3563                             struct mlx4_cmd_info *cmd)
3564 {
3565         int err;
3566         struct mlx4_qp_context *context = inbox->buf + 8;
3567
3568         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3569         if (err)
3570                 return err;
3571         err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
3572         if (err)
3573                 return err;
3574
3575         adjust_proxy_tun_qkey(dev, vhcr, context);
3576         update_gid(dev, inbox, (u8)slave);
3577         update_pkey_index(dev, slave, inbox);
3578         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3579 }
3580
3581 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3582                             struct mlx4_vhcr *vhcr,
3583                             struct mlx4_cmd_mailbox *inbox,
3584                             struct mlx4_cmd_mailbox *outbox,
3585                             struct mlx4_cmd_info *cmd)
3586 {
3587         int err;
3588         struct mlx4_qp_context *context = inbox->buf + 8;
3589
3590         err = adjust_qp_sched_queue(dev, slave, context, inbox);
3591         if (err)
3592                 return err;
3593         err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
3594         if (err)
3595                 return err;
3596
3597         adjust_proxy_tun_qkey(dev, vhcr, context);
3598         update_gid(dev, inbox, (u8)slave);
3599         update_pkey_index(dev, slave, inbox);
3600         return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3601 }
3602
3603 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3604                          struct mlx4_vhcr *vhcr,
3605                          struct mlx4_cmd_mailbox *inbox,
3606                          struct mlx4_cmd_mailbox *outbox,
3607                          struct mlx4_cmd_info *cmd)
3608 {
3609         int err;
3610         int qpn = vhcr->in_modifier & 0x7fffff;
3611         struct res_qp *qp;
3612
3613         err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3614         if (err)
3615                 return err;
3616         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3617         if (err)
3618                 goto ex_abort;
3619
3620         atomic_dec(&qp->mtt->ref_count);
3621         atomic_dec(&qp->rcq->ref_count);
3622         atomic_dec(&qp->scq->ref_count);
3623         if (qp->srq)
3624                 atomic_dec(&qp->srq->ref_count);
3625         res_end_move(dev, slave, RES_QP, qpn);
3626         return 0;
3627
3628 ex_abort:
3629         res_abort_move(dev, slave, RES_QP, qpn);
3630
3631         return err;
3632 }
3633
3634 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3635                                 struct res_qp *rqp, u8 *gid)
3636 {
3637         struct res_gid *res;
3638
3639         list_for_each_entry(res, &rqp->mcg_list, list) {
3640                 if (!memcmp(res->gid, gid, 16))
3641                         return res;
3642         }
3643         return NULL;
3644 }
3645
3646 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3647                        u8 *gid, enum mlx4_protocol prot,
3648                        enum mlx4_steer_type steer, u64 reg_id)
3649 {
3650         struct res_gid *res;
3651         int err;
3652
3653         res = kzalloc(sizeof *res, GFP_KERNEL);
3654         if (!res)
3655                 return -ENOMEM;
3656
3657         spin_lock_irq(&rqp->mcg_spl);
3658         if (find_gid(dev, slave, rqp, gid)) {
3659                 kfree(res);
3660                 err = -EEXIST;
3661         } else {
3662                 memcpy(res->gid, gid, 16);
3663                 res->prot = prot;
3664                 res->steer = steer;
3665                 res->reg_id = reg_id;
3666                 list_add_tail(&res->list, &rqp->mcg_list);
3667                 err = 0;
3668         }
3669         spin_unlock_irq(&rqp->mcg_spl);
3670
3671         return err;
3672 }
3673
3674 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3675                        u8 *gid, enum mlx4_protocol prot,
3676                        enum mlx4_steer_type steer, u64 *reg_id)
3677 {
3678         struct res_gid *res;
3679         int err;
3680
3681         spin_lock_irq(&rqp->mcg_spl);
3682         res = find_gid(dev, slave, rqp, gid);
3683         if (!res || res->prot != prot || res->steer != steer)
3684                 err = -EINVAL;
3685         else {
3686                 *reg_id = res->reg_id;
3687                 list_del(&res->list);
3688                 kfree(res);
3689                 err = 0;
3690         }
3691         spin_unlock_irq(&rqp->mcg_spl);
3692
3693         return err;
3694 }
3695
3696 static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
3697                      u8 gid[16], int block_loopback, enum mlx4_protocol prot,
3698                      enum mlx4_steer_type type, u64 *reg_id)
3699 {
3700         switch (dev->caps.steering_mode) {
3701         case MLX4_STEERING_MODE_DEVICE_MANAGED: {
3702                 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3703                 if (port < 0)
3704                         return port;
3705                 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
3706                                                 block_loopback, prot,
3707                                                 reg_id);
3708         }
3709         case MLX4_STEERING_MODE_B0:
3710                 if (prot == MLX4_PROT_ETH) {
3711                         int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3712                         if (port < 0)
3713                                 return port;
3714                         gid[5] = port;
3715                 }
3716                 return mlx4_qp_attach_common(dev, qp, gid,
3717                                             block_loopback, prot, type);
3718         default:
3719                 return -EINVAL;
3720         }
3721 }
3722
3723 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
3724                      u8 gid[16], enum mlx4_protocol prot,
3725                      enum mlx4_steer_type type, u64 reg_id)
3726 {
3727         switch (dev->caps.steering_mode) {
3728         case MLX4_STEERING_MODE_DEVICE_MANAGED:
3729                 return mlx4_flow_detach(dev, reg_id);
3730         case MLX4_STEERING_MODE_B0:
3731                 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
3732         default:
3733                 return -EINVAL;
3734         }
3735 }
3736
3737 static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
3738                             u8 *gid, enum mlx4_protocol prot)
3739 {
3740         int real_port;
3741
3742         if (prot != MLX4_PROT_ETH)
3743                 return 0;
3744
3745         if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
3746             dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3747                 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
3748                 if (real_port < 0)
3749                         return -EINVAL;
3750                 gid[5] = real_port;
3751         }
3752
3753         return 0;
3754 }
3755
3756 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3757                                struct mlx4_vhcr *vhcr,
3758                                struct mlx4_cmd_mailbox *inbox,
3759                                struct mlx4_cmd_mailbox *outbox,
3760                                struct mlx4_cmd_info *cmd)
3761 {
3762         struct mlx4_qp qp; /* dummy for calling attach/detach */
3763         u8 *gid = inbox->buf;
3764         enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
3765         int err;
3766         int qpn;
3767         struct res_qp *rqp;
3768         u64 reg_id = 0;
3769         int attach = vhcr->op_modifier;
3770         int block_loopback = vhcr->in_modifier >> 31;
3771         u8 steer_type_mask = 2;
3772         enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
3773
3774         qpn = vhcr->in_modifier & 0xffffff;
3775         err = get_res(dev, slave, qpn, RES_QP, &rqp);
3776         if (err)
3777                 return err;
3778
3779         qp.qpn = qpn;
3780         if (attach) {
3781                 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
3782                                 type, &reg_id);
3783                 if (err) {
3784                         pr_err("Fail to attach rule to qp 0x%x\n", qpn);
3785                         goto ex_put;
3786                 }
3787                 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
3788                 if (err)
3789                         goto ex_detach;
3790         } else {
3791                 err = mlx4_adjust_port(dev, slave, gid, prot);
3792                 if (err)
3793                         goto ex_put;
3794
3795                 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
3796                 if (err)
3797                         goto ex_put;
3798
3799                 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
3800                 if (err)
3801                         pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
3802                                qpn, reg_id);
3803         }
3804         put_res(dev, slave, qpn, RES_QP);
3805         return err;
3806
3807 ex_detach:
3808         qp_detach(dev, &qp, gid, prot, type, reg_id);
3809 ex_put:
3810         put_res(dev, slave, qpn, RES_QP);
3811         return err;
3812 }
3813
3814 /*
3815  * MAC validation for Flow Steering rules.
3816  * VF can attach rules only with a mac address which is assigned to it.
3817  */
3818 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
3819                                    struct list_head *rlist)
3820 {
3821         struct mac_res *res, *tmp;
3822         __be64 be_mac;
3823
3824         /* make sure it isn't multicast or broadcast mac*/
3825         if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
3826             !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
3827                 list_for_each_entry_safe(res, tmp, rlist, list) {
3828                         be_mac = cpu_to_be64(res->mac << 16);
3829                         if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
3830                                 return 0;
3831                 }
3832                 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
3833                        eth_header->eth.dst_mac, slave);
3834                 return -EINVAL;
3835         }
3836         return 0;
3837 }
3838
3839 /*
3840  * In case of missing eth header, append eth header with a MAC address
3841  * assigned to the VF.
3842  */
3843 static int add_eth_header(struct mlx4_dev *dev, int slave,
3844                           struct mlx4_cmd_mailbox *inbox,
3845                           struct list_head *rlist, int header_id)
3846 {
3847         struct mac_res *res, *tmp;
3848         u8 port;
3849         struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3850         struct mlx4_net_trans_rule_hw_eth *eth_header;
3851         struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
3852         struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
3853         __be64 be_mac = 0;
3854         __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
3855
3856         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
3857         port = ctrl->port;
3858         eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
3859
3860         /* Clear a space in the inbox for eth header */
3861         switch (header_id) {
3862         case MLX4_NET_TRANS_RULE_ID_IPV4:
3863                 ip_header =
3864                         (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
3865                 memmove(ip_header, eth_header,
3866                         sizeof(*ip_header) + sizeof(*l4_header));
3867                 break;
3868         case MLX4_NET_TRANS_RULE_ID_TCP:
3869         case MLX4_NET_TRANS_RULE_ID_UDP:
3870                 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
3871                             (eth_header + 1);
3872                 memmove(l4_header, eth_header, sizeof(*l4_header));
3873                 break;
3874         default:
3875                 return -EINVAL;
3876         }
3877         list_for_each_entry_safe(res, tmp, rlist, list) {
3878                 if (port == res->port) {
3879                         be_mac = cpu_to_be64(res->mac << 16);
3880                         break;
3881                 }
3882         }
3883         if (!be_mac) {
3884                 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
3885                        port);
3886                 return -EINVAL;
3887         }
3888
3889         memset(eth_header, 0, sizeof(*eth_header));
3890         eth_header->size = sizeof(*eth_header) >> 2;
3891         eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
3892         memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
3893         memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
3894
3895         return 0;
3896
3897 }
3898
3899 #define MLX4_UPD_QP_PATH_MASK_SUPPORTED (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)
3900 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
3901                            struct mlx4_vhcr *vhcr,
3902                            struct mlx4_cmd_mailbox *inbox,
3903                            struct mlx4_cmd_mailbox *outbox,
3904                            struct mlx4_cmd_info *cmd_info)
3905 {
3906         int err;
3907         u32 qpn = vhcr->in_modifier & 0xffffff;
3908         struct res_qp *rqp;
3909         u64 mac;
3910         unsigned port;
3911         u64 pri_addr_path_mask;
3912         struct mlx4_update_qp_context *cmd;
3913         int smac_index;
3914
3915         cmd = (struct mlx4_update_qp_context *)inbox->buf;
3916
3917         pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
3918         if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
3919             (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
3920                 return -EPERM;
3921
3922         /* Just change the smac for the QP */
3923         err = get_res(dev, slave, qpn, RES_QP, &rqp);
3924         if (err) {
3925                 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
3926                 return err;
3927         }
3928
3929         port = (rqp->sched_queue >> 6 & 1) + 1;
3930         smac_index = cmd->qp_context.pri_path.grh_mylmc;
3931         err = mac_find_smac_ix_in_slave(dev, slave, port,
3932                                         smac_index, &mac);
3933         if (err) {
3934                 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
3935                          qpn, smac_index);
3936                 goto err_mac;
3937         }
3938
3939         err = mlx4_cmd(dev, inbox->dma,
3940                        vhcr->in_modifier, 0,
3941                        MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
3942                        MLX4_CMD_NATIVE);
3943         if (err) {
3944                 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
3945                 goto err_mac;
3946         }
3947
3948 err_mac:
3949         put_res(dev, slave, qpn, RES_QP);
3950         return err;
3951 }
3952
3953 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3954                                          struct mlx4_vhcr *vhcr,
3955                                          struct mlx4_cmd_mailbox *inbox,
3956                                          struct mlx4_cmd_mailbox *outbox,
3957                                          struct mlx4_cmd_info *cmd)
3958 {
3959
3960         struct mlx4_priv *priv = mlx4_priv(dev);
3961         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3962         struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
3963         int err;
3964         int qpn;
3965         struct res_qp *rqp;
3966         struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3967         struct _rule_hw  *rule_header;
3968         int header_id;
3969
3970         if (dev->caps.steering_mode !=
3971             MLX4_STEERING_MODE_DEVICE_MANAGED)
3972                 return -EOPNOTSUPP;
3973
3974         ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
3975         ctrl->port = mlx4_slave_convert_port(dev, slave, ctrl->port);
3976         if (ctrl->port <= 0)
3977                 return -EINVAL;
3978         qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
3979         err = get_res(dev, slave, qpn, RES_QP, &rqp);
3980         if (err) {
3981                 pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
3982                 return err;
3983         }
3984         rule_header = (struct _rule_hw *)(ctrl + 1);
3985         header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
3986
3987         switch (header_id) {
3988         case MLX4_NET_TRANS_RULE_ID_ETH:
3989                 if (validate_eth_header_mac(slave, rule_header, rlist)) {
3990                         err = -EINVAL;
3991                         goto err_put;
3992                 }
3993                 break;
3994         case MLX4_NET_TRANS_RULE_ID_IB:
3995                 break;
3996         case MLX4_NET_TRANS_RULE_ID_IPV4:
3997         case MLX4_NET_TRANS_RULE_ID_TCP:
3998         case MLX4_NET_TRANS_RULE_ID_UDP:
3999                 pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
4000                 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4001                         err = -EINVAL;
4002                         goto err_put;
4003                 }
4004                 vhcr->in_modifier +=
4005                         sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4006                 break;
4007         default:
4008                 pr_err("Corrupted mailbox.\n");
4009                 err = -EINVAL;
4010                 goto err_put;
4011         }
4012
4013         err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4014                            vhcr->in_modifier, 0,
4015                            MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4016                            MLX4_CMD_NATIVE);
4017         if (err)
4018                 goto err_put;
4019
4020         err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
4021         if (err) {
4022                 mlx4_err(dev, "Fail to add flow steering resources.\n ");
4023                 /* detach rule*/
4024                 mlx4_cmd(dev, vhcr->out_param, 0, 0,
4025                          MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4026                          MLX4_CMD_NATIVE);
4027                 goto err_put;
4028         }
4029         atomic_inc(&rqp->ref_count);
4030 err_put:
4031         put_res(dev, slave, qpn, RES_QP);
4032         return err;
4033 }
4034
4035 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4036                                          struct mlx4_vhcr *vhcr,
4037                                          struct mlx4_cmd_mailbox *inbox,
4038                                          struct mlx4_cmd_mailbox *outbox,
4039                                          struct mlx4_cmd_info *cmd)
4040 {
4041         int err;
4042         struct res_qp *rqp;
4043         struct res_fs_rule *rrule;
4044
4045         if (dev->caps.steering_mode !=
4046             MLX4_STEERING_MODE_DEVICE_MANAGED)
4047                 return -EOPNOTSUPP;
4048
4049         err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4050         if (err)
4051                 return err;
4052         /* Release the rule form busy state before removal */
4053         put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4054         err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4055         if (err)
4056                 return err;
4057
4058         err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4059         if (err) {
4060                 mlx4_err(dev, "Fail to remove flow steering resources.\n ");
4061                 goto out;
4062         }
4063
4064         err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4065                        MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4066                        MLX4_CMD_NATIVE);
4067         if (!err)
4068                 atomic_dec(&rqp->ref_count);
4069 out:
4070         put_res(dev, slave, rrule->qpn, RES_QP);
4071         return err;
4072 }
4073
4074 enum {
4075         BUSY_MAX_RETRIES = 10
4076 };
4077
4078 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4079                                struct mlx4_vhcr *vhcr,
4080                                struct mlx4_cmd_mailbox *inbox,
4081                                struct mlx4_cmd_mailbox *outbox,
4082                                struct mlx4_cmd_info *cmd)
4083 {
4084         int err;
4085         int index = vhcr->in_modifier & 0xffff;
4086
4087         err = get_res(dev, slave, index, RES_COUNTER, NULL);
4088         if (err)
4089                 return err;
4090
4091         err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4092         put_res(dev, slave, index, RES_COUNTER);
4093         return err;
4094 }
4095
4096 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4097 {
4098         struct res_gid *rgid;
4099         struct res_gid *tmp;
4100         struct mlx4_qp qp; /* dummy for calling attach/detach */
4101
4102         list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
4103                 switch (dev->caps.steering_mode) {
4104                 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4105                         mlx4_flow_detach(dev, rgid->reg_id);
4106                         break;
4107                 case MLX4_STEERING_MODE_B0:
4108                         qp.qpn = rqp->local_qpn;
4109                         (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4110                                                      rgid->prot, rgid->steer);
4111                         break;
4112                 }
4113                 list_del(&rgid->list);
4114                 kfree(rgid);
4115         }
4116 }
4117
4118 static int _move_all_busy(struct mlx4_dev *dev, int slave,
4119                           enum mlx4_resource type, int print)
4120 {
4121         struct mlx4_priv *priv = mlx4_priv(dev);
4122         struct mlx4_resource_tracker *tracker =
4123                 &priv->mfunc.master.res_tracker;
4124         struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4125         struct res_common *r;
4126         struct res_common *tmp;
4127         int busy;
4128
4129         busy = 0;
4130         spin_lock_irq(mlx4_tlock(dev));
4131         list_for_each_entry_safe(r, tmp, rlist, list) {
4132                 if (r->owner == slave) {
4133                         if (!r->removing) {
4134                                 if (r->state == RES_ANY_BUSY) {
4135                                         if (print)
4136                                                 mlx4_dbg(dev,
4137                                                          "%s id 0x%llx is busy\n",
4138                                                           ResourceType(type),
4139                                                           r->res_id);
4140                                         ++busy;
4141                                 } else {
4142                                         r->from_state = r->state;
4143                                         r->state = RES_ANY_BUSY;
4144                                         r->removing = 1;
4145                                 }
4146                         }
4147                 }
4148         }
4149         spin_unlock_irq(mlx4_tlock(dev));
4150
4151         return busy;
4152 }
4153
4154 static int move_all_busy(struct mlx4_dev *dev, int slave,
4155                          enum mlx4_resource type)
4156 {
4157         unsigned long begin;
4158         int busy;
4159
4160         begin = jiffies;
4161         do {
4162                 busy = _move_all_busy(dev, slave, type, 0);
4163                 if (time_after(jiffies, begin + 5 * HZ))
4164                         break;
4165                 if (busy)
4166                         cond_resched();
4167         } while (busy);
4168
4169         if (busy)
4170                 busy = _move_all_busy(dev, slave, type, 1);
4171
4172         return busy;
4173 }
4174 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4175 {
4176         struct mlx4_priv *priv = mlx4_priv(dev);
4177         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4178         struct list_head *qp_list =
4179                 &tracker->slave_list[slave].res_list[RES_QP];
4180         struct res_qp *qp;
4181         struct res_qp *tmp;
4182         int state;
4183         u64 in_param;
4184         int qpn;
4185         int err;
4186
4187         err = move_all_busy(dev, slave, RES_QP);
4188         if (err)
4189                 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
4190                           "for slave %d\n", slave);
4191
4192         spin_lock_irq(mlx4_tlock(dev));
4193         list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4194                 spin_unlock_irq(mlx4_tlock(dev));
4195                 if (qp->com.owner == slave) {
4196                         qpn = qp->com.res_id;
4197                         detach_qp(dev, slave, qp);
4198                         state = qp->com.from_state;
4199                         while (state != 0) {
4200                                 switch (state) {
4201                                 case RES_QP_RESERVED:
4202                                         spin_lock_irq(mlx4_tlock(dev));
4203                                         rb_erase(&qp->com.node,
4204                                                  &tracker->res_tree[RES_QP]);
4205                                         list_del(&qp->com.list);
4206                                         spin_unlock_irq(mlx4_tlock(dev));
4207                                         if (!valid_reserved(dev, slave, qpn)) {
4208                                                 __mlx4_qp_release_range(dev, qpn, 1);
4209                                                 mlx4_release_resource(dev, slave,
4210                                                                       RES_QP, 1, 0);
4211                                         }
4212                                         kfree(qp);
4213                                         state = 0;
4214                                         break;
4215                                 case RES_QP_MAPPED:
4216                                         if (!valid_reserved(dev, slave, qpn))
4217                                                 __mlx4_qp_free_icm(dev, qpn);
4218                                         state = RES_QP_RESERVED;
4219                                         break;
4220                                 case RES_QP_HW:
4221                                         in_param = slave;
4222                                         err = mlx4_cmd(dev, in_param,
4223                                                        qp->local_qpn, 2,
4224                                                        MLX4_CMD_2RST_QP,
4225                                                        MLX4_CMD_TIME_CLASS_A,
4226                                                        MLX4_CMD_NATIVE);
4227                                         if (err)
4228                                                 mlx4_dbg(dev, "rem_slave_qps: failed"
4229                                                          " to move slave %d qpn %d to"
4230                                                          " reset\n", slave,
4231                                                          qp->local_qpn);
4232                                         atomic_dec(&qp->rcq->ref_count);
4233                                         atomic_dec(&qp->scq->ref_count);
4234                                         atomic_dec(&qp->mtt->ref_count);
4235                                         if (qp->srq)
4236                                                 atomic_dec(&qp->srq->ref_count);
4237                                         state = RES_QP_MAPPED;
4238                                         break;
4239                                 default:
4240                                         state = 0;
4241                                 }
4242                         }
4243                 }
4244                 spin_lock_irq(mlx4_tlock(dev));
4245         }
4246         spin_unlock_irq(mlx4_tlock(dev));
4247 }
4248
4249 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4250 {
4251         struct mlx4_priv *priv = mlx4_priv(dev);
4252         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4253         struct list_head *srq_list =
4254                 &tracker->slave_list[slave].res_list[RES_SRQ];
4255         struct res_srq *srq;
4256         struct res_srq *tmp;
4257         int state;
4258         u64 in_param;
4259         LIST_HEAD(tlist);
4260         int srqn;
4261         int err;
4262
4263         err = move_all_busy(dev, slave, RES_SRQ);
4264         if (err)
4265                 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
4266                           "busy for slave %d\n", slave);
4267
4268         spin_lock_irq(mlx4_tlock(dev));
4269         list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4270                 spin_unlock_irq(mlx4_tlock(dev));
4271                 if (srq->com.owner == slave) {
4272                         srqn = srq->com.res_id;
4273                         state = srq->com.from_state;
4274                         while (state != 0) {
4275                                 switch (state) {
4276                                 case RES_SRQ_ALLOCATED:
4277                                         __mlx4_srq_free_icm(dev, srqn);
4278                                         spin_lock_irq(mlx4_tlock(dev));
4279                                         rb_erase(&srq->com.node,
4280                                                  &tracker->res_tree[RES_SRQ]);
4281                                         list_del(&srq->com.list);
4282                                         spin_unlock_irq(mlx4_tlock(dev));
4283                                         mlx4_release_resource(dev, slave,
4284                                                               RES_SRQ, 1, 0);
4285                                         kfree(srq);
4286                                         state = 0;
4287                                         break;
4288
4289                                 case RES_SRQ_HW:
4290                                         in_param = slave;
4291                                         err = mlx4_cmd(dev, in_param, srqn, 1,
4292                                                        MLX4_CMD_HW2SW_SRQ,
4293                                                        MLX4_CMD_TIME_CLASS_A,
4294                                                        MLX4_CMD_NATIVE);
4295                                         if (err)
4296                                                 mlx4_dbg(dev, "rem_slave_srqs: failed"
4297                                                          " to move slave %d srq %d to"
4298                                                          " SW ownership\n",
4299                                                          slave, srqn);
4300
4301                                         atomic_dec(&srq->mtt->ref_count);
4302                                         if (srq->cq)
4303                                                 atomic_dec(&srq->cq->ref_count);
4304                                         state = RES_SRQ_ALLOCATED;
4305                                         break;
4306
4307                                 default:
4308                                         state = 0;
4309                                 }
4310                         }
4311                 }
4312                 spin_lock_irq(mlx4_tlock(dev));
4313         }
4314         spin_unlock_irq(mlx4_tlock(dev));
4315 }
4316
4317 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4318 {
4319         struct mlx4_priv *priv = mlx4_priv(dev);
4320         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4321         struct list_head *cq_list =
4322                 &tracker->slave_list[slave].res_list[RES_CQ];
4323         struct res_cq *cq;
4324         struct res_cq *tmp;
4325         int state;
4326         u64 in_param;
4327         LIST_HEAD(tlist);
4328         int cqn;
4329         int err;
4330
4331         err = move_all_busy(dev, slave, RES_CQ);
4332         if (err)
4333                 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
4334                           "busy for slave %d\n", slave);
4335
4336         spin_lock_irq(mlx4_tlock(dev));
4337         list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4338                 spin_unlock_irq(mlx4_tlock(dev));
4339                 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4340                         cqn = cq->com.res_id;
4341                         state = cq->com.from_state;
4342                         while (state != 0) {
4343                                 switch (state) {
4344                                 case RES_CQ_ALLOCATED:
4345                                         __mlx4_cq_free_icm(dev, cqn);
4346                                         spin_lock_irq(mlx4_tlock(dev));
4347                                         rb_erase(&cq->com.node,
4348                                                  &tracker->res_tree[RES_CQ]);
4349                                         list_del(&cq->com.list);
4350                                         spin_unlock_irq(mlx4_tlock(dev));
4351                                         mlx4_release_resource(dev, slave,
4352                                                               RES_CQ, 1, 0);
4353                                         kfree(cq);
4354                                         state = 0;
4355                                         break;
4356
4357                                 case RES_CQ_HW:
4358                                         in_param = slave;
4359                                         err = mlx4_cmd(dev, in_param, cqn, 1,
4360                                                        MLX4_CMD_HW2SW_CQ,
4361                                                        MLX4_CMD_TIME_CLASS_A,
4362                                                        MLX4_CMD_NATIVE);
4363                                         if (err)
4364                                                 mlx4_dbg(dev, "rem_slave_cqs: failed"
4365                                                          " to move slave %d cq %d to"
4366                                                          " SW ownership\n",
4367                                                          slave, cqn);
4368                                         atomic_dec(&cq->mtt->ref_count);
4369                                         state = RES_CQ_ALLOCATED;
4370                                         break;
4371
4372                                 default:
4373                                         state = 0;
4374                                 }
4375                         }
4376                 }
4377                 spin_lock_irq(mlx4_tlock(dev));
4378         }
4379         spin_unlock_irq(mlx4_tlock(dev));
4380 }
4381
4382 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4383 {
4384         struct mlx4_priv *priv = mlx4_priv(dev);
4385         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4386         struct list_head *mpt_list =
4387                 &tracker->slave_list[slave].res_list[RES_MPT];
4388         struct res_mpt *mpt;
4389         struct res_mpt *tmp;
4390         int state;
4391         u64 in_param;
4392         LIST_HEAD(tlist);
4393         int mptn;
4394         int err;
4395
4396         err = move_all_busy(dev, slave, RES_MPT);
4397         if (err)
4398                 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
4399                           "busy for slave %d\n", slave);
4400
4401         spin_lock_irq(mlx4_tlock(dev));
4402         list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4403                 spin_unlock_irq(mlx4_tlock(dev));
4404                 if (mpt->com.owner == slave) {
4405                         mptn = mpt->com.res_id;
4406                         state = mpt->com.from_state;
4407                         while (state != 0) {
4408                                 switch (state) {
4409                                 case RES_MPT_RESERVED:
4410                                         __mlx4_mpt_release(dev, mpt->key);
4411                                         spin_lock_irq(mlx4_tlock(dev));
4412                                         rb_erase(&mpt->com.node,
4413                                                  &tracker->res_tree[RES_MPT]);
4414                                         list_del(&mpt->com.list);
4415                                         spin_unlock_irq(mlx4_tlock(dev));
4416                                         mlx4_release_resource(dev, slave,
4417                                                               RES_MPT, 1, 0);
4418                                         kfree(mpt);
4419                                         state = 0;
4420                                         break;
4421
4422                                 case RES_MPT_MAPPED:
4423                                         __mlx4_mpt_free_icm(dev, mpt->key);
4424                                         state = RES_MPT_RESERVED;
4425                                         break;
4426
4427                                 case RES_MPT_HW:
4428                                         in_param = slave;
4429                                         err = mlx4_cmd(dev, in_param, mptn, 0,
4430                                                      MLX4_CMD_HW2SW_MPT,
4431                                                      MLX4_CMD_TIME_CLASS_A,
4432                                                      MLX4_CMD_NATIVE);
4433                                         if (err)
4434                                                 mlx4_dbg(dev, "rem_slave_mrs: failed"
4435                                                          " to move slave %d mpt %d to"
4436                                                          " SW ownership\n",
4437                                                          slave, mptn);
4438                                         if (mpt->mtt)
4439                                                 atomic_dec(&mpt->mtt->ref_count);
4440                                         state = RES_MPT_MAPPED;
4441                                         break;
4442                                 default:
4443                                         state = 0;
4444                                 }
4445                         }
4446                 }
4447                 spin_lock_irq(mlx4_tlock(dev));
4448         }
4449         spin_unlock_irq(mlx4_tlock(dev));
4450 }
4451
4452 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4453 {
4454         struct mlx4_priv *priv = mlx4_priv(dev);
4455         struct mlx4_resource_tracker *tracker =
4456                 &priv->mfunc.master.res_tracker;
4457         struct list_head *mtt_list =
4458                 &tracker->slave_list[slave].res_list[RES_MTT];
4459         struct res_mtt *mtt;
4460         struct res_mtt *tmp;
4461         int state;
4462         LIST_HEAD(tlist);
4463         int base;
4464         int err;
4465
4466         err = move_all_busy(dev, slave, RES_MTT);
4467         if (err)
4468                 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
4469                           "busy for slave %d\n", slave);
4470
4471         spin_lock_irq(mlx4_tlock(dev));
4472         list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4473                 spin_unlock_irq(mlx4_tlock(dev));
4474                 if (mtt->com.owner == slave) {
4475                         base = mtt->com.res_id;
4476                         state = mtt->com.from_state;
4477                         while (state != 0) {
4478                                 switch (state) {
4479                                 case RES_MTT_ALLOCATED:
4480                                         __mlx4_free_mtt_range(dev, base,
4481                                                               mtt->order);
4482                                         spin_lock_irq(mlx4_tlock(dev));
4483                                         rb_erase(&mtt->com.node,
4484                                                  &tracker->res_tree[RES_MTT]);
4485                                         list_del(&mtt->com.list);
4486                                         spin_unlock_irq(mlx4_tlock(dev));
4487                                         mlx4_release_resource(dev, slave, RES_MTT,
4488                                                               1 << mtt->order, 0);
4489                                         kfree(mtt);
4490                                         state = 0;
4491                                         break;
4492
4493                                 default:
4494                                         state = 0;
4495                                 }
4496                         }
4497                 }
4498                 spin_lock_irq(mlx4_tlock(dev));
4499         }
4500         spin_unlock_irq(mlx4_tlock(dev));
4501 }
4502
4503 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
4504 {
4505         struct mlx4_priv *priv = mlx4_priv(dev);
4506         struct mlx4_resource_tracker *tracker =
4507                 &priv->mfunc.master.res_tracker;
4508         struct list_head *fs_rule_list =
4509                 &tracker->slave_list[slave].res_list[RES_FS_RULE];
4510         struct res_fs_rule *fs_rule;
4511         struct res_fs_rule *tmp;
4512         int state;
4513         u64 base;
4514         int err;
4515
4516         err = move_all_busy(dev, slave, RES_FS_RULE);
4517         if (err)
4518                 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
4519                           slave);
4520
4521         spin_lock_irq(mlx4_tlock(dev));
4522         list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
4523                 spin_unlock_irq(mlx4_tlock(dev));
4524                 if (fs_rule->com.owner == slave) {
4525                         base = fs_rule->com.res_id;
4526                         state = fs_rule->com.from_state;
4527                         while (state != 0) {
4528                                 switch (state) {
4529                                 case RES_FS_RULE_ALLOCATED:
4530                                         /* detach rule */
4531                                         err = mlx4_cmd(dev, base, 0, 0,
4532                                                        MLX4_QP_FLOW_STEERING_DETACH,
4533                                                        MLX4_CMD_TIME_CLASS_A,
4534                                                        MLX4_CMD_NATIVE);
4535
4536                                         spin_lock_irq(mlx4_tlock(dev));
4537                                         rb_erase(&fs_rule->com.node,
4538                                                  &tracker->res_tree[RES_FS_RULE]);
4539                                         list_del(&fs_rule->com.list);
4540                                         spin_unlock_irq(mlx4_tlock(dev));
4541                                         kfree(fs_rule);
4542                                         state = 0;
4543                                         break;
4544
4545                                 default:
4546                                         state = 0;
4547                                 }
4548                         }
4549                 }
4550                 spin_lock_irq(mlx4_tlock(dev));
4551         }
4552         spin_unlock_irq(mlx4_tlock(dev));
4553 }
4554
4555 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
4556 {
4557         struct mlx4_priv *priv = mlx4_priv(dev);
4558         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4559         struct list_head *eq_list =
4560                 &tracker->slave_list[slave].res_list[RES_EQ];
4561         struct res_eq *eq;
4562         struct res_eq *tmp;
4563         int err;
4564         int state;
4565         LIST_HEAD(tlist);
4566         int eqn;
4567         struct mlx4_cmd_mailbox *mailbox;
4568
4569         err = move_all_busy(dev, slave, RES_EQ);
4570         if (err)
4571                 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
4572                           "busy for slave %d\n", slave);
4573
4574         spin_lock_irq(mlx4_tlock(dev));
4575         list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
4576                 spin_unlock_irq(mlx4_tlock(dev));
4577                 if (eq->com.owner == slave) {
4578                         eqn = eq->com.res_id;
4579                         state = eq->com.from_state;
4580                         while (state != 0) {
4581                                 switch (state) {
4582                                 case RES_EQ_RESERVED:
4583                                         spin_lock_irq(mlx4_tlock(dev));
4584                                         rb_erase(&eq->com.node,
4585                                                  &tracker->res_tree[RES_EQ]);
4586                                         list_del(&eq->com.list);
4587                                         spin_unlock_irq(mlx4_tlock(dev));
4588                                         kfree(eq);
4589                                         state = 0;
4590                                         break;
4591
4592                                 case RES_EQ_HW:
4593                                         mailbox = mlx4_alloc_cmd_mailbox(dev);
4594                                         if (IS_ERR(mailbox)) {
4595                                                 cond_resched();
4596                                                 continue;
4597                                         }
4598                                         err = mlx4_cmd_box(dev, slave, 0,
4599                                                            eqn & 0xff, 0,
4600                                                            MLX4_CMD_HW2SW_EQ,
4601                                                            MLX4_CMD_TIME_CLASS_A,
4602                                                            MLX4_CMD_NATIVE);
4603                                         if (err)
4604                                                 mlx4_dbg(dev, "rem_slave_eqs: failed"
4605                                                          " to move slave %d eqs %d to"
4606                                                          " SW ownership\n", slave, eqn);
4607                                         mlx4_free_cmd_mailbox(dev, mailbox);
4608                                         atomic_dec(&eq->mtt->ref_count);
4609                                         state = RES_EQ_RESERVED;
4610                                         break;
4611
4612                                 default:
4613                                         state = 0;
4614                                 }
4615                         }
4616                 }
4617                 spin_lock_irq(mlx4_tlock(dev));
4618         }
4619         spin_unlock_irq(mlx4_tlock(dev));
4620 }
4621
4622 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
4623 {
4624         struct mlx4_priv *priv = mlx4_priv(dev);
4625         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4626         struct list_head *counter_list =
4627                 &tracker->slave_list[slave].res_list[RES_COUNTER];
4628         struct res_counter *counter;
4629         struct res_counter *tmp;
4630         int err;
4631         int index;
4632
4633         err = move_all_busy(dev, slave, RES_COUNTER);
4634         if (err)
4635                 mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
4636                           "busy for slave %d\n", slave);
4637
4638         spin_lock_irq(mlx4_tlock(dev));
4639         list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
4640                 if (counter->com.owner == slave) {
4641                         index = counter->com.res_id;
4642                         rb_erase(&counter->com.node,
4643                                  &tracker->res_tree[RES_COUNTER]);
4644                         list_del(&counter->com.list);
4645                         kfree(counter);
4646                         __mlx4_counter_free(dev, index);
4647                         mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
4648                 }
4649         }
4650         spin_unlock_irq(mlx4_tlock(dev));
4651 }
4652
4653 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
4654 {
4655         struct mlx4_priv *priv = mlx4_priv(dev);
4656         struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4657         struct list_head *xrcdn_list =
4658                 &tracker->slave_list[slave].res_list[RES_XRCD];
4659         struct res_xrcdn *xrcd;
4660         struct res_xrcdn *tmp;
4661         int err;
4662         int xrcdn;
4663
4664         err = move_all_busy(dev, slave, RES_XRCD);
4665         if (err)
4666                 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
4667                           "busy for slave %d\n", slave);
4668
4669         spin_lock_irq(mlx4_tlock(dev));
4670         list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
4671                 if (xrcd->com.owner == slave) {
4672                         xrcdn = xrcd->com.res_id;
4673                         rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
4674                         list_del(&xrcd->com.list);
4675                         kfree(xrcd);
4676                         __mlx4_xrcd_free(dev, xrcdn);
4677                 }
4678         }
4679         spin_unlock_irq(mlx4_tlock(dev));
4680 }
4681
4682 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
4683 {
4684         struct mlx4_priv *priv = mlx4_priv(dev);
4685         mlx4_reset_roce_gids(dev, slave);
4686         mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4687         rem_slave_vlans(dev, slave);
4688         rem_slave_macs(dev, slave);
4689         rem_slave_fs_rule(dev, slave);
4690         rem_slave_qps(dev, slave);
4691         rem_slave_srqs(dev, slave);
4692         rem_slave_cqs(dev, slave);
4693         rem_slave_mrs(dev, slave);
4694         rem_slave_eqs(dev, slave);
4695         rem_slave_mtts(dev, slave);
4696         rem_slave_counters(dev, slave);
4697         rem_slave_xrcdns(dev, slave);
4698         mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4699 }
4700
4701 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
4702 {
4703         struct mlx4_vf_immed_vlan_work *work =
4704                 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
4705         struct mlx4_cmd_mailbox *mailbox;
4706         struct mlx4_update_qp_context *upd_context;
4707         struct mlx4_dev *dev = &work->priv->dev;
4708         struct mlx4_resource_tracker *tracker =
4709                 &work->priv->mfunc.master.res_tracker;
4710         struct list_head *qp_list =
4711                 &tracker->slave_list[work->slave].res_list[RES_QP];
4712         struct res_qp *qp;
4713         struct res_qp *tmp;
4714         u64 qp_path_mask_vlan_ctrl =
4715                        ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
4716                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
4717                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
4718                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
4719                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
4720                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
4721
4722         u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
4723                        (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
4724                        (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
4725                        (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
4726                        (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
4727                        (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
4728                        (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
4729
4730         int err;
4731         int port, errors = 0;
4732         u8 vlan_control;
4733
4734         if (mlx4_is_slave(dev)) {
4735                 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
4736                           work->slave);
4737                 goto out;
4738         }
4739
4740         mailbox = mlx4_alloc_cmd_mailbox(dev);
4741         if (IS_ERR(mailbox))
4742                 goto out;
4743         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
4744                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4745                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
4746                         MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
4747                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4748                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
4749                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4750         else if (!work->vlan_id)
4751                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4752                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4753         else
4754                 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4755                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4756                         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
4757
4758         upd_context = mailbox->buf;
4759         upd_context->qp_mask = cpu_to_be64(MLX4_UPD_QP_MASK_VSD);
4760
4761         spin_lock_irq(mlx4_tlock(dev));
4762         list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4763                 spin_unlock_irq(mlx4_tlock(dev));
4764                 if (qp->com.owner == work->slave) {
4765                         if (qp->com.from_state != RES_QP_HW ||
4766                             !qp->sched_queue ||  /* no INIT2RTR trans yet */
4767                             mlx4_is_qp_reserved(dev, qp->local_qpn) ||
4768                             qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
4769                                 spin_lock_irq(mlx4_tlock(dev));
4770                                 continue;
4771                         }
4772                         port = (qp->sched_queue >> 6 & 1) + 1;
4773                         if (port != work->port) {
4774                                 spin_lock_irq(mlx4_tlock(dev));
4775                                 continue;
4776                         }
4777                         if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
4778                                 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
4779                         else
4780                                 upd_context->primary_addr_path_mask =
4781                                         cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
4782                         if (work->vlan_id == MLX4_VGT) {
4783                                 upd_context->qp_context.param3 = qp->param3;
4784                                 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
4785                                 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
4786                                 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
4787                                 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
4788                                 upd_context->qp_context.pri_path.feup = qp->feup;
4789                                 upd_context->qp_context.pri_path.sched_queue =
4790                                         qp->sched_queue;
4791                         } else {
4792                                 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
4793                                 upd_context->qp_context.pri_path.vlan_control = vlan_control;
4794                                 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
4795                                 upd_context->qp_context.pri_path.fvl_rx =
4796                                         qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
4797                                 upd_context->qp_context.pri_path.fl =
4798                                         qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
4799                                 upd_context->qp_context.pri_path.feup =
4800                                         qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
4801                                 upd_context->qp_context.pri_path.sched_queue =
4802                                         qp->sched_queue & 0xC7;
4803                                 upd_context->qp_context.pri_path.sched_queue |=
4804                                         ((work->qos & 0x7) << 3);
4805                         }
4806
4807                         err = mlx4_cmd(dev, mailbox->dma,
4808                                        qp->local_qpn & 0xffffff,
4809                                        0, MLX4_CMD_UPDATE_QP,
4810                                        MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
4811                         if (err) {
4812                                 mlx4_info(dev, "UPDATE_QP failed for slave %d, "
4813                                           "port %d, qpn %d (%d)\n",
4814                                           work->slave, port, qp->local_qpn,
4815                                           err);
4816                                 errors++;
4817                         }
4818                 }
4819                 spin_lock_irq(mlx4_tlock(dev));
4820         }
4821         spin_unlock_irq(mlx4_tlock(dev));
4822         mlx4_free_cmd_mailbox(dev, mailbox);
4823
4824         if (errors)
4825                 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
4826                          errors, work->slave, work->port);
4827
4828         /* unregister previous vlan_id if needed and we had no errors
4829          * while updating the QPs
4830          */
4831         if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
4832             NO_INDX != work->orig_vlan_ix)
4833                 __mlx4_unregister_vlan(&work->priv->dev, work->port,
4834                                        work->orig_vlan_id);
4835 out:
4836         kfree(work);
4837         return;
4838 }