drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd *cmd)
 119 {
 120         unsigned long flags;
 121         int ret;
 122
 123         spin_lock_irqsave(&cmd->alloc_lock, flags);
 124         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 125         if (ret < cmd->max_reg_cmds)
 126                 clear_bit(ret, &cmd->bitmask);
 127         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 128
 129         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 130 }
 131
 132 static void free_ent(struct mlx5_cmd *cmd, int idx)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&cmd->alloc_lock, flags);
 137         set_bit(idx, &cmd->bitmask);
 138         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 139 }
 140
 141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 142 {
 143         return cmd->cmd_buf + (idx << cmd->log_stride);
 144 }
 145
 146 static u8 xor8_buf(void *buf, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151
 152         for (i = 0; i < len; i++)
 153                 sum ^= ptr[i];
 154
 155         return sum;
 156 }
 157
 158 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 159 {
 160         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 161                 return -EINVAL;
 162
 163         if (xor8_buf(block, sizeof(*block)) != 0xff)
 164                 return -EINVAL;
 165
 166         return 0;
 167 }
 168
 169 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 170                            int csum)
 171 {
 172         block->token = token;
 173         if (csum) {
 174                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 175                                             sizeof(block->data) - 2);
 176                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 177         }
 178 }
 179
 180 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 181 {
 182         struct mlx5_cmd_mailbox *next = msg->next;
 183
 184         while (next) {
 185                 calc_block_sig(next->buf, token, csum);
 186                 next = next->next;
 187         }
 188 }
 189
 190 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 191 {
 192         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 193         calc_chain_sig(ent->in, ent->token, csum);
 194         calc_chain_sig(ent->out, ent->token, csum);
 195 }
 196
 197 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 198 {
 199         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 200         u8 own;
 201
 202         do {
 203                 own = ent->lay->status_own;
 204                 if (!(own & CMD_OWNER_HW)) {
 205                         ent->ret = 0;
 206                         return;
 207                 }
 208                 usleep_range(5000, 10000);
 209         } while (time_before(jiffies, poll_end));
 210
 211         ent->ret = -ETIMEDOUT;
 212 }
 213
 214 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 215 {
 216         kfree(ent);
 217 }
 218
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225
 226         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 227         if (sig != 0xff)
 228                 return -EINVAL;
 229
 230         while (next) {
 231                 err = verify_block_sig(next->buf);
 232                 if (err)
 233                         return err;
 234
 235                 next = next->next;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void dump_buf(void *buf, int size, int data_only, int offset)
 242 {
 243         __be32 *p = buf;
 244         int i;
 245
 246         for (i = 0; i < size; i += 16) {
 247                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 248                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 249                          be32_to_cpu(p[3]));
 250                 p += 4;
 251                 offset += 16;
 252         }
 253         if (!data_only)
 254                 pr_debug("\n");
 255 }
 256
 257 enum {
 258         MLX5_DRIVER_STATUS_ABORTED = 0xfe,
 259         MLX5_DRIVER_SYND = 0xbadd00de,
 260 };
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DEALLOC_PD:
 282         case MLX5_CMD_OP_DEALLOC_UAR:
 283         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 284         case MLX5_CMD_OP_DEALLOC_XRCD:
 285         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 286         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 287         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 288         case MLX5_CMD_OP_DESTROY_TIR:
 289         case MLX5_CMD_OP_DESTROY_SQ:
 290         case MLX5_CMD_OP_DESTROY_RQ:
 291         case MLX5_CMD_OP_DESTROY_RMP:
 292         case MLX5_CMD_OP_DESTROY_TIS:
 293         case MLX5_CMD_OP_DESTROY_RQT:
 294         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 295         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 296         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 297         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 298                 return MLX5_CMD_STAT_OK;
 299
 300         case MLX5_CMD_OP_QUERY_HCA_CAP:
 301         case MLX5_CMD_OP_QUERY_ADAPTER:
 302         case MLX5_CMD_OP_INIT_HCA:
 303         case MLX5_CMD_OP_ENABLE_HCA:
 304         case MLX5_CMD_OP_QUERY_PAGES:
 305         case MLX5_CMD_OP_SET_HCA_CAP:
 306         case MLX5_CMD_OP_QUERY_ISSI:
 307         case MLX5_CMD_OP_SET_ISSI:
 308         case MLX5_CMD_OP_CREATE_MKEY:
 309         case MLX5_CMD_OP_QUERY_MKEY:
 310         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 311         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 312         case MLX5_CMD_OP_CREATE_EQ:
 313         case MLX5_CMD_OP_QUERY_EQ:
 314         case MLX5_CMD_OP_GEN_EQE:
 315         case MLX5_CMD_OP_CREATE_CQ:
 316         case MLX5_CMD_OP_QUERY_CQ:
 317         case MLX5_CMD_OP_MODIFY_CQ:
 318         case MLX5_CMD_OP_CREATE_QP:
 319         case MLX5_CMD_OP_RST2INIT_QP:
 320         case MLX5_CMD_OP_INIT2RTR_QP:
 321         case MLX5_CMD_OP_RTR2RTS_QP:
 322         case MLX5_CMD_OP_RTS2RTS_QP:
 323         case MLX5_CMD_OP_SQERR2RTS_QP:
 324         case MLX5_CMD_OP_2ERR_QP:
 325         case MLX5_CMD_OP_2RST_QP:
 326         case MLX5_CMD_OP_QUERY_QP:
 327         case MLX5_CMD_OP_SQD_RTS_QP:
 328         case MLX5_CMD_OP_INIT2INIT_QP:
 329         case MLX5_CMD_OP_CREATE_PSV:
 330         case MLX5_CMD_OP_CREATE_SRQ:
 331         case MLX5_CMD_OP_QUERY_SRQ:
 332         case MLX5_CMD_OP_ARM_RQ:
 333         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 334         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 335         case MLX5_CMD_OP_ARM_XRC_SRQ:
 336         case MLX5_CMD_OP_CREATE_DCT:
 337         case MLX5_CMD_OP_DRAIN_DCT:
 338         case MLX5_CMD_OP_QUERY_DCT:
 339         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 340         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 341         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 342         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 343         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 344         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 345         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 346         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 347         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 348         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 349         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 350         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 351         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 352         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 353         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 354         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 355         case MLX5_CMD_OP_ALLOC_PD:
 356         case MLX5_CMD_OP_ALLOC_UAR:
 357         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 358         case MLX5_CMD_OP_ACCESS_REG:
 359         case MLX5_CMD_OP_ATTACH_TO_MCG:
 360         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 361         case MLX5_CMD_OP_MAD_IFC:
 362         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 363         case MLX5_CMD_OP_SET_MAD_DEMUX:
 364         case MLX5_CMD_OP_NOP:
 365         case MLX5_CMD_OP_ALLOC_XRCD:
 366         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 367         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 368         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 369         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 370         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 371         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 372         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 373         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 374         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 375         case MLX5_CMD_OP_CREATE_TIR:
 376         case MLX5_CMD_OP_MODIFY_TIR:
 377         case MLX5_CMD_OP_QUERY_TIR:
 378         case MLX5_CMD_OP_CREATE_SQ:
 379         case MLX5_CMD_OP_MODIFY_SQ:
 380         case MLX5_CMD_OP_QUERY_SQ:
 381         case MLX5_CMD_OP_CREATE_RQ:
 382         case MLX5_CMD_OP_MODIFY_RQ:
 383         case MLX5_CMD_OP_QUERY_RQ:
 384         case MLX5_CMD_OP_CREATE_RMP:
 385         case MLX5_CMD_OP_MODIFY_RMP:
 386         case MLX5_CMD_OP_QUERY_RMP:
 387         case MLX5_CMD_OP_CREATE_TIS:
 388         case MLX5_CMD_OP_MODIFY_TIS:
 389         case MLX5_CMD_OP_QUERY_TIS:
 390         case MLX5_CMD_OP_CREATE_RQT:
 391         case MLX5_CMD_OP_MODIFY_RQT:
 392         case MLX5_CMD_OP_QUERY_RQT:
 393         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 394         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 395         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 396         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 397         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 398         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 399         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 400         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 401                 *status = MLX5_DRIVER_STATUS_ABORTED;
 402                 *synd = MLX5_DRIVER_SYND;
 403                 return -EIO;
 404         default:
 405                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 406                 return -EINVAL;
 407         }
 408 }
 409
 410 const char *mlx5_command_str(int command)
 411 {
 412 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 413
 414         switch (command) {
 415         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 416         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 417         MLX5_COMMAND_STR_CASE(INIT_HCA);
 418         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 419         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 420         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 421         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 422         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 423         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 424         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 425         MLX5_COMMAND_STR_CASE(SET_ISSI);
 426         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 427         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 428         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 429         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 430         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 431         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 432         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 433         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 434         MLX5_COMMAND_STR_CASE(GEN_EQE);
 435         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 436         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 437         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 438         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 439         MLX5_COMMAND_STR_CASE(CREATE_QP);
 440         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 441         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 442         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 443         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 444         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 445         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 446         MLX5_COMMAND_STR_CASE(2ERR_QP);
 447         MLX5_COMMAND_STR_CASE(2RST_QP);
 448         MLX5_COMMAND_STR_CASE(QUERY_QP);
 449         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 450         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 451         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 452         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 453         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 454         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 455         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 456         MLX5_COMMAND_STR_CASE(ARM_RQ);
 457         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 460         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 461         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 462         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 463         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 464         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 465         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 466         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 467         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 468         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 469         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 470         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 471         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 472         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 473         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 474         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 475         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 476         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 477         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 478         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 479         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 480         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 481         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 482         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 483         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 484         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 485         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 486         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 487         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 488         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 489         MLX5_COMMAND_STR_CASE(DETTACH_FROM_MCG);
 490         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 491         MLX5_COMMAND_STR_CASE(MAD_IFC);
 492         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 493         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 494         MLX5_COMMAND_STR_CASE(NOP);
 495         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 496         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 497         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 498         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 499         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 500         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 501         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 502         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 503         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 504         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 505         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 506         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 507         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 508         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 509         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 510         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 511         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 512         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 513         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 514         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 515         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 516         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 517         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 518         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 519         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 520         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 521         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 522         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 523         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 524         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 525         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 526         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 527         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 528         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 529         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 530         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 531         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 532         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 533         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 534         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 535         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 536         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 537         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 538         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 539         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 540         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 541         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 542         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 543         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 544         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 545         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 546         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 547         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 548         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 549         default: return "unknown command opcode";
 550         }
 551 }
 552
 553 static void dump_command(struct mlx5_core_dev *dev,
 554                          struct mlx5_cmd_work_ent *ent, int input)
 555 {
 556         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 557         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 558         struct mlx5_cmd_mailbox *next = msg->next;
 559         int data_only;
 560         u32 offset = 0;
 561         int dump_len;
 562
 563         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 564
 565         if (data_only)
 566                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 567                                    "dump command data %s(0x%x) %s\n",
 568                                    mlx5_command_str(op), op,
 569                                    input ? "INPUT" : "OUTPUT");
 570         else
 571                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 572                               mlx5_command_str(op), op,
 573                               input ? "INPUT" : "OUTPUT");
 574
 575         if (data_only) {
 576                 if (input) {
 577                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 578                         offset += sizeof(ent->lay->in);
 579                 } else {
 580                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 581                         offset += sizeof(ent->lay->out);
 582                 }
 583         } else {
 584                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 585                 offset += sizeof(*ent->lay);
 586         }
 587
 588         while (next && offset < msg->len) {
 589                 if (data_only) {
 590                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 591                         dump_buf(next->buf, dump_len, 1, offset);
 592                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 593                 } else {
 594                         mlx5_core_dbg(dev, "command block:\n");
 595                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 596                         offset += sizeof(struct mlx5_cmd_prot_block);
 597                 }
 598                 next = next->next;
 599         }
 600
 601         if (data_only)
 602                 pr_debug("\n");
 603 }
 604
 605 static void cmd_work_handler(struct work_struct *work)
 606 {
 607         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 608         struct mlx5_cmd *cmd = ent->cmd;
 609         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 610         struct mlx5_cmd_layout *lay;
 611         struct semaphore *sem;
 612         unsigned long flags;
 613
 614         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 615         down(sem);
 616         if (!ent->page_queue) {
 617                 ent->idx = alloc_ent(cmd);
 618                 if (ent->idx < 0) {
 619                         mlx5_core_err(dev, "failed to allocate command entry\n");
 620                         up(sem);
 621                         return;
 622                 }
 623         } else {
 624                 ent->idx = cmd->max_reg_cmds;
 625                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 626                 clear_bit(ent->idx, &cmd->bitmask);
 627                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 628         }
 629
 630         ent->token = alloc_token(cmd);
 631         cmd->ent_arr[ent->idx] = ent;
 632         lay = get_inst(cmd, ent->idx);
 633         ent->lay = lay;
 634         memset(lay, 0, sizeof(*lay));
 635         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 636         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 637         if (ent->in->next)
 638                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 639         lay->inlen = cpu_to_be32(ent->in->len);
 640         if (ent->out->next)
 641                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 642         lay->outlen = cpu_to_be32(ent->out->len);
 643         lay->type = MLX5_PCI_CMD_XPORT;
 644         lay->token = ent->token;
 645         lay->status_own = CMD_OWNER_HW;
 646         set_signature(ent, !cmd->checksum_disabled);
 647         dump_command(dev, ent, 1);
 648         ent->ts1 = ktime_get_ns();
 649
 650         /* ring doorbell after the descriptor is valid */
 651         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 652         wmb();
 653         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 654         mmiowb();
 655         /* if not in polling don't use ent after this point */
 656         if (cmd->mode == CMD_MODE_POLLING) {
 657                 poll_timeout(ent);
 658                 /* make sure we read the descriptor after ownership is SW */
 659                 rmb();
 660                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 661         }
 662 }
 663
 664 static const char *deliv_status_to_str(u8 status)
 665 {
 666         switch (status) {
 667         case MLX5_CMD_DELIVERY_STAT_OK:
 668                 return "no errors";
 669         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 670                 return "signature error";
 671         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 672                 return "token error";
 673         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 674                 return "bad block number";
 675         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 676                 return "output pointer not aligned to block size";
 677         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 678                 return "input pointer not aligned to block size";
 679         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 680                 return "firmware internal error";
 681         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 682                 return "command input length error";
 683         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 684                 return "command ouput length error";
 685         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 686                 return "reserved fields not cleared";
 687         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 688                 return "bad command descriptor type";
 689         default:
 690                 return "unknown status code";
 691         }
 692 }
 693
 694 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 695 {
 696         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 697
 698         return be16_to_cpu(hdr->opcode);
 699 }
 700
 701 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 702 {
 703         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 704         struct mlx5_cmd *cmd = &dev->cmd;
 705         int err;
 706
 707         if (cmd->mode == CMD_MODE_POLLING) {
 708                 wait_for_completion(&ent->done);
 709                 err = ent->ret;
 710         } else {
 711                 if (!wait_for_completion_timeout(&ent->done, timeout))
 712                         err = -ETIMEDOUT;
 713                 else
 714                         err = 0;
 715         }
 716         if (err == -ETIMEDOUT) {
 717                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 718                                mlx5_command_str(msg_to_opcode(ent->in)),
 719                                msg_to_opcode(ent->in));
 720         }
 721         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 722                       err, deliv_status_to_str(ent->status), ent->status);
 723
 724         return err;
 725 }
 726
 727 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
 728 {
 729         return &out->syndrome;
 730 }
 731
 732 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
 733 {
 734         return &out->status;
 735 }
 736
 737 /*  Notes:
 738  *    1. Callback functions may not sleep
 739  *    2. page queue commands do not support asynchrous completion
 740  */
 741 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 742                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 743                            mlx5_cmd_cbk_t callback,
 744                            void *context, int page_queue, u8 *status)
 745 {
 746         struct mlx5_cmd *cmd = &dev->cmd;
 747         struct mlx5_cmd_work_ent *ent;
 748         struct mlx5_cmd_stats *stats;
 749         int err = 0;
 750         s64 ds;
 751         u16 op;
 752
 753         if (callback && page_queue)
 754                 return -EINVAL;
 755
 756         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 757                         page_queue);
 758         if (IS_ERR(ent))
 759                 return PTR_ERR(ent);
 760
 761         if (!callback)
 762                 init_completion(&ent->done);
 763
 764         INIT_WORK(&ent->work, cmd_work_handler);
 765         if (page_queue) {
 766                 cmd_work_handler(&ent->work);
 767         } else if (!queue_work(cmd->wq, &ent->work)) {
 768                 mlx5_core_warn(dev, "failed to queue work\n");
 769                 err = -ENOMEM;
 770                 goto out_free;
 771         }
 772
 773         if (!callback) {
 774                 err = wait_func(dev, ent);
 775                 if (err == -ETIMEDOUT)
 776                         goto out;
 777
 778                 ds = ent->ts2 - ent->ts1;
 779                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 780                 if (op < ARRAY_SIZE(cmd->stats)) {
 781                         stats = &cmd->stats[op];
 782                         spin_lock_irq(&stats->lock);
 783                         stats->sum += ds;
 784                         ++stats->n;
 785                         spin_unlock_irq(&stats->lock);
 786                 }
 787                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 788                                    "fw exec time for %s is %lld nsec\n",
 789                                    mlx5_command_str(op), ds);
 790                 *status = ent->status;
 791                 free_cmd(ent);
 792         }
 793
 794         return err;
 795
 796 out_free:
 797         free_cmd(ent);
 798 out:
 799         return err;
 800 }
 801
 802 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 803                          size_t count, loff_t *pos)
 804 {
 805         struct mlx5_core_dev *dev = filp->private_data;
 806         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 807         char lbuf[3];
 808         int err;
 809
 810         if (!dbg->in_msg || !dbg->out_msg)
 811                 return -ENOMEM;
 812
 813         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 814                 return -EFAULT;
 815
 816         lbuf[sizeof(lbuf) - 1] = 0;
 817
 818         if (strcmp(lbuf, "go"))
 819                 return -EINVAL;
 820
 821         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 822
 823         return err ? err : count;
 824 }
 825
 826
 827 static const struct file_operations fops = {
 828         .owner  = THIS_MODULE,
 829         .open   = simple_open,
 830         .write  = dbg_write,
 831 };
 832
 833 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 834 {
 835         struct mlx5_cmd_prot_block *block;
 836         struct mlx5_cmd_mailbox *next;
 837         int copy;
 838
 839         if (!to || !from)
 840                 return -ENOMEM;
 841
 842         copy = min_t(int, size, sizeof(to->first.data));
 843         memcpy(to->first.data, from, copy);
 844         size -= copy;
 845         from += copy;
 846
 847         next = to->next;
 848         while (size) {
 849                 if (!next) {
 850                         /* this is a BUG */
 851                         return -ENOMEM;
 852                 }
 853
 854                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 855                 block = next->buf;
 856                 memcpy(block->data, from, copy);
 857                 from += copy;
 858                 size -= copy;
 859                 next = next->next;
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 866 {
 867         struct mlx5_cmd_prot_block *block;
 868         struct mlx5_cmd_mailbox *next;
 869         int copy;
 870
 871         if (!to || !from)
 872                 return -ENOMEM;
 873
 874         copy = min_t(int, size, sizeof(from->first.data));
 875         memcpy(to, from->first.data, copy);
 876         size -= copy;
 877         to += copy;
 878
 879         next = from->next;
 880         while (size) {
 881                 if (!next) {
 882                         /* this is a BUG */
 883                         return -ENOMEM;
 884                 }
 885
 886                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 887                 block = next->buf;
 888
 889                 memcpy(to, block->data, copy);
 890                 to += copy;
 891                 size -= copy;
 892                 next = next->next;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 899                                               gfp_t flags)
 900 {
 901         struct mlx5_cmd_mailbox *mailbox;
 902
 903         mailbox = kmalloc(sizeof(*mailbox), flags);
 904         if (!mailbox)
 905                 return ERR_PTR(-ENOMEM);
 906
 907         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 908                                       &mailbox->dma);
 909         if (!mailbox->buf) {
 910                 mlx5_core_dbg(dev, "failed allocation\n");
 911                 kfree(mailbox);
 912                 return ERR_PTR(-ENOMEM);
 913         }
 914         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 915         mailbox->next = NULL;
 916
 917         return mailbox;
 918 }
 919
 920 static void free_cmd_box(struct mlx5_core_dev *dev,
 921                          struct mlx5_cmd_mailbox *mailbox)
 922 {
 923         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 924         kfree(mailbox);
 925 }
 926
 927 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 928                                                gfp_t flags, int size)
 929 {
 930         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 931         struct mlx5_cmd_prot_block *block;
 932         struct mlx5_cmd_msg *msg;
 933         int blen;
 934         int err;
 935         int n;
 936         int i;
 937
 938         msg = kzalloc(sizeof(*msg), flags);
 939         if (!msg)
 940                 return ERR_PTR(-ENOMEM);
 941
 942         blen = size - min_t(int, sizeof(msg->first.data), size);
 943         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 944
 945         for (i = 0; i < n; i++) {
 946                 tmp = alloc_cmd_box(dev, flags);
 947                 if (IS_ERR(tmp)) {
 948                         mlx5_core_warn(dev, "failed allocating block\n");
 949                         err = PTR_ERR(tmp);
 950                         goto err_alloc;
 951                 }
 952
 953                 block = tmp->buf;
 954                 tmp->next = head;
 955                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 956                 block->block_num = cpu_to_be32(n - i - 1);
 957                 head = tmp;
 958         }
 959         msg->next = head;
 960         msg->len = size;
 961         return msg;
 962
 963 err_alloc:
 964         while (head) {
 965                 tmp = head->next;
 966                 free_cmd_box(dev, head);
 967                 head = tmp;
 968         }
 969         kfree(msg);
 970
 971         return ERR_PTR(err);
 972 }
 973
 974 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 975                                   struct mlx5_cmd_msg *msg)
 976 {
 977         struct mlx5_cmd_mailbox *head = msg->next;
 978         struct mlx5_cmd_mailbox *next;
 979
 980         while (head) {
 981                 next = head->next;
 982                 free_cmd_box(dev, head);
 983                 head = next;
 984         }
 985         kfree(msg);
 986 }
 987
 988 static ssize_t data_write(struct file *filp, const char __user *buf,
 989                           size_t count, loff_t *pos)
 990 {
 991         struct mlx5_core_dev *dev = filp->private_data;
 992         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 993         void *ptr;
 994         int err;
 995
 996         if (*pos != 0)
 997                 return -EINVAL;
 998
 999         kfree(dbg->in_msg);
1000         dbg->in_msg = NULL;
1001         dbg->inlen = 0;
1002
1003         ptr = kzalloc(count, GFP_KERNEL);
1004         if (!ptr)
1005                 return -ENOMEM;
1006
1007         if (copy_from_user(ptr, buf, count)) {
1008                 err = -EFAULT;
1009                 goto out;
1010         }
1011         dbg->in_msg = ptr;
1012         dbg->inlen = count;
1013
1014         *pos = count;
1015
1016         return count;
1017
1018 out:
1019         kfree(ptr);
1020         return err;
1021 }
1022
1023 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1024                          loff_t *pos)
1025 {
1026         struct mlx5_core_dev *dev = filp->private_data;
1027         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1028         int copy;
1029
1030         if (*pos)
1031                 return 0;
1032
1033         if (!dbg->out_msg)
1034                 return -ENOMEM;
1035
1036         copy = min_t(int, count, dbg->outlen);
1037         if (copy_to_user(buf, dbg->out_msg, copy))
1038                 return -EFAULT;
1039
1040         *pos += copy;
1041
1042         return copy;
1043 }
1044
1045 static const struct file_operations dfops = {
1046         .owner  = THIS_MODULE,
1047         .open   = simple_open,
1048         .write  = data_write,
1049         .read   = data_read,
1050 };
1051
1052 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1053                            loff_t *pos)
1054 {
1055         struct mlx5_core_dev *dev = filp->private_data;
1056         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1057         char outlen[8];
1058         int err;
1059
1060         if (*pos)
1061                 return 0;
1062
1063         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1064         if (err < 0)
1065                 return err;
1066
1067         if (copy_to_user(buf, &outlen, err))
1068                 return -EFAULT;
1069
1070         *pos += err;
1071
1072         return err;
1073 }
1074
1075 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1076                             size_t count, loff_t *pos)
1077 {
1078         struct mlx5_core_dev *dev = filp->private_data;
1079         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1080         char outlen_str[8];
1081         int outlen;
1082         void *ptr;
1083         int err;
1084
1085         if (*pos != 0 || count > 6)
1086                 return -EINVAL;
1087
1088         kfree(dbg->out_msg);
1089         dbg->out_msg = NULL;
1090         dbg->outlen = 0;
1091
1092         if (copy_from_user(outlen_str, buf, count))
1093                 return -EFAULT;
1094
1095         outlen_str[7] = 0;
1096
1097         err = sscanf(outlen_str, "%d", &outlen);
1098         if (err < 0)
1099                 return err;
1100
1101         ptr = kzalloc(outlen, GFP_KERNEL);
1102         if (!ptr)
1103                 return -ENOMEM;
1104
1105         dbg->out_msg = ptr;
1106         dbg->outlen = outlen;
1107
1108         *pos = count;
1109
1110         return count;
1111 }
1112
1113 static const struct file_operations olfops = {
1114         .owner  = THIS_MODULE,
1115         .open   = simple_open,
1116         .write  = outlen_write,
1117         .read   = outlen_read,
1118 };
1119
1120 static void set_wqname(struct mlx5_core_dev *dev)
1121 {
1122         struct mlx5_cmd *cmd = &dev->cmd;
1123
1124         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1125                  dev_name(&dev->pdev->dev));
1126 }
1127
1128 static void clean_debug_files(struct mlx5_core_dev *dev)
1129 {
1130         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1131
1132         if (!mlx5_debugfs_root)
1133                 return;
1134
1135         mlx5_cmdif_debugfs_cleanup(dev);
1136         debugfs_remove_recursive(dbg->dbg_root);
1137 }
1138
1139 static int create_debugfs_files(struct mlx5_core_dev *dev)
1140 {
1141         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1142         int err = -ENOMEM;
1143
1144         if (!mlx5_debugfs_root)
1145                 return 0;
1146
1147         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1148         if (!dbg->dbg_root)
1149                 return err;
1150
1151         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1152                                           dev, &dfops);
1153         if (!dbg->dbg_in)
1154                 goto err_dbg;
1155
1156         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1157                                            dev, &dfops);
1158         if (!dbg->dbg_out)
1159                 goto err_dbg;
1160
1161         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1162                                               dev, &olfops);
1163         if (!dbg->dbg_outlen)
1164                 goto err_dbg;
1165
1166         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1167                                             &dbg->status);
1168         if (!dbg->dbg_status)
1169                 goto err_dbg;
1170
1171         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1172         if (!dbg->dbg_run)
1173                 goto err_dbg;
1174
1175         mlx5_cmdif_debugfs_init(dev);
1176
1177         return 0;
1178
1179 err_dbg:
1180         clean_debug_files(dev);
1181         return err;
1182 }
1183
1184 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1185 {
1186         struct mlx5_cmd *cmd = &dev->cmd;
1187         int i;
1188
1189         for (i = 0; i < cmd->max_reg_cmds; i++)
1190                 down(&cmd->sem);
1191
1192         down(&cmd->pages_sem);
1193
1194         flush_workqueue(cmd->wq);
1195
1196         cmd->mode = CMD_MODE_EVENTS;
1197
1198         up(&cmd->pages_sem);
1199         for (i = 0; i < cmd->max_reg_cmds; i++)
1200                 up(&cmd->sem);
1201 }
1202
1203 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1204 {
1205         struct mlx5_cmd *cmd = &dev->cmd;
1206         int i;
1207
1208         for (i = 0; i < cmd->max_reg_cmds; i++)
1209                 down(&cmd->sem);
1210
1211         down(&cmd->pages_sem);
1212
1213         flush_workqueue(cmd->wq);
1214         cmd->mode = CMD_MODE_POLLING;
1215
1216         up(&cmd->pages_sem);
1217         for (i = 0; i < cmd->max_reg_cmds; i++)
1218                 up(&cmd->sem);
1219 }
1220
1221 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1222 {
1223         unsigned long flags;
1224
1225         if (msg->cache) {
1226                 spin_lock_irqsave(&msg->cache->lock, flags);
1227                 list_add_tail(&msg->list, &msg->cache->head);
1228                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1229         } else {
1230                 mlx5_free_cmd_msg(dev, msg);
1231         }
1232 }
1233
1234 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1235 {
1236         struct mlx5_cmd *cmd = &dev->cmd;
1237         struct mlx5_cmd_work_ent *ent;
1238         mlx5_cmd_cbk_t callback;
1239         void *context;
1240         int err;
1241         int i;
1242         s64 ds;
1243         struct mlx5_cmd_stats *stats;
1244         unsigned long flags;
1245         unsigned long vector;
1246
1247         /* there can be at most 32 command queues */
1248         vector = vec & 0xffffffff;
1249         for (i = 0; i < (1 << cmd->log_sz); i++) {
1250                 if (test_bit(i, &vector)) {
1251                         struct semaphore *sem;
1252
1253                         ent = cmd->ent_arr[i];
1254                         if (ent->page_queue)
1255                                 sem = &cmd->pages_sem;
1256                         else
1257                                 sem = &cmd->sem;
1258                         ent->ts2 = ktime_get_ns();
1259                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1260                         dump_command(dev, ent, 0);
1261                         if (!ent->ret) {
1262                                 if (!cmd->checksum_disabled)
1263                                         ent->ret = verify_signature(ent);
1264                                 else
1265                                         ent->ret = 0;
1266                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1267                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1268                                 else
1269                                         ent->status = ent->lay->status_own >> 1;
1270
1271                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1272                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1273                         }
1274                         free_ent(cmd, ent->idx);
1275
1276                         if (ent->callback) {
1277                                 ds = ent->ts2 - ent->ts1;
1278                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1279                                         stats = &cmd->stats[ent->op];
1280                                         spin_lock_irqsave(&stats->lock, flags);
1281                                         stats->sum += ds;
1282                                         ++stats->n;
1283                                         spin_unlock_irqrestore(&stats->lock, flags);
1284                                 }
1285
1286                                 callback = ent->callback;
1287                                 context = ent->context;
1288                                 err = ent->ret;
1289                                 if (!err)
1290                                         err = mlx5_copy_from_msg(ent->uout,
1291                                                                  ent->out,
1292                                                                  ent->uout_size);
1293
1294                                 mlx5_free_cmd_msg(dev, ent->out);
1295                                 free_msg(dev, ent->in);
1296
1297                                 err = err ? err : ent->status;
1298                                 free_cmd(ent);
1299                                 callback(err, context);
1300                         } else {
1301                                 complete(&ent->done);
1302                         }
1303                         up(sem);
1304                 }
1305         }
1306 }
1307 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1308
1309 static int status_to_err(u8 status)
1310 {
1311         return status ? -1 : 0; /* TBD more meaningful codes */
1312 }
1313
1314 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1315                                       gfp_t gfp)
1316 {
1317         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1318         struct mlx5_cmd *cmd = &dev->cmd;
1319         struct cache_ent *ent = NULL;
1320
1321         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1322                 ent = &cmd->cache.large;
1323         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1324                 ent = &cmd->cache.med;
1325
1326         if (ent) {
1327                 spin_lock_irq(&ent->lock);
1328                 if (!list_empty(&ent->head)) {
1329                         msg = list_entry(ent->head.next, typeof(*msg), list);
1330                         /* For cached lists, we must explicitly state what is
1331                          * the real size
1332                          */
1333                         msg->len = in_size;
1334                         list_del(&msg->list);
1335                 }
1336                 spin_unlock_irq(&ent->lock);
1337         }
1338
1339         if (IS_ERR(msg))
1340                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1341
1342         return msg;
1343 }
1344
1345 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1346 {
1347         return be16_to_cpu(in->opcode);
1348 }
1349
1350 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1351 {
1352         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1353 }
1354
1355 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1356                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1357 {
1358         struct mlx5_cmd_msg *inb;
1359         struct mlx5_cmd_msg *outb;
1360         int pages_queue;
1361         gfp_t gfp;
1362         int err;
1363         u8 status = 0;
1364         u32 drv_synd;
1365
1366         if (pci_channel_offline(dev->pdev) ||
1367             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1368                 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1369                 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1370                 *get_status_ptr(out) = status;
1371                 return err;
1372         }
1373
1374         pages_queue = is_manage_pages(in);
1375         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1376
1377         inb = alloc_msg(dev, in_size, gfp);
1378         if (IS_ERR(inb)) {
1379                 err = PTR_ERR(inb);
1380                 return err;
1381         }
1382
1383         err = mlx5_copy_to_msg(inb, in, in_size);
1384         if (err) {
1385                 mlx5_core_warn(dev, "err %d\n", err);
1386                 goto out_in;
1387         }
1388
1389         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1390         if (IS_ERR(outb)) {
1391                 err = PTR_ERR(outb);
1392                 goto out_in;
1393         }
1394
1395         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1396                               pages_queue, &status);
1397         if (err)
1398                 goto out_out;
1399
1400         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1401         if (status) {
1402                 err = status_to_err(status);
1403                 goto out_out;
1404         }
1405
1406         if (!callback)
1407                 err = mlx5_copy_from_msg(out, outb, out_size);
1408
1409 out_out:
1410         if (!callback)
1411                 mlx5_free_cmd_msg(dev, outb);
1412
1413 out_in:
1414         if (!callback)
1415                 free_msg(dev, inb);
1416         return err;
1417 }
1418
1419 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1420                   int out_size)
1421 {
1422         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1423 }
1424 EXPORT_SYMBOL(mlx5_cmd_exec);
1425
1426 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1427                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1428                      void *context)
1429 {
1430         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1431 }
1432 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1433
1434 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1435 {
1436         struct mlx5_cmd *cmd = &dev->cmd;
1437         struct mlx5_cmd_msg *msg;
1438         struct mlx5_cmd_msg *n;
1439
1440         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1441                 list_del(&msg->list);
1442                 mlx5_free_cmd_msg(dev, msg);
1443         }
1444
1445         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1446                 list_del(&msg->list);
1447                 mlx5_free_cmd_msg(dev, msg);
1448         }
1449 }
1450
1451 static int create_msg_cache(struct mlx5_core_dev *dev)
1452 {
1453         struct mlx5_cmd *cmd = &dev->cmd;
1454         struct mlx5_cmd_msg *msg;
1455         int err;
1456         int i;
1457
1458         spin_lock_init(&cmd->cache.large.lock);
1459         INIT_LIST_HEAD(&cmd->cache.large.head);
1460         spin_lock_init(&cmd->cache.med.lock);
1461         INIT_LIST_HEAD(&cmd->cache.med.head);
1462
1463         for (i = 0; i < NUM_LONG_LISTS; i++) {
1464                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1465                 if (IS_ERR(msg)) {
1466                         err = PTR_ERR(msg);
1467                         goto ex_err;
1468                 }
1469                 msg->cache = &cmd->cache.large;
1470                 list_add_tail(&msg->list, &cmd->cache.large.head);
1471         }
1472
1473         for (i = 0; i < NUM_MED_LISTS; i++) {
1474                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1475                 if (IS_ERR(msg)) {
1476                         err = PTR_ERR(msg);
1477                         goto ex_err;
1478                 }
1479                 msg->cache = &cmd->cache.med;
1480                 list_add_tail(&msg->list, &cmd->cache.med.head);
1481         }
1482
1483         return 0;
1484
1485 ex_err:
1486         destroy_msg_cache(dev);
1487         return err;
1488 }
1489
1490 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1491 {
1492         struct device *ddev = &dev->pdev->dev;
1493
1494         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1495                                                  &cmd->alloc_dma, GFP_KERNEL);
1496         if (!cmd->cmd_alloc_buf)
1497                 return -ENOMEM;
1498
1499         /* make sure it is aligned to 4K */
1500         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1501                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1502                 cmd->dma = cmd->alloc_dma;
1503                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1504                 return 0;
1505         }
1506
1507         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1508                           cmd->alloc_dma);
1509         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1510                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1511                                                  &cmd->alloc_dma, GFP_KERNEL);
1512         if (!cmd->cmd_alloc_buf)
1513                 return -ENOMEM;
1514
1515         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1516         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1517         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1518         return 0;
1519 }
1520
1521 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1522 {
1523         struct device *ddev = &dev->pdev->dev;
1524
1525         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1526                           cmd->alloc_dma);
1527 }
1528
1529 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1530 {
1531         int size = sizeof(struct mlx5_cmd_prot_block);
1532         int align = roundup_pow_of_two(size);
1533         struct mlx5_cmd *cmd = &dev->cmd;
1534         u32 cmd_h, cmd_l;
1535         u16 cmd_if_rev;
1536         int err;
1537         int i;
1538
1539         memset(cmd, 0, sizeof(*cmd));
1540         cmd_if_rev = cmdif_rev(dev);
1541         if (cmd_if_rev != CMD_IF_REV) {
1542                 dev_err(&dev->pdev->dev,
1543                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1544                         CMD_IF_REV, cmd_if_rev);
1545                 return -EINVAL;
1546         }
1547
1548         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1549         if (!cmd->pool)
1550                 return -ENOMEM;
1551
1552         err = alloc_cmd_page(dev, cmd);
1553         if (err)
1554                 goto err_free_pool;
1555
1556         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1557         cmd->log_sz = cmd_l >> 4 & 0xf;
1558         cmd->log_stride = cmd_l & 0xf;
1559         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1560                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1561                         1 << cmd->log_sz);
1562                 err = -EINVAL;
1563                 goto err_free_page;
1564         }
1565
1566         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1567                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1568                 err = -EINVAL;
1569                 goto err_free_page;
1570         }
1571
1572         cmd->checksum_disabled = 1;
1573         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1574         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1575
1576         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1577         if (cmd->cmdif_rev > CMD_IF_REV) {
1578                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1579                         CMD_IF_REV, cmd->cmdif_rev);
1580                 err = -ENOTSUPP;
1581                 goto err_free_page;
1582         }
1583
1584         spin_lock_init(&cmd->alloc_lock);
1585         spin_lock_init(&cmd->token_lock);
1586         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1587                 spin_lock_init(&cmd->stats[i].lock);
1588
1589         sema_init(&cmd->sem, cmd->max_reg_cmds);
1590         sema_init(&cmd->pages_sem, 1);
1591
1592         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1593         cmd_l = (u32)(cmd->dma);
1594         if (cmd_l & 0xfff) {
1595                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1596                 err = -ENOMEM;
1597                 goto err_free_page;
1598         }
1599
1600         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1601         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1602
1603         /* Make sure firmware sees the complete address before we proceed */
1604         wmb();
1605
1606         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1607
1608         cmd->mode = CMD_MODE_POLLING;
1609
1610         err = create_msg_cache(dev);
1611         if (err) {
1612                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1613                 goto err_free_page;
1614         }
1615
1616         set_wqname(dev);
1617         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1618         if (!cmd->wq) {
1619                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1620                 err = -ENOMEM;
1621                 goto err_cache;
1622         }
1623
1624         err = create_debugfs_files(dev);
1625         if (err) {
1626                 err = -ENOMEM;
1627                 goto err_wq;
1628         }
1629
1630         return 0;
1631
1632 err_wq:
1633         destroy_workqueue(cmd->wq);
1634
1635 err_cache:
1636         destroy_msg_cache(dev);
1637
1638 err_free_page:
1639         free_cmd_page(dev, cmd);
1640
1641 err_free_pool:
1642         pci_pool_destroy(cmd->pool);
1643
1644         return err;
1645 }
1646 EXPORT_SYMBOL(mlx5_cmd_init);
1647
1648 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1649 {
1650         struct mlx5_cmd *cmd = &dev->cmd;
1651
1652         clean_debug_files(dev);
1653         destroy_workqueue(cmd->wq);
1654         destroy_msg_cache(dev);
1655         free_cmd_page(dev, cmd);
1656         pci_pool_destroy(cmd->pool);
1657 }
1658 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1659
1660 static const char *cmd_status_str(u8 status)
1661 {
1662         switch (status) {
1663         case MLX5_CMD_STAT_OK:
1664                 return "OK";
1665         case MLX5_CMD_STAT_INT_ERR:
1666                 return "internal error";
1667         case MLX5_CMD_STAT_BAD_OP_ERR:
1668                 return "bad operation";
1669         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1670                 return "bad parameter";
1671         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1672                 return "bad system state";
1673         case MLX5_CMD_STAT_BAD_RES_ERR:
1674                 return "bad resource";
1675         case MLX5_CMD_STAT_RES_BUSY:
1676                 return "resource busy";
1677         case MLX5_CMD_STAT_LIM_ERR:
1678                 return "limits exceeded";
1679         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1680                 return "bad resource state";
1681         case MLX5_CMD_STAT_IX_ERR:
1682                 return "bad index";
1683         case MLX5_CMD_STAT_NO_RES_ERR:
1684                 return "no resources";
1685         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1686                 return "bad input length";
1687         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1688                 return "bad output length";
1689         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1690                 return "bad QP state";
1691         case MLX5_CMD_STAT_BAD_PKT_ERR:
1692                 return "bad packet (discarded)";
1693         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1694                 return "bad size too many outstanding CQEs";
1695         default:
1696                 return "unknown status";
1697         }
1698 }
1699
1700 static int cmd_status_to_err(u8 status)
1701 {
1702         switch (status) {
1703         case MLX5_CMD_STAT_OK:                          return 0;
1704         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1705         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1706         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1707         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1708         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1709         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1710         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1711         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1712         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1713         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1714         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1715         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1716         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1717         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1718         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1719         default:                                        return -EIO;
1720         }
1721 }
1722
1723 /* this will be available till all the commands use set/get macros */
1724 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1725 {
1726         if (!hdr->status)
1727                 return 0;
1728
1729         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1730                 cmd_status_str(hdr->status), hdr->status,
1731                 be32_to_cpu(hdr->syndrome));
1732
1733         return cmd_status_to_err(hdr->status);
1734 }
1735
1736 int mlx5_cmd_status_to_err_v2(void *ptr)
1737 {
1738         u32     syndrome;
1739         u8      status;
1740
1741         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1742         if (!status)
1743                 return 0;
1744
1745         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1746
1747         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1748                 cmd_status_str(status), status, syndrome);
1749
1750         return cmd_status_to_err(status);
1751 }